[Pkg-clamav-commits] [SCM] Debian repository for ClamAV branch, debian/unstable, updated. debian/0.95+dfsg-1-6156-g094ec9b
Török Edvin
edwin at clamav.net
Sun Apr 4 01:20:47 UTC 2010
The following commit has been merged in the debian/unstable branch:
commit f728ee7f097984a3bfe1c93e6b1a0eb45a8d86d0
Author: Török Edvin <edwin at clamav.net>
Date: Mon Feb 15 18:27:45 2010 +0200
Update autogenerated files after LLVM import.
diff --git a/libclamav/c++/ARMGenAsmWriter.inc b/libclamav/c++/ARMGenAsmWriter.inc
index c301a40..c0909e4 100644
--- a/libclamav/c++/ARMGenAsmWriter.inc
+++ b/libclamav/c++/ARMGenAsmWriter.inc
@@ -21,1573 +21,1652 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
0U, // IMPLICIT_DEF
0U, // SUBREG_TO_REG
0U, // COPY_TO_REGCLASS
- 1U, // DEBUG_VALUE
- 134217741U, // ADCSSri
- 134217741U, // ADCSSrr
- 134217741U, // ADCSSrs
- 269516819U, // ADCri
- 269549587U, // ADCrr
- 404750355U, // ADCrs
- 271679511U, // ADDSri
- 271679511U, // ADDSrr
- 405897239U, // ADDSrs
- 269516828U, // ADDri
- 269549596U, // ADDrr
- 404750364U, // ADDrs
- 138412064U, // ADJCALLSTACKDOWN
- 138412084U, // ADJCALLSTACKUP
- 269516870U, // ANDri
- 269549638U, // ANDrr
- 404750406U, // ANDrs
- 542113866U, // ATOMIC_CMP_SWAP_I16
- 543162442U, // ATOMIC_CMP_SWAP_I32
- 544211018U, // ATOMIC_CMP_SWAP_I8
- 545259594U, // ATOMIC_LOAD_ADD_I16
- 546308170U, // ATOMIC_LOAD_ADD_I32
- 547356746U, // ATOMIC_LOAD_ADD_I8
- 548405322U, // ATOMIC_LOAD_AND_I16
- 549453898U, // ATOMIC_LOAD_AND_I32
- 550502474U, // ATOMIC_LOAD_AND_I8
- 551551050U, // ATOMIC_LOAD_NAND_I16
- 552599626U, // ATOMIC_LOAD_NAND_I32
- 553648202U, // ATOMIC_LOAD_NAND_I8
- 554696778U, // ATOMIC_LOAD_OR_I16
- 555745354U, // ATOMIC_LOAD_OR_I32
- 556793930U, // ATOMIC_LOAD_OR_I8
- 557842506U, // ATOMIC_LOAD_SUB_I16
- 558891082U, // ATOMIC_LOAD_SUB_I32
- 559939658U, // ATOMIC_LOAD_SUB_I8
- 560988234U, // ATOMIC_LOAD_XOR_I16
- 562036810U, // ATOMIC_LOAD_XOR_I32
- 563085386U, // ATOMIC_LOAD_XOR_I8
- 564133962U, // ATOMIC_SWAP_I16
- 565182538U, // ATOMIC_SWAP_I32
- 566231114U, // ATOMIC_SWAP_I8
- 138412107U, // B
- 271679566U, // BFC
- 269516882U, // BICri
- 269549650U, // BICrr
- 404750418U, // BICrs
- 671088726U, // BL
- 138412122U, // BLX
- 138412122U, // BLXr9
- 808583263U, // BL_pred
- 671088726U, // BLr9
- 808583263U, // BLr9_pred
- 138412130U, // BRIND
- 134217830U, // BR_JTadd
- 939524207U, // BR_JTm
- 164626552U, // BR_JTr
- 138412161U, // BX
- 1105199249U, // BX_RET
- 138412161U, // BXr9
- 808550548U, // Bcc
- 1211203734U, // CLZ
- 1211203738U, // CMNzri
- 1211203738U, // CMNzrr
- 1345421466U, // CMNzrs
- 1211203742U, // CMPri
- 1211203742U, // CMPrr
- 1345421470U, // CMPrs
- 1211203742U, // CMPzri
- 1211203742U, // CMPzrr
- 1345421470U, // CMPzrs
- 1476395082U, // CONSTPOOL_ENTRY
- 269516962U, // EORri
- 269549730U, // EORrr
- 404750498U, // EORrs
- 1240629414U, // FCONSTD
- 1241677990U, // FCONSTS
- 1108345003U, // FMSTAT
- 169869488U, // Int_MemBarrierV6
- 189U, // Int_MemBarrierV7
- 170918064U, // Int_SyncBarrierV6
- 193U, // Int_SyncBarrierV7
- 171966661U, // Int_eh_sjlj_setjmp
- 1613955279U, // LDM
- 1613955279U, // LDM_RET
- 1345421523U, // LDR
- 1345421527U, // LDRB
- 405897431U, // LDRB_POST
- 405897431U, // LDRB_PRE
- 405897436U, // LDRD
- 1211203809U, // LDREX
- 1211203815U, // LDREXB
- 271679726U, // LDREXD
- 1211203829U, // LDREXH
- 1345421564U, // LDRH
- 405897468U, // LDRH_POST
- 405897468U, // LDRH_PRE
- 1345421569U, // LDRSB
- 405897473U, // LDRSB_POST
- 405897473U, // LDRSB_PRE
- 1345421575U, // LDRSH
- 405897479U, // LDRSH_POST
- 405897479U, // LDRSH_PRE
- 405897427U, // LDR_POST
- 405897427U, // LDR_PRE
- 1345421523U, // LDRcp
- 1783628045U, // LEApcrel
- 1784676621U, // LEApcrelJT
- 1383072019U, // MLA
- 1345421591U, // MLS
- 271679771U, // MOVCCi
- 271679771U, // MOVCCr
- 405897499U, // MOVCCs
- 271679775U, // MOVTi16
- 1250132251U, // MOVi
- 1211203876U, // MOVi16
- 1211203867U, // MOVi2pieces
- 1211203876U, // MOVi32imm
- 1249902875U, // MOVr
- 1249902875U, // MOVrx
- 1383334171U, // MOVs
- 1211203881U, // MOVsra_flag
- 1211203881U, // MOVsrl_flag
- 269549870U, // MUL
- 1250132274U, // MVNi
- 1249902898U, // MVNr
- 1383334194U, // MVNs
- 269517110U, // ORRri
- 269549878U, // ORRrr
- 404750646U, // ORRrs
- 1922040122U, // PICADD
- 2057306426U, // PICLDR
- 2058355002U, // PICLDRB
- 2059403578U, // PICLDRH
- 2060452154U, // PICLDRSB
- 2061500730U, // PICLDRSH
- 2062549306U, // PICSTR
- 2063597882U, // PICSTRB
- 2064646458U, // PICSTRH
- 1345421628U, // PKHBT
- 1345421634U, // PKHTB
- 1211203912U, // RBIT
- 1211203917U, // REV
- 1211203921U, // REV16
- 1211203927U, // REVSH
- 271679837U, // RSBSri
- 405897565U, // RSBSrs
- 269517154U, // RSBri
- 404750690U, // RSBrs
- 134218086U, // RSCSri
- 134218086U, // RSCSrs
- 269517164U, // RSCri
- 404750700U, // RSCrs
- 134218096U, // SBCSSri
- 134218096U, // SBCSSrr
- 134218096U, // SBCSSrs
- 269517174U, // SBCri
- 269549942U, // SBCrr
- 404750710U, // SBCrs
- 1345421690U, // SBFX
- 1345421695U, // SMLABB
- 1345421702U, // SMLABT
- 1383072141U, // SMLAL
- 1345421715U, // SMLATB
- 1345421722U, // SMLATT
- 1345421729U, // SMLAWB
- 1345421736U, // SMLAWT
- 1345421743U, // SMMLA
- 1345421749U, // SMMLS
- 271679931U, // SMMUL
- 271679937U, // SMULBB
- 271679944U, // SMULBT
- 1383072207U, // SMULL
- 271679957U, // SMULTB
- 271679964U, // SMULTT
- 271679971U, // SMULWB
- 271679978U, // SMULWT
- 1613955569U, // STM
- 1345421813U, // STR
- 1345421817U, // STRB
- 405799417U, // STRB_POST
- 405799417U, // STRB_PRE
- 405897726U, // STRD
- 271680003U, // STREX
- 271680009U, // STREXB
- 1345421840U, // STREXD
- 271680023U, // STREXH
- 1345421854U, // STRH
- 405799454U, // STRH_POST
- 405799454U, // STRH_PRE
- 405799413U, // STR_POST
- 405799413U, // STR_PRE
- 271680035U, // SUBSri
- 271680035U, // SUBSrr
- 405897763U, // SUBSrs
- 269517352U, // SUBri
- 269550120U, // SUBrr
- 404750888U, // SUBrs
- 271680044U, // SXTABrr
- 1345421868U, // SXTABrr_rot
- 271680050U, // SXTAHrr
- 1345421874U, // SXTAHrr_rot
- 1211204152U, // SXTBr
- 271680056U, // SXTBr_rot
- 1211204157U, // SXTHr
- 271680061U, // SXTHr_rot
- 1211204162U, // TEQri
- 1211204162U, // TEQrr
- 1345421890U, // TEQrs
- 582U, // TPsoft
- 1211204185U, // TSTri
- 1211204185U, // TSTrr
- 1345421913U, // TSTrs
- 1345421917U, // UBFX
- 1345421922U, // UMAAL
- 1383072360U, // UMLAL
- 1383072366U, // UMULL
- 271680116U, // UXTABrr
- 1345421940U, // UXTABrr_rot
- 271680122U, // UXTAHrr
- 1345421946U, // UXTAHrr_rot
- 1211204224U, // UXTB16r
- 271680128U, // UXTB16r_rot
- 1211204231U, // UXTBr
- 271680135U, // UXTBr_rot
- 1211204236U, // UXTHr
- 271680140U, // UXTHr_rot
- 1394672273U, // VABALsv2i64
- 1395720849U, // VABALsv4i32
- 1396769425U, // VABALsv8i16
- 1397818001U, // VABALuv2i64
- 1398866577U, // VABALuv4i32
- 1399915153U, // VABALuv8i16
- 1396769431U, // VABAsv16i8
- 1394672279U, // VABAsv2i32
- 1395720855U, // VABAsv4i16
- 1394672279U, // VABAsv4i32
- 1395720855U, // VABAsv8i16
- 1396769431U, // VABAsv8i8
- 1399915159U, // VABAuv16i8
- 1397818007U, // VABAuv2i32
- 1398866583U, // VABAuv4i16
- 1397818007U, // VABAuv4i32
- 1398866583U, // VABAuv8i16
- 1399915159U, // VABAuv8i8
- 320864924U, // VABDLsv2i64
- 321913500U, // VABDLsv4i32
- 322962076U, // VABDLsv8i16
- 324010652U, // VABDLuv2i64
- 325059228U, // VABDLuv4i32
- 326107804U, // VABDLuv8i16
- 302154402U, // VABDfd
- 302154402U, // VABDfq
- 322962082U, // VABDsv16i8
- 320864930U, // VABDsv2i32
- 321913506U, // VABDsv4i16
- 320864930U, // VABDsv4i32
- 321913506U, // VABDsv8i16
- 322962082U, // VABDsv8i8
- 326107810U, // VABDuv16i8
- 324010658U, // VABDuv2i32
- 325059234U, // VABDuv4i16
- 324010658U, // VABDuv4i32
- 325059234U, // VABDuv8i16
- 326107810U, // VABDuv8i8
- 1240629927U, // VABSD
- 1241678503U, // VABSS
- 1241678503U, // VABSfd
- 1241678503U, // VABSfd_sfp
- 1241678503U, // VABSfq
- 1262486183U, // VABSv16i8
- 1260389031U, // VABSv2i32
- 1261437607U, // VABSv4i16
- 1260389031U, // VABSv4i32
- 1261437607U, // VABSv8i16
- 1262486183U, // VABSv8i8
- 302154412U, // VACGEd
- 302154412U, // VACGEq
- 302154418U, // VACGTd
- 302154418U, // VACGTq
- 301105848U, // VADDD
- 327156413U, // VADDHNv2i32
- 328204989U, // VADDHNv4i16
- 329253565U, // VADDHNv8i8
- 320864964U, // VADDLsv2i64
- 321913540U, // VADDLsv4i32
- 322962116U, // VADDLsv8i16
- 324010692U, // VADDLuv2i64
- 325059268U, // VADDLuv4i32
- 326107844U, // VADDLuv8i16
- 302154424U, // VADDS
- 320864970U, // VADDWsv2i64
- 321913546U, // VADDWsv4i32
- 322962122U, // VADDWsv8i16
- 324010698U, // VADDWuv2i64
- 325059274U, // VADDWuv4i32
- 326107850U, // VADDWuv8i16
- 302154424U, // VADDfd
- 302154424U, // VADDfd_sfp
- 302154424U, // VADDfq
- 330302136U, // VADDv16i8
- 327156408U, // VADDv1i64
- 328204984U, // VADDv2i32
- 327156408U, // VADDv2i64
- 329253560U, // VADDv4i16
- 328204984U, // VADDv4i32
- 329253560U, // VADDv8i16
- 330302136U, // VADDv8i8
- 271680208U, // VANDd
- 271680208U, // VANDq
- 271680213U, // VBICd
- 271680213U, // VBICq
- 1345422042U, // VBSLd
- 1345422042U, // VBSLq
- 302154463U, // VCEQfd
- 302154463U, // VCEQfq
- 330302175U, // VCEQv16i8
- 328205023U, // VCEQv2i32
- 329253599U, // VCEQv4i16
- 328205023U, // VCEQv4i32
- 329253599U, // VCEQv8i16
- 330302175U, // VCEQv8i8
- 302154468U, // VCGEfd
- 302154468U, // VCGEfq
- 322962148U, // VCGEsv16i8
- 320864996U, // VCGEsv2i32
- 321913572U, // VCGEsv4i16
- 320864996U, // VCGEsv4i32
- 321913572U, // VCGEsv8i16
- 322962148U, // VCGEsv8i8
- 326107876U, // VCGEuv16i8
- 324010724U, // VCGEuv2i32
- 325059300U, // VCGEuv4i16
- 324010724U, // VCGEuv4i32
- 325059300U, // VCGEuv8i16
- 326107876U, // VCGEuv8i8
- 302154473U, // VCGTfd
- 302154473U, // VCGTfq
- 322962153U, // VCGTsv16i8
- 320865001U, // VCGTsv2i32
- 321913577U, // VCGTsv4i16
- 320865001U, // VCGTsv4i32
- 321913577U, // VCGTsv8i16
- 322962153U, // VCGTsv8i8
- 326107881U, // VCGTuv16i8
- 324010729U, // VCGTuv2i32
- 325059305U, // VCGTuv4i16
- 324010729U, // VCGTuv4i32
- 325059305U, // VCGTuv8i16
- 326107881U, // VCGTuv8i8
- 1262486254U, // VCLSv16i8
- 1260389102U, // VCLSv2i32
- 1261437678U, // VCLSv4i16
- 1260389102U, // VCLSv4i32
- 1261437678U, // VCLSv8i16
- 1262486254U, // VCLSv8i8
- 1269826291U, // VCLZv16i8
- 1267729139U, // VCLZv2i32
- 1268777715U, // VCLZv4i16
- 1267729139U, // VCLZv4i32
- 1268777715U, // VCLZv8i16
- 1269826291U, // VCLZv8i8
- 1240630008U, // VCMPED
- 1241678584U, // VCMPES
- 838107896U, // VCMPEZD
- 839156472U, // VCMPEZS
- 1270973182U, // VCNTd
- 1270973182U, // VCNTq
- 1271923459U, // VCVTDS
- 1272972035U, // VCVTSD
- 1274348291U, // VCVTf2sd
- 1274348291U, // VCVTf2sd_sfp
- 1274348291U, // VCVTf2sq
- 1275396867U, // VCVTf2ud
- 1275396867U, // VCVTf2ud_sfp
- 1275396867U, // VCVTf2uq
- 334660355U, // VCVTf2xsd
- 334660355U, // VCVTf2xsq
- 335708931U, // VCVTf2xud
- 335708931U, // VCVTf2xuq
- 1276445443U, // VCVTs2fd
- 1276445443U, // VCVTs2fd_sfp
- 1276445443U, // VCVTs2fq
- 1277494019U, // VCVTu2fd
- 1277494019U, // VCVTu2fd_sfp
- 1277494019U, // VCVTu2fq
- 336757507U, // VCVTxs2fd
- 336757507U, // VCVTxs2fq
- 337806083U, // VCVTxu2fd
- 337806083U, // VCVTxu2fq
- 301105928U, // VDIVD
- 302154504U, // VDIVS
- 1278313229U, // VDUP16d
- 1278313229U, // VDUP16q
- 1279361805U, // VDUP32d
- 1279361805U, // VDUP32q
- 1270973197U, // VDUP8d
- 1270973197U, // VDUP8q
- 338789133U, // VDUPLN16d
- 338789133U, // VDUPLN16q
- 339837709U, // VDUPLN32d
- 339837709U, // VDUPLN32q
- 331449101U, // VDUPLN8d
- 331449101U, // VDUPLN8q
- 339837709U, // VDUPLNfd
- 339837709U, // VDUPLNfq
- 1279361805U, // VDUPfd
- 1279361805U, // VDUPfdf
- 1279361805U, // VDUPfq
- 1279361805U, // VDUPfqf
- 271680274U, // VEORd
- 271680274U, // VEORq
- 1412530967U, // VEXTd16
- 1413579543U, // VEXTd32
- 1405190935U, // VEXTd8
- 1413579543U, // VEXTdf
- 1412530967U, // VEXTq16
- 1413579543U, // VEXTq32
- 1405190935U, // VEXTq8
- 1413579543U, // VEXTqf
- 339837094U, // VGETLNi32
- 321912998U, // VGETLNs16
- 322961574U, // VGETLNs8
- 325058726U, // VGETLNu16
- 326107302U, // VGETLNu8
- 322962204U, // VHADDsv16i8
- 320865052U, // VHADDsv2i32
- 321913628U, // VHADDsv4i16
- 320865052U, // VHADDsv4i32
- 321913628U, // VHADDsv8i16
- 322962204U, // VHADDsv8i8
- 326107932U, // VHADDuv16i8
- 324010780U, // VHADDuv2i32
- 325059356U, // VHADDuv4i16
- 324010780U, // VHADDuv4i32
- 325059356U, // VHADDuv8i16
- 326107932U, // VHADDuv8i8
- 322962210U, // VHSUBsv16i8
- 320865058U, // VHSUBsv2i32
- 321913634U, // VHSUBsv4i16
- 320865058U, // VHSUBsv4i32
- 321913634U, // VHSUBsv8i16
- 322962210U, // VHSUBsv8i8
- 326107938U, // VHSUBuv16i8
- 324010786U, // VHSUBuv2i32
- 325059362U, // VHSUBuv4i16
- 324010786U, // VHSUBuv4i32
- 325059362U, // VHSUBuv8i16
- 326107938U, // VHSUBuv8i8
- 475104040U, // VLD1d16
- 476152616U, // VLD1d32
- 477201192U, // VLD1d64
- 478249768U, // VLD1d8
- 476152616U, // VLD1df
- 473269032U, // VLD1q16
- 474317608U, // VLD1q32
- 479560488U, // VLD1q64
- 465929000U, // VLD1q8
- 474317608U, // VLD1qf
- 2219934509U, // VLD2LNd16
- 2220983085U, // VLD2LNd32
- 2223080237U, // VLD2LNd8
- 2219934509U, // VLD2LNq16a
- 2219934509U, // VLD2LNq16b
- 2220983085U, // VLD2LNq32a
- 2220983085U, // VLD2LNq32b
- 2354152237U, // VLD2d16
- 2355200813U, // VLD2d32
- 2356249384U, // VLD2d64
- 2357297965U, // VLD2d8
- 2488369965U, // VLD2q16
- 2489418541U, // VLD2q32
- 2491515693U, // VLD2q8
- 2622587698U, // VLD3LNd16
- 2623636274U, // VLD3LNd32
- 2625733426U, // VLD3LNd8
- 2622587698U, // VLD3LNq16a
- 2622587698U, // VLD3LNq16b
- 2623636274U, // VLD3LNq32a
- 2623636274U, // VLD3LNq32b
- 2756805426U, // VLD3d16
- 2757854002U, // VLD3d32
- 2758902568U, // VLD3d64
- 2759951154U, // VLD3d8
- 2488369970U, // VLD3q16a
- 2488369970U, // VLD3q16b
- 2489418546U, // VLD3q32a
- 2489418546U, // VLD3q32b
- 2491515698U, // VLD3q8a
- 2491515698U, // VLD3q8b
- 2891023159U, // VLD4LNd16
- 2892071735U, // VLD4LNd32
- 2894168887U, // VLD4LNd8
- 2891023159U, // VLD4LNq16a
- 2891023159U, // VLD4LNq16b
- 2892071735U, // VLD4LNq32a
- 2892071735U, // VLD4LNq32b
- 2488369975U, // VLD4d16
- 2489418551U, // VLD4d32
- 2490467112U, // VLD4d64
- 2491515703U, // VLD4d8
- 2219934519U, // VLD4q16a
- 2219934519U, // VLD4q16b
- 2220983095U, // VLD4q32a
- 2220983095U, // VLD4q32b
- 2223080247U, // VLD4q8a
- 2223080247U, // VLD4q8b
- 2952790844U, // VLDMD
- 2952790844U, // VLDMS
- 345080641U, // VLDRD
- 271975238U, // VLDRQ
- 339837761U, // VLDRS
- 302154573U, // VMAXfd
- 302154573U, // VMAXfq
- 322962253U, // VMAXsv16i8
- 320865101U, // VMAXsv2i32
- 321913677U, // VMAXsv4i16
- 320865101U, // VMAXsv4i32
- 321913677U, // VMAXsv8i16
- 322962253U, // VMAXsv8i8
- 326107981U, // VMAXuv16i8
- 324010829U, // VMAXuv2i32
- 325059405U, // VMAXuv4i16
- 324010829U, // VMAXuv4i32
- 325059405U, // VMAXuv8i16
- 326107981U, // VMAXuv8i8
- 302154578U, // VMINfd
- 302154578U, // VMINfq
- 322962258U, // VMINsv16i8
- 320865106U, // VMINsv2i32
- 321913682U, // VMINsv4i16
- 320865106U, // VMINsv4i32
- 321913682U, // VMINsv8i16
- 322962258U, // VMINsv8i8
- 326107986U, // VMINuv16i8
- 324010834U, // VMINuv2i32
- 325059410U, // VMINuv4i16
- 324010834U, // VMINuv4i32
- 325059410U, // VMINuv8i16
- 326107986U, // VMINuv8i8
- 1374847831U, // VMLAD
- 455148380U, // VMLALslsv2i32
- 456196956U, // VMLALslsv4i16
- 458294108U, // VMLALsluv2i32
- 459342684U, // VMLALsluv4i16
- 1394672476U, // VMLALsv2i64
- 1395721052U, // VMLALsv4i32
- 1396769628U, // VMLALsv8i16
- 1397818204U, // VMLALuv2i64
- 1398866780U, // VMLALuv4i32
- 1399915356U, // VMLALuv8i16
- 1375896407U, // VMLAS
- 1375896407U, // VMLAfd
- 1375896407U, // VMLAfq
- 436372311U, // VMLAslfd
- 436372311U, // VMLAslfq
- 462488407U, // VMLAslv2i32
- 463536983U, // VMLAslv4i16
- 462488407U, // VMLAslv4i32
- 463536983U, // VMLAslv8i16
- 1404109655U, // VMLAv16i8
- 1402012503U, // VMLAv2i32
- 1403061079U, // VMLAv4i16
- 1402012503U, // VMLAv4i32
- 1403061079U, // VMLAv8i16
- 1404109655U, // VMLAv8i8
- 1374847842U, // VMLSD
- 455148391U, // VMLSLslsv2i32
- 456196967U, // VMLSLslsv4i16
- 458294119U, // VMLSLsluv2i32
- 459342695U, // VMLSLsluv4i16
- 1394672487U, // VMLSLsv2i64
- 1395721063U, // VMLSLsv4i32
- 1396769639U, // VMLSLsv8i16
- 1397818215U, // VMLSLuv2i64
- 1398866791U, // VMLSLuv4i32
- 1399915367U, // VMLSLuv8i16
- 1375896418U, // VMLSS
- 1375896418U, // VMLSfd
- 1375896418U, // VMLSfq
- 436372322U, // VMLSslfd
- 436372322U, // VMLSslfq
- 462488418U, // VMLSslv2i32
- 463536994U, // VMLSslv4i16
- 462488418U, // VMLSslv4i32
- 463536994U, // VMLSslv8i16
- 1404109666U, // VMLSv16i8
- 1402012514U, // VMLSv2i32
- 1403061090U, // VMLSv4i16
- 1402012514U, // VMLSv4i32
- 1403061090U, // VMLSv8i16
- 1404109666U, // VMLSv8i8
- 1240629414U, // VMOVD
- 271679654U, // VMOVDRR
- 301105318U, // VMOVDcc
- 1211203750U, // VMOVDneon
- 1260389229U, // VMOVLsv2i64
- 1261437805U, // VMOVLsv4i32
- 1262486381U, // VMOVLsv8i16
- 1263534957U, // VMOVLuv2i64
- 1264583533U, // VMOVLuv4i32
- 1265632109U, // VMOVLuv8i16
- 1266680691U, // VMOVNv2i32
- 1267729267U, // VMOVNv4i16
- 1268777843U, // VMOVNv8i8
- 1211203750U, // VMOVQ
- 271679654U, // VMOVRRD
- 1211203750U, // VMOVRS
- 1241677990U, // VMOVS
- 1211203750U, // VMOVSR
- 302153894U, // VMOVScc
- 1270251686U, // VMOVv16i8
- 1267138726U, // VMOVv1i64
- 1268220070U, // VMOVv2i32
- 1267138726U, // VMOVv2i64
- 1269301414U, // VMOVv4i16
- 1268220070U, // VMOVv4i32
- 1269301414U, // VMOVv8i16
- 1270251686U, // VMOVv8i8
- 301106041U, // VMULD
- 346030974U, // VMULLp
- 1394606974U, // VMULLslsv2i32
- 1395655550U, // VMULLslsv4i16
- 1397752702U, // VMULLsluv2i32
- 1398801278U, // VMULLsluv4i16
- 320865150U, // VMULLsv2i64
- 321913726U, // VMULLsv4i32
- 322962302U, // VMULLsv8i16
- 324010878U, // VMULLuv2i64
- 325059454U, // VMULLuv4i32
- 326108030U, // VMULLuv8i16
- 302154617U, // VMULS
- 302154617U, // VMULfd
- 302154617U, // VMULfd_sfp
- 302154617U, // VMULfq
- 346030969U, // VMULpd
- 346030969U, // VMULpq
- 1375896441U, // VMULslfd
- 1375896441U, // VMULslfq
- 1401947001U, // VMULslv2i32
- 1402995577U, // VMULslv4i16
- 1401947001U, // VMULslv4i32
- 1402995577U, // VMULslv8i16
- 330302329U, // VMULv16i8
- 328205177U, // VMULv2i32
- 329253753U, // VMULv4i16
- 328205177U, // VMULv4i32
- 329253753U, // VMULv8i16
- 330302329U, // VMULv8i8
- 1211204484U, // VMVNd
- 1211204484U, // VMVNq
- 1240630153U, // VNEGD
- 301106057U, // VNEGDcc
- 1241678729U, // VNEGS
- 302154633U, // VNEGScc
- 1241678729U, // VNEGf32d
- 1241678729U, // VNEGf32d_sfp
- 1241678729U, // VNEGf32q
- 1261437833U, // VNEGs16d
- 1261437833U, // VNEGs16q
- 1260389257U, // VNEGs32d
- 1260389257U, // VNEGs32q
- 1262486409U, // VNEGs8d
- 1262486409U, // VNEGs8q
- 1374847886U, // VNMLAD
- 1375896462U, // VNMLAS
- 1374847892U, // VNMLSD
- 1375896468U, // VNMLSS
- 301106074U, // VNMULD
- 302154650U, // VNMULS
- 271680416U, // VORNd
- 271680416U, // VORNq
- 271680421U, // VORRd
- 271680421U, // VORRq
- 323027882U, // VPADALsv16i8
- 320930730U, // VPADALsv2i32
- 321979306U, // VPADALsv4i16
- 320930730U, // VPADALsv4i32
- 321979306U, // VPADALsv8i16
- 323027882U, // VPADALsv8i8
- 326173610U, // VPADALuv16i8
- 324076458U, // VPADALuv2i32
- 325125034U, // VPADALuv4i16
- 324076458U, // VPADALuv4i32
- 325125034U, // VPADALuv8i16
- 326173610U, // VPADALuv8i8
- 1262486449U, // VPADDLsv16i8
- 1260389297U, // VPADDLsv2i32
- 1261437873U, // VPADDLsv4i16
- 1260389297U, // VPADDLsv4i32
- 1261437873U, // VPADDLsv8i16
- 1262486449U, // VPADDLsv8i8
- 1265632177U, // VPADDLuv16i8
- 1263535025U, // VPADDLuv2i32
- 1264583601U, // VPADDLuv4i16
- 1263535025U, // VPADDLuv4i32
- 1264583601U, // VPADDLuv8i16
- 1265632177U, // VPADDLuv8i8
- 302154680U, // VPADDf
- 329253816U, // VPADDi16
- 328205240U, // VPADDi32
- 330302392U, // VPADDi8
- 302154686U, // VPMAXf
- 321913790U, // VPMAXs16
- 320865214U, // VPMAXs32
- 322962366U, // VPMAXs8
- 325059518U, // VPMAXu16
- 324010942U, // VPMAXu32
- 326108094U, // VPMAXu8
- 302154692U, // VPMINf
- 321913796U, // VPMINs16
- 320865220U, // VPMINs32
- 322962372U, // VPMINs8
- 325059524U, // VPMINu16
- 324010948U, // VPMINu32
- 326108100U, // VPMINu8
- 1262486474U, // VQABSv16i8
- 1260389322U, // VQABSv2i32
- 1261437898U, // VQABSv4i16
- 1260389322U, // VQABSv4i32
- 1261437898U, // VQABSv8i16
- 1262486474U, // VQABSv8i8
- 322962384U, // VQADDsv16i8
- 347079632U, // VQADDsv1i64
- 320865232U, // VQADDsv2i32
- 347079632U, // VQADDsv2i64
- 321913808U, // VQADDsv4i16
- 320865232U, // VQADDsv4i32
- 321913808U, // VQADDsv8i16
- 322962384U, // VQADDsv8i8
- 326108112U, // VQADDuv16i8
- 348128208U, // VQADDuv1i64
- 324010960U, // VQADDuv2i32
- 348128208U, // VQADDuv2i64
- 325059536U, // VQADDuv4i16
- 324010960U, // VQADDuv4i32
- 325059536U, // VQADDuv8i16
- 326108112U, // VQADDuv8i8
- 455148502U, // VQDMLALslv2i32
- 456197078U, // VQDMLALslv4i16
- 1394672598U, // VQDMLALv2i64
- 1395721174U, // VQDMLALv4i32
- 455148510U, // VQDMLSLslv2i32
- 456197086U, // VQDMLSLslv4i16
- 1394672606U, // VQDMLSLv2i64
- 1395721182U, // VQDMLSLv4i32
- 1394607078U, // VQDMULHslv2i32
- 1395655654U, // VQDMULHslv4i16
- 1394607078U, // VQDMULHslv4i32
- 1395655654U, // VQDMULHslv8i16
- 320865254U, // VQDMULHv2i32
- 321913830U, // VQDMULHv4i16
- 320865254U, // VQDMULHv4i32
- 321913830U, // VQDMULHv8i16
- 1394607086U, // VQDMULLslv2i32
- 1395655662U, // VQDMULLslv4i16
- 320865262U, // VQDMULLv2i64
- 321913838U, // VQDMULLv4i32
- 1286603766U, // VQMOVNsuv2i32
- 1260389366U, // VQMOVNsuv4i16
- 1261437942U, // VQMOVNsuv8i8
- 1286603774U, // VQMOVNsv2i32
- 1260389374U, // VQMOVNsv4i16
- 1261437950U, // VQMOVNsv8i8
- 1287652350U, // VQMOVNuv2i32
- 1263535102U, // VQMOVNuv4i16
- 1264583678U, // VQMOVNuv8i8
- 1262486533U, // VQNEGv16i8
- 1260389381U, // VQNEGv2i32
- 1261437957U, // VQNEGv4i16
- 1260389381U, // VQNEGv4i32
- 1261437957U, // VQNEGv8i16
- 1262486533U, // VQNEGv8i8
- 1394607115U, // VQRDMULHslv2i32
- 1395655691U, // VQRDMULHslv4i16
- 1394607115U, // VQRDMULHslv4i32
- 1395655691U, // VQRDMULHslv8i16
- 320865291U, // VQRDMULHv2i32
- 321913867U, // VQRDMULHv4i16
- 320865291U, // VQRDMULHv4i32
- 321913867U, // VQRDMULHv8i16
- 322962452U, // VQRSHLsv16i8
- 347079700U, // VQRSHLsv1i64
- 320865300U, // VQRSHLsv2i32
- 347079700U, // VQRSHLsv2i64
- 321913876U, // VQRSHLsv4i16
- 320865300U, // VQRSHLsv4i32
- 321913876U, // VQRSHLsv8i16
- 322962452U, // VQRSHLsv8i8
- 326108180U, // VQRSHLuv16i8
- 348128276U, // VQRSHLuv1i64
- 324011028U, // VQRSHLuv2i32
- 348128276U, // VQRSHLuv2i64
- 325059604U, // VQRSHLuv4i16
- 324011028U, // VQRSHLuv4i32
- 325059604U, // VQRSHLuv8i16
- 326108180U, // VQRSHLuv8i8
- 347079707U, // VQRSHRNsv2i32
- 320865307U, // VQRSHRNsv4i16
- 321913883U, // VQRSHRNsv8i8
- 348128283U, // VQRSHRNuv2i32
- 324011035U, // VQRSHRNuv4i16
- 325059611U, // VQRSHRNuv8i8
- 347079715U, // VQRSHRUNv2i32
- 320865315U, // VQRSHRUNv4i16
- 321913891U, // VQRSHRUNv8i8
- 322962476U, // VQSHLsiv16i8
- 347079724U, // VQSHLsiv1i64
- 320865324U, // VQSHLsiv2i32
- 347079724U, // VQSHLsiv2i64
- 321913900U, // VQSHLsiv4i16
- 320865324U, // VQSHLsiv4i32
- 321913900U, // VQSHLsiv8i16
- 322962476U, // VQSHLsiv8i8
- 322962482U, // VQSHLsuv16i8
- 347079730U, // VQSHLsuv1i64
- 320865330U, // VQSHLsuv2i32
- 347079730U, // VQSHLsuv2i64
- 321913906U, // VQSHLsuv4i16
- 320865330U, // VQSHLsuv4i32
- 321913906U, // VQSHLsuv8i16
- 322962482U, // VQSHLsuv8i8
- 322962476U, // VQSHLsv16i8
- 347079724U, // VQSHLsv1i64
- 320865324U, // VQSHLsv2i32
- 347079724U, // VQSHLsv2i64
- 321913900U, // VQSHLsv4i16
- 320865324U, // VQSHLsv4i32
- 321913900U, // VQSHLsv8i16
- 322962476U, // VQSHLsv8i8
- 326108204U, // VQSHLuiv16i8
- 348128300U, // VQSHLuiv1i64
- 324011052U, // VQSHLuiv2i32
- 348128300U, // VQSHLuiv2i64
- 325059628U, // VQSHLuiv4i16
- 324011052U, // VQSHLuiv4i32
- 325059628U, // VQSHLuiv8i16
- 326108204U, // VQSHLuiv8i8
- 326108204U, // VQSHLuv16i8
- 348128300U, // VQSHLuv1i64
- 324011052U, // VQSHLuv2i32
- 348128300U, // VQSHLuv2i64
- 325059628U, // VQSHLuv4i16
- 324011052U, // VQSHLuv4i32
- 325059628U, // VQSHLuv8i16
- 326108204U, // VQSHLuv8i8
- 347079737U, // VQSHRNsv2i32
- 320865337U, // VQSHRNsv4i16
- 321913913U, // VQSHRNsv8i8
- 348128313U, // VQSHRNuv2i32
- 324011065U, // VQSHRNuv4i16
- 325059641U, // VQSHRNuv8i8
- 347079744U, // VQSHRUNv2i32
- 320865344U, // VQSHRUNv4i16
- 321913920U, // VQSHRUNv8i8
- 322962504U, // VQSUBsv16i8
- 347079752U, // VQSUBsv1i64
- 320865352U, // VQSUBsv2i32
- 347079752U, // VQSUBsv2i64
- 321913928U, // VQSUBsv4i16
- 320865352U, // VQSUBsv4i32
- 321913928U, // VQSUBsv8i16
- 322962504U, // VQSUBsv8i8
- 326108232U, // VQSUBuv16i8
- 348128328U, // VQSUBuv1i64
- 324011080U, // VQSUBuv2i32
- 348128328U, // VQSUBuv2i64
- 325059656U, // VQSUBuv4i16
- 324011080U, // VQSUBuv4i32
- 325059656U, // VQSUBuv8i16
- 326108232U, // VQSUBuv8i8
- 327156814U, // VRADDHNv2i32
- 328205390U, // VRADDHNv4i16
- 329253966U, // VRADDHNv8i8
- 1263535190U, // VRECPEd
- 1241678934U, // VRECPEfd
- 1241678934U, // VRECPEfq
- 1263535190U, // VRECPEq
- 302154845U, // VRECPSfd
- 302154845U, // VRECPSfq
- 1270973540U, // VREV16d8
- 1270973540U, // VREV16q8
- 1278313579U, // VREV32d16
- 1270973547U, // VREV32d8
- 1278313579U, // VREV32q16
- 1270973547U, // VREV32q8
- 1278313586U, // VREV64d16
- 1279362162U, // VREV64d32
- 1270973554U, // VREV64d8
- 1279362162U, // VREV64df
- 1278313586U, // VREV64q16
- 1279362162U, // VREV64q32
- 1270973554U, // VREV64q8
- 1279362162U, // VREV64qf
- 322962553U, // VRHADDsv16i8
- 320865401U, // VRHADDsv2i32
- 321913977U, // VRHADDsv4i16
- 320865401U, // VRHADDsv4i32
- 321913977U, // VRHADDsv8i16
- 322962553U, // VRHADDsv8i8
- 326108281U, // VRHADDuv16i8
- 324011129U, // VRHADDuv2i32
- 325059705U, // VRHADDuv4i16
- 324011129U, // VRHADDuv4i32
- 325059705U, // VRHADDuv8i16
- 326108281U, // VRHADDuv8i8
- 322962560U, // VRSHLsv16i8
- 347079808U, // VRSHLsv1i64
- 320865408U, // VRSHLsv2i32
- 347079808U, // VRSHLsv2i64
- 321913984U, // VRSHLsv4i16
- 320865408U, // VRSHLsv4i32
- 321913984U, // VRSHLsv8i16
- 322962560U, // VRSHLsv8i8
- 326108288U, // VRSHLuv16i8
- 348128384U, // VRSHLuv1i64
- 324011136U, // VRSHLuv2i32
- 348128384U, // VRSHLuv2i64
- 325059712U, // VRSHLuv4i16
- 324011136U, // VRSHLuv4i32
- 325059712U, // VRSHLuv8i16
- 326108288U, // VRSHLuv8i8
- 327156870U, // VRSHRNv2i32
- 328205446U, // VRSHRNv4i16
- 329254022U, // VRSHRNv8i8
- 322962573U, // VRSHRsv16i8
- 347079821U, // VRSHRsv1i64
- 320865421U, // VRSHRsv2i32
- 347079821U, // VRSHRsv2i64
- 321913997U, // VRSHRsv4i16
- 320865421U, // VRSHRsv4i32
- 321913997U, // VRSHRsv8i16
- 322962573U, // VRSHRsv8i8
- 326108301U, // VRSHRuv16i8
- 348128397U, // VRSHRuv1i64
- 324011149U, // VRSHRuv2i32
- 348128397U, // VRSHRuv2i64
- 325059725U, // VRSHRuv4i16
- 324011149U, // VRSHRuv4i32
- 325059725U, // VRSHRuv8i16
- 326108301U, // VRSHRuv8i8
- 1263535251U, // VRSQRTEd
- 1241678995U, // VRSQRTEfd
- 1241678995U, // VRSQRTEfq
- 1263535251U, // VRSQRTEq
- 302154907U, // VRSQRTSfd
- 302154907U, // VRSQRTSfq
- 1396769955U, // VRSRAsv16i8
- 1420887203U, // VRSRAsv1i64
- 1394672803U, // VRSRAsv2i32
- 1420887203U, // VRSRAsv2i64
- 1395721379U, // VRSRAsv4i16
- 1394672803U, // VRSRAsv4i32
- 1395721379U, // VRSRAsv8i16
- 1396769955U, // VRSRAsv8i8
- 1399915683U, // VRSRAuv16i8
- 1421935779U, // VRSRAuv1i64
- 1397818531U, // VRSRAuv2i32
- 1421935779U, // VRSRAuv2i64
- 1398867107U, // VRSRAuv4i16
- 1397818531U, // VRSRAuv4i32
- 1398867107U, // VRSRAuv8i16
- 1399915683U, // VRSRAuv8i8
- 327156905U, // VRSUBHNv2i32
- 328205481U, // VRSUBHNv4i16
- 329254057U, // VRSUBHNv8i8
- 1412530342U, // VSETLNi16
- 1413578918U, // VSETLNi32
- 1405190310U, // VSETLNi8
- 329254065U, // VSHLLi16
- 328205489U, // VSHLLi32
- 330302641U, // VSHLLi8
- 320865457U, // VSHLLsv2i64
- 321914033U, // VSHLLsv4i32
- 322962609U, // VSHLLsv8i16
- 324011185U, // VSHLLuv2i64
- 325059761U, // VSHLLuv4i32
- 326108337U, // VSHLLuv8i16
- 330302647U, // VSHLiv16i8
- 327156919U, // VSHLiv1i64
- 328205495U, // VSHLiv2i32
- 327156919U, // VSHLiv2i64
- 329254071U, // VSHLiv4i16
- 328205495U, // VSHLiv4i32
- 329254071U, // VSHLiv8i16
- 330302647U, // VSHLiv8i8
- 322962615U, // VSHLsv16i8
- 347079863U, // VSHLsv1i64
- 320865463U, // VSHLsv2i32
- 347079863U, // VSHLsv2i64
- 321914039U, // VSHLsv4i16
- 320865463U, // VSHLsv4i32
- 321914039U, // VSHLsv8i16
- 322962615U, // VSHLsv8i8
- 326108343U, // VSHLuv16i8
- 348128439U, // VSHLuv1i64
- 324011191U, // VSHLuv2i32
- 348128439U, // VSHLuv2i64
- 325059767U, // VSHLuv4i16
- 324011191U, // VSHLuv4i32
- 325059767U, // VSHLuv8i16
- 326108343U, // VSHLuv8i8
- 327156924U, // VSHRNv2i32
- 328205500U, // VSHRNv4i16
- 329254076U, // VSHRNv8i8
- 322962626U, // VSHRsv16i8
- 347079874U, // VSHRsv1i64
- 320865474U, // VSHRsv2i32
- 347079874U, // VSHRsv2i64
- 321914050U, // VSHRsv4i16
- 320865474U, // VSHRsv4i32
- 321914050U, // VSHRsv8i16
- 322962626U, // VSHRsv8i8
- 326108354U, // VSHRuv16i8
- 348128450U, // VSHRuv1i64
- 324011202U, // VSHRuv2i32
- 348128450U, // VSHRuv2i64
- 325059778U, // VSHRuv4i16
- 324011202U, // VSHRuv4i32
- 325059778U, // VSHRuv8i16
- 326108354U, // VSHRuv8i8
- 1288700675U, // VSITOD
- 1276445443U, // VSITOS
- 1405191367U, // VSLIv16i8
- 1418822855U, // VSLIv1i64
- 1413579975U, // VSLIv2i32
- 1418822855U, // VSLIv2i64
- 1412531399U, // VSLIv4i16
- 1413579975U, // VSLIv4i32
- 1412531399U, // VSLIv8i16
- 1405191367U, // VSLIv8i8
- 1240630476U, // VSQRTD
- 1241679052U, // VSQRTS
- 1396770002U, // VSRAsv16i8
- 1420887250U, // VSRAsv1i64
- 1394672850U, // VSRAsv2i32
- 1420887250U, // VSRAsv2i64
- 1395721426U, // VSRAsv4i16
- 1394672850U, // VSRAsv4i32
- 1395721426U, // VSRAsv8i16
- 1396770002U, // VSRAsv8i8
- 1399915730U, // VSRAuv16i8
- 1421935826U, // VSRAuv1i64
- 1397818578U, // VSRAuv2i32
- 1421935826U, // VSRAuv2i64
- 1398867154U, // VSRAuv4i16
- 1397818578U, // VSRAuv4i32
- 1398867154U, // VSRAuv8i16
- 1399915730U, // VSRAuv8i8
- 1405191383U, // VSRIv16i8
- 1418822871U, // VSRIv1i64
- 1413579991U, // VSRIv2i32
- 1418822871U, // VSRIv2i64
- 1412531415U, // VSRIv4i16
- 1413579991U, // VSRIv4i32
- 1412531415U, // VSRIv8i16
- 1405191383U, // VSRIv8i8
- 475563228U, // VST1d16
- 476611804U, // VST1d32
- 477660380U, // VST1d64
- 478708956U, // VST1d8
- 476611804U, // VST1df
- 473498844U, // VST1q16
- 474547420U, // VST1q32
- 479790300U, // VST1q64
- 466158812U, // VST1q8
- 474547420U, // VST1qf
- 2757264609U, // VST2LNd16
- 2758313185U, // VST2LNd32
- 2760410337U, // VST2LNd8
- 2757264609U, // VST2LNq16a
- 2757264609U, // VST2LNq16b
- 2758313185U, // VST2LNq32a
- 2758313185U, // VST2LNq32b
- 2354611425U, // VST2d16
- 2355660001U, // VST2d32
- 2356708572U, // VST2d64
- 2357757153U, // VST2d8
- 2488829153U, // VST2q16
- 2489877729U, // VST2q32
- 2491974881U, // VST2q8
- 2488829158U, // VST3LNd16
- 2489877734U, // VST3LNd32
- 2491974886U, // VST3LNd8
- 2488829158U, // VST3LNq16a
- 2488829158U, // VST3LNq16b
- 2489877734U, // VST3LNq32a
- 2489877734U, // VST3LNq32b
- 2757264614U, // VST3d16
- 2758313190U, // VST3d32
- 2759361756U, // VST3d64
- 2760410342U, // VST3d8
- 2488894694U, // VST3q16a
- 2488894694U, // VST3q16b
- 2489943270U, // VST3q32a
- 2489943270U, // VST3q32b
- 2492040422U, // VST3q8a
- 2492040422U, // VST3q8b
- 2220393707U, // VST4LNd16
- 2221442283U, // VST4LNd32
- 2223539435U, // VST4LNd8
- 2220393707U, // VST4LNq16a
- 2220393707U, // VST4LNq16b
- 2221442283U, // VST4LNq32a
- 2221442283U, // VST4LNq32b
- 2488829163U, // VST4d16
- 2489877739U, // VST4d32
- 2490926300U, // VST4d64
- 2491974891U, // VST4d8
- 2220459243U, // VST4q16a
- 2220459243U, // VST4q16b
- 2221507819U, // VST4q32a
- 2221507819U, // VST4q32b
- 2223604971U, // VST4q8a
- 2223604971U, // VST4q8b
- 2952791280U, // VSTMD
- 2952791280U, // VSTMS
- 345081077U, // VSTRD
- 271975674U, // VSTRQ
- 339838197U, // VSTRS
- 301106433U, // VSUBD
- 327156998U, // VSUBHNv2i32
- 328205574U, // VSUBHNv4i16
- 329254150U, // VSUBHNv8i8
- 320865549U, // VSUBLsv2i64
- 321914125U, // VSUBLsv4i32
- 322962701U, // VSUBLsv8i16
- 324011277U, // VSUBLuv2i64
- 325059853U, // VSUBLuv4i32
- 326108429U, // VSUBLuv8i16
- 302155009U, // VSUBS
- 320865555U, // VSUBWsv2i64
- 321914131U, // VSUBWsv4i32
- 322962707U, // VSUBWsv8i16
- 324011283U, // VSUBWuv2i64
- 325059859U, // VSUBWuv4i32
- 326108435U, // VSUBWuv8i16
- 302155009U, // VSUBfd
- 302155009U, // VSUBfd_sfp
- 302155009U, // VSUBfq
- 330302721U, // VSUBv16i8
- 327156993U, // VSUBv1i64
- 328205569U, // VSUBv2i32
- 327156993U, // VSUBv2i64
- 329254145U, // VSUBv4i16
- 328205569U, // VSUBv4i32
- 329254145U, // VSUBv8i16
- 330302721U, // VSUBv8i8
- 331449625U, // VTBL1
- 1405191449U, // VTBL2
- 465667353U, // VTBL3
- 2344715545U, // VTBL4
- 1405191454U, // VTBX1
- 465667358U, // VTBX2
- 2344715550U, // VTBX3
- 2747368734U, // VTBX4
- 1289749251U, // VTOSIZD
- 1274348291U, // VTOSIZS
- 1290797827U, // VTOUIZD
- 1275396867U, // VTOUIZS
- 1412531491U, // VTRNd16
- 1413580067U, // VTRNd32
- 1405191459U, // VTRNd8
- 1412531491U, // VTRNq16
- 1413580067U, // VTRNq32
- 1405191459U, // VTRNq8
- 331449640U, // VTSTv16i8
- 339838248U, // VTSTv2i32
- 338789672U, // VTSTv4i16
- 339838248U, // VTSTv4i32
- 338789672U, // VTSTv8i16
- 331449640U, // VTSTv8i8
- 1291846403U, // VUITOD
- 1277494019U, // VUITOS
- 1412531501U, // VUZPd16
- 1413580077U, // VUZPd32
- 1405191469U, // VUZPd8
- 1412531501U, // VUZPq16
- 1413580077U, // VUZPq32
- 1405191469U, // VUZPq8
- 1412531506U, // VZIPd16
- 1413580082U, // VZIPd32
- 1405191474U, // VZIPd8
- 1412531506U, // VZIPq16
- 1413580082U, // VZIPq32
- 1405191474U, // VZIPq8
- 134217741U, // t2ADCSri
- 134219063U, // t2ADCSrr
- 134219063U, // t2ADCSrs
- 3090251795U, // t2ADCri
- 3172106259U, // t2ADCrr
- 3306323987U, // t2ADCrs
- 353533975U, // t2ADDSri
- 353533975U, // t2ADDSrr
- 1427275799U, // t2ADDSrs
- 3172106268U, // t2ADDrSPi
- 271680831U, // t2ADDrSPi12
- 3306323996U, // t2ADDrSPs
- 3172106268U, // t2ADDri
- 3090253119U, // t2ADDri12
- 3172106268U, // t2ADDrr
- 3306323996U, // t2ADDrs
- 3090251846U, // t2ANDri
- 3172106310U, // t2ANDrr
- 3306324038U, // t2ANDrs
- 3172107588U, // t2ASRri
- 3172107588U, // t2ASRrr
- 138413384U, // t2B
- 271679566U, // t2BFC
- 3090251858U, // t2BICri
- 3172106322U, // t2BICrr
- 3306324050U, // t2BICrs
- 220201080U, // t2BR_JT
- 890568852U, // t2Bcc
- 1211203734U, // t2CLZ
- 1293058202U, // t2CMNzri
- 1293058202U, // t2CMNzrr
- 353534106U, // t2CMNzrs
- 1293058206U, // t2CMPri
- 1293058206U, // t2CMPrr
- 353534110U, // t2CMPrs
- 1293058206U, // t2CMPzri
- 1293058206U, // t2CMPzrr
- 353534110U, // t2CMPzrs
- 3090251938U, // t2EORri
- 3172106402U, // t2EORrr
- 3306324130U, // t2EORrs
- 3355444557U, // t2IT
- 189U, // t2Int_MemBarrierV7
- 193U, // t2Int_SyncBarrierV7
- 221250896U, // t2Int_eh_sjlj_setjmp
- 1698693327U, // t2LDM
- 1698693327U, // t2LDM_RET
- 1345421527U, // t2LDRB_POST
- 1345421527U, // t2LDRB_PRE
- 353534167U, // t2LDRBi12
- 271679703U, // t2LDRBi8
- 1293058263U, // t2LDRBpci
- 1427275991U, // t2LDRBs
- 1345421532U, // t2LDRDi8
- 271679708U, // t2LDRDpci
- 1211203809U, // t2LDREX
- 1211203815U, // t2LDREXB
- 271679726U, // t2LDREXD
- 1211203829U, // t2LDREXH
- 1345421564U, // t2LDRH_POST
- 1345421564U, // t2LDRH_PRE
- 353534204U, // t2LDRHi12
- 271679740U, // t2LDRHi8
- 1293058300U, // t2LDRHpci
- 1427276028U, // t2LDRHs
- 1345421569U, // t2LDRSB_POST
- 1345421569U, // t2LDRSB_PRE
- 353534209U, // t2LDRSBi12
- 271679745U, // t2LDRSBi8
- 1293058305U, // t2LDRSBpci
- 1427276033U, // t2LDRSBs
- 1345421575U, // t2LDRSH_POST
- 1345421575U, // t2LDRSH_PRE
- 353534215U, // t2LDRSHi12
- 271679751U, // t2LDRSHi8
- 1293058311U, // t2LDRSHpci
- 1427276039U, // t2LDRSHs
- 1345421523U, // t2LDR_POST
- 1345421523U, // t2LDR_PRE
- 353534163U, // t2LDRi12
- 271679699U, // t2LDRi8
- 1293058259U, // t2LDRpci
- 134219100U, // t2LDRpci_pic
- 1427275987U, // t2LDRs
- 1293550949U, // t2LEApcrel
- 354026853U, // t2LEApcrelJT
- 3172107625U, // t2LSLri
- 3172107625U, // t2LSLrr
- 3172107629U, // t2LSRri
- 3172107629U, // t2LSRrr
- 1345421587U, // t2MLA
- 1345421591U, // t2MLS
- 1427277124U, // t2MOVCCasr
- 353534235U, // t2MOVCCi
- 1427277161U, // t2MOVCClsl
- 1427277165U, // t2MOVCClsr
- 353534235U, // t2MOVCCr
- 1427277169U, // t2MOVCCror
- 271679775U, // t2MOVTi16
- 3579478299U, // t2MOVi
- 1211203876U, // t2MOVi16
- 1211203876U, // t2MOVi32imm
- 3579478299U, // t2MOVr
- 3579512181U, // t2MOVrx
- 134219129U, // t2MOVsra_flag
- 134219137U, // t2MOVsrl_flag
- 271679790U, // t2MUL
- 3579511090U, // t2MVNi
- 1293058354U, // t2MVNr
- 353534258U, // t2MVNs
- 3090253193U, // t2ORNri
- 3090253193U, // t2ORNrr
- 3224470921U, // t2ORNrs
- 3090252086U, // t2ORRri
- 3172106550U, // t2ORRrr
- 3306324278U, // t2ORRrs
- 1345421628U, // t2PKHBT
- 1345421634U, // t2PKHTB
- 1211203912U, // t2RBIT
- 1293058381U, // t2REV
- 1293058385U, // t2REV16
- 1293058391U, // t2REVSH
- 3172107633U, // t2RORri
- 3172107633U, // t2RORrr
- 3623879010U, // t2RSBSri
- 3492905314U, // t2RSBSrs
- 353534306U, // t2RSBri
- 1345421666U, // t2RSBrs
- 134218096U, // t2SBCSri
- 134219149U, // t2SBCSrr
- 134219149U, // t2SBCSrs
- 3090252150U, // t2SBCri
- 3172106614U, // t2SBCrr
- 3306324342U, // t2SBCrs
- 1345421690U, // t2SBFX
- 1345421695U, // t2SMLABB
- 1345421702U, // t2SMLABT
- 1345421709U, // t2SMLAL
- 1345421715U, // t2SMLATB
- 1345421722U, // t2SMLATT
- 1345421729U, // t2SMLAWB
- 1345421736U, // t2SMLAWT
- 1345421743U, // t2SMMLA
- 1345421749U, // t2SMMLS
- 271679931U, // t2SMMUL
- 271679937U, // t2SMULBB
- 271679944U, // t2SMULBT
- 1345421775U, // t2SMULL
- 271679957U, // t2SMULTB
- 271679964U, // t2SMULTT
- 271679971U, // t2SMULWB
- 271679978U, // t2SMULWT
- 1698693617U, // t2STM
- 1345323513U, // t2STRB_POST
- 1345323513U, // t2STRB_PRE
- 353534457U, // t2STRBi12
- 271679993U, // t2STRBi8
- 1427276281U, // t2STRBs
- 1345421822U, // t2STRDi8
- 271680003U, // t2STREX
- 271680009U, // t2STREXB
- 1345421840U, // t2STREXD
- 271680023U, // t2STREXH
- 1345323550U, // t2STRH_POST
- 1345323550U, // t2STRH_PRE
- 353534494U, // t2STRHi12
- 271680030U, // t2STRHi8
- 1427276318U, // t2STRHs
- 1345323509U, // t2STR_POST
- 1345323509U, // t2STR_PRE
- 353534453U, // t2STRi12
- 271679989U, // t2STRi8
- 1427276277U, // t2STRs
- 353534499U, // t2SUBSri
- 353534499U, // t2SUBSrr
- 1427276323U, // t2SUBSrs
- 3172106792U, // t2SUBrSPi
- 271680917U, // t2SUBrSPi12
- 134219162U, // t2SUBrSPi12_
- 134219170U, // t2SUBrSPi_
- 3224470056U, // t2SUBrSPs
- 134219179U, // t2SUBrSPs_
- 3172106792U, // t2SUBri
- 3090253205U, // t2SUBri12
- 3172106792U, // t2SUBrr
- 3306324520U, // t2SUBrs
- 271680044U, // t2SXTABrr
- 1345421868U, // t2SXTABrr_rot
- 271680050U, // t2SXTAHrr
- 1345421874U, // t2SXTAHrr_rot
- 1293058616U, // t2SXTBr
- 353534520U, // t2SXTBr_rot
- 1293058621U, // t2SXTHr
- 353534525U, // t2SXTHr_rot
- 3758097842U, // t2TBB
- 3758097847U, // t2TBH
- 1293058626U, // t2TEQri
- 1293058626U, // t2TEQrr
- 353534530U, // t2TEQrs
- 582U, // t2TPsoft
- 1293058649U, // t2TSTri
- 1293058649U, // t2TSTrr
- 353534553U, // t2TSTrs
- 1345421917U, // t2UBFX
- 1345421922U, // t2UMAAL
- 1345421928U, // t2UMLAL
- 1345421934U, // t2UMULL
- 271680116U, // t2UXTABrr
- 1345421940U, // t2UXTABrr_rot
- 271680122U, // t2UXTAHrr
- 1345421946U, // t2UXTAHrr_rot
- 1293058688U, // t2UXTB16r
- 353534592U, // t2UXTB16r_rot
- 1293058695U, // t2UXTBr
- 353534599U, // t2UXTBr_rot
- 1293058700U, // t2UXTHr
- 353534604U, // t2UXTHr_rot
- 3983245331U, // tADC
- 271679516U, // tADDhirr
- 3982557212U, // tADDi3
- 3983245340U, // tADDi8
- 225445308U, // tADDrPCi
- 134284732U, // tADDrSP
- 134219196U, // tADDrSPi
- 3982557212U, // tADDrr
- 135005628U, // tADDspi
- 134284732U, // tADDspr
- 134284737U, // tADDspr_
- 138413512U, // tADJCALLSTACKDOWN
- 138413533U, // tADJCALLSTACKUP
- 3983245382U, // tAND
- 134284784U, // tANDsp
- 3982558532U, // tASRri
- 3983246660U, // tASRrr
- 138412107U, // tB
- 3983245394U, // tBIC
- 671088726U, // tBL
- 671088730U, // tBLXi
- 671088730U, // tBLXi_r9
- 138412122U, // tBLXr
- 138412122U, // tBLXr_r9
- 671088726U, // tBLr9
- 138412152U, // tBRIND
- 226492536U, // tBR_JTr
- 138412161U, // tBX
- 1527U, // tBX_RET
- 138412130U, // tBX_RET_vararg
- 138412161U, // tBXr9
- 808550548U, // tBcc
- 227541078U, // tBfar
- 134219261U, // tCBNZ
- 134219267U, // tCBZ
- 1211203738U, // tCMNz
- 1211203742U, // tCMPhir
- 1211203742U, // tCMPi8
- 1211203742U, // tCMPr
- 1211203742U, // tCMPzhir
- 1211203742U, // tCMPzi8
- 1211203742U, // tCMPzr
- 3983245474U, // tEOR
- 228591112U, // tInt_eh_sjlj_setjmp
- 1613955279U, // tLDM
- 1345421523U, // tLDR
- 1345421527U, // tLDRB
- 1345421527U, // tLDRBi
- 1345421564U, // tLDRH
- 1345421564U, // tLDRHi
- 271679745U, // tLDRSB
- 271679751U, // tLDRSH
- 1211203795U, // tLDRcp
- 1345421523U, // tLDRi
- 1303380179U, // tLDRpci
- 134219325U, // tLDRpci_pic
- 271679699U, // tLDRspi
- 1211204965U, // tLEApcrel
- 271680869U, // tLEApcrelJT
- 3982558569U, // tLSLri
- 3983246697U, // tLSLrr
- 3982558573U, // tLSRri
- 3983246701U, // tLSRrr
- 271679771U, // tMOVCCi
- 271679771U, // tMOVCCr
- 272631366U, // tMOVCCr_pseudo
- 134219345U, // tMOVSr
- 134219351U, // tMOVgpr2gpr
- 134219351U, // tMOVgpr2tgpr
- 3989111067U, // tMOVi8
- 134219351U, // tMOVr
- 134219351U, // tMOVtgpr2gpr
- 3983245614U, // tMUL
- 3989111090U, // tMVN
- 3983245622U, // tORR
- 1976566074U, // tPICADD
- 1077708380U, // tPOP
- 1077708380U, // tPOP_RET
- 1077708384U, // tPUSH
- 1211203917U, // tREV
- 1211203921U, // tREV16
- 1211203927U, // tREVSH
- 3983246705U, // tROR
- 3989078370U, // tRSB
- 271679699U, // tRestore
- 3983245686U, // tSBC
- 1613955569U, // tSTM
- 1345421813U, // tSTR
- 1345421817U, // tSTRB
- 1345421817U, // tSTRBi
- 1345421854U, // tSTRH
- 1345421854U, // tSTRHi
- 1345421813U, // tSTRi
- 271679989U, // tSTRspi
- 3982557736U, // tSUBi3
- 3983245864U, // tSUBi8
- 3982557736U, // tSUBrr
- 135005797U, // tSUBspi
- 135005611U, // tSUBspi_
- 1211204152U, // tSXTB
- 1211204157U, // tSXTH
- 271679989U, // tSpill
- 582U, // tTPsoft
- 1211204185U, // tTST
- 1211204231U, // tUXTB
- 1211204236U, // tUXTH
+ 1U, // DBG_VALUE
+ 67108875U, // ADCSSri
+ 67108875U, // ADCSSrr
+ 67108875U, // ADCSSrs
+ 134758417U, // ADCri
+ 134774801U, // ADCrr
+ 202375185U, // ADCrs
+ 135839765U, // ADDSri
+ 135839765U, // ADDSrr
+ 202948629U, // ADDSrs
+ 134758426U, // ADDri
+ 134774810U, // ADDrr
+ 202375194U, // ADDrs
+ 69206046U, // ADJCALLSTACKDOWN
+ 69206066U, // ADJCALLSTACKUP
+ 134758468U, // ANDri
+ 134774852U, // ANDrr
+ 202375236U, // ANDrs
+ 271056968U, // ATOMIC_CMP_SWAP_I16
+ 271581256U, // ATOMIC_CMP_SWAP_I32
+ 272105544U, // ATOMIC_CMP_SWAP_I8
+ 272629832U, // ATOMIC_LOAD_ADD_I16
+ 273154120U, // ATOMIC_LOAD_ADD_I32
+ 273678408U, // ATOMIC_LOAD_ADD_I8
+ 274202696U, // ATOMIC_LOAD_AND_I16
+ 274726984U, // ATOMIC_LOAD_AND_I32
+ 275251272U, // ATOMIC_LOAD_AND_I8
+ 275775560U, // ATOMIC_LOAD_NAND_I16
+ 276299848U, // ATOMIC_LOAD_NAND_I32
+ 276824136U, // ATOMIC_LOAD_NAND_I8
+ 277348424U, // ATOMIC_LOAD_OR_I16
+ 277872712U, // ATOMIC_LOAD_OR_I32
+ 278397000U, // ATOMIC_LOAD_OR_I8
+ 278921288U, // ATOMIC_LOAD_SUB_I16
+ 279445576U, // ATOMIC_LOAD_SUB_I32
+ 279969864U, // ATOMIC_LOAD_SUB_I8
+ 280494152U, // ATOMIC_LOAD_XOR_I16
+ 281018440U, // ATOMIC_LOAD_XOR_I32
+ 281542728U, // ATOMIC_LOAD_XOR_I8
+ 282067016U, // ATOMIC_SWAP_I16
+ 282591304U, // ATOMIC_SWAP_I32
+ 283115592U, // ATOMIC_SWAP_I8
+ 69206089U, // B
+ 135839820U, // BFC
+ 134758480U, // BICri
+ 134774864U, // BICrr
+ 202375248U, // BICrs
+ 337166420U, // BKPT
+ 402653273U, // BL
+ 69206109U, // BLX
+ 69206109U, // BLXr9
+ 337182818U, // BL_pred
+ 402653273U, // BLr9
+ 337182818U, // BLr9_pred
+ 69206117U, // BRIND
+ 67108969U, // BR_JTadd
+ 469762162U, // BR_JTm
+ 82313339U, // BR_JTr
+ 69206148U, // BX
+ 337166484U, // BXJ
+ 552599704U, // BX_RET
+ 69206148U, // BXr9
+ 337166491U, // Bcc
+ 620314781U, // CDP
+ 687866017U, // CDP2
+ 739819688U, // CLZ
+ 739819692U, // CMNzri
+ 739819692U, // CMNzrr
+ 806928556U, // CMNzrs
+ 739819696U, // CMPri
+ 739819696U, // CMPrr
+ 806928560U, // CMPrs
+ 739819696U, // CMPzri
+ 739819696U, // CMPzrr
+ 806928560U, // CMPzrs
+ 872415304U, // CONSTPOOL_ENTRY
+ 939524276U, // CPS
+ 337166520U, // DBG
+ 134758588U, // EORri
+ 134774972U, // EORrr
+ 202375356U, // EORrs
+ 755597504U, // FCONSTD
+ 756121792U, // FCONSTS
+ 555221189U, // FMSTAT
+ 85983434U, // Int_MemBarrierV6
+ 215U, // Int_MemBarrierV7
+ 86507722U, // Int_SyncBarrierV6
+ 219U, // Int_SyncBarrierV7
+ 87032031U, // Int_eh_sjlj_setjmp
+ 1008320745U, // LDM
+ 1008320745U, // LDM_RET
+ 806928621U, // LDR
+ 806928625U, // LDRB
+ 202948849U, // LDRBT
+ 202948849U, // LDRB_POST
+ 202948849U, // LDRB_PRE
+ 202948854U, // LDRD
+ 739819771U, // LDREX
+ 739819777U, // LDREXB
+ 135840008U, // LDREXD
+ 739819791U, // LDREXH
+ 806928662U, // LDRH
+ 202948886U, // LDRH_POST
+ 202948886U, // LDRH_PRE
+ 806928667U, // LDRSB
+ 202948891U, // LDRSB_POST
+ 202948891U, // LDRSB_PRE
+ 806928673U, // LDRSH
+ 202948897U, // LDRSH_POST
+ 202948897U, // LDRSH_PRE
+ 202948903U, // LDRT
+ 202948845U, // LDR_POST
+ 202948845U, // LDR_PRE
+ 806928621U, // LDRcp
+ 1094189356U, // LEApcrel
+ 1094713644U, // LEApcrelJT
+ 620331314U, // MCR
+ 671121718U, // MCR2
+ 217678141U, // MCRR
+ 671121730U, // MCRR2
+ 826802506U, // MLA
+ 806928718U, // MLS
+ 135840082U, // MOVCCi
+ 135840082U, // MOVCCr
+ 202948946U, // MOVCCs
+ 135840086U, // MOVTi16
+ 760349010U, // MOVi
+ 739819867U, // MOVi16
+ 739819858U, // MOVi2pieces
+ 739819867U, // MOVi32imm
+ 760217938U, // MOVr
+ 760217938U, // MOVrx
+ 826949970U, // MOVs
+ 739819872U, // MOVsra_flag
+ 739819872U, // MOVsrl_flag
+ 620331365U, // MRC
+ 671121769U, // MRC2
+ 217678192U, // MRRC
+ 671121781U, // MRRC2
+ 337166717U, // MRS
+ 337166717U, // MRSsys
+ 358089085U, // MSR
+ 358613373U, // MSRsys
+ 134775169U, // MUL
+ 760349061U, // MVNi
+ 760217989U, // MVNr
+ 826950021U, // MVNs
+ 538968457U, // NOP
+ 134758797U, // ORRri
+ 134775181U, // ORRrr
+ 202375565U, // ORRrs
+ 1164444049U, // PICADD
+ 1232077201U, // PICLDR
+ 1232601489U, // PICLDRB
+ 1233125777U, // PICLDRH
+ 1233650065U, // PICLDRSB
+ 1234174353U, // PICLDRSH
+ 1234698641U, // PICSTR
+ 1235222929U, // PICSTRB
+ 1235747217U, // PICSTRH
+ 806928787U, // PKHBT
+ 806928793U, // PKHTB
+ 135840159U, // QADD
+ 135840164U, // QADD16
+ 135840171U, // QADD8
+ 135840177U, // QASX
+ 135840182U, // QDADD
+ 135840188U, // QDSUB
+ 135840194U, // QSAX
+ 135840199U, // QSUB
+ 135840204U, // QSUB16
+ 135840211U, // QSUB8
+ 739819993U, // RBIT
+ 739819998U, // REV
+ 739820002U, // REV16
+ 739820008U, // REVSH
+ 135840238U, // RSBSri
+ 202949102U, // RSBSrs
+ 134758899U, // RSBri
+ 202375667U, // RSBrs
+ 67109367U, // RSCSri
+ 67109367U, // RSCSrs
+ 134758909U, // RSCri
+ 202375677U, // RSCrs
+ 67109377U, // SBCSSri
+ 67109377U, // SBCSSrr
+ 67109377U, // SBCSSrs
+ 134758919U, // SBCri
+ 134775303U, // SBCrr
+ 202375687U, // SBCrs
+ 806928907U, // SBFX
+ 528U, // SETENDBE
+ 538U, // SETENDLE
+ 538968612U, // SEV
+ 806928936U, // SMLABB
+ 806928943U, // SMLABT
+ 826802742U, // SMLAL
+ 806928956U, // SMLALBB
+ 806928964U, // SMLALBT
+ 806928972U, // SMLALTB
+ 806928980U, // SMLALTT
+ 806928988U, // SMLATB
+ 806928995U, // SMLATT
+ 806929002U, // SMLAWB
+ 806929009U, // SMLAWT
+ 806929016U, // SMMLA
+ 806929022U, // SMMLS
+ 135840388U, // SMMUL
+ 135840394U, // SMULBB
+ 135840401U, // SMULBT
+ 826802840U, // SMULL
+ 135840414U, // SMULTB
+ 135840421U, // SMULTT
+ 135840428U, // SMULWB
+ 135840435U, // SMULWT
+ 1008321210U, // STM
+ 806929086U, // STR
+ 806929090U, // STRB
+ 202900167U, // STRBT
+ 202900162U, // STRB_POST
+ 202900162U, // STRB_PRE
+ 202949325U, // STRD
+ 135840466U, // STREX
+ 135840472U, // STREXB
+ 806929119U, // STREXD
+ 135840486U, // STREXH
+ 806929133U, // STRH
+ 202900205U, // STRH_POST
+ 202900205U, // STRH_PRE
+ 202900210U, // STRT
+ 202900158U, // STR_POST
+ 202900158U, // STR_PRE
+ 135840503U, // SUBSri
+ 135840503U, // SUBSrr
+ 202949367U, // SUBSrs
+ 134759164U, // SUBri
+ 134775548U, // SUBrr
+ 202375932U, // SUBrs
+ 337167104U, // SVC
+ 135840516U, // SWP
+ 135840520U, // SWPB
+ 135840525U, // SXTABrr
+ 806929165U, // SXTABrr_rot
+ 135840531U, // SXTAHrr
+ 806929171U, // SXTAHrr_rot
+ 739820313U, // SXTBr
+ 135840537U, // SXTBr_rot
+ 739820318U, // SXTHr
+ 135840542U, // SXTHr_rot
+ 739820323U, // TEQri
+ 739820323U, // TEQrr
+ 806929187U, // TEQrs
+ 807U, // TPsoft
+ 538968890U, // TRAP
+ 739820351U, // TSTri
+ 739820351U, // TSTrr
+ 806929215U, // TSTrs
+ 806929219U, // UBFX
+ 806929224U, // UMAAL
+ 826803022U, // UMLAL
+ 826803028U, // UMULL
+ 135840602U, // UQADD16
+ 135840610U, // UQADD8
+ 135840617U, // UQASX
+ 135840623U, // UQSAX
+ 135840629U, // UQSUB16
+ 135840637U, // UQSUB8
+ 135840644U, // UXTABrr
+ 806929284U, // UXTABrr_rot
+ 135840650U, // UXTAHrr
+ 806929290U, // UXTAHrr_rot
+ 739820432U, // UXTB16r
+ 135840656U, // UXTB16r_rot
+ 739820439U, // UXTBr
+ 135840663U, // UXTBr_rot
+ 739820444U, // UXTHr
+ 135840668U, // UXTHr_rot
+ 833651617U, // VABALsv2i64
+ 834175905U, // VABALsv4i32
+ 834700193U, // VABALsv8i16
+ 835224481U, // VABALuv2i64
+ 835748769U, // VABALuv4i32
+ 836273057U, // VABALuv8i16
+ 834700199U, // VABAsv16i8
+ 833651623U, // VABAsv2i32
+ 834175911U, // VABAsv4i16
+ 833651623U, // VABAsv4i32
+ 834175911U, // VABAsv8i16
+ 834700199U, // VABAsv8i8
+ 836273063U, // VABAuv16i8
+ 835224487U, // VABAuv2i32
+ 835748775U, // VABAuv4i16
+ 835224487U, // VABAuv4i32
+ 835748775U, // VABAuv8i16
+ 836273063U, // VABAuv8i8
+ 162530220U, // VABDLsv2i64
+ 163054508U, // VABDLsv4i32
+ 163578796U, // VABDLsv8i16
+ 164103084U, // VABDLuv2i64
+ 164627372U, // VABDLuv4i32
+ 165151660U, // VABDLuv8i16
+ 152142770U, // VABDfd
+ 152142770U, // VABDfq
+ 163578802U, // VABDsv16i8
+ 162530226U, // VABDsv2i32
+ 163054514U, // VABDsv4i16
+ 162530226U, // VABDsv4i32
+ 163054514U, // VABDsv8i16
+ 163578802U, // VABDsv8i8
+ 165151666U, // VABDuv16i8
+ 164103090U, // VABDuv2i32
+ 164627378U, // VABDuv4i16
+ 164103090U, // VABDuv4i32
+ 164627378U, // VABDuv8i16
+ 165151666U, // VABDuv8i8
+ 755598263U, // VABSD
+ 756122551U, // VABSS
+ 756122551U, // VABSfd
+ 756122551U, // VABSfd_sfp
+ 756122551U, // VABSfq
+ 767558583U, // VABSv16i8
+ 766510007U, // VABSv2i32
+ 767034295U, // VABSv4i16
+ 766510007U, // VABSv4i32
+ 767034295U, // VABSv8i16
+ 767558583U, // VABSv8i8
+ 152142780U, // VACGEd
+ 152142780U, // VACGEq
+ 152142786U, // VACGTd
+ 152142786U, // VACGTq
+ 151618504U, // VADDD
+ 165675981U, // VADDHNv2i32
+ 166200269U, // VADDHNv4i16
+ 166724557U, // VADDHNv8i8
+ 162530260U, // VADDLsv2i64
+ 163054548U, // VADDLsv4i32
+ 163578836U, // VADDLsv8i16
+ 164103124U, // VADDLuv2i64
+ 164627412U, // VADDLuv4i32
+ 165151700U, // VADDLuv8i16
+ 152142792U, // VADDS
+ 162530266U, // VADDWsv2i64
+ 163054554U, // VADDWsv4i32
+ 163578842U, // VADDWsv8i16
+ 164103130U, // VADDWuv2i64
+ 164627418U, // VADDWuv4i32
+ 165151706U, // VADDWuv8i16
+ 152142792U, // VADDfd
+ 152142792U, // VADDfd_sfp
+ 152142792U, // VADDfq
+ 167248840U, // VADDv16i8
+ 165675976U, // VADDv1i64
+ 166200264U, // VADDv2i32
+ 165675976U, // VADDv2i64
+ 166724552U, // VADDv4i16
+ 166200264U, // VADDv4i32
+ 166724552U, // VADDv8i16
+ 167248840U, // VADDv8i8
+ 135840736U, // VANDd
+ 135840736U, // VANDq
+ 135840741U, // VBICd
+ 135840741U, // VBICq
+ 806929386U, // VBIFd
+ 806929386U, // VBIFq
+ 806929391U, // VBITd
+ 806929391U, // VBITq
+ 806929396U, // VBSLd
+ 806929396U, // VBSLq
+ 152142841U, // VCEQfd
+ 152142841U, // VCEQfq
+ 167248889U, // VCEQv16i8
+ 166200313U, // VCEQv2i32
+ 166724601U, // VCEQv4i16
+ 166200313U, // VCEQv4i32
+ 166724601U, // VCEQv8i16
+ 167248889U, // VCEQv8i8
+ 152142846U, // VCGEfd
+ 152142846U, // VCGEfq
+ 163578878U, // VCGEsv16i8
+ 162530302U, // VCGEsv2i32
+ 163054590U, // VCGEsv4i16
+ 162530302U, // VCGEsv4i32
+ 163054590U, // VCGEsv8i16
+ 163578878U, // VCGEsv8i8
+ 165151742U, // VCGEuv16i8
+ 164103166U, // VCGEuv2i32
+ 164627454U, // VCGEuv4i16
+ 164103166U, // VCGEuv4i32
+ 164627454U, // VCGEuv8i16
+ 165151742U, // VCGEuv8i8
+ 152142851U, // VCGTfd
+ 152142851U, // VCGTfq
+ 163578883U, // VCGTsv16i8
+ 162530307U, // VCGTsv2i32
+ 163054595U, // VCGTsv4i16
+ 162530307U, // VCGTsv4i32
+ 163054595U, // VCGTsv8i16
+ 163578883U, // VCGTsv8i8
+ 165151747U, // VCGTuv16i8
+ 164103171U, // VCGTuv2i32
+ 164627459U, // VCGTuv4i16
+ 164103171U, // VCGTuv4i32
+ 164627459U, // VCGTuv8i16
+ 165151747U, // VCGTuv8i8
+ 767558664U, // VCLSv16i8
+ 766510088U, // VCLSv2i32
+ 767034376U, // VCLSv4i16
+ 766510088U, // VCLSv4i32
+ 767034376U, // VCLSv8i16
+ 767558664U, // VCLSv8i8
+ 771228685U, // VCLZv16i8
+ 770180109U, // VCLZv2i32
+ 770704397U, // VCLZv4i16
+ 770180109U, // VCLZv4i32
+ 770704397U, // VCLZv8i16
+ 771228685U, // VCLZv8i8
+ 755598354U, // VCMPD
+ 755598359U, // VCMPED
+ 756122647U, // VCMPES
+ 353010711U, // VCMPEZD
+ 353534999U, // VCMPEZS
+ 756122642U, // VCMPS
+ 353010706U, // VCMPZD
+ 353534994U, // VCMPZS
+ 771802141U, // VCNTd
+ 771802141U, // VCNTq
+ 772277282U, // VCVTBHS
+ 772801570U, // VCVTBSH
+ 773325864U, // VCVTDS
+ 773850152U, // VCVTSD
+ 772277293U, // VCVTTHS
+ 772801581U, // VCVTTSH
+ 774554664U, // VCVTf2sd
+ 774554664U, // VCVTf2sd_sfp
+ 774554664U, // VCVTf2sq
+ 775078952U, // VCVTf2ud
+ 775078952U, // VCVTf2ud_sfp
+ 775078952U, // VCVTf2uq
+ 170492968U, // VCVTf2xsd
+ 170492968U, // VCVTf2xsq
+ 171017256U, // VCVTf2xud
+ 171017256U, // VCVTf2xuq
+ 775603240U, // VCVTs2fd
+ 775603240U, // VCVTs2fd_sfp
+ 775603240U, // VCVTs2fq
+ 776127528U, // VCVTu2fd
+ 776127528U, // VCVTu2fd_sfp
+ 776127528U, // VCVTu2fq
+ 171541544U, // VCVTxs2fd
+ 171541544U, // VCVTxs2fq
+ 172065832U, // VCVTxu2fd
+ 172065832U, // VCVTxu2fq
+ 151618611U, // VDIVD
+ 152142899U, // VDIVS
+ 776520760U, // VDUP16d
+ 776520760U, // VDUP16q
+ 777045048U, // VDUP32d
+ 777045048U, // VDUP32q
+ 771802168U, // VDUP8d
+ 771802168U, // VDUP8q
+ 172540984U, // VDUPLN16d
+ 172540984U, // VDUPLN16q
+ 173065272U, // VDUPLN32d
+ 173065272U, // VDUPLN32q
+ 167822392U, // VDUPLN8d
+ 167822392U, // VDUPLN8q
+ 173065272U, // VDUPLNfd
+ 173065272U, // VDUPLNfq
+ 777045048U, // VDUPfd
+ 777045048U, // VDUPfdf
+ 777045048U, // VDUPfq
+ 777045048U, // VDUPfqf
+ 135840829U, // VEORd
+ 135840829U, // VEORq
+ 843629634U, // VEXTd16
+ 844153922U, // VEXTd32
+ 838911042U, // VEXTd8
+ 844153922U, // VEXTdf
+ 843629634U, // VEXTq16
+ 844153922U, // VEXTq32
+ 838911042U, // VEXTq8
+ 844153922U, // VEXTqf
+ 173064384U, // VGETLNi32
+ 163053760U, // VGETLNs16
+ 163578048U, // VGETLNs8
+ 164626624U, // VGETLNu16
+ 165150912U, // VGETLNu8
+ 163578951U, // VHADDsv16i8
+ 162530375U, // VHADDsv2i32
+ 163054663U, // VHADDsv4i16
+ 162530375U, // VHADDsv4i32
+ 163054663U, // VHADDsv8i16
+ 163578951U, // VHADDsv8i8
+ 165151815U, // VHADDuv16i8
+ 164103239U, // VHADDuv2i32
+ 164627527U, // VHADDuv4i16
+ 164103239U, // VHADDuv4i32
+ 164627527U, // VHADDuv8i16
+ 165151815U, // VHADDuv8i8
+ 163578957U, // VHSUBsv16i8
+ 162530381U, // VHSUBsv2i32
+ 163054669U, // VHSUBsv4i16
+ 162530381U, // VHSUBsv4i32
+ 163054669U, // VHSUBsv8i16
+ 163578957U, // VHSUBsv8i8
+ 165151821U, // VHSUBuv16i8
+ 164103245U, // VHSUBuv2i32
+ 164627533U, // VHSUBuv4i16
+ 164103245U, // VHSUBuv4i32
+ 164627533U, // VHSUBuv8i16
+ 165151821U, // VHSUBuv8i8
+ 240698451U, // VLD1d16
+ 241222739U, // VLD1d32
+ 241747027U, // VLD1d64
+ 242271315U, // VLD1d8
+ 241222739U, // VLD1df
+ 239797331U, // VLD1q16
+ 240321619U, // VLD1q32
+ 242943059U, // VLD1q64
+ 235078739U, // VLD1q8
+ 240321619U, // VLD1qf
+ 1314440280U, // VLD2LNd16
+ 1314964568U, // VLD2LNd32
+ 1316013144U, // VLD2LNd8
+ 1314440280U, // VLD2LNq16a
+ 1314440280U, // VLD2LNq16b
+ 1314964568U, // VLD2LNq32a
+ 1314964568U, // VLD2LNq32b
+ 643351640U, // VLD2d16
+ 643875928U, // VLD2d32
+ 644400211U, // VLD2d64
+ 644924504U, // VLD2d8
+ 1381549144U, // VLD2q16
+ 1382073432U, // VLD2q32
+ 1383122008U, // VLD2q8
+ 1448658013U, // VLD3LNd16
+ 1449182301U, // VLD3LNd32
+ 1450230877U, // VLD3LNd8
+ 1448658013U, // VLD3LNq16a
+ 1448658013U, // VLD3LNq16b
+ 1449182301U, // VLD3LNq32a
+ 1449182301U, // VLD3LNq32b
+ 1515766877U, // VLD3d16
+ 1516291165U, // VLD3d32
+ 1516815443U, // VLD3d64
+ 1517339741U, // VLD3d8
+ 1381549149U, // VLD3q16a
+ 1381549149U, // VLD3q16b
+ 1382073437U, // VLD3q32a
+ 1382073437U, // VLD3q32b
+ 1383122013U, // VLD3q8a
+ 1383122013U, // VLD3q8b
+ 1582875746U, // VLD4LNd16
+ 1583400034U, // VLD4LNd32
+ 1584448610U, // VLD4LNd8
+ 1582875746U, // VLD4LNq16a
+ 1582875746U, // VLD4LNq16b
+ 1583400034U, // VLD4LNq32a
+ 1583400034U, // VLD4LNq32b
+ 1381549154U, // VLD4d16
+ 1382073442U, // VLD4d32
+ 1382597715U, // VLD4d64
+ 1383122018U, // VLD4d8
+ 1314440290U, // VLD4q16a
+ 1314440290U, // VLD4q16b
+ 1314964578U, // VLD4q32a
+ 1314964578U, // VLD4q32b
+ 1316013154U, // VLD4q8a
+ 1316013154U, // VLD4q8b
+ 1610613863U, // VLDMD
+ 1610613863U, // VLDMS
+ 175686764U, // VLDRD
+ 136004721U, // VLDRQ
+ 173065324U, // VLDRS
+ 152142968U, // VMAXfd
+ 152142968U, // VMAXfq
+ 163579000U, // VMAXsv16i8
+ 162530424U, // VMAXsv2i32
+ 163054712U, // VMAXsv4i16
+ 162530424U, // VMAXsv4i32
+ 163054712U, // VMAXsv8i16
+ 163579000U, // VMAXsv8i8
+ 165151864U, // VMAXuv16i8
+ 164103288U, // VMAXuv2i32
+ 164627576U, // VMAXuv4i16
+ 164103288U, // VMAXuv4i32
+ 164627576U, // VMAXuv8i16
+ 165151864U, // VMAXuv8i8
+ 152142973U, // VMINfd
+ 152142973U, // VMINfq
+ 163579005U, // VMINsv16i8
+ 162530429U, // VMINsv2i32
+ 163054717U, // VMINsv4i16
+ 162530429U, // VMINsv4i32
+ 163054717U, // VMINsv8i16
+ 163579005U, // VMINsv8i8
+ 165151869U, // VMINuv16i8
+ 164103293U, // VMINuv2i32
+ 164627581U, // VMINuv4i16
+ 164103293U, // VMINuv4i32
+ 164627581U, // VMINuv8i16
+ 165151869U, // VMINuv8i8
+ 822707330U, // VMLAD
+ 229672071U, // VMLALslsv2i32
+ 230196359U, // VMLALslsv4i16
+ 231244935U, // VMLALsluv2i32
+ 231769223U, // VMLALsluv4i16
+ 833651847U, // VMLALsv2i64
+ 834176135U, // VMLALsv4i32
+ 834700423U, // VMLALsv8i16
+ 835224711U, // VMLALuv2i64
+ 835748999U, // VMLALuv4i32
+ 836273287U, // VMLALuv8i16
+ 823231618U, // VMLAS
+ 823231618U, // VMLAfd
+ 823231618U, // VMLAfq
+ 219251842U, // VMLAslfd
+ 219251842U, // VMLAslfq
+ 233342082U, // VMLAslv2i32
+ 233866370U, // VMLAslv4i16
+ 233342082U, // VMLAslv4i32
+ 233866370U, // VMLAslv8i16
+ 838370434U, // VMLAv16i8
+ 837321858U, // VMLAv2i32
+ 837846146U, // VMLAv4i16
+ 837321858U, // VMLAv4i32
+ 837846146U, // VMLAv8i16
+ 838370434U, // VMLAv8i8
+ 822707341U, // VMLSD
+ 229672082U, // VMLSLslsv2i32
+ 230196370U, // VMLSLslsv4i16
+ 231244946U, // VMLSLsluv2i32
+ 231769234U, // VMLSLsluv4i16
+ 833651858U, // VMLSLsv2i64
+ 834176146U, // VMLSLsv4i32
+ 834700434U, // VMLSLsv8i16
+ 835224722U, // VMLSLuv2i64
+ 835749010U, // VMLSLuv4i32
+ 836273298U, // VMLSLuv8i16
+ 823231629U, // VMLSS
+ 823231629U, // VMLSfd
+ 823231629U, // VMLSfq
+ 219251853U, // VMLSslfd
+ 219251853U, // VMLSslfq
+ 233342093U, // VMLSslv2i32
+ 233866381U, // VMLSslv4i16
+ 233342093U, // VMLSslv4i32
+ 233866381U, // VMLSslv8i16
+ 838370445U, // VMLSv16i8
+ 837321869U, // VMLSv2i32
+ 837846157U, // VMLSv4i16
+ 837321869U, // VMLSv4i32
+ 837846157U, // VMLSv8i16
+ 838370445U, // VMLSv8i8
+ 755597504U, // VMOVD
+ 135839936U, // VMOVDRR
+ 151617728U, // VMOVDcc
+ 739819712U, // VMOVDneon
+ 766510232U, // VMOVLsv2i64
+ 767034520U, // VMOVLsv4i32
+ 767558808U, // VMOVLsv8i16
+ 768083096U, // VMOVLuv2i64
+ 768607384U, // VMOVLuv4i32
+ 769131672U, // VMOVLuv8i16
+ 769655966U, // VMOVNv2i32
+ 770180254U, // VMOVNv4i16
+ 770704542U, // VMOVNv8i8
+ 739819712U, // VMOVQ
+ 135839936U, // VMOVRRD
+ 806928576U, // VMOVRRS
+ 739819712U, // VMOVRS
+ 756121792U, // VMOVS
+ 739819712U, // VMOVSR
+ 806928576U, // VMOVSRR
+ 152142016U, // VMOVScc
+ 771457216U, // VMOVv16i8
+ 769900736U, // VMOVv1i64
+ 770441408U, // VMOVv2i32
+ 769900736U, // VMOVv2i64
+ 770982080U, // VMOVv4i16
+ 770441408U, // VMOVv4i32
+ 770982080U, // VMOVv8i16
+ 771457216U, // VMOVv8i8
+ 337166533U, // VMRS
+ 377488548U, // VMSR
+ 151618729U, // VMULD
+ 176686254U, // VMULLp
+ 833619118U, // VMULLslsv2i32
+ 834143406U, // VMULLslsv4i16
+ 835191982U, // VMULLsluv2i32
+ 835716270U, // VMULLsluv4i16
+ 162530478U, // VMULLsv2i64
+ 163054766U, // VMULLsv4i32
+ 163579054U, // VMULLsv8i16
+ 164103342U, // VMULLuv2i64
+ 164627630U, // VMULLuv4i32
+ 165151918U, // VMULLuv8i16
+ 152143017U, // VMULS
+ 152143017U, // VMULfd
+ 152143017U, // VMULfd_sfp
+ 152143017U, // VMULfq
+ 176686249U, // VMULpd
+ 176686249U, // VMULpq
+ 823231657U, // VMULslfd
+ 823231657U, // VMULslfq
+ 837289129U, // VMULslv2i32
+ 837813417U, // VMULslv4i16
+ 837289129U, // VMULslv4i32
+ 837813417U, // VMULslv8i16
+ 167249065U, // VMULv16i8
+ 166200489U, // VMULv2i32
+ 166724777U, // VMULv4i16
+ 166200489U, // VMULv4i32
+ 166724777U, // VMULv8i16
+ 167249065U, // VMULv8i8
+ 739820724U, // VMVNd
+ 739820724U, // VMVNq
+ 755598521U, // VNEGD
+ 151618745U, // VNEGDcc
+ 756122809U, // VNEGS
+ 152143033U, // VNEGScc
+ 756122809U, // VNEGf32d
+ 756122809U, // VNEGf32d_sfp
+ 756122809U, // VNEGf32q
+ 767034553U, // VNEGs16d
+ 767034553U, // VNEGs16q
+ 766510265U, // VNEGs32d
+ 766510265U, // VNEGs32q
+ 767558841U, // VNEGs8d
+ 767558841U, // VNEGs8q
+ 822707390U, // VNMLAD
+ 823231678U, // VNMLAS
+ 822707396U, // VNMLSD
+ 823231684U, // VNMLSS
+ 151618762U, // VNMULD
+ 152143050U, // VNMULS
+ 135840976U, // VORNd
+ 135840976U, // VORNq
+ 135840981U, // VORRd
+ 135840981U, // VORRq
+ 163611866U, // VPADALsv16i8
+ 162563290U, // VPADALsv2i32
+ 163087578U, // VPADALsv4i16
+ 162563290U, // VPADALsv4i32
+ 163087578U, // VPADALsv8i16
+ 163611866U, // VPADALsv8i8
+ 165184730U, // VPADALuv16i8
+ 164136154U, // VPADALuv2i32
+ 164660442U, // VPADALuv4i16
+ 164136154U, // VPADALuv4i32
+ 164660442U, // VPADALuv8i16
+ 165184730U, // VPADALuv8i8
+ 767558881U, // VPADDLsv16i8
+ 766510305U, // VPADDLsv2i32
+ 767034593U, // VPADDLsv4i16
+ 766510305U, // VPADDLsv4i32
+ 767034593U, // VPADDLsv8i16
+ 767558881U, // VPADDLsv8i8
+ 769131745U, // VPADDLuv16i8
+ 768083169U, // VPADDLuv2i32
+ 768607457U, // VPADDLuv4i16
+ 768083169U, // VPADDLuv4i32
+ 768607457U, // VPADDLuv8i16
+ 769131745U, // VPADDLuv8i8
+ 152143080U, // VPADDf
+ 166724840U, // VPADDi16
+ 166200552U, // VPADDi32
+ 167249128U, // VPADDi8
+ 152143086U, // VPMAXf
+ 163054830U, // VPMAXs16
+ 162530542U, // VPMAXs32
+ 163579118U, // VPMAXs8
+ 164627694U, // VPMAXu16
+ 164103406U, // VPMAXu32
+ 165151982U, // VPMAXu8
+ 152143092U, // VPMINf
+ 163054836U, // VPMINs16
+ 162530548U, // VPMINs32
+ 163579124U, // VPMINs8
+ 164627700U, // VPMINu16
+ 164103412U, // VPMINu32
+ 165151988U, // VPMINu8
+ 767558906U, // VQABSv16i8
+ 766510330U, // VQABSv2i32
+ 767034618U, // VQABSv4i16
+ 766510330U, // VQABSv4i32
+ 767034618U, // VQABSv8i16
+ 767558906U, // VQABSv8i8
+ 163579136U, // VQADDsv16i8
+ 177210624U, // VQADDsv1i64
+ 162530560U, // VQADDsv2i32
+ 177210624U, // VQADDsv2i64
+ 163054848U, // VQADDsv4i16
+ 162530560U, // VQADDsv4i32
+ 163054848U, // VQADDsv8i16
+ 163579136U, // VQADDsv8i8
+ 165152000U, // VQADDuv16i8
+ 177734912U, // VQADDuv1i64
+ 164103424U, // VQADDuv2i32
+ 177734912U, // VQADDuv2i64
+ 164627712U, // VQADDuv4i16
+ 164103424U, // VQADDuv4i32
+ 164627712U, // VQADDuv8i16
+ 165152000U, // VQADDuv8i8
+ 229672198U, // VQDMLALslv2i32
+ 230196486U, // VQDMLALslv4i16
+ 833651974U, // VQDMLALv2i64
+ 834176262U, // VQDMLALv4i32
+ 229672206U, // VQDMLSLslv2i32
+ 230196494U, // VQDMLSLslv4i16
+ 833651982U, // VQDMLSLv2i64
+ 834176270U, // VQDMLSLv4i32
+ 833619222U, // VQDMULHslv2i32
+ 834143510U, // VQDMULHslv4i16
+ 833619222U, // VQDMULHslv4i32
+ 834143510U, // VQDMULHslv8i16
+ 162530582U, // VQDMULHv2i32
+ 163054870U, // VQDMULHv4i16
+ 162530582U, // VQDMULHv4i32
+ 163054870U, // VQDMULHv8i16
+ 833619230U, // VQDMULLslv2i32
+ 834143518U, // VQDMULLslv4i16
+ 162530590U, // VQDMULLv2i64
+ 163054878U, // VQDMULLv4i32
+ 781190438U, // VQMOVNsuv2i32
+ 766510374U, // VQMOVNsuv4i16
+ 767034662U, // VQMOVNsuv8i8
+ 781190446U, // VQMOVNsv2i32
+ 766510382U, // VQMOVNsv4i16
+ 767034670U, // VQMOVNsv8i8
+ 781714734U, // VQMOVNuv2i32
+ 768083246U, // VQMOVNuv4i16
+ 768607534U, // VQMOVNuv8i8
+ 767558965U, // VQNEGv16i8
+ 766510389U, // VQNEGv2i32
+ 767034677U, // VQNEGv4i16
+ 766510389U, // VQNEGv4i32
+ 767034677U, // VQNEGv8i16
+ 767558965U, // VQNEGv8i8
+ 833619259U, // VQRDMULHslv2i32
+ 834143547U, // VQRDMULHslv4i16
+ 833619259U, // VQRDMULHslv4i32
+ 834143547U, // VQRDMULHslv8i16
+ 162530619U, // VQRDMULHv2i32
+ 163054907U, // VQRDMULHv4i16
+ 162530619U, // VQRDMULHv4i32
+ 163054907U, // VQRDMULHv8i16
+ 163579204U, // VQRSHLsv16i8
+ 177210692U, // VQRSHLsv1i64
+ 162530628U, // VQRSHLsv2i32
+ 177210692U, // VQRSHLsv2i64
+ 163054916U, // VQRSHLsv4i16
+ 162530628U, // VQRSHLsv4i32
+ 163054916U, // VQRSHLsv8i16
+ 163579204U, // VQRSHLsv8i8
+ 165152068U, // VQRSHLuv16i8
+ 177734980U, // VQRSHLuv1i64
+ 164103492U, // VQRSHLuv2i32
+ 177734980U, // VQRSHLuv2i64
+ 164627780U, // VQRSHLuv4i16
+ 164103492U, // VQRSHLuv4i32
+ 164627780U, // VQRSHLuv8i16
+ 165152068U, // VQRSHLuv8i8
+ 177210699U, // VQRSHRNsv2i32
+ 162530635U, // VQRSHRNsv4i16
+ 163054923U, // VQRSHRNsv8i8
+ 177734987U, // VQRSHRNuv2i32
+ 164103499U, // VQRSHRNuv4i16
+ 164627787U, // VQRSHRNuv8i8
+ 177210707U, // VQRSHRUNv2i32
+ 162530643U, // VQRSHRUNv4i16
+ 163054931U, // VQRSHRUNv8i8
+ 163579228U, // VQSHLsiv16i8
+ 177210716U, // VQSHLsiv1i64
+ 162530652U, // VQSHLsiv2i32
+ 177210716U, // VQSHLsiv2i64
+ 163054940U, // VQSHLsiv4i16
+ 162530652U, // VQSHLsiv4i32
+ 163054940U, // VQSHLsiv8i16
+ 163579228U, // VQSHLsiv8i8
+ 163579234U, // VQSHLsuv16i8
+ 177210722U, // VQSHLsuv1i64
+ 162530658U, // VQSHLsuv2i32
+ 177210722U, // VQSHLsuv2i64
+ 163054946U, // VQSHLsuv4i16
+ 162530658U, // VQSHLsuv4i32
+ 163054946U, // VQSHLsuv8i16
+ 163579234U, // VQSHLsuv8i8
+ 163579228U, // VQSHLsv16i8
+ 177210716U, // VQSHLsv1i64
+ 162530652U, // VQSHLsv2i32
+ 177210716U, // VQSHLsv2i64
+ 163054940U, // VQSHLsv4i16
+ 162530652U, // VQSHLsv4i32
+ 163054940U, // VQSHLsv8i16
+ 163579228U, // VQSHLsv8i8
+ 165152092U, // VQSHLuiv16i8
+ 177735004U, // VQSHLuiv1i64
+ 164103516U, // VQSHLuiv2i32
+ 177735004U, // VQSHLuiv2i64
+ 164627804U, // VQSHLuiv4i16
+ 164103516U, // VQSHLuiv4i32
+ 164627804U, // VQSHLuiv8i16
+ 165152092U, // VQSHLuiv8i8
+ 165152092U, // VQSHLuv16i8
+ 177735004U, // VQSHLuv1i64
+ 164103516U, // VQSHLuv2i32
+ 177735004U, // VQSHLuv2i64
+ 164627804U, // VQSHLuv4i16
+ 164103516U, // VQSHLuv4i32
+ 164627804U, // VQSHLuv8i16
+ 165152092U, // VQSHLuv8i8
+ 177210729U, // VQSHRNsv2i32
+ 162530665U, // VQSHRNsv4i16
+ 163054953U, // VQSHRNsv8i8
+ 177735017U, // VQSHRNuv2i32
+ 164103529U, // VQSHRNuv4i16
+ 164627817U, // VQSHRNuv8i8
+ 177210736U, // VQSHRUNv2i32
+ 162530672U, // VQSHRUNv4i16
+ 163054960U, // VQSHRUNv8i8
+ 163579256U, // VQSUBsv16i8
+ 177210744U, // VQSUBsv1i64
+ 162530680U, // VQSUBsv2i32
+ 177210744U, // VQSUBsv2i64
+ 163054968U, // VQSUBsv4i16
+ 162530680U, // VQSUBsv4i32
+ 163054968U, // VQSUBsv8i16
+ 163579256U, // VQSUBsv8i8
+ 165152120U, // VQSUBuv16i8
+ 177735032U, // VQSUBuv1i64
+ 164103544U, // VQSUBuv2i32
+ 177735032U, // VQSUBuv2i64
+ 164627832U, // VQSUBuv4i16
+ 164103544U, // VQSUBuv4i32
+ 164627832U, // VQSUBuv8i16
+ 165152120U, // VQSUBuv8i8
+ 165676414U, // VRADDHNv2i32
+ 166200702U, // VRADDHNv4i16
+ 166724990U, // VRADDHNv8i8
+ 768083334U, // VRECPEd
+ 756123014U, // VRECPEfd
+ 756123014U, // VRECPEfq
+ 768083334U, // VRECPEq
+ 152143245U, // VRECPSfd
+ 152143245U, // VRECPSfq
+ 771802516U, // VREV16d8
+ 771802516U, // VREV16q8
+ 776521115U, // VREV32d16
+ 771802523U, // VREV32d8
+ 776521115U, // VREV32q16
+ 771802523U, // VREV32q8
+ 776521122U, // VREV64d16
+ 777045410U, // VREV64d32
+ 771802530U, // VREV64d8
+ 777045410U, // VREV64df
+ 776521122U, // VREV64q16
+ 777045410U, // VREV64q32
+ 771802530U, // VREV64q8
+ 777045410U, // VREV64qf
+ 163579305U, // VRHADDsv16i8
+ 162530729U, // VRHADDsv2i32
+ 163055017U, // VRHADDsv4i16
+ 162530729U, // VRHADDsv4i32
+ 163055017U, // VRHADDsv8i16
+ 163579305U, // VRHADDsv8i8
+ 165152169U, // VRHADDuv16i8
+ 164103593U, // VRHADDuv2i32
+ 164627881U, // VRHADDuv4i16
+ 164103593U, // VRHADDuv4i32
+ 164627881U, // VRHADDuv8i16
+ 165152169U, // VRHADDuv8i8
+ 163579312U, // VRSHLsv16i8
+ 177210800U, // VRSHLsv1i64
+ 162530736U, // VRSHLsv2i32
+ 177210800U, // VRSHLsv2i64
+ 163055024U, // VRSHLsv4i16
+ 162530736U, // VRSHLsv4i32
+ 163055024U, // VRSHLsv8i16
+ 163579312U, // VRSHLsv8i8
+ 165152176U, // VRSHLuv16i8
+ 177735088U, // VRSHLuv1i64
+ 164103600U, // VRSHLuv2i32
+ 177735088U, // VRSHLuv2i64
+ 164627888U, // VRSHLuv4i16
+ 164103600U, // VRSHLuv4i32
+ 164627888U, // VRSHLuv8i16
+ 165152176U, // VRSHLuv8i8
+ 165676470U, // VRSHRNv2i32
+ 166200758U, // VRSHRNv4i16
+ 166725046U, // VRSHRNv8i8
+ 163579325U, // VRSHRsv16i8
+ 177210813U, // VRSHRsv1i64
+ 162530749U, // VRSHRsv2i32
+ 177210813U, // VRSHRsv2i64
+ 163055037U, // VRSHRsv4i16
+ 162530749U, // VRSHRsv4i32
+ 163055037U, // VRSHRsv8i16
+ 163579325U, // VRSHRsv8i8
+ 165152189U, // VRSHRuv16i8
+ 177735101U, // VRSHRuv1i64
+ 164103613U, // VRSHRuv2i32
+ 177735101U, // VRSHRuv2i64
+ 164627901U, // VRSHRuv4i16
+ 164103613U, // VRSHRuv4i32
+ 164627901U, // VRSHRuv8i16
+ 165152189U, // VRSHRuv8i8
+ 768083395U, // VRSQRTEd
+ 756123075U, // VRSQRTEfd
+ 756123075U, // VRSQRTEfq
+ 768083395U, // VRSQRTEq
+ 152143307U, // VRSQRTSfd
+ 152143307U, // VRSQRTSfq
+ 834700755U, // VRSRAsv16i8
+ 848332243U, // VRSRAsv1i64
+ 833652179U, // VRSRAsv2i32
+ 848332243U, // VRSRAsv2i64
+ 834176467U, // VRSRAsv4i16
+ 833652179U, // VRSRAsv4i32
+ 834176467U, // VRSRAsv8i16
+ 834700755U, // VRSRAsv8i8
+ 836273619U, // VRSRAuv16i8
+ 848856531U, // VRSRAuv1i64
+ 835225043U, // VRSRAuv2i32
+ 848856531U, // VRSRAuv2i64
+ 835749331U, // VRSRAuv4i16
+ 835225043U, // VRSRAuv4i32
+ 835749331U, // VRSRAuv8i16
+ 836273619U, // VRSRAuv8i8
+ 165676505U, // VRSUBHNv2i32
+ 166200793U, // VRSUBHNv4i16
+ 166725081U, // VRSUBHNv8i8
+ 843628736U, // VSETLNi16
+ 844153024U, // VSETLNi32
+ 838910144U, // VSETLNi8
+ 166725089U, // VSHLLi16
+ 166200801U, // VSHLLi32
+ 167249377U, // VSHLLi8
+ 162530785U, // VSHLLsv2i64
+ 163055073U, // VSHLLsv4i32
+ 163579361U, // VSHLLsv8i16
+ 164103649U, // VSHLLuv2i64
+ 164627937U, // VSHLLuv4i32
+ 165152225U, // VSHLLuv8i16
+ 167249383U, // VSHLiv16i8
+ 165676519U, // VSHLiv1i64
+ 166200807U, // VSHLiv2i32
+ 165676519U, // VSHLiv2i64
+ 166725095U, // VSHLiv4i16
+ 166200807U, // VSHLiv4i32
+ 166725095U, // VSHLiv8i16
+ 167249383U, // VSHLiv8i8
+ 163579367U, // VSHLsv16i8
+ 177210855U, // VSHLsv1i64
+ 162530791U, // VSHLsv2i32
+ 177210855U, // VSHLsv2i64
+ 163055079U, // VSHLsv4i16
+ 162530791U, // VSHLsv4i32
+ 163055079U, // VSHLsv8i16
+ 163579367U, // VSHLsv8i8
+ 165152231U, // VSHLuv16i8
+ 177735143U, // VSHLuv1i64
+ 164103655U, // VSHLuv2i32
+ 177735143U, // VSHLuv2i64
+ 164627943U, // VSHLuv4i16
+ 164103655U, // VSHLuv4i32
+ 164627943U, // VSHLuv8i16
+ 165152231U, // VSHLuv8i8
+ 165676524U, // VSHRNv2i32
+ 166200812U, // VSHRNv4i16
+ 166725100U, // VSHRNv8i8
+ 163579378U, // VSHRsv16i8
+ 177210866U, // VSHRsv1i64
+ 162530802U, // VSHRsv2i32
+ 177210866U, // VSHRsv2i64
+ 163055090U, // VSHRsv4i16
+ 162530802U, // VSHRsv4i32
+ 163055090U, // VSHRsv8i16
+ 163579378U, // VSHRsv8i8
+ 165152242U, // VSHRuv16i8
+ 177735154U, // VSHRuv1i64
+ 164103666U, // VSHRuv2i32
+ 177735154U, // VSHRuv2i64
+ 164627954U, // VSHRuv4i16
+ 164103666U, // VSHRuv4i32
+ 164627954U, // VSHRuv8i16
+ 165152242U, // VSHRuv8i8
+ 178258984U, // VSHTOD
+ 178783272U, // VSHTOS
+ 783467560U, // VSITOD
+ 775603240U, // VSITOS
+ 838911479U, // VSLIv16i8
+ 846775799U, // VSLIv1i64
+ 844154359U, // VSLIv2i32
+ 846775799U, // VSLIv2i64
+ 843630071U, // VSLIv4i16
+ 844154359U, // VSLIv4i32
+ 843630071U, // VSLIv8i16
+ 838911479U, // VSLIv8i8
+ 179405864U, // VSLTOD
+ 171541544U, // VSLTOS
+ 755598844U, // VSQRTD
+ 756123132U, // VSQRTS
+ 834700802U, // VSRAsv16i8
+ 848332290U, // VSRAsv1i64
+ 833652226U, // VSRAsv2i32
+ 848332290U, // VSRAsv2i64
+ 834176514U, // VSRAsv4i16
+ 833652226U, // VSRAsv4i32
+ 834176514U, // VSRAsv8i16
+ 834700802U, // VSRAsv8i8
+ 836273666U, // VSRAuv16i8
+ 848856578U, // VSRAuv1i64
+ 835225090U, // VSRAuv2i32
+ 848856578U, // VSRAuv2i64
+ 835749378U, // VSRAuv4i16
+ 835225090U, // VSRAuv4i32
+ 835749378U, // VSRAuv8i16
+ 836273666U, // VSRAuv8i8
+ 838911495U, // VSRIv16i8
+ 846775815U, // VSRIv1i64
+ 844154375U, // VSRIv2i32
+ 846775815U, // VSRIv2i64
+ 843630087U, // VSRIv4i16
+ 844154375U, // VSRIv4i32
+ 843630087U, // VSRIv8i16
+ 838911495U, // VSRIv8i8
+ 240944652U, // VST1d16
+ 241468940U, // VST1d32
+ 241993228U, // VST1d64
+ 242517516U, // VST1d8
+ 241468940U, // VST1df
+ 239912460U, // VST1q16
+ 240436748U, // VST1q32
+ 243058188U, // VST1q64
+ 235193868U, // VST1q8
+ 240436748U, // VST1qf
+ 1516013073U, // VST2LNd16
+ 1516537361U, // VST2LNd32
+ 1517585937U, // VST2LNd8
+ 1516013073U, // VST2LNq16a
+ 1516013073U, // VST2LNq16b
+ 1516537361U, // VST2LNq32a
+ 1516537361U, // VST2LNq32b
+ 643597841U, // VST2d16
+ 644122129U, // VST2d32
+ 644646412U, // VST2d64
+ 645170705U, // VST2d8
+ 1381795345U, // VST2q16
+ 1382319633U, // VST2q32
+ 1383368209U, // VST2q8
+ 1381795350U, // VST3LNd16
+ 1382319638U, // VST3LNd32
+ 1383368214U, // VST3LNd8
+ 1381795350U, // VST3LNq16a
+ 1381795350U, // VST3LNq16b
+ 1382319638U, // VST3LNq32a
+ 1382319638U, // VST3LNq32b
+ 1516013078U, // VST3d16
+ 1516537366U, // VST3d32
+ 1517061644U, // VST3d64
+ 1517585942U, // VST3d8
+ 1381828118U, // VST3q16a
+ 1381828118U, // VST3q16b
+ 1382352406U, // VST3q32a
+ 1382352406U, // VST3q32b
+ 1383400982U, // VST3q8a
+ 1383400982U, // VST3q8b
+ 1314686491U, // VST4LNd16
+ 1315210779U, // VST4LNd32
+ 1316259355U, // VST4LNd8
+ 1314686491U, // VST4LNq16a
+ 1314686491U, // VST4LNq16b
+ 1315210779U, // VST4LNq32a
+ 1315210779U, // VST4LNq32b
+ 1381795355U, // VST4d16
+ 1382319643U, // VST4d32
+ 1382843916U, // VST4d64
+ 1383368219U, // VST4d8
+ 1314719259U, // VST4q16a
+ 1314719259U, // VST4q16b
+ 1315243547U, // VST4q32a
+ 1315243547U, // VST4q32b
+ 1316292123U, // VST4q8a
+ 1316292123U, // VST4q8b
+ 1610614304U, // VSTMD
+ 1610614304U, // VSTMS
+ 175687205U, // VSTRD
+ 136005162U, // VSTRQ
+ 173065765U, // VSTRS
+ 151619121U, // VSUBD
+ 165676598U, // VSUBHNv2i32
+ 166200886U, // VSUBHNv4i16
+ 166725174U, // VSUBHNv8i8
+ 162530877U, // VSUBLsv2i64
+ 163055165U, // VSUBLsv4i32
+ 163579453U, // VSUBLsv8i16
+ 164103741U, // VSUBLuv2i64
+ 164628029U, // VSUBLuv4i32
+ 165152317U, // VSUBLuv8i16
+ 152143409U, // VSUBS
+ 162530883U, // VSUBWsv2i64
+ 163055171U, // VSUBWsv4i32
+ 163579459U, // VSUBWsv8i16
+ 164103747U, // VSUBWuv2i64
+ 164628035U, // VSUBWuv4i32
+ 165152323U, // VSUBWuv8i16
+ 152143409U, // VSUBfd
+ 152143409U, // VSUBfd_sfp
+ 152143409U, // VSUBfq
+ 167249457U, // VSUBv16i8
+ 165676593U, // VSUBv1i64
+ 166200881U, // VSUBv2i32
+ 165676593U, // VSUBv2i64
+ 166725169U, // VSUBv4i16
+ 166200881U, // VSUBv4i32
+ 166725169U, // VSUBv8i16
+ 167249457U, // VSUBv8i8
+ 167822921U, // VTBL1
+ 838911561U, // VTBL2
+ 234931785U, // VTBL3
+ 637584969U, // VTBL4
+ 838911566U, // VTBX1
+ 234931790U, // VTBX2
+ 637584974U, // VTBX3
+ 1510000206U, // VTBX4
+ 179831848U, // VTOSHD
+ 180356136U, // VTOSHS
+ 785040979U, // VTOSIRD
+ 774555219U, // VTOSIRS
+ 785040424U, // VTOSIZD
+ 774554664U, // VTOSIZS
+ 180978728U, // VTOSLD
+ 170492968U, // VTOSLS
+ 181404712U, // VTOUHD
+ 181929000U, // VTOUHS
+ 786613843U, // VTOUIRD
+ 775079507U, // VTOUIRS
+ 786613288U, // VTOUIZD
+ 775078952U, // VTOUIZS
+ 182551592U, // VTOULD
+ 171017256U, // VTOULS
+ 843630169U, // VTRNd16
+ 844154457U, // VTRNd32
+ 838911577U, // VTRNd8
+ 843630169U, // VTRNq16
+ 844154457U, // VTRNq32
+ 838911577U, // VTRNq8
+ 167822942U, // VTSTv16i8
+ 173065822U, // VTSTv2i32
+ 172541534U, // VTSTv4i16
+ 173065822U, // VTSTv4i32
+ 172541534U, // VTSTv8i16
+ 167822942U, // VTSTv8i8
+ 182977576U, // VUHTOD
+ 183501864U, // VUHTOS
+ 788186152U, // VUITOD
+ 776127528U, // VUITOS
+ 184124456U, // VULTOD
+ 172065832U, // VULTOS
+ 843630179U, // VUZPd16
+ 844154467U, // VUZPd32
+ 838911587U, // VUZPd8
+ 843630179U, // VUZPq16
+ 844154467U, // VUZPq32
+ 838911587U, // VUZPq8
+ 843630184U, // VZIPd16
+ 844154472U, // VZIPd32
+ 838911592U, // VZIPd8
+ 843630184U, // VZIPq16
+ 844154472U, // VZIPq32
+ 838911592U, // VZIPq8
+ 538969709U, // WFE
+ 538969713U, // WFI
+ 538969717U, // YIELD
+ 67108875U, // t2ADCSri
+ 67110523U, // t2ADCSrr
+ 67110523U, // t2ADCSrs
+ 1679343633U, // t2ADCri
+ 1728151569U, // t2ADCrr
+ 1795260433U, // t2ADCrs
+ 184647701U, // t2ADDSri
+ 184647701U, // t2ADDSrr
+ 855736341U, // t2ADDSrs
+ 1728151578U, // t2ADDrSPi
+ 135841411U, // t2ADDrSPi12
+ 1795260442U, // t2ADDrSPs
+ 1728151578U, // t2ADDri
+ 1679345283U, // t2ADDri12
+ 1728151578U, // t2ADDrr
+ 1795260442U, // t2ADDrs
+ 1679343684U, // t2ANDri
+ 1728151620U, // t2ANDrr
+ 1795260484U, // t2ANDrs
+ 1728153224U, // t2ASRri
+ 1728153224U, // t2ASRrr
+ 69207692U, // t2B
+ 135839820U, // t2BFC
+ 806930065U, // t2BFI
+ 1679343696U, // t2BICri
+ 1728151632U, // t2BICrr
+ 1795260496U, // t2BICrs
+ 117964923U, // t2BR_JT
+ 386056347U, // t2Bcc
+ 739819688U, // t2CLZ
+ 788627628U, // t2CMNzri
+ 788627628U, // t2CMNzrr
+ 184647852U, // t2CMNzrs
+ 788627632U, // t2CMPri
+ 788627632U, // t2CMPrr
+ 184647856U, // t2CMPrs
+ 788627632U, // t2CMPzri
+ 788627632U, // t2CMPzrr
+ 184647856U, // t2CMPzrs
+ 1679343804U, // t2EORri
+ 1728151740U, // t2EORrr
+ 1795260604U, // t2EORrs
+ 1811941013U, // t2IT
+ 215U, // t2Int_MemBarrierV7
+ 219U, // t2Int_SyncBarrierV7
+ 1879049880U, // t2Int_eh_sjlj_setjmp
+ 1058013417U, // t2LDM
+ 1058013417U, // t2LDM_RET
+ 806928625U, // t2LDRB_POST
+ 806928625U, // t2LDRB_PRE
+ 184647921U, // t2LDRBi12
+ 135839985U, // t2LDRBi8
+ 788627697U, // t2LDRBpci
+ 855736561U, // t2LDRBs
+ 806928630U, // t2LDRDi8
+ 135839990U, // t2LDRDpci
+ 739819771U, // t2LDREX
+ 739819777U, // t2LDREXB
+ 135840008U, // t2LDREXD
+ 739819791U, // t2LDREXH
+ 806928662U, // t2LDRH_POST
+ 806928662U, // t2LDRH_PRE
+ 184647958U, // t2LDRHi12
+ 135840022U, // t2LDRHi8
+ 788627734U, // t2LDRHpci
+ 855736598U, // t2LDRHs
+ 806928667U, // t2LDRSB_POST
+ 806928667U, // t2LDRSB_PRE
+ 184647963U, // t2LDRSBi12
+ 135840027U, // t2LDRSBi8
+ 788627739U, // t2LDRSBpci
+ 855736603U, // t2LDRSBs
+ 806928673U, // t2LDRSH_POST
+ 806928673U, // t2LDRSH_PRE
+ 184647969U, // t2LDRSHi12
+ 135840033U, // t2LDRSHi8
+ 788627745U, // t2LDRSHpci
+ 855736609U, // t2LDRSHs
+ 806928621U, // t2LDR_POST
+ 806928621U, // t2LDR_PRE
+ 184647917U, // t2LDRi12
+ 135839981U, // t2LDRi8
+ 788627693U, // t2LDRpci
+ 67110557U, // t2LDRpci_pic
+ 855736557U, // t2LDRs
+ 788874918U, // t2LEApcrel
+ 184895142U, // t2LEApcrelJT
+ 1728153258U, // t2LSLri
+ 1728153258U, // t2LSLrr
+ 1728153262U, // t2LSRri
+ 1728153262U, // t2LSRrr
+ 806928714U, // t2MLA
+ 806928718U, // t2MLS
+ 855737992U, // t2MOVCCasr
+ 184648018U, // t2MOVCCi
+ 855738026U, // t2MOVCClsl
+ 855738030U, // t2MOVCClsr
+ 184648018U, // t2MOVCCr
+ 855738034U, // t2MOVCCror
+ 135840086U, // t2MOVTi16
+ 1998422354U, // t2MOVi
+ 739819867U, // t2MOVi16
+ 739819867U, // t2MOVi32imm
+ 1998422354U, // t2MOVr
+ 1998440118U, // t2MOVrx
+ 67110586U, // t2MOVsra_flag
+ 67110594U, // t2MOVsrl_flag
+ 135840129U, // t2MUL
+ 1998438789U, // t2MVNi
+ 788627845U, // t2MVNr
+ 184648069U, // t2MVNs
+ 1679345354U, // t2ORNri
+ 1679345354U, // t2ORNrr
+ 1746454218U, // t2ORNrs
+ 1679344013U, // t2ORRri
+ 1728151949U, // t2ORRrr
+ 1795260813U, // t2ORRrs
+ 806928787U, // t2PKHBT
+ 806928793U, // t2PKHTB
+ 739819993U, // t2RBIT
+ 788627934U, // t2REV
+ 788627938U, // t2REV16
+ 788627944U, // t2REVSH
+ 1728153266U, // t2RORri
+ 1728153266U, // t2RORrr
+ 2013266419U, // t2RSBSri
+ 1947779571U, // t2RSBSrs
+ 184648179U, // t2RSBri
+ 806928883U, // t2RSBrs
+ 67109377U, // t2SBCSri
+ 67110606U, // t2SBCSrr
+ 67110606U, // t2SBCSrs
+ 1679344135U, // t2SBCri
+ 1728152071U, // t2SBCrr
+ 1795260935U, // t2SBCrs
+ 806928907U, // t2SBFX
+ 806928936U, // t2SMLABB
+ 806928943U, // t2SMLABT
+ 806928950U, // t2SMLAL
+ 806928988U, // t2SMLATB
+ 806928995U, // t2SMLATT
+ 806929002U, // t2SMLAWB
+ 806929009U, // t2SMLAWT
+ 806929016U, // t2SMMLA
+ 806929022U, // t2SMMLS
+ 135840388U, // t2SMMUL
+ 135840394U, // t2SMULBB
+ 135840401U, // t2SMULBT
+ 806929048U, // t2SMULL
+ 135840414U, // t2SMULTB
+ 135840421U, // t2SMULTT
+ 135840428U, // t2SMULWB
+ 135840435U, // t2SMULWT
+ 1058013882U, // t2STM
+ 806879938U, // t2STRB_POST
+ 806879938U, // t2STRB_PRE
+ 184648386U, // t2STRBi12
+ 135840450U, // t2STRBi8
+ 855737026U, // t2STRBs
+ 806929101U, // t2STRDi8
+ 135840466U, // t2STREX
+ 135840472U, // t2STREXB
+ 806929119U, // t2STREXD
+ 135840486U, // t2STREXH
+ 806879981U, // t2STRH_POST
+ 806879981U, // t2STRH_PRE
+ 184648429U, // t2STRHi12
+ 135840493U, // t2STRHi8
+ 855737069U, // t2STRHs
+ 806879934U, // t2STR_POST
+ 806879934U, // t2STR_PRE
+ 184648382U, // t2STRi12
+ 135840446U, // t2STRi8
+ 855737022U, // t2STRs
+ 184648439U, // t2SUBSri
+ 184648439U, // t2SUBSrr
+ 855737079U, // t2SUBSrs
+ 1728152316U, // t2SUBrSPi
+ 135841494U, // t2SUBrSPi12
+ 67110619U, // t2SUBrSPi12_
+ 67110627U, // t2SUBrSPi_
+ 1746453244U, // t2SUBrSPs
+ 67110636U, // t2SUBrSPs_
+ 1728152316U, // t2SUBri
+ 1679345366U, // t2SUBri12
+ 1728152316U, // t2SUBrr
+ 1795261180U, // t2SUBrs
+ 135840525U, // t2SXTABrr
+ 806929165U, // t2SXTABrr_rot
+ 135840531U, // t2SXTAHrr
+ 806929171U, // t2SXTAHrr_rot
+ 788628249U, // t2SXTBr
+ 184648473U, // t2SXTBr_rot
+ 788628254U, // t2SXTHr
+ 184648478U, // t2SXTHr_rot
+ 2080376563U, // t2TBB
+ 2080376568U, // t2TBH
+ 788628259U, // t2TEQri
+ 788628259U, // t2TEQrr
+ 184648483U, // t2TEQrs
+ 807U, // t2TPsoft
+ 788628287U, // t2TSTri
+ 788628287U, // t2TSTrr
+ 184648511U, // t2TSTrs
+ 806929219U, // t2UBFX
+ 806929224U, // t2UMAAL
+ 806929230U, // t2UMLAL
+ 806929236U, // t2UMULL
+ 135840644U, // t2UXTABrr
+ 806929284U, // t2UXTABrr_rot
+ 135840650U, // t2UXTAHrr
+ 806929290U, // t2UXTAHrr_rot
+ 788628368U, // t2UXTB16r
+ 184648592U, // t2UXTB16r_rot
+ 788628375U, // t2UXTBr
+ 184648599U, // t2UXTBr_rot
+ 788628380U, // t2UXTHr
+ 184648604U, // t2UXTHr_rot
+ 2200305681U, // tADC
+ 135839770U, // tADDhirr
+ 2199945242U, // tADDi3
+ 2200305690U, // tADDi8
+ 120063741U, // tADDrPCi
+ 67143421U, // tADDrSP
+ 67110653U, // tADDrSPi
+ 2199945242U, // tADDrr
+ 67520253U, // tADDspi
+ 67143421U, // tADDspr
+ 67143426U, // tADDspr_
+ 69207817U, // tADJCALLSTACKDOWN
+ 69207838U, // tADJCALLSTACKUP
+ 2200305732U, // tAND
+ 67143473U, // tANDsp
+ 2199946888U, // tASRri
+ 2200307336U, // tASRrr
+ 69206089U, // tB
+ 2200305744U, // tBIC
+ 69207864U, // tBKPT
+ 402653273U, // tBL
+ 402653277U, // tBLXi
+ 402653277U, // tBLXi_r9
+ 69206109U, // tBLXr
+ 69206109U, // tBLXr_r9
+ 402653273U, // tBLr9
+ 69206139U, // tBRIND
+ 120586363U, // tBR_JTr
+ 69206148U, // tBX
+ 1854U, // tBX_RET
+ 69206117U, // tBX_RET_vararg
+ 69206148U, // tBXr9
+ 337166491U, // tBcc
+ 121110617U, // tBfar
+ 67110724U, // tCBNZ
+ 67110730U, // tCBZ
+ 739819692U, // tCMNz
+ 739819696U, // tCMPhir
+ 739819696U, // tCMPi8
+ 739819696U, // tCMPr
+ 739819696U, // tCMPzhir
+ 739819696U, // tCMPzi8
+ 739819696U, // tCMPzr
+ 2200305852U, // tEOR
+ 1879049880U, // tInt_eh_sjlj_setjmp
+ 1008320745U, // tLDM
+ 806928621U, // tLDR
+ 806928625U, // tLDRB
+ 806928625U, // tLDRBi
+ 806928662U, // tLDRH
+ 806928662U, // tLDRHi
+ 135840027U, // tLDRSB
+ 135840033U, // tLDRSH
+ 739819757U, // tLDRcp
+ 806928621U, // tLDRi
+ 792723693U, // tLDRpci
+ 67110735U, // tLDRpci_pic
+ 135839981U, // tLDRspi
+ 739821222U, // tLEApcrel
+ 135841446U, // tLEApcrelJT
+ 2199946922U, // tLSLri
+ 2200307370U, // tLSLrr
+ 2199946926U, // tLSRri
+ 2200307374U, // tLSRrr
+ 135840082U, // tMOVCCi
+ 135840082U, // tMOVCCr
+ 136316760U, // tMOVCCr_pseudo
+ 67110755U, // tMOVSr
+ 67110761U, // tMOVgpr2gpr
+ 67110761U, // tMOVgpr2tgpr
+ 2202714450U, // tMOVi8
+ 67110761U, // tMOVr
+ 67110761U, // tMOVtgpr2gpr
+ 2200306049U, // tMUL
+ 2202714501U, // tMVN
+ 2200306061U, // tORR
+ 1196425617U, // tPICADD
+ 538871662U, // tPOP
+ 538871662U, // tPOP_RET
+ 538871666U, // tPUSH
+ 739819998U, // tREV
+ 739820002U, // tREV16
+ 739820008U, // tREVSH
+ 2200307378U, // tROR
+ 2202698227U, // tRSB
+ 135839981U, // tRestore
+ 2200306183U, // tSBC
+ 1008321210U, // tSTM
+ 806929086U, // tSTR
+ 806929090U, // tSTRB
+ 806929090U, // tSTRBi
+ 806929133U, // tSTRH
+ 806929133U, // tSTRHi
+ 806929086U, // tSTRi
+ 135840446U, // tSTRspi
+ 2199945980U, // tSUBi3
+ 2200306428U, // tSUBi8
+ 2199945980U, // tSUBrr
+ 67520375U, // tSUBspi
+ 67520236U, // tSUBspi_
+ 739820313U, // tSXTB
+ 739820318U, // tSXTH
+ 135840446U, // tSpill
+ 807U, // tTPsoft
+ 739820351U, // tTST
+ 739820439U, // tUXTB
+ 739820444U, // tUXTH
0U
};
const char *AsmStrs =
- "DEBUG_VALUE\000adcs\t\000adc\000adds\000add\000@ ADJCALLSTACKDOWN \000@"
- " ADJCALLSTACKUP \000and\000\000b\t\000bfc\000bic\000bl\t\000blx\t\000bl"
- "\000bx\t\000add\tpc, \000ldr\tpc, \000mov\tpc, \000mov\tlr, pc\n\tbx\t\000"
- "bx\000b\000clz\000cmn\000cmp\000eor\000vmov\000vmrs\000mcr\tp15, 0, \000"
- "dmb\000dsb\000str\tsp, [\000ldm\000ldr\000ldrb\000ldrd\000ldrex\000ldre"
- "xb\000ldrexd\000ldrexh\000ldrh\000ldrsb\000ldrsh\000.set \000mla\000mls"
- "\000mov\000movt\000movw\000movs\000mul\000mvn\000orr\000\n\000pkhbt\000"
- "pkhtb\000rbit\000rev\000rev16\000revsh\000rsbs\000rsb\000rscs\t\000rsc\000"
- "sbcs\t\000sbc\000sbfx\000smlabb\000smlabt\000smlal\000smlatb\000smlatt\000"
- "smlawb\000smlawt\000smmla\000smmls\000smmul\000smulbb\000smulbt\000smul"
- "l\000smultb\000smultt\000smulwb\000smulwt\000stm\000str\000strb\000strd"
- "\000strex\000strexb\000strexd\000strexh\000strh\000subs\000sub\000sxtab"
- "\000sxtah\000sxtb\000sxth\000teq\000bl\t__aeabi_read_tp\000tst\000ubfx\000"
- "umaal\000umlal\000umull\000uxtab\000uxtah\000uxtb16\000uxtb\000uxth\000"
- "vabal\000vaba\000vabdl\000vabd\000vabs\000vacge\000vacgt\000vadd\000vad"
- "dhn\000vaddl\000vaddw\000vand\000vbic\000vbsl\000vceq\000vcge\000vcgt\000"
- "vcls\000vclz\000vcmpe\000vcnt\000vcvt\000vdiv\000vdup\000veor\000vext\000"
- "vhadd\000vhsub\000vld1\000vld2\000vld3\000vld4\000vldm\000vldr\000vldmi"
- "a\000vmax\000vmin\000vmla\000vmlal\000vmls\000vmlsl\000vmovl\000vmovn\000"
- "vmul\000vmull\000vmvn\000vneg\000vnmla\000vnmls\000vnmul\000vorn\000vor"
- "r\000vpadal\000vpaddl\000vpadd\000vpmax\000vpmin\000vqabs\000vqadd\000v"
- "qdmlal\000vqdmlsl\000vqdmulh\000vqdmull\000vqmovun\000vqmovn\000vqneg\000"
- "vqrdmulh\000vqrshl\000vqrshrn\000vqrshrun\000vqshl\000vqshlu\000vqshrn\000"
- "vqshrun\000vqsub\000vraddhn\000vrecpe\000vrecps\000vrev16\000vrev32\000"
- "vrev64\000vrhadd\000vrshl\000vrshrn\000vrshr\000vrsqrte\000vrsqrts\000v"
- "rsra\000vrsubhn\000vshll\000vshl\000vshrn\000vshr\000vsli\000vsqrt\000v"
- "sra\000vsri\000vst1\000vst2\000vst3\000vst4\000vstm\000vstr\000vstmia\000"
- "vsub\000vsubhn\000vsubl\000vsubw\000vtbl\000vtbx\000vtrn\000vtst\000vuz"
- "p\000vzip\000adcs.w\t\000addw\000asr\000b.w\t\000it\000str.w\tsp, [\000"
- "@ ldr.w\t\000adr\000lsl\000lsr\000ror\000rrx\000asrs.w\t\000lsrs.w\t\000"
- "orn\000sbcs.w\t\000subw\000@ subw\t\000@ sub.w\t\000@ sub\t\000tbb\t\000"
- "tbh\t\000add\t\000@ add\t\000@ tADJCALLSTACKDOWN \000@ tADJCALLSTACKUP "
- "\000@ and\t\000bx\tlr\000cbnz\t\000cbz\t\000mov\tr12, r1\t@ begin eh.se"
- "tjmp\n\tmov\tr1, sp\n\tstr\tr1, [\000@ ldr.n\t\000@ tMOVCCr \000movs\t\000"
- "mov\t\000pop\000push\000sub\t\000";
+ "DBG_VALUE\000adcs\t\000adc\000adds\000add\000@ ADJCALLSTACKDOWN \000@ A"
+ "DJCALLSTACKUP \000and\000\000b\t\000bfc\000bic\000bkpt\000bl\t\000blx\t"
+ "\000bl\000bx\t\000add\tpc, \000ldr\tpc, \000mov\tpc, \000mov\tlr, pc\n\t"
+ "bx\t\000bxj\000bx\000b\000cdp\000cdp2\tp\000clz\000cmn\000cmp\000cps\000"
+ "dbg\000eor\000vmov\000vmrs\000mcr\tp15, 0, \000dmb\000dsb\000str\tsp, ["
+ "\000ldm\000ldr\000ldrb\000ldrd\000ldrex\000ldrexb\000ldrexd\000ldrexh\000"
+ "ldrh\000ldrsb\000ldrsh\000ldrt\000.set \000mcr\000mcr2\tp\000mcrr\000mc"
+ "rr2\tp\000mla\000mls\000mov\000movt\000movw\000movs\000mrc\000mrc2\tp\000"
+ "mrrc\000mrrc2\tp\000mrs\000mul\000mvn\000nop\000orr\000\n\000pkhbt\000p"
+ "khtb\000qadd\000qadd16\000qadd8\000qasx\000qdadd\000qdsub\000qsax\000qs"
+ "ub\000qsub16\000qsub8\000rbit\000rev\000rev16\000revsh\000rsbs\000rsb\000"
+ "rscs\t\000rsc\000sbcs\t\000sbc\000sbfx\000setend\tbe\000setend\tle\000s"
+ "ev\000smlabb\000smlabt\000smlal\000smlalbb\000smlalbt\000smlaltb\000sml"
+ "altt\000smlatb\000smlatt\000smlawb\000smlawt\000smmla\000smmls\000smmul"
+ "\000smulbb\000smulbt\000smull\000smultb\000smultt\000smulwb\000smulwt\000"
+ "stm\000str\000strb\000strbt\000strd\000strex\000strexb\000strexd\000str"
+ "exh\000strh\000strt\000subs\000sub\000svc\000swp\000swpb\000sxtab\000sx"
+ "tah\000sxtb\000sxth\000teq\000bl\t__aeabi_read_tp\000trap\000tst\000ubf"
+ "x\000umaal\000umlal\000umull\000uqadd16\000uqadd8\000uqasx\000uqsax\000"
+ "uqsub16\000uqsub8\000uxtab\000uxtah\000uxtb16\000uxtb\000uxth\000vabal\000"
+ "vaba\000vabdl\000vabd\000vabs\000vacge\000vacgt\000vadd\000vaddhn\000va"
+ "ddl\000vaddw\000vand\000vbic\000vbif\000vbit\000vbsl\000vceq\000vcge\000"
+ "vcgt\000vcls\000vclz\000vcmp\000vcmpe\000vcnt\000vcvtb\000vcvt\000vcvtt"
+ "\000vdiv\000vdup\000veor\000vext\000vhadd\000vhsub\000vld1\000vld2\000v"
+ "ld3\000vld4\000vldm\000vldr\000vldmia\000vmax\000vmin\000vmla\000vmlal\000"
+ "vmls\000vmlsl\000vmovl\000vmovn\000vmsr\000vmul\000vmull\000vmvn\000vne"
+ "g\000vnmla\000vnmls\000vnmul\000vorn\000vorr\000vpadal\000vpaddl\000vpa"
+ "dd\000vpmax\000vpmin\000vqabs\000vqadd\000vqdmlal\000vqdmlsl\000vqdmulh"
+ "\000vqdmull\000vqmovun\000vqmovn\000vqneg\000vqrdmulh\000vqrshl\000vqrs"
+ "hrn\000vqrshrun\000vqshl\000vqshlu\000vqshrn\000vqshrun\000vqsub\000vra"
+ "ddhn\000vrecpe\000vrecps\000vrev16\000vrev32\000vrev64\000vrhadd\000vrs"
+ "hl\000vrshrn\000vrshr\000vrsqrte\000vrsqrts\000vrsra\000vrsubhn\000vshl"
+ "l\000vshl\000vshrn\000vshr\000vsli\000vsqrt\000vsra\000vsri\000vst1\000"
+ "vst2\000vst3\000vst4\000vstm\000vstr\000vstmia\000vsub\000vsubhn\000vsu"
+ "bl\000vsubw\000vtbl\000vtbx\000vcvtr\000vtrn\000vtst\000vuzp\000vzip\000"
+ "wfe\000wfi\000yield\000adcs.w\t\000addw\000asr\000b.w\t\000bfi\000it\000"
+ "str\t\000@ ldr.w\t\000adr\000lsl\000lsr\000ror\000rrx\000asrs.w\t\000ls"
+ "rs.w\t\000orn\000sbcs.w\t\000subw\000@ subw\t\000@ sub.w\t\000@ sub\t\000"
+ "tbb\t\000tbh\t\000add\t\000@ add\t\000@ tADJCALLSTACKDOWN \000@ tADJCAL"
+ "LSTACKUP \000@ and\t\000bkpt\t\000bx\tlr\000cbnz\t\000cbz\t\000@ ldr.n\t"
+ "\000@ tMOVCCr \000movs\t\000mov\t\000pop\000push\000sub\t\000";
-
-#ifndef NO_ASM_WRITER_BOILERPLATE
- if (MI->getOpcode() == TargetInstrInfo::INLINEASM) {
- printInlineAsm(MI);
- return;
- } else if (MI->isLabel()) {
- printLabel(MI);
- return;
- } else if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
- printImplicitDef(MI);
- return;
- } else if (MI->getOpcode() == TargetInstrInfo::KILL) {
- printKill(MI);
- return;
- }
-
-
-#endif
O << "\t";
// Emit the opcode for the instruction.
@@ -1596,11 +1675,11 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
O << AsmStrs+(Bits & 2047)-1;
- // Fragment 0 encoded into 5 bits for 30 unique commands.
- switch ((Bits >> 27) & 31) {
+ // Fragment 0 encoded into 6 bits for 33 unique commands.
+ switch ((Bits >> 26) & 63) {
default: // unreachable.
case 0:
- // DEBUG_VALUE, Int_MemBarrierV7, Int_SyncBarrierV7, TPsoft, t2Int_MemBar...
+ // DBG_VALUE, Int_MemBarrierV7, Int_SyncBarrierV7, SETENDBE, SETENDLE, TP...
return;
break;
case 1:
@@ -1612,7 +1691,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printPredicateOperand(MI, 3);
break;
case 3:
- // ADCrs, ADDSrs, ADDrs, ANDrs, BICrs, EORrs, LDRB_POST, LDRB_PRE, LDRD, ...
+ // ADCrs, ADDSrs, ADDrs, ANDrs, BICrs, EORrs, LDRBT, LDRB_POST, LDRB_PRE,...
printPredicateOperand(MI, 5);
break;
case 4:
@@ -1620,14 +1699,14 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
PrintSpecial(MI, "comment");
break;
case 5:
+ // BKPT, BL_pred, BLr9_pred, BXJ, Bcc, DBG, MRS, MRSsys, MSR, MSRsys, SVC...
+ printPredicateOperand(MI, 1);
+ break;
+ case 6:
// BL, BLr9, tBL, tBLXi, tBLXi_r9, tBLr9
printOperand(MI, 0, "call");
return;
break;
- case 6:
- // BL_pred, BLr9_pred, Bcc, VCMPEZD, VCMPEZS, t2Bcc, tBcc
- printPredicateOperand(MI, 1);
- break;
case 7:
// BR_JTm
printAddrMode2Operand(MI, 0);
@@ -1636,30 +1715,45 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
return;
break;
case 8:
- // BX_RET, FMSTAT, tPOP, tPOP_RET, tPUSH
+ // BX_RET, FMSTAT, NOP, SEV, TRAP, WFE, WFI, YIELD, tPOP, tPOP_RET, tPUSH
printPredicateOperand(MI, 0);
break;
case 9:
+ // CDP, MCR, MRC, VLD2d16, VLD2d32, VLD2d64, VLD2d8, VST2d16, VST2d32, VS...
+ printPredicateOperand(MI, 6);
+ break;
+ case 10:
+ // CDP2, MCR2, MCRR2, MRC2, MRRC2
+ printNoHashImmediate(MI, 0);
+ O << ", ";
+ printOperand(MI, 1);
+ break;
+ case 11:
// CLZ, CMNzri, CMNzrr, CMPri, CMPrr, CMPzri, CMPzrr, FCONSTD, FCONSTS, L...
printPredicateOperand(MI, 2);
break;
- case 10:
+ case 12:
// CMNzrs, CMPrs, CMPzrs, LDR, LDRB, LDRH, LDRSB, LDRSH, LDRcp, MLA, MLS,...
printPredicateOperand(MI, 4);
break;
- case 11:
+ case 13:
// CONSTPOOL_ENTRY
printCPInstOperand(MI, 0, "label");
O << ' ';
printCPInstOperand(MI, 1, "cpentry");
return;
break;
- case 12:
+ case 14:
+ // CPS
+ printOperand(MI, 0, "cps");
+ return;
+ break;
+ case 15:
// LDM, LDM_RET, STM, t2LDM, t2LDM_RET, t2STM, tLDM, tSTM
printAddrMode4Operand(MI, 0, "submode");
printPredicateOperand(MI, 2);
break;
- case 13:
+ case 16:
// LEApcrel, LEApcrelJT
PrintSpecial(MI, "private");
O << "PCRELV";
@@ -1667,39 +1761,35 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
O << ", (";
printOperand(MI, 1);
break;
- case 14:
+ case 17:
// PICADD, tPICADD
printPCLabel(MI, 2);
break;
- case 15:
+ case 18:
// PICLDR, PICLDRB, PICLDRH, PICLDRSB, PICLDRSH, PICSTR, PICSTRB, PICSTRH
printAddrModePCOperand(MI, 1, "label");
break;
- case 16:
+ case 19:
// VLD2LNd16, VLD2LNd32, VLD2LNd8, VLD2LNq16a, VLD2LNq16b, VLD2LNq32a, VL...
printPredicateOperand(MI, 9);
break;
- case 17:
- // VLD2d16, VLD2d32, VLD2d64, VLD2d8, VST2d16, VST2d32, VST2d64, VST2d8, ...
- printPredicateOperand(MI, 6);
- break;
- case 18:
+ case 20:
// VLD2q16, VLD2q32, VLD2q8, VLD3q16a, VLD3q16b, VLD3q32a, VLD3q32b, VLD3...
printPredicateOperand(MI, 8);
break;
- case 19:
+ case 21:
// VLD3LNd16, VLD3LNd32, VLD3LNd8, VLD3LNq16a, VLD3LNq16b, VLD3LNq32a, VL...
printPredicateOperand(MI, 11);
break;
- case 20:
+ case 22:
// VLD3d16, VLD3d32, VLD3d64, VLD3d8, VST2LNd16, VST2LNd32, VST2LNd8, VST...
printPredicateOperand(MI, 7);
break;
- case 21:
+ case 23:
// VLD4LNd16, VLD4LNd32, VLD4LNd8, VLD4LNq16a, VLD4LNq16b, VLD4LNq32a, VL...
printPredicateOperand(MI, 13);
break;
- case 22:
+ case 24:
// VLDMD, VLDMS, VSTMD, VSTMS
printAddrMode5Operand(MI, 0, "submode");
printPredicateOperand(MI, 2);
@@ -1709,28 +1799,44 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printRegisterList(MI, 4);
return;
break;
- case 23:
+ case 25:
// t2ADCri, t2ADCrr, t2ADDrSPi, t2ADDri, t2ADDri12, t2ADDrr, t2ANDri, t2A...
printSBitModifierOperand(MI, 5);
printPredicateOperand(MI, 3);
break;
- case 24:
+ case 26:
// t2ADCrs, t2ADDrSPs, t2ADDrs, t2ANDrs, t2BICrs, t2EORrs, t2ORNrs, t2ORR...
printSBitModifierOperand(MI, 6);
printPredicateOperand(MI, 4);
break;
- case 25:
+ case 27:
// t2IT
printThumbITMask(MI, 1);
O << "\t";
printPredicateOperand(MI, 0);
return;
break;
- case 26:
+ case 28:
+ // t2Int_eh_sjlj_setjmp, tInt_eh_sjlj_setjmp
+ printOperand(MI, 1);
+ O << ", [";
+ printOperand(MI, 0);
+ O << ", #8]\t@ begin eh.setjmp\n\tmov\t";
+ printOperand(MI, 1);
+ O << ", pc\n\tadds\t";
+ printOperand(MI, 1);
+ O << ", #9\n\tstr\t";
+ printOperand(MI, 1);
+ O << ", [";
+ printOperand(MI, 0);
+ O << ", #4]\n\tmovs\tr0, #0\n\tb\t1f\n\tmovs\tr0, #1\t@ end eh.setjmp\n1:";
+ return;
+ break;
+ case 29:
// t2MOVi, t2MOVr, t2MOVrx, t2MVNi, t2RSBSrs
printSBitModifierOperand(MI, 4);
break;
- case 27:
+ case 30:
// t2RSBSri
printSBitModifierOperand(MI, 3);
O << ".w\t";
@@ -1741,25 +1847,25 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printOperand(MI, 2);
return;
break;
- case 28:
+ case 31:
// t2TBB, t2TBH
printTBAddrMode(MI, 0);
O << "\n";
printJT2BlockOperand(MI, 1);
return;
break;
- case 29:
+ case 32:
// tADC, tADDi3, tADDi8, tADDrr, tAND, tASRri, tASRrr, tBIC, tEOR, tLSLri...
printSBitModifierOperand(MI, 1);
break;
}
- // Fragment 1 encoded into 7 bits for 94 unique commands.
- switch ((Bits >> 20) & 127) {
+ // Fragment 1 encoded into 7 bits for 107 unique commands.
+ switch ((Bits >> 19) & 127) {
default: // unreachable.
case 0:
- // ADCSSri, ADCSSrr, ADCSSrs, BR_JTadd, RSCSri, RSCSrs, SBCSSri, SBCSSrr,...
+ // ADCSSri, ADCSSrr, ADCSSrs, BR_JTadd, MCR2, MCRR2, MRC2, MRRC2, RSCSri,...
O << ", ";
break;
case 1:
@@ -1783,11 +1889,11 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
return;
break;
case 3:
- // ADDSri, ADDSrr, ADDSrs, BFC, BL_pred, BLr9_pred, Bcc, CLZ, CMNzri, CMN...
+ // ADDSri, ADDSrr, ADDSrs, BFC, BKPT, BL_pred, BLr9_pred, BXJ, Bcc, CLZ, ...
O << "\t";
break;
case 4:
- // ADJCALLSTACKDOWN, ADJCALLSTACKUP, B, BLX, BLXr9, BRIND, BX, BXr9, t2B,...
+ // ADJCALLSTACKDOWN, ADJCALLSTACKUP, B, BLX, BLXr9, BRIND, BX, BXr9, NOP,...
return;
break;
case 5:
@@ -1922,38 +2028,61 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
return;
break;
case 31:
- // FCONSTD, VABSD, VADDD, VCMPED, VCMPEZD, VDIVD, VMLAD, VMLSD, VMOVD, VM...
+ // CDP, MCR, MCRR, MRC, MRRC
+ O << "\tp";
+ printNoHashImmediate(MI, 0);
+ O << ", ";
+ printOperand(MI, 1);
+ break;
+ case 32:
+ // CDP2
+ O << ", cr";
+ printNoHashImmediate(MI, 2);
+ O << ", cr";
+ printNoHashImmediate(MI, 3);
+ O << ", cr";
+ printNoHashImmediate(MI, 4);
+ O << ", ";
+ printOperand(MI, 5);
+ return;
+ break;
+ case 33:
+ // FCONSTD, VABSD, VADDD, VCMPD, VCMPED, VCMPEZD, VCMPZD, VDIVD, VMLAD, V...
O << ".f64\t";
printOperand(MI, 0);
break;
- case 32:
+ case 34:
// FCONSTS, VABDfd, VABDfq, VABSS, VABSfd, VABSfd_sfp, VABSfq, VACGEd, VA...
O << ".f32\t";
printOperand(MI, 0);
break;
- case 33:
+ case 35:
// FMSTAT
O << "\tapsr_nzcv, fpscr";
return;
break;
- case 34:
+ case 36:
// Int_MemBarrierV6
O << ", c7, c10, 5";
return;
break;
- case 35:
+ case 37:
// Int_SyncBarrierV6
O << ", c7, c10, 4";
return;
break;
- case 36:
+ case 38:
// Int_eh_sjlj_setjmp
- O << ", #+8] @ eh_setjmp begin\n\tadd\tr12, pc, #8\n\tstr\tr12, [";
+ O << ", #+8] @ eh_setjmp begin\n\tadd\t";
+ printOperand(MI, 1);
+ O << ", pc, #8\n\tstr\t";
+ printOperand(MI, 1);
+ O << ", [";
printOperand(MI, 0);
O << ", #+4]\n\tmov\tr0, #0\n\tadd\tpc, pc, #0\n\tmov\tr0, #1 @ eh_setjmp end";
return;
break;
- case 37:
+ case 39:
// LEApcrel
O << "-(";
PrintSpecial(MI, "private");
@@ -1973,7 +2102,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
PrintSpecial(MI, "uid");
return;
break;
- case 38:
+ case 40:
// LEApcrelJT
O << '_';
printNoHashImmediate(MI, 2);
@@ -1995,21 +2124,33 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
PrintSpecial(MI, "uid");
return;
break;
- case 39:
+ case 41:
// MLA, MOVs, MVNs, SMLAL, SMULL, UMLAL, UMULL
printSBitModifierOperand(MI, 6);
O << "\t";
printOperand(MI, 0);
O << ", ";
break;
- case 40:
+ case 42:
// MOVi, MOVr, MOVrx, MVNi, MVNr
printSBitModifierOperand(MI, 4);
O << "\t";
printOperand(MI, 0);
O << ", ";
break;
- case 41:
+ case 43:
+ // MSR
+ O << "\tcpsr, ";
+ printOperand(MI, 0);
+ return;
+ break;
+ case 44:
+ // MSRsys
+ O << "\tspsr, ";
+ printOperand(MI, 0);
+ return;
+ break;
+ case 45:
// PICADD
O << ":\n\tadd";
printPredicateOperand(MI, 3);
@@ -2019,7 +2160,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printOperand(MI, 1);
return;
break;
- case 42:
+ case 46:
// PICLDR
O << ":\n\tldr";
printPredicateOperand(MI, 3);
@@ -2029,7 +2170,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printAddrModePCOperand(MI, 1);
return;
break;
- case 43:
+ case 47:
// PICLDRB
O << ":\n\tldrb";
printPredicateOperand(MI, 3);
@@ -2039,7 +2180,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printAddrModePCOperand(MI, 1);
return;
break;
- case 44:
+ case 48:
// PICLDRH
O << ":\n\tldrh";
printPredicateOperand(MI, 3);
@@ -2049,7 +2190,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printAddrModePCOperand(MI, 1);
return;
break;
- case 45:
+ case 49:
// PICLDRSB
O << ":\n\tldrsb";
printPredicateOperand(MI, 3);
@@ -2059,7 +2200,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printAddrModePCOperand(MI, 1);
return;
break;
- case 46:
+ case 50:
// PICLDRSH
O << ":\n\tldrsh";
printPredicateOperand(MI, 3);
@@ -2069,7 +2210,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printAddrModePCOperand(MI, 1);
return;
break;
- case 47:
+ case 51:
// PICSTR
O << ":\n\tstr";
printPredicateOperand(MI, 3);
@@ -2079,7 +2220,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printAddrModePCOperand(MI, 1);
return;
break;
- case 48:
+ case 52:
// PICSTRB
O << ":\n\tstrb";
printPredicateOperand(MI, 3);
@@ -2089,7 +2230,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printAddrModePCOperand(MI, 1);
return;
break;
- case 49:
+ case 53:
// PICSTRH
O << ":\n\tstrh";
printPredicateOperand(MI, 3);
@@ -2099,71 +2240,87 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printAddrModePCOperand(MI, 1);
return;
break;
- case 50:
+ case 54:
// VABALsv2i64, VABAsv2i32, VABAsv4i32, VABDLsv2i64, VABDsv2i32, VABDsv4i...
O << ".s32\t";
printOperand(MI, 0);
O << ", ";
break;
- case 51:
+ case 55:
// VABALsv4i32, VABAsv4i16, VABAsv8i16, VABDLsv4i32, VABDsv4i16, VABDsv8i...
O << ".s16\t";
printOperand(MI, 0);
O << ", ";
break;
- case 52:
+ case 56:
// VABALsv8i16, VABAsv16i8, VABAsv8i8, VABDLsv8i16, VABDsv16i8, VABDsv8i8...
O << ".s8\t";
printOperand(MI, 0);
O << ", ";
break;
- case 53:
+ case 57:
// VABALuv2i64, VABAuv2i32, VABAuv4i32, VABDLuv2i64, VABDuv2i32, VABDuv4i...
O << ".u32\t";
printOperand(MI, 0);
O << ", ";
break;
- case 54:
+ case 58:
// VABALuv4i32, VABAuv4i16, VABAuv8i16, VABDLuv4i32, VABDuv4i16, VABDuv8i...
O << ".u16\t";
printOperand(MI, 0);
O << ", ";
break;
- case 55:
+ case 59:
// VABALuv8i16, VABAuv16i8, VABAuv8i8, VABDLuv8i16, VABDuv16i8, VABDuv8i8...
O << ".u8\t";
printOperand(MI, 0);
O << ", ";
break;
- case 56:
+ case 60:
// VADDHNv2i32, VADDv1i64, VADDv2i64, VMOVNv2i32, VMOVv1i64, VMOVv2i64, V...
O << ".i64\t";
printOperand(MI, 0);
O << ", ";
break;
- case 57:
+ case 61:
// VADDHNv4i16, VADDv2i32, VADDv4i32, VCEQv2i32, VCEQv4i32, VCLZv2i32, VC...
O << ".i32\t";
printOperand(MI, 0);
O << ", ";
break;
- case 58:
+ case 62:
// VADDHNv8i8, VADDv4i16, VADDv8i16, VCEQv4i16, VCEQv8i16, VCLZv4i16, VCL...
O << ".i16\t";
printOperand(MI, 0);
O << ", ";
break;
- case 59:
+ case 63:
// VADDv16i8, VADDv8i8, VCEQv16i8, VCEQv8i8, VCLZv16i8, VCLZv8i8, VMLAv16...
O << ".i8\t";
printOperand(MI, 0);
O << ", ";
break;
- case 60:
+ case 64:
// VCNTd, VCNTq, VDUP8d, VDUP8q, VDUPLN8d, VDUPLN8q, VEXTd8, VEXTq8, VLD1...
O << ".8\t";
break;
- case 61:
+ case 65:
+ // VCVTBHS, VCVTTHS
+ O << ".f16.f32\t";
+ printOperand(MI, 0);
+ O << ", ";
+ printOperand(MI, 1);
+ return;
+ break;
+ case 66:
+ // VCVTBSH, VCVTTSH
+ O << ".f32.f16\t";
+ printOperand(MI, 0);
+ O << ", ";
+ printOperand(MI, 1);
+ return;
+ break;
+ case 67:
// VCVTDS
O << ".f64.f32\t";
printOperand(MI, 0);
@@ -2171,7 +2328,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printOperand(MI, 1);
return;
break;
- case 62:
+ case 68:
// VCVTSD
O << ".f32.f64\t";
printOperand(MI, 0);
@@ -2179,63 +2336,69 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printOperand(MI, 1);
return;
break;
- case 63:
- // VCVTf2sd, VCVTf2sd_sfp, VCVTf2sq, VCVTf2xsd, VCVTf2xsq, VTOSIZS
+ case 69:
+ // VCVTf2sd, VCVTf2sd_sfp, VCVTf2sq, VCVTf2xsd, VCVTf2xsq, VTOSIRS, VTOSI...
O << ".s32.f32\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
break;
- case 64:
- // VCVTf2ud, VCVTf2ud_sfp, VCVTf2uq, VCVTf2xud, VCVTf2xuq, VTOUIZS
+ case 70:
+ // VCVTf2ud, VCVTf2ud_sfp, VCVTf2uq, VCVTf2xud, VCVTf2xuq, VTOUIRS, VTOUI...
O << ".u32.f32\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
break;
- case 65:
- // VCVTs2fd, VCVTs2fd_sfp, VCVTs2fq, VCVTxs2fd, VCVTxs2fq, VSITOS
+ case 71:
+ // VCVTs2fd, VCVTs2fd_sfp, VCVTs2fq, VCVTxs2fd, VCVTxs2fq, VSITOS, VSLTOS
O << ".f32.s32\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
break;
- case 66:
- // VCVTu2fd, VCVTu2fd_sfp, VCVTu2fq, VCVTxu2fd, VCVTxu2fq, VUITOS
+ case 72:
+ // VCVTu2fd, VCVTu2fd_sfp, VCVTu2fq, VCVTxu2fd, VCVTxu2fq, VUITOS, VULTOS
O << ".f32.u32\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
break;
- case 67:
+ case 73:
// VDUP16d, VDUP16q, VDUPLN16d, VDUPLN16q, VEXTd16, VEXTq16, VLD1q16, VRE...
O << ".16\t";
break;
- case 68:
+ case 74:
// VDUP32d, VDUP32q, VDUPLN32d, VDUPLN32q, VDUPLNfd, VDUPLNfq, VDUPfd, VD...
O << ".32\t";
break;
- case 69:
+ case 75:
// VLD1d16, VLD2LNd16, VLD2LNq16a, VLD2LNq16b, VLD2d16, VLD2q16, VLD3LNd1...
O << ".16\t{";
break;
- case 70:
+ case 76:
// VLD1d32, VLD1df, VLD2LNd32, VLD2LNq32a, VLD2LNq32b, VLD2d32, VLD2q32, ...
O << ".32\t{";
break;
- case 71:
+ case 77:
// VLD1d64, VLD2d64, VLD3d64, VLD4d64, VST1d64, VST2d64, VST3d64, VST4d64
O << ".64\t{";
break;
- case 72:
+ case 78:
// VLD1d8, VLD2LNd8, VLD2d8, VLD2q8, VLD3LNd8, VLD3d8, VLD3q8a, VLD3q8b, ...
O << ".8\t{";
break;
- case 73:
+ case 79:
// VLD1q64, VLDRD, VSLIv1i64, VSLIv2i64, VSRIv1i64, VSRIv2i64, VST1q64, V...
O << ".64\t";
break;
- case 74:
+ case 80:
+ // VMSR
+ O << "\tfpscr, ";
+ printOperand(MI, 0);
+ return;
+ break;
+ case 81:
// VMULLp, VMULpd, VMULpq
O << ".p8\t";
printOperand(MI, 0);
@@ -2245,69 +2408,138 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printOperand(MI, 2);
return;
break;
- case 75:
+ case 82:
// VQADDsv1i64, VQADDsv2i64, VQMOVNsuv2i32, VQMOVNsv2i32, VQRSHLsv1i64, V...
O << ".s64\t";
printOperand(MI, 0);
O << ", ";
break;
- case 76:
+ case 83:
// VQADDuv1i64, VQADDuv2i64, VQMOVNuv2i32, VQRSHLuv1i64, VQRSHLuv2i64, VQ...
O << ".u64\t";
printOperand(MI, 0);
O << ", ";
break;
- case 77:
- // VSITOD
+ case 84:
+ // VSHTOD
+ O << ".f64.s16\t";
+ printOperand(MI, 0);
+ O << ", ";
+ printOperand(MI, 1);
+ O << ", ";
+ printOperand(MI, 2);
+ return;
+ break;
+ case 85:
+ // VSHTOS
+ O << ".f32.s16\t";
+ printOperand(MI, 0);
+ O << ", ";
+ printOperand(MI, 1);
+ O << ", ";
+ printOperand(MI, 2);
+ return;
+ break;
+ case 86:
+ // VSITOD, VSLTOD
O << ".f64.s32\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
+ break;
+ case 87:
+ // VTOSHD
+ O << ".s16.f64\t";
+ printOperand(MI, 0);
+ O << ", ";
+ printOperand(MI, 1);
+ O << ", ";
+ printOperand(MI, 2);
return;
break;
- case 78:
- // VTOSIZD
+ case 88:
+ // VTOSHS
+ O << ".s16.f32\t";
+ printOperand(MI, 0);
+ O << ", ";
+ printOperand(MI, 1);
+ O << ", ";
+ printOperand(MI, 2);
+ return;
+ break;
+ case 89:
+ // VTOSIRD, VTOSIZD, VTOSLD
O << ".s32.f64\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
+ break;
+ case 90:
+ // VTOUHD
+ O << ".u16.f64\t";
+ printOperand(MI, 0);
+ O << ", ";
+ printOperand(MI, 1);
+ O << ", ";
+ printOperand(MI, 2);
return;
break;
- case 79:
- // VTOUIZD
+ case 91:
+ // VTOUHS
+ O << ".u16.f32\t";
+ printOperand(MI, 0);
+ O << ", ";
+ printOperand(MI, 1);
+ O << ", ";
+ printOperand(MI, 2);
+ return;
+ break;
+ case 92:
+ // VTOUIRD, VTOUIZD, VTOULD
O << ".u32.f64\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
+ break;
+ case 93:
+ // VUHTOD
+ O << ".f64.u16\t";
+ printOperand(MI, 0);
+ O << ", ";
+ printOperand(MI, 1);
+ O << ", ";
+ printOperand(MI, 2);
return;
break;
- case 80:
- // VUITOD
- O << ".f64.u32\t";
+ case 94:
+ // VUHTOS
+ O << ".f32.u16\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
+ O << ", ";
+ printOperand(MI, 2);
return;
break;
- case 81:
+ case 95:
+ // VUITOD, VULTOD
+ O << ".f64.u32\t";
+ printOperand(MI, 0);
+ O << ", ";
+ printOperand(MI, 1);
+ break;
+ case 96:
// t2ADCrr, t2ADCrs, t2ADDSri, t2ADDSrr, t2ADDSrs, t2ADDrSPi, t2ADDrSPs, ...
O << ".w\t";
printOperand(MI, 0);
break;
- case 82:
+ case 97:
// t2BR_JT
O << "\n";
printJT2BlockOperand(MI, 2);
return;
break;
- case 83:
- // t2Int_eh_sjlj_setjmp
- O << ", #+8] @ eh_setjmp begin\n\tadr\tr12, 0f\n\torr.w\tr12, r12, #1\n\tstr.w\tr12, [";
- printOperand(MI, 0);
- O << ", #+4]\n\tmovs\tr0, #0\n\tb\t1f\n0:\tmovs\tr0, #1 @ eh_setjmp end\n1:";
- return;
- break;
- case 84:
+ case 98:
// t2LDM, t2LDM_RET, t2STM
printAddrMode4Operand(MI, 0, "wide");
O << "\t";
@@ -2316,42 +2548,35 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printRegisterList(MI, 4);
return;
break;
- case 85:
+ case 99:
// t2MOVi, t2MOVr, t2MOVrx, t2MVNi
printPredicateOperand(MI, 2);
break;
- case 86:
+ case 100:
// tADC, tADDi3, tADDi8, tADDrr, tAND, tASRri, tASRrr, tBIC, tEOR, tLSLri...
printPredicateOperand(MI, 4);
O << "\t";
printOperand(MI, 0);
O << ", ";
break;
- case 87:
+ case 101:
// tADDrPCi
O << ", pc, ";
printThumbS4ImmOperand(MI, 1);
return;
break;
- case 88:
+ case 102:
// tBR_JTr
O << "\n\t.align\t2\n";
printJTBlockOperand(MI, 1);
return;
break;
- case 89:
+ case 103:
// tBfar
O << "\t@ far jump";
return;
break;
- case 90:
- // tInt_eh_sjlj_setjmp
- O << ", #8]\n\tadr\tr1, 0f\n\tadds\tr1, #1\n\tstr\tr1, [";
- printOperand(MI, 0);
- O << ", #4]\n\tmov\tr1, r12\n\tmovs\tr0, #0\n\tb\t1f\n.align 2\n0:\tmovs\tr0, #1\t@ end eh.setjmp\n1:";
- return;
- break;
- case 91:
+ case 104:
// tLDRpci
O << ".n\t";
printOperand(MI, 0);
@@ -2359,7 +2584,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printOperand(MI, 1);
return;
break;
- case 92:
+ case 105:
// tMOVi8, tMVN, tRSB
printPredicateOperand(MI, 3);
O << "\t";
@@ -2367,7 +2592,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
O << ", ";
printOperand(MI, 2);
break;
- case 93:
+ case 106:
// tPICADD
O << ":\n\tadd\t";
printOperand(MI, 0);
@@ -2377,8 +2602,8 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
}
- // Fragment 2 encoded into 5 bits for 26 unique commands.
- switch ((Bits >> 15) & 31) {
+ // Fragment 2 encoded into 5 bits for 27 unique commands.
+ switch ((Bits >> 14) & 31) {
default: // unreachable.
case 0:
// ADCSSri, ADCSSrr, ADCSSrs, BR_JTadd, MLA, MOVr, MOVrx, MVNr, RSCSri, R...
@@ -2390,11 +2615,11 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
return;
break;
case 2:
- // ADCrr, ADDrr, ANDrr, BICrr, EORrr, MUL, ORRrr, SBCrr, SUBrr, VABALsv2i...
+ // ADCrr, ADDrr, ANDrr, BICrr, EORrr, MCR2, MCRR2, MRC2, MRRC2, MUL, ORRr...
printOperand(MI, 2);
break;
case 3:
- // ADDSri, ADDSrr, ADDSrs, BFC, Bcc, CLZ, CMNzri, CMNzrr, CMNzrs, CMPri, ...
+ // ADDSri, ADDSrr, ADDSrs, BFC, BKPT, BXJ, Bcc, CLZ, CMNzri, CMNzrr, CMNz...
printOperand(MI, 0);
break;
case 4:
@@ -2403,81 +2628,93 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
return;
break;
case 5:
- // FCONSTD, FCONSTS, VABDfd, VABDfq, VABSD, VABSS, VABSfd, VABSfd_sfp, VA...
+ // CDP
+ O << ", cr";
+ printNoHashImmediate(MI, 2);
+ O << ", cr";
+ printNoHashImmediate(MI, 3);
+ O << ", cr";
+ printNoHashImmediate(MI, 4);
O << ", ";
+ printOperand(MI, 5);
+ return;
break;
case 6:
+ // FCONSTD, FCONSTS, MCR, MCRR, MRC, MRRC, VABDfd, VABDfq, VABSD, VABSS, ...
+ O << ", ";
+ break;
+ case 7:
// LDM, LDM_RET, STM, tLDM, tSTM
printAddrMode4Operand(MI, 0);
O << ", ";
printRegisterList(MI, 4);
return;
break;
- case 7:
+ case 8:
// MOVi, MVNi
printSOImmOperand(MI, 1);
return;
break;
- case 8:
+ case 9:
// MOVs, MVNs
printSORegOperand(MI, 1);
return;
break;
- case 9:
- // VCMPEZD, VCMPEZS, tRSB
+ case 10:
+ // VCMPEZD, VCMPEZS, VCMPZD, VCMPZS, tRSB
O << ", #0";
return;
break;
- case 10:
+ case 11:
// VCVTf2sd, VCVTf2sd_sfp, VCVTf2sq, VCVTf2ud, VCVTf2ud_sfp, VCVTf2uq, VC...
return;
break;
- case 11:
+ case 12:
// VLD1q16, VLD1q32, VLD1q64, VLD1q8, VLD1qf
printOperand(MI, 0, "dregpair");
O << ", ";
printAddrMode6Operand(MI, 1);
return;
break;
- case 12:
+ case 13:
// VLDRQ, VSTRQ
printAddrMode4Operand(MI, 1);
O << ", ";
printOperand(MI, 0, "dregpair");
return;
break;
- case 13:
+ case 14:
// VMOVv16i8, VMOVv8i8
printHex8ImmOperand(MI, 1);
return;
break;
- case 14:
+ case 15:
// VMOVv1i64, VMOVv2i64
printHex64ImmOperand(MI, 1);
return;
break;
- case 15:
+ case 16:
// VMOVv2i32, VMOVv4i32
printHex32ImmOperand(MI, 1);
return;
break;
- case 16:
+ case 17:
// VMOVv4i16, VMOVv8i16
printHex16ImmOperand(MI, 1);
return;
break;
- case 17:
+ case 18:
// VST1d16, VST1d32, VST1d64, VST1d8, VST1df, VST2LNd16, VST2LNd32, VST2L...
printOperand(MI, 4);
break;
- case 18:
+ case 19:
// VST1q16, VST1q32, VST1q64, VST1q8, VST1qf
printOperand(MI, 4, "dregpair");
O << ", ";
printAddrMode6Operand(MI, 0);
return;
break;
- case 19:
+ case 20:
// VST3q16a, VST3q16b, VST3q32a, VST3q32b, VST3q8a, VST3q8b, VST4q16a, VS...
printOperand(MI, 5);
O << ", ";
@@ -2485,12 +2722,12 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
O << ", ";
printOperand(MI, 7);
break;
- case 20:
+ case 21:
// t2LEApcrel, t2LEApcrelJT
O << ", #";
printOperand(MI, 1);
break;
- case 21:
+ case 22:
// t2MOVi, t2MOVr
O << ".w\t";
printOperand(MI, 0);
@@ -2498,7 +2735,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printOperand(MI, 1);
return;
break;
- case 22:
+ case 23:
// t2MOVrx, t2MVNi
O << "\t";
printOperand(MI, 0);
@@ -2506,17 +2743,17 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printOperand(MI, 1);
return;
break;
- case 23:
+ case 24:
// tADC, tADDi8, tAND, tASRrr, tBIC, tEOR, tLSLrr, tLSRrr, tMUL, tORR, tR...
printOperand(MI, 3);
return;
break;
- case 24:
+ case 25:
// tADDspi, tSUBspi, tSUBspi_
printThumbS4ImmOperand(MI, 2);
return;
break;
- case 25:
+ case 26:
// tPOP, tPOP_RET, tPUSH
printRegisterList(MI, 2);
return;
@@ -3819,7 +4056,10 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::ADDrr:
case ARM::ANDrr:
case ARM::BICrr:
+ case ARM::BKPT:
+ case ARM::BXJ:
case ARM::Bcc:
+ case ARM::DBG:
case ARM::EORrr:
case ARM::MOVr:
case ARM::MUL:
@@ -3827,6 +4067,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::ORRrr:
case ARM::SBCrr:
case ARM::SUBrr:
+ case ARM::SVC:
case ARM::VABSv16i8:
case ARM::VABSv2i32:
case ARM::VABSv4i16:
@@ -3927,6 +4168,16 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::ADDSri:
case ARM::ADDSrr:
case ARM::ADDSrs:
+ case ARM::QADD:
+ case ARM::QADD16:
+ case ARM::QADD8:
+ case ARM::QASX:
+ case ARM::QDADD:
+ case ARM::QDSUB:
+ case ARM::QSAX:
+ case ARM::QSUB:
+ case ARM::QSUB16:
+ case ARM::QSUB8:
case ARM::RSBSri:
case ARM::RSBSrs:
case ARM::SMMUL:
@@ -3941,6 +4192,12 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::SUBSrs:
case ARM::SXTABrr:
case ARM::SXTAHrr:
+ case ARM::UQADD16:
+ case ARM::UQADD8:
+ case ARM::UQASX:
+ case ARM::UQSAX:
+ case ARM::UQSUB16:
+ case ARM::UQSUB8:
case ARM::UXTABrr:
case ARM::UXTAHrr:
case ARM::VANDd:
@@ -3997,6 +4254,16 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::RSBSri:
case ARM::SUBSri: printSOImmOperand(MI, 2); break;
case ARM::ADDSrr:
+ case ARM::QADD:
+ case ARM::QADD16:
+ case ARM::QADD8:
+ case ARM::QASX:
+ case ARM::QDADD:
+ case ARM::QDSUB:
+ case ARM::QSAX:
+ case ARM::QSUB:
+ case ARM::QSUB16:
+ case ARM::QSUB8:
case ARM::SMMUL:
case ARM::SMULBB:
case ARM::SMULBT:
@@ -4007,6 +4274,12 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::SUBSrr:
case ARM::SXTABrr:
case ARM::SXTAHrr:
+ case ARM::UQADD16:
+ case ARM::UQADD8:
+ case ARM::UQASX:
+ case ARM::UQSAX:
+ case ARM::UQSUB16:
+ case ARM::UQSUB8:
case ARM::UXTABrr:
case ARM::UXTAHrr:
case ARM::VANDd:
@@ -4069,13 +4342,17 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::FCONSTD:
case ARM::FCONSTS:
case ARM::MOVrx:
+ case ARM::MRS:
+ case ARM::MRSsys:
case ARM::VABSD:
case ARM::VABSS:
case ARM::VABSfd:
case ARM::VABSfd_sfp:
case ARM::VABSfq:
+ case ARM::VCMPD:
case ARM::VCMPED:
case ARM::VCMPES:
+ case ARM::VCMPS:
case ARM::VCVTf2xsd:
case ARM::VCVTf2xsq:
case ARM::VCVTf2xud:
@@ -4088,6 +4365,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::VMOVDcc:
case ARM::VMOVS:
case ARM::VMOVScc:
+ case ARM::VMRS:
case ARM::VNEGD:
case ARM::VNEGDcc:
case ARM::VNEGS:
@@ -4099,8 +4377,16 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::VRECPEfq:
case ARM::VRSQRTEfd:
case ARM::VRSQRTEfq:
+ case ARM::VSLTOD:
+ case ARM::VSLTOS:
case ARM::VSQRTD:
case ARM::VSQRTS:
+ case ARM::VTOSLD:
+ case ARM::VTOSLS:
+ case ARM::VTOULD:
+ case ARM::VTOULS:
+ case ARM::VULTOD:
+ case ARM::VULTOS:
case ARM::t2CMNzri:
case ARM::t2CMNzrr:
case ARM::t2CMNzrs:
@@ -4155,13 +4441,17 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::FCONSTD: printVFPf64ImmOperand(MI, 1); break;
case ARM::FCONSTS: printVFPf32ImmOperand(MI, 1); break;
case ARM::MOVrx: O << ", rrx"; break;
+ case ARM::MRS: O << ", cpsr"; break;
+ case ARM::MRSsys: O << ", spsr"; break;
case ARM::VABSD:
case ARM::VABSS:
case ARM::VABSfd:
case ARM::VABSfd_sfp:
case ARM::VABSfq:
+ case ARM::VCMPD:
case ARM::VCMPED:
case ARM::VCMPES:
+ case ARM::VCMPS:
case ARM::VMOVD:
case ARM::VMOVS:
case ARM::VNEGD:
@@ -4211,8 +4501,17 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::VMOVScc:
case ARM::VNEGDcc:
case ARM::VNEGScc:
+ case ARM::VSLTOD:
+ case ARM::VSLTOS:
+ case ARM::VTOSLD:
+ case ARM::VTOSLS:
+ case ARM::VTOULD:
+ case ARM::VTOULS:
+ case ARM::VULTOD:
+ case ARM::VULTOS:
case ARM::t2MOVCCi:
case ARM::t2MOVCCr: printOperand(MI, 2); break;
+ case ARM::VMRS: O << ", fpscr"; break;
case ARM::t2CMNzrs:
case ARM::t2CMPrs:
case ARM::t2CMPzrs:
@@ -4240,13 +4539,17 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
}
return;
break;
+ case ARM::LDRBT:
case ARM::LDRB_POST:
case ARM::LDRH_POST:
case ARM::LDRSB_POST:
case ARM::LDRSH_POST:
+ case ARM::LDRT:
case ARM::LDR_POST:
+ case ARM::STRBT:
case ARM::STRB_POST:
case ARM::STRH_POST:
+ case ARM::STRT:
case ARM::STR_POST:
case ARM::t2LDRB_POST:
case ARM::t2LDRH_POST:
@@ -4260,9 +4563,13 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printOperand(MI, 2);
O << "], ";
switch (MI->getOpcode()) {
+ case ARM::LDRBT:
case ARM::LDRB_POST:
+ case ARM::LDRT:
case ARM::LDR_POST:
+ case ARM::STRBT:
case ARM::STRB_POST:
+ case ARM::STRT:
case ARM::STR_POST: printAddrMode2OffsetOperand(MI, 3); break;
case ARM::LDRH_POST:
case ARM::LDRSB_POST:
@@ -4320,6 +4627,8 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::STREX:
case ARM::STREXB:
case ARM::STREXH:
+ case ARM::SWP:
+ case ARM::SWPB:
case ARM::t2LDREXD:
case ARM::t2STREX:
case ARM::t2STREXB:
@@ -4331,11 +4640,53 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
O << ']';
return;
break;
+ case ARM::MCR:
+ case ARM::MRC:
+ printOperand(MI, 2);
+ O << ", cr";
+ printNoHashImmediate(MI, 3);
+ O << ", cr";
+ printNoHashImmediate(MI, 4);
+ O << ", ";
+ printOperand(MI, 5);
+ return;
+ break;
+ case ARM::MCR2:
+ case ARM::MRC2:
+ O << ", cr";
+ printNoHashImmediate(MI, 3);
+ O << ", cr";
+ printNoHashImmediate(MI, 4);
+ O << ", ";
+ printOperand(MI, 5);
+ return;
+ break;
+ case ARM::MCRR:
+ case ARM::MRRC:
+ printOperand(MI, 2);
+ O << ", ";
+ printOperand(MI, 3);
+ O << ", cr";
+ printNoHashImmediate(MI, 4);
+ return;
+ break;
+ case ARM::MCRR2:
+ case ARM::MRRC2:
+ O << ", ";
+ printOperand(MI, 3);
+ O << ", cr";
+ printNoHashImmediate(MI, 4);
+ return;
+ break;
case ARM::MLA:
case ARM::SMLAL:
case ARM::SMULL:
case ARM::UMLAL:
case ARM::UMULL:
+ case ARM::VBIFd:
+ case ARM::VBIFq:
+ case ARM::VBITd:
+ case ARM::VBITq:
case ARM::VBSLd:
case ARM::VBSLq:
case ARM::VSLIv16i8:
@@ -4366,6 +4717,10 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::SBFX:
case ARM::SMLABB:
case ARM::SMLABT:
+ case ARM::SMLALBB:
+ case ARM::SMLALBT:
+ case ARM::SMLALTB:
+ case ARM::SMLALTT:
case ARM::SMLATB:
case ARM::SMLATT:
case ARM::SMLAWB:
@@ -4386,6 +4741,9 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::VEXTq32:
case ARM::VEXTq8:
case ARM::VEXTqf:
+ case ARM::VMOVRRS:
+ case ARM::VMOVSRR:
+ case ARM::t2BFI:
case ARM::t2MLA:
case ARM::t2MLS:
case ARM::t2PKHBT:
@@ -4418,6 +4776,10 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::SBFX:
case ARM::SMLABB:
case ARM::SMLABT:
+ case ARM::SMLALBB:
+ case ARM::SMLALBT:
+ case ARM::SMLALTB:
+ case ARM::SMLALTT:
case ARM::SMLATB:
case ARM::SMLATT:
case ARM::SMLAWB:
@@ -4434,6 +4796,9 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::VEXTq32:
case ARM::VEXTq8:
case ARM::VEXTqf:
+ case ARM::VMOVRRS:
+ case ARM::VMOVSRR:
+ case ARM::t2BFI:
case ARM::t2MLA:
case ARM::t2MLS:
case ARM::t2SBFX:
@@ -5263,3 +5628,420 @@ const char *ARMAsmPrinter::getRegisterName(unsigned RegNo) {
"sp\000";
return AsmStrs+RegAsmOffset[RegNo-1];
}
+
+
+#ifdef GET_INSTRUCTION_NAME
+#undef GET_INSTRUCTION_NAME
+
+/// getInstructionName: This method is automatically generated by tblgen
+/// from the instruction set description. This returns the enum name of the
+/// specified instruction.
+const char *ARMAsmPrinter::getInstructionName(unsigned Opcode) {
+ assert(Opcode < 1611 && "Invalid instruction number!");
+
+ static const unsigned InstAsmOffset[] = {
+ 0, 4, 14, 24, 33, 42, 47, 62, 76, 89, 103, 120, 130, 138,
+ 146, 154, 160, 166, 172, 179, 186, 193, 199, 205, 211, 228, 243, 249,
+ 255, 261, 281, 301, 320, 340, 360, 379, 399, 419, 438, 459, 480, 500,
+ 519, 538, 556, 576, 596, 615, 635, 655, 674, 690, 706, 721, 723, 727,
+ 733, 739, 745, 750, 753, 757, 763, 771, 776, 786, 792, 801, 808, 815,
+ 818, 822, 829, 834, 838, 842, 847, 851, 858, 865, 872, 878, 884, 890,
+ 897, 904, 911, 927, 931, 935, 941, 947, 953, 961, 969, 976, 993, 1010,
+ 1028, 1046, 1065, 1069, 1077, 1081, 1086, 1092, 1102, 1111, 1116, 1122, 1129, 1136,
+ 1143, 1148, 1158, 1167, 1173, 1184, 1194, 1200, 1211, 1221, 1226, 1235, 1243, 1249,
+ 1258, 1269, 1273, 1278, 1283, 1289, 1293, 1297, 1304, 1311, 1318, 1326, 1331, 1338,
+ 1350, 1360, 1365, 1371, 1376, 1388, 1400, 1404, 1409, 1414, 1420, 1424, 1431, 1435,
+ 1442, 1446, 1451, 1456, 1461, 1465, 1471, 1477, 1483, 1490, 1497, 1505, 1513, 1522,
+ 1531, 1538, 1546, 1554, 1560, 1566, 1571, 1578, 1584, 1589, 1595, 1601, 1606, 1611,
+ 1618, 1624, 1629, 1633, 1639, 1645, 1652, 1659, 1665, 1671, 1678, 1685, 1691, 1697,
+ 1705, 1713, 1721, 1727, 1733, 1739, 1744, 1753, 1762, 1766, 1773, 1780, 1786, 1794,
+ 1802, 1810, 1818, 1825, 1832, 1839, 1846, 1852, 1858, 1864, 1871, 1878, 1884, 1891,
+ 1898, 1905, 1912, 1916, 1920, 1925, 1931, 1941, 1950, 1955, 1961, 1968, 1975, 1982,
+ 1987, 1997, 2006, 2011, 2020, 2028, 2035, 2042, 2049, 2055, 2061, 2067, 2071, 2075,
+ 2080, 2088, 2100, 2108, 2120, 2126, 2136, 2142, 2152, 2158, 2164, 2170, 2177, 2182,
+ 2188, 2194, 2200, 2205, 2211, 2217, 2223, 2231, 2238, 2244, 2250, 2258, 2265, 2273,
+ 2285, 2293, 2305, 2313, 2325, 2331, 2341, 2347, 2357, 2369, 2381, 2393, 2405, 2417,
+ 2429, 2440, 2451, 2462, 2473, 2484, 2494, 2505, 2516, 2527, 2538, 2549, 2559, 2571,
+ 2583, 2595, 2607, 2619, 2631, 2638, 2645, 2656, 2667, 2678, 2689, 2700, 2710, 2721,
+ 2732, 2743, 2754, 2765, 2775, 2781, 2787, 2794, 2805, 2812, 2822, 2832, 2842, 2852,
+ 2862, 2871, 2878, 2885, 2892, 2899, 2905, 2917, 2929, 2940, 2952, 2964, 2976, 2988,
+ 3000, 3012, 3018, 3030, 3042, 3054, 3066, 3078, 3090, 3097, 3108, 3115, 3125, 3135,
+ 3145, 3155, 3165, 3175, 3185, 3194, 3200, 3206, 3212, 3218, 3224, 3230, 3236, 3242,
+ 3248, 3254, 3261, 3268, 3278, 3288, 3298, 3308, 3318, 3327, 3334, 3341, 3352, 3363,
+ 3374, 3385, 3396, 3406, 3417, 3428, 3439, 3450, 3461, 3471, 3478, 3485, 3496, 3507,
+ 3518, 3529, 3540, 3550, 3561, 3572, 3583, 3594, 3605, 3615, 3625, 3635, 3645, 3655,
+ 3665, 3674, 3684, 3694, 3704, 3714, 3724, 3733, 3739, 3746, 3753, 3761, 3769, 3775,
+ 3782, 3789, 3795, 3801, 3809, 3817, 3824, 3831, 3839, 3847, 3856, 3869, 3878, 3887,
+ 3900, 3909, 3919, 3929, 3939, 3949, 3958, 3971, 3980, 3989, 4002, 4011, 4021, 4031,
+ 4041, 4051, 4057, 4063, 4071, 4079, 4087, 4095, 4102, 4109, 4119, 4129, 4139, 4149,
+ 4158, 4167, 4176, 4185, 4192, 4200, 4207, 4215, 4221, 4227, 4235, 4243, 4250, 4257,
+ 4265, 4273, 4280, 4287, 4297, 4307, 4316, 4326, 4335, 4347, 4359, 4371, 4383, 4395,
+ 4406, 4418, 4430, 4442, 4454, 4466, 4477, 4489, 4501, 4513, 4525, 4537, 4548, 4560,
+ 4572, 4584, 4596, 4608, 4619, 4627, 4635, 4643, 4650, 4657, 4665, 4673, 4681, 4688,
+ 4695, 4705, 4715, 4724, 4735, 4746, 4757, 4768, 4776, 4784, 4792, 4799, 4807, 4815,
+ 4822, 4832, 4842, 4851, 4862, 4873, 4884, 4895, 4903, 4911, 4919, 4926, 4935, 4944,
+ 4953, 4962, 4970, 4978, 4988, 4998, 5007, 5018, 5029, 5040, 5051, 5059, 5067, 5075,
+ 5082, 5091, 5100, 5109, 5118, 5126, 5134, 5140, 5146, 5152, 5158, 5164, 5171, 5178,
+ 5189, 5200, 5211, 5222, 5233, 5243, 5254, 5265, 5276, 5287, 5298, 5308, 5315, 5322,
+ 5333, 5344, 5355, 5366, 5377, 5387, 5398, 5409, 5420, 5431, 5442, 5452, 5458, 5472,
+ 5486, 5500, 5514, 5526, 5538, 5550, 5562, 5574, 5586, 5592, 5599, 5606, 5615, 5624,
+ 5636, 5648, 5660, 5672, 5682, 5692, 5702, 5712, 5722, 5731, 5737, 5751, 5765, 5779,
+ 5793, 5805, 5817, 5829, 5841, 5853, 5865, 5871, 5878, 5885, 5894, 5903, 5915, 5927,
+ 5939, 5951, 5961, 5971, 5981, 5991, 6001, 6010, 6016, 6024, 6032, 6042, 6054, 6066,
+ 6078, 6090, 6102, 6114, 6125, 6136, 6146, 6152, 6160, 6168, 6175, 6181, 6188, 6196,
+ 6204, 6214, 6224, 6234, 6244, 6254, 6264, 6274, 6283, 6288, 6293, 6299, 6306, 6320,
+ 6334, 6348, 6362, 6374, 6386, 6398, 6410, 6422, 6434, 6440, 6447, 6458, 6465, 6472,
+ 6479, 6488, 6497, 6509, 6521, 6533, 6545, 6555, 6565, 6575, 6585, 6595, 6604, 6610,
+ 6616, 6622, 6630, 6636, 6644, 6653, 6666, 6675, 6684, 6693, 6702, 6711, 6719, 6727,
+ 6734, 6741, 6748, 6755, 6762, 6769, 6775, 6781, 6787, 6793, 6806, 6819, 6832, 6845,
+ 6858, 6870, 6883, 6896, 6909, 6922, 6935, 6947, 6960, 6973, 6986, 6999, 7012, 7024,
+ 7037, 7050, 7063, 7076, 7089, 7101, 7108, 7117, 7126, 7134, 7141, 7150, 7159, 7167,
+ 7176, 7185, 7193, 7200, 7209, 7218, 7226, 7235, 7244, 7252, 7263, 7274, 7285, 7296,
+ 7307, 7317, 7329, 7341, 7353, 7365, 7377, 7389, 7401, 7412, 7424, 7436, 7448, 7460,
+ 7472, 7484, 7496, 7507, 7522, 7537, 7550, 7563, 7578, 7593, 7606, 7619, 7634, 7649,
+ 7664, 7679, 7692, 7705, 7718, 7731, 7746, 7761, 7774, 7787, 7801, 7815, 7828, 7841,
+ 7854, 7866, 7879, 7892, 7904, 7915, 7926, 7937, 7948, 7959, 7969, 7985, 8001, 8017,
+ 8033, 8047, 8061, 8075, 8089, 8102, 8115, 8128, 8141, 8154, 8167, 8180, 8192, 8205,
+ 8218, 8231, 8244, 8257, 8270, 8283, 8295, 8309, 8323, 8336, 8350, 8364, 8377, 8391,
+ 8405, 8418, 8431, 8444, 8457, 8470, 8483, 8496, 8509, 8521, 8534, 8547, 8560, 8573,
+ 8586, 8599, 8612, 8624, 8636, 8648, 8660, 8672, 8684, 8696, 8708, 8719, 8732, 8745,
+ 8758, 8771, 8784, 8797, 8810, 8822, 8834, 8846, 8858, 8870, 8882, 8894, 8906, 8917,
+ 8930, 8943, 8955, 8968, 8981, 8993, 9006, 9019, 9031, 9043, 9055, 9067, 9079, 9091,
+ 9103, 9115, 9126, 9138, 9150, 9162, 9174, 9186, 9198, 9210, 9221, 9234, 9247, 9259,
+ 9267, 9276, 9285, 9293, 9302, 9311, 9320, 9329, 9339, 9348, 9358, 9367, 9377, 9387,
+ 9396, 9405, 9415, 9425, 9434, 9443, 9456, 9469, 9482, 9495, 9508, 9520, 9533, 9546,
+ 9559, 9572, 9585, 9597, 9609, 9621, 9633, 9645, 9657, 9669, 9681, 9692, 9704, 9716,
+ 9728, 9740, 9752, 9764, 9776, 9787, 9799, 9811, 9822, 9834, 9846, 9858, 9870, 9882,
+ 9894, 9906, 9917, 9929, 9941, 9953, 9965, 9977, 9989, 10001, 10012, 10021, 10031, 10041,
+ 10050, 10060, 10070, 10082, 10094, 10106, 10118, 10130, 10142, 10154, 10165, 10177, 10189, 10201,
+ 10213, 10225, 10237, 10249, 10260, 10273, 10286, 10298, 10308, 10318, 10327, 10336, 10345, 10353,
+ 10365, 10377, 10389, 10401, 10413, 10425, 10436, 10447, 10458, 10469, 10480, 10491, 10502, 10512,
+ 10523, 10534, 10545, 10556, 10567, 10578, 10589, 10599, 10610, 10621, 10632, 10643, 10654, 10665,
+ 10676, 10686, 10697, 10708, 10718, 10729, 10740, 10751, 10762, 10773, 10784, 10795, 10805, 10816,
+ 10827, 10838, 10849, 10860, 10871, 10882, 10892, 10899, 10906, 10913, 10920, 10930, 10940, 10950,
+ 10960, 10970, 10980, 10990, 10999, 11006, 11013, 11020, 11027, 11038, 11049, 11060, 11071, 11082,
+ 11093, 11104, 11114, 11125, 11136, 11147, 11158, 11169, 11180, 11191, 11201, 11211, 11221, 11231,
+ 11241, 11251, 11261, 11271, 11280, 11288, 11296, 11304, 11311, 11318, 11326, 11334, 11342, 11349,
+ 11356, 11366, 11376, 11385, 11396, 11407, 11418, 11429, 11437, 11445, 11453, 11460, 11468, 11476,
+ 11483, 11493, 11503, 11512, 11523, 11534, 11545, 11556, 11564, 11572, 11580, 11587, 11596, 11605,
+ 11614, 11623, 11631, 11639, 11649, 11659, 11668, 11679, 11690, 11701, 11712, 11720, 11728, 11736,
+ 11743, 11752, 11761, 11770, 11779, 11787, 11795, 11801, 11807, 11813, 11819, 11825, 11831, 11843,
+ 11855, 11866, 11878, 11890, 11902, 11914, 11926, 11938, 11944, 11956, 11968, 11980, 11992, 12004,
+ 12016, 12023, 12034, 12041, 12051, 12061, 12071, 12081, 12091, 12101, 12111, 12120, 12126, 12132,
+ 12138, 12144, 12150, 12156, 12162, 12168, 12175, 12182, 12190, 12198, 12206, 12214, 12221, 12228,
+ 12235, 12242, 12250, 12258, 12266, 12274, 12281, 12288, 12296, 12304, 12311, 12319, 12327, 12334,
+ 12344, 12354, 12364, 12374, 12384, 12393, 12400, 12407, 12414, 12421, 12428, 12435, 12443, 12451,
+ 12458, 12466, 12474, 12481, 12489, 12497, 12504, 12512, 12520, 12527, 12531, 12535, 12541, 12550,
+ 12559, 12568, 12576, 12584, 12592, 12601, 12610, 12619, 12629, 12641, 12651, 12659, 12669, 12677,
+ 12685, 12693, 12701, 12709, 12717, 12725, 12729, 12735, 12741, 12749, 12757, 12765, 12773, 12779,
+ 12785, 12794, 12803, 12812, 12820, 12828, 12836, 12845, 12854, 12863, 12871, 12879, 12887, 12892,
+ 12911, 12931, 12952, 12958, 12968, 12980, 12991, 13001, 13010, 13020, 13028, 13037, 13047, 13055,
+ 13064, 13073, 13082, 13094, 13105, 13115, 13124, 13134, 13142, 13155, 13167, 13178, 13188, 13199,
+ 13208, 13221, 13233, 13244, 13254, 13265, 13274, 13285, 13295, 13304, 13312, 13321, 13334, 13341,
+ 13352, 13365, 13373, 13381, 13389, 13397, 13403, 13409, 13420, 13429, 13440, 13451, 13460, 13471,
+ 13481, 13488, 13497, 13509, 13516, 13524, 13538, 13552, 13558, 13565, 13572, 13579, 13587, 13595,
+ 13603, 13611, 13619, 13627, 13635, 13643, 13650, 13656, 13664, 13672, 13680, 13688, 13697, 13706,
+ 13714, 13722, 13731, 13740, 13749, 13757, 13765, 13773, 13780, 13789, 13798, 13806, 13815, 13824,
+ 13833, 13842, 13850, 13858, 13866, 13875, 13884, 13892, 13901, 13910, 13919, 13928, 13934, 13946,
+ 13957, 13967, 13976, 13984, 13993, 14001, 14010, 14019, 14028, 14040, 14051, 14061, 14070, 14078,
+ 14089, 14099, 14108, 14116, 14123, 14132, 14141, 14150, 14160, 14172, 14185, 14196, 14206, 14217,
+ 14225, 14235, 14243, 14251, 14261, 14275, 14285, 14299, 14307, 14319, 14327, 14339, 14345, 14351,
+ 14359, 14367, 14375, 14384, 14392, 14400, 14408, 14415, 14423, 14431, 14439, 14449, 14463, 14473,
+ 14487, 14497, 14511, 14519, 14531, 14539, 14551, 14556, 14565, 14572, 14579, 14588, 14596, 14605,
+ 14612, 14620, 14628, 14637, 14655, 14671, 14676, 14683, 14690, 14697, 14700, 14705, 14711, 14715,
+ 14721, 14730, 14736, 14745, 14751, 14758, 14766, 14770, 14778, 14793, 14799, 14804, 14810, 14816,
+ 14821, 14827, 14835, 14842, 14848, 14857, 14865, 14872, 14877, 14897, 14902, 14907, 14913, 14920,
+ 14926, 14933, 14940, 14947, 14954, 14960, 14968, 14980, 14988, 14998, 15010, 15017, 15024, 15031,
+ 15038, 15046, 15054, 15069, 15076, 15088, 15101, 15108, 15114, 15127, 15132, 15137, 15142, 15150,
+ 15155, 15164, 15170, 15175, 15182, 15189, 15194, 15199, 15208, 15213, 15218, 15223, 15229, 15236,
+ 15242, 15249, 15255, 15263, 15270, 15277, 15284, 15292, 15301, 15307, 15313, 15320, 15328, 15333,
+ 15339, 0
+ };
+
+ const char *Strs =
+ "PHI\000INLINEASM\000DBG_LABEL\000EH_LABEL\000GC_LABEL\000KILL\000EXTRAC"
+ "T_SUBREG\000INSERT_SUBREG\000IMPLICIT_DEF\000SUBREG_TO_REG\000COPY_TO_R"
+ "EGCLASS\000DBG_VALUE\000ADCSSri\000ADCSSrr\000ADCSSrs\000ADCri\000ADCrr"
+ "\000ADCrs\000ADDSri\000ADDSrr\000ADDSrs\000ADDri\000ADDrr\000ADDrs\000A"
+ "DJCALLSTACKDOWN\000ADJCALLSTACKUP\000ANDri\000ANDrr\000ANDrs\000ATOMIC_"
+ "CMP_SWAP_I16\000ATOMIC_CMP_SWAP_I32\000ATOMIC_CMP_SWAP_I8\000ATOMIC_LOA"
+ "D_ADD_I16\000ATOMIC_LOAD_ADD_I32\000ATOMIC_LOAD_ADD_I8\000ATOMIC_LOAD_A"
+ "ND_I16\000ATOMIC_LOAD_AND_I32\000ATOMIC_LOAD_AND_I8\000ATOMIC_LOAD_NAND"
+ "_I16\000ATOMIC_LOAD_NAND_I32\000ATOMIC_LOAD_NAND_I8\000ATOMIC_LOAD_OR_I"
+ "16\000ATOMIC_LOAD_OR_I32\000ATOMIC_LOAD_OR_I8\000ATOMIC_LOAD_SUB_I16\000"
+ "ATOMIC_LOAD_SUB_I32\000ATOMIC_LOAD_SUB_I8\000ATOMIC_LOAD_XOR_I16\000ATO"
+ "MIC_LOAD_XOR_I32\000ATOMIC_LOAD_XOR_I8\000ATOMIC_SWAP_I16\000ATOMIC_SWA"
+ "P_I32\000ATOMIC_SWAP_I8\000B\000BFC\000BICri\000BICrr\000BICrs\000BKPT\000"
+ "BL\000BLX\000BLXr9\000BL_pred\000BLr9\000BLr9_pred\000BRIND\000BR_JTadd"
+ "\000BR_JTm\000BR_JTr\000BX\000BXJ\000BX_RET\000BXr9\000Bcc\000CDP\000CD"
+ "P2\000CLZ\000CMNzri\000CMNzrr\000CMNzrs\000CMPri\000CMPrr\000CMPrs\000C"
+ "MPzri\000CMPzrr\000CMPzrs\000CONSTPOOL_ENTRY\000CPS\000DBG\000EORri\000"
+ "EORrr\000EORrs\000FCONSTD\000FCONSTS\000FMSTAT\000Int_MemBarrierV6\000I"
+ "nt_MemBarrierV7\000Int_SyncBarrierV6\000Int_SyncBarrierV7\000Int_eh_sjl"
+ "j_setjmp\000LDM\000LDM_RET\000LDR\000LDRB\000LDRBT\000LDRB_POST\000LDRB"
+ "_PRE\000LDRD\000LDREX\000LDREXB\000LDREXD\000LDREXH\000LDRH\000LDRH_POS"
+ "T\000LDRH_PRE\000LDRSB\000LDRSB_POST\000LDRSB_PRE\000LDRSH\000LDRSH_POS"
+ "T\000LDRSH_PRE\000LDRT\000LDR_POST\000LDR_PRE\000LDRcp\000LEApcrel\000L"
+ "EApcrelJT\000MCR\000MCR2\000MCRR\000MCRR2\000MLA\000MLS\000MOVCCi\000MO"
+ "VCCr\000MOVCCs\000MOVTi16\000MOVi\000MOVi16\000MOVi2pieces\000MOVi32imm"
+ "\000MOVr\000MOVrx\000MOVs\000MOVsra_flag\000MOVsrl_flag\000MRC\000MRC2\000"
+ "MRRC\000MRRC2\000MRS\000MRSsys\000MSR\000MSRsys\000MUL\000MVNi\000MVNr\000"
+ "MVNs\000NOP\000ORRri\000ORRrr\000ORRrs\000PICADD\000PICLDR\000PICLDRB\000"
+ "PICLDRH\000PICLDRSB\000PICLDRSH\000PICSTR\000PICSTRB\000PICSTRH\000PKHB"
+ "T\000PKHTB\000QADD\000QADD16\000QADD8\000QASX\000QDADD\000QDSUB\000QSAX"
+ "\000QSUB\000QSUB16\000QSUB8\000RBIT\000REV\000REV16\000REVSH\000RSBSri\000"
+ "RSBSrs\000RSBri\000RSBrs\000RSCSri\000RSCSrs\000RSCri\000RSCrs\000SBCSS"
+ "ri\000SBCSSrr\000SBCSSrs\000SBCri\000SBCrr\000SBCrs\000SBFX\000SETENDBE"
+ "\000SETENDLE\000SEV\000SMLABB\000SMLABT\000SMLAL\000SMLALBB\000SMLALBT\000"
+ "SMLALTB\000SMLALTT\000SMLATB\000SMLATT\000SMLAWB\000SMLAWT\000SMMLA\000"
+ "SMMLS\000SMMUL\000SMULBB\000SMULBT\000SMULL\000SMULTB\000SMULTT\000SMUL"
+ "WB\000SMULWT\000STM\000STR\000STRB\000STRBT\000STRB_POST\000STRB_PRE\000"
+ "STRD\000STREX\000STREXB\000STREXD\000STREXH\000STRH\000STRH_POST\000STR"
+ "H_PRE\000STRT\000STR_POST\000STR_PRE\000SUBSri\000SUBSrr\000SUBSrs\000S"
+ "UBri\000SUBrr\000SUBrs\000SVC\000SWP\000SWPB\000SXTABrr\000SXTABrr_rot\000"
+ "SXTAHrr\000SXTAHrr_rot\000SXTBr\000SXTBr_rot\000SXTHr\000SXTHr_rot\000T"
+ "EQri\000TEQrr\000TEQrs\000TPsoft\000TRAP\000TSTri\000TSTrr\000TSTrs\000"
+ "UBFX\000UMAAL\000UMLAL\000UMULL\000UQADD16\000UQADD8\000UQASX\000UQSAX\000"
+ "UQSUB16\000UQSUB8\000UXTABrr\000UXTABrr_rot\000UXTAHrr\000UXTAHrr_rot\000"
+ "UXTB16r\000UXTB16r_rot\000UXTBr\000UXTBr_rot\000UXTHr\000UXTHr_rot\000V"
+ "ABALsv2i64\000VABALsv4i32\000VABALsv8i16\000VABALuv2i64\000VABALuv4i32\000"
+ "VABALuv8i16\000VABAsv16i8\000VABAsv2i32\000VABAsv4i16\000VABAsv4i32\000"
+ "VABAsv8i16\000VABAsv8i8\000VABAuv16i8\000VABAuv2i32\000VABAuv4i16\000VA"
+ "BAuv4i32\000VABAuv8i16\000VABAuv8i8\000VABDLsv2i64\000VABDLsv4i32\000VA"
+ "BDLsv8i16\000VABDLuv2i64\000VABDLuv4i32\000VABDLuv8i16\000VABDfd\000VAB"
+ "Dfq\000VABDsv16i8\000VABDsv2i32\000VABDsv4i16\000VABDsv4i32\000VABDsv8i"
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+ "\000VABDuv8i16\000VABDuv8i8\000VABSD\000VABSS\000VABSfd\000VABSfd_sfp\000"
+ "VABSfq\000VABSv16i8\000VABSv2i32\000VABSv4i16\000VABSv4i32\000VABSv8i16"
+ "\000VABSv8i8\000VACGEd\000VACGEq\000VACGTd\000VACGTq\000VADDD\000VADDHN"
+ "v2i32\000VADDHNv4i16\000VADDHNv8i8\000VADDLsv2i64\000VADDLsv4i32\000VAD"
+ "DLsv8i16\000VADDLuv2i64\000VADDLuv4i32\000VADDLuv8i16\000VADDS\000VADDW"
+ "sv2i64\000VADDWsv4i32\000VADDWsv8i16\000VADDWuv2i64\000VADDWuv4i32\000V"
+ "ADDWuv8i16\000VADDfd\000VADDfd_sfp\000VADDfq\000VADDv16i8\000VADDv1i64\000"
+ "VADDv2i32\000VADDv2i64\000VADDv4i16\000VADDv4i32\000VADDv8i16\000VADDv8"
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+ "VCEQv4i16\000VCEQv4i32\000VCEQv8i16\000VCEQv8i8\000VCGEfd\000VCGEfq\000"
+ "VCGEsv16i8\000VCGEsv2i32\000VCGEsv4i16\000VCGEsv4i32\000VCGEsv8i16\000V"
+ "CGEsv8i8\000VCGEuv16i8\000VCGEuv2i32\000VCGEuv4i16\000VCGEuv4i32\000VCG"
+ "Euv8i16\000VCGEuv8i8\000VCGTfd\000VCGTfq\000VCGTsv16i8\000VCGTsv2i32\000"
+ "VCGTsv4i16\000VCGTsv4i32\000VCGTsv8i16\000VCGTsv8i8\000VCGTuv16i8\000VC"
+ "GTuv2i32\000VCGTuv4i16\000VCGTuv4i32\000VCGTuv8i16\000VCGTuv8i8\000VCLS"
+ "v16i8\000VCLSv2i32\000VCLSv4i16\000VCLSv4i32\000VCLSv8i16\000VCLSv8i8\000"
+ "VCLZv16i8\000VCLZv2i32\000VCLZv4i16\000VCLZv4i32\000VCLZv8i16\000VCLZv8"
+ "i8\000VCMPD\000VCMPED\000VCMPES\000VCMPEZD\000VCMPEZS\000VCMPS\000VCMPZ"
+ "D\000VCMPZS\000VCNTd\000VCNTq\000VCVTBHS\000VCVTBSH\000VCVTDS\000VCVTSD"
+ "\000VCVTTHS\000VCVTTSH\000VCVTf2sd\000VCVTf2sd_sfp\000VCVTf2sq\000VCVTf"
+ "2ud\000VCVTf2ud_sfp\000VCVTf2uq\000VCVTf2xsd\000VCVTf2xsq\000VCVTf2xud\000"
+ "VCVTf2xuq\000VCVTs2fd\000VCVTs2fd_sfp\000VCVTs2fq\000VCVTu2fd\000VCVTu2"
+ "fd_sfp\000VCVTu2fq\000VCVTxs2fd\000VCVTxs2fq\000VCVTxu2fd\000VCVTxu2fq\000"
+ "VDIVD\000VDIVS\000VDUP16d\000VDUP16q\000VDUP32d\000VDUP32q\000VDUP8d\000"
+ "VDUP8q\000VDUPLN16d\000VDUPLN16q\000VDUPLN32d\000VDUPLN32q\000VDUPLN8d\000"
+ "VDUPLN8q\000VDUPLNfd\000VDUPLNfq\000VDUPfd\000VDUPfdf\000VDUPfq\000VDUP"
+ "fqf\000VEORd\000VEORq\000VEXTd16\000VEXTd32\000VEXTd8\000VEXTdf\000VEXT"
+ "q16\000VEXTq32\000VEXTq8\000VEXTqf\000VGETLNi32\000VGETLNs16\000VGETLNs"
+ "8\000VGETLNu16\000VGETLNu8\000VHADDsv16i8\000VHADDsv2i32\000VHADDsv4i16"
+ "\000VHADDsv4i32\000VHADDsv8i16\000VHADDsv8i8\000VHADDuv16i8\000VHADDuv2"
+ "i32\000VHADDuv4i16\000VHADDuv4i32\000VHADDuv8i16\000VHADDuv8i8\000VHSUB"
+ "sv16i8\000VHSUBsv2i32\000VHSUBsv4i16\000VHSUBsv4i32\000VHSUBsv8i16\000V"
+ "HSUBsv8i8\000VHSUBuv16i8\000VHSUBuv2i32\000VHSUBuv4i16\000VHSUBuv4i32\000"
+ "VHSUBuv8i16\000VHSUBuv8i8\000VLD1d16\000VLD1d32\000VLD1d64\000VLD1d8\000"
+ "VLD1df\000VLD1q16\000VLD1q32\000VLD1q64\000VLD1q8\000VLD1qf\000VLD2LNd1"
+ "6\000VLD2LNd32\000VLD2LNd8\000VLD2LNq16a\000VLD2LNq16b\000VLD2LNq32a\000"
+ "VLD2LNq32b\000VLD2d16\000VLD2d32\000VLD2d64\000VLD2d8\000VLD2q16\000VLD"
+ "2q32\000VLD2q8\000VLD3LNd16\000VLD3LNd32\000VLD3LNd8\000VLD3LNq16a\000V"
+ "LD3LNq16b\000VLD3LNq32a\000VLD3LNq32b\000VLD3d16\000VLD3d32\000VLD3d64\000"
+ "VLD3d8\000VLD3q16a\000VLD3q16b\000VLD3q32a\000VLD3q32b\000VLD3q8a\000VL"
+ "D3q8b\000VLD4LNd16\000VLD4LNd32\000VLD4LNd8\000VLD4LNq16a\000VLD4LNq16b"
+ "\000VLD4LNq32a\000VLD4LNq32b\000VLD4d16\000VLD4d32\000VLD4d64\000VLD4d8"
+ "\000VLD4q16a\000VLD4q16b\000VLD4q32a\000VLD4q32b\000VLD4q8a\000VLD4q8b\000"
+ "VLDMD\000VLDMS\000VLDRD\000VLDRQ\000VLDRS\000VMAXfd\000VMAXfq\000VMAXsv"
+ "16i8\000VMAXsv2i32\000VMAXsv4i16\000VMAXsv4i32\000VMAXsv8i16\000VMAXsv8"
+ "i8\000VMAXuv16i8\000VMAXuv2i32\000VMAXuv4i16\000VMAXuv4i32\000VMAXuv8i1"
+ "6\000VMAXuv8i8\000VMINfd\000VMINfq\000VMINsv16i8\000VMINsv2i32\000VMINs"
+ "v4i16\000VMINsv4i32\000VMINsv8i16\000VMINsv8i8\000VMINuv16i8\000VMINuv2"
+ "i32\000VMINuv4i16\000VMINuv4i32\000VMINuv8i16\000VMINuv8i8\000VMLAD\000"
+ "VMLALslsv2i32\000VMLALslsv4i16\000VMLALsluv2i32\000VMLALsluv4i16\000VML"
+ "ALsv2i64\000VMLALsv4i32\000VMLALsv8i16\000VMLALuv2i64\000VMLALuv4i32\000"
+ "VMLALuv8i16\000VMLAS\000VMLAfd\000VMLAfq\000VMLAslfd\000VMLAslfq\000VML"
+ "Aslv2i32\000VMLAslv4i16\000VMLAslv4i32\000VMLAslv8i16\000VMLAv16i8\000V"
+ "MLAv2i32\000VMLAv4i16\000VMLAv4i32\000VMLAv8i16\000VMLAv8i8\000VMLSD\000"
+ "VMLSLslsv2i32\000VMLSLslsv4i16\000VMLSLsluv2i32\000VMLSLsluv4i16\000VML"
+ "SLsv2i64\000VMLSLsv4i32\000VMLSLsv8i16\000VMLSLuv2i64\000VMLSLuv4i32\000"
+ "VMLSLuv8i16\000VMLSS\000VMLSfd\000VMLSfq\000VMLSslfd\000VMLSslfq\000VML"
+ "Sslv2i32\000VMLSslv4i16\000VMLSslv4i32\000VMLSslv8i16\000VMLSv16i8\000V"
+ "MLSv2i32\000VMLSv4i16\000VMLSv4i32\000VMLSv8i16\000VMLSv8i8\000VMOVD\000"
+ "VMOVDRR\000VMOVDcc\000VMOVDneon\000VMOVLsv2i64\000VMOVLsv4i32\000VMOVLs"
+ "v8i16\000VMOVLuv2i64\000VMOVLuv4i32\000VMOVLuv8i16\000VMOVNv2i32\000VMO"
+ "VNv4i16\000VMOVNv8i8\000VMOVQ\000VMOVRRD\000VMOVRRS\000VMOVRS\000VMOVS\000"
+ "VMOVSR\000VMOVSRR\000VMOVScc\000VMOVv16i8\000VMOVv1i64\000VMOVv2i32\000"
+ "VMOVv2i64\000VMOVv4i16\000VMOVv4i32\000VMOVv8i16\000VMOVv8i8\000VMRS\000"
+ "VMSR\000VMULD\000VMULLp\000VMULLslsv2i32\000VMULLslsv4i16\000VMULLsluv2"
+ "i32\000VMULLsluv4i16\000VMULLsv2i64\000VMULLsv4i32\000VMULLsv8i16\000VM"
+ "ULLuv2i64\000VMULLuv4i32\000VMULLuv8i16\000VMULS\000VMULfd\000VMULfd_sf"
+ "p\000VMULfq\000VMULpd\000VMULpq\000VMULslfd\000VMULslfq\000VMULslv2i32\000"
+ "VMULslv4i16\000VMULslv4i32\000VMULslv8i16\000VMULv16i8\000VMULv2i32\000"
+ "VMULv4i16\000VMULv4i32\000VMULv8i16\000VMULv8i8\000VMVNd\000VMVNq\000VN"
+ "EGD\000VNEGDcc\000VNEGS\000VNEGScc\000VNEGf32d\000VNEGf32d_sfp\000VNEGf"
+ "32q\000VNEGs16d\000VNEGs16q\000VNEGs32d\000VNEGs32q\000VNEGs8d\000VNEGs"
+ "8q\000VNMLAD\000VNMLAS\000VNMLSD\000VNMLSS\000VNMULD\000VNMULS\000VORNd"
+ "\000VORNq\000VORRd\000VORRq\000VPADALsv16i8\000VPADALsv2i32\000VPADALsv"
+ "4i16\000VPADALsv4i32\000VPADALsv8i16\000VPADALsv8i8\000VPADALuv16i8\000"
+ "VPADALuv2i32\000VPADALuv4i16\000VPADALuv4i32\000VPADALuv8i16\000VPADALu"
+ "v8i8\000VPADDLsv16i8\000VPADDLsv2i32\000VPADDLsv4i16\000VPADDLsv4i32\000"
+ "VPADDLsv8i16\000VPADDLsv8i8\000VPADDLuv16i8\000VPADDLuv2i32\000VPADDLuv"
+ "4i16\000VPADDLuv4i32\000VPADDLuv8i16\000VPADDLuv8i8\000VPADDf\000VPADDi"
+ "16\000VPADDi32\000VPADDi8\000VPMAXf\000VPMAXs16\000VPMAXs32\000VPMAXs8\000"
+ "VPMAXu16\000VPMAXu32\000VPMAXu8\000VPMINf\000VPMINs16\000VPMINs32\000VP"
+ "MINs8\000VPMINu16\000VPMINu32\000VPMINu8\000VQABSv16i8\000VQABSv2i32\000"
+ "VQABSv4i16\000VQABSv4i32\000VQABSv8i16\000VQABSv8i8\000VQADDsv16i8\000V"
+ "QADDsv1i64\000VQADDsv2i32\000VQADDsv2i64\000VQADDsv4i16\000VQADDsv4i32\000"
+ "VQADDsv8i16\000VQADDsv8i8\000VQADDuv16i8\000VQADDuv1i64\000VQADDuv2i32\000"
+ "VQADDuv2i64\000VQADDuv4i16\000VQADDuv4i32\000VQADDuv8i16\000VQADDuv8i8\000"
+ "VQDMLALslv2i32\000VQDMLALslv4i16\000VQDMLALv2i64\000VQDMLALv4i32\000VQD"
+ "MLSLslv2i32\000VQDMLSLslv4i16\000VQDMLSLv2i64\000VQDMLSLv4i32\000VQDMUL"
+ "Hslv2i32\000VQDMULHslv4i16\000VQDMULHslv4i32\000VQDMULHslv8i16\000VQDMU"
+ "LHv2i32\000VQDMULHv4i16\000VQDMULHv4i32\000VQDMULHv8i16\000VQDMULLslv2i"
+ "32\000VQDMULLslv4i16\000VQDMULLv2i64\000VQDMULLv4i32\000VQMOVNsuv2i32\000"
+ "VQMOVNsuv4i16\000VQMOVNsuv8i8\000VQMOVNsv2i32\000VQMOVNsv4i16\000VQMOVN"
+ "sv8i8\000VQMOVNuv2i32\000VQMOVNuv4i16\000VQMOVNuv8i8\000VQNEGv16i8\000V"
+ "QNEGv2i32\000VQNEGv4i16\000VQNEGv4i32\000VQNEGv8i16\000VQNEGv8i8\000VQR"
+ "DMULHslv2i32\000VQRDMULHslv4i16\000VQRDMULHslv4i32\000VQRDMULHslv8i16\000"
+ "VQRDMULHv2i32\000VQRDMULHv4i16\000VQRDMULHv4i32\000VQRDMULHv8i16\000VQR"
+ "SHLsv16i8\000VQRSHLsv1i64\000VQRSHLsv2i32\000VQRSHLsv2i64\000VQRSHLsv4i"
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+ "RSHLuv1i64\000VQRSHLuv2i32\000VQRSHLuv2i64\000VQRSHLuv4i16\000VQRSHLuv4"
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+ "VQRSHRNsv8i8\000VQRSHRNuv2i32\000VQRSHRNuv4i16\000VQRSHRNuv8i8\000VQRSH"
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+ "QSHLsiv8i16\000VQSHLsiv8i8\000VQSHLsuv16i8\000VQSHLsuv1i64\000VQSHLsuv2"
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+ "VQSHLsuv8i8\000VQSHLsv16i8\000VQSHLsv1i64\000VQSHLsv2i32\000VQSHLsv2i64"
+ "\000VQSHLsv4i16\000VQSHLsv4i32\000VQSHLsv8i16\000VQSHLsv8i8\000VQSHLuiv"
+ "16i8\000VQSHLuiv1i64\000VQSHLuiv2i32\000VQSHLuiv2i64\000VQSHLuiv4i16\000"
+ "VQSHLuiv4i32\000VQSHLuiv8i16\000VQSHLuiv8i8\000VQSHLuv16i8\000VQSHLuv1i"
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+ "uv8i16\000VQSHLuv8i8\000VQSHRNsv2i32\000VQSHRNsv4i16\000VQSHRNsv8i8\000"
+ "VQSHRNuv2i32\000VQSHRNuv4i16\000VQSHRNuv8i8\000VQSHRUNv2i32\000VQSHRUNv"
+ "4i16\000VQSHRUNv8i8\000VQSUBsv16i8\000VQSUBsv1i64\000VQSUBsv2i32\000VQS"
+ "UBsv2i64\000VQSUBsv4i16\000VQSUBsv4i32\000VQSUBsv8i16\000VQSUBsv8i8\000"
+ "VQSUBuv16i8\000VQSUBuv1i64\000VQSUBuv2i32\000VQSUBuv2i64\000VQSUBuv4i16"
+ "\000VQSUBuv4i32\000VQSUBuv8i16\000VQSUBuv8i8\000VRADDHNv2i32\000VRADDHN"
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+ "VREV32q16\000VREV32q8\000VREV64d16\000VREV64d32\000VREV64d8\000VREV64df"
+ "\000VREV64q16\000VREV64q32\000VREV64q8\000VREV64qf\000VRHADDsv16i8\000V"
+ "RHADDsv2i32\000VRHADDsv4i16\000VRHADDsv4i32\000VRHADDsv8i16\000VRHADDsv"
+ "8i8\000VRHADDuv16i8\000VRHADDuv2i32\000VRHADDuv4i16\000VRHADDuv4i32\000"
+ "VRHADDuv8i16\000VRHADDuv8i8\000VRSHLsv16i8\000VRSHLsv1i64\000VRSHLsv2i3"
+ "2\000VRSHLsv2i64\000VRSHLsv4i16\000VRSHLsv4i32\000VRSHLsv8i16\000VRSHLs"
+ "v8i8\000VRSHLuv16i8\000VRSHLuv1i64\000VRSHLuv2i32\000VRSHLuv2i64\000VRS"
+ "HLuv4i16\000VRSHLuv4i32\000VRSHLuv8i16\000VRSHLuv8i8\000VRSHRNv2i32\000"
+ "VRSHRNv4i16\000VRSHRNv8i8\000VRSHRsv16i8\000VRSHRsv1i64\000VRSHRsv2i32\000"
+ "VRSHRsv2i64\000VRSHRsv4i16\000VRSHRsv4i32\000VRSHRsv8i16\000VRSHRsv8i8\000"
+ "VRSHRuv16i8\000VRSHRuv1i64\000VRSHRuv2i32\000VRSHRuv2i64\000VRSHRuv4i16"
+ "\000VRSHRuv4i32\000VRSHRuv8i16\000VRSHRuv8i8\000VRSQRTEd\000VRSQRTEfd\000"
+ "VRSQRTEfq\000VRSQRTEq\000VRSQRTSfd\000VRSQRTSfq\000VRSRAsv16i8\000VRSRA"
+ "sv1i64\000VRSRAsv2i32\000VRSRAsv2i64\000VRSRAsv4i16\000VRSRAsv4i32\000V"
+ "RSRAsv8i16\000VRSRAsv8i8\000VRSRAuv16i8\000VRSRAuv1i64\000VRSRAuv2i32\000"
+ "VRSRAuv2i64\000VRSRAuv4i16\000VRSRAuv4i32\000VRSRAuv8i16\000VRSRAuv8i8\000"
+ "VRSUBHNv2i32\000VRSUBHNv4i16\000VRSUBHNv8i8\000VSETLNi16\000VSETLNi32\000"
+ "VSETLNi8\000VSHLLi16\000VSHLLi32\000VSHLLi8\000VSHLLsv2i64\000VSHLLsv4i"
+ "32\000VSHLLsv8i16\000VSHLLuv2i64\000VSHLLuv4i32\000VSHLLuv8i16\000VSHLi"
+ "v16i8\000VSHLiv1i64\000VSHLiv2i32\000VSHLiv2i64\000VSHLiv4i16\000VSHLiv"
+ "4i32\000VSHLiv8i16\000VSHLiv8i8\000VSHLsv16i8\000VSHLsv1i64\000VSHLsv2i"
+ "32\000VSHLsv2i64\000VSHLsv4i16\000VSHLsv4i32\000VSHLsv8i16\000VSHLsv8i8"
+ "\000VSHLuv16i8\000VSHLuv1i64\000VSHLuv2i32\000VSHLuv2i64\000VSHLuv4i16\000"
+ "VSHLuv4i32\000VSHLuv8i16\000VSHLuv8i8\000VSHRNv2i32\000VSHRNv4i16\000VS"
+ "HRNv8i8\000VSHRsv16i8\000VSHRsv1i64\000VSHRsv2i32\000VSHRsv2i64\000VSHR"
+ "sv4i16\000VSHRsv4i32\000VSHRsv8i16\000VSHRsv8i8\000VSHRuv16i8\000VSHRuv"
+ "1i64\000VSHRuv2i32\000VSHRuv2i64\000VSHRuv4i16\000VSHRuv4i32\000VSHRuv8"
+ "i16\000VSHRuv8i8\000VSHTOD\000VSHTOS\000VSITOD\000VSITOS\000VSLIv16i8\000"
+ "VSLIv1i64\000VSLIv2i32\000VSLIv2i64\000VSLIv4i16\000VSLIv4i32\000VSLIv8"
+ "i16\000VSLIv8i8\000VSLTOD\000VSLTOS\000VSQRTD\000VSQRTS\000VSRAsv16i8\000"
+ "VSRAsv1i64\000VSRAsv2i32\000VSRAsv2i64\000VSRAsv4i16\000VSRAsv4i32\000V"
+ "SRAsv8i16\000VSRAsv8i8\000VSRAuv16i8\000VSRAuv1i64\000VSRAuv2i32\000VSR"
+ "Auv2i64\000VSRAuv4i16\000VSRAuv4i32\000VSRAuv8i16\000VSRAuv8i8\000VSRIv"
+ "16i8\000VSRIv1i64\000VSRIv2i32\000VSRIv2i64\000VSRIv4i16\000VSRIv4i32\000"
+ "VSRIv8i16\000VSRIv8i8\000VST1d16\000VST1d32\000VST1d64\000VST1d8\000VST"
+ "1df\000VST1q16\000VST1q32\000VST1q64\000VST1q8\000VST1qf\000VST2LNd16\000"
+ "VST2LNd32\000VST2LNd8\000VST2LNq16a\000VST2LNq16b\000VST2LNq32a\000VST2"
+ "LNq32b\000VST2d16\000VST2d32\000VST2d64\000VST2d8\000VST2q16\000VST2q32"
+ "\000VST2q8\000VST3LNd16\000VST3LNd32\000VST3LNd8\000VST3LNq16a\000VST3L"
+ "Nq16b\000VST3LNq32a\000VST3LNq32b\000VST3d16\000VST3d32\000VST3d64\000V"
+ "ST3d8\000VST3q16a\000VST3q16b\000VST3q32a\000VST3q32b\000VST3q8a\000VST"
+ "3q8b\000VST4LNd16\000VST4LNd32\000VST4LNd8\000VST4LNq16a\000VST4LNq16b\000"
+ "VST4LNq32a\000VST4LNq32b\000VST4d16\000VST4d32\000VST4d64\000VST4d8\000"
+ "VST4q16a\000VST4q16b\000VST4q32a\000VST4q32b\000VST4q8a\000VST4q8b\000V"
+ "STMD\000VSTMS\000VSTRD\000VSTRQ\000VSTRS\000VSUBD\000VSUBHNv2i32\000VSU"
+ "BHNv4i16\000VSUBHNv8i8\000VSUBLsv2i64\000VSUBLsv4i32\000VSUBLsv8i16\000"
+ "VSUBLuv2i64\000VSUBLuv4i32\000VSUBLuv8i16\000VSUBS\000VSUBWsv2i64\000VS"
+ "UBWsv4i32\000VSUBWsv8i16\000VSUBWuv2i64\000VSUBWuv4i32\000VSUBWuv8i16\000"
+ "VSUBfd\000VSUBfd_sfp\000VSUBfq\000VSUBv16i8\000VSUBv1i64\000VSUBv2i32\000"
+ "VSUBv2i64\000VSUBv4i16\000VSUBv4i32\000VSUBv8i16\000VSUBv8i8\000VTBL1\000"
+ "VTBL2\000VTBL3\000VTBL4\000VTBX1\000VTBX2\000VTBX3\000VTBX4\000VTOSHD\000"
+ "VTOSHS\000VTOSIRD\000VTOSIRS\000VTOSIZD\000VTOSIZS\000VTOSLD\000VTOSLS\000"
+ "VTOUHD\000VTOUHS\000VTOUIRD\000VTOUIRS\000VTOUIZD\000VTOUIZS\000VTOULD\000"
+ "VTOULS\000VTRNd16\000VTRNd32\000VTRNd8\000VTRNq16\000VTRNq32\000VTRNq8\000"
+ "VTSTv16i8\000VTSTv2i32\000VTSTv4i16\000VTSTv4i32\000VTSTv8i16\000VTSTv8"
+ "i8\000VUHTOD\000VUHTOS\000VUITOD\000VUITOS\000VULTOD\000VULTOS\000VUZPd"
+ "16\000VUZPd32\000VUZPd8\000VUZPq16\000VUZPq32\000VUZPq8\000VZIPd16\000V"
+ "ZIPd32\000VZIPd8\000VZIPq16\000VZIPq32\000VZIPq8\000WFE\000WFI\000YIELD"
+ "\000t2ADCSri\000t2ADCSrr\000t2ADCSrs\000t2ADCri\000t2ADCrr\000t2ADCrs\000"
+ "t2ADDSri\000t2ADDSrr\000t2ADDSrs\000t2ADDrSPi\000t2ADDrSPi12\000t2ADDrS"
+ "Ps\000t2ADDri\000t2ADDri12\000t2ADDrr\000t2ADDrs\000t2ANDri\000t2ANDrr\000"
+ "t2ANDrs\000t2ASRri\000t2ASRrr\000t2B\000t2BFC\000t2BFI\000t2BICri\000t2"
+ "BICrr\000t2BICrs\000t2BR_JT\000t2Bcc\000t2CLZ\000t2CMNzri\000t2CMNzrr\000"
+ "t2CMNzrs\000t2CMPri\000t2CMPrr\000t2CMPrs\000t2CMPzri\000t2CMPzrr\000t2"
+ "CMPzrs\000t2EORri\000t2EORrr\000t2EORrs\000t2IT\000t2Int_MemBarrierV7\000"
+ "t2Int_SyncBarrierV7\000t2Int_eh_sjlj_setjmp\000t2LDM\000t2LDM_RET\000t2"
+ "LDRB_POST\000t2LDRB_PRE\000t2LDRBi12\000t2LDRBi8\000t2LDRBpci\000t2LDRB"
+ "s\000t2LDRDi8\000t2LDRDpci\000t2LDREX\000t2LDREXB\000t2LDREXD\000t2LDRE"
+ "XH\000t2LDRH_POST\000t2LDRH_PRE\000t2LDRHi12\000t2LDRHi8\000t2LDRHpci\000"
+ "t2LDRHs\000t2LDRSB_POST\000t2LDRSB_PRE\000t2LDRSBi12\000t2LDRSBi8\000t2"
+ "LDRSBpci\000t2LDRSBs\000t2LDRSH_POST\000t2LDRSH_PRE\000t2LDRSHi12\000t2"
+ "LDRSHi8\000t2LDRSHpci\000t2LDRSHs\000t2LDR_POST\000t2LDR_PRE\000t2LDRi1"
+ "2\000t2LDRi8\000t2LDRpci\000t2LDRpci_pic\000t2LDRs\000t2LEApcrel\000t2L"
+ "EApcrelJT\000t2LSLri\000t2LSLrr\000t2LSRri\000t2LSRrr\000t2MLA\000t2MLS"
+ "\000t2MOVCCasr\000t2MOVCCi\000t2MOVCClsl\000t2MOVCClsr\000t2MOVCCr\000t"
+ "2MOVCCror\000t2MOVTi16\000t2MOVi\000t2MOVi16\000t2MOVi32imm\000t2MOVr\000"
+ "t2MOVrx\000t2MOVsra_flag\000t2MOVsrl_flag\000t2MUL\000t2MVNi\000t2MVNr\000"
+ "t2MVNs\000t2ORNri\000t2ORNrr\000t2ORNrs\000t2ORRri\000t2ORRrr\000t2ORRr"
+ "s\000t2PKHBT\000t2PKHTB\000t2RBIT\000t2REV\000t2REV16\000t2REVSH\000t2R"
+ "ORri\000t2RORrr\000t2RSBSri\000t2RSBSrs\000t2RSBri\000t2RSBrs\000t2SBCS"
+ "ri\000t2SBCSrr\000t2SBCSrs\000t2SBCri\000t2SBCrr\000t2SBCrs\000t2SBFX\000"
+ "t2SMLABB\000t2SMLABT\000t2SMLAL\000t2SMLATB\000t2SMLATT\000t2SMLAWB\000"
+ "t2SMLAWT\000t2SMMLA\000t2SMMLS\000t2SMMUL\000t2SMULBB\000t2SMULBT\000t2"
+ "SMULL\000t2SMULTB\000t2SMULTT\000t2SMULWB\000t2SMULWT\000t2STM\000t2STR"
+ "B_POST\000t2STRB_PRE\000t2STRBi12\000t2STRBi8\000t2STRBs\000t2STRDi8\000"
+ "t2STREX\000t2STREXB\000t2STREXD\000t2STREXH\000t2STRH_POST\000t2STRH_PR"
+ "E\000t2STRHi12\000t2STRHi8\000t2STRHs\000t2STR_POST\000t2STR_PRE\000t2S"
+ "TRi12\000t2STRi8\000t2STRs\000t2SUBSri\000t2SUBSrr\000t2SUBSrs\000t2SUB"
+ "rSPi\000t2SUBrSPi12\000t2SUBrSPi12_\000t2SUBrSPi_\000t2SUBrSPs\000t2SUB"
+ "rSPs_\000t2SUBri\000t2SUBri12\000t2SUBrr\000t2SUBrs\000t2SXTABrr\000t2S"
+ "XTABrr_rot\000t2SXTAHrr\000t2SXTAHrr_rot\000t2SXTBr\000t2SXTBr_rot\000t"
+ "2SXTHr\000t2SXTHr_rot\000t2TBB\000t2TBH\000t2TEQri\000t2TEQrr\000t2TEQr"
+ "s\000t2TPsoft\000t2TSTri\000t2TSTrr\000t2TSTrs\000t2UBFX\000t2UMAAL\000"
+ "t2UMLAL\000t2UMULL\000t2UXTABrr\000t2UXTABrr_rot\000t2UXTAHrr\000t2UXTA"
+ "Hrr_rot\000t2UXTB16r\000t2UXTB16r_rot\000t2UXTBr\000t2UXTBr_rot\000t2UX"
+ "THr\000t2UXTHr_rot\000tADC\000tADDhirr\000tADDi3\000tADDi8\000tADDrPCi\000"
+ "tADDrSP\000tADDrSPi\000tADDrr\000tADDspi\000tADDspr\000tADDspr_\000tADJ"
+ "CALLSTACKDOWN\000tADJCALLSTACKUP\000tAND\000tANDsp\000tASRri\000tASRrr\000"
+ "tB\000tBIC\000tBKPT\000tBL\000tBLXi\000tBLXi_r9\000tBLXr\000tBLXr_r9\000"
+ "tBLr9\000tBRIND\000tBR_JTr\000tBX\000tBX_RET\000tBX_RET_vararg\000tBXr9"
+ "\000tBcc\000tBfar\000tCBNZ\000tCBZ\000tCMNz\000tCMPhir\000tCMPi8\000tCM"
+ "Pr\000tCMPzhir\000tCMPzi8\000tCMPzr\000tEOR\000tInt_eh_sjlj_setjmp\000t"
+ "LDM\000tLDR\000tLDRB\000tLDRBi\000tLDRH\000tLDRHi\000tLDRSB\000tLDRSH\000"
+ "tLDRcp\000tLDRi\000tLDRpci\000tLDRpci_pic\000tLDRspi\000tLEApcrel\000tL"
+ "EApcrelJT\000tLSLri\000tLSLrr\000tLSRri\000tLSRrr\000tMOVCCi\000tMOVCCr"
+ "\000tMOVCCr_pseudo\000tMOVSr\000tMOVgpr2gpr\000tMOVgpr2tgpr\000tMOVi8\000"
+ "tMOVr\000tMOVtgpr2gpr\000tMUL\000tMVN\000tORR\000tPICADD\000tPOP\000tPO"
+ "P_RET\000tPUSH\000tREV\000tREV16\000tREVSH\000tROR\000tRSB\000tRestore\000"
+ "tSBC\000tSTM\000tSTR\000tSTRB\000tSTRBi\000tSTRH\000tSTRHi\000tSTRi\000"
+ "tSTRspi\000tSUBi3\000tSUBi8\000tSUBrr\000tSUBspi\000tSUBspi_\000tSXTB\000"
+ "tSXTH\000tSpill\000tTPsoft\000tTST\000tUXTB\000tUXTH\000";
+ return Strs+InstAsmOffset[Opcode];
+}
+
+#endif
diff --git a/libclamav/c++/ARMGenCodeEmitter.inc b/libclamav/c++/ARMGenCodeEmitter.inc
index a10485a..8ba99a8 100644
--- a/libclamav/c++/ARMGenCodeEmitter.inc
+++ b/libclamav/c++/ARMGenCodeEmitter.inc
@@ -66,6 +66,7 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
62914560U, // BICri
29360128U, // BICrr
29360128U, // BICrs
+ 18874480U, // BKPT
3942645760U, // BL
19922736U, // BLX
19922736U, // BLXr9
@@ -77,9 +78,12 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
118550528U, // BR_JTm
27324416U, // BR_JTr
19922704U, // BX
+ 18874400U, // BXJ
19922718U, // BX_RET
19922704U, // BXr9
167772160U, // Bcc
+ 234881024U, // CDP
+ 4261412864U, // CDP2
24055568U, // CLZ
57671680U, // CMNzri
24117248U, // CMNzrr
@@ -91,6 +95,8 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
22020096U, // CMPzrr
22020096U, // CMPzrs
0U, // CONSTPOOL_ENTRY
+ 4043309056U, // CPS
+ 52429040U, // DBG
35651584U, // EORri
2097152U, // EORrr
2097152U, // EORrs
@@ -106,6 +112,7 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
135266304U, // LDM_RET
84934656U, // LDR
89128960U, // LDRB
+ 74448896U, // LDRBT
72351744U, // LDRB_POST
91226112U, // LDRB_PRE
16777424U, // LDRD
@@ -122,11 +129,16 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
17826032U, // LDRSH
3145968U, // LDRSH_POST
19923184U, // LDRSH_PRE
+ 70254592U, // LDRT
68157440U, // LDR_POST
87031808U, // LDR_PRE
84934656U, // LDRcp
0U, // LEApcrel
33554432U, // LEApcrelJT
+ 234881040U, // MCR
+ 4261412880U, // MCR2
+ 205520896U, // MCRR
+ 4232052736U, // MCRR2
2097296U, // MLA
6291600U, // MLS
60817408U, // MOVCCi
@@ -142,10 +154,19 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
27262976U, // MOVs
27262976U, // MOVsra_flag
27262976U, // MOVsrl_flag
+ 235929616U, // MRC
+ 4262461456U, // MRC2
+ 206569472U, // MRRC
+ 4233101312U, // MRRC2
+ 16777216U, // MRS
+ 20971520U, // MRSsys
+ 18874368U, // MSR
+ 23068672U, // MSRsys
144U, // MUL
65011712U, // MVNi
31457280U, // MVNr
31457280U, // MVNs
+ 52428800U, // NOP
58720256U, // ORRri
25165824U, // ORRrr
25165824U, // ORRrs
@@ -160,6 +181,16 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
16777392U, // PICSTRH
109051920U, // PKHBT
109051984U, // PKHTB
+ 16777296U, // QADD
+ 102760464U, // QADD16
+ 102760592U, // QADD8
+ 102760496U, // QASX
+ 20971600U, // QDADD
+ 23068752U, // QDSUB
+ 102760528U, // QSAX
+ 18874448U, // QSUB
+ 102760560U, // QSUB16
+ 102760688U, // QSUB8
117378864U, // RBIT
113184560U, // REV
113184688U, // REV16
@@ -179,9 +210,16 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
12582912U, // SBCrr
12582912U, // SBCrs
127926352U, // SBFX
+ 4043375104U, // SETENDBE
+ 4043374592U, // SETENDLE
+ 52428804U, // SEV
16777344U, // SMLABB
16777408U, // SMLABT
14680208U, // SMLAL
+ 20971648U, // SMLALBB
+ 20971712U, // SMLALBT
+ 20971680U, // SMLALTB
+ 20971744U, // SMLALTT
16777376U, // SMLATB
16777440U, // SMLATT
18874496U, // SMLAWB
@@ -199,6 +237,7 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
134217728U, // STM
83886080U, // STR
88080384U, // STRB
+ 73400320U, // STRBT
71303168U, // STRB_POST
90177536U, // STRB_PRE
16777456U, // STRD
@@ -209,6 +248,7 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
16777392U, // STRH
2097328U, // STRH_POST
18874544U, // STRH_PRE
+ 69206016U, // STRT
67108864U, // STR_POST
85983232U, // STR_PRE
38797312U, // SUBSri
@@ -217,6 +257,9 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
37748736U, // SUBri
4194304U, // SUBrr
4194304U, // SUBrs
+ 251658240U, // SVC
+ 16777360U, // SWP
+ 20971664U, // SWPB
111149168U, // SXTABrr
111149168U, // SXTABrr_rot
112197744U, // SXTAHrr
@@ -229,6 +272,7 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
19922944U, // TEQrr
19922944U, // TEQrs
184549376U, // TPsoft
+ 133169392U, // TRAP
51380224U, // TSTri
17825792U, // TSTrr
17825792U, // TSTrs
@@ -236,6 +280,12 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
4194448U, // UMAAL
10485904U, // UMLAL
8388752U, // UMULL
+ 106954768U, // UQADD16
+ 106954896U, // UQADD8
+ 106954800U, // UQASX
+ 106954832U, // UQSAX
+ 106954864U, // UQSUB16
+ 106954992U, // UQSUB8
115343472U, // UXTABrr
115343472U, // UXTABrr_rot
116392048U, // UXTAHrr
@@ -331,6 +381,10 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
4060086608U, // VANDq
4061135120U, // VBICd
4061135184U, // VBICq
+ 4080009488U, // VBIFd
+ 4080009552U, // VBIFq
+ 4078960912U, // VBITd
+ 4078960976U, // VBITq
4077912336U, // VBSLd
4077912400U, // VBSLq
4060089856U, // VCEQfd
@@ -381,14 +435,22 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
4088923328U, // VCLZv4i32
4088661184U, // VCLZv8i16
4088398976U, // VCLZv8i8
+ 246680384U, // VCMPD
246680512U, // VCMPED
246680256U, // VCMPES
246746048U, // VCMPEZD
246745792U, // VCMPEZS
+ 246680128U, // VCMPS
+ 246745920U, // VCMPZD
+ 246745664U, // VCMPZS
4088399104U, // VCNTd
4088399168U, // VCNTq
+ 246614592U, // VCVTBHS
+ 246549056U, // VCVTBSH
246876864U, // VCVTDS
246877120U, // VCVTSD
+ 246614720U, // VCVTTHS
+ 246549184U, // VCVTTSH
4089120512U, // VCVTf2sd
4089120512U, // VCVTf2sd_sfp
4089120576U, // VCVTf2sq
@@ -626,9 +688,11 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
4088529408U, // VMOVNv8i8
4062183760U, // VMOVQ
206572304U, // VMOVRRD
+ 206572048U, // VMOVRRS
235932176U, // VMOVRS
246417984U, // VMOVS
234883600U, // VMOVSR
+ 205523472U, // VMOVSRR
246417984U, // VMOVScc
4068478544U, // VMOVv16i8
4068478512U, // VMOVv1i64
@@ -638,6 +702,8 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
4068474960U, // VMOVv4i32
4068477008U, // VMOVv8i16
4068478480U, // VMOVv8i8
+ 250677776U, // VMRS
+ 249629200U, // VMSR
236980992U, // VMULD
4068478464U, // VMULLp
4070574656U, // VMULLslsv2i32
@@ -1040,6 +1106,8 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
4087349328U, // VSHRuv4i32
4086300752U, // VSHRuv8i16
4085776400U, // VSHRuv8i8
+ 247073600U, // VSHTOD
+ 247073344U, // VSHTOS
246942656U, // VSITOD
246942400U, // VSITOS
4085777744U, // VSLIv16i8
@@ -1050,6 +1118,8 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
4087350608U, // VSLIv4i32
4086302032U, // VSLIv8i16
4085777680U, // VSLIv8i8
+ 247073728U, // VSLTOD
+ 247073472U, // VSLTOS
246483904U, // VSQRTD
246483648U, // VSQRTS
4068999504U, // VSRAsv16i8
@@ -1175,10 +1245,22 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
4088400192U, // VTBX2
4088400448U, // VTBX3
4088400704U, // VTBX4
+ 247335744U, // VTOSHD
+ 247335488U, // VTOSHS
+ 247270208U, // VTOSIRD
+ 247269952U, // VTOSIRS
247270336U, // VTOSIZD
247270080U, // VTOSIZS
+ 247335872U, // VTOSLD
+ 247335616U, // VTOSLS
+ 247401280U, // VTOUHD
+ 247401024U, // VTOUHS
+ 247204672U, // VTOUIRD
+ 247204416U, // VTOUIRS
247204800U, // VTOUIZD
247204544U, // VTOUIZS
+ 247401408U, // VTOULD
+ 247401152U, // VTOULS
4088791168U, // VTRNd16
4089053312U, // VTRNd32
4088529024U, // VTRNd8
@@ -1191,8 +1273,12 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
4062185552U, // VTSTv4i32
4061136976U, // VTSTv8i16
4060088336U, // VTSTv8i8
+ 247139136U, // VUHTOD
+ 247138880U, // VUHTOS
246942528U, // VUITOD
246942272U, // VUITOS
+ 247139264U, // VULTOD
+ 247139008U, // VULTOS
4088791296U, // VUZPd16
4089053440U, // VUZPd32
4088529152U, // VUZPd8
@@ -1205,6 +1291,9 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
4088791488U, // VZIPq16
4089053632U, // VZIPq32
4088529344U, // VZIPq8
+ 52428802U, // WFE
+ 52428803U, // WFI
+ 52428801U, // YIELD
4048551936U, // t2ADCSri
3947888640U, // t2ADCSrr
3947888640U, // t2ADCSrs
@@ -1228,6 +1317,7 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
4198559744U, // t2ASRrr
4026568704U, // t2B
4084137984U, // t2BFC
+ 4083154944U, // t2BFI
4028628992U, // t2BICri
3927965696U, // t2BICrr
3927965696U, // t2BICrs
@@ -1441,6 +1531,7 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
16640U, // tASRrr
57344U, // tB
17280U, // tBIC
+ 48640U, // tBKPT
4026585088U, // tBL
4026580992U, // tBLXi
4026580992U, // tBLXi_r9
@@ -1581,6 +1672,7 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::BICri:
case ARM::BICrr:
case ARM::BICrs:
+ case ARM::BKPT:
case ARM::BL:
case ARM::BLX:
case ARM::BLXr9:
@@ -1592,9 +1684,12 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::BR_JTm:
case ARM::BR_JTr:
case ARM::BX:
+ case ARM::BXJ:
case ARM::BX_RET:
case ARM::BXr9:
case ARM::Bcc:
+ case ARM::CDP:
+ case ARM::CDP2:
case ARM::CLZ:
case ARM::CMNzri:
case ARM::CMNzrr:
@@ -1606,6 +1701,8 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::CMPzrr:
case ARM::CMPzrs:
case ARM::CONSTPOOL_ENTRY:
+ case ARM::CPS:
+ case ARM::DBG:
case ARM::EORri:
case ARM::EORrr:
case ARM::EORrs:
@@ -1621,6 +1718,7 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::LDM_RET:
case ARM::LDR:
case ARM::LDRB:
+ case ARM::LDRBT:
case ARM::LDRB_POST:
case ARM::LDRB_PRE:
case ARM::LDRD:
@@ -1637,11 +1735,16 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::LDRSH:
case ARM::LDRSH_POST:
case ARM::LDRSH_PRE:
+ case ARM::LDRT:
case ARM::LDR_POST:
case ARM::LDR_PRE:
case ARM::LDRcp:
case ARM::LEApcrel:
case ARM::LEApcrelJT:
+ case ARM::MCR:
+ case ARM::MCR2:
+ case ARM::MCRR:
+ case ARM::MCRR2:
case ARM::MLA:
case ARM::MLS:
case ARM::MOVCCi:
@@ -1657,10 +1760,19 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::MOVs:
case ARM::MOVsra_flag:
case ARM::MOVsrl_flag:
+ case ARM::MRC:
+ case ARM::MRC2:
+ case ARM::MRRC:
+ case ARM::MRRC2:
+ case ARM::MRS:
+ case ARM::MRSsys:
+ case ARM::MSR:
+ case ARM::MSRsys:
case ARM::MUL:
case ARM::MVNi:
case ARM::MVNr:
case ARM::MVNs:
+ case ARM::NOP:
case ARM::ORRri:
case ARM::ORRrr:
case ARM::ORRrs:
@@ -1675,6 +1787,16 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::PICSTRH:
case ARM::PKHBT:
case ARM::PKHTB:
+ case ARM::QADD:
+ case ARM::QADD16:
+ case ARM::QADD8:
+ case ARM::QASX:
+ case ARM::QDADD:
+ case ARM::QDSUB:
+ case ARM::QSAX:
+ case ARM::QSUB:
+ case ARM::QSUB16:
+ case ARM::QSUB8:
case ARM::RBIT:
case ARM::REV:
case ARM::REV16:
@@ -1694,9 +1816,16 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::SBCrr:
case ARM::SBCrs:
case ARM::SBFX:
+ case ARM::SETENDBE:
+ case ARM::SETENDLE:
+ case ARM::SEV:
case ARM::SMLABB:
case ARM::SMLABT:
case ARM::SMLAL:
+ case ARM::SMLALBB:
+ case ARM::SMLALBT:
+ case ARM::SMLALTB:
+ case ARM::SMLALTT:
case ARM::SMLATB:
case ARM::SMLATT:
case ARM::SMLAWB:
@@ -1714,6 +1843,7 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::STM:
case ARM::STR:
case ARM::STRB:
+ case ARM::STRBT:
case ARM::STRB_POST:
case ARM::STRB_PRE:
case ARM::STRD:
@@ -1724,6 +1854,7 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::STRH:
case ARM::STRH_POST:
case ARM::STRH_PRE:
+ case ARM::STRT:
case ARM::STR_POST:
case ARM::STR_PRE:
case ARM::SUBSri:
@@ -1732,6 +1863,9 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::SUBri:
case ARM::SUBrr:
case ARM::SUBrs:
+ case ARM::SVC:
+ case ARM::SWP:
+ case ARM::SWPB:
case ARM::SXTABrr:
case ARM::SXTABrr_rot:
case ARM::SXTAHrr:
@@ -1744,6 +1878,7 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::TEQrr:
case ARM::TEQrs:
case ARM::TPsoft:
+ case ARM::TRAP:
case ARM::TSTri:
case ARM::TSTrr:
case ARM::TSTrs:
@@ -1751,6 +1886,12 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::UMAAL:
case ARM::UMLAL:
case ARM::UMULL:
+ case ARM::UQADD16:
+ case ARM::UQADD8:
+ case ARM::UQASX:
+ case ARM::UQSAX:
+ case ARM::UQSUB16:
+ case ARM::UQSUB8:
case ARM::UXTABrr:
case ARM::UXTABrr_rot:
case ARM::UXTAHrr:
@@ -1846,6 +1987,10 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::VANDq:
case ARM::VBICd:
case ARM::VBICq:
+ case ARM::VBIFd:
+ case ARM::VBIFq:
+ case ARM::VBITd:
+ case ARM::VBITq:
case ARM::VBSLd:
case ARM::VBSLq:
case ARM::VCEQfd:
@@ -1896,14 +2041,22 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::VCLZv4i32:
case ARM::VCLZv8i16:
case ARM::VCLZv8i8:
+ case ARM::VCMPD:
case ARM::VCMPED:
case ARM::VCMPES:
case ARM::VCMPEZD:
case ARM::VCMPEZS:
+ case ARM::VCMPS:
+ case ARM::VCMPZD:
+ case ARM::VCMPZS:
case ARM::VCNTd:
case ARM::VCNTq:
+ case ARM::VCVTBHS:
+ case ARM::VCVTBSH:
case ARM::VCVTDS:
case ARM::VCVTSD:
+ case ARM::VCVTTHS:
+ case ARM::VCVTTSH:
case ARM::VCVTf2sd:
case ARM::VCVTf2sd_sfp:
case ARM::VCVTf2sq:
@@ -2141,9 +2294,11 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::VMOVNv8i8:
case ARM::VMOVQ:
case ARM::VMOVRRD:
+ case ARM::VMOVRRS:
case ARM::VMOVRS:
case ARM::VMOVS:
case ARM::VMOVSR:
+ case ARM::VMOVSRR:
case ARM::VMOVScc:
case ARM::VMOVv16i8:
case ARM::VMOVv1i64:
@@ -2153,6 +2308,8 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::VMOVv4i32:
case ARM::VMOVv8i16:
case ARM::VMOVv8i8:
+ case ARM::VMRS:
+ case ARM::VMSR:
case ARM::VMULD:
case ARM::VMULLp:
case ARM::VMULLslsv2i32:
@@ -2555,6 +2712,8 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::VSHRuv4i32:
case ARM::VSHRuv8i16:
case ARM::VSHRuv8i8:
+ case ARM::VSHTOD:
+ case ARM::VSHTOS:
case ARM::VSITOD:
case ARM::VSITOS:
case ARM::VSLIv16i8:
@@ -2565,6 +2724,8 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::VSLIv4i32:
case ARM::VSLIv8i16:
case ARM::VSLIv8i8:
+ case ARM::VSLTOD:
+ case ARM::VSLTOS:
case ARM::VSQRTD:
case ARM::VSQRTS:
case ARM::VSRAsv16i8:
@@ -2690,10 +2851,22 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::VTBX2:
case ARM::VTBX3:
case ARM::VTBX4:
+ case ARM::VTOSHD:
+ case ARM::VTOSHS:
+ case ARM::VTOSIRD:
+ case ARM::VTOSIRS:
case ARM::VTOSIZD:
case ARM::VTOSIZS:
+ case ARM::VTOSLD:
+ case ARM::VTOSLS:
+ case ARM::VTOUHD:
+ case ARM::VTOUHS:
+ case ARM::VTOUIRD:
+ case ARM::VTOUIRS:
case ARM::VTOUIZD:
case ARM::VTOUIZS:
+ case ARM::VTOULD:
+ case ARM::VTOULS:
case ARM::VTRNd16:
case ARM::VTRNd32:
case ARM::VTRNd8:
@@ -2706,8 +2879,12 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::VTSTv4i32:
case ARM::VTSTv8i16:
case ARM::VTSTv8i8:
+ case ARM::VUHTOD:
+ case ARM::VUHTOS:
case ARM::VUITOD:
case ARM::VUITOS:
+ case ARM::VULTOD:
+ case ARM::VULTOS:
case ARM::VUZPd16:
case ARM::VUZPd32:
case ARM::VUZPd8:
@@ -2720,6 +2897,9 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::VZIPq16:
case ARM::VZIPq32:
case ARM::VZIPq8:
+ case ARM::WFE:
+ case ARM::WFI:
+ case ARM::YIELD:
case ARM::t2ADCSri:
case ARM::t2ADCSrr:
case ARM::t2ADCSrs:
@@ -2743,6 +2923,7 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::t2ASRrr:
case ARM::t2B:
case ARM::t2BFC:
+ case ARM::t2BFI:
case ARM::t2BICri:
case ARM::t2BICrr:
case ARM::t2BICrs:
@@ -2956,6 +3137,7 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::tASRrr:
case ARM::tB:
case ARM::tBIC:
+ case ARM::tBKPT:
case ARM::tBL:
case ARM::tBLXi:
case ARM::tBLXi_r9:
diff --git a/libclamav/c++/ARMGenDAGISel.inc b/libclamav/c++/ARMGenDAGISel.inc
index d9ed02b..5ba1ab4 100644
--- a/libclamav/c++/ARMGenDAGISel.inc
+++ b/libclamav/c++/ARMGenDAGISel.inc
@@ -2741,38 +2741,45 @@ SDNode *Select_ARMISD_CMPZ(SDNode *N) {
DISABLE_INLINE SDNode *Emit_29(SDNode *N, unsigned Opc0) {
SDValue N0 = N->getOperand(0);
- return CurDAG->SelectNodeTo(N, Opc0, MVT::i32, N0);
+ SDValue N1 = N->getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, MVT::i32, N0, N1);
}
SDNode *Select_ARMISD_EH_SJLJ_SETJMP_i32(SDNode *N) {
- // Pattern: (ARMeh_sjlj_setjmp:i32 GPR:i32:$src)
- // Emits: (Int_eh_sjlj_setjmp:isVoid GPR:i32:$src)
+ // Pattern: (ARMeh_sjlj_setjmp:i32 GPR:i32:$src, GPR:i32:$val)
+ // Emits: (Int_eh_sjlj_setjmp:isVoid GPR:i32:$src, GPR:i32:$val)
// Pattern complexity = 3 cost = 1 size = 0
if ((!Subtarget->isThumb())) {
SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::i32) {
+ SDValue N1 = N->getOperand(1);
+ if (N0.getValueType() == MVT::i32 &&
+ N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_29(N, ARM::Int_eh_sjlj_setjmp);
return Result;
}
}
- // Pattern: (ARMeh_sjlj_setjmp:i32 GPR:i32:$src)
- // Emits: (tInt_eh_sjlj_setjmp:isVoid GPR:i32:$src)
+ // Pattern: (ARMeh_sjlj_setjmp:i32 tGPR:i32:$src, tGPR:i32:$val)
+ // Emits: (tInt_eh_sjlj_setjmp:isVoid tGPR:i32:$src, tGPR:i32:$val)
// Pattern complexity = 3 cost = 1 size = 0
if ((Subtarget->isThumb1Only())) {
SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::i32) {
+ SDValue N1 = N->getOperand(1);
+ if (N0.getValueType() == MVT::i32 &&
+ N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_29(N, ARM::tInt_eh_sjlj_setjmp);
return Result;
}
}
- // Pattern: (ARMeh_sjlj_setjmp:i32 GPR:i32:$src)
- // Emits: (t2Int_eh_sjlj_setjmp:isVoid GPR:i32:$src)
+ // Pattern: (ARMeh_sjlj_setjmp:i32 GPR:i32:$src, tGPR:i32:$val)
+ // Emits: (t2Int_eh_sjlj_setjmp:isVoid GPR:i32:$src, tGPR:i32:$val)
// Pattern complexity = 3 cost = 1 size = 0
if ((Subtarget->isThumb2())) {
SDValue N0 = N->getOperand(0);
- if (N0.getValueType() == MVT::i32) {
+ SDValue N1 = N->getOperand(1);
+ if (N0.getValueType() == MVT::i32 &&
+ N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_29(N, ARM::t2Int_eh_sjlj_setjmp);
return Result;
}
@@ -2848,7 +2855,7 @@ SDNode *Select_ARMISD_FTOSI_f32(SDNode *N) {
if ((Subtarget->hasNEON()) && (Subtarget->useNEONForSinglePrecisionFP())) {
SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::f32) {
- SDNode *Result = Emit_32(N, TargetInstrInfo::IMPLICIT_DEF, TargetInstrInfo::INSERT_SUBREG, ARM::VCVTf2sd_sfp, TargetInstrInfo::EXTRACT_SUBREG, MVT::v2f32, MVT::f64, MVT::f64, MVT::f32);
+ SDNode *Result = Emit_32(N, TargetOpcode::IMPLICIT_DEF, TargetOpcode::INSERT_SUBREG, ARM::VCVTf2sd_sfp, TargetOpcode::EXTRACT_SUBREG, MVT::v2f32, MVT::f64, MVT::f64, MVT::f32);
return Result;
}
}
@@ -2887,7 +2894,7 @@ SDNode *Select_ARMISD_FTOUI_f32(SDNode *N) {
if ((Subtarget->hasNEON()) && (Subtarget->useNEONForSinglePrecisionFP())) {
SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::f32) {
- SDNode *Result = Emit_32(N, TargetInstrInfo::IMPLICIT_DEF, TargetInstrInfo::INSERT_SUBREG, ARM::VCVTf2ud_sfp, TargetInstrInfo::EXTRACT_SUBREG, MVT::v2f32, MVT::f64, MVT::f64, MVT::f32);
+ SDNode *Result = Emit_32(N, TargetOpcode::IMPLICIT_DEF, TargetOpcode::INSERT_SUBREG, ARM::VCVTf2ud_sfp, TargetOpcode::EXTRACT_SUBREG, MVT::v2f32, MVT::f64, MVT::f64, MVT::f32);
return Result;
}
}
@@ -2969,54 +2976,52 @@ DISABLE_INLINE SDNode *Emit_37(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT
return ResNode;
}
SDNode *Select_ARMISD_PIC_ADD_i32(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
- // Pattern: (ARMpic_add:i32 (ld:i32 (ARMWrapper:iPTR (tconstpool:iPTR):$addr))<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i32):$cp)
- // Emits: (tLDRpci_pic:i32 (tconstpool:i32):$addr, (imm:i32):$cp)
- // Pattern complexity = 16 cost = 1 size = 0
- if ((Subtarget->isThumb1Only())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ARMISD::Wrapper) {
- SDValue N010 = N01.getNode()->getOperand(0);
- if (N010.getNode()->getOpcode() == ISD::TargetConstantPool) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_37(N, ARM::tLDRpci_pic, MVT::i32);
- return Result;
- }
+ // Pattern: (ARMpic_add:i32 (ld:i32 (ARMWrapper:iPTR (tconstpool:iPTR):$addr))<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i32):$cp)
+ // Emits: (tLDRpci_pic:i32 (tconstpool:i32):$addr, (imm:i32):$cp)
+ // Pattern complexity = 16 cost = 1 size = 0
+ if ((Subtarget->isThumb1Only())) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ARMISD::Wrapper) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ if (N010.getNode()->getOpcode() == ISD::TargetConstantPool) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_37(N, ARM::tLDRpci_pic, MVT::i32);
+ return Result;
}
}
}
}
}
+ }
- // Pattern: (ARMpic_add:i32 (ld:i32 (ARMWrapper:iPTR (tconstpool:iPTR):$addr))<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i32):$cp)
- // Emits: (t2LDRpci_pic:i32 (tconstpool:i32):$addr, (imm:i32):$cp)
- // Pattern complexity = 16 cost = 1 size = 0
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ARMISD::Wrapper) {
- SDValue N010 = N01.getNode()->getOperand(0);
- if (N010.getNode()->getOpcode() == ISD::TargetConstantPool) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_37(N, ARM::t2LDRpci_pic, MVT::i32);
- return Result;
- }
+ // Pattern: (ARMpic_add:i32 (ld:i32 (ARMWrapper:iPTR (tconstpool:iPTR):$addr))<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i32):$cp)
+ // Emits: (t2LDRpci_pic:i32 (tconstpool:i32):$addr, (imm:i32):$cp)
+ // Pattern complexity = 16 cost = 1 size = 0
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ARMISD::Wrapper) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ if (N010.getNode()->getOpcode() == ISD::TargetConstantPool) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_37(N, ARM::t2LDRpci_pic, MVT::i32);
+ return Result;
}
}
}
@@ -3163,7 +3168,7 @@ SDNode *Select_ARMISD_SITOF_f32(SDNode *N) {
// Emits: (EXTRACT_SUBREG:f32 (VCVTs2fd_sfp:f64 (INSERT_SUBREG:f64 (IMPLICIT_DEF:v2i32), SPR:f32:$a, 1:i32)), 1:i32)
// Pattern complexity = 3 cost = 4 size = 0
if ((Subtarget->hasNEON()) && (Subtarget->useNEONForSinglePrecisionFP())) {
- SDNode *Result = Emit_32(N, TargetInstrInfo::IMPLICIT_DEF, TargetInstrInfo::INSERT_SUBREG, ARM::VCVTs2fd_sfp, TargetInstrInfo::EXTRACT_SUBREG, MVT::v2i32, MVT::f64, MVT::f64, MVT::f32);
+ SDNode *Result = Emit_32(N, TargetOpcode::IMPLICIT_DEF, TargetOpcode::INSERT_SUBREG, ARM::VCVTs2fd_sfp, TargetOpcode::EXTRACT_SUBREG, MVT::v2i32, MVT::f64, MVT::f64, MVT::f32);
return Result;
}
@@ -3322,7 +3327,7 @@ SDNode *Select_ARMISD_UITOF_f32(SDNode *N) {
// Emits: (EXTRACT_SUBREG:f32 (VCVTu2fd_sfp:f64 (INSERT_SUBREG:f64 (IMPLICIT_DEF:v2i32), SPR:f32:$a, 1:i32)), 1:i32)
// Pattern complexity = 3 cost = 4 size = 0
if ((Subtarget->hasNEON()) && (Subtarget->useNEONForSinglePrecisionFP())) {
- SDNode *Result = Emit_32(N, TargetInstrInfo::IMPLICIT_DEF, TargetInstrInfo::INSERT_SUBREG, ARM::VCVTu2fd_sfp, TargetInstrInfo::EXTRACT_SUBREG, MVT::v2i32, MVT::f64, MVT::f64, MVT::f32);
+ SDNode *Result = Emit_32(N, TargetOpcode::IMPLICIT_DEF, TargetOpcode::INSERT_SUBREG, ARM::VCVTu2fd_sfp, TargetOpcode::EXTRACT_SUBREG, MVT::v2i32, MVT::f64, MVT::f64, MVT::f32);
return Result;
}
@@ -4032,7 +4037,7 @@ SDNode *Select_ARMISD_VDUPLANE_v16i8(SDNode *N) {
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_46(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VDUPLN8q, MVT::v8i8, MVT::v16i8);
+ SDNode *Result = Emit_46(N, TargetOpcode::EXTRACT_SUBREG, ARM::VDUPLN8q, MVT::v8i8, MVT::v16i8);
return Result;
}
@@ -4089,7 +4094,7 @@ SDNode *Select_ARMISD_VDUPLANE_v8i16(SDNode *N) {
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_47(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VDUPLN16q, MVT::v4i16, MVT::v8i16);
+ SDNode *Result = Emit_47(N, TargetOpcode::EXTRACT_SUBREG, ARM::VDUPLN16q, MVT::v4i16, MVT::v8i16);
return Result;
}
@@ -4146,7 +4151,7 @@ SDNode *Select_ARMISD_VDUPLANE_v4i32(SDNode *N) {
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_48(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VDUPLN32q, MVT::v2i32, MVT::v4i32);
+ SDNode *Result = Emit_48(N, TargetOpcode::EXTRACT_SUBREG, ARM::VDUPLN32q, MVT::v2i32, MVT::v4i32);
return Result;
}
@@ -4168,7 +4173,7 @@ SDNode *Select_ARMISD_VDUPLANE_v2i64(SDNode *N) {
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_49(N, TargetInstrInfo::EXTRACT_SUBREG, TargetInstrInfo::INSERT_SUBREG, MVT::i64, MVT::v2i64);
+ SDNode *Result = Emit_49(N, TargetOpcode::EXTRACT_SUBREG, TargetOpcode::INSERT_SUBREG, MVT::i64, MVT::v2i64);
return Result;
}
@@ -4213,7 +4218,7 @@ SDNode *Select_ARMISD_VDUPLANE_v4f32(SDNode *N) {
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_48(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VDUPLNfq, MVT::v2f32, MVT::v4f32);
+ SDNode *Result = Emit_48(N, TargetOpcode::EXTRACT_SUBREG, ARM::VDUPLNfq, MVT::v2f32, MVT::v4f32);
return Result;
}
@@ -4226,7 +4231,7 @@ SDNode *Select_ARMISD_VDUPLANE_v2f64(SDNode *N) {
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_49(N, TargetInstrInfo::EXTRACT_SUBREG, TargetInstrInfo::INSERT_SUBREG, MVT::f64, MVT::v2f64);
+ SDNode *Result = Emit_49(N, TargetOpcode::EXTRACT_SUBREG, TargetOpcode::INSERT_SUBREG, MVT::f64, MVT::v2f64);
return Result;
}
@@ -4395,7 +4400,7 @@ SDNode *Select_ARMISD_VGETLANEs_i32(SDNode *N) {
// Emits: (VGETLNs8:i32 (EXTRACT_SUBREG:v8i8 QPR:v16i8:$src, (DSubReg_i8_reg:i32 (imm:i32):$lane)), (SubReg_i8_lane:i32 (imm:i32):$lane))
// Pattern complexity = 6 cost = 2 size = 0
if (N0.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_46(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VGETLNs8, MVT::v8i8, MVT::i32);
+ SDNode *Result = Emit_46(N, TargetOpcode::EXTRACT_SUBREG, ARM::VGETLNs8, MVT::v8i8, MVT::i32);
return Result;
}
@@ -4403,7 +4408,7 @@ SDNode *Select_ARMISD_VGETLANEs_i32(SDNode *N) {
// Emits: (VGETLNs16:i32 (EXTRACT_SUBREG:v4i16 QPR:v16i8:$src, (DSubReg_i16_reg:i32 (imm:i32):$lane)), (SubReg_i16_lane:i32 (imm:i32):$lane))
// Pattern complexity = 6 cost = 2 size = 0
if (N0.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_47(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VGETLNs16, MVT::v4i16, MVT::i32);
+ SDNode *Result = Emit_47(N, TargetOpcode::EXTRACT_SUBREG, ARM::VGETLNs16, MVT::v4i16, MVT::i32);
return Result;
}
}
@@ -4443,7 +4448,7 @@ SDNode *Select_ARMISD_VGETLANEu_i32(SDNode *N) {
// Emits: (VGETLNu8:i32 (EXTRACT_SUBREG:v8i8 QPR:v16i8:$src, (DSubReg_i8_reg:i32 (imm:i32):$lane)), (SubReg_i8_lane:i32 (imm:i32):$lane))
// Pattern complexity = 6 cost = 2 size = 0
if (N0.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_46(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VGETLNu8, MVT::v8i8, MVT::i32);
+ SDNode *Result = Emit_46(N, TargetOpcode::EXTRACT_SUBREG, ARM::VGETLNu8, MVT::v8i8, MVT::i32);
return Result;
}
@@ -4451,7 +4456,7 @@ SDNode *Select_ARMISD_VGETLANEu_i32(SDNode *N) {
// Emits: (VGETLNu16:i32 (EXTRACT_SUBREG:v4i16 QPR:v16i8:$src, (DSubReg_i16_reg:i32 (imm:i32):$lane)), (SubReg_i16_lane:i32 (imm:i32):$lane))
// Pattern complexity = 6 cost = 2 size = 0
if (N0.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_47(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VGETLNu16, MVT::v4i16, MVT::i32);
+ SDNode *Result = Emit_47(N, TargetOpcode::EXTRACT_SUBREG, ARM::VGETLNu16, MVT::v4i16, MVT::i32);
return Result;
}
}
@@ -11329,7 +11334,7 @@ SDNode *Select_ISD_ADD_v8i16(SDNode *N) {
SDValue N111 = N11.getNode()->getOperand(1);
if (N111.getNode()->getOpcode() == ISD::Constant &&
N110.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_133(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLAslv8i16, MVT::v4i16, MVT::v8i16);
+ SDNode *Result = Emit_133(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMLAslv8i16, MVT::v4i16, MVT::v8i16);
return Result;
}
}
@@ -11344,7 +11349,7 @@ SDNode *Select_ISD_ADD_v8i16(SDNode *N) {
if (N101.getNode()->getOpcode() == ISD::Constant) {
SDValue N11 = N1.getNode()->getOperand(1);
if (N100.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_134(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLAslv8i16, MVT::v4i16, MVT::v8i16);
+ SDNode *Result = Emit_134(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMLAslv8i16, MVT::v4i16, MVT::v8i16);
return Result;
}
}
@@ -11365,7 +11370,7 @@ SDNode *Select_ISD_ADD_v8i16(SDNode *N) {
if (N011.getNode()->getOpcode() == ISD::Constant) {
SDValue N1 = N->getOperand(1);
if (N010.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_135(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLAslv8i16, MVT::v4i16, MVT::v8i16);
+ SDNode *Result = Emit_135(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMLAslv8i16, MVT::v4i16, MVT::v8i16);
return Result;
}
}
@@ -11382,7 +11387,7 @@ SDNode *Select_ISD_ADD_v8i16(SDNode *N) {
SDValue N01 = N0.getNode()->getOperand(1);
SDValue N1 = N->getOperand(1);
if (N000.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_136(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLAslv8i16, MVT::v4i16, MVT::v8i16);
+ SDNode *Result = Emit_136(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMLAslv8i16, MVT::v4i16, MVT::v8i16);
return Result;
}
}
@@ -11891,7 +11896,7 @@ SDNode *Select_ISD_ADD_v4i32(SDNode *N) {
SDValue N111 = N11.getNode()->getOperand(1);
if (N111.getNode()->getOpcode() == ISD::Constant &&
N110.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_137(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLAslv4i32, MVT::v2i32, MVT::v4i32);
+ SDNode *Result = Emit_137(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMLAslv4i32, MVT::v2i32, MVT::v4i32);
return Result;
}
}
@@ -11906,7 +11911,7 @@ SDNode *Select_ISD_ADD_v4i32(SDNode *N) {
if (N101.getNode()->getOpcode() == ISD::Constant) {
SDValue N11 = N1.getNode()->getOperand(1);
if (N100.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_138(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLAslv4i32, MVT::v2i32, MVT::v4i32);
+ SDNode *Result = Emit_138(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMLAslv4i32, MVT::v2i32, MVT::v4i32);
return Result;
}
}
@@ -11927,7 +11932,7 @@ SDNode *Select_ISD_ADD_v4i32(SDNode *N) {
if (N011.getNode()->getOpcode() == ISD::Constant) {
SDValue N1 = N->getOperand(1);
if (N010.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_139(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLAslv4i32, MVT::v2i32, MVT::v4i32);
+ SDNode *Result = Emit_139(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMLAslv4i32, MVT::v2i32, MVT::v4i32);
return Result;
}
}
@@ -11944,7 +11949,7 @@ SDNode *Select_ISD_ADD_v4i32(SDNode *N) {
SDValue N01 = N0.getNode()->getOperand(1);
SDValue N1 = N->getOperand(1);
if (N000.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_140(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLAslv4i32, MVT::v2i32, MVT::v4i32);
+ SDNode *Result = Emit_140(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMLAslv4i32, MVT::v2i32, MVT::v4i32);
return Result;
}
}
@@ -15612,7 +15617,7 @@ SDNode *Select_ISD_EXTRACT_VECTOR_ELT_i32(SDNode *N) {
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_48(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VGETLNi32, MVT::v2i32, MVT::i32);
+ SDNode *Result = Emit_48(N, TargetOpcode::EXTRACT_SUBREG, ARM::VGETLNi32, MVT::v2i32, MVT::i32);
return Result;
}
@@ -15647,7 +15652,7 @@ SDNode *Select_ISD_EXTRACT_VECTOR_ELT_f32(SDNode *N) {
// Emits: (EXTRACT_SUBREG:f32 (COPY_TO_REGCLASS:v2f32 DPR:v2f32:$src1, DPR_VFP2:f64), (SSubReg_f32_reg:i32 (imm:i32):$src2))
// Pattern complexity = 6 cost = 2 size = 0
if (N0.getValueType() == MVT::v2f32) {
- SDNode *Result = Emit_202(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, MVT::v2f32, MVT::f32);
+ SDNode *Result = Emit_202(N, TargetOpcode::COPY_TO_REGCLASS, TargetOpcode::EXTRACT_SUBREG, MVT::v2f32, MVT::f32);
return Result;
}
@@ -15655,7 +15660,7 @@ SDNode *Select_ISD_EXTRACT_VECTOR_ELT_f32(SDNode *N) {
// Emits: (EXTRACT_SUBREG:f32 (COPY_TO_REGCLASS:v4f32 QPR:v4f32:$src1, QPR_VFP2:v16i8), (SSubReg_f32_reg:i32 (imm:i32):$src2))
// Pattern complexity = 6 cost = 2 size = 0
if (N0.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_203(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, MVT::v4f32, MVT::f32);
+ SDNode *Result = Emit_203(N, TargetOpcode::COPY_TO_REGCLASS, TargetOpcode::EXTRACT_SUBREG, MVT::v4f32, MVT::f32);
return Result;
}
}
@@ -15676,7 +15681,7 @@ SDNode *Select_ISD_EXTRACT_VECTOR_ELT_f64(SDNode *N) {
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_204(N, TargetInstrInfo::EXTRACT_SUBREG, MVT::f64);
+ SDNode *Result = Emit_204(N, TargetOpcode::EXTRACT_SUBREG, MVT::f64);
return Result;
}
@@ -15698,7 +15703,7 @@ SDNode *Select_ISD_FABS_f32(SDNode *N) {
// Emits: (EXTRACT_SUBREG:f32 (VABSfd_sfp:f64 (INSERT_SUBREG:f64 (IMPLICIT_DEF:v2f32), SPR:f32:$a, 1:i32)), 1:i32)
// Pattern complexity = 3 cost = 4 size = 0
if ((Subtarget->hasNEON()) && (Subtarget->useNEONForSinglePrecisionFP())) {
- SDNode *Result = Emit_32(N, TargetInstrInfo::IMPLICIT_DEF, TargetInstrInfo::INSERT_SUBREG, ARM::VABSfd_sfp, TargetInstrInfo::EXTRACT_SUBREG, MVT::v2f32, MVT::f64, MVT::f64, MVT::f32);
+ SDNode *Result = Emit_32(N, TargetOpcode::IMPLICIT_DEF, TargetOpcode::INSERT_SUBREG, ARM::VABSfd_sfp, TargetOpcode::EXTRACT_SUBREG, MVT::v2f32, MVT::f64, MVT::f64, MVT::f32);
return Result;
}
@@ -15813,7 +15818,7 @@ SDNode *Select_ISD_FADD_f32(SDNode *N) {
// Emits: (EXTRACT_SUBREG:f32 (VADDfd_sfp:f64 (INSERT_SUBREG:f64 (IMPLICIT_DEF:v2f32), SPR:f32:$a, 1:i32), (INSERT_SUBREG:f64 (IMPLICIT_DEF:v2f32), SPR:f32:$b, 1:i32)), 1:i32)
// Pattern complexity = 3 cost = 6 size = 0
if ((Subtarget->hasNEON()) && (Subtarget->useNEONForSinglePrecisionFP())) {
- SDNode *Result = Emit_206(N, TargetInstrInfo::IMPLICIT_DEF, TargetInstrInfo::INSERT_SUBREG, TargetInstrInfo::IMPLICIT_DEF, TargetInstrInfo::INSERT_SUBREG, ARM::VADDfd_sfp, TargetInstrInfo::EXTRACT_SUBREG, MVT::v2f32, MVT::f64, MVT::v2f32, MVT::f64, MVT::f64, MVT::f32);
+ SDNode *Result = Emit_206(N, TargetOpcode::IMPLICIT_DEF, TargetOpcode::INSERT_SUBREG, TargetOpcode::IMPLICIT_DEF, TargetOpcode::INSERT_SUBREG, ARM::VADDfd_sfp, TargetOpcode::EXTRACT_SUBREG, MVT::v2f32, MVT::f64, MVT::v2f32, MVT::f64, MVT::f64, MVT::f32);
return Result;
}
@@ -16085,7 +16090,7 @@ SDNode *Select_ISD_FADD_v4f32(SDNode *N) {
SDValue N111 = N11.getNode()->getOperand(1);
if (N111.getNode()->getOpcode() == ISD::Constant &&
N110.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_137(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLAslfq, MVT::v2f32, MVT::v4f32);
+ SDNode *Result = Emit_137(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMLAslfq, MVT::v2f32, MVT::v4f32);
return Result;
}
}
@@ -16100,7 +16105,7 @@ SDNode *Select_ISD_FADD_v4f32(SDNode *N) {
if (N101.getNode()->getOpcode() == ISD::Constant) {
SDValue N11 = N1.getNode()->getOperand(1);
if (N100.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_138(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLAslfq, MVT::v2f32, MVT::v4f32);
+ SDNode *Result = Emit_138(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMLAslfq, MVT::v2f32, MVT::v4f32);
return Result;
}
}
@@ -16121,7 +16126,7 @@ SDNode *Select_ISD_FADD_v4f32(SDNode *N) {
if (N011.getNode()->getOpcode() == ISD::Constant) {
SDValue N1 = N->getOperand(1);
if (N010.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_139(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLAslfq, MVT::v2f32, MVT::v4f32);
+ SDNode *Result = Emit_139(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMLAslfq, MVT::v2f32, MVT::v4f32);
return Result;
}
}
@@ -16138,7 +16143,7 @@ SDNode *Select_ISD_FADD_v4f32(SDNode *N) {
SDValue N01 = N0.getNode()->getOperand(1);
SDValue N1 = N->getOperand(1);
if (N000.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_140(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLAslfq, MVT::v2f32, MVT::v4f32);
+ SDNode *Result = Emit_140(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMLAslfq, MVT::v2f32, MVT::v4f32);
return Result;
}
}
@@ -16252,7 +16257,7 @@ SDNode *Select_ISD_FMUL_f32(SDNode *N) {
// Emits: (EXTRACT_SUBREG:f32 (VMULfd_sfp:f64 (INSERT_SUBREG:f64 (IMPLICIT_DEF:v2f32), SPR:f32:$a, 1:i32), (INSERT_SUBREG:f64 (IMPLICIT_DEF:v2f32), SPR:f32:$b, 1:i32)), 1:i32)
// Pattern complexity = 3 cost = 6 size = 0
if ((Subtarget->hasNEON()) && (Subtarget->useNEONForSinglePrecisionFP())) {
- SDNode *Result = Emit_206(N, TargetInstrInfo::IMPLICIT_DEF, TargetInstrInfo::INSERT_SUBREG, TargetInstrInfo::IMPLICIT_DEF, TargetInstrInfo::INSERT_SUBREG, ARM::VMULfd_sfp, TargetInstrInfo::EXTRACT_SUBREG, MVT::v2f32, MVT::f64, MVT::v2f32, MVT::f64, MVT::f64, MVT::f32);
+ SDNode *Result = Emit_206(N, TargetOpcode::IMPLICIT_DEF, TargetOpcode::INSERT_SUBREG, TargetOpcode::IMPLICIT_DEF, TargetOpcode::INSERT_SUBREG, ARM::VMULfd_sfp, TargetOpcode::EXTRACT_SUBREG, MVT::v2f32, MVT::f64, MVT::v2f32, MVT::f64, MVT::f64, MVT::f32);
return Result;
}
@@ -16418,7 +16423,7 @@ SDNode *Select_ISD_FMUL_v4f32(SDNode *N) {
SDValue N11 = N1.getNode()->getOperand(1);
if (N11.getNode()->getOpcode() == ISD::Constant &&
N10.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_210(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMULslfq, MVT::v2f32, MVT::v4f32);
+ SDNode *Result = Emit_210(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMULslfq, MVT::v2f32, MVT::v4f32);
return Result;
}
}
@@ -16433,7 +16438,7 @@ SDNode *Select_ISD_FMUL_v4f32(SDNode *N) {
if (N01.getNode()->getOpcode() == ISD::Constant) {
SDValue N1 = N->getOperand(1);
if (N00.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_211(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMULslfq, MVT::v2f32, MVT::v4f32);
+ SDNode *Result = Emit_211(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMULslfq, MVT::v2f32, MVT::v4f32);
return Result;
}
}
@@ -16486,7 +16491,7 @@ SDNode *Select_ISD_FNEG_f32(SDNode *N) {
// Emits: (EXTRACT_SUBREG:f32 (VNEGf32d_sfp:f64 (INSERT_SUBREG:f64 (IMPLICIT_DEF:v2f32), SPR:f32:$a, 1:i32)), 1:i32)
// Pattern complexity = 3 cost = 4 size = 0
if ((Subtarget->hasNEON()) && (Subtarget->useNEONForSinglePrecisionFP())) {
- SDNode *Result = Emit_32(N, TargetInstrInfo::IMPLICIT_DEF, TargetInstrInfo::INSERT_SUBREG, ARM::VNEGf32d_sfp, TargetInstrInfo::EXTRACT_SUBREG, MVT::v2f32, MVT::f64, MVT::f64, MVT::f32);
+ SDNode *Result = Emit_32(N, TargetOpcode::IMPLICIT_DEF, TargetOpcode::INSERT_SUBREG, ARM::VNEGf32d_sfp, TargetOpcode::EXTRACT_SUBREG, MVT::v2f32, MVT::f64, MVT::f64, MVT::f32);
return Result;
}
@@ -16685,7 +16690,7 @@ SDNode *Select_ISD_FSUB_f32(SDNode *N) {
// Emits: (EXTRACT_SUBREG:f32 (VSUBfd_sfp:f64 (INSERT_SUBREG:f64 (IMPLICIT_DEF:v2f32), SPR:f32:$a, 1:i32), (INSERT_SUBREG:f64 (IMPLICIT_DEF:v2f32), SPR:f32:$b, 1:i32)), 1:i32)
// Pattern complexity = 3 cost = 6 size = 0
if ((Subtarget->hasNEON()) && (Subtarget->useNEONForSinglePrecisionFP())) {
- SDNode *Result = Emit_206(N, TargetInstrInfo::IMPLICIT_DEF, TargetInstrInfo::INSERT_SUBREG, TargetInstrInfo::IMPLICIT_DEF, TargetInstrInfo::INSERT_SUBREG, ARM::VSUBfd_sfp, TargetInstrInfo::EXTRACT_SUBREG, MVT::v2f32, MVT::f64, MVT::v2f32, MVT::f64, MVT::f64, MVT::f32);
+ SDNode *Result = Emit_206(N, TargetOpcode::IMPLICIT_DEF, TargetOpcode::INSERT_SUBREG, TargetOpcode::IMPLICIT_DEF, TargetOpcode::INSERT_SUBREG, ARM::VSUBfd_sfp, TargetOpcode::EXTRACT_SUBREG, MVT::v2f32, MVT::f64, MVT::v2f32, MVT::f64, MVT::f64, MVT::f32);
return Result;
}
@@ -16856,7 +16861,7 @@ SDNode *Select_ISD_FSUB_v4f32(SDNode *N) {
SDValue N111 = N11.getNode()->getOperand(1);
if (N111.getNode()->getOpcode() == ISD::Constant &&
N110.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_137(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLSslfq, MVT::v2f32, MVT::v4f32);
+ SDNode *Result = Emit_137(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMLSslfq, MVT::v2f32, MVT::v4f32);
return Result;
}
}
@@ -16871,7 +16876,7 @@ SDNode *Select_ISD_FSUB_v4f32(SDNode *N) {
if (N101.getNode()->getOpcode() == ISD::Constant) {
SDValue N11 = N1.getNode()->getOperand(1);
if (N100.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_138(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLSslfq, MVT::v2f32, MVT::v4f32);
+ SDNode *Result = Emit_138(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMLSslfq, MVT::v2f32, MVT::v4f32);
return Result;
}
}
@@ -16940,7 +16945,7 @@ SDNode *Select_ISD_INSERT_VECTOR_ELT_v16i8(SDNode *N) {
SDValue N2 = N->getOperand(2);
if (N2.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_213(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VSETLNi8, TargetInstrInfo::INSERT_SUBREG, MVT::v8i8, MVT::f64, MVT::v16i8);
+ SDNode *Result = Emit_213(N, TargetOpcode::EXTRACT_SUBREG, ARM::VSETLNi8, TargetOpcode::INSERT_SUBREG, MVT::v8i8, MVT::f64, MVT::v16i8);
return Result;
}
@@ -16985,7 +16990,7 @@ SDNode *Select_ISD_INSERT_VECTOR_ELT_v8i16(SDNode *N) {
SDValue N2 = N->getOperand(2);
if (N2.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_214(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VSETLNi16, TargetInstrInfo::INSERT_SUBREG, MVT::v4i16, MVT::f64, MVT::v8i16);
+ SDNode *Result = Emit_214(N, TargetOpcode::EXTRACT_SUBREG, ARM::VSETLNi16, TargetOpcode::INSERT_SUBREG, MVT::v4i16, MVT::f64, MVT::v8i16);
return Result;
}
@@ -17028,7 +17033,7 @@ SDNode *Select_ISD_INSERT_VECTOR_ELT_v4i32(SDNode *N) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_215(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VSETLNi32, TargetInstrInfo::INSERT_SUBREG, MVT::v2i32, MVT::f64, MVT::v4i32);
+ SDNode *Result = Emit_215(N, TargetOpcode::EXTRACT_SUBREG, ARM::VSETLNi32, TargetOpcode::INSERT_SUBREG, MVT::v2i32, MVT::f64, MVT::v4i32);
return Result;
}
@@ -17051,7 +17056,7 @@ SDNode *Select_ISD_INSERT_VECTOR_ELT_v2f32(SDNode *N) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_216(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::INSERT_SUBREG, MVT::v2f32, MVT::v2f32);
+ SDNode *Result = Emit_216(N, TargetOpcode::COPY_TO_REGCLASS, TargetOpcode::INSERT_SUBREG, MVT::v2f32, MVT::v2f32);
return Result;
}
@@ -17074,7 +17079,7 @@ SDNode *Select_ISD_INSERT_VECTOR_ELT_v4f32(SDNode *N) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_217(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::INSERT_SUBREG, MVT::v4f32, MVT::v4f32);
+ SDNode *Result = Emit_217(N, TargetOpcode::COPY_TO_REGCLASS, TargetOpcode::INSERT_SUBREG, MVT::v4f32, MVT::v4f32);
return Result;
}
@@ -17095,7 +17100,7 @@ SDNode *Select_ISD_INSERT_VECTOR_ELT_v2f64(SDNode *N) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_218(N, TargetInstrInfo::INSERT_SUBREG, MVT::v2f64);
+ SDNode *Result = Emit_218(N, TargetOpcode::INSERT_SUBREG, MVT::v2f64);
return Result;
}
@@ -19275,7 +19280,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(SDNode *N) {
N1.getValueType() == MVT::v8i16 &&
N2.getValueType() == MVT::v8i16 &&
N20.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_228(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VQDMULHslv8i16, MVT::v4i16, MVT::v8i16);
+ SDNode *Result = Emit_228(N, TargetOpcode::EXTRACT_SUBREG, ARM::VQDMULHslv8i16, MVT::v4i16, MVT::v8i16);
return Result;
}
}
@@ -19294,7 +19299,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(SDNode *N) {
N1.getValueType() == MVT::v8i16 &&
N2.getValueType() == MVT::v8i16 &&
N20.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_228(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VQRDMULHslv8i16, MVT::v4i16, MVT::v8i16);
+ SDNode *Result = Emit_228(N, TargetOpcode::EXTRACT_SUBREG, ARM::VQRDMULHslv8i16, MVT::v4i16, MVT::v8i16);
return Result;
}
}
@@ -19313,7 +19318,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(SDNode *N) {
if (N1.getValueType() == MVT::v8i16 &&
N10.getValueType() == MVT::v8i16 &&
N2.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_231(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VQDMULHslv8i16, MVT::v4i16, MVT::v8i16);
+ SDNode *Result = Emit_231(N, TargetOpcode::EXTRACT_SUBREG, ARM::VQDMULHslv8i16, MVT::v4i16, MVT::v8i16);
return Result;
}
}
@@ -19333,7 +19338,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(SDNode *N) {
if (N1.getValueType() == MVT::v8i16 &&
N10.getValueType() == MVT::v8i16 &&
N2.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_231(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VQRDMULHslv8i16, MVT::v4i16, MVT::v8i16);
+ SDNode *Result = Emit_231(N, TargetOpcode::EXTRACT_SUBREG, ARM::VQRDMULHslv8i16, MVT::v4i16, MVT::v8i16);
return Result;
}
}
@@ -21518,7 +21523,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(SDNode *N) {
N1.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v4i32 &&
N20.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_234(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VQDMULHslv4i32, MVT::v2i32, MVT::v4i32);
+ SDNode *Result = Emit_234(N, TargetOpcode::EXTRACT_SUBREG, ARM::VQDMULHslv4i32, MVT::v2i32, MVT::v4i32);
return Result;
}
}
@@ -21537,7 +21542,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(SDNode *N) {
N1.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v4i32 &&
N20.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_234(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VQRDMULHslv4i32, MVT::v2i32, MVT::v4i32);
+ SDNode *Result = Emit_234(N, TargetOpcode::EXTRACT_SUBREG, ARM::VQRDMULHslv4i32, MVT::v2i32, MVT::v4i32);
return Result;
}
}
@@ -21556,7 +21561,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(SDNode *N) {
if (N1.getValueType() == MVT::v4i32 &&
N10.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_236(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VQDMULHslv4i32, MVT::v2i32, MVT::v4i32);
+ SDNode *Result = Emit_236(N, TargetOpcode::EXTRACT_SUBREG, ARM::VQDMULHslv4i32, MVT::v2i32, MVT::v4i32);
return Result;
}
}
@@ -21576,7 +21581,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(SDNode *N) {
if (N1.getValueType() == MVT::v4i32 &&
N10.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_236(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VQRDMULHslv4i32, MVT::v2i32, MVT::v4i32);
+ SDNode *Result = Emit_236(N, TargetOpcode::EXTRACT_SUBREG, ARM::VQRDMULHslv4i32, MVT::v2i32, MVT::v4i32);
return Result;
}
}
@@ -26551,7 +26556,7 @@ SDNode *Select_ISD_MUL_v8i16(SDNode *N) {
SDValue N11 = N1.getNode()->getOperand(1);
if (N11.getNode()->getOpcode() == ISD::Constant &&
N10.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_259(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMULslv8i16, MVT::v4i16, MVT::v8i16);
+ SDNode *Result = Emit_259(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMULslv8i16, MVT::v4i16, MVT::v8i16);
return Result;
}
}
@@ -26566,7 +26571,7 @@ SDNode *Select_ISD_MUL_v8i16(SDNode *N) {
if (N01.getNode()->getOpcode() == ISD::Constant) {
SDValue N1 = N->getOperand(1);
if (N00.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_260(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMULslv8i16, MVT::v4i16, MVT::v8i16);
+ SDNode *Result = Emit_260(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMULslv8i16, MVT::v4i16, MVT::v8i16);
return Result;
}
}
@@ -26681,7 +26686,7 @@ SDNode *Select_ISD_MUL_v4i32(SDNode *N) {
SDValue N11 = N1.getNode()->getOperand(1);
if (N11.getNode()->getOpcode() == ISD::Constant &&
N10.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_210(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMULslv4i32, MVT::v2i32, MVT::v4i32);
+ SDNode *Result = Emit_210(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMULslv4i32, MVT::v2i32, MVT::v4i32);
return Result;
}
}
@@ -26696,7 +26701,7 @@ SDNode *Select_ISD_MUL_v4i32(SDNode *N) {
if (N01.getNode()->getOpcode() == ISD::Constant) {
SDValue N1 = N->getOperand(1);
if (N00.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_211(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMULslv4i32, MVT::v2i32, MVT::v4i32);
+ SDNode *Result = Emit_211(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMULslv4i32, MVT::v2i32, MVT::v4i32);
return Result;
}
}
@@ -33893,7 +33898,7 @@ DISABLE_INLINE SDNode *Emit_288(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::Si
SDNode *Select_ISD_SCALAR_TO_VECTOR_v8i8(SDNode *N) {
SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_288(N, TargetInstrInfo::IMPLICIT_DEF, ARM::VSETLNi8, MVT::v8i8, MVT::v8i8);
+ SDNode *Result = Emit_288(N, TargetOpcode::IMPLICIT_DEF, ARM::VSETLNi8, MVT::v8i8, MVT::v8i8);
return Result;
}
@@ -33916,7 +33921,7 @@ DISABLE_INLINE SDNode *Emit_289(SDNode *N, unsigned Opc0, unsigned Opc1, unsigne
SDNode *Select_ISD_SCALAR_TO_VECTOR_v16i8(SDNode *N) {
SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_289(N, TargetInstrInfo::IMPLICIT_DEF, TargetInstrInfo::IMPLICIT_DEF, ARM::VSETLNi8, TargetInstrInfo::INSERT_SUBREG, MVT::v16i8, MVT::v8i8, MVT::f64, MVT::v16i8);
+ SDNode *Result = Emit_289(N, TargetOpcode::IMPLICIT_DEF, TargetOpcode::IMPLICIT_DEF, ARM::VSETLNi8, TargetOpcode::INSERT_SUBREG, MVT::v16i8, MVT::v8i8, MVT::f64, MVT::v16i8);
return Result;
}
@@ -33927,7 +33932,7 @@ SDNode *Select_ISD_SCALAR_TO_VECTOR_v16i8(SDNode *N) {
SDNode *Select_ISD_SCALAR_TO_VECTOR_v4i16(SDNode *N) {
SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_288(N, TargetInstrInfo::IMPLICIT_DEF, ARM::VSETLNi16, MVT::v4i16, MVT::v4i16);
+ SDNode *Result = Emit_288(N, TargetOpcode::IMPLICIT_DEF, ARM::VSETLNi16, MVT::v4i16, MVT::v4i16);
return Result;
}
@@ -33938,7 +33943,7 @@ SDNode *Select_ISD_SCALAR_TO_VECTOR_v4i16(SDNode *N) {
SDNode *Select_ISD_SCALAR_TO_VECTOR_v8i16(SDNode *N) {
SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_289(N, TargetInstrInfo::IMPLICIT_DEF, TargetInstrInfo::IMPLICIT_DEF, ARM::VSETLNi16, TargetInstrInfo::INSERT_SUBREG, MVT::v8i16, MVT::v4i16, MVT::f64, MVT::v8i16);
+ SDNode *Result = Emit_289(N, TargetOpcode::IMPLICIT_DEF, TargetOpcode::IMPLICIT_DEF, ARM::VSETLNi16, TargetOpcode::INSERT_SUBREG, MVT::v8i16, MVT::v4i16, MVT::f64, MVT::v8i16);
return Result;
}
@@ -33949,7 +33954,7 @@ SDNode *Select_ISD_SCALAR_TO_VECTOR_v8i16(SDNode *N) {
SDNode *Select_ISD_SCALAR_TO_VECTOR_v2i32(SDNode *N) {
SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_288(N, TargetInstrInfo::IMPLICIT_DEF, ARM::VSETLNi32, MVT::v2i32, MVT::v2i32);
+ SDNode *Result = Emit_288(N, TargetOpcode::IMPLICIT_DEF, ARM::VSETLNi32, MVT::v2i32, MVT::v2i32);
return Result;
}
@@ -33960,7 +33965,7 @@ SDNode *Select_ISD_SCALAR_TO_VECTOR_v2i32(SDNode *N) {
SDNode *Select_ISD_SCALAR_TO_VECTOR_v4i32(SDNode *N) {
SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_289(N, TargetInstrInfo::IMPLICIT_DEF, TargetInstrInfo::IMPLICIT_DEF, ARM::VSETLNi32, TargetInstrInfo::INSERT_SUBREG, MVT::v4i32, MVT::v2i32, MVT::f64, MVT::v4i32);
+ SDNode *Result = Emit_289(N, TargetOpcode::IMPLICIT_DEF, TargetOpcode::IMPLICIT_DEF, ARM::VSETLNi32, TargetOpcode::INSERT_SUBREG, MVT::v4i32, MVT::v2i32, MVT::f64, MVT::v4i32);
return Result;
}
@@ -33977,7 +33982,7 @@ DISABLE_INLINE SDNode *Emit_290(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::Si
SDNode *Select_ISD_SCALAR_TO_VECTOR_v2f32(SDNode *N) {
SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::f32) {
- SDNode *Result = Emit_290(N, TargetInstrInfo::IMPLICIT_DEF, TargetInstrInfo::INSERT_SUBREG, MVT::v2f32, MVT::v2f32);
+ SDNode *Result = Emit_290(N, TargetOpcode::IMPLICIT_DEF, TargetOpcode::INSERT_SUBREG, MVT::v2f32, MVT::v2f32);
return Result;
}
@@ -33988,7 +33993,7 @@ SDNode *Select_ISD_SCALAR_TO_VECTOR_v2f32(SDNode *N) {
SDNode *Select_ISD_SCALAR_TO_VECTOR_v4f32(SDNode *N) {
SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::f32) {
- SDNode *Result = Emit_290(N, TargetInstrInfo::IMPLICIT_DEF, TargetInstrInfo::INSERT_SUBREG, MVT::v4f32, MVT::v4f32);
+ SDNode *Result = Emit_290(N, TargetOpcode::IMPLICIT_DEF, TargetOpcode::INSERT_SUBREG, MVT::v4f32, MVT::v4f32);
return Result;
}
@@ -34005,7 +34010,7 @@ DISABLE_INLINE SDNode *Emit_291(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::Si
SDNode *Select_ISD_SCALAR_TO_VECTOR_v2f64(SDNode *N) {
SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::f64) {
- SDNode *Result = Emit_291(N, TargetInstrInfo::IMPLICIT_DEF, TargetInstrInfo::INSERT_SUBREG, MVT::v2f64, MVT::v2f64);
+ SDNode *Result = Emit_291(N, TargetOpcode::IMPLICIT_DEF, TargetOpcode::INSERT_SUBREG, MVT::v2f64, MVT::v2f64);
return Result;
}
@@ -36294,7 +36299,7 @@ SDNode *Select_ISD_SUB_v8i16(SDNode *N) {
SDValue N111 = N11.getNode()->getOperand(1);
if (N111.getNode()->getOpcode() == ISD::Constant &&
N110.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_133(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLSslv8i16, MVT::v4i16, MVT::v8i16);
+ SDNode *Result = Emit_133(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMLSslv8i16, MVT::v4i16, MVT::v8i16);
return Result;
}
}
@@ -36309,7 +36314,7 @@ SDNode *Select_ISD_SUB_v8i16(SDNode *N) {
if (N101.getNode()->getOpcode() == ISD::Constant) {
SDValue N11 = N1.getNode()->getOperand(1);
if (N100.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_134(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLSslv8i16, MVT::v4i16, MVT::v8i16);
+ SDNode *Result = Emit_134(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMLSslv8i16, MVT::v4i16, MVT::v8i16);
return Result;
}
}
@@ -36507,7 +36512,7 @@ SDNode *Select_ISD_SUB_v4i32(SDNode *N) {
SDValue N111 = N11.getNode()->getOperand(1);
if (N111.getNode()->getOpcode() == ISD::Constant &&
N110.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_137(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLSslv4i32, MVT::v2i32, MVT::v4i32);
+ SDNode *Result = Emit_137(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMLSslv4i32, MVT::v2i32, MVT::v4i32);
return Result;
}
}
@@ -36522,7 +36527,7 @@ SDNode *Select_ISD_SUB_v4i32(SDNode *N) {
if (N101.getNode()->getOpcode() == ISD::Constant) {
SDValue N11 = N1.getNode()->getOperand(1);
if (N100.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_138(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLSslv4i32, MVT::v2i32, MVT::v4i32);
+ SDNode *Result = Emit_138(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMLSslv4i32, MVT::v2i32, MVT::v4i32);
return Result;
}
}
diff --git a/libclamav/c++/ARMGenInstrInfo.inc b/libclamav/c++/ARMGenInstrInfo.inc
index 017af5b..26f9fa6 100644
--- a/libclamav/c++/ARMGenInstrInfo.inc
+++ b/libclamav/c++/ARMGenInstrInfo.inc
@@ -41,145 +41,157 @@ static const TargetOperandInfo OperandInfo16[] = { { ARM::GPRRegClassID, 0, 0 },
static const TargetOperandInfo OperandInfo17[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
static const TargetOperandInfo OperandInfo18[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
static const TargetOperandInfo OperandInfo19[] = { { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo20[] = { { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo21[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo22[] = { { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo23[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo24[] = { { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo25[] = { { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo26[] = { { ARM::SPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo27[] = { { 0, 0, 0 }, { 0, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo28[] = { { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo29[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((1 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo30[] = { { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo31[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, };
-static const TargetOperandInfo OperandInfo32[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo33[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo34[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo35[] = { { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, };
-static const TargetOperandInfo OperandInfo36[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, };
-static const TargetOperandInfo OperandInfo37[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, };
-static const TargetOperandInfo OperandInfo38[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo39[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo40[] = { { ARM::GPRRegClassID, 0, (1 << TOI::EARLY_CLOBBER) }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo41[] = { { ARM::GPRRegClassID, 0, (1 << TOI::EARLY_CLOBBER) }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo42[] = { { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo43[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo44[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo45[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo46[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo47[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo48[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo49[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo50[] = { { ARM::SPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo51[] = { { ARM::DPR_VFP2RegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo52[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo53[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo54[] = { { ARM::SPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo55[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo56[] = { { ARM::DPR_VFP2RegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo57[] = { { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo58[] = { { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo59[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo60[] = { { ARM::SPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo61[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo62[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo63[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo64[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo65[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo66[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo67[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo68[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo69[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo70[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo71[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo72[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, ((1 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo73[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo74[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo75[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, ((1 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, ((2 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo76[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo77[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((3 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo78[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, ((1 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, ((2 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, ((3 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo79[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((4 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo80[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo81[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo82[] = { { ARM::SPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo83[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo84[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPR_8RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo85[] = { { ARM::SPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::SPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo86[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo87[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo88[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPR_8RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo89[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, 0 }, { ARM::DPR_8RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo90[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo91[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo92[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo93[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo94[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo95[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo96[] = { { ARM::SPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo97[] = { { ARM::SPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo98[] = { { ARM::QPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo99[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo100[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPR_8RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo101[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo102[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo103[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPR_8RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo104[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { ARM::DPR_8RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo105[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo106[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo107[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo108[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo109[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo110[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo111[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo112[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo113[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo114[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo115[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo116[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo117[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo118[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo119[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo120[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo121[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo122[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo123[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo124[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo125[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo126[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, ((1 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo127[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, ((1 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo128[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo129[] = { { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo130[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((1 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo131[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo132[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo133[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, };
-static const TargetOperandInfo OperandInfo134[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, };
-static const TargetOperandInfo OperandInfo135[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo136[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, { ARM::tGPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo137[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo138[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, { ARM::tGPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo139[] = { { ARM::tGPRRegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo140[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo141[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo142[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo143[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo144[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo145[] = { { ARM::tGPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo146[] = { { ARM::tGPRRegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo147[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo148[] = { { ARM::tGPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo149[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo150[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo151[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo152[] = { { ARM::tGPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo153[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo154[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo155[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo156[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo157[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo158[] = { { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo20[] = { { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo21[] = { { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo22[] = { { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo23[] = { { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo24[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo25[] = { { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo26[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo27[] = { { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo28[] = { { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo29[] = { { ARM::SPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo30[] = { { 0, 0, 0 }, { 0, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo31[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo32[] = { { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo33[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((1 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo34[] = { { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo35[] = { { 0, 0, 0 }, { 0, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo36[] = { { 0, 0, 0 }, { 0, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo37[] = { { 0, 0, 0 }, { 0, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo38[] = { { 0, 0, 0 }, { 0, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo39[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, };
+static const TargetOperandInfo OperandInfo40[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo41[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo42[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo43[] = { { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, };
+static const TargetOperandInfo OperandInfo44[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, };
+static const TargetOperandInfo OperandInfo45[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, };
+static const TargetOperandInfo OperandInfo46[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo47[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo48[] = { { ARM::GPRRegClassID, 0, (1 << TOI::EARLY_CLOBBER) }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo49[] = { { ARM::GPRRegClassID, 0, (1 << TOI::EARLY_CLOBBER) }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo50[] = { { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo51[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo52[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo53[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo54[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo55[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo56[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo57[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo58[] = { { ARM::SPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo59[] = { { ARM::DPR_VFP2RegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo60[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo61[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo62[] = { { ARM::SPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo63[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo64[] = { { ARM::DPR_VFP2RegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo65[] = { { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo66[] = { { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo67[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo68[] = { { ARM::SPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo69[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo70[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo71[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo72[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo73[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo74[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo75[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo76[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo77[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo78[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo79[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo80[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, ((1 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo81[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo82[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo83[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, ((1 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, ((2 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo84[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo85[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((3 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo86[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, ((1 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, ((2 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, ((3 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo87[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((4 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo88[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo89[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo90[] = { { ARM::SPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo91[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo92[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPR_8RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo93[] = { { ARM::SPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::SPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo94[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo95[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo96[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPR_8RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo97[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, 0 }, { ARM::DPR_8RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo98[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo99[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo100[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo101[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo102[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo103[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo104[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo105[] = { { ARM::SPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo106[] = { { ARM::SPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo107[] = { { ARM::SPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::SPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo108[] = { { ARM::QPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo109[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo110[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPR_8RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo111[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo112[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { ARM::DPR_VFP2RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo113[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPR_8RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo114[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { ARM::DPR_8RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo115[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo116[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo117[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo118[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo119[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo120[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo121[] = { { ARM::SPRRegClassID, 0, 0 }, { ARM::SPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo122[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo123[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo124[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo125[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo126[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo127[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo128[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo129[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo130[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo131[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo132[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo133[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo134[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo135[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo136[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo137[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo138[] = { { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, 0 }, { ARM::DPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, ((1 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo139[] = { { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, 0 }, { ARM::QPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, ((1 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo140[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo141[] = { { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo142[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo143[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((1 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo144[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo145[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, };
+static const TargetOperandInfo OperandInfo146[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, };
+static const TargetOperandInfo OperandInfo147[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo148[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, { ARM::tGPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo149[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo150[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, { ARM::tGPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo151[] = { { ARM::tGPRRegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo152[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo153[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo154[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo155[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo156[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo157[] = { { ARM::tGPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo158[] = { { ARM::tGPRRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo159[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo160[] = { { ARM::tGPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo161[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo162[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo163[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo164[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo165[] = { { ARM::tGPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo166[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo167[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo168[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo169[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo170[] = { { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, { 0, 0, 0 }, };
static const TargetInstrDesc ARMInsts[] = {
{ 0, 0, 0, 128, "PHI", 0|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, 0 }, // Inst #0 = PHI
@@ -188,12 +200,12 @@ static const TargetInstrDesc ARMInsts[] = {
{ 3, 1, 0, 128, "EH_LABEL", 0|(1<<TID::NotDuplicable)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo14 }, // Inst #3 = EH_LABEL
{ 4, 1, 0, 128, "GC_LABEL", 0|(1<<TID::NotDuplicable)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo14 }, // Inst #4 = GC_LABEL
{ 5, 0, 0, 128, "KILL", 0|(1<<TID::Variadic), 0, NULL, NULL, NULL, 0 }, // Inst #5 = KILL
- { 6, 3, 1, 128, "EXTRACT_SUBREG", 0, 0, NULL, NULL, NULL, OperandInfo24 }, // Inst #6 = EXTRACT_SUBREG
- { 7, 4, 1, 128, "INSERT_SUBREG", 0, 0, NULL, NULL, NULL, OperandInfo27 }, // Inst #7 = INSERT_SUBREG
+ { 6, 3, 1, 128, "EXTRACT_SUBREG", 0, 0, NULL, NULL, NULL, OperandInfo27 }, // Inst #6 = EXTRACT_SUBREG
+ { 7, 4, 1, 128, "INSERT_SUBREG", 0, 0, NULL, NULL, NULL, OperandInfo30 }, // Inst #7 = INSERT_SUBREG
{ 8, 1, 1, 128, "IMPLICIT_DEF", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0, NULL, NULL, NULL, OperandInfo14 }, // Inst #8 = IMPLICIT_DEF
- { 9, 4, 1, 128, "SUBREG_TO_REG", 0, 0, NULL, NULL, NULL, OperandInfo42 }, // Inst #9 = SUBREG_TO_REG
- { 10, 3, 1, 128, "COPY_TO_REGCLASS", 0|(1<<TID::CheapAsAMove), 0, NULL, NULL, NULL, OperandInfo24 }, // Inst #10 = COPY_TO_REGCLASS
- { 11, 0, 0, 128, "DEBUG_VALUE", 0|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::CheapAsAMove), 0, NULL, NULL, NULL, 0 }, // Inst #11 = DEBUG_VALUE
+ { 9, 4, 1, 128, "SUBREG_TO_REG", 0, 0, NULL, NULL, NULL, OperandInfo50 }, // Inst #9 = SUBREG_TO_REG
+ { 10, 3, 1, 128, "COPY_TO_REGCLASS", 0|(1<<TID::CheapAsAMove), 0, NULL, NULL, NULL, OperandInfo27 }, // Inst #10 = COPY_TO_REGCLASS
+ { 11, 0, 0, 128, "DBG_VALUE", 0|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::CheapAsAMove), 0, NULL, NULL, NULL, 0 }, // Inst #11 = DBG_VALUE
{ 12, 3, 1, 88, "ADCSSri", 0, 0|1|(3<<4)|(4<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #12 = ADCSSri
{ 13, 3, 1, 89, "ADCSSrr", 0, 0|1|(3<<4)|(4<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #13 = ADCSSrr
{ 14, 5, 1, 91, "ADCSSrs", 0, 0|1|(3<<4)|(5<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #14 = ADCSSrs
@@ -240,1467 +252,1558 @@ static const TargetInstrDesc ARMInsts[] = {
{ 55, 6, 1, 88, "BICri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #55 = BICri
{ 56, 6, 1, 89, "BICrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #56 = BICrr
{ 57, 8, 1, 91, "BICrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), NULL, NULL, NULL, OperandInfo7 }, // Inst #57 = BICrs
- { 58, 1, 0, 0, "BL", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(2<<9), NULL, ImplicitList3, Barriers2, OperandInfo14 }, // Inst #58 = BL
- { 59, 1, 0, 0, "BLX", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(3<<9), NULL, ImplicitList3, Barriers2, OperandInfo16 }, // Inst #59 = BLX
- { 60, 1, 0, 0, "BLXr9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(3<<9), NULL, ImplicitList4, Barriers2, OperandInfo16 }, // Inst #60 = BLXr9
- { 61, 3, 0, 0, "BL_pred", 0|(1<<TID::Call)|(1<<TID::Predicable)|(1<<TID::Variadic), 0|(3<<4)|(2<<9), NULL, ImplicitList3, Barriers2, OperandInfo11 }, // Inst #61 = BL_pred
- { 62, 1, 0, 0, "BLr9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(2<<9), NULL, ImplicitList4, Barriers2, OperandInfo14 }, // Inst #62 = BLr9
- { 63, 3, 0, 0, "BLr9_pred", 0|(1<<TID::Call)|(1<<TID::Predicable)|(1<<TID::Variadic), 0|(3<<4)|(2<<9), NULL, ImplicitList4, Barriers2, OperandInfo11 }, // Inst #63 = BLr9_pred
- { 64, 1, 0, 0, "BRIND", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|(3<<4)|(3<<9), NULL, NULL, NULL, OperandInfo16 }, // Inst #64 = BRIND
- { 65, 4, 0, 0, "BR_JTadd", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::NotDuplicable), 0|(1<<4)|(3<<9), NULL, NULL, NULL, OperandInfo17 }, // Inst #65 = BR_JTadd
- { 66, 5, 0, 0, "BR_JTm", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::Terminator)|(1<<TID::NotDuplicable), 0|(1<<4)|(3<<9), NULL, NULL, NULL, OperandInfo18 }, // Inst #66 = BR_JTm
- { 67, 3, 0, 0, "BR_JTr", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::NotDuplicable), 0|(1<<4)|(3<<9), NULL, NULL, NULL, OperandInfo19 }, // Inst #67 = BR_JTr
- { 68, 1, 0, 0, "BX", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(2<<4)|(3<<9), NULL, ImplicitList3, Barriers2, OperandInfo16 }, // Inst #68 = BX
- { 69, 2, 0, 0, "BX_RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Predicable)|(1<<TID::Terminator), 0|(3<<4)|(3<<9), NULL, NULL, NULL, OperandInfo20 }, // Inst #69 = BX_RET
- { 70, 1, 0, 0, "BXr9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(2<<4)|(3<<9), NULL, ImplicitList4, Barriers2, OperandInfo16 }, // Inst #70 = BXr9
- { 71, 3, 0, 0, "Bcc", 0|(1<<TID::Branch)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #71 = Bcc
- { 72, 4, 1, 125, "CLZ", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #72 = CLZ
- { 73, 4, 0, 97, "CMNzri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #73 = CMNzri
- { 74, 4, 0, 98, "CMNzrr", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #74 = CMNzrr
- { 75, 6, 0, 100, "CMNzrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #75 = CMNzrs
- { 76, 4, 0, 97, "CMPri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #76 = CMPri
- { 77, 4, 0, 98, "CMPrr", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #77 = CMPrr
- { 78, 6, 0, 100, "CMPrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #78 = CMPrs
- { 79, 4, 0, 97, "CMPzri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #79 = CMPzri
- { 80, 4, 0, 98, "CMPzrr", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #80 = CMPzrr
- { 81, 6, 0, 100, "CMPzrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #81 = CMPzrs
- { 82, 3, 0, 128, "CONSTPOOL_ENTRY", 0|(1<<TID::NotDuplicable), 0|(1<<4), NULL, NULL, NULL, OperandInfo24 }, // Inst #82 = CONSTPOOL_ENTRY
- { 83, 6, 1, 88, "EORri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #83 = EORri
- { 84, 6, 1, 89, "EORrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #84 = EORrr
- { 85, 8, 1, 91, "EORrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), NULL, NULL, NULL, OperandInfo7 }, // Inst #85 = EORrs
- { 86, 4, 1, 26, "FCONSTD", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|(3<<4)|(22<<9)|(1<<17), NULL, NULL, NULL, OperandInfo25 }, // Inst #86 = FCONSTD
- { 87, 4, 1, 26, "FCONSTS", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|(3<<4)|(22<<9)|(1<<17), NULL, NULL, NULL, OperandInfo26 }, // Inst #87 = FCONSTS
- { 88, 2, 0, 82, "FMSTAT", 0|(1<<TID::Predicable), 0|(3<<4)|(22<<9)|(1<<17), ImplicitList5, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #88 = FMSTAT
- { 89, 1, 0, 128, "Int_MemBarrierV6", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, OperandInfo16 }, // Inst #89 = Int_MemBarrierV6
- { 90, 0, 0, 128, "Int_MemBarrierV7", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, 0 }, // Inst #90 = Int_MemBarrierV7
- { 91, 1, 0, 128, "Int_SyncBarrierV6", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, OperandInfo16 }, // Inst #91 = Int_SyncBarrierV6
- { 92, 0, 0, 128, "Int_SyncBarrierV7", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, 0 }, // Inst #92 = Int_SyncBarrierV7
- { 93, 1, 0, 128, "Int_eh_sjlj_setjmp", 0, 0|(1<<4), NULL, ImplicitList6, Barriers3, OperandInfo16 }, // Inst #93 = Int_eh_sjlj_setjmp
- { 94, 5, 0, 103, "LDM", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|4|(3<<4)|(10<<9), NULL, NULL, NULL, OperandInfo28 }, // Inst #94 = LDM
- { 95, 5, 0, 0, "LDM_RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|4|(3<<4)|(10<<9), NULL, NULL, NULL, OperandInfo28 }, // Inst #95 = LDM_RET
- { 96, 6, 1, 104, "LDR", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|2|(3<<4)|(6<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #96 = LDR
- { 97, 6, 1, 104, "LDRB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|2|(3<<4)|(6<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #97 = LDRB
- { 98, 7, 2, 105, "LDRB_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|2|(3<<4)|(2<<7)|(6<<9), NULL, NULL, NULL, OperandInfo29 }, // Inst #98 = LDRB_POST
- { 99, 7, 2, 105, "LDRB_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|2|(3<<4)|(1<<7)|(6<<9), NULL, NULL, NULL, OperandInfo29 }, // Inst #99 = LDRB_PRE
- { 100, 7, 2, 104, "LDRD", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(8<<9), NULL, NULL, NULL, OperandInfo10 }, // Inst #100 = LDRD
- { 101, 4, 1, 128, "LDREX", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #101 = LDREX
- { 102, 4, 1, 128, "LDREXB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #102 = LDREXB
- { 103, 5, 2, 128, "LDREXD", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #103 = LDREXD
- { 104, 4, 1, 128, "LDREXH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #104 = LDREXH
- { 105, 6, 1, 104, "LDRH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|3|(3<<4)|(8<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #105 = LDRH
- { 106, 7, 2, 105, "LDRH_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(2<<7)|(8<<9), NULL, NULL, NULL, OperandInfo29 }, // Inst #106 = LDRH_POST
- { 107, 7, 2, 105, "LDRH_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(1<<7)|(8<<9), NULL, NULL, NULL, OperandInfo29 }, // Inst #107 = LDRH_PRE
- { 108, 6, 1, 104, "LDRSB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|3|(3<<4)|(8<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #108 = LDRSB
- { 109, 7, 2, 105, "LDRSB_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(2<<7)|(8<<9), NULL, NULL, NULL, OperandInfo29 }, // Inst #109 = LDRSB_POST
- { 110, 7, 2, 105, "LDRSB_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(1<<7)|(8<<9), NULL, NULL, NULL, OperandInfo29 }, // Inst #110 = LDRSB_PRE
- { 111, 6, 1, 104, "LDRSH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|3|(3<<4)|(8<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #111 = LDRSH
- { 112, 7, 2, 105, "LDRSH_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(2<<7)|(8<<9), NULL, NULL, NULL, OperandInfo29 }, // Inst #112 = LDRSH_POST
- { 113, 7, 2, 105, "LDRSH_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(1<<7)|(8<<9), NULL, NULL, NULL, OperandInfo29 }, // Inst #113 = LDRSH_PRE
- { 114, 7, 2, 105, "LDR_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|2|(3<<4)|(2<<7)|(6<<9), NULL, NULL, NULL, OperandInfo29 }, // Inst #114 = LDR_POST
- { 115, 7, 2, 105, "LDR_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|2|(3<<4)|(1<<7)|(6<<9), NULL, NULL, NULL, OperandInfo29 }, // Inst #115 = LDR_PRE
- { 116, 6, 1, 104, "LDRcp", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::UnmodeledSideEffects), 0|2|(3<<4)|(6<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #116 = LDRcp
- { 117, 4, 1, 88, "LEApcrel", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4), NULL, NULL, NULL, OperandInfo22 }, // Inst #117 = LEApcrel
- { 118, 5, 1, 88, "LEApcrelJT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4), NULL, NULL, NULL, OperandInfo30 }, // Inst #118 = LEApcrelJT
- { 119, 7, 1, 109, "MLA", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo31 }, // Inst #119 = MLA
- { 120, 6, 1, 109, "MLS", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #120 = MLS
- { 121, 5, 1, 93, "MOVCCi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo15 }, // Inst #121 = MOVCCi
- { 122, 5, 1, 94, "MOVCCr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo33 }, // Inst #122 = MOVCCr
- { 123, 7, 1, 96, "MOVCCs", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4)|(5<<9)|(1<<15), NULL, NULL, NULL, OperandInfo34 }, // Inst #123 = MOVCCs
- { 124, 5, 1, 111, "MOVTi16", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo15 }, // Inst #124 = MOVTi16
- { 125, 5, 1, 111, "MOVi", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::HasOptionalDef)|(1<<TID::CheapAsAMove), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo35 }, // Inst #125 = MOVi
- { 126, 4, 1, 111, "MOVi16", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #126 = MOVi16
- { 127, 4, 1, 111, "MOVi2pieces", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|1|(2<<4), NULL, NULL, NULL, OperandInfo22 }, // Inst #127 = MOVi2pieces
- { 128, 4, 1, 111, "MOVi32imm", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|1|(2<<4), NULL, NULL, NULL, OperandInfo22 }, // Inst #128 = MOVi32imm
- { 129, 5, 1, 112, "MOVr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo36 }, // Inst #129 = MOVr
- { 130, 5, 1, 113, "MOVrx", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(1<<15), ImplicitList1, NULL, NULL, OperandInfo36 }, // Inst #130 = MOVrx
- { 131, 7, 1, 114, "MOVs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9)|(1<<15), NULL, NULL, NULL, OperandInfo37 }, // Inst #131 = MOVs
- { 132, 4, 1, 113, "MOVsra_flag", 0|(1<<TID::Predicable), 0|1|(3<<4)|(1<<15), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #132 = MOVsra_flag
- { 133, 4, 1, 113, "MOVsrl_flag", 0|(1<<TID::Predicable), 0|1|(3<<4)|(1<<15), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #133 = MOVsrl_flag
- { 134, 6, 1, 116, "MUL", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #134 = MUL
- { 135, 5, 1, 111, "MVNi", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::HasOptionalDef)|(1<<TID::CheapAsAMove), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo35 }, // Inst #135 = MVNi
- { 136, 5, 1, 112, "MVNr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo36 }, // Inst #136 = MVNr
- { 137, 7, 1, 114, "MVNs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9)|(1<<15), NULL, NULL, NULL, OperandInfo37 }, // Inst #137 = MVNs
- { 138, 6, 1, 88, "ORRri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #138 = ORRri
- { 139, 6, 1, 89, "ORRrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #139 = ORRrr
- { 140, 8, 1, 91, "ORRrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), NULL, NULL, NULL, OperandInfo7 }, // Inst #140 = ORRrs
- { 141, 5, 1, 89, "PICADD", 0|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|1|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #141 = PICADD
- { 142, 5, 1, 104, "PICLDR", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|2|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #142 = PICLDR
- { 143, 5, 1, 104, "PICLDRB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|2|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #143 = PICLDRB
- { 144, 5, 1, 104, "PICLDRH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|3|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #144 = PICLDRH
- { 145, 5, 1, 104, "PICLDRSB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|3|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #145 = PICLDRSB
- { 146, 5, 1, 104, "PICLDRSH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|3|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #146 = PICLDRSH
- { 147, 5, 0, 121, "PICSTR", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|2|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #147 = PICSTR
- { 148, 5, 0, 121, "PICSTRB", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|2|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #148 = PICSTRB
- { 149, 5, 0, 121, "PICSTRH", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|3|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #149 = PICSTRH
- { 150, 6, 1, 90, "PKHBT", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #150 = PKHBT
- { 151, 6, 1, 90, "PKHTB", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #151 = PKHTB
- { 152, 4, 1, 125, "RBIT", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #152 = RBIT
- { 153, 4, 1, 125, "REV", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #153 = REV
- { 154, 4, 1, 125, "REV16", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #154 = REV16
- { 155, 4, 1, 125, "REVSH", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #155 = REVSH
- { 156, 5, 1, 88, "RSBSri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #156 = RSBSri
- { 157, 7, 1, 91, "RSBSrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #157 = RSBSrs
- { 158, 6, 1, 88, "RSBri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #158 = RSBri
- { 159, 8, 1, 91, "RSBrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), NULL, NULL, NULL, OperandInfo7 }, // Inst #159 = RSBrs
- { 160, 3, 1, 88, "RSCSri", 0, 0|1|(3<<4)|(4<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #160 = RSCSri
- { 161, 5, 1, 91, "RSCSrs", 0, 0|1|(3<<4)|(5<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #161 = RSCSrs
- { 162, 6, 1, 88, "RSCri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #162 = RSCri
- { 163, 8, 1, 91, "RSCrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), ImplicitList1, NULL, NULL, OperandInfo7 }, // Inst #163 = RSCrs
- { 164, 3, 1, 88, "SBCSSri", 0, 0|1|(3<<4)|(4<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #164 = SBCSSri
- { 165, 3, 1, 89, "SBCSSrr", 0, 0|1|(3<<4)|(4<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #165 = SBCSSrr
- { 166, 5, 1, 91, "SBCSSrs", 0, 0|1|(3<<4)|(5<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #166 = SBCSSrs
- { 167, 6, 1, 88, "SBCri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #167 = SBCri
- { 168, 6, 1, 89, "SBCrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), ImplicitList1, NULL, NULL, OperandInfo6 }, // Inst #168 = SBCrr
- { 169, 8, 1, 91, "SBCrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), ImplicitList1, NULL, NULL, OperandInfo7 }, // Inst #169 = SBCrs
- { 170, 6, 1, 88, "SBFX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo38 }, // Inst #170 = SBFX
- { 171, 6, 1, 108, "SMLABB", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #171 = SMLABB
- { 172, 6, 1, 108, "SMLABT", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #172 = SMLABT
- { 173, 7, 2, 110, "SMLAL", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo31 }, // Inst #173 = SMLAL
- { 174, 6, 1, 108, "SMLATB", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #174 = SMLATB
- { 175, 6, 1, 108, "SMLATT", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #175 = SMLATT
- { 176, 6, 1, 108, "SMLAWB", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #176 = SMLAWB
- { 177, 6, 1, 108, "SMLAWT", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #177 = SMLAWT
- { 178, 6, 1, 109, "SMMLA", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #178 = SMMLA
- { 179, 6, 1, 109, "SMMLS", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #179 = SMMLS
- { 180, 5, 1, 116, "SMMUL", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #180 = SMMUL
- { 181, 5, 1, 116, "SMULBB", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #181 = SMULBB
- { 182, 5, 1, 116, "SMULBT", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #182 = SMULBT
- { 183, 7, 2, 117, "SMULL", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo31 }, // Inst #183 = SMULL
- { 184, 5, 1, 116, "SMULTB", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #184 = SMULTB
- { 185, 5, 1, 116, "SMULTT", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #185 = SMULTT
- { 186, 5, 1, 115, "SMULWB", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #186 = SMULWB
- { 187, 5, 1, 115, "SMULWT", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #187 = SMULWT
- { 188, 5, 0, 120, "STM", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|4|(3<<4)|(10<<9), NULL, NULL, NULL, OperandInfo28 }, // Inst #188 = STM
- { 189, 6, 0, 121, "STR", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|2|(3<<4)|(7<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #189 = STR
- { 190, 6, 0, 121, "STRB", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|2|(3<<4)|(7<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #190 = STRB
- { 191, 7, 1, 122, "STRB_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|2|(3<<4)|(2<<7)|(7<<9), NULL, NULL, NULL, OperandInfo39 }, // Inst #191 = STRB_POST
- { 192, 7, 1, 122, "STRB_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|2|(3<<4)|(1<<7)|(7<<9), NULL, NULL, NULL, OperandInfo39 }, // Inst #192 = STRB_PRE
- { 193, 7, 0, 121, "STRD", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|3|(3<<4)|(9<<9), NULL, NULL, NULL, OperandInfo10 }, // Inst #193 = STRD
- { 194, 5, 1, 128, "STREX", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #194 = STREX
- { 195, 5, 1, 128, "STREXB", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #195 = STREXB
- { 196, 6, 1, 128, "STREXD", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo41 }, // Inst #196 = STREXD
- { 197, 5, 1, 128, "STREXH", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #197 = STREXH
- { 198, 6, 0, 121, "STRH", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|3|(3<<4)|(9<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #198 = STRH
- { 199, 7, 1, 122, "STRH_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|3|(3<<4)|(2<<7)|(9<<9), NULL, NULL, NULL, OperandInfo39 }, // Inst #199 = STRH_POST
- { 200, 7, 1, 122, "STRH_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|3|(3<<4)|(1<<7)|(9<<9), NULL, NULL, NULL, OperandInfo39 }, // Inst #200 = STRH_PRE
- { 201, 7, 1, 122, "STR_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|2|(3<<4)|(2<<7)|(7<<9), NULL, NULL, NULL, OperandInfo39 }, // Inst #201 = STR_POST
- { 202, 7, 1, 122, "STR_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|2|(3<<4)|(1<<7)|(7<<9), NULL, NULL, NULL, OperandInfo39 }, // Inst #202 = STR_PRE
- { 203, 5, 1, 88, "SUBSri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #203 = SUBSri
- { 204, 5, 1, 89, "SUBSrr", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #204 = SUBSrr
- { 205, 7, 1, 91, "SUBSrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #205 = SUBSrs
- { 206, 6, 1, 88, "SUBri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #206 = SUBri
- { 207, 6, 1, 89, "SUBrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #207 = SUBrr
- { 208, 8, 1, 91, "SUBrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), NULL, NULL, NULL, OperandInfo7 }, // Inst #208 = SUBrs
- { 209, 5, 1, 89, "SXTABrr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #209 = SXTABrr
- { 210, 6, 1, 90, "SXTABrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #210 = SXTABrr_rot
- { 211, 5, 1, 89, "SXTAHrr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #211 = SXTAHrr
- { 212, 6, 1, 90, "SXTAHrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #212 = SXTAHrr_rot
- { 213, 4, 1, 125, "SXTBr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #213 = SXTBr
- { 214, 5, 1, 126, "SXTBr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #214 = SXTBr_rot
- { 215, 4, 1, 125, "SXTHr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #215 = SXTHr
- { 216, 5, 1, 126, "SXTHr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #216 = SXTHr_rot
- { 217, 4, 0, 97, "TEQri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #217 = TEQri
- { 218, 4, 0, 98, "TEQrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #218 = TEQrr
- { 219, 6, 0, 100, "TEQrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #219 = TEQrs
- { 220, 0, 0, 0, "TPsoft", 0|(1<<TID::Call), 0|(3<<4)|(2<<9), NULL, ImplicitList7, Barriers1, 0 }, // Inst #220 = TPsoft
- { 221, 4, 0, 97, "TSTri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #221 = TSTri
- { 222, 4, 0, 98, "TSTrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #222 = TSTrr
- { 223, 6, 0, 100, "TSTrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #223 = TSTrs
- { 224, 6, 1, 88, "UBFX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo38 }, // Inst #224 = UBFX
- { 225, 6, 2, 110, "UMAAL", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #225 = UMAAL
- { 226, 7, 2, 110, "UMLAL", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo31 }, // Inst #226 = UMLAL
- { 227, 7, 2, 117, "UMULL", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo31 }, // Inst #227 = UMULL
- { 228, 5, 1, 89, "UXTABrr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #228 = UXTABrr
- { 229, 6, 1, 90, "UXTABrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #229 = UXTABrr_rot
- { 230, 5, 1, 89, "UXTAHrr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #230 = UXTAHrr
- { 231, 6, 1, 90, "UXTAHrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #231 = UXTAHrr_rot
- { 232, 4, 1, 125, "UXTB16r", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #232 = UXTB16r
- { 233, 5, 1, 126, "UXTB16r_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #233 = UXTB16r_rot
- { 234, 4, 1, 125, "UXTBr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #234 = UXTBr
- { 235, 5, 1, 126, "UXTBr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #235 = UXTBr_rot
- { 236, 4, 1, 125, "UXTHr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #236 = UXTHr
- { 237, 5, 1, 126, "UXTHr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #237 = UXTHr_rot
- { 238, 6, 1, 17, "VABALsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #238 = VABALsv2i64
- { 239, 6, 1, 17, "VABALsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #239 = VABALsv4i32
- { 240, 6, 1, 17, "VABALsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #240 = VABALsv8i16
- { 241, 6, 1, 17, "VABALuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #241 = VABALuv2i64
- { 242, 6, 1, 17, "VABALuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #242 = VABALuv4i32
- { 243, 6, 1, 17, "VABALuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #243 = VABALuv8i16
- { 244, 6, 1, 18, "VABAsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #244 = VABAsv16i8
- { 245, 6, 1, 19, "VABAsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #245 = VABAsv2i32
- { 246, 6, 1, 17, "VABAsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #246 = VABAsv4i16
- { 247, 6, 1, 20, "VABAsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #247 = VABAsv4i32
- { 248, 6, 1, 18, "VABAsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #248 = VABAsv8i16
- { 249, 6, 1, 17, "VABAsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #249 = VABAsv8i8
- { 250, 6, 1, 18, "VABAuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #250 = VABAuv16i8
- { 251, 6, 1, 19, "VABAuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #251 = VABAuv2i32
- { 252, 6, 1, 17, "VABAuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #252 = VABAuv4i16
- { 253, 6, 1, 20, "VABAuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #253 = VABAuv4i32
- { 254, 6, 1, 18, "VABAuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #254 = VABAuv8i16
- { 255, 6, 1, 17, "VABAuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #255 = VABAuv8i8
- { 256, 5, 1, 4, "VABDLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #256 = VABDLsv2i64
- { 257, 5, 1, 4, "VABDLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #257 = VABDLsv4i32
- { 258, 5, 1, 4, "VABDLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #258 = VABDLsv8i16
- { 259, 5, 1, 4, "VABDLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #259 = VABDLuv2i64
- { 260, 5, 1, 4, "VABDLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #260 = VABDLuv4i32
- { 261, 5, 1, 4, "VABDLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #261 = VABDLuv8i16
- { 262, 5, 1, 1, "VABDfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #262 = VABDfd
- { 263, 5, 1, 2, "VABDfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #263 = VABDfq
- { 264, 5, 1, 4, "VABDsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #264 = VABDsv16i8
- { 265, 5, 1, 3, "VABDsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #265 = VABDsv2i32
- { 266, 5, 1, 3, "VABDsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #266 = VABDsv4i16
- { 267, 5, 1, 4, "VABDsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #267 = VABDsv4i32
- { 268, 5, 1, 4, "VABDsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #268 = VABDsv8i16
- { 269, 5, 1, 3, "VABDsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #269 = VABDsv8i8
- { 270, 5, 1, 4, "VABDuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #270 = VABDuv16i8
- { 271, 5, 1, 3, "VABDuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #271 = VABDuv2i32
- { 272, 5, 1, 3, "VABDuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #272 = VABDuv4i16
- { 273, 5, 1, 4, "VABDuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #273 = VABDuv4i32
- { 274, 5, 1, 4, "VABDuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #274 = VABDuv8i16
- { 275, 5, 1, 3, "VABDuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #275 = VABDuv8i8
- { 276, 4, 1, 87, "VABSD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #276 = VABSD
- { 277, 4, 1, 86, "VABSS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #277 = VABSS
- { 278, 4, 1, 57, "VABSfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #278 = VABSfd
- { 279, 4, 1, 57, "VABSfd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #279 = VABSfd_sfp
- { 280, 4, 1, 58, "VABSfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #280 = VABSfq
- { 281, 4, 1, 60, "VABSv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #281 = VABSv16i8
- { 282, 4, 1, 59, "VABSv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #282 = VABSv2i32
- { 283, 4, 1, 59, "VABSv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #283 = VABSv4i16
- { 284, 4, 1, 60, "VABSv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #284 = VABSv4i32
- { 285, 4, 1, 60, "VABSv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #285 = VABSv8i16
- { 286, 4, 1, 59, "VABSv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #286 = VABSv8i8
- { 287, 5, 1, 1, "VACGEd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #287 = VACGEd
- { 288, 5, 1, 2, "VACGEq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #288 = VACGEq
- { 289, 5, 1, 1, "VACGTd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #289 = VACGTd
- { 290, 5, 1, 2, "VACGTq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #290 = VACGTq
- { 291, 5, 1, 62, "VADDD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #291 = VADDD
- { 292, 5, 1, 3, "VADDHNv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #292 = VADDHNv2i32
- { 293, 5, 1, 3, "VADDHNv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #293 = VADDHNv4i16
- { 294, 5, 1, 3, "VADDHNv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #294 = VADDHNv8i8
- { 295, 5, 1, 44, "VADDLsv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #295 = VADDLsv2i64
- { 296, 5, 1, 44, "VADDLsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #296 = VADDLsv4i32
- { 297, 5, 1, 44, "VADDLsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #297 = VADDLsv8i16
- { 298, 5, 1, 44, "VADDLuv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #298 = VADDLuv2i64
- { 299, 5, 1, 44, "VADDLuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #299 = VADDLuv4i32
- { 300, 5, 1, 44, "VADDLuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #300 = VADDLuv8i16
- { 301, 5, 1, 61, "VADDS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #301 = VADDS
- { 302, 5, 1, 47, "VADDWsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #302 = VADDWsv2i64
- { 303, 5, 1, 47, "VADDWsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #303 = VADDWsv4i32
- { 304, 5, 1, 47, "VADDWsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #304 = VADDWsv8i16
- { 305, 5, 1, 47, "VADDWuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #305 = VADDWuv2i64
- { 306, 5, 1, 47, "VADDWuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #306 = VADDWuv4i32
- { 307, 5, 1, 47, "VADDWuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #307 = VADDWuv8i16
- { 308, 5, 1, 1, "VADDfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #308 = VADDfd
- { 309, 5, 1, 1, "VADDfd_sfp", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #309 = VADDfd_sfp
- { 310, 5, 1, 2, "VADDfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #310 = VADDfq
- { 311, 5, 1, 6, "VADDv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #311 = VADDv16i8
- { 312, 5, 1, 5, "VADDv1i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #312 = VADDv1i64
- { 313, 5, 1, 5, "VADDv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #313 = VADDv2i32
- { 314, 5, 1, 6, "VADDv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #314 = VADDv2i64
- { 315, 5, 1, 5, "VADDv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #315 = VADDv4i16
- { 316, 5, 1, 6, "VADDv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #316 = VADDv4i32
- { 317, 5, 1, 6, "VADDv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #317 = VADDv8i16
- { 318, 5, 1, 5, "VADDv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #318 = VADDv8i8
- { 319, 5, 1, 5, "VANDd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #319 = VANDd
- { 320, 5, 1, 6, "VANDq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #320 = VANDq
- { 321, 5, 1, 5, "VBICd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #321 = VBICd
- { 322, 5, 1, 6, "VBICq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #322 = VBICq
- { 323, 6, 1, 7, "VBSLd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #323 = VBSLd
- { 324, 6, 1, 8, "VBSLq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #324 = VBSLq
- { 325, 5, 1, 1, "VCEQfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #325 = VCEQfd
- { 326, 5, 1, 2, "VCEQfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #326 = VCEQfq
- { 327, 5, 1, 4, "VCEQv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #327 = VCEQv16i8
- { 328, 5, 1, 3, "VCEQv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #328 = VCEQv2i32
- { 329, 5, 1, 3, "VCEQv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #329 = VCEQv4i16
- { 330, 5, 1, 4, "VCEQv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #330 = VCEQv4i32
- { 331, 5, 1, 4, "VCEQv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #331 = VCEQv8i16
- { 332, 5, 1, 3, "VCEQv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #332 = VCEQv8i8
- { 333, 5, 1, 1, "VCGEfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #333 = VCGEfd
- { 334, 5, 1, 2, "VCGEfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #334 = VCGEfq
- { 335, 5, 1, 4, "VCGEsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #335 = VCGEsv16i8
- { 336, 5, 1, 3, "VCGEsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #336 = VCGEsv2i32
- { 337, 5, 1, 3, "VCGEsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #337 = VCGEsv4i16
- { 338, 5, 1, 4, "VCGEsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #338 = VCGEsv4i32
- { 339, 5, 1, 4, "VCGEsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #339 = VCGEsv8i16
- { 340, 5, 1, 3, "VCGEsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #340 = VCGEsv8i8
- { 341, 5, 1, 4, "VCGEuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #341 = VCGEuv16i8
- { 342, 5, 1, 3, "VCGEuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #342 = VCGEuv2i32
- { 343, 5, 1, 3, "VCGEuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #343 = VCGEuv4i16
- { 344, 5, 1, 4, "VCGEuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #344 = VCGEuv4i32
- { 345, 5, 1, 4, "VCGEuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #345 = VCGEuv8i16
- { 346, 5, 1, 3, "VCGEuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #346 = VCGEuv8i8
- { 347, 5, 1, 1, "VCGTfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #347 = VCGTfd
- { 348, 5, 1, 2, "VCGTfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #348 = VCGTfq
- { 349, 5, 1, 4, "VCGTsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #349 = VCGTsv16i8
- { 350, 5, 1, 3, "VCGTsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #350 = VCGTsv2i32
- { 351, 5, 1, 3, "VCGTsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #351 = VCGTsv4i16
- { 352, 5, 1, 4, "VCGTsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #352 = VCGTsv4i32
- { 353, 5, 1, 4, "VCGTsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #353 = VCGTsv8i16
- { 354, 5, 1, 3, "VCGTsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #354 = VCGTsv8i8
- { 355, 5, 1, 4, "VCGTuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #355 = VCGTuv16i8
- { 356, 5, 1, 3, "VCGTuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #356 = VCGTuv2i32
- { 357, 5, 1, 3, "VCGTuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #357 = VCGTuv4i16
- { 358, 5, 1, 4, "VCGTuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #358 = VCGTuv4i32
- { 359, 5, 1, 4, "VCGTuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #359 = VCGTuv8i16
- { 360, 5, 1, 3, "VCGTuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #360 = VCGTuv8i8
- { 361, 4, 1, 8, "VCLSv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #361 = VCLSv16i8
- { 362, 4, 1, 7, "VCLSv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #362 = VCLSv2i32
- { 363, 4, 1, 7, "VCLSv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #363 = VCLSv4i16
- { 364, 4, 1, 8, "VCLSv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #364 = VCLSv4i32
- { 365, 4, 1, 8, "VCLSv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #365 = VCLSv8i16
- { 366, 4, 1, 7, "VCLSv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #366 = VCLSv8i8
- { 367, 4, 1, 8, "VCLZv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #367 = VCLZv16i8
- { 368, 4, 1, 7, "VCLZv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #368 = VCLZv2i32
- { 369, 4, 1, 7, "VCLZv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #369 = VCLZv4i16
- { 370, 4, 1, 8, "VCLZv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #370 = VCLZv4i32
- { 371, 4, 1, 8, "VCLZv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #371 = VCLZv8i16
- { 372, 4, 1, 7, "VCLZv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #372 = VCLZv8i8
- { 373, 4, 0, 64, "VCMPED", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo49 }, // Inst #373 = VCMPED
- { 374, 4, 0, 63, "VCMPES", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo50 }, // Inst #374 = VCMPES
- { 375, 3, 0, 64, "VCMPEZD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo57 }, // Inst #375 = VCMPEZD
- { 376, 3, 0, 63, "VCMPEZS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo58 }, // Inst #376 = VCMPEZS
- { 377, 4, 1, 7, "VCNTd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #377 = VCNTd
- { 378, 4, 1, 8, "VCNTq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #378 = VCNTq
- { 379, 4, 1, 66, "VCVTDS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #379 = VCVTDS
- { 380, 4, 1, 69, "VCVTSD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #380 = VCVTSD
- { 381, 4, 1, 57, "VCVTf2sd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #381 = VCVTf2sd
- { 382, 4, 1, 57, "VCVTf2sd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #382 = VCVTf2sd_sfp
- { 383, 4, 1, 58, "VCVTf2sq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #383 = VCVTf2sq
- { 384, 4, 1, 57, "VCVTf2ud", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #384 = VCVTf2ud
- { 385, 4, 1, 57, "VCVTf2ud_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #385 = VCVTf2ud_sfp
- { 386, 4, 1, 58, "VCVTf2uq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #386 = VCVTf2uq
- { 387, 5, 1, 57, "VCVTf2xsd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #387 = VCVTf2xsd
- { 388, 5, 1, 58, "VCVTf2xsq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #388 = VCVTf2xsq
- { 389, 5, 1, 57, "VCVTf2xud", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #389 = VCVTf2xud
- { 390, 5, 1, 58, "VCVTf2xuq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #390 = VCVTf2xuq
- { 391, 4, 1, 57, "VCVTs2fd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #391 = VCVTs2fd
- { 392, 4, 1, 57, "VCVTs2fd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #392 = VCVTs2fd_sfp
- { 393, 4, 1, 58, "VCVTs2fq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #393 = VCVTs2fq
- { 394, 4, 1, 57, "VCVTu2fd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #394 = VCVTu2fd
- { 395, 4, 1, 57, "VCVTu2fd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #395 = VCVTu2fd_sfp
- { 396, 4, 1, 58, "VCVTu2fq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #396 = VCVTu2fq
- { 397, 5, 1, 57, "VCVTxs2fd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #397 = VCVTxs2fd
- { 398, 5, 1, 58, "VCVTxs2fq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #398 = VCVTxs2fq
- { 399, 5, 1, 57, "VCVTxu2fd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #399 = VCVTxu2fd
- { 400, 5, 1, 58, "VCVTxu2fq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #400 = VCVTxu2fq
- { 401, 5, 1, 72, "VDIVD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #401 = VDIVD
- { 402, 5, 1, 71, "VDIVS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #402 = VDIVS
- { 403, 4, 1, 24, "VDUP16d", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo63 }, // Inst #403 = VDUP16d
- { 404, 4, 1, 24, "VDUP16q", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo64 }, // Inst #404 = VDUP16q
- { 405, 4, 1, 24, "VDUP32d", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo63 }, // Inst #405 = VDUP32d
- { 406, 4, 1, 24, "VDUP32q", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo64 }, // Inst #406 = VDUP32q
- { 407, 4, 1, 24, "VDUP8d", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo63 }, // Inst #407 = VDUP8d
- { 408, 4, 1, 24, "VDUP8q", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo64 }, // Inst #408 = VDUP8q
- { 409, 5, 1, 21, "VDUPLN16d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #409 = VDUPLN16d
- { 410, 5, 1, 21, "VDUPLN16q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #410 = VDUPLN16q
- { 411, 5, 1, 21, "VDUPLN32d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #411 = VDUPLN32d
- { 412, 5, 1, 21, "VDUPLN32q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #412 = VDUPLN32q
- { 413, 5, 1, 21, "VDUPLN8d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #413 = VDUPLN8d
- { 414, 5, 1, 21, "VDUPLN8q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #414 = VDUPLN8q
- { 415, 5, 1, 21, "VDUPLNfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #415 = VDUPLNfd
- { 416, 5, 1, 21, "VDUPLNfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #416 = VDUPLNfq
- { 417, 4, 1, 24, "VDUPfd", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo63 }, // Inst #417 = VDUPfd
- { 418, 4, 1, 21, "VDUPfdf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #418 = VDUPfdf
- { 419, 4, 1, 24, "VDUPfq", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo64 }, // Inst #419 = VDUPfq
- { 420, 4, 1, 21, "VDUPfqf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo66 }, // Inst #420 = VDUPfqf
- { 421, 5, 1, 5, "VEORd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #421 = VEORd
- { 422, 5, 1, 6, "VEORq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #422 = VEORq
- { 423, 6, 1, 9, "VEXTd16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo67 }, // Inst #423 = VEXTd16
- { 424, 6, 1, 9, "VEXTd32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo67 }, // Inst #424 = VEXTd32
- { 425, 6, 1, 9, "VEXTd8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo67 }, // Inst #425 = VEXTd8
- { 426, 6, 1, 9, "VEXTdf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo67 }, // Inst #426 = VEXTdf
- { 427, 6, 1, 10, "VEXTq16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #427 = VEXTq16
- { 428, 6, 1, 10, "VEXTq32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #428 = VEXTq32
- { 429, 6, 1, 10, "VEXTq8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #429 = VEXTq8
- { 430, 6, 1, 10, "VEXTqf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #430 = VEXTqf
- { 431, 5, 1, 28, "VGETLNi32", 0|(1<<TID::Predicable), 0|(3<<4)|(25<<9), NULL, NULL, NULL, OperandInfo69 }, // Inst #431 = VGETLNi32
- { 432, 5, 1, 28, "VGETLNs16", 0|(1<<TID::Predicable), 0|(3<<4)|(25<<9), NULL, NULL, NULL, OperandInfo69 }, // Inst #432 = VGETLNs16
- { 433, 5, 1, 28, "VGETLNs8", 0|(1<<TID::Predicable), 0|(3<<4)|(25<<9), NULL, NULL, NULL, OperandInfo69 }, // Inst #433 = VGETLNs8
- { 434, 5, 1, 28, "VGETLNu16", 0|(1<<TID::Predicable), 0|(3<<4)|(25<<9), NULL, NULL, NULL, OperandInfo69 }, // Inst #434 = VGETLNu16
- { 435, 5, 1, 28, "VGETLNu8", 0|(1<<TID::Predicable), 0|(3<<4)|(25<<9), NULL, NULL, NULL, OperandInfo69 }, // Inst #435 = VGETLNu8
- { 436, 5, 1, 4, "VHADDsv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #436 = VHADDsv16i8
- { 437, 5, 1, 3, "VHADDsv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #437 = VHADDsv2i32
- { 438, 5, 1, 3, "VHADDsv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #438 = VHADDsv4i16
- { 439, 5, 1, 4, "VHADDsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #439 = VHADDsv4i32
- { 440, 5, 1, 4, "VHADDsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #440 = VHADDsv8i16
- { 441, 5, 1, 3, "VHADDsv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #441 = VHADDsv8i8
- { 442, 5, 1, 4, "VHADDuv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #442 = VHADDuv16i8
- { 443, 5, 1, 3, "VHADDuv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #443 = VHADDuv2i32
- { 444, 5, 1, 3, "VHADDuv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #444 = VHADDuv4i16
- { 445, 5, 1, 4, "VHADDuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #445 = VHADDuv4i32
- { 446, 5, 1, 4, "VHADDuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #446 = VHADDuv8i16
- { 447, 5, 1, 3, "VHADDuv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #447 = VHADDuv8i8
- { 448, 5, 1, 4, "VHSUBsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #448 = VHSUBsv16i8
- { 449, 5, 1, 3, "VHSUBsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #449 = VHSUBsv2i32
- { 450, 5, 1, 3, "VHSUBsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #450 = VHSUBsv4i16
- { 451, 5, 1, 4, "VHSUBsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #451 = VHSUBsv4i32
- { 452, 5, 1, 4, "VHSUBsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #452 = VHSUBsv8i16
- { 453, 5, 1, 3, "VHSUBsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #453 = VHSUBsv8i8
- { 454, 5, 1, 4, "VHSUBuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #454 = VHSUBuv16i8
- { 455, 5, 1, 3, "VHSUBuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #455 = VHSUBuv2i32
- { 456, 5, 1, 3, "VHSUBuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #456 = VHSUBuv4i16
- { 457, 5, 1, 4, "VHSUBuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #457 = VHSUBuv4i32
- { 458, 5, 1, 4, "VHSUBuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #458 = VHSUBuv8i16
- { 459, 5, 1, 3, "VHSUBuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #459 = VHSUBuv8i8
- { 460, 7, 1, 11, "VLD1d16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #460 = VLD1d16
- { 461, 7, 1, 11, "VLD1d32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #461 = VLD1d32
- { 462, 7, 1, 11, "VLD1d64", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #462 = VLD1d64
- { 463, 7, 1, 11, "VLD1d8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #463 = VLD1d8
- { 464, 7, 1, 11, "VLD1df", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #464 = VLD1df
- { 465, 7, 1, 11, "VLD1q16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 }, // Inst #465 = VLD1q16
- { 466, 7, 1, 11, "VLD1q32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 }, // Inst #466 = VLD1q32
- { 467, 7, 1, 11, "VLD1q64", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 }, // Inst #467 = VLD1q64
- { 468, 7, 1, 11, "VLD1q8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 }, // Inst #468 = VLD1q8
- { 469, 7, 1, 11, "VLD1qf", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 }, // Inst #469 = VLD1qf
- { 470, 11, 2, 12, "VLD2LNd16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo72 }, // Inst #470 = VLD2LNd16
- { 471, 11, 2, 12, "VLD2LNd32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo72 }, // Inst #471 = VLD2LNd32
- { 472, 11, 2, 12, "VLD2LNd8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo72 }, // Inst #472 = VLD2LNd8
- { 473, 11, 2, 12, "VLD2LNq16a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo72 }, // Inst #473 = VLD2LNq16a
- { 474, 11, 2, 12, "VLD2LNq16b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo72 }, // Inst #474 = VLD2LNq16b
- { 475, 11, 2, 12, "VLD2LNq32a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo72 }, // Inst #475 = VLD2LNq32a
- { 476, 11, 2, 12, "VLD2LNq32b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo72 }, // Inst #476 = VLD2LNq32b
- { 477, 8, 2, 12, "VLD2d16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo73 }, // Inst #477 = VLD2d16
- { 478, 8, 2, 12, "VLD2d32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo73 }, // Inst #478 = VLD2d32
- { 479, 8, 2, 11, "VLD2d64", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo73 }, // Inst #479 = VLD2d64
- { 480, 8, 2, 12, "VLD2d8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo73 }, // Inst #480 = VLD2d8
- { 481, 10, 4, 12, "VLD2q16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo74 }, // Inst #481 = VLD2q16
- { 482, 10, 4, 12, "VLD2q32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo74 }, // Inst #482 = VLD2q32
- { 483, 10, 4, 12, "VLD2q8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo74 }, // Inst #483 = VLD2q8
- { 484, 13, 3, 13, "VLD3LNd16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo75 }, // Inst #484 = VLD3LNd16
- { 485, 13, 3, 13, "VLD3LNd32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo75 }, // Inst #485 = VLD3LNd32
- { 486, 13, 3, 13, "VLD3LNd8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo75 }, // Inst #486 = VLD3LNd8
- { 487, 13, 3, 13, "VLD3LNq16a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo75 }, // Inst #487 = VLD3LNq16a
- { 488, 13, 3, 13, "VLD3LNq16b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo75 }, // Inst #488 = VLD3LNq16b
- { 489, 13, 3, 13, "VLD3LNq32a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo75 }, // Inst #489 = VLD3LNq32a
- { 490, 13, 3, 13, "VLD3LNq32b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo75 }, // Inst #490 = VLD3LNq32b
- { 491, 9, 3, 13, "VLD3d16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo76 }, // Inst #491 = VLD3d16
- { 492, 9, 3, 13, "VLD3d32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo76 }, // Inst #492 = VLD3d32
- { 493, 9, 3, 11, "VLD3d64", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo76 }, // Inst #493 = VLD3d64
- { 494, 9, 3, 13, "VLD3d8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo76 }, // Inst #494 = VLD3d8
- { 495, 10, 4, 13, "VLD3q16a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #495 = VLD3q16a
- { 496, 10, 4, 13, "VLD3q16b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #496 = VLD3q16b
- { 497, 10, 4, 13, "VLD3q32a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #497 = VLD3q32a
- { 498, 10, 4, 13, "VLD3q32b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #498 = VLD3q32b
- { 499, 10, 4, 13, "VLD3q8a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #499 = VLD3q8a
- { 500, 10, 4, 13, "VLD3q8b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #500 = VLD3q8b
- { 501, 15, 4, 14, "VLD4LNd16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #501 = VLD4LNd16
- { 502, 15, 4, 14, "VLD4LNd32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #502 = VLD4LNd32
- { 503, 15, 4, 14, "VLD4LNd8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #503 = VLD4LNd8
- { 504, 15, 4, 14, "VLD4LNq16a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #504 = VLD4LNq16a
- { 505, 15, 4, 14, "VLD4LNq16b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #505 = VLD4LNq16b
- { 506, 15, 4, 14, "VLD4LNq32a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #506 = VLD4LNq32a
- { 507, 15, 4, 14, "VLD4LNq32b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #507 = VLD4LNq32b
- { 508, 10, 4, 14, "VLD4d16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo74 }, // Inst #508 = VLD4d16
- { 509, 10, 4, 14, "VLD4d32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo74 }, // Inst #509 = VLD4d32
- { 510, 10, 4, 11, "VLD4d64", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo74 }, // Inst #510 = VLD4d64
- { 511, 10, 4, 14, "VLD4d8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo74 }, // Inst #511 = VLD4d8
- { 512, 11, 5, 14, "VLD4q16a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo79 }, // Inst #512 = VLD4q16a
- { 513, 11, 5, 14, "VLD4q16b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo79 }, // Inst #513 = VLD4q16b
- { 514, 11, 5, 14, "VLD4q32a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo79 }, // Inst #514 = VLD4q32a
- { 515, 11, 5, 14, "VLD4q32b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo79 }, // Inst #515 = VLD4q32b
- { 516, 11, 5, 14, "VLD4q8a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo79 }, // Inst #516 = VLD4q8a
- { 517, 11, 5, 14, "VLD4q8b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo79 }, // Inst #517 = VLD4q8b
- { 518, 5, 0, 75, "VLDMD", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|5|(3<<4)|(21<<9)|(3<<17), NULL, NULL, NULL, OperandInfo28 }, // Inst #518 = VLDMD
- { 519, 5, 0, 75, "VLDMS", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|5|(3<<4)|(21<<9)|(1<<17), NULL, NULL, NULL, OperandInfo28 }, // Inst #519 = VLDMS
- { 520, 5, 1, 74, "VLDRD", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|5|(3<<4)|(20<<9)|(3<<17), NULL, NULL, NULL, OperandInfo80 }, // Inst #520 = VLDRD
- { 521, 5, 1, 75, "VLDRQ", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|4|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #521 = VLDRQ
- { 522, 5, 1, 73, "VLDRS", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|5|(3<<4)|(20<<9)|(1<<17), NULL, NULL, NULL, OperandInfo82 }, // Inst #522 = VLDRS
- { 523, 5, 1, 1, "VMAXfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #523 = VMAXfd
- { 524, 5, 1, 2, "VMAXfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #524 = VMAXfq
- { 525, 5, 1, 4, "VMAXsv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #525 = VMAXsv16i8
- { 526, 5, 1, 3, "VMAXsv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #526 = VMAXsv2i32
- { 527, 5, 1, 3, "VMAXsv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #527 = VMAXsv4i16
- { 528, 5, 1, 4, "VMAXsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #528 = VMAXsv4i32
- { 529, 5, 1, 4, "VMAXsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #529 = VMAXsv8i16
- { 530, 5, 1, 3, "VMAXsv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #530 = VMAXsv8i8
- { 531, 5, 1, 4, "VMAXuv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #531 = VMAXuv16i8
- { 532, 5, 1, 3, "VMAXuv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #532 = VMAXuv2i32
- { 533, 5, 1, 3, "VMAXuv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #533 = VMAXuv4i16
- { 534, 5, 1, 4, "VMAXuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #534 = VMAXuv4i32
- { 535, 5, 1, 4, "VMAXuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #535 = VMAXuv8i16
- { 536, 5, 1, 3, "VMAXuv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #536 = VMAXuv8i8
- { 537, 5, 1, 1, "VMINfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #537 = VMINfd
- { 538, 5, 1, 2, "VMINfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #538 = VMINfq
- { 539, 5, 1, 4, "VMINsv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #539 = VMINsv16i8
- { 540, 5, 1, 3, "VMINsv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #540 = VMINsv2i32
- { 541, 5, 1, 3, "VMINsv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #541 = VMINsv4i16
- { 542, 5, 1, 4, "VMINsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #542 = VMINsv4i32
- { 543, 5, 1, 4, "VMINsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #543 = VMINsv8i16
- { 544, 5, 1, 3, "VMINsv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #544 = VMINsv8i8
- { 545, 5, 1, 4, "VMINuv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #545 = VMINuv16i8
- { 546, 5, 1, 3, "VMINuv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #546 = VMINuv2i32
- { 547, 5, 1, 3, "VMINuv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #547 = VMINuv4i16
- { 548, 5, 1, 4, "VMINuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #548 = VMINuv4i32
- { 549, 5, 1, 4, "VMINuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #549 = VMINuv8i16
- { 550, 5, 1, 3, "VMINuv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #550 = VMINuv8i8
- { 551, 6, 1, 77, "VMLAD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #551 = VMLAD
- { 552, 7, 1, 19, "VMLALslsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo83 }, // Inst #552 = VMLALslsv2i32
- { 553, 7, 1, 17, "VMLALslsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo84 }, // Inst #553 = VMLALslsv4i16
- { 554, 7, 1, 19, "VMLALsluv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo83 }, // Inst #554 = VMLALsluv2i32
- { 555, 7, 1, 17, "VMLALsluv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo84 }, // Inst #555 = VMLALsluv4i16
- { 556, 6, 1, 17, "VMLALsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #556 = VMLALsv2i64
- { 557, 6, 1, 17, "VMLALsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #557 = VMLALsv4i32
- { 558, 6, 1, 17, "VMLALsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #558 = VMLALsv8i16
- { 559, 6, 1, 17, "VMLALuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #559 = VMLALuv2i64
- { 560, 6, 1, 17, "VMLALuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #560 = VMLALuv4i32
- { 561, 6, 1, 17, "VMLALuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #561 = VMLALuv8i16
- { 562, 6, 1, 76, "VMLAS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo85 }, // Inst #562 = VMLAS
- { 563, 6, 1, 15, "VMLAfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #563 = VMLAfd
- { 564, 6, 1, 16, "VMLAfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #564 = VMLAfq
- { 565, 7, 1, 15, "VMLAslfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo86 }, // Inst #565 = VMLAslfd
- { 566, 7, 1, 16, "VMLAslfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 }, // Inst #566 = VMLAslfq
- { 567, 7, 1, 19, "VMLAslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo86 }, // Inst #567 = VMLAslv2i32
- { 568, 7, 1, 17, "VMLAslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo88 }, // Inst #568 = VMLAslv4i16
- { 569, 7, 1, 20, "VMLAslv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 }, // Inst #569 = VMLAslv4i32
- { 570, 7, 1, 18, "VMLAslv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo89 }, // Inst #570 = VMLAslv8i16
- { 571, 6, 1, 18, "VMLAv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #571 = VMLAv16i8
- { 572, 6, 1, 19, "VMLAv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #572 = VMLAv2i32
- { 573, 6, 1, 17, "VMLAv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #573 = VMLAv4i16
- { 574, 6, 1, 20, "VMLAv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #574 = VMLAv4i32
- { 575, 6, 1, 18, "VMLAv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #575 = VMLAv8i16
- { 576, 6, 1, 17, "VMLAv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #576 = VMLAv8i8
- { 577, 6, 1, 77, "VMLSD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #577 = VMLSD
- { 578, 7, 1, 19, "VMLSLslsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo83 }, // Inst #578 = VMLSLslsv2i32
- { 579, 7, 1, 17, "VMLSLslsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo84 }, // Inst #579 = VMLSLslsv4i16
- { 580, 7, 1, 19, "VMLSLsluv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo83 }, // Inst #580 = VMLSLsluv2i32
- { 581, 7, 1, 17, "VMLSLsluv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo84 }, // Inst #581 = VMLSLsluv4i16
- { 582, 6, 1, 17, "VMLSLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #582 = VMLSLsv2i64
- { 583, 6, 1, 17, "VMLSLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #583 = VMLSLsv4i32
- { 584, 6, 1, 17, "VMLSLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #584 = VMLSLsv8i16
- { 585, 6, 1, 17, "VMLSLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #585 = VMLSLuv2i64
- { 586, 6, 1, 17, "VMLSLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #586 = VMLSLuv4i32
- { 587, 6, 1, 17, "VMLSLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #587 = VMLSLuv8i16
- { 588, 6, 1, 76, "VMLSS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo85 }, // Inst #588 = VMLSS
- { 589, 6, 1, 15, "VMLSfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #589 = VMLSfd
- { 590, 6, 1, 16, "VMLSfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #590 = VMLSfq
- { 591, 7, 1, 15, "VMLSslfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo86 }, // Inst #591 = VMLSslfd
- { 592, 7, 1, 16, "VMLSslfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 }, // Inst #592 = VMLSslfq
- { 593, 7, 1, 19, "VMLSslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo86 }, // Inst #593 = VMLSslv2i32
- { 594, 7, 1, 17, "VMLSslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo88 }, // Inst #594 = VMLSslv4i16
- { 595, 7, 1, 20, "VMLSslv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 }, // Inst #595 = VMLSslv4i32
- { 596, 7, 1, 18, "VMLSslv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo89 }, // Inst #596 = VMLSslv8i16
- { 597, 6, 1, 18, "VMLSv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #597 = VMLSv16i8
- { 598, 6, 1, 19, "VMLSv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #598 = VMLSv2i32
- { 599, 6, 1, 17, "VMLSv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #599 = VMLSv4i16
- { 600, 6, 1, 20, "VMLSv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #600 = VMLSv4i32
- { 601, 6, 1, 18, "VMLSv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #601 = VMLSv8i16
- { 602, 6, 1, 17, "VMLSv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #602 = VMLSv8i8
- { 603, 4, 1, 87, "VMOVD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #603 = VMOVD
- { 604, 5, 1, 23, "VMOVDRR", 0|(1<<TID::Predicable), 0|(3<<4)|(19<<9)|(1<<17), NULL, NULL, NULL, OperandInfo90 }, // Inst #604 = VMOVDRR
- { 605, 5, 1, 87, "VMOVDcc", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #605 = VMOVDcc
- { 606, 4, 1, 21, "VMOVDneon", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #606 = VMOVDneon
- { 607, 4, 1, 38, "VMOVLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo92 }, // Inst #607 = VMOVLsv2i64
- { 608, 4, 1, 38, "VMOVLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo92 }, // Inst #608 = VMOVLsv4i32
- { 609, 4, 1, 38, "VMOVLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo92 }, // Inst #609 = VMOVLsv8i16
- { 610, 4, 1, 38, "VMOVLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo92 }, // Inst #610 = VMOVLuv2i64
- { 611, 4, 1, 38, "VMOVLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo92 }, // Inst #611 = VMOVLuv4i32
- { 612, 4, 1, 38, "VMOVLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo92 }, // Inst #612 = VMOVLuv8i16
- { 613, 4, 1, 21, "VMOVNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #613 = VMOVNv2i32
- { 614, 4, 1, 21, "VMOVNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #614 = VMOVNv4i16
- { 615, 4, 1, 21, "VMOVNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #615 = VMOVNv8i8
- { 616, 4, 1, 21, "VMOVQ", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #616 = VMOVQ
- { 617, 5, 2, 22, "VMOVRRD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(17<<9)|(1<<17), NULL, NULL, NULL, OperandInfo94 }, // Inst #617 = VMOVRRD
- { 618, 4, 1, 28, "VMOVRS", 0|(1<<TID::Predicable), 0|(3<<4)|(16<<9)|(1<<17), NULL, NULL, NULL, OperandInfo95 }, // Inst #618 = VMOVRS
- { 619, 4, 1, 86, "VMOVS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #619 = VMOVS
- { 620, 4, 1, 24, "VMOVSR", 0|(1<<TID::Predicable), 0|(3<<4)|(18<<9)|(1<<17), NULL, NULL, NULL, OperandInfo96 }, // Inst #620 = VMOVSR
- { 621, 5, 1, 86, "VMOVScc", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo97 }, // Inst #621 = VMOVScc
- { 622, 4, 1, 26, "VMOVv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo98 }, // Inst #622 = VMOVv16i8
- { 623, 4, 1, 26, "VMOVv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo25 }, // Inst #623 = VMOVv1i64
- { 624, 4, 1, 26, "VMOVv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo25 }, // Inst #624 = VMOVv2i32
- { 625, 4, 1, 26, "VMOVv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo98 }, // Inst #625 = VMOVv2i64
- { 626, 4, 1, 26, "VMOVv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo25 }, // Inst #626 = VMOVv4i16
- { 627, 4, 1, 26, "VMOVv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo98 }, // Inst #627 = VMOVv4i32
- { 628, 4, 1, 26, "VMOVv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo98 }, // Inst #628 = VMOVv8i16
- { 629, 4, 1, 26, "VMOVv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo25 }, // Inst #629 = VMOVv8i8
- { 630, 5, 1, 79, "VMULD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #630 = VMULD
- { 631, 5, 1, 29, "VMULLp", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #631 = VMULLp
- { 632, 6, 1, 29, "VMULLslsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo99 }, // Inst #632 = VMULLslsv2i32
- { 633, 6, 1, 29, "VMULLslsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo100 }, // Inst #633 = VMULLslsv4i16
- { 634, 6, 1, 29, "VMULLsluv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo99 }, // Inst #634 = VMULLsluv2i32
- { 635, 6, 1, 29, "VMULLsluv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo100 }, // Inst #635 = VMULLsluv4i16
- { 636, 5, 1, 29, "VMULLsv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #636 = VMULLsv2i64
- { 637, 5, 1, 29, "VMULLsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #637 = VMULLsv4i32
- { 638, 5, 1, 29, "VMULLsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #638 = VMULLsv8i16
- { 639, 5, 1, 29, "VMULLuv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #639 = VMULLuv2i64
- { 640, 5, 1, 29, "VMULLuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #640 = VMULLuv4i32
- { 641, 5, 1, 29, "VMULLuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #641 = VMULLuv8i16
- { 642, 5, 1, 78, "VMULS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #642 = VMULS
- { 643, 5, 1, 1, "VMULfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #643 = VMULfd
- { 644, 5, 1, 1, "VMULfd_sfp", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #644 = VMULfd_sfp
- { 645, 5, 1, 2, "VMULfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #645 = VMULfq
- { 646, 5, 1, 29, "VMULpd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #646 = VMULpd
- { 647, 5, 1, 30, "VMULpq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #647 = VMULpq
- { 648, 6, 1, 1, "VMULslfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo101 }, // Inst #648 = VMULslfd
- { 649, 6, 1, 2, "VMULslfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo102 }, // Inst #649 = VMULslfq
- { 650, 6, 1, 31, "VMULslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo101 }, // Inst #650 = VMULslv2i32
- { 651, 6, 1, 29, "VMULslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo103 }, // Inst #651 = VMULslv4i16
- { 652, 6, 1, 32, "VMULslv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo102 }, // Inst #652 = VMULslv4i32
- { 653, 6, 1, 30, "VMULslv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #653 = VMULslv8i16
- { 654, 5, 1, 30, "VMULv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #654 = VMULv16i8
- { 655, 5, 1, 31, "VMULv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #655 = VMULv2i32
- { 656, 5, 1, 29, "VMULv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #656 = VMULv4i16
- { 657, 5, 1, 32, "VMULv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #657 = VMULv4i32
- { 658, 5, 1, 30, "VMULv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #658 = VMULv8i16
- { 659, 5, 1, 29, "VMULv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #659 = VMULv8i8
- { 660, 4, 1, 44, "VMVNd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #660 = VMVNd
- { 661, 4, 1, 44, "VMVNq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #661 = VMVNq
- { 662, 4, 1, 87, "VNEGD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #662 = VNEGD
- { 663, 5, 1, 87, "VNEGDcc", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #663 = VNEGDcc
- { 664, 4, 1, 86, "VNEGS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #664 = VNEGS
- { 665, 5, 1, 86, "VNEGScc", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo97 }, // Inst #665 = VNEGScc
- { 666, 4, 1, 57, "VNEGf32d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #666 = VNEGf32d
- { 667, 4, 1, 57, "VNEGf32d_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #667 = VNEGf32d_sfp
- { 668, 4, 1, 58, "VNEGf32q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #668 = VNEGf32q
- { 669, 4, 1, 44, "VNEGs16d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #669 = VNEGs16d
- { 670, 4, 1, 44, "VNEGs16q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #670 = VNEGs16q
- { 671, 4, 1, 44, "VNEGs32d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #671 = VNEGs32d
- { 672, 4, 1, 44, "VNEGs32q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #672 = VNEGs32q
- { 673, 4, 1, 44, "VNEGs8d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #673 = VNEGs8d
- { 674, 4, 1, 44, "VNEGs8q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #674 = VNEGs8q
- { 675, 6, 1, 77, "VNMLAD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #675 = VNMLAD
- { 676, 6, 1, 76, "VNMLAS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo85 }, // Inst #676 = VNMLAS
- { 677, 6, 1, 77, "VNMLSD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #677 = VNMLSD
- { 678, 6, 1, 76, "VNMLSS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo85 }, // Inst #678 = VNMLSS
- { 679, 5, 1, 79, "VNMULD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #679 = VNMULD
- { 680, 5, 1, 78, "VNMULS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #680 = VNMULS
- { 681, 5, 1, 5, "VORNd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #681 = VORNd
- { 682, 5, 1, 6, "VORNq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #682 = VORNq
- { 683, 5, 1, 5, "VORRd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #683 = VORRd
- { 684, 5, 1, 6, "VORRq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #684 = VORRq
- { 685, 5, 1, 34, "VPADALsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #685 = VPADALsv16i8
- { 686, 5, 1, 33, "VPADALsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #686 = VPADALsv2i32
- { 687, 5, 1, 33, "VPADALsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #687 = VPADALsv4i16
- { 688, 5, 1, 34, "VPADALsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #688 = VPADALsv4i32
- { 689, 5, 1, 34, "VPADALsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #689 = VPADALsv8i16
- { 690, 5, 1, 33, "VPADALsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #690 = VPADALsv8i8
- { 691, 5, 1, 34, "VPADALuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #691 = VPADALuv16i8
- { 692, 5, 1, 33, "VPADALuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #692 = VPADALuv2i32
- { 693, 5, 1, 33, "VPADALuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #693 = VPADALuv4i16
- { 694, 5, 1, 34, "VPADALuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #694 = VPADALuv4i32
- { 695, 5, 1, 34, "VPADALuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #695 = VPADALuv8i16
- { 696, 5, 1, 33, "VPADALuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #696 = VPADALuv8i8
- { 697, 4, 1, 44, "VPADDLsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #697 = VPADDLsv16i8
- { 698, 4, 1, 44, "VPADDLsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #698 = VPADDLsv2i32
- { 699, 4, 1, 44, "VPADDLsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #699 = VPADDLsv4i16
- { 700, 4, 1, 44, "VPADDLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #700 = VPADDLsv4i32
- { 701, 4, 1, 44, "VPADDLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #701 = VPADDLsv8i16
- { 702, 4, 1, 44, "VPADDLsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #702 = VPADDLsv8i8
- { 703, 4, 1, 44, "VPADDLuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #703 = VPADDLuv16i8
- { 704, 4, 1, 44, "VPADDLuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #704 = VPADDLuv2i32
- { 705, 4, 1, 44, "VPADDLuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #705 = VPADDLuv4i16
- { 706, 4, 1, 44, "VPADDLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #706 = VPADDLuv4i32
- { 707, 4, 1, 44, "VPADDLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #707 = VPADDLuv8i16
- { 708, 4, 1, 44, "VPADDLuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #708 = VPADDLuv8i8
- { 709, 5, 1, 1, "VPADDf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #709 = VPADDf
- { 710, 5, 1, 5, "VPADDi16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #710 = VPADDi16
- { 711, 5, 1, 5, "VPADDi32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #711 = VPADDi32
- { 712, 5, 1, 5, "VPADDi8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #712 = VPADDi8
- { 713, 5, 1, 3, "VPMAXf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #713 = VPMAXf
- { 714, 5, 1, 3, "VPMAXs16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #714 = VPMAXs16
- { 715, 5, 1, 3, "VPMAXs32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #715 = VPMAXs32
- { 716, 5, 1, 3, "VPMAXs8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #716 = VPMAXs8
- { 717, 5, 1, 3, "VPMAXu16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #717 = VPMAXu16
- { 718, 5, 1, 3, "VPMAXu32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #718 = VPMAXu32
- { 719, 5, 1, 3, "VPMAXu8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #719 = VPMAXu8
- { 720, 5, 1, 3, "VPMINf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #720 = VPMINf
- { 721, 5, 1, 3, "VPMINs16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #721 = VPMINs16
- { 722, 5, 1, 3, "VPMINs32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #722 = VPMINs32
- { 723, 5, 1, 3, "VPMINs8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #723 = VPMINs8
- { 724, 5, 1, 3, "VPMINu16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #724 = VPMINu16
- { 725, 5, 1, 3, "VPMINu32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #725 = VPMINu32
- { 726, 5, 1, 3, "VPMINu8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #726 = VPMINu8
- { 727, 4, 1, 39, "VQABSv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #727 = VQABSv16i8
- { 728, 4, 1, 38, "VQABSv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #728 = VQABSv2i32
- { 729, 4, 1, 38, "VQABSv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #729 = VQABSv4i16
- { 730, 4, 1, 39, "VQABSv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #730 = VQABSv4i32
- { 731, 4, 1, 39, "VQABSv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #731 = VQABSv8i16
- { 732, 4, 1, 38, "VQABSv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #732 = VQABSv8i8
- { 733, 5, 1, 4, "VQADDsv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #733 = VQADDsv16i8
- { 734, 5, 1, 3, "VQADDsv1i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #734 = VQADDsv1i64
- { 735, 5, 1, 3, "VQADDsv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #735 = VQADDsv2i32
- { 736, 5, 1, 4, "VQADDsv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #736 = VQADDsv2i64
- { 737, 5, 1, 3, "VQADDsv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #737 = VQADDsv4i16
- { 738, 5, 1, 4, "VQADDsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #738 = VQADDsv4i32
- { 739, 5, 1, 4, "VQADDsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #739 = VQADDsv8i16
- { 740, 5, 1, 3, "VQADDsv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #740 = VQADDsv8i8
- { 741, 5, 1, 4, "VQADDuv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #741 = VQADDuv16i8
- { 742, 5, 1, 3, "VQADDuv1i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #742 = VQADDuv1i64
- { 743, 5, 1, 3, "VQADDuv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #743 = VQADDuv2i32
- { 744, 5, 1, 4, "VQADDuv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #744 = VQADDuv2i64
- { 745, 5, 1, 3, "VQADDuv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #745 = VQADDuv4i16
- { 746, 5, 1, 4, "VQADDuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #746 = VQADDuv4i32
- { 747, 5, 1, 4, "VQADDuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #747 = VQADDuv8i16
- { 748, 5, 1, 3, "VQADDuv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #748 = VQADDuv8i8
- { 749, 7, 1, 19, "VQDMLALslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo83 }, // Inst #749 = VQDMLALslv2i32
- { 750, 7, 1, 17, "VQDMLALslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo84 }, // Inst #750 = VQDMLALslv4i16
- { 751, 6, 1, 17, "VQDMLALv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #751 = VQDMLALv2i64
- { 752, 6, 1, 17, "VQDMLALv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #752 = VQDMLALv4i32
- { 753, 7, 1, 19, "VQDMLSLslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo83 }, // Inst #753 = VQDMLSLslv2i32
- { 754, 7, 1, 17, "VQDMLSLslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo84 }, // Inst #754 = VQDMLSLslv4i16
- { 755, 6, 1, 17, "VQDMLSLv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #755 = VQDMLSLv2i64
- { 756, 6, 1, 17, "VQDMLSLv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #756 = VQDMLSLv4i32
- { 757, 6, 1, 31, "VQDMULHslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo101 }, // Inst #757 = VQDMULHslv2i32
- { 758, 6, 1, 29, "VQDMULHslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo103 }, // Inst #758 = VQDMULHslv4i16
- { 759, 6, 1, 32, "VQDMULHslv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo102 }, // Inst #759 = VQDMULHslv4i32
- { 760, 6, 1, 30, "VQDMULHslv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #760 = VQDMULHslv8i16
- { 761, 5, 1, 31, "VQDMULHv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #761 = VQDMULHv2i32
- { 762, 5, 1, 29, "VQDMULHv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #762 = VQDMULHv4i16
- { 763, 5, 1, 32, "VQDMULHv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #763 = VQDMULHv4i32
- { 764, 5, 1, 30, "VQDMULHv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #764 = VQDMULHv8i16
- { 765, 6, 1, 29, "VQDMULLslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo99 }, // Inst #765 = VQDMULLslv2i32
- { 766, 6, 1, 29, "VQDMULLslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo100 }, // Inst #766 = VQDMULLslv4i16
- { 767, 5, 1, 29, "VQDMULLv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #767 = VQDMULLv2i64
- { 768, 5, 1, 29, "VQDMULLv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #768 = VQDMULLv4i32
- { 769, 4, 1, 38, "VQMOVNsuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #769 = VQMOVNsuv2i32
- { 770, 4, 1, 38, "VQMOVNsuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #770 = VQMOVNsuv4i16
- { 771, 4, 1, 38, "VQMOVNsuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #771 = VQMOVNsuv8i8
- { 772, 4, 1, 38, "VQMOVNsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #772 = VQMOVNsv2i32
- { 773, 4, 1, 38, "VQMOVNsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #773 = VQMOVNsv4i16
- { 774, 4, 1, 38, "VQMOVNsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #774 = VQMOVNsv8i8
- { 775, 4, 1, 38, "VQMOVNuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #775 = VQMOVNuv2i32
- { 776, 4, 1, 38, "VQMOVNuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #776 = VQMOVNuv4i16
- { 777, 4, 1, 38, "VQMOVNuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #777 = VQMOVNuv8i8
- { 778, 4, 1, 39, "VQNEGv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #778 = VQNEGv16i8
- { 779, 4, 1, 38, "VQNEGv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #779 = VQNEGv2i32
- { 780, 4, 1, 38, "VQNEGv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #780 = VQNEGv4i16
- { 781, 4, 1, 39, "VQNEGv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #781 = VQNEGv4i32
- { 782, 4, 1, 39, "VQNEGv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #782 = VQNEGv8i16
- { 783, 4, 1, 38, "VQNEGv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #783 = VQNEGv8i8
- { 784, 6, 1, 31, "VQRDMULHslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo101 }, // Inst #784 = VQRDMULHslv2i32
- { 785, 6, 1, 29, "VQRDMULHslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo103 }, // Inst #785 = VQRDMULHslv4i16
- { 786, 6, 1, 32, "VQRDMULHslv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo102 }, // Inst #786 = VQRDMULHslv4i32
- { 787, 6, 1, 30, "VQRDMULHslv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #787 = VQRDMULHslv8i16
- { 788, 5, 1, 31, "VQRDMULHv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #788 = VQRDMULHv2i32
- { 789, 5, 1, 29, "VQRDMULHv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #789 = VQRDMULHv4i16
- { 790, 5, 1, 32, "VQRDMULHv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #790 = VQRDMULHv4i32
- { 791, 5, 1, 30, "VQRDMULHv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #791 = VQRDMULHv8i16
- { 792, 5, 1, 43, "VQRSHLsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #792 = VQRSHLsv16i8
- { 793, 5, 1, 42, "VQRSHLsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #793 = VQRSHLsv1i64
- { 794, 5, 1, 42, "VQRSHLsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #794 = VQRSHLsv2i32
- { 795, 5, 1, 43, "VQRSHLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #795 = VQRSHLsv2i64
- { 796, 5, 1, 42, "VQRSHLsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #796 = VQRSHLsv4i16
- { 797, 5, 1, 43, "VQRSHLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #797 = VQRSHLsv4i32
- { 798, 5, 1, 43, "VQRSHLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #798 = VQRSHLsv8i16
- { 799, 5, 1, 42, "VQRSHLsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #799 = VQRSHLsv8i8
- { 800, 5, 1, 43, "VQRSHLuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #800 = VQRSHLuv16i8
- { 801, 5, 1, 42, "VQRSHLuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #801 = VQRSHLuv1i64
- { 802, 5, 1, 42, "VQRSHLuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #802 = VQRSHLuv2i32
- { 803, 5, 1, 43, "VQRSHLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #803 = VQRSHLuv2i64
- { 804, 5, 1, 42, "VQRSHLuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #804 = VQRSHLuv4i16
- { 805, 5, 1, 43, "VQRSHLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #805 = VQRSHLuv4i32
- { 806, 5, 1, 43, "VQRSHLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #806 = VQRSHLuv8i16
- { 807, 5, 1, 42, "VQRSHLuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #807 = VQRSHLuv8i8
- { 808, 5, 1, 42, "VQRSHRNsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #808 = VQRSHRNsv2i32
- { 809, 5, 1, 42, "VQRSHRNsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #809 = VQRSHRNsv4i16
- { 810, 5, 1, 42, "VQRSHRNsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #810 = VQRSHRNsv8i8
- { 811, 5, 1, 42, "VQRSHRNuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #811 = VQRSHRNuv2i32
- { 812, 5, 1, 42, "VQRSHRNuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #812 = VQRSHRNuv4i16
- { 813, 5, 1, 42, "VQRSHRNuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #813 = VQRSHRNuv8i8
- { 814, 5, 1, 42, "VQRSHRUNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #814 = VQRSHRUNv2i32
- { 815, 5, 1, 42, "VQRSHRUNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #815 = VQRSHRUNv4i16
- { 816, 5, 1, 42, "VQRSHRUNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #816 = VQRSHRUNv8i8
- { 817, 5, 1, 42, "VQSHLsiv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #817 = VQSHLsiv16i8
- { 818, 5, 1, 42, "VQSHLsiv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #818 = VQSHLsiv1i64
- { 819, 5, 1, 42, "VQSHLsiv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #819 = VQSHLsiv2i32
- { 820, 5, 1, 42, "VQSHLsiv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #820 = VQSHLsiv2i64
- { 821, 5, 1, 42, "VQSHLsiv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #821 = VQSHLsiv4i16
- { 822, 5, 1, 42, "VQSHLsiv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #822 = VQSHLsiv4i32
- { 823, 5, 1, 42, "VQSHLsiv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #823 = VQSHLsiv8i16
- { 824, 5, 1, 42, "VQSHLsiv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #824 = VQSHLsiv8i8
- { 825, 5, 1, 42, "VQSHLsuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #825 = VQSHLsuv16i8
- { 826, 5, 1, 42, "VQSHLsuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #826 = VQSHLsuv1i64
- { 827, 5, 1, 42, "VQSHLsuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #827 = VQSHLsuv2i32
- { 828, 5, 1, 42, "VQSHLsuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #828 = VQSHLsuv2i64
- { 829, 5, 1, 42, "VQSHLsuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #829 = VQSHLsuv4i16
- { 830, 5, 1, 42, "VQSHLsuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #830 = VQSHLsuv4i32
- { 831, 5, 1, 42, "VQSHLsuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #831 = VQSHLsuv8i16
- { 832, 5, 1, 42, "VQSHLsuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #832 = VQSHLsuv8i8
- { 833, 5, 1, 43, "VQSHLsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #833 = VQSHLsv16i8
- { 834, 5, 1, 42, "VQSHLsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #834 = VQSHLsv1i64
- { 835, 5, 1, 42, "VQSHLsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #835 = VQSHLsv2i32
- { 836, 5, 1, 43, "VQSHLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #836 = VQSHLsv2i64
- { 837, 5, 1, 42, "VQSHLsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #837 = VQSHLsv4i16
- { 838, 5, 1, 43, "VQSHLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #838 = VQSHLsv4i32
- { 839, 5, 1, 43, "VQSHLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #839 = VQSHLsv8i16
- { 840, 5, 1, 42, "VQSHLsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #840 = VQSHLsv8i8
- { 841, 5, 1, 42, "VQSHLuiv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #841 = VQSHLuiv16i8
- { 842, 5, 1, 42, "VQSHLuiv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #842 = VQSHLuiv1i64
- { 843, 5, 1, 42, "VQSHLuiv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #843 = VQSHLuiv2i32
- { 844, 5, 1, 42, "VQSHLuiv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #844 = VQSHLuiv2i64
- { 845, 5, 1, 42, "VQSHLuiv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #845 = VQSHLuiv4i16
- { 846, 5, 1, 42, "VQSHLuiv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #846 = VQSHLuiv4i32
- { 847, 5, 1, 42, "VQSHLuiv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #847 = VQSHLuiv8i16
- { 848, 5, 1, 42, "VQSHLuiv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #848 = VQSHLuiv8i8
- { 849, 5, 1, 43, "VQSHLuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #849 = VQSHLuv16i8
- { 850, 5, 1, 42, "VQSHLuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #850 = VQSHLuv1i64
- { 851, 5, 1, 42, "VQSHLuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #851 = VQSHLuv2i32
- { 852, 5, 1, 43, "VQSHLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #852 = VQSHLuv2i64
- { 853, 5, 1, 42, "VQSHLuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #853 = VQSHLuv4i16
- { 854, 5, 1, 43, "VQSHLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #854 = VQSHLuv4i32
- { 855, 5, 1, 43, "VQSHLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #855 = VQSHLuv8i16
- { 856, 5, 1, 42, "VQSHLuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #856 = VQSHLuv8i8
- { 857, 5, 1, 42, "VQSHRNsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #857 = VQSHRNsv2i32
- { 858, 5, 1, 42, "VQSHRNsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #858 = VQSHRNsv4i16
- { 859, 5, 1, 42, "VQSHRNsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #859 = VQSHRNsv8i8
- { 860, 5, 1, 42, "VQSHRNuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #860 = VQSHRNuv2i32
- { 861, 5, 1, 42, "VQSHRNuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #861 = VQSHRNuv4i16
- { 862, 5, 1, 42, "VQSHRNuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #862 = VQSHRNuv8i8
- { 863, 5, 1, 42, "VQSHRUNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #863 = VQSHRUNv2i32
- { 864, 5, 1, 42, "VQSHRUNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #864 = VQSHRUNv4i16
- { 865, 5, 1, 42, "VQSHRUNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #865 = VQSHRUNv8i8
- { 866, 5, 1, 4, "VQSUBsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #866 = VQSUBsv16i8
- { 867, 5, 1, 3, "VQSUBsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #867 = VQSUBsv1i64
- { 868, 5, 1, 3, "VQSUBsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #868 = VQSUBsv2i32
- { 869, 5, 1, 4, "VQSUBsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #869 = VQSUBsv2i64
- { 870, 5, 1, 3, "VQSUBsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #870 = VQSUBsv4i16
- { 871, 5, 1, 4, "VQSUBsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #871 = VQSUBsv4i32
- { 872, 5, 1, 4, "VQSUBsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #872 = VQSUBsv8i16
- { 873, 5, 1, 3, "VQSUBsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #873 = VQSUBsv8i8
- { 874, 5, 1, 4, "VQSUBuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #874 = VQSUBuv16i8
- { 875, 5, 1, 3, "VQSUBuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #875 = VQSUBuv1i64
- { 876, 5, 1, 3, "VQSUBuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #876 = VQSUBuv2i32
- { 877, 5, 1, 4, "VQSUBuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #877 = VQSUBuv2i64
- { 878, 5, 1, 3, "VQSUBuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #878 = VQSUBuv4i16
- { 879, 5, 1, 4, "VQSUBuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #879 = VQSUBuv4i32
- { 880, 5, 1, 4, "VQSUBuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #880 = VQSUBuv8i16
- { 881, 5, 1, 3, "VQSUBuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #881 = VQSUBuv8i8
- { 882, 5, 1, 3, "VRADDHNv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #882 = VRADDHNv2i32
- { 883, 5, 1, 3, "VRADDHNv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #883 = VRADDHNv4i16
- { 884, 5, 1, 3, "VRADDHNv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #884 = VRADDHNv8i8
- { 885, 4, 1, 57, "VRECPEd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #885 = VRECPEd
- { 886, 4, 1, 57, "VRECPEfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #886 = VRECPEfd
- { 887, 4, 1, 58, "VRECPEfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #887 = VRECPEfq
- { 888, 4, 1, 58, "VRECPEq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #888 = VRECPEq
- { 889, 5, 1, 40, "VRECPSfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #889 = VRECPSfd
- { 890, 5, 1, 41, "VRECPSfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #890 = VRECPSfq
- { 891, 4, 1, 21, "VREV16d8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #891 = VREV16d8
- { 892, 4, 1, 21, "VREV16q8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #892 = VREV16q8
- { 893, 4, 1, 21, "VREV32d16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #893 = VREV32d16
- { 894, 4, 1, 21, "VREV32d8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #894 = VREV32d8
- { 895, 4, 1, 21, "VREV32q16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #895 = VREV32q16
- { 896, 4, 1, 21, "VREV32q8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #896 = VREV32q8
- { 897, 4, 1, 21, "VREV64d16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #897 = VREV64d16
- { 898, 4, 1, 21, "VREV64d32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #898 = VREV64d32
- { 899, 4, 1, 21, "VREV64d8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #899 = VREV64d8
- { 900, 4, 1, 21, "VREV64df", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #900 = VREV64df
- { 901, 4, 1, 21, "VREV64q16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #901 = VREV64q16
- { 902, 4, 1, 21, "VREV64q32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #902 = VREV64q32
- { 903, 4, 1, 21, "VREV64q8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #903 = VREV64q8
- { 904, 4, 1, 21, "VREV64qf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #904 = VREV64qf
- { 905, 5, 1, 4, "VRHADDsv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #905 = VRHADDsv16i8
- { 906, 5, 1, 3, "VRHADDsv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #906 = VRHADDsv2i32
- { 907, 5, 1, 3, "VRHADDsv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #907 = VRHADDsv4i16
- { 908, 5, 1, 4, "VRHADDsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #908 = VRHADDsv4i32
- { 909, 5, 1, 4, "VRHADDsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #909 = VRHADDsv8i16
- { 910, 5, 1, 3, "VRHADDsv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #910 = VRHADDsv8i8
- { 911, 5, 1, 4, "VRHADDuv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #911 = VRHADDuv16i8
- { 912, 5, 1, 3, "VRHADDuv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #912 = VRHADDuv2i32
- { 913, 5, 1, 3, "VRHADDuv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #913 = VRHADDuv4i16
- { 914, 5, 1, 4, "VRHADDuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #914 = VRHADDuv4i32
- { 915, 5, 1, 4, "VRHADDuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #915 = VRHADDuv8i16
- { 916, 5, 1, 3, "VRHADDuv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #916 = VRHADDuv8i8
- { 917, 5, 1, 43, "VRSHLsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #917 = VRSHLsv16i8
- { 918, 5, 1, 42, "VRSHLsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #918 = VRSHLsv1i64
- { 919, 5, 1, 42, "VRSHLsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #919 = VRSHLsv2i32
- { 920, 5, 1, 43, "VRSHLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #920 = VRSHLsv2i64
- { 921, 5, 1, 42, "VRSHLsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #921 = VRSHLsv4i16
- { 922, 5, 1, 43, "VRSHLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #922 = VRSHLsv4i32
- { 923, 5, 1, 43, "VRSHLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #923 = VRSHLsv8i16
- { 924, 5, 1, 42, "VRSHLsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #924 = VRSHLsv8i8
- { 925, 5, 1, 43, "VRSHLuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #925 = VRSHLuv16i8
- { 926, 5, 1, 42, "VRSHLuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #926 = VRSHLuv1i64
- { 927, 5, 1, 42, "VRSHLuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #927 = VRSHLuv2i32
- { 928, 5, 1, 43, "VRSHLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #928 = VRSHLuv2i64
- { 929, 5, 1, 42, "VRSHLuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #929 = VRSHLuv4i16
- { 930, 5, 1, 43, "VRSHLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #930 = VRSHLuv4i32
- { 931, 5, 1, 43, "VRSHLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #931 = VRSHLuv8i16
- { 932, 5, 1, 42, "VRSHLuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #932 = VRSHLuv8i8
- { 933, 5, 1, 42, "VRSHRNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #933 = VRSHRNv2i32
- { 934, 5, 1, 42, "VRSHRNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #934 = VRSHRNv4i16
- { 935, 5, 1, 42, "VRSHRNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #935 = VRSHRNv8i8
- { 936, 5, 1, 42, "VRSHRsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #936 = VRSHRsv16i8
- { 937, 5, 1, 42, "VRSHRsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #937 = VRSHRsv1i64
- { 938, 5, 1, 42, "VRSHRsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #938 = VRSHRsv2i32
- { 939, 5, 1, 42, "VRSHRsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #939 = VRSHRsv2i64
- { 940, 5, 1, 42, "VRSHRsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #940 = VRSHRsv4i16
- { 941, 5, 1, 42, "VRSHRsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #941 = VRSHRsv4i32
- { 942, 5, 1, 42, "VRSHRsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #942 = VRSHRsv8i16
- { 943, 5, 1, 42, "VRSHRsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #943 = VRSHRsv8i8
- { 944, 5, 1, 42, "VRSHRuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #944 = VRSHRuv16i8
- { 945, 5, 1, 42, "VRSHRuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #945 = VRSHRuv1i64
- { 946, 5, 1, 42, "VRSHRuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #946 = VRSHRuv2i32
- { 947, 5, 1, 42, "VRSHRuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #947 = VRSHRuv2i64
- { 948, 5, 1, 42, "VRSHRuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #948 = VRSHRuv4i16
- { 949, 5, 1, 42, "VRSHRuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #949 = VRSHRuv4i32
- { 950, 5, 1, 42, "VRSHRuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #950 = VRSHRuv8i16
- { 951, 5, 1, 42, "VRSHRuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #951 = VRSHRuv8i8
- { 952, 4, 1, 57, "VRSQRTEd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #952 = VRSQRTEd
- { 953, 4, 1, 57, "VRSQRTEfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #953 = VRSQRTEfd
- { 954, 4, 1, 58, "VRSQRTEfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #954 = VRSQRTEfq
- { 955, 4, 1, 58, "VRSQRTEq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #955 = VRSQRTEq
- { 956, 5, 1, 40, "VRSQRTSfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #956 = VRSQRTSfd
- { 957, 5, 1, 41, "VRSQRTSfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #957 = VRSQRTSfq
- { 958, 6, 1, 33, "VRSRAsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #958 = VRSRAsv16i8
- { 959, 6, 1, 33, "VRSRAsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #959 = VRSRAsv1i64
- { 960, 6, 1, 33, "VRSRAsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #960 = VRSRAsv2i32
- { 961, 6, 1, 33, "VRSRAsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #961 = VRSRAsv2i64
- { 962, 6, 1, 33, "VRSRAsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #962 = VRSRAsv4i16
- { 963, 6, 1, 33, "VRSRAsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #963 = VRSRAsv4i32
- { 964, 6, 1, 33, "VRSRAsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #964 = VRSRAsv8i16
- { 965, 6, 1, 33, "VRSRAsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #965 = VRSRAsv8i8
- { 966, 6, 1, 33, "VRSRAuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #966 = VRSRAuv16i8
- { 967, 6, 1, 33, "VRSRAuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #967 = VRSRAuv1i64
- { 968, 6, 1, 33, "VRSRAuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #968 = VRSRAuv2i32
- { 969, 6, 1, 33, "VRSRAuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #969 = VRSRAuv2i64
- { 970, 6, 1, 33, "VRSRAuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #970 = VRSRAuv4i16
- { 971, 6, 1, 33, "VRSRAuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #971 = VRSRAuv4i32
- { 972, 6, 1, 33, "VRSRAuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #972 = VRSRAuv8i16
- { 973, 6, 1, 33, "VRSRAuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #973 = VRSRAuv8i8
- { 974, 5, 1, 3, "VRSUBHNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #974 = VRSUBHNv2i32
- { 975, 5, 1, 3, "VRSUBHNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #975 = VRSUBHNv4i16
- { 976, 5, 1, 3, "VRSUBHNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #976 = VRSUBHNv8i8
- { 977, 6, 1, 25, "VSETLNi16", 0|(1<<TID::Predicable), 0|(3<<4)|(26<<9), NULL, NULL, NULL, OperandInfo109 }, // Inst #977 = VSETLNi16
- { 978, 6, 1, 25, "VSETLNi32", 0|(1<<TID::Predicable), 0|(3<<4)|(26<<9), NULL, NULL, NULL, OperandInfo109 }, // Inst #978 = VSETLNi32
- { 979, 6, 1, 25, "VSETLNi8", 0|(1<<TID::Predicable), 0|(3<<4)|(26<<9), NULL, NULL, NULL, OperandInfo109 }, // Inst #979 = VSETLNi8
- { 980, 5, 1, 44, "VSHLLi16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #980 = VSHLLi16
- { 981, 5, 1, 44, "VSHLLi32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #981 = VSHLLi32
- { 982, 5, 1, 44, "VSHLLi8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #982 = VSHLLi8
- { 983, 5, 1, 44, "VSHLLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #983 = VSHLLsv2i64
- { 984, 5, 1, 44, "VSHLLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #984 = VSHLLsv4i32
- { 985, 5, 1, 44, "VSHLLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #985 = VSHLLsv8i16
- { 986, 5, 1, 44, "VSHLLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #986 = VSHLLuv2i64
- { 987, 5, 1, 44, "VSHLLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #987 = VSHLLuv4i32
- { 988, 5, 1, 44, "VSHLLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #988 = VSHLLuv8i16
- { 989, 5, 1, 44, "VSHLiv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #989 = VSHLiv16i8
- { 990, 5, 1, 44, "VSHLiv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #990 = VSHLiv1i64
- { 991, 5, 1, 44, "VSHLiv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #991 = VSHLiv2i32
- { 992, 5, 1, 44, "VSHLiv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #992 = VSHLiv2i64
- { 993, 5, 1, 44, "VSHLiv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #993 = VSHLiv4i16
- { 994, 5, 1, 44, "VSHLiv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #994 = VSHLiv4i32
- { 995, 5, 1, 44, "VSHLiv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #995 = VSHLiv8i16
- { 996, 5, 1, 44, "VSHLiv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #996 = VSHLiv8i8
- { 997, 5, 1, 45, "VSHLsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #997 = VSHLsv16i8
- { 998, 5, 1, 44, "VSHLsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #998 = VSHLsv1i64
- { 999, 5, 1, 44, "VSHLsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #999 = VSHLsv2i32
- { 1000, 5, 1, 45, "VSHLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1000 = VSHLsv2i64
- { 1001, 5, 1, 44, "VSHLsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1001 = VSHLsv4i16
- { 1002, 5, 1, 45, "VSHLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1002 = VSHLsv4i32
- { 1003, 5, 1, 45, "VSHLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1003 = VSHLsv8i16
- { 1004, 5, 1, 44, "VSHLsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1004 = VSHLsv8i8
- { 1005, 5, 1, 45, "VSHLuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1005 = VSHLuv16i8
- { 1006, 5, 1, 44, "VSHLuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1006 = VSHLuv1i64
- { 1007, 5, 1, 44, "VSHLuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1007 = VSHLuv2i32
- { 1008, 5, 1, 45, "VSHLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1008 = VSHLuv2i64
- { 1009, 5, 1, 44, "VSHLuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1009 = VSHLuv4i16
- { 1010, 5, 1, 45, "VSHLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1010 = VSHLuv4i32
- { 1011, 5, 1, 45, "VSHLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1011 = VSHLuv8i16
- { 1012, 5, 1, 44, "VSHLuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1012 = VSHLuv8i8
- { 1013, 5, 1, 44, "VSHRNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #1013 = VSHRNv2i32
- { 1014, 5, 1, 44, "VSHRNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #1014 = VSHRNv4i16
- { 1015, 5, 1, 44, "VSHRNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #1015 = VSHRNv8i8
- { 1016, 5, 1, 44, "VSHRsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #1016 = VSHRsv16i8
- { 1017, 5, 1, 44, "VSHRsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #1017 = VSHRsv1i64
- { 1018, 5, 1, 44, "VSHRsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #1018 = VSHRsv2i32
- { 1019, 5, 1, 44, "VSHRsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #1019 = VSHRsv2i64
- { 1020, 5, 1, 44, "VSHRsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #1020 = VSHRsv4i16
- { 1021, 5, 1, 44, "VSHRsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #1021 = VSHRsv4i32
- { 1022, 5, 1, 44, "VSHRsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #1022 = VSHRsv8i16
- { 1023, 5, 1, 44, "VSHRsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #1023 = VSHRsv8i8
- { 1024, 5, 1, 44, "VSHRuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #1024 = VSHRuv16i8
- { 1025, 5, 1, 44, "VSHRuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #1025 = VSHRuv1i64
- { 1026, 5, 1, 44, "VSHRuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #1026 = VSHRuv2i32
- { 1027, 5, 1, 44, "VSHRuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #1027 = VSHRuv2i64
- { 1028, 5, 1, 44, "VSHRuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #1028 = VSHRuv4i16
- { 1029, 5, 1, 44, "VSHRuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #1029 = VSHRuv4i32
- { 1030, 5, 1, 44, "VSHRuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #1030 = VSHRuv8i16
- { 1031, 5, 1, 44, "VSHRuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #1031 = VSHRuv8i8
- { 1032, 4, 1, 67, "VSITOD", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #1032 = VSITOD
- { 1033, 4, 1, 68, "VSITOS", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #1033 = VSITOS
- { 1034, 6, 1, 45, "VSLIv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #1034 = VSLIv16i8
- { 1035, 6, 1, 44, "VSLIv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1035 = VSLIv1i64
- { 1036, 6, 1, 44, "VSLIv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1036 = VSLIv2i32
- { 1037, 6, 1, 45, "VSLIv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #1037 = VSLIv2i64
- { 1038, 6, 1, 44, "VSLIv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1038 = VSLIv4i16
- { 1039, 6, 1, 45, "VSLIv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #1039 = VSLIv4i32
- { 1040, 6, 1, 45, "VSLIv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #1040 = VSLIv8i16
- { 1041, 6, 1, 44, "VSLIv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1041 = VSLIv8i8
- { 1042, 4, 1, 81, "VSQRTD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #1042 = VSQRTD
- { 1043, 4, 1, 80, "VSQRTS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #1043 = VSQRTS
- { 1044, 6, 1, 33, "VSRAsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #1044 = VSRAsv16i8
- { 1045, 6, 1, 33, "VSRAsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1045 = VSRAsv1i64
- { 1046, 6, 1, 33, "VSRAsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1046 = VSRAsv2i32
- { 1047, 6, 1, 33, "VSRAsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #1047 = VSRAsv2i64
- { 1048, 6, 1, 33, "VSRAsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1048 = VSRAsv4i16
- { 1049, 6, 1, 33, "VSRAsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #1049 = VSRAsv4i32
- { 1050, 6, 1, 33, "VSRAsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #1050 = VSRAsv8i16
- { 1051, 6, 1, 33, "VSRAsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1051 = VSRAsv8i8
- { 1052, 6, 1, 33, "VSRAuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #1052 = VSRAuv16i8
- { 1053, 6, 1, 33, "VSRAuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1053 = VSRAuv1i64
- { 1054, 6, 1, 33, "VSRAuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1054 = VSRAuv2i32
- { 1055, 6, 1, 33, "VSRAuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #1055 = VSRAuv2i64
- { 1056, 6, 1, 33, "VSRAuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1056 = VSRAuv4i16
- { 1057, 6, 1, 33, "VSRAuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #1057 = VSRAuv4i32
- { 1058, 6, 1, 33, "VSRAuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #1058 = VSRAuv8i16
- { 1059, 6, 1, 33, "VSRAuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1059 = VSRAuv8i8
- { 1060, 6, 1, 45, "VSRIv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #1060 = VSRIv16i8
- { 1061, 6, 1, 44, "VSRIv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1061 = VSRIv1i64
- { 1062, 6, 1, 44, "VSRIv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1062 = VSRIv2i32
- { 1063, 6, 1, 45, "VSRIv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #1063 = VSRIv2i64
- { 1064, 6, 1, 44, "VSRIv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1064 = VSRIv4i16
- { 1065, 6, 1, 45, "VSRIv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #1065 = VSRIv4i32
- { 1066, 6, 1, 45, "VSRIv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #1066 = VSRIv8i16
- { 1067, 6, 1, 44, "VSRIv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1067 = VSRIv8i8
- { 1068, 7, 0, 46, "VST1d16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo110 }, // Inst #1068 = VST1d16
- { 1069, 7, 0, 46, "VST1d32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo110 }, // Inst #1069 = VST1d32
- { 1070, 7, 0, 46, "VST1d64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo110 }, // Inst #1070 = VST1d64
- { 1071, 7, 0, 46, "VST1d8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo110 }, // Inst #1071 = VST1d8
- { 1072, 7, 0, 46, "VST1df", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo110 }, // Inst #1072 = VST1df
- { 1073, 7, 0, 46, "VST1q16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo111 }, // Inst #1073 = VST1q16
- { 1074, 7, 0, 46, "VST1q32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo111 }, // Inst #1074 = VST1q32
- { 1075, 7, 0, 46, "VST1q64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo111 }, // Inst #1075 = VST1q64
- { 1076, 7, 0, 46, "VST1q8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo111 }, // Inst #1076 = VST1q8
- { 1077, 7, 0, 46, "VST1qf", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo111 }, // Inst #1077 = VST1qf
- { 1078, 9, 0, 46, "VST2LNd16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo112 }, // Inst #1078 = VST2LNd16
- { 1079, 9, 0, 46, "VST2LNd32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo112 }, // Inst #1079 = VST2LNd32
- { 1080, 9, 0, 46, "VST2LNd8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo112 }, // Inst #1080 = VST2LNd8
- { 1081, 9, 0, 46, "VST2LNq16a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo112 }, // Inst #1081 = VST2LNq16a
- { 1082, 9, 0, 46, "VST2LNq16b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo112 }, // Inst #1082 = VST2LNq16b
- { 1083, 9, 0, 46, "VST2LNq32a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo112 }, // Inst #1083 = VST2LNq32a
- { 1084, 9, 0, 46, "VST2LNq32b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo112 }, // Inst #1084 = VST2LNq32b
- { 1085, 8, 0, 46, "VST2d16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo113 }, // Inst #1085 = VST2d16
- { 1086, 8, 0, 46, "VST2d32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo113 }, // Inst #1086 = VST2d32
- { 1087, 8, 0, 46, "VST2d64", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo113 }, // Inst #1087 = VST2d64
- { 1088, 8, 0, 46, "VST2d8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo113 }, // Inst #1088 = VST2d8
- { 1089, 10, 0, 46, "VST2q16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo114 }, // Inst #1089 = VST2q16
- { 1090, 10, 0, 46, "VST2q32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo114 }, // Inst #1090 = VST2q32
- { 1091, 10, 0, 46, "VST2q8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo114 }, // Inst #1091 = VST2q8
- { 1092, 10, 0, 46, "VST3LNd16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo115 }, // Inst #1092 = VST3LNd16
- { 1093, 10, 0, 46, "VST3LNd32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo115 }, // Inst #1093 = VST3LNd32
- { 1094, 10, 0, 46, "VST3LNd8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo115 }, // Inst #1094 = VST3LNd8
- { 1095, 10, 0, 46, "VST3LNq16a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo115 }, // Inst #1095 = VST3LNq16a
- { 1096, 10, 0, 46, "VST3LNq16b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo115 }, // Inst #1096 = VST3LNq16b
- { 1097, 10, 0, 46, "VST3LNq32a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo115 }, // Inst #1097 = VST3LNq32a
- { 1098, 10, 0, 46, "VST3LNq32b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo115 }, // Inst #1098 = VST3LNq32b
- { 1099, 9, 0, 46, "VST3d16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #1099 = VST3d16
- { 1100, 9, 0, 46, "VST3d32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #1100 = VST3d32
- { 1101, 9, 0, 46, "VST3d64", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #1101 = VST3d64
- { 1102, 9, 0, 46, "VST3d8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #1102 = VST3d8
- { 1103, 10, 1, 46, "VST3q16a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1103 = VST3q16a
- { 1104, 10, 1, 46, "VST3q16b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1104 = VST3q16b
- { 1105, 10, 1, 46, "VST3q32a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1105 = VST3q32a
- { 1106, 10, 1, 46, "VST3q32b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1106 = VST3q32b
- { 1107, 10, 1, 46, "VST3q8a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1107 = VST3q8a
- { 1108, 10, 1, 46, "VST3q8b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1108 = VST3q8b
- { 1109, 11, 0, 46, "VST4LNd16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1109 = VST4LNd16
- { 1110, 11, 0, 46, "VST4LNd32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1110 = VST4LNd32
- { 1111, 11, 0, 46, "VST4LNd8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1111 = VST4LNd8
- { 1112, 11, 0, 46, "VST4LNq16a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1112 = VST4LNq16a
- { 1113, 11, 0, 46, "VST4LNq16b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1113 = VST4LNq16b
- { 1114, 11, 0, 46, "VST4LNq32a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1114 = VST4LNq32a
- { 1115, 11, 0, 46, "VST4LNq32b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1115 = VST4LNq32b
- { 1116, 10, 0, 46, "VST4d16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo114 }, // Inst #1116 = VST4d16
- { 1117, 10, 0, 46, "VST4d32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo114 }, // Inst #1117 = VST4d32
- { 1118, 10, 0, 46, "VST4d64", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo114 }, // Inst #1118 = VST4d64
- { 1119, 10, 0, 46, "VST4d8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo114 }, // Inst #1119 = VST4d8
- { 1120, 11, 1, 46, "VST4q16a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo119 }, // Inst #1120 = VST4q16a
- { 1121, 11, 1, 46, "VST4q16b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo119 }, // Inst #1121 = VST4q16b
- { 1122, 11, 1, 46, "VST4q32a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo119 }, // Inst #1122 = VST4q32a
- { 1123, 11, 1, 46, "VST4q32b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo119 }, // Inst #1123 = VST4q32b
- { 1124, 11, 1, 46, "VST4q8a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo119 }, // Inst #1124 = VST4q8a
- { 1125, 11, 1, 46, "VST4q8b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo119 }, // Inst #1125 = VST4q8b
- { 1126, 5, 0, 85, "VSTMD", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|5|(3<<4)|(21<<9)|(3<<17), NULL, NULL, NULL, OperandInfo28 }, // Inst #1126 = VSTMD
- { 1127, 5, 0, 85, "VSTMS", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|5|(3<<4)|(21<<9)|(1<<17), NULL, NULL, NULL, OperandInfo28 }, // Inst #1127 = VSTMS
- { 1128, 5, 0, 84, "VSTRD", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|5|(3<<4)|(20<<9)|(3<<17), NULL, NULL, NULL, OperandInfo80 }, // Inst #1128 = VSTRD
- { 1129, 5, 0, 85, "VSTRQ", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|4|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #1129 = VSTRQ
- { 1130, 5, 0, 83, "VSTRS", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|5|(3<<4)|(20<<9)|(1<<17), NULL, NULL, NULL, OperandInfo82 }, // Inst #1130 = VSTRS
- { 1131, 5, 1, 62, "VSUBD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1131 = VSUBD
- { 1132, 5, 1, 3, "VSUBHNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #1132 = VSUBHNv2i32
- { 1133, 5, 1, 3, "VSUBHNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #1133 = VSUBHNv4i16
- { 1134, 5, 1, 3, "VSUBHNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #1134 = VSUBHNv8i8
- { 1135, 5, 1, 44, "VSUBLsv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #1135 = VSUBLsv2i64
- { 1136, 5, 1, 44, "VSUBLsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #1136 = VSUBLsv4i32
- { 1137, 5, 1, 44, "VSUBLsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #1137 = VSUBLsv8i16
- { 1138, 5, 1, 44, "VSUBLuv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #1138 = VSUBLuv2i64
- { 1139, 5, 1, 44, "VSUBLuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #1139 = VSUBLuv4i32
- { 1140, 5, 1, 44, "VSUBLuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #1140 = VSUBLuv8i16
- { 1141, 5, 1, 61, "VSUBS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #1141 = VSUBS
- { 1142, 5, 1, 47, "VSUBWsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #1142 = VSUBWsv2i64
- { 1143, 5, 1, 47, "VSUBWsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #1143 = VSUBWsv4i32
- { 1144, 5, 1, 47, "VSUBWsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #1144 = VSUBWsv8i16
- { 1145, 5, 1, 47, "VSUBWuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #1145 = VSUBWuv2i64
- { 1146, 5, 1, 47, "VSUBWuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #1146 = VSUBWuv4i32
- { 1147, 5, 1, 47, "VSUBWuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #1147 = VSUBWuv8i16
- { 1148, 5, 1, 1, "VSUBfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1148 = VSUBfd
- { 1149, 5, 1, 1, "VSUBfd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #1149 = VSUBfd_sfp
- { 1150, 5, 1, 2, "VSUBfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1150 = VSUBfq
- { 1151, 5, 1, 48, "VSUBv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1151 = VSUBv16i8
- { 1152, 5, 1, 47, "VSUBv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1152 = VSUBv1i64
- { 1153, 5, 1, 47, "VSUBv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1153 = VSUBv2i32
- { 1154, 5, 1, 48, "VSUBv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1154 = VSUBv2i64
- { 1155, 5, 1, 47, "VSUBv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1155 = VSUBv4i16
- { 1156, 5, 1, 48, "VSUBv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1156 = VSUBv4i32
- { 1157, 5, 1, 48, "VSUBv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1157 = VSUBv8i16
- { 1158, 5, 1, 47, "VSUBv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1158 = VSUBv8i8
- { 1159, 5, 1, 49, "VTBL1", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1159 = VTBL1
- { 1160, 6, 1, 50, "VTBL2", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo120 }, // Inst #1160 = VTBL2
- { 1161, 7, 1, 51, "VTBL3", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo121 }, // Inst #1161 = VTBL3
- { 1162, 8, 1, 52, "VTBL4", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo122 }, // Inst #1162 = VTBL4
- { 1163, 6, 1, 53, "VTBX1", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #1163 = VTBX1
- { 1164, 7, 1, 54, "VTBX2", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo123 }, // Inst #1164 = VTBX2
- { 1165, 8, 1, 55, "VTBX3", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1165 = VTBX3
- { 1166, 9, 1, 56, "VTBX4", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1166 = VTBX4
- { 1167, 4, 1, 65, "VTOSIZD", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #1167 = VTOSIZD
- { 1168, 4, 1, 70, "VTOSIZS", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #1168 = VTOSIZS
- { 1169, 4, 1, 65, "VTOUIZD", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #1169 = VTOUIZD
- { 1170, 4, 1, 70, "VTOUIZS", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #1170 = VTOUIZS
- { 1171, 6, 2, 35, "VTRNd16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1171 = VTRNd16
- { 1172, 6, 2, 35, "VTRNd32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1172 = VTRNd32
- { 1173, 6, 2, 35, "VTRNd8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1173 = VTRNd8
- { 1174, 6, 2, 36, "VTRNq16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo127 }, // Inst #1174 = VTRNq16
- { 1175, 6, 2, 36, "VTRNq32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo127 }, // Inst #1175 = VTRNq32
- { 1176, 6, 2, 36, "VTRNq8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo127 }, // Inst #1176 = VTRNq8
- { 1177, 5, 1, 4, "VTSTv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1177 = VTSTv16i8
- { 1178, 5, 1, 3, "VTSTv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1178 = VTSTv2i32
- { 1179, 5, 1, 3, "VTSTv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1179 = VTSTv4i16
- { 1180, 5, 1, 4, "VTSTv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1180 = VTSTv4i32
- { 1181, 5, 1, 4, "VTSTv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1181 = VTSTv8i16
- { 1182, 5, 1, 3, "VTSTv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1182 = VTSTv8i8
- { 1183, 4, 1, 67, "VUITOD", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #1183 = VUITOD
- { 1184, 4, 1, 68, "VUITOS", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #1184 = VUITOS
- { 1185, 6, 2, 35, "VUZPd16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1185 = VUZPd16
- { 1186, 6, 2, 35, "VUZPd32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1186 = VUZPd32
- { 1187, 6, 2, 35, "VUZPd8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1187 = VUZPd8
- { 1188, 6, 2, 37, "VUZPq16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo127 }, // Inst #1188 = VUZPq16
- { 1189, 6, 2, 37, "VUZPq32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo127 }, // Inst #1189 = VUZPq32
- { 1190, 6, 2, 37, "VUZPq8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo127 }, // Inst #1190 = VUZPq8
- { 1191, 6, 2, 35, "VZIPd16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1191 = VZIPd16
- { 1192, 6, 2, 35, "VZIPd32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1192 = VZIPd32
- { 1193, 6, 2, 35, "VZIPd8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1193 = VZIPd8
- { 1194, 6, 2, 37, "VZIPq16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo127 }, // Inst #1194 = VZIPq16
- { 1195, 6, 2, 37, "VZIPq32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo127 }, // Inst #1195 = VZIPq32
- { 1196, 6, 2, 37, "VZIPq8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo127 }, // Inst #1196 = VZIPq8
- { 1197, 3, 1, 88, "t2ADCSri", 0, 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #1197 = t2ADCSri
- { 1198, 3, 1, 89, "t2ADCSrr", 0|(1<<TID::Commutable), 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #1198 = t2ADCSrr
- { 1199, 4, 1, 90, "t2ADCSrs", 0, 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo128 }, // Inst #1199 = t2ADCSrs
- { 1200, 6, 1, 88, "t2ADCri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #1200 = t2ADCri
- { 1201, 6, 1, 89, "t2ADCrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo6 }, // Inst #1201 = t2ADCrr
- { 1202, 7, 1, 90, "t2ADCrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo37 }, // Inst #1202 = t2ADCrs
- { 1203, 5, 1, 88, "t2ADDSri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1203 = t2ADDSri
- { 1204, 5, 1, 89, "t2ADDSrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #1204 = t2ADDSrr
- { 1205, 6, 1, 90, "t2ADDSrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #1205 = t2ADDSrs
- { 1206, 6, 1, 88, "t2ADDrSPi", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1206 = t2ADDrSPi
- { 1207, 5, 1, 88, "t2ADDrSPi12", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1207 = t2ADDrSPi12
- { 1208, 7, 1, 90, "t2ADDrSPs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo37 }, // Inst #1208 = t2ADDrSPs
- { 1209, 6, 1, 88, "t2ADDri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1209 = t2ADDri
- { 1210, 6, 1, 88, "t2ADDri12", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1210 = t2ADDri12
- { 1211, 6, 1, 89, "t2ADDrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1211 = t2ADDrr
- { 1212, 7, 1, 90, "t2ADDrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo37 }, // Inst #1212 = t2ADDrs
- { 1213, 6, 1, 88, "t2ANDri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1213 = t2ANDri
- { 1214, 6, 1, 89, "t2ANDrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1214 = t2ANDrr
- { 1215, 7, 1, 90, "t2ANDrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo37 }, // Inst #1215 = t2ANDrs
- { 1216, 6, 1, 113, "t2ASRri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1216 = t2ASRri
- { 1217, 6, 1, 114, "t2ASRrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1217 = t2ASRrr
- { 1218, 1, 0, 0, "t2B", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Predicable)|(1<<TID::Terminator), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo14 }, // Inst #1218 = t2B
- { 1219, 5, 1, 126, "t2BFC", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo15 }, // Inst #1219 = t2BFC
- { 1220, 6, 1, 88, "t2BICri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1220 = t2BICri
- { 1221, 6, 1, 89, "t2BICrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1221 = t2BICrr
- { 1222, 7, 1, 90, "t2BICrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo37 }, // Inst #1222 = t2BICrs
- { 1223, 4, 0, 0, "t2BR_JT", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::NotDuplicable), 0|(1<<4)|(23<<9), NULL, NULL, NULL, OperandInfo17 }, // Inst #1223 = t2BR_JT
- { 1224, 3, 0, 0, "t2Bcc", 0|(1<<TID::Branch)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #1224 = t2Bcc
- { 1225, 4, 1, 125, "t2CLZ", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1225 = t2CLZ
- { 1226, 4, 0, 97, "t2CMNzri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #1226 = t2CMNzri
- { 1227, 4, 0, 98, "t2CMNzrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1227 = t2CMNzrr
- { 1228, 5, 0, 99, "t2CMNzrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1228 = t2CMNzrs
- { 1229, 4, 0, 97, "t2CMPri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #1229 = t2CMPri
- { 1230, 4, 0, 98, "t2CMPrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1230 = t2CMPrr
- { 1231, 5, 0, 99, "t2CMPrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1231 = t2CMPrs
- { 1232, 4, 0, 97, "t2CMPzri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #1232 = t2CMPzri
- { 1233, 4, 0, 98, "t2CMPzrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1233 = t2CMPzrr
- { 1234, 5, 0, 99, "t2CMPzrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1234 = t2CMPzrs
- { 1235, 6, 1, 88, "t2EORri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1235 = t2EORri
- { 1236, 6, 1, 89, "t2EORrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1236 = t2EORrr
- { 1237, 7, 1, 90, "t2EORrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo37 }, // Inst #1237 = t2EORrs
- { 1238, 2, 0, 92, "t2IT", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo129 }, // Inst #1238 = t2IT
- { 1239, 0, 0, 128, "t2Int_MemBarrierV7", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, 0 }, // Inst #1239 = t2Int_MemBarrierV7
- { 1240, 0, 0, 128, "t2Int_SyncBarrierV7", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, 0 }, // Inst #1240 = t2Int_SyncBarrierV7
- { 1241, 1, 0, 128, "t2Int_eh_sjlj_setjmp", 0, 0|(1<<4)|(23<<9), NULL, ImplicitList6, Barriers3, OperandInfo16 }, // Inst #1241 = t2Int_eh_sjlj_setjmp
- { 1242, 5, 0, 103, "t2LDM", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo28 }, // Inst #1242 = t2LDM
- { 1243, 5, 0, 0, "t2LDM_RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo28 }, // Inst #1243 = t2LDM_RET
- { 1244, 6, 2, 102, "t2LDRB_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo130 }, // Inst #1244 = t2LDRB_POST
- { 1245, 6, 2, 102, "t2LDRB_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo130 }, // Inst #1245 = t2LDRB_PRE
- { 1246, 5, 1, 101, "t2LDRBi12", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1246 = t2LDRBi12
- { 1247, 5, 1, 101, "t2LDRBi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1247 = t2LDRBi8
- { 1248, 4, 1, 101, "t2LDRBpci", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|14|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1248 = t2LDRBpci
- { 1249, 6, 1, 104, "t2LDRBs", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1249 = t2LDRBs
- { 1250, 6, 2, 101, "t2LDRDi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|15|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1250 = t2LDRDi8
- { 1251, 5, 2, 101, "t2LDRDpci", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|15|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1251 = t2LDRDpci
- { 1252, 4, 1, 128, "t2LDREX", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1252 = t2LDREX
- { 1253, 4, 1, 128, "t2LDREXB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1253 = t2LDREXB
- { 1254, 5, 2, 128, "t2LDREXD", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1254 = t2LDREXD
- { 1255, 4, 1, 128, "t2LDREXH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1255 = t2LDREXH
- { 1256, 6, 2, 102, "t2LDRH_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo130 }, // Inst #1256 = t2LDRH_POST
- { 1257, 6, 2, 102, "t2LDRH_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo130 }, // Inst #1257 = t2LDRH_PRE
- { 1258, 5, 1, 101, "t2LDRHi12", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1258 = t2LDRHi12
- { 1259, 5, 1, 101, "t2LDRHi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1259 = t2LDRHi8
- { 1260, 4, 1, 101, "t2LDRHpci", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|14|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1260 = t2LDRHpci
- { 1261, 6, 1, 104, "t2LDRHs", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1261 = t2LDRHs
- { 1262, 6, 2, 102, "t2LDRSB_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo130 }, // Inst #1262 = t2LDRSB_POST
- { 1263, 6, 2, 102, "t2LDRSB_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo130 }, // Inst #1263 = t2LDRSB_PRE
- { 1264, 5, 1, 101, "t2LDRSBi12", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1264 = t2LDRSBi12
- { 1265, 5, 1, 101, "t2LDRSBi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1265 = t2LDRSBi8
- { 1266, 4, 1, 101, "t2LDRSBpci", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|14|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1266 = t2LDRSBpci
- { 1267, 6, 1, 104, "t2LDRSBs", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1267 = t2LDRSBs
- { 1268, 6, 2, 102, "t2LDRSH_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo130 }, // Inst #1268 = t2LDRSH_POST
- { 1269, 6, 2, 102, "t2LDRSH_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo130 }, // Inst #1269 = t2LDRSH_PRE
- { 1270, 5, 1, 101, "t2LDRSHi12", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1270 = t2LDRSHi12
- { 1271, 5, 1, 101, "t2LDRSHi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1271 = t2LDRSHi8
- { 1272, 4, 1, 101, "t2LDRSHpci", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|14|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1272 = t2LDRSHpci
- { 1273, 6, 1, 104, "t2LDRSHs", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1273 = t2LDRSHs
- { 1274, 6, 2, 102, "t2LDR_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo130 }, // Inst #1274 = t2LDR_POST
- { 1275, 6, 2, 102, "t2LDR_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo130 }, // Inst #1275 = t2LDR_PRE
- { 1276, 5, 1, 101, "t2LDRi12", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1276 = t2LDRi12
- { 1277, 5, 1, 101, "t2LDRi8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1277 = t2LDRi8
- { 1278, 4, 1, 101, "t2LDRpci", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|14|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1278 = t2LDRpci
- { 1279, 3, 1, 128, "t2LDRpci_pic", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|(1<<4), NULL, NULL, NULL, OperandInfo19 }, // Inst #1279 = t2LDRpci_pic
- { 1280, 6, 1, 104, "t2LDRs", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1280 = t2LDRs
- { 1281, 4, 1, 88, "t2LEApcrel", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1281 = t2LEApcrel
- { 1282, 5, 1, 88, "t2LEApcrelJT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo30 }, // Inst #1282 = t2LEApcrelJT
- { 1283, 6, 1, 113, "t2LSLri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1283 = t2LSLri
- { 1284, 6, 1, 114, "t2LSLrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1284 = t2LSLrr
- { 1285, 6, 1, 113, "t2LSRri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1285 = t2LSRri
- { 1286, 6, 1, 114, "t2LSRrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1286 = t2LSRrr
- { 1287, 6, 1, 109, "t2MLA", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1287 = t2MLA
- { 1288, 6, 1, 109, "t2MLS", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1288 = t2MLS
- { 1289, 6, 1, 95, "t2MOVCCasr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo131 }, // Inst #1289 = t2MOVCCasr
- { 1290, 5, 1, 93, "t2MOVCCi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo15 }, // Inst #1290 = t2MOVCCi
- { 1291, 6, 1, 95, "t2MOVCClsl", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo131 }, // Inst #1291 = t2MOVCClsl
- { 1292, 6, 1, 95, "t2MOVCClsr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo131 }, // Inst #1292 = t2MOVCClsr
- { 1293, 5, 1, 94, "t2MOVCCr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #1293 = t2MOVCCr
- { 1294, 6, 1, 95, "t2MOVCCror", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo131 }, // Inst #1294 = t2MOVCCror
- { 1295, 5, 1, 111, "t2MOVTi16", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo15 }, // Inst #1295 = t2MOVTi16
- { 1296, 5, 1, 111, "t2MOVi", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::HasOptionalDef)|(1<<TID::CheapAsAMove), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo35 }, // Inst #1296 = t2MOVi
- { 1297, 4, 1, 111, "t2MOVi16", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1297 = t2MOVi16
- { 1298, 4, 1, 111, "t2MOVi32imm", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|(2<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1298 = t2MOVi32imm
- { 1299, 5, 1, 112, "t2MOVr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo36 }, // Inst #1299 = t2MOVr
- { 1300, 5, 1, 113, "t2MOVrx", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo36 }, // Inst #1300 = t2MOVrx
- { 1301, 2, 1, 113, "t2MOVsra_flag", 0, 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo132 }, // Inst #1301 = t2MOVsra_flag
- { 1302, 2, 1, 113, "t2MOVsrl_flag", 0, 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo132 }, // Inst #1302 = t2MOVsrl_flag
- { 1303, 5, 1, 116, "t2MUL", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1303 = t2MUL
- { 1304, 5, 1, 111, "t2MVNi", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::HasOptionalDef)|(1<<TID::CheapAsAMove), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo35 }, // Inst #1304 = t2MVNi
- { 1305, 4, 1, 112, "t2MVNr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1305 = t2MVNr
- { 1306, 5, 1, 113, "t2MVNs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1306 = t2MVNs
- { 1307, 6, 1, 88, "t2ORNri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1307 = t2ORNri
- { 1308, 6, 1, 89, "t2ORNrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1308 = t2ORNrr
- { 1309, 7, 1, 90, "t2ORNrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo37 }, // Inst #1309 = t2ORNrs
- { 1310, 6, 1, 88, "t2ORRri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1310 = t2ORRri
- { 1311, 6, 1, 89, "t2ORRrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1311 = t2ORRrr
- { 1312, 7, 1, 90, "t2ORRrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo37 }, // Inst #1312 = t2ORRrs
- { 1313, 6, 1, 90, "t2PKHBT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1313 = t2PKHBT
- { 1314, 6, 1, 90, "t2PKHTB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1314 = t2PKHTB
- { 1315, 4, 1, 125, "t2RBIT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1315 = t2RBIT
- { 1316, 4, 1, 125, "t2REV", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1316 = t2REV
- { 1317, 4, 1, 125, "t2REV16", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1317 = t2REV16
- { 1318, 4, 1, 125, "t2REVSH", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1318 = t2REVSH
- { 1319, 6, 1, 113, "t2RORri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1319 = t2RORri
- { 1320, 6, 1, 114, "t2RORrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1320 = t2RORrr
- { 1321, 4, 1, 88, "t2RSBSri", 0|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo133 }, // Inst #1321 = t2RSBSri
- { 1322, 5, 1, 90, "t2RSBSrs", 0|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo134 }, // Inst #1322 = t2RSBSrs
- { 1323, 5, 1, 88, "t2RSBri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1323 = t2RSBri
- { 1324, 6, 1, 90, "t2RSBrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1324 = t2RSBrs
- { 1325, 3, 1, 88, "t2SBCSri", 0, 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #1325 = t2SBCSri
- { 1326, 3, 1, 89, "t2SBCSrr", 0, 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #1326 = t2SBCSrr
- { 1327, 4, 1, 90, "t2SBCSrs", 0, 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo128 }, // Inst #1327 = t2SBCSrs
- { 1328, 6, 1, 88, "t2SBCri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #1328 = t2SBCri
- { 1329, 6, 1, 89, "t2SBCrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo6 }, // Inst #1329 = t2SBCrr
- { 1330, 7, 1, 90, "t2SBCrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo37 }, // Inst #1330 = t2SBCrs
- { 1331, 6, 1, 88, "t2SBFX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo38 }, // Inst #1331 = t2SBFX
- { 1332, 6, 1, 108, "t2SMLABB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1332 = t2SMLABB
- { 1333, 6, 1, 108, "t2SMLABT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1333 = t2SMLABT
- { 1334, 6, 2, 110, "t2SMLAL", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1334 = t2SMLAL
- { 1335, 6, 1, 108, "t2SMLATB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1335 = t2SMLATB
- { 1336, 6, 1, 108, "t2SMLATT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1336 = t2SMLATT
- { 1337, 6, 1, 108, "t2SMLAWB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1337 = t2SMLAWB
- { 1338, 6, 1, 108, "t2SMLAWT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1338 = t2SMLAWT
- { 1339, 6, 1, 109, "t2SMMLA", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1339 = t2SMMLA
- { 1340, 6, 1, 109, "t2SMMLS", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1340 = t2SMMLS
- { 1341, 5, 1, 116, "t2SMMUL", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1341 = t2SMMUL
- { 1342, 5, 1, 116, "t2SMULBB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1342 = t2SMULBB
- { 1343, 5, 1, 116, "t2SMULBT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1343 = t2SMULBT
- { 1344, 6, 2, 117, "t2SMULL", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1344 = t2SMULL
- { 1345, 5, 1, 116, "t2SMULTB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1345 = t2SMULTB
- { 1346, 5, 1, 116, "t2SMULTT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1346 = t2SMULTT
- { 1347, 5, 1, 115, "t2SMULWB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1347 = t2SMULWB
- { 1348, 5, 1, 115, "t2SMULWT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1348 = t2SMULWT
- { 1349, 5, 0, 120, "t2STM", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo28 }, // Inst #1349 = t2STM
- { 1350, 6, 1, 119, "t2STRB_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo135 }, // Inst #1350 = t2STRB_POST
- { 1351, 6, 1, 119, "t2STRB_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo135 }, // Inst #1351 = t2STRB_PRE
- { 1352, 5, 0, 118, "t2STRBi12", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1352 = t2STRBi12
- { 1353, 5, 0, 118, "t2STRBi8", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1353 = t2STRBi8
- { 1354, 6, 0, 121, "t2STRBs", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1354 = t2STRBs
- { 1355, 6, 0, 121, "t2STRDi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|15|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1355 = t2STRDi8
- { 1356, 5, 1, 128, "t2STREX", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #1356 = t2STREX
- { 1357, 5, 1, 128, "t2STREXB", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #1357 = t2STREXB
- { 1358, 6, 1, 128, "t2STREXD", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo41 }, // Inst #1358 = t2STREXD
- { 1359, 5, 1, 128, "t2STREXH", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #1359 = t2STREXH
- { 1360, 6, 1, 119, "t2STRH_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo135 }, // Inst #1360 = t2STRH_POST
- { 1361, 6, 1, 119, "t2STRH_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo135 }, // Inst #1361 = t2STRH_PRE
- { 1362, 5, 0, 118, "t2STRHi12", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1362 = t2STRHi12
- { 1363, 5, 0, 118, "t2STRHi8", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1363 = t2STRHi8
- { 1364, 6, 0, 121, "t2STRHs", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1364 = t2STRHs
- { 1365, 6, 1, 119, "t2STR_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo135 }, // Inst #1365 = t2STR_POST
- { 1366, 6, 1, 119, "t2STR_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo135 }, // Inst #1366 = t2STR_PRE
- { 1367, 5, 0, 118, "t2STRi12", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1367 = t2STRi12
- { 1368, 5, 0, 118, "t2STRi8", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1368 = t2STRi8
- { 1369, 6, 0, 121, "t2STRs", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1369 = t2STRs
- { 1370, 5, 1, 88, "t2SUBSri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1370 = t2SUBSri
- { 1371, 5, 1, 89, "t2SUBSrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #1371 = t2SUBSrr
- { 1372, 6, 1, 90, "t2SUBSrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #1372 = t2SUBSrs
- { 1373, 6, 1, 88, "t2SUBrSPi", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1373 = t2SUBrSPi
- { 1374, 5, 1, 88, "t2SUBrSPi12", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1374 = t2SUBrSPi12
- { 1375, 3, 1, 128, "t2SUBrSPi12_", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo2 }, // Inst #1375 = t2SUBrSPi12_
- { 1376, 3, 1, 128, "t2SUBrSPi_", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo2 }, // Inst #1376 = t2SUBrSPi_
- { 1377, 7, 1, 90, "t2SUBrSPs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo37 }, // Inst #1377 = t2SUBrSPs
- { 1378, 4, 1, 128, "t2SUBrSPs_", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo128 }, // Inst #1378 = t2SUBrSPs_
- { 1379, 6, 1, 88, "t2SUBri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1379 = t2SUBri
- { 1380, 6, 1, 88, "t2SUBri12", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1380 = t2SUBri12
- { 1381, 6, 1, 89, "t2SUBrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1381 = t2SUBrr
- { 1382, 7, 1, 90, "t2SUBrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo37 }, // Inst #1382 = t2SUBrs
- { 1383, 5, 1, 89, "t2SXTABrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1383 = t2SXTABrr
- { 1384, 6, 1, 91, "t2SXTABrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1384 = t2SXTABrr_rot
- { 1385, 5, 1, 89, "t2SXTAHrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1385 = t2SXTAHrr
- { 1386, 6, 1, 91, "t2SXTAHrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1386 = t2SXTAHrr_rot
- { 1387, 4, 1, 125, "t2SXTBr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1387 = t2SXTBr
- { 1388, 5, 1, 126, "t2SXTBr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1388 = t2SXTBr_rot
- { 1389, 4, 1, 125, "t2SXTHr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1389 = t2SXTHr
- { 1390, 5, 1, 126, "t2SXTHr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1390 = t2SXTHr_rot
- { 1391, 3, 0, 0, "t2TBB", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::NotDuplicable)|(1<<TID::UnmodeledSideEffects), 0|(1<<4)|(23<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #1391 = t2TBB
- { 1392, 3, 0, 0, "t2TBH", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::NotDuplicable)|(1<<TID::UnmodeledSideEffects), 0|(1<<4)|(23<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #1392 = t2TBH
- { 1393, 4, 0, 97, "t2TEQri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #1393 = t2TEQri
- { 1394, 4, 0, 98, "t2TEQrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1394 = t2TEQrr
- { 1395, 5, 0, 99, "t2TEQrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1395 = t2TEQrs
- { 1396, 0, 0, 0, "t2TPsoft", 0|(1<<TID::Call), 0|(3<<4)|(23<<9), NULL, ImplicitList7, Barriers1, 0 }, // Inst #1396 = t2TPsoft
- { 1397, 4, 0, 97, "t2TSTri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #1397 = t2TSTri
- { 1398, 4, 0, 98, "t2TSTrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1398 = t2TSTrr
- { 1399, 5, 0, 99, "t2TSTrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1399 = t2TSTrs
- { 1400, 6, 1, 88, "t2UBFX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo38 }, // Inst #1400 = t2UBFX
- { 1401, 6, 2, 110, "t2UMAAL", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1401 = t2UMAAL
- { 1402, 6, 2, 110, "t2UMLAL", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1402 = t2UMLAL
- { 1403, 6, 2, 117, "t2UMULL", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1403 = t2UMULL
- { 1404, 5, 1, 89, "t2UXTABrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1404 = t2UXTABrr
- { 1405, 6, 1, 91, "t2UXTABrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1405 = t2UXTABrr_rot
- { 1406, 5, 1, 89, "t2UXTAHrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1406 = t2UXTAHrr
- { 1407, 6, 1, 91, "t2UXTAHrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1407 = t2UXTAHrr_rot
- { 1408, 4, 1, 125, "t2UXTB16r", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1408 = t2UXTB16r
- { 1409, 5, 1, 126, "t2UXTB16r_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1409 = t2UXTB16r_rot
- { 1410, 4, 1, 125, "t2UXTBr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1410 = t2UXTBr
- { 1411, 5, 1, 126, "t2UXTBr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1411 = t2UXTBr_rot
- { 1412, 4, 1, 125, "t2UXTHr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1412 = t2UXTHr
- { 1413, 5, 1, 126, "t2UXTHr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1413 = t2UXTHr_rot
- { 1414, 6, 2, 89, "tADC", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo136 }, // Inst #1414 = tADC
- { 1415, 5, 1, 89, "tADDhirr", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #1415 = tADDhirr
- { 1416, 6, 2, 88, "tADDi3", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo137 }, // Inst #1416 = tADDi3
- { 1417, 6, 2, 88, "tADDi8", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo138 }, // Inst #1417 = tADDi8
- { 1418, 2, 1, 88, "tADDrPCi", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo139 }, // Inst #1418 = tADDrPCi
- { 1419, 3, 1, 89, "tADDrSP", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo140 }, // Inst #1419 = tADDrSP
- { 1420, 3, 1, 88, "tADDrSPi", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo141 }, // Inst #1420 = tADDrSPi
- { 1421, 6, 2, 89, "tADDrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo142 }, // Inst #1421 = tADDrr
- { 1422, 3, 1, 88, "tADDspi", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo143 }, // Inst #1422 = tADDspi
- { 1423, 3, 1, 89, "tADDspr", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo140 }, // Inst #1423 = tADDspr
- { 1424, 3, 1, 128, "tADDspr_", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo3 }, // Inst #1424 = tADDspr_
- { 1425, 1, 0, 128, "tADJCALLSTACKDOWN", 0, 0|(1<<4), ImplicitList2, ImplicitList2, NULL, OperandInfo14 }, // Inst #1425 = tADJCALLSTACKDOWN
- { 1426, 2, 0, 128, "tADJCALLSTACKUP", 0, 0|(1<<4), ImplicitList2, ImplicitList2, NULL, OperandInfo129 }, // Inst #1426 = tADJCALLSTACKUP
- { 1427, 6, 2, 89, "tAND", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo136 }, // Inst #1427 = tAND
- { 1428, 3, 1, 128, "tANDsp", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, ImplicitList1, Barriers1, OperandInfo144 }, // Inst #1428 = tANDsp
- { 1429, 6, 2, 113, "tASRri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo137 }, // Inst #1429 = tASRri
- { 1430, 6, 2, 114, "tASRrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo136 }, // Inst #1430 = tASRrr
- { 1431, 1, 0, 0, "tB", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Predicable)|(1<<TID::Terminator), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo14 }, // Inst #1431 = tB
- { 1432, 6, 2, 89, "tBIC", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo136 }, // Inst #1432 = tBIC
- { 1433, 1, 0, 0, "tBL", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList3, Barriers2, OperandInfo14 }, // Inst #1433 = tBL
- { 1434, 1, 0, 0, "tBLXi", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList3, Barriers2, OperandInfo14 }, // Inst #1434 = tBLXi
- { 1435, 1, 0, 0, "tBLXi_r9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList4, Barriers2, OperandInfo14 }, // Inst #1435 = tBLXi_r9
- { 1436, 1, 0, 0, "tBLXr", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(4<<4)|(23<<9), NULL, ImplicitList3, Barriers2, OperandInfo16 }, // Inst #1436 = tBLXr
- { 1437, 1, 0, 0, "tBLXr_r9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(4<<4)|(23<<9), NULL, ImplicitList4, Barriers2, OperandInfo16 }, // Inst #1437 = tBLXr_r9
- { 1438, 1, 0, 0, "tBLr9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList4, Barriers2, OperandInfo14 }, // Inst #1438 = tBLr9
- { 1439, 1, 0, 0, "tBRIND", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo16 }, // Inst #1439 = tBRIND
- { 1440, 3, 0, 0, "tBR_JTr", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|(1<<4)|(23<<9), NULL, NULL, NULL, OperandInfo145 }, // Inst #1440 = tBR_JTr
- { 1441, 1, 0, 0, "tBX", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList3, Barriers2, OperandInfo146 }, // Inst #1441 = tBX
- { 1442, 0, 0, 0, "tBX_RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|(4<<4)|(23<<9), NULL, NULL, NULL, 0 }, // Inst #1442 = tBX_RET
- { 1443, 1, 0, 0, "tBX_RET_vararg", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo146 }, // Inst #1443 = tBX_RET_vararg
- { 1444, 1, 0, 0, "tBXr9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList4, Barriers2, OperandInfo146 }, // Inst #1444 = tBXr9
- { 1445, 3, 0, 0, "tBcc", 0|(1<<TID::Branch)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #1445 = tBcc
- { 1446, 1, 0, 0, "tBfar", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, ImplicitList8, NULL, OperandInfo14 }, // Inst #1446 = tBfar
- { 1447, 2, 0, 0, "tCBNZ", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo139 }, // Inst #1447 = tCBNZ
- { 1448, 2, 0, 0, "tCBZ", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo139 }, // Inst #1448 = tCBZ
- { 1449, 4, 0, 98, "tCMNz", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo147 }, // Inst #1449 = tCMNz
- { 1450, 4, 0, 98, "tCMPhir", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1450 = tCMPhir
- { 1451, 4, 0, 97, "tCMPi8", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo148 }, // Inst #1451 = tCMPi8
- { 1452, 4, 0, 98, "tCMPr", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo147 }, // Inst #1452 = tCMPr
- { 1453, 4, 0, 98, "tCMPzhir", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1453 = tCMPzhir
- { 1454, 4, 0, 97, "tCMPzi8", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo148 }, // Inst #1454 = tCMPzi8
- { 1455, 4, 0, 98, "tCMPzr", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo147 }, // Inst #1455 = tCMPzr
- { 1456, 6, 2, 89, "tEOR", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo136 }, // Inst #1456 = tEOR
- { 1457, 1, 0, 128, "tInt_eh_sjlj_setjmp", 0, 0|(1<<4)|(23<<9), NULL, ImplicitList9, Barriers4, OperandInfo16 }, // Inst #1457 = tInt_eh_sjlj_setjmp
- { 1458, 5, 0, 103, "tLDM", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo28 }, // Inst #1458 = tLDM
- { 1459, 6, 1, 104, "tLDR", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|9|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo149 }, // Inst #1459 = tLDR
- { 1460, 6, 1, 104, "tLDRB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|7|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo149 }, // Inst #1460 = tLDRB
- { 1461, 6, 1, 104, "tLDRBi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|7|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo149 }, // Inst #1461 = tLDRBi
- { 1462, 6, 1, 104, "tLDRH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|8|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo149 }, // Inst #1462 = tLDRH
- { 1463, 6, 1, 104, "tLDRHi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|8|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo149 }, // Inst #1463 = tLDRHi
- { 1464, 5, 1, 104, "tLDRSB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|7|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo150 }, // Inst #1464 = tLDRSB
- { 1465, 5, 1, 104, "tLDRSH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|8|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo150 }, // Inst #1465 = tLDRSH
- { 1466, 4, 1, 101, "tLDRcp", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::UnmodeledSideEffects), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo148 }, // Inst #1466 = tLDRcp
- { 1467, 6, 1, 104, "tLDRi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|9|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo149 }, // Inst #1467 = tLDRi
- { 1468, 4, 1, 101, "tLDRpci", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo148 }, // Inst #1468 = tLDRpci
- { 1469, 3, 1, 128, "tLDRpci_pic", 0|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|(1<<4), NULL, NULL, NULL, OperandInfo19 }, // Inst #1469 = tLDRpci_pic
- { 1470, 5, 1, 101, "tLDRspi", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo151 }, // Inst #1470 = tLDRspi
- { 1471, 4, 1, 88, "tLEApcrel", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo148 }, // Inst #1471 = tLEApcrel
- { 1472, 5, 1, 88, "tLEApcrelJT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo152 }, // Inst #1472 = tLEApcrelJT
- { 1473, 6, 2, 113, "tLSLri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo137 }, // Inst #1473 = tLSLri
- { 1474, 6, 2, 114, "tLSLrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo136 }, // Inst #1474 = tLSLrr
- { 1475, 6, 2, 113, "tLSRri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo137 }, // Inst #1475 = tLSRri
- { 1476, 6, 2, 114, "tLSRrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo136 }, // Inst #1476 = tLSRrr
- { 1477, 5, 1, 93, "tMOVCCi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo15 }, // Inst #1477 = tMOVCCi
- { 1478, 5, 1, 94, "tMOVCCr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #1478 = tMOVCCr
- { 1479, 5, 1, 128, "tMOVCCr_pseudo", 0|(1<<TID::Predicable)|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo150 }, // Inst #1479 = tMOVCCr_pseudo
- { 1480, 2, 1, 112, "tMOVSr", 0, 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo153 }, // Inst #1480 = tMOVSr
- { 1481, 2, 1, 112, "tMOVgpr2gpr", 0, 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo132 }, // Inst #1481 = tMOVgpr2gpr
- { 1482, 2, 1, 112, "tMOVgpr2tgpr", 0, 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo154 }, // Inst #1482 = tMOVgpr2tgpr
- { 1483, 5, 2, 111, "tMOVi8", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo155 }, // Inst #1483 = tMOVi8
- { 1484, 2, 1, 112, "tMOVr", 0, 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo153 }, // Inst #1484 = tMOVr
- { 1485, 2, 1, 112, "tMOVtgpr2gpr", 0, 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo156 }, // Inst #1485 = tMOVtgpr2gpr
- { 1486, 6, 2, 116, "tMUL", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo136 }, // Inst #1486 = tMUL
- { 1487, 5, 2, 112, "tMVN", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo157 }, // Inst #1487 = tMVN
- { 1488, 6, 2, 89, "tORR", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo136 }, // Inst #1488 = tORR
- { 1489, 3, 1, 89, "tPICADD", 0|(1<<TID::NotDuplicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo143 }, // Inst #1489 = tPICADD
- { 1490, 3, 0, 0, "tPOP", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|(4<<4)|(23<<9), ImplicitList2, ImplicitList2, NULL, OperandInfo158 }, // Inst #1490 = tPOP
- { 1491, 3, 0, 0, "tPOP_RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo158 }, // Inst #1491 = tPOP_RET
- { 1492, 3, 0, 0, "tPUSH", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|(4<<4)|(23<<9), ImplicitList2, ImplicitList2, NULL, OperandInfo158 }, // Inst #1492 = tPUSH
- { 1493, 4, 1, 125, "tREV", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo147 }, // Inst #1493 = tREV
- { 1494, 4, 1, 125, "tREV16", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo147 }, // Inst #1494 = tREV16
- { 1495, 4, 1, 125, "tREVSH", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo147 }, // Inst #1495 = tREVSH
- { 1496, 6, 2, 114, "tROR", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo136 }, // Inst #1496 = tROR
- { 1497, 5, 2, 88, "tRSB", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo157 }, // Inst #1497 = tRSB
- { 1498, 5, 1, 101, "tRestore", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo151 }, // Inst #1498 = tRestore
- { 1499, 6, 2, 89, "tSBC", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo136 }, // Inst #1499 = tSBC
- { 1500, 5, 0, 120, "tSTM", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo28 }, // Inst #1500 = tSTM
- { 1501, 6, 0, 121, "tSTR", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|9|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo149 }, // Inst #1501 = tSTR
- { 1502, 6, 0, 121, "tSTRB", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|7|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo149 }, // Inst #1502 = tSTRB
- { 1503, 6, 0, 121, "tSTRBi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|7|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo149 }, // Inst #1503 = tSTRBi
- { 1504, 6, 0, 121, "tSTRH", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|8|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo149 }, // Inst #1504 = tSTRH
- { 1505, 6, 0, 121, "tSTRHi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|8|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo149 }, // Inst #1505 = tSTRHi
- { 1506, 6, 0, 121, "tSTRi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|9|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo149 }, // Inst #1506 = tSTRi
- { 1507, 5, 0, 118, "tSTRspi", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo151 }, // Inst #1507 = tSTRspi
- { 1508, 6, 2, 88, "tSUBi3", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo137 }, // Inst #1508 = tSUBi3
- { 1509, 6, 2, 88, "tSUBi8", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo138 }, // Inst #1509 = tSUBi8
- { 1510, 6, 2, 89, "tSUBrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo142 }, // Inst #1510 = tSUBrr
- { 1511, 3, 1, 88, "tSUBspi", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo143 }, // Inst #1511 = tSUBspi
- { 1512, 3, 1, 128, "tSUBspi_", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo2 }, // Inst #1512 = tSUBspi_
- { 1513, 4, 1, 125, "tSXTB", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo147 }, // Inst #1513 = tSXTB
- { 1514, 4, 1, 125, "tSXTH", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo147 }, // Inst #1514 = tSXTH
- { 1515, 5, 0, 118, "tSpill", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo151 }, // Inst #1515 = tSpill
- { 1516, 0, 0, 0, "tTPsoft", 0|(1<<TID::Call), 0|(3<<4)|(23<<9), NULL, ImplicitList10, NULL, 0 }, // Inst #1516 = tTPsoft
- { 1517, 4, 0, 98, "tTST", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo147 }, // Inst #1517 = tTST
- { 1518, 4, 1, 125, "tUXTB", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo147 }, // Inst #1518 = tUXTB
- { 1519, 4, 1, 125, "tUXTH", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo147 }, // Inst #1519 = tUXTH
+ { 58, 3, 0, 128, "BKPT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #58 = BKPT
+ { 59, 1, 0, 0, "BL", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(2<<9), NULL, ImplicitList3, Barriers2, OperandInfo14 }, // Inst #59 = BL
+ { 60, 1, 0, 0, "BLX", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(3<<9), NULL, ImplicitList3, Barriers2, OperandInfo16 }, // Inst #60 = BLX
+ { 61, 1, 0, 0, "BLXr9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(3<<9), NULL, ImplicitList4, Barriers2, OperandInfo16 }, // Inst #61 = BLXr9
+ { 62, 3, 0, 0, "BL_pred", 0|(1<<TID::Call)|(1<<TID::Predicable)|(1<<TID::Variadic), 0|(3<<4)|(2<<9), NULL, ImplicitList3, Barriers2, OperandInfo11 }, // Inst #62 = BL_pred
+ { 63, 1, 0, 0, "BLr9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(2<<9), NULL, ImplicitList4, Barriers2, OperandInfo14 }, // Inst #63 = BLr9
+ { 64, 3, 0, 0, "BLr9_pred", 0|(1<<TID::Call)|(1<<TID::Predicable)|(1<<TID::Variadic), 0|(3<<4)|(2<<9), NULL, ImplicitList4, Barriers2, OperandInfo11 }, // Inst #64 = BLr9_pred
+ { 65, 1, 0, 0, "BRIND", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|(3<<4)|(3<<9), NULL, NULL, NULL, OperandInfo16 }, // Inst #65 = BRIND
+ { 66, 4, 0, 0, "BR_JTadd", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::NotDuplicable), 0|(1<<4)|(3<<9), NULL, NULL, NULL, OperandInfo17 }, // Inst #66 = BR_JTadd
+ { 67, 5, 0, 0, "BR_JTm", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::Terminator)|(1<<TID::NotDuplicable), 0|(1<<4)|(3<<9), NULL, NULL, NULL, OperandInfo18 }, // Inst #67 = BR_JTm
+ { 68, 3, 0, 0, "BR_JTr", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::NotDuplicable), 0|(1<<4)|(3<<9), NULL, NULL, NULL, OperandInfo19 }, // Inst #68 = BR_JTr
+ { 69, 1, 0, 0, "BX", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(2<<4)|(3<<9), NULL, ImplicitList3, Barriers2, OperandInfo16 }, // Inst #69 = BX
+ { 70, 3, 0, 128, "BXJ", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo20 }, // Inst #70 = BXJ
+ { 71, 2, 0, 0, "BX_RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Predicable)|(1<<TID::Terminator), 0|(3<<4)|(3<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #71 = BX_RET
+ { 72, 1, 0, 0, "BXr9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(2<<4)|(3<<9), NULL, ImplicitList4, Barriers2, OperandInfo16 }, // Inst #72 = BXr9
+ { 73, 3, 0, 0, "Bcc", 0|(1<<TID::Branch)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #73 = Bcc
+ { 74, 8, 0, 128, "CDP", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #74 = CDP
+ { 75, 6, 0, 128, "CDP2", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #75 = CDP2
+ { 76, 4, 1, 125, "CLZ", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #76 = CLZ
+ { 77, 4, 0, 97, "CMNzri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 }, // Inst #77 = CMNzri
+ { 78, 4, 0, 98, "CMNzrr", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo24 }, // Inst #78 = CMNzrr
+ { 79, 6, 0, 100, "CMNzrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo26 }, // Inst #79 = CMNzrs
+ { 80, 4, 0, 97, "CMPri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 }, // Inst #80 = CMPri
+ { 81, 4, 0, 98, "CMPrr", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo24 }, // Inst #81 = CMPrr
+ { 82, 6, 0, 100, "CMPrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo26 }, // Inst #82 = CMPrs
+ { 83, 4, 0, 97, "CMPzri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 }, // Inst #83 = CMPzri
+ { 84, 4, 0, 98, "CMPzrr", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo24 }, // Inst #84 = CMPzrr
+ { 85, 6, 0, 100, "CMPzrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo26 }, // Inst #85 = CMPzrs
+ { 86, 3, 0, 128, "CONSTPOOL_ENTRY", 0|(1<<TID::NotDuplicable), 0|(1<<4), NULL, NULL, NULL, OperandInfo27 }, // Inst #86 = CONSTPOOL_ENTRY
+ { 87, 1, 0, 128, "CPS", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo14 }, // Inst #87 = CPS
+ { 88, 3, 0, 128, "DBG", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #88 = DBG
+ { 89, 6, 1, 88, "EORri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #89 = EORri
+ { 90, 6, 1, 89, "EORrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #90 = EORrr
+ { 91, 8, 1, 91, "EORrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), NULL, NULL, NULL, OperandInfo7 }, // Inst #91 = EORrs
+ { 92, 4, 1, 26, "FCONSTD", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|(3<<4)|(22<<9)|(1<<17), NULL, NULL, NULL, OperandInfo28 }, // Inst #92 = FCONSTD
+ { 93, 4, 1, 26, "FCONSTS", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|(3<<4)|(22<<9)|(1<<17), NULL, NULL, NULL, OperandInfo29 }, // Inst #93 = FCONSTS
+ { 94, 2, 0, 82, "FMSTAT", 0|(1<<TID::Predicable), 0|(3<<4)|(22<<9)|(1<<17), ImplicitList5, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #94 = FMSTAT
+ { 95, 1, 0, 128, "Int_MemBarrierV6", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, OperandInfo16 }, // Inst #95 = Int_MemBarrierV6
+ { 96, 0, 0, 128, "Int_MemBarrierV7", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, 0 }, // Inst #96 = Int_MemBarrierV7
+ { 97, 1, 0, 128, "Int_SyncBarrierV6", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, OperandInfo16 }, // Inst #97 = Int_SyncBarrierV6
+ { 98, 0, 0, 128, "Int_SyncBarrierV7", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, 0 }, // Inst #98 = Int_SyncBarrierV7
+ { 99, 2, 0, 128, "Int_eh_sjlj_setjmp", 0, 0|(1<<4), NULL, ImplicitList6, Barriers3, OperandInfo31 }, // Inst #99 = Int_eh_sjlj_setjmp
+ { 100, 5, 0, 103, "LDM", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|4|(3<<4)|(10<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #100 = LDM
+ { 101, 5, 0, 0, "LDM_RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|4|(3<<4)|(10<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #101 = LDM_RET
+ { 102, 6, 1, 104, "LDR", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|2|(3<<4)|(6<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #102 = LDR
+ { 103, 6, 1, 104, "LDRB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|2|(3<<4)|(6<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #103 = LDRB
+ { 104, 7, 2, 105, "LDRBT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|2|(3<<4)|(2<<7)|(6<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #104 = LDRBT
+ { 105, 7, 2, 105, "LDRB_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|2|(3<<4)|(2<<7)|(6<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #105 = LDRB_POST
+ { 106, 7, 2, 105, "LDRB_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|2|(3<<4)|(1<<7)|(6<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #106 = LDRB_PRE
+ { 107, 7, 2, 104, "LDRD", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(8<<9), NULL, NULL, NULL, OperandInfo10 }, // Inst #107 = LDRD
+ { 108, 4, 1, 128, "LDREX", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #108 = LDREX
+ { 109, 4, 1, 128, "LDREXB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #109 = LDREXB
+ { 110, 5, 2, 128, "LDREXD", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #110 = LDREXD
+ { 111, 4, 1, 128, "LDREXH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #111 = LDREXH
+ { 112, 6, 1, 104, "LDRH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|3|(3<<4)|(8<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #112 = LDRH
+ { 113, 7, 2, 105, "LDRH_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(2<<7)|(8<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #113 = LDRH_POST
+ { 114, 7, 2, 105, "LDRH_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(1<<7)|(8<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #114 = LDRH_PRE
+ { 115, 6, 1, 104, "LDRSB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|3|(3<<4)|(8<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #115 = LDRSB
+ { 116, 7, 2, 105, "LDRSB_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(2<<7)|(8<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #116 = LDRSB_POST
+ { 117, 7, 2, 105, "LDRSB_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(1<<7)|(8<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #117 = LDRSB_PRE
+ { 118, 6, 1, 104, "LDRSH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|3|(3<<4)|(8<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #118 = LDRSH
+ { 119, 7, 2, 105, "LDRSH_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(2<<7)|(8<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #119 = LDRSH_POST
+ { 120, 7, 2, 105, "LDRSH_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(1<<7)|(8<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #120 = LDRSH_PRE
+ { 121, 7, 2, 105, "LDRT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|2|(3<<4)|(2<<7)|(6<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #121 = LDRT
+ { 122, 7, 2, 105, "LDR_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|2|(3<<4)|(2<<7)|(6<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #122 = LDR_POST
+ { 123, 7, 2, 105, "LDR_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|2|(3<<4)|(1<<7)|(6<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #123 = LDR_PRE
+ { 124, 6, 1, 104, "LDRcp", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::UnmodeledSideEffects), 0|2|(3<<4)|(6<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #124 = LDRcp
+ { 125, 4, 1, 88, "LEApcrel", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4), NULL, NULL, NULL, OperandInfo25 }, // Inst #125 = LEApcrel
+ { 126, 5, 1, 88, "LEApcrelJT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4), NULL, NULL, NULL, OperandInfo34 }, // Inst #126 = LEApcrelJT
+ { 127, 8, 0, 128, "MCR", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo35 }, // Inst #127 = MCR
+ { 128, 6, 0, 128, "MCR2", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo36 }, // Inst #128 = MCR2
+ { 129, 7, 0, 128, "MCRR", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo37 }, // Inst #129 = MCRR
+ { 130, 5, 0, 128, "MCRR2", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo38 }, // Inst #130 = MCRR2
+ { 131, 7, 1, 109, "MLA", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo39 }, // Inst #131 = MLA
+ { 132, 6, 1, 109, "MLS", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #132 = MLS
+ { 133, 5, 1, 93, "MOVCCi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo15 }, // Inst #133 = MOVCCi
+ { 134, 5, 1, 94, "MOVCCr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo41 }, // Inst #134 = MOVCCr
+ { 135, 7, 1, 96, "MOVCCs", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4)|(5<<9)|(1<<15), NULL, NULL, NULL, OperandInfo42 }, // Inst #135 = MOVCCs
+ { 136, 5, 1, 111, "MOVTi16", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo15 }, // Inst #136 = MOVTi16
+ { 137, 5, 1, 111, "MOVi", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::HasOptionalDef)|(1<<TID::CheapAsAMove), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo43 }, // Inst #137 = MOVi
+ { 138, 4, 1, 111, "MOVi16", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo25 }, // Inst #138 = MOVi16
+ { 139, 4, 1, 111, "MOVi2pieces", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|1|(2<<4), NULL, NULL, NULL, OperandInfo25 }, // Inst #139 = MOVi2pieces
+ { 140, 4, 1, 111, "MOVi32imm", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|1|(2<<4), NULL, NULL, NULL, OperandInfo25 }, // Inst #140 = MOVi32imm
+ { 141, 5, 1, 112, "MOVr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo44 }, // Inst #141 = MOVr
+ { 142, 5, 1, 113, "MOVrx", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(1<<15), ImplicitList1, NULL, NULL, OperandInfo44 }, // Inst #142 = MOVrx
+ { 143, 7, 1, 114, "MOVs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9)|(1<<15), NULL, NULL, NULL, OperandInfo45 }, // Inst #143 = MOVs
+ { 144, 4, 1, 113, "MOVsra_flag", 0|(1<<TID::Predicable), 0|1|(3<<4)|(1<<15), NULL, ImplicitList1, Barriers1, OperandInfo24 }, // Inst #144 = MOVsra_flag
+ { 145, 4, 1, 113, "MOVsrl_flag", 0|(1<<TID::Predicable), 0|1|(3<<4)|(1<<15), NULL, ImplicitList1, Barriers1, OperandInfo24 }, // Inst #145 = MOVsrl_flag
+ { 146, 8, 0, 128, "MRC", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo35 }, // Inst #146 = MRC
+ { 147, 6, 0, 128, "MRC2", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo36 }, // Inst #147 = MRC2
+ { 148, 7, 0, 128, "MRRC", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo37 }, // Inst #148 = MRRC
+ { 149, 5, 0, 128, "MRRC2", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo38 }, // Inst #149 = MRRC2
+ { 150, 3, 1, 128, "MRS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo20 }, // Inst #150 = MRS
+ { 151, 3, 1, 128, "MRSsys", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo20 }, // Inst #151 = MRSsys
+ { 152, 3, 0, 128, "MSR", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo20 }, // Inst #152 = MSR
+ { 153, 3, 0, 128, "MSRsys", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo20 }, // Inst #153 = MSRsys
+ { 154, 6, 1, 116, "MUL", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #154 = MUL
+ { 155, 5, 1, 111, "MVNi", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::HasOptionalDef)|(1<<TID::CheapAsAMove), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo43 }, // Inst #155 = MVNi
+ { 156, 5, 1, 112, "MVNr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo44 }, // Inst #156 = MVNr
+ { 157, 7, 1, 114, "MVNs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9)|(1<<15), NULL, NULL, NULL, OperandInfo45 }, // Inst #157 = MVNs
+ { 158, 2, 0, 128, "NOP", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #158 = NOP
+ { 159, 6, 1, 88, "ORRri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #159 = ORRri
+ { 160, 6, 1, 89, "ORRrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #160 = ORRrr
+ { 161, 8, 1, 91, "ORRrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), NULL, NULL, NULL, OperandInfo7 }, // Inst #161 = ORRrs
+ { 162, 5, 1, 89, "PICADD", 0|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|1|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #162 = PICADD
+ { 163, 5, 1, 104, "PICLDR", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|2|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #163 = PICLDR
+ { 164, 5, 1, 104, "PICLDRB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|2|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #164 = PICLDRB
+ { 165, 5, 1, 104, "PICLDRH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|3|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #165 = PICLDRH
+ { 166, 5, 1, 104, "PICLDRSB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|3|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #166 = PICLDRSB
+ { 167, 5, 1, 104, "PICLDRSH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|3|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #167 = PICLDRSH
+ { 168, 5, 0, 121, "PICSTR", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|2|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #168 = PICSTR
+ { 169, 5, 0, 121, "PICSTRB", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|2|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #169 = PICSTRB
+ { 170, 5, 0, 121, "PICSTRH", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|3|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #170 = PICSTRH
+ { 171, 6, 1, 90, "PKHBT", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #171 = PKHBT
+ { 172, 6, 1, 90, "PKHTB", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #172 = PKHTB
+ { 173, 5, 1, 89, "QADD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #173 = QADD
+ { 174, 5, 1, 89, "QADD16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #174 = QADD16
+ { 175, 5, 1, 89, "QADD8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #175 = QADD8
+ { 176, 5, 1, 89, "QASX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #176 = QASX
+ { 177, 5, 1, 89, "QDADD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #177 = QDADD
+ { 178, 5, 1, 89, "QDSUB", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #178 = QDSUB
+ { 179, 5, 1, 89, "QSAX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #179 = QSAX
+ { 180, 5, 1, 89, "QSUB", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #180 = QSUB
+ { 181, 5, 1, 89, "QSUB16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #181 = QSUB16
+ { 182, 5, 1, 89, "QSUB8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #182 = QSUB8
+ { 183, 4, 1, 125, "RBIT", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #183 = RBIT
+ { 184, 4, 1, 125, "REV", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #184 = REV
+ { 185, 4, 1, 125, "REV16", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #185 = REV16
+ { 186, 4, 1, 125, "REVSH", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #186 = REVSH
+ { 187, 5, 1, 88, "RSBSri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #187 = RSBSri
+ { 188, 7, 1, 91, "RSBSrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #188 = RSBSrs
+ { 189, 6, 1, 88, "RSBri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #189 = RSBri
+ { 190, 8, 1, 91, "RSBrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), NULL, NULL, NULL, OperandInfo7 }, // Inst #190 = RSBrs
+ { 191, 3, 1, 88, "RSCSri", 0, 0|1|(3<<4)|(4<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #191 = RSCSri
+ { 192, 5, 1, 91, "RSCSrs", 0, 0|1|(3<<4)|(5<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #192 = RSCSrs
+ { 193, 6, 1, 88, "RSCri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #193 = RSCri
+ { 194, 8, 1, 91, "RSCrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), ImplicitList1, NULL, NULL, OperandInfo7 }, // Inst #194 = RSCrs
+ { 195, 3, 1, 88, "SBCSSri", 0, 0|1|(3<<4)|(4<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #195 = SBCSSri
+ { 196, 3, 1, 89, "SBCSSrr", 0, 0|1|(3<<4)|(4<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #196 = SBCSSrr
+ { 197, 5, 1, 91, "SBCSSrs", 0, 0|1|(3<<4)|(5<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #197 = SBCSSrs
+ { 198, 6, 1, 88, "SBCri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #198 = SBCri
+ { 199, 6, 1, 89, "SBCrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), ImplicitList1, NULL, NULL, OperandInfo6 }, // Inst #199 = SBCrr
+ { 200, 8, 1, 91, "SBCrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), ImplicitList1, NULL, NULL, OperandInfo7 }, // Inst #200 = SBCrs
+ { 201, 6, 1, 88, "SBFX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo46 }, // Inst #201 = SBFX
+ { 202, 0, 0, 128, "SETENDBE", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 }, // Inst #202 = SETENDBE
+ { 203, 0, 0, 128, "SETENDLE", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 }, // Inst #203 = SETENDLE
+ { 204, 2, 0, 128, "SEV", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #204 = SEV
+ { 205, 6, 1, 108, "SMLABB", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #205 = SMLABB
+ { 206, 6, 1, 108, "SMLABT", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #206 = SMLABT
+ { 207, 7, 2, 110, "SMLAL", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo39 }, // Inst #207 = SMLAL
+ { 208, 6, 2, 110, "SMLALBB", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #208 = SMLALBB
+ { 209, 6, 2, 110, "SMLALBT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #209 = SMLALBT
+ { 210, 6, 2, 110, "SMLALTB", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #210 = SMLALTB
+ { 211, 6, 2, 110, "SMLALTT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #211 = SMLALTT
+ { 212, 6, 1, 108, "SMLATB", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #212 = SMLATB
+ { 213, 6, 1, 108, "SMLATT", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #213 = SMLATT
+ { 214, 6, 1, 108, "SMLAWB", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #214 = SMLAWB
+ { 215, 6, 1, 108, "SMLAWT", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #215 = SMLAWT
+ { 216, 6, 1, 109, "SMMLA", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #216 = SMMLA
+ { 217, 6, 1, 109, "SMMLS", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #217 = SMMLS
+ { 218, 5, 1, 116, "SMMUL", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #218 = SMMUL
+ { 219, 5, 1, 116, "SMULBB", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #219 = SMULBB
+ { 220, 5, 1, 116, "SMULBT", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #220 = SMULBT
+ { 221, 7, 2, 117, "SMULL", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo39 }, // Inst #221 = SMULL
+ { 222, 5, 1, 116, "SMULTB", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #222 = SMULTB
+ { 223, 5, 1, 116, "SMULTT", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #223 = SMULTT
+ { 224, 5, 1, 115, "SMULWB", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #224 = SMULWB
+ { 225, 5, 1, 115, "SMULWT", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #225 = SMULWT
+ { 226, 5, 0, 120, "STM", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|4|(3<<4)|(10<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #226 = STM
+ { 227, 6, 0, 121, "STR", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|2|(3<<4)|(7<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #227 = STR
+ { 228, 6, 0, 121, "STRB", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|2|(3<<4)|(7<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #228 = STRB
+ { 229, 7, 1, 122, "STRBT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|2|(3<<4)|(2<<7)|(7<<9), NULL, NULL, NULL, OperandInfo47 }, // Inst #229 = STRBT
+ { 230, 7, 1, 122, "STRB_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|2|(3<<4)|(2<<7)|(7<<9), NULL, NULL, NULL, OperandInfo47 }, // Inst #230 = STRB_POST
+ { 231, 7, 1, 122, "STRB_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|2|(3<<4)|(1<<7)|(7<<9), NULL, NULL, NULL, OperandInfo47 }, // Inst #231 = STRB_PRE
+ { 232, 7, 0, 121, "STRD", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|3|(3<<4)|(9<<9), NULL, NULL, NULL, OperandInfo10 }, // Inst #232 = STRD
+ { 233, 5, 1, 128, "STREX", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo48 }, // Inst #233 = STREX
+ { 234, 5, 1, 128, "STREXB", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo48 }, // Inst #234 = STREXB
+ { 235, 6, 1, 128, "STREXD", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo49 }, // Inst #235 = STREXD
+ { 236, 5, 1, 128, "STREXH", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo48 }, // Inst #236 = STREXH
+ { 237, 6, 0, 121, "STRH", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|3|(3<<4)|(9<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #237 = STRH
+ { 238, 7, 1, 122, "STRH_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|3|(3<<4)|(2<<7)|(9<<9), NULL, NULL, NULL, OperandInfo47 }, // Inst #238 = STRH_POST
+ { 239, 7, 1, 122, "STRH_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|3|(3<<4)|(1<<7)|(9<<9), NULL, NULL, NULL, OperandInfo47 }, // Inst #239 = STRH_PRE
+ { 240, 7, 1, 122, "STRT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|2|(3<<4)|(2<<7)|(7<<9), NULL, NULL, NULL, OperandInfo47 }, // Inst #240 = STRT
+ { 241, 7, 1, 122, "STR_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|2|(3<<4)|(2<<7)|(7<<9), NULL, NULL, NULL, OperandInfo47 }, // Inst #241 = STR_POST
+ { 242, 7, 1, 122, "STR_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|2|(3<<4)|(1<<7)|(7<<9), NULL, NULL, NULL, OperandInfo47 }, // Inst #242 = STR_PRE
+ { 243, 5, 1, 88, "SUBSri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #243 = SUBSri
+ { 244, 5, 1, 89, "SUBSrr", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #244 = SUBSrr
+ { 245, 7, 1, 91, "SUBSrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #245 = SUBSrs
+ { 246, 6, 1, 88, "SUBri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #246 = SUBri
+ { 247, 6, 1, 89, "SUBrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #247 = SUBrr
+ { 248, 8, 1, 91, "SUBrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), NULL, NULL, NULL, OperandInfo7 }, // Inst #248 = SUBrs
+ { 249, 3, 0, 0, "SVC", 0|(1<<TID::Call)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #249 = SVC
+ { 250, 5, 1, 128, "SWP", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #250 = SWP
+ { 251, 5, 1, 128, "SWPB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #251 = SWPB
+ { 252, 5, 1, 89, "SXTABrr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #252 = SXTABrr
+ { 253, 6, 1, 90, "SXTABrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #253 = SXTABrr_rot
+ { 254, 5, 1, 89, "SXTAHrr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #254 = SXTAHrr
+ { 255, 6, 1, 90, "SXTAHrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #255 = SXTAHrr_rot
+ { 256, 4, 1, 125, "SXTBr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #256 = SXTBr
+ { 257, 5, 1, 126, "SXTBr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #257 = SXTBr_rot
+ { 258, 4, 1, 125, "SXTHr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #258 = SXTHr
+ { 259, 5, 1, 126, "SXTHr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #259 = SXTHr_rot
+ { 260, 4, 0, 97, "TEQri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 }, // Inst #260 = TEQri
+ { 261, 4, 0, 98, "TEQrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo24 }, // Inst #261 = TEQrr
+ { 262, 6, 0, 100, "TEQrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo26 }, // Inst #262 = TEQrs
+ { 263, 0, 0, 0, "TPsoft", 0|(1<<TID::Call), 0|(3<<4)|(2<<9), NULL, ImplicitList7, Barriers1, 0 }, // Inst #263 = TPsoft
+ { 264, 2, 0, 128, "TRAP", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #264 = TRAP
+ { 265, 4, 0, 97, "TSTri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 }, // Inst #265 = TSTri
+ { 266, 4, 0, 98, "TSTrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo24 }, // Inst #266 = TSTrr
+ { 267, 6, 0, 100, "TSTrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo26 }, // Inst #267 = TSTrs
+ { 268, 6, 1, 88, "UBFX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo46 }, // Inst #268 = UBFX
+ { 269, 6, 2, 110, "UMAAL", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #269 = UMAAL
+ { 270, 7, 2, 110, "UMLAL", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo39 }, // Inst #270 = UMLAL
+ { 271, 7, 2, 117, "UMULL", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo39 }, // Inst #271 = UMULL
+ { 272, 5, 1, 89, "UQADD16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #272 = UQADD16
+ { 273, 5, 1, 89, "UQADD8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #273 = UQADD8
+ { 274, 5, 1, 89, "UQASX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #274 = UQASX
+ { 275, 5, 1, 89, "UQSAX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #275 = UQSAX
+ { 276, 5, 1, 89, "UQSUB16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #276 = UQSUB16
+ { 277, 5, 1, 89, "UQSUB8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #277 = UQSUB8
+ { 278, 5, 1, 89, "UXTABrr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #278 = UXTABrr
+ { 279, 6, 1, 90, "UXTABrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #279 = UXTABrr_rot
+ { 280, 5, 1, 89, "UXTAHrr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #280 = UXTAHrr
+ { 281, 6, 1, 90, "UXTAHrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #281 = UXTAHrr_rot
+ { 282, 4, 1, 125, "UXTB16r", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #282 = UXTB16r
+ { 283, 5, 1, 126, "UXTB16r_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #283 = UXTB16r_rot
+ { 284, 4, 1, 125, "UXTBr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #284 = UXTBr
+ { 285, 5, 1, 126, "UXTBr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #285 = UXTBr_rot
+ { 286, 4, 1, 125, "UXTHr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #286 = UXTHr
+ { 287, 5, 1, 126, "UXTHr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #287 = UXTHr_rot
+ { 288, 6, 1, 17, "VABALsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #288 = VABALsv2i64
+ { 289, 6, 1, 17, "VABALsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #289 = VABALsv4i32
+ { 290, 6, 1, 17, "VABALsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #290 = VABALsv8i16
+ { 291, 6, 1, 17, "VABALuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #291 = VABALuv2i64
+ { 292, 6, 1, 17, "VABALuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #292 = VABALuv4i32
+ { 293, 6, 1, 17, "VABALuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #293 = VABALuv8i16
+ { 294, 6, 1, 18, "VABAsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #294 = VABAsv16i8
+ { 295, 6, 1, 19, "VABAsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #295 = VABAsv2i32
+ { 296, 6, 1, 17, "VABAsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #296 = VABAsv4i16
+ { 297, 6, 1, 20, "VABAsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #297 = VABAsv4i32
+ { 298, 6, 1, 18, "VABAsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #298 = VABAsv8i16
+ { 299, 6, 1, 17, "VABAsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #299 = VABAsv8i8
+ { 300, 6, 1, 18, "VABAuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #300 = VABAuv16i8
+ { 301, 6, 1, 19, "VABAuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #301 = VABAuv2i32
+ { 302, 6, 1, 17, "VABAuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #302 = VABAuv4i16
+ { 303, 6, 1, 20, "VABAuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #303 = VABAuv4i32
+ { 304, 6, 1, 18, "VABAuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #304 = VABAuv8i16
+ { 305, 6, 1, 17, "VABAuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #305 = VABAuv8i8
+ { 306, 5, 1, 4, "VABDLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #306 = VABDLsv2i64
+ { 307, 5, 1, 4, "VABDLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #307 = VABDLsv4i32
+ { 308, 5, 1, 4, "VABDLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #308 = VABDLsv8i16
+ { 309, 5, 1, 4, "VABDLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #309 = VABDLuv2i64
+ { 310, 5, 1, 4, "VABDLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #310 = VABDLuv4i32
+ { 311, 5, 1, 4, "VABDLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #311 = VABDLuv8i16
+ { 312, 5, 1, 1, "VABDfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #312 = VABDfd
+ { 313, 5, 1, 2, "VABDfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #313 = VABDfq
+ { 314, 5, 1, 4, "VABDsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #314 = VABDsv16i8
+ { 315, 5, 1, 3, "VABDsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #315 = VABDsv2i32
+ { 316, 5, 1, 3, "VABDsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #316 = VABDsv4i16
+ { 317, 5, 1, 4, "VABDsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #317 = VABDsv4i32
+ { 318, 5, 1, 4, "VABDsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #318 = VABDsv8i16
+ { 319, 5, 1, 3, "VABDsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #319 = VABDsv8i8
+ { 320, 5, 1, 4, "VABDuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #320 = VABDuv16i8
+ { 321, 5, 1, 3, "VABDuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #321 = VABDuv2i32
+ { 322, 5, 1, 3, "VABDuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #322 = VABDuv4i16
+ { 323, 5, 1, 4, "VABDuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #323 = VABDuv4i32
+ { 324, 5, 1, 4, "VABDuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #324 = VABDuv8i16
+ { 325, 5, 1, 3, "VABDuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #325 = VABDuv8i8
+ { 326, 4, 1, 87, "VABSD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #326 = VABSD
+ { 327, 4, 1, 86, "VABSS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo58 }, // Inst #327 = VABSS
+ { 328, 4, 1, 57, "VABSfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #328 = VABSfd
+ { 329, 4, 1, 57, "VABSfd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #329 = VABSfd_sfp
+ { 330, 4, 1, 58, "VABSfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #330 = VABSfq
+ { 331, 4, 1, 60, "VABSv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #331 = VABSv16i8
+ { 332, 4, 1, 59, "VABSv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #332 = VABSv2i32
+ { 333, 4, 1, 59, "VABSv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #333 = VABSv4i16
+ { 334, 4, 1, 60, "VABSv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #334 = VABSv4i32
+ { 335, 4, 1, 60, "VABSv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #335 = VABSv8i16
+ { 336, 4, 1, 59, "VABSv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #336 = VABSv8i8
+ { 337, 5, 1, 1, "VACGEd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #337 = VACGEd
+ { 338, 5, 1, 2, "VACGEq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #338 = VACGEq
+ { 339, 5, 1, 1, "VACGTd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #339 = VACGTd
+ { 340, 5, 1, 2, "VACGTq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #340 = VACGTq
+ { 341, 5, 1, 62, "VADDD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #341 = VADDD
+ { 342, 5, 1, 3, "VADDHNv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #342 = VADDHNv2i32
+ { 343, 5, 1, 3, "VADDHNv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #343 = VADDHNv4i16
+ { 344, 5, 1, 3, "VADDHNv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #344 = VADDHNv8i8
+ { 345, 5, 1, 44, "VADDLsv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #345 = VADDLsv2i64
+ { 346, 5, 1, 44, "VADDLsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #346 = VADDLsv4i32
+ { 347, 5, 1, 44, "VADDLsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #347 = VADDLsv8i16
+ { 348, 5, 1, 44, "VADDLuv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #348 = VADDLuv2i64
+ { 349, 5, 1, 44, "VADDLuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #349 = VADDLuv4i32
+ { 350, 5, 1, 44, "VADDLuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #350 = VADDLuv8i16
+ { 351, 5, 1, 61, "VADDS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #351 = VADDS
+ { 352, 5, 1, 47, "VADDWsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #352 = VADDWsv2i64
+ { 353, 5, 1, 47, "VADDWsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #353 = VADDWsv4i32
+ { 354, 5, 1, 47, "VADDWsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #354 = VADDWsv8i16
+ { 355, 5, 1, 47, "VADDWuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #355 = VADDWuv2i64
+ { 356, 5, 1, 47, "VADDWuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #356 = VADDWuv4i32
+ { 357, 5, 1, 47, "VADDWuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #357 = VADDWuv8i16
+ { 358, 5, 1, 1, "VADDfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #358 = VADDfd
+ { 359, 5, 1, 1, "VADDfd_sfp", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #359 = VADDfd_sfp
+ { 360, 5, 1, 2, "VADDfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #360 = VADDfq
+ { 361, 5, 1, 6, "VADDv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #361 = VADDv16i8
+ { 362, 5, 1, 5, "VADDv1i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #362 = VADDv1i64
+ { 363, 5, 1, 5, "VADDv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #363 = VADDv2i32
+ { 364, 5, 1, 6, "VADDv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #364 = VADDv2i64
+ { 365, 5, 1, 5, "VADDv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #365 = VADDv4i16
+ { 366, 5, 1, 6, "VADDv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #366 = VADDv4i32
+ { 367, 5, 1, 6, "VADDv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #367 = VADDv8i16
+ { 368, 5, 1, 5, "VADDv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #368 = VADDv8i8
+ { 369, 5, 1, 5, "VANDd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #369 = VANDd
+ { 370, 5, 1, 6, "VANDq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #370 = VANDq
+ { 371, 5, 1, 5, "VBICd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #371 = VBICd
+ { 372, 5, 1, 6, "VBICq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #372 = VBICq
+ { 373, 6, 1, 5, "VBIFd", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #373 = VBIFd
+ { 374, 6, 1, 6, "VBIFq", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #374 = VBIFq
+ { 375, 6, 1, 5, "VBITd", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #375 = VBITd
+ { 376, 6, 1, 6, "VBITq", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #376 = VBITq
+ { 377, 6, 1, 7, "VBSLd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #377 = VBSLd
+ { 378, 6, 1, 8, "VBSLq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #378 = VBSLq
+ { 379, 5, 1, 1, "VCEQfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #379 = VCEQfd
+ { 380, 5, 1, 2, "VCEQfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #380 = VCEQfq
+ { 381, 5, 1, 4, "VCEQv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #381 = VCEQv16i8
+ { 382, 5, 1, 3, "VCEQv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #382 = VCEQv2i32
+ { 383, 5, 1, 3, "VCEQv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #383 = VCEQv4i16
+ { 384, 5, 1, 4, "VCEQv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #384 = VCEQv4i32
+ { 385, 5, 1, 4, "VCEQv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #385 = VCEQv8i16
+ { 386, 5, 1, 3, "VCEQv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #386 = VCEQv8i8
+ { 387, 5, 1, 1, "VCGEfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #387 = VCGEfd
+ { 388, 5, 1, 2, "VCGEfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #388 = VCGEfq
+ { 389, 5, 1, 4, "VCGEsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #389 = VCGEsv16i8
+ { 390, 5, 1, 3, "VCGEsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #390 = VCGEsv2i32
+ { 391, 5, 1, 3, "VCGEsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #391 = VCGEsv4i16
+ { 392, 5, 1, 4, "VCGEsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #392 = VCGEsv4i32
+ { 393, 5, 1, 4, "VCGEsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #393 = VCGEsv8i16
+ { 394, 5, 1, 3, "VCGEsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #394 = VCGEsv8i8
+ { 395, 5, 1, 4, "VCGEuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #395 = VCGEuv16i8
+ { 396, 5, 1, 3, "VCGEuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #396 = VCGEuv2i32
+ { 397, 5, 1, 3, "VCGEuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #397 = VCGEuv4i16
+ { 398, 5, 1, 4, "VCGEuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #398 = VCGEuv4i32
+ { 399, 5, 1, 4, "VCGEuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #399 = VCGEuv8i16
+ { 400, 5, 1, 3, "VCGEuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #400 = VCGEuv8i8
+ { 401, 5, 1, 1, "VCGTfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #401 = VCGTfd
+ { 402, 5, 1, 2, "VCGTfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #402 = VCGTfq
+ { 403, 5, 1, 4, "VCGTsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #403 = VCGTsv16i8
+ { 404, 5, 1, 3, "VCGTsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #404 = VCGTsv2i32
+ { 405, 5, 1, 3, "VCGTsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #405 = VCGTsv4i16
+ { 406, 5, 1, 4, "VCGTsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #406 = VCGTsv4i32
+ { 407, 5, 1, 4, "VCGTsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #407 = VCGTsv8i16
+ { 408, 5, 1, 3, "VCGTsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #408 = VCGTsv8i8
+ { 409, 5, 1, 4, "VCGTuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #409 = VCGTuv16i8
+ { 410, 5, 1, 3, "VCGTuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #410 = VCGTuv2i32
+ { 411, 5, 1, 3, "VCGTuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #411 = VCGTuv4i16
+ { 412, 5, 1, 4, "VCGTuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #412 = VCGTuv4i32
+ { 413, 5, 1, 4, "VCGTuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #413 = VCGTuv8i16
+ { 414, 5, 1, 3, "VCGTuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #414 = VCGTuv8i8
+ { 415, 4, 1, 8, "VCLSv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #415 = VCLSv16i8
+ { 416, 4, 1, 7, "VCLSv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #416 = VCLSv2i32
+ { 417, 4, 1, 7, "VCLSv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #417 = VCLSv4i16
+ { 418, 4, 1, 8, "VCLSv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #418 = VCLSv4i32
+ { 419, 4, 1, 8, "VCLSv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #419 = VCLSv8i16
+ { 420, 4, 1, 7, "VCLSv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #420 = VCLSv8i8
+ { 421, 4, 1, 8, "VCLZv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #421 = VCLZv16i8
+ { 422, 4, 1, 7, "VCLZv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #422 = VCLZv2i32
+ { 423, 4, 1, 7, "VCLZv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #423 = VCLZv4i16
+ { 424, 4, 1, 8, "VCLZv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #424 = VCLZv4i32
+ { 425, 4, 1, 8, "VCLZv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #425 = VCLZv8i16
+ { 426, 4, 1, 7, "VCLZv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #426 = VCLZv8i8
+ { 427, 4, 0, 64, "VCMPD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo57 }, // Inst #427 = VCMPD
+ { 428, 4, 0, 64, "VCMPED", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo57 }, // Inst #428 = VCMPED
+ { 429, 4, 0, 63, "VCMPES", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo58 }, // Inst #429 = VCMPES
+ { 430, 3, 0, 64, "VCMPEZD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo65 }, // Inst #430 = VCMPEZD
+ { 431, 3, 0, 63, "VCMPEZS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo66 }, // Inst #431 = VCMPEZS
+ { 432, 4, 0, 63, "VCMPS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo58 }, // Inst #432 = VCMPS
+ { 433, 3, 0, 64, "VCMPZD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo65 }, // Inst #433 = VCMPZD
+ { 434, 3, 0, 63, "VCMPZS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo66 }, // Inst #434 = VCMPZS
+ { 435, 4, 1, 7, "VCNTd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #435 = VCNTd
+ { 436, 4, 1, 8, "VCNTq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #436 = VCNTq
+ { 437, 4, 1, 66, "VCVTBHS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo58 }, // Inst #437 = VCVTBHS
+ { 438, 4, 1, 66, "VCVTBSH", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo58 }, // Inst #438 = VCVTBSH
+ { 439, 4, 1, 66, "VCVTDS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo67 }, // Inst #439 = VCVTDS
+ { 440, 4, 1, 69, "VCVTSD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #440 = VCVTSD
+ { 441, 4, 1, 66, "VCVTTHS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo58 }, // Inst #441 = VCVTTHS
+ { 442, 4, 1, 66, "VCVTTSH", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo58 }, // Inst #442 = VCVTTSH
+ { 443, 4, 1, 57, "VCVTf2sd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #443 = VCVTf2sd
+ { 444, 4, 1, 57, "VCVTf2sd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #444 = VCVTf2sd_sfp
+ { 445, 4, 1, 58, "VCVTf2sq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #445 = VCVTf2sq
+ { 446, 4, 1, 57, "VCVTf2ud", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #446 = VCVTf2ud
+ { 447, 4, 1, 57, "VCVTf2ud_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #447 = VCVTf2ud_sfp
+ { 448, 4, 1, 58, "VCVTf2uq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #448 = VCVTf2uq
+ { 449, 5, 1, 57, "VCVTf2xsd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #449 = VCVTf2xsd
+ { 450, 5, 1, 58, "VCVTf2xsq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #450 = VCVTf2xsq
+ { 451, 5, 1, 57, "VCVTf2xud", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #451 = VCVTf2xud
+ { 452, 5, 1, 58, "VCVTf2xuq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #452 = VCVTf2xuq
+ { 453, 4, 1, 57, "VCVTs2fd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #453 = VCVTs2fd
+ { 454, 4, 1, 57, "VCVTs2fd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #454 = VCVTs2fd_sfp
+ { 455, 4, 1, 58, "VCVTs2fq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #455 = VCVTs2fq
+ { 456, 4, 1, 57, "VCVTu2fd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #456 = VCVTu2fd
+ { 457, 4, 1, 57, "VCVTu2fd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #457 = VCVTu2fd_sfp
+ { 458, 4, 1, 58, "VCVTu2fq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #458 = VCVTu2fq
+ { 459, 5, 1, 57, "VCVTxs2fd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #459 = VCVTxs2fd
+ { 460, 5, 1, 58, "VCVTxs2fq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #460 = VCVTxs2fq
+ { 461, 5, 1, 57, "VCVTxu2fd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #461 = VCVTxu2fd
+ { 462, 5, 1, 58, "VCVTxu2fq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #462 = VCVTxu2fq
+ { 463, 5, 1, 72, "VDIVD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #463 = VDIVD
+ { 464, 5, 1, 71, "VDIVS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #464 = VDIVS
+ { 465, 4, 1, 24, "VDUP16d", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo71 }, // Inst #465 = VDUP16d
+ { 466, 4, 1, 24, "VDUP16q", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo72 }, // Inst #466 = VDUP16q
+ { 467, 4, 1, 24, "VDUP32d", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo71 }, // Inst #467 = VDUP32d
+ { 468, 4, 1, 24, "VDUP32q", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo72 }, // Inst #468 = VDUP32q
+ { 469, 4, 1, 24, "VDUP8d", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo71 }, // Inst #469 = VDUP8d
+ { 470, 4, 1, 24, "VDUP8q", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo72 }, // Inst #470 = VDUP8q
+ { 471, 5, 1, 21, "VDUPLN16d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #471 = VDUPLN16d
+ { 472, 5, 1, 21, "VDUPLN16q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo73 }, // Inst #472 = VDUPLN16q
+ { 473, 5, 1, 21, "VDUPLN32d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #473 = VDUPLN32d
+ { 474, 5, 1, 21, "VDUPLN32q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo73 }, // Inst #474 = VDUPLN32q
+ { 475, 5, 1, 21, "VDUPLN8d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #475 = VDUPLN8d
+ { 476, 5, 1, 21, "VDUPLN8q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo73 }, // Inst #476 = VDUPLN8q
+ { 477, 5, 1, 21, "VDUPLNfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #477 = VDUPLNfd
+ { 478, 5, 1, 21, "VDUPLNfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo73 }, // Inst #478 = VDUPLNfq
+ { 479, 4, 1, 24, "VDUPfd", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo71 }, // Inst #479 = VDUPfd
+ { 480, 4, 1, 21, "VDUPfdf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo67 }, // Inst #480 = VDUPfdf
+ { 481, 4, 1, 24, "VDUPfq", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo72 }, // Inst #481 = VDUPfq
+ { 482, 4, 1, 21, "VDUPfqf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo74 }, // Inst #482 = VDUPfqf
+ { 483, 5, 1, 5, "VEORd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #483 = VEORd
+ { 484, 5, 1, 6, "VEORq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #484 = VEORq
+ { 485, 6, 1, 9, "VEXTd16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo75 }, // Inst #485 = VEXTd16
+ { 486, 6, 1, 9, "VEXTd32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo75 }, // Inst #486 = VEXTd32
+ { 487, 6, 1, 9, "VEXTd8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo75 }, // Inst #487 = VEXTd8
+ { 488, 6, 1, 9, "VEXTdf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo75 }, // Inst #488 = VEXTdf
+ { 489, 6, 1, 10, "VEXTq16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo76 }, // Inst #489 = VEXTq16
+ { 490, 6, 1, 10, "VEXTq32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo76 }, // Inst #490 = VEXTq32
+ { 491, 6, 1, 10, "VEXTq8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo76 }, // Inst #491 = VEXTq8
+ { 492, 6, 1, 10, "VEXTqf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo76 }, // Inst #492 = VEXTqf
+ { 493, 5, 1, 28, "VGETLNi32", 0|(1<<TID::Predicable), 0|(3<<4)|(25<<9), NULL, NULL, NULL, OperandInfo77 }, // Inst #493 = VGETLNi32
+ { 494, 5, 1, 28, "VGETLNs16", 0|(1<<TID::Predicable), 0|(3<<4)|(25<<9), NULL, NULL, NULL, OperandInfo77 }, // Inst #494 = VGETLNs16
+ { 495, 5, 1, 28, "VGETLNs8", 0|(1<<TID::Predicable), 0|(3<<4)|(25<<9), NULL, NULL, NULL, OperandInfo77 }, // Inst #495 = VGETLNs8
+ { 496, 5, 1, 28, "VGETLNu16", 0|(1<<TID::Predicable), 0|(3<<4)|(25<<9), NULL, NULL, NULL, OperandInfo77 }, // Inst #496 = VGETLNu16
+ { 497, 5, 1, 28, "VGETLNu8", 0|(1<<TID::Predicable), 0|(3<<4)|(25<<9), NULL, NULL, NULL, OperandInfo77 }, // Inst #497 = VGETLNu8
+ { 498, 5, 1, 4, "VHADDsv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #498 = VHADDsv16i8
+ { 499, 5, 1, 3, "VHADDsv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #499 = VHADDsv2i32
+ { 500, 5, 1, 3, "VHADDsv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #500 = VHADDsv4i16
+ { 501, 5, 1, 4, "VHADDsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #501 = VHADDsv4i32
+ { 502, 5, 1, 4, "VHADDsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #502 = VHADDsv8i16
+ { 503, 5, 1, 3, "VHADDsv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #503 = VHADDsv8i8
+ { 504, 5, 1, 4, "VHADDuv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #504 = VHADDuv16i8
+ { 505, 5, 1, 3, "VHADDuv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #505 = VHADDuv2i32
+ { 506, 5, 1, 3, "VHADDuv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #506 = VHADDuv4i16
+ { 507, 5, 1, 4, "VHADDuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #507 = VHADDuv4i32
+ { 508, 5, 1, 4, "VHADDuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #508 = VHADDuv8i16
+ { 509, 5, 1, 3, "VHADDuv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #509 = VHADDuv8i8
+ { 510, 5, 1, 4, "VHSUBsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #510 = VHSUBsv16i8
+ { 511, 5, 1, 3, "VHSUBsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #511 = VHSUBsv2i32
+ { 512, 5, 1, 3, "VHSUBsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #512 = VHSUBsv4i16
+ { 513, 5, 1, 4, "VHSUBsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #513 = VHSUBsv4i32
+ { 514, 5, 1, 4, "VHSUBsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #514 = VHSUBsv8i16
+ { 515, 5, 1, 3, "VHSUBsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #515 = VHSUBsv8i8
+ { 516, 5, 1, 4, "VHSUBuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #516 = VHSUBuv16i8
+ { 517, 5, 1, 3, "VHSUBuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #517 = VHSUBuv2i32
+ { 518, 5, 1, 3, "VHSUBuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #518 = VHSUBuv4i16
+ { 519, 5, 1, 4, "VHSUBuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #519 = VHSUBuv4i32
+ { 520, 5, 1, 4, "VHSUBuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #520 = VHSUBuv8i16
+ { 521, 5, 1, 3, "VHSUBuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #521 = VHSUBuv8i8
+ { 522, 7, 1, 11, "VLD1d16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #522 = VLD1d16
+ { 523, 7, 1, 11, "VLD1d32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #523 = VLD1d32
+ { 524, 7, 1, 11, "VLD1d64", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #524 = VLD1d64
+ { 525, 7, 1, 11, "VLD1d8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #525 = VLD1d8
+ { 526, 7, 1, 11, "VLD1df", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #526 = VLD1df
+ { 527, 7, 1, 11, "VLD1q16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo79 }, // Inst #527 = VLD1q16
+ { 528, 7, 1, 11, "VLD1q32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo79 }, // Inst #528 = VLD1q32
+ { 529, 7, 1, 11, "VLD1q64", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo79 }, // Inst #529 = VLD1q64
+ { 530, 7, 1, 11, "VLD1q8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo79 }, // Inst #530 = VLD1q8
+ { 531, 7, 1, 11, "VLD1qf", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo79 }, // Inst #531 = VLD1qf
+ { 532, 11, 2, 12, "VLD2LNd16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo80 }, // Inst #532 = VLD2LNd16
+ { 533, 11, 2, 12, "VLD2LNd32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo80 }, // Inst #533 = VLD2LNd32
+ { 534, 11, 2, 12, "VLD2LNd8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo80 }, // Inst #534 = VLD2LNd8
+ { 535, 11, 2, 12, "VLD2LNq16a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo80 }, // Inst #535 = VLD2LNq16a
+ { 536, 11, 2, 12, "VLD2LNq16b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo80 }, // Inst #536 = VLD2LNq16b
+ { 537, 11, 2, 12, "VLD2LNq32a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo80 }, // Inst #537 = VLD2LNq32a
+ { 538, 11, 2, 12, "VLD2LNq32b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo80 }, // Inst #538 = VLD2LNq32b
+ { 539, 8, 2, 12, "VLD2d16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #539 = VLD2d16
+ { 540, 8, 2, 12, "VLD2d32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #540 = VLD2d32
+ { 541, 8, 2, 11, "VLD2d64", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #541 = VLD2d64
+ { 542, 8, 2, 12, "VLD2d8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #542 = VLD2d8
+ { 543, 10, 4, 12, "VLD2q16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo82 }, // Inst #543 = VLD2q16
+ { 544, 10, 4, 12, "VLD2q32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo82 }, // Inst #544 = VLD2q32
+ { 545, 10, 4, 12, "VLD2q8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo82 }, // Inst #545 = VLD2q8
+ { 546, 13, 3, 13, "VLD3LNd16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo83 }, // Inst #546 = VLD3LNd16
+ { 547, 13, 3, 13, "VLD3LNd32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo83 }, // Inst #547 = VLD3LNd32
+ { 548, 13, 3, 13, "VLD3LNd8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo83 }, // Inst #548 = VLD3LNd8
+ { 549, 13, 3, 13, "VLD3LNq16a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo83 }, // Inst #549 = VLD3LNq16a
+ { 550, 13, 3, 13, "VLD3LNq16b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo83 }, // Inst #550 = VLD3LNq16b
+ { 551, 13, 3, 13, "VLD3LNq32a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo83 }, // Inst #551 = VLD3LNq32a
+ { 552, 13, 3, 13, "VLD3LNq32b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo83 }, // Inst #552 = VLD3LNq32b
+ { 553, 9, 3, 13, "VLD3d16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo84 }, // Inst #553 = VLD3d16
+ { 554, 9, 3, 13, "VLD3d32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo84 }, // Inst #554 = VLD3d32
+ { 555, 9, 3, 11, "VLD3d64", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo84 }, // Inst #555 = VLD3d64
+ { 556, 9, 3, 13, "VLD3d8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo84 }, // Inst #556 = VLD3d8
+ { 557, 10, 4, 13, "VLD3q16a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo85 }, // Inst #557 = VLD3q16a
+ { 558, 10, 4, 13, "VLD3q16b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo85 }, // Inst #558 = VLD3q16b
+ { 559, 10, 4, 13, "VLD3q32a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo85 }, // Inst #559 = VLD3q32a
+ { 560, 10, 4, 13, "VLD3q32b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo85 }, // Inst #560 = VLD3q32b
+ { 561, 10, 4, 13, "VLD3q8a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo85 }, // Inst #561 = VLD3q8a
+ { 562, 10, 4, 13, "VLD3q8b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo85 }, // Inst #562 = VLD3q8b
+ { 563, 15, 4, 14, "VLD4LNd16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo86 }, // Inst #563 = VLD4LNd16
+ { 564, 15, 4, 14, "VLD4LNd32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo86 }, // Inst #564 = VLD4LNd32
+ { 565, 15, 4, 14, "VLD4LNd8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo86 }, // Inst #565 = VLD4LNd8
+ { 566, 15, 4, 14, "VLD4LNq16a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo86 }, // Inst #566 = VLD4LNq16a
+ { 567, 15, 4, 14, "VLD4LNq16b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo86 }, // Inst #567 = VLD4LNq16b
+ { 568, 15, 4, 14, "VLD4LNq32a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo86 }, // Inst #568 = VLD4LNq32a
+ { 569, 15, 4, 14, "VLD4LNq32b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo86 }, // Inst #569 = VLD4LNq32b
+ { 570, 10, 4, 14, "VLD4d16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo82 }, // Inst #570 = VLD4d16
+ { 571, 10, 4, 14, "VLD4d32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo82 }, // Inst #571 = VLD4d32
+ { 572, 10, 4, 11, "VLD4d64", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo82 }, // Inst #572 = VLD4d64
+ { 573, 10, 4, 14, "VLD4d8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo82 }, // Inst #573 = VLD4d8
+ { 574, 11, 5, 14, "VLD4q16a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 }, // Inst #574 = VLD4q16a
+ { 575, 11, 5, 14, "VLD4q16b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 }, // Inst #575 = VLD4q16b
+ { 576, 11, 5, 14, "VLD4q32a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 }, // Inst #576 = VLD4q32a
+ { 577, 11, 5, 14, "VLD4q32b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 }, // Inst #577 = VLD4q32b
+ { 578, 11, 5, 14, "VLD4q8a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 }, // Inst #578 = VLD4q8a
+ { 579, 11, 5, 14, "VLD4q8b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 }, // Inst #579 = VLD4q8b
+ { 580, 5, 0, 75, "VLDMD", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|5|(3<<4)|(21<<9)|(3<<17), NULL, NULL, NULL, OperandInfo32 }, // Inst #580 = VLDMD
+ { 581, 5, 0, 75, "VLDMS", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|5|(3<<4)|(21<<9)|(1<<17), NULL, NULL, NULL, OperandInfo32 }, // Inst #581 = VLDMS
+ { 582, 5, 1, 74, "VLDRD", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|5|(3<<4)|(20<<9)|(3<<17), NULL, NULL, NULL, OperandInfo88 }, // Inst #582 = VLDRD
+ { 583, 5, 1, 75, "VLDRQ", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|4|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo89 }, // Inst #583 = VLDRQ
+ { 584, 5, 1, 73, "VLDRS", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|5|(3<<4)|(20<<9)|(1<<17), NULL, NULL, NULL, OperandInfo90 }, // Inst #584 = VLDRS
+ { 585, 5, 1, 1, "VMAXfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #585 = VMAXfd
+ { 586, 5, 1, 2, "VMAXfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #586 = VMAXfq
+ { 587, 5, 1, 4, "VMAXsv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #587 = VMAXsv16i8
+ { 588, 5, 1, 3, "VMAXsv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #588 = VMAXsv2i32
+ { 589, 5, 1, 3, "VMAXsv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #589 = VMAXsv4i16
+ { 590, 5, 1, 4, "VMAXsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #590 = VMAXsv4i32
+ { 591, 5, 1, 4, "VMAXsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #591 = VMAXsv8i16
+ { 592, 5, 1, 3, "VMAXsv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #592 = VMAXsv8i8
+ { 593, 5, 1, 4, "VMAXuv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #593 = VMAXuv16i8
+ { 594, 5, 1, 3, "VMAXuv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #594 = VMAXuv2i32
+ { 595, 5, 1, 3, "VMAXuv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #595 = VMAXuv4i16
+ { 596, 5, 1, 4, "VMAXuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #596 = VMAXuv4i32
+ { 597, 5, 1, 4, "VMAXuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #597 = VMAXuv8i16
+ { 598, 5, 1, 3, "VMAXuv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #598 = VMAXuv8i8
+ { 599, 5, 1, 1, "VMINfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #599 = VMINfd
+ { 600, 5, 1, 2, "VMINfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #600 = VMINfq
+ { 601, 5, 1, 4, "VMINsv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #601 = VMINsv16i8
+ { 602, 5, 1, 3, "VMINsv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #602 = VMINsv2i32
+ { 603, 5, 1, 3, "VMINsv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #603 = VMINsv4i16
+ { 604, 5, 1, 4, "VMINsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #604 = VMINsv4i32
+ { 605, 5, 1, 4, "VMINsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #605 = VMINsv8i16
+ { 606, 5, 1, 3, "VMINsv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #606 = VMINsv8i8
+ { 607, 5, 1, 4, "VMINuv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #607 = VMINuv16i8
+ { 608, 5, 1, 3, "VMINuv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #608 = VMINuv2i32
+ { 609, 5, 1, 3, "VMINuv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #609 = VMINuv4i16
+ { 610, 5, 1, 4, "VMINuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #610 = VMINuv4i32
+ { 611, 5, 1, 4, "VMINuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #611 = VMINuv8i16
+ { 612, 5, 1, 3, "VMINuv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #612 = VMINuv8i8
+ { 613, 6, 1, 77, "VMLAD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #613 = VMLAD
+ { 614, 7, 1, 19, "VMLALslsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #614 = VMLALslsv2i32
+ { 615, 7, 1, 17, "VMLALslsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo92 }, // Inst #615 = VMLALslsv4i16
+ { 616, 7, 1, 19, "VMLALsluv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #616 = VMLALsluv2i32
+ { 617, 7, 1, 17, "VMLALsluv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo92 }, // Inst #617 = VMLALsluv4i16
+ { 618, 6, 1, 17, "VMLALsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #618 = VMLALsv2i64
+ { 619, 6, 1, 17, "VMLALsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #619 = VMLALsv4i32
+ { 620, 6, 1, 17, "VMLALsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #620 = VMLALsv8i16
+ { 621, 6, 1, 17, "VMLALuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #621 = VMLALuv2i64
+ { 622, 6, 1, 17, "VMLALuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #622 = VMLALuv4i32
+ { 623, 6, 1, 17, "VMLALuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #623 = VMLALuv8i16
+ { 624, 6, 1, 76, "VMLAS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #624 = VMLAS
+ { 625, 6, 1, 15, "VMLAfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #625 = VMLAfd
+ { 626, 6, 1, 16, "VMLAfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #626 = VMLAfq
+ { 627, 7, 1, 15, "VMLAslfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo94 }, // Inst #627 = VMLAslfd
+ { 628, 7, 1, 16, "VMLAslfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo95 }, // Inst #628 = VMLAslfq
+ { 629, 7, 1, 19, "VMLAslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo94 }, // Inst #629 = VMLAslv2i32
+ { 630, 7, 1, 17, "VMLAslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo96 }, // Inst #630 = VMLAslv4i16
+ { 631, 7, 1, 20, "VMLAslv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo95 }, // Inst #631 = VMLAslv4i32
+ { 632, 7, 1, 18, "VMLAslv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo97 }, // Inst #632 = VMLAslv8i16
+ { 633, 6, 1, 18, "VMLAv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #633 = VMLAv16i8
+ { 634, 6, 1, 19, "VMLAv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #634 = VMLAv2i32
+ { 635, 6, 1, 17, "VMLAv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #635 = VMLAv4i16
+ { 636, 6, 1, 20, "VMLAv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #636 = VMLAv4i32
+ { 637, 6, 1, 18, "VMLAv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #637 = VMLAv8i16
+ { 638, 6, 1, 17, "VMLAv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #638 = VMLAv8i8
+ { 639, 6, 1, 77, "VMLSD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #639 = VMLSD
+ { 640, 7, 1, 19, "VMLSLslsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #640 = VMLSLslsv2i32
+ { 641, 7, 1, 17, "VMLSLslsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo92 }, // Inst #641 = VMLSLslsv4i16
+ { 642, 7, 1, 19, "VMLSLsluv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #642 = VMLSLsluv2i32
+ { 643, 7, 1, 17, "VMLSLsluv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo92 }, // Inst #643 = VMLSLsluv4i16
+ { 644, 6, 1, 17, "VMLSLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #644 = VMLSLsv2i64
+ { 645, 6, 1, 17, "VMLSLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #645 = VMLSLsv4i32
+ { 646, 6, 1, 17, "VMLSLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #646 = VMLSLsv8i16
+ { 647, 6, 1, 17, "VMLSLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #647 = VMLSLuv2i64
+ { 648, 6, 1, 17, "VMLSLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #648 = VMLSLuv4i32
+ { 649, 6, 1, 17, "VMLSLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #649 = VMLSLuv8i16
+ { 650, 6, 1, 76, "VMLSS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #650 = VMLSS
+ { 651, 6, 1, 15, "VMLSfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #651 = VMLSfd
+ { 652, 6, 1, 16, "VMLSfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #652 = VMLSfq
+ { 653, 7, 1, 15, "VMLSslfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo94 }, // Inst #653 = VMLSslfd
+ { 654, 7, 1, 16, "VMLSslfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo95 }, // Inst #654 = VMLSslfq
+ { 655, 7, 1, 19, "VMLSslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo94 }, // Inst #655 = VMLSslv2i32
+ { 656, 7, 1, 17, "VMLSslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo96 }, // Inst #656 = VMLSslv4i16
+ { 657, 7, 1, 20, "VMLSslv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo95 }, // Inst #657 = VMLSslv4i32
+ { 658, 7, 1, 18, "VMLSslv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo97 }, // Inst #658 = VMLSslv8i16
+ { 659, 6, 1, 18, "VMLSv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #659 = VMLSv16i8
+ { 660, 6, 1, 19, "VMLSv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #660 = VMLSv2i32
+ { 661, 6, 1, 17, "VMLSv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #661 = VMLSv4i16
+ { 662, 6, 1, 20, "VMLSv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #662 = VMLSv4i32
+ { 663, 6, 1, 18, "VMLSv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #663 = VMLSv8i16
+ { 664, 6, 1, 17, "VMLSv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #664 = VMLSv8i8
+ { 665, 4, 1, 87, "VMOVD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #665 = VMOVD
+ { 666, 5, 1, 23, "VMOVDRR", 0|(1<<TID::Predicable), 0|(3<<4)|(19<<9)|(1<<17), NULL, NULL, NULL, OperandInfo98 }, // Inst #666 = VMOVDRR
+ { 667, 5, 1, 87, "VMOVDcc", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo99 }, // Inst #667 = VMOVDcc
+ { 668, 4, 1, 21, "VMOVDneon", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #668 = VMOVDneon
+ { 669, 4, 1, 38, "VMOVLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo100 }, // Inst #669 = VMOVLsv2i64
+ { 670, 4, 1, 38, "VMOVLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo100 }, // Inst #670 = VMOVLsv4i32
+ { 671, 4, 1, 38, "VMOVLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo100 }, // Inst #671 = VMOVLsv8i16
+ { 672, 4, 1, 38, "VMOVLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo100 }, // Inst #672 = VMOVLuv2i64
+ { 673, 4, 1, 38, "VMOVLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo100 }, // Inst #673 = VMOVLuv4i32
+ { 674, 4, 1, 38, "VMOVLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo100 }, // Inst #674 = VMOVLuv8i16
+ { 675, 4, 1, 21, "VMOVNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo101 }, // Inst #675 = VMOVNv2i32
+ { 676, 4, 1, 21, "VMOVNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo101 }, // Inst #676 = VMOVNv4i16
+ { 677, 4, 1, 21, "VMOVNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo101 }, // Inst #677 = VMOVNv8i8
+ { 678, 4, 1, 21, "VMOVQ", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #678 = VMOVQ
+ { 679, 5, 2, 22, "VMOVRRD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(17<<9)|(1<<17), NULL, NULL, NULL, OperandInfo102 }, // Inst #679 = VMOVRRD
+ { 680, 6, 2, 22, "VMOVRRS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(17<<9)|(1<<17), NULL, NULL, NULL, OperandInfo103 }, // Inst #680 = VMOVRRS
+ { 681, 4, 1, 28, "VMOVRS", 0|(1<<TID::Predicable), 0|(3<<4)|(16<<9)|(1<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #681 = VMOVRS
+ { 682, 4, 1, 86, "VMOVS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo58 }, // Inst #682 = VMOVS
+ { 683, 4, 1, 24, "VMOVSR", 0|(1<<TID::Predicable), 0|(3<<4)|(18<<9)|(1<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #683 = VMOVSR
+ { 684, 6, 2, 23, "VMOVSRR", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(19<<9)|(1<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #684 = VMOVSRR
+ { 685, 5, 1, 86, "VMOVScc", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #685 = VMOVScc
+ { 686, 4, 1, 26, "VMOVv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #686 = VMOVv16i8
+ { 687, 4, 1, 26, "VMOVv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo28 }, // Inst #687 = VMOVv1i64
+ { 688, 4, 1, 26, "VMOVv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo28 }, // Inst #688 = VMOVv2i32
+ { 689, 4, 1, 26, "VMOVv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #689 = VMOVv2i64
+ { 690, 4, 1, 26, "VMOVv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo28 }, // Inst #690 = VMOVv4i16
+ { 691, 4, 1, 26, "VMOVv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #691 = VMOVv4i32
+ { 692, 4, 1, 26, "VMOVv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #692 = VMOVv8i16
+ { 693, 4, 1, 26, "VMOVv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo28 }, // Inst #693 = VMOVv8i8
+ { 694, 3, 1, 82, "VMRS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(22<<9)|(1<<17), ImplicitList5, NULL, NULL, OperandInfo20 }, // Inst #694 = VMRS
+ { 695, 3, 0, 82, "VMSR", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(22<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo20 }, // Inst #695 = VMSR
+ { 696, 5, 1, 79, "VMULD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #696 = VMULD
+ { 697, 5, 1, 29, "VMULLp", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #697 = VMULLp
+ { 698, 6, 1, 29, "VMULLslsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo109 }, // Inst #698 = VMULLslsv2i32
+ { 699, 6, 1, 29, "VMULLslsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo110 }, // Inst #699 = VMULLslsv4i16
+ { 700, 6, 1, 29, "VMULLsluv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo109 }, // Inst #700 = VMULLsluv2i32
+ { 701, 6, 1, 29, "VMULLsluv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo110 }, // Inst #701 = VMULLsluv4i16
+ { 702, 5, 1, 29, "VMULLsv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #702 = VMULLsv2i64
+ { 703, 5, 1, 29, "VMULLsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #703 = VMULLsv4i32
+ { 704, 5, 1, 29, "VMULLsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #704 = VMULLsv8i16
+ { 705, 5, 1, 29, "VMULLuv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #705 = VMULLuv2i64
+ { 706, 5, 1, 29, "VMULLuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #706 = VMULLuv4i32
+ { 707, 5, 1, 29, "VMULLuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #707 = VMULLuv8i16
+ { 708, 5, 1, 78, "VMULS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #708 = VMULS
+ { 709, 5, 1, 1, "VMULfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #709 = VMULfd
+ { 710, 5, 1, 1, "VMULfd_sfp", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #710 = VMULfd_sfp
+ { 711, 5, 1, 2, "VMULfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #711 = VMULfq
+ { 712, 5, 1, 29, "VMULpd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #712 = VMULpd
+ { 713, 5, 1, 30, "VMULpq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #713 = VMULpq
+ { 714, 6, 1, 1, "VMULslfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo111 }, // Inst #714 = VMULslfd
+ { 715, 6, 1, 2, "VMULslfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo112 }, // Inst #715 = VMULslfq
+ { 716, 6, 1, 31, "VMULslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo111 }, // Inst #716 = VMULslv2i32
+ { 717, 6, 1, 29, "VMULslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo113 }, // Inst #717 = VMULslv4i16
+ { 718, 6, 1, 32, "VMULslv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo112 }, // Inst #718 = VMULslv4i32
+ { 719, 6, 1, 30, "VMULslv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo114 }, // Inst #719 = VMULslv8i16
+ { 720, 5, 1, 30, "VMULv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #720 = VMULv16i8
+ { 721, 5, 1, 31, "VMULv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #721 = VMULv2i32
+ { 722, 5, 1, 29, "VMULv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #722 = VMULv4i16
+ { 723, 5, 1, 32, "VMULv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #723 = VMULv4i32
+ { 724, 5, 1, 30, "VMULv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #724 = VMULv8i16
+ { 725, 5, 1, 29, "VMULv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #725 = VMULv8i8
+ { 726, 4, 1, 44, "VMVNd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #726 = VMVNd
+ { 727, 4, 1, 44, "VMVNq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #727 = VMVNq
+ { 728, 4, 1, 87, "VNEGD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #728 = VNEGD
+ { 729, 5, 1, 87, "VNEGDcc", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo99 }, // Inst #729 = VNEGDcc
+ { 730, 4, 1, 86, "VNEGS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo58 }, // Inst #730 = VNEGS
+ { 731, 5, 1, 86, "VNEGScc", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #731 = VNEGScc
+ { 732, 4, 1, 57, "VNEGf32d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #732 = VNEGf32d
+ { 733, 4, 1, 57, "VNEGf32d_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #733 = VNEGf32d_sfp
+ { 734, 4, 1, 58, "VNEGf32q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #734 = VNEGf32q
+ { 735, 4, 1, 44, "VNEGs16d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #735 = VNEGs16d
+ { 736, 4, 1, 44, "VNEGs16q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #736 = VNEGs16q
+ { 737, 4, 1, 44, "VNEGs32d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #737 = VNEGs32d
+ { 738, 4, 1, 44, "VNEGs32q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #738 = VNEGs32q
+ { 739, 4, 1, 44, "VNEGs8d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #739 = VNEGs8d
+ { 740, 4, 1, 44, "VNEGs8q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #740 = VNEGs8q
+ { 741, 6, 1, 77, "VNMLAD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #741 = VNMLAD
+ { 742, 6, 1, 76, "VNMLAS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #742 = VNMLAS
+ { 743, 6, 1, 77, "VNMLSD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #743 = VNMLSD
+ { 744, 6, 1, 76, "VNMLSS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #744 = VNMLSS
+ { 745, 5, 1, 79, "VNMULD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #745 = VNMULD
+ { 746, 5, 1, 78, "VNMULS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #746 = VNMULS
+ { 747, 5, 1, 5, "VORNd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #747 = VORNd
+ { 748, 5, 1, 6, "VORNq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #748 = VORNq
+ { 749, 5, 1, 5, "VORRd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #749 = VORRd
+ { 750, 5, 1, 6, "VORRq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #750 = VORRq
+ { 751, 5, 1, 34, "VPADALsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo115 }, // Inst #751 = VPADALsv16i8
+ { 752, 5, 1, 33, "VPADALsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo99 }, // Inst #752 = VPADALsv2i32
+ { 753, 5, 1, 33, "VPADALsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo99 }, // Inst #753 = VPADALsv4i16
+ { 754, 5, 1, 34, "VPADALsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo115 }, // Inst #754 = VPADALsv4i32
+ { 755, 5, 1, 34, "VPADALsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo115 }, // Inst #755 = VPADALsv8i16
+ { 756, 5, 1, 33, "VPADALsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo99 }, // Inst #756 = VPADALsv8i8
+ { 757, 5, 1, 34, "VPADALuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo115 }, // Inst #757 = VPADALuv16i8
+ { 758, 5, 1, 33, "VPADALuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo99 }, // Inst #758 = VPADALuv2i32
+ { 759, 5, 1, 33, "VPADALuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo99 }, // Inst #759 = VPADALuv4i16
+ { 760, 5, 1, 34, "VPADALuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo115 }, // Inst #760 = VPADALuv4i32
+ { 761, 5, 1, 34, "VPADALuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo115 }, // Inst #761 = VPADALuv8i16
+ { 762, 5, 1, 33, "VPADALuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo99 }, // Inst #762 = VPADALuv8i8
+ { 763, 4, 1, 44, "VPADDLsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #763 = VPADDLsv16i8
+ { 764, 4, 1, 44, "VPADDLsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #764 = VPADDLsv2i32
+ { 765, 4, 1, 44, "VPADDLsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #765 = VPADDLsv4i16
+ { 766, 4, 1, 44, "VPADDLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #766 = VPADDLsv4i32
+ { 767, 4, 1, 44, "VPADDLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #767 = VPADDLsv8i16
+ { 768, 4, 1, 44, "VPADDLsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #768 = VPADDLsv8i8
+ { 769, 4, 1, 44, "VPADDLuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #769 = VPADDLuv16i8
+ { 770, 4, 1, 44, "VPADDLuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #770 = VPADDLuv2i32
+ { 771, 4, 1, 44, "VPADDLuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #771 = VPADDLuv4i16
+ { 772, 4, 1, 44, "VPADDLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #772 = VPADDLuv4i32
+ { 773, 4, 1, 44, "VPADDLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #773 = VPADDLuv8i16
+ { 774, 4, 1, 44, "VPADDLuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #774 = VPADDLuv8i8
+ { 775, 5, 1, 1, "VPADDf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #775 = VPADDf
+ { 776, 5, 1, 5, "VPADDi16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #776 = VPADDi16
+ { 777, 5, 1, 5, "VPADDi32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #777 = VPADDi32
+ { 778, 5, 1, 5, "VPADDi8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #778 = VPADDi8
+ { 779, 5, 1, 3, "VPMAXf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #779 = VPMAXf
+ { 780, 5, 1, 3, "VPMAXs16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #780 = VPMAXs16
+ { 781, 5, 1, 3, "VPMAXs32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #781 = VPMAXs32
+ { 782, 5, 1, 3, "VPMAXs8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #782 = VPMAXs8
+ { 783, 5, 1, 3, "VPMAXu16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #783 = VPMAXu16
+ { 784, 5, 1, 3, "VPMAXu32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #784 = VPMAXu32
+ { 785, 5, 1, 3, "VPMAXu8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #785 = VPMAXu8
+ { 786, 5, 1, 3, "VPMINf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #786 = VPMINf
+ { 787, 5, 1, 3, "VPMINs16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #787 = VPMINs16
+ { 788, 5, 1, 3, "VPMINs32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #788 = VPMINs32
+ { 789, 5, 1, 3, "VPMINs8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #789 = VPMINs8
+ { 790, 5, 1, 3, "VPMINu16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #790 = VPMINu16
+ { 791, 5, 1, 3, "VPMINu32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #791 = VPMINu32
+ { 792, 5, 1, 3, "VPMINu8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #792 = VPMINu8
+ { 793, 4, 1, 39, "VQABSv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #793 = VQABSv16i8
+ { 794, 4, 1, 38, "VQABSv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #794 = VQABSv2i32
+ { 795, 4, 1, 38, "VQABSv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #795 = VQABSv4i16
+ { 796, 4, 1, 39, "VQABSv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #796 = VQABSv4i32
+ { 797, 4, 1, 39, "VQABSv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #797 = VQABSv8i16
+ { 798, 4, 1, 38, "VQABSv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #798 = VQABSv8i8
+ { 799, 5, 1, 4, "VQADDsv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #799 = VQADDsv16i8
+ { 800, 5, 1, 3, "VQADDsv1i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #800 = VQADDsv1i64
+ { 801, 5, 1, 3, "VQADDsv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #801 = VQADDsv2i32
+ { 802, 5, 1, 4, "VQADDsv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #802 = VQADDsv2i64
+ { 803, 5, 1, 3, "VQADDsv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #803 = VQADDsv4i16
+ { 804, 5, 1, 4, "VQADDsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #804 = VQADDsv4i32
+ { 805, 5, 1, 4, "VQADDsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #805 = VQADDsv8i16
+ { 806, 5, 1, 3, "VQADDsv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #806 = VQADDsv8i8
+ { 807, 5, 1, 4, "VQADDuv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #807 = VQADDuv16i8
+ { 808, 5, 1, 3, "VQADDuv1i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #808 = VQADDuv1i64
+ { 809, 5, 1, 3, "VQADDuv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #809 = VQADDuv2i32
+ { 810, 5, 1, 4, "VQADDuv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #810 = VQADDuv2i64
+ { 811, 5, 1, 3, "VQADDuv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #811 = VQADDuv4i16
+ { 812, 5, 1, 4, "VQADDuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #812 = VQADDuv4i32
+ { 813, 5, 1, 4, "VQADDuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #813 = VQADDuv8i16
+ { 814, 5, 1, 3, "VQADDuv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #814 = VQADDuv8i8
+ { 815, 7, 1, 19, "VQDMLALslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #815 = VQDMLALslv2i32
+ { 816, 7, 1, 17, "VQDMLALslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo92 }, // Inst #816 = VQDMLALslv4i16
+ { 817, 6, 1, 17, "VQDMLALv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #817 = VQDMLALv2i64
+ { 818, 6, 1, 17, "VQDMLALv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #818 = VQDMLALv4i32
+ { 819, 7, 1, 19, "VQDMLSLslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #819 = VQDMLSLslv2i32
+ { 820, 7, 1, 17, "VQDMLSLslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo92 }, // Inst #820 = VQDMLSLslv4i16
+ { 821, 6, 1, 17, "VQDMLSLv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #821 = VQDMLSLv2i64
+ { 822, 6, 1, 17, "VQDMLSLv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #822 = VQDMLSLv4i32
+ { 823, 6, 1, 31, "VQDMULHslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo111 }, // Inst #823 = VQDMULHslv2i32
+ { 824, 6, 1, 29, "VQDMULHslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo113 }, // Inst #824 = VQDMULHslv4i16
+ { 825, 6, 1, 32, "VQDMULHslv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo112 }, // Inst #825 = VQDMULHslv4i32
+ { 826, 6, 1, 30, "VQDMULHslv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo114 }, // Inst #826 = VQDMULHslv8i16
+ { 827, 5, 1, 31, "VQDMULHv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #827 = VQDMULHv2i32
+ { 828, 5, 1, 29, "VQDMULHv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #828 = VQDMULHv4i16
+ { 829, 5, 1, 32, "VQDMULHv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #829 = VQDMULHv4i32
+ { 830, 5, 1, 30, "VQDMULHv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #830 = VQDMULHv8i16
+ { 831, 6, 1, 29, "VQDMULLslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo109 }, // Inst #831 = VQDMULLslv2i32
+ { 832, 6, 1, 29, "VQDMULLslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo110 }, // Inst #832 = VQDMULLslv4i16
+ { 833, 5, 1, 29, "VQDMULLv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #833 = VQDMULLv2i64
+ { 834, 5, 1, 29, "VQDMULLv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #834 = VQDMULLv4i32
+ { 835, 4, 1, 38, "VQMOVNsuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo101 }, // Inst #835 = VQMOVNsuv2i32
+ { 836, 4, 1, 38, "VQMOVNsuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo101 }, // Inst #836 = VQMOVNsuv4i16
+ { 837, 4, 1, 38, "VQMOVNsuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo101 }, // Inst #837 = VQMOVNsuv8i8
+ { 838, 4, 1, 38, "VQMOVNsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo101 }, // Inst #838 = VQMOVNsv2i32
+ { 839, 4, 1, 38, "VQMOVNsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo101 }, // Inst #839 = VQMOVNsv4i16
+ { 840, 4, 1, 38, "VQMOVNsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo101 }, // Inst #840 = VQMOVNsv8i8
+ { 841, 4, 1, 38, "VQMOVNuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo101 }, // Inst #841 = VQMOVNuv2i32
+ { 842, 4, 1, 38, "VQMOVNuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo101 }, // Inst #842 = VQMOVNuv4i16
+ { 843, 4, 1, 38, "VQMOVNuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo101 }, // Inst #843 = VQMOVNuv8i8
+ { 844, 4, 1, 39, "VQNEGv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #844 = VQNEGv16i8
+ { 845, 4, 1, 38, "VQNEGv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #845 = VQNEGv2i32
+ { 846, 4, 1, 38, "VQNEGv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #846 = VQNEGv4i16
+ { 847, 4, 1, 39, "VQNEGv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #847 = VQNEGv4i32
+ { 848, 4, 1, 39, "VQNEGv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #848 = VQNEGv8i16
+ { 849, 4, 1, 38, "VQNEGv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #849 = VQNEGv8i8
+ { 850, 6, 1, 31, "VQRDMULHslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo111 }, // Inst #850 = VQRDMULHslv2i32
+ { 851, 6, 1, 29, "VQRDMULHslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo113 }, // Inst #851 = VQRDMULHslv4i16
+ { 852, 6, 1, 32, "VQRDMULHslv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo112 }, // Inst #852 = VQRDMULHslv4i32
+ { 853, 6, 1, 30, "VQRDMULHslv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo114 }, // Inst #853 = VQRDMULHslv8i16
+ { 854, 5, 1, 31, "VQRDMULHv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #854 = VQRDMULHv2i32
+ { 855, 5, 1, 29, "VQRDMULHv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #855 = VQRDMULHv4i16
+ { 856, 5, 1, 32, "VQRDMULHv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #856 = VQRDMULHv4i32
+ { 857, 5, 1, 30, "VQRDMULHv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #857 = VQRDMULHv8i16
+ { 858, 5, 1, 43, "VQRSHLsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #858 = VQRSHLsv16i8
+ { 859, 5, 1, 42, "VQRSHLsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #859 = VQRSHLsv1i64
+ { 860, 5, 1, 42, "VQRSHLsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #860 = VQRSHLsv2i32
+ { 861, 5, 1, 43, "VQRSHLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #861 = VQRSHLsv2i64
+ { 862, 5, 1, 42, "VQRSHLsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #862 = VQRSHLsv4i16
+ { 863, 5, 1, 43, "VQRSHLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #863 = VQRSHLsv4i32
+ { 864, 5, 1, 43, "VQRSHLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #864 = VQRSHLsv8i16
+ { 865, 5, 1, 42, "VQRSHLsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #865 = VQRSHLsv8i8
+ { 866, 5, 1, 43, "VQRSHLuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #866 = VQRSHLuv16i8
+ { 867, 5, 1, 42, "VQRSHLuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #867 = VQRSHLuv1i64
+ { 868, 5, 1, 42, "VQRSHLuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #868 = VQRSHLuv2i32
+ { 869, 5, 1, 43, "VQRSHLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #869 = VQRSHLuv2i64
+ { 870, 5, 1, 42, "VQRSHLuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #870 = VQRSHLuv4i16
+ { 871, 5, 1, 43, "VQRSHLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #871 = VQRSHLuv4i32
+ { 872, 5, 1, 43, "VQRSHLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #872 = VQRSHLuv8i16
+ { 873, 5, 1, 42, "VQRSHLuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #873 = VQRSHLuv8i8
+ { 874, 5, 1, 42, "VQRSHRNsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #874 = VQRSHRNsv2i32
+ { 875, 5, 1, 42, "VQRSHRNsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #875 = VQRSHRNsv4i16
+ { 876, 5, 1, 42, "VQRSHRNsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #876 = VQRSHRNsv8i8
+ { 877, 5, 1, 42, "VQRSHRNuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #877 = VQRSHRNuv2i32
+ { 878, 5, 1, 42, "VQRSHRNuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #878 = VQRSHRNuv4i16
+ { 879, 5, 1, 42, "VQRSHRNuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #879 = VQRSHRNuv8i8
+ { 880, 5, 1, 42, "VQRSHRUNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #880 = VQRSHRUNv2i32
+ { 881, 5, 1, 42, "VQRSHRUNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #881 = VQRSHRUNv4i16
+ { 882, 5, 1, 42, "VQRSHRUNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #882 = VQRSHRUNv8i8
+ { 883, 5, 1, 42, "VQSHLsiv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #883 = VQSHLsiv16i8
+ { 884, 5, 1, 42, "VQSHLsiv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #884 = VQSHLsiv1i64
+ { 885, 5, 1, 42, "VQSHLsiv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #885 = VQSHLsiv2i32
+ { 886, 5, 1, 42, "VQSHLsiv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #886 = VQSHLsiv2i64
+ { 887, 5, 1, 42, "VQSHLsiv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #887 = VQSHLsiv4i16
+ { 888, 5, 1, 42, "VQSHLsiv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #888 = VQSHLsiv4i32
+ { 889, 5, 1, 42, "VQSHLsiv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #889 = VQSHLsiv8i16
+ { 890, 5, 1, 42, "VQSHLsiv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #890 = VQSHLsiv8i8
+ { 891, 5, 1, 42, "VQSHLsuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #891 = VQSHLsuv16i8
+ { 892, 5, 1, 42, "VQSHLsuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #892 = VQSHLsuv1i64
+ { 893, 5, 1, 42, "VQSHLsuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #893 = VQSHLsuv2i32
+ { 894, 5, 1, 42, "VQSHLsuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #894 = VQSHLsuv2i64
+ { 895, 5, 1, 42, "VQSHLsuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #895 = VQSHLsuv4i16
+ { 896, 5, 1, 42, "VQSHLsuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #896 = VQSHLsuv4i32
+ { 897, 5, 1, 42, "VQSHLsuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #897 = VQSHLsuv8i16
+ { 898, 5, 1, 42, "VQSHLsuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #898 = VQSHLsuv8i8
+ { 899, 5, 1, 43, "VQSHLsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #899 = VQSHLsv16i8
+ { 900, 5, 1, 42, "VQSHLsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #900 = VQSHLsv1i64
+ { 901, 5, 1, 42, "VQSHLsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #901 = VQSHLsv2i32
+ { 902, 5, 1, 43, "VQSHLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #902 = VQSHLsv2i64
+ { 903, 5, 1, 42, "VQSHLsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #903 = VQSHLsv4i16
+ { 904, 5, 1, 43, "VQSHLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #904 = VQSHLsv4i32
+ { 905, 5, 1, 43, "VQSHLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #905 = VQSHLsv8i16
+ { 906, 5, 1, 42, "VQSHLsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #906 = VQSHLsv8i8
+ { 907, 5, 1, 42, "VQSHLuiv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #907 = VQSHLuiv16i8
+ { 908, 5, 1, 42, "VQSHLuiv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #908 = VQSHLuiv1i64
+ { 909, 5, 1, 42, "VQSHLuiv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #909 = VQSHLuiv2i32
+ { 910, 5, 1, 42, "VQSHLuiv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #910 = VQSHLuiv2i64
+ { 911, 5, 1, 42, "VQSHLuiv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #911 = VQSHLuiv4i16
+ { 912, 5, 1, 42, "VQSHLuiv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #912 = VQSHLuiv4i32
+ { 913, 5, 1, 42, "VQSHLuiv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #913 = VQSHLuiv8i16
+ { 914, 5, 1, 42, "VQSHLuiv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #914 = VQSHLuiv8i8
+ { 915, 5, 1, 43, "VQSHLuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #915 = VQSHLuv16i8
+ { 916, 5, 1, 42, "VQSHLuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #916 = VQSHLuv1i64
+ { 917, 5, 1, 42, "VQSHLuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #917 = VQSHLuv2i32
+ { 918, 5, 1, 43, "VQSHLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #918 = VQSHLuv2i64
+ { 919, 5, 1, 42, "VQSHLuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #919 = VQSHLuv4i16
+ { 920, 5, 1, 43, "VQSHLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #920 = VQSHLuv4i32
+ { 921, 5, 1, 43, "VQSHLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #921 = VQSHLuv8i16
+ { 922, 5, 1, 42, "VQSHLuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #922 = VQSHLuv8i8
+ { 923, 5, 1, 42, "VQSHRNsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #923 = VQSHRNsv2i32
+ { 924, 5, 1, 42, "VQSHRNsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #924 = VQSHRNsv4i16
+ { 925, 5, 1, 42, "VQSHRNsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #925 = VQSHRNsv8i8
+ { 926, 5, 1, 42, "VQSHRNuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #926 = VQSHRNuv2i32
+ { 927, 5, 1, 42, "VQSHRNuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #927 = VQSHRNuv4i16
+ { 928, 5, 1, 42, "VQSHRNuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #928 = VQSHRNuv8i8
+ { 929, 5, 1, 42, "VQSHRUNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #929 = VQSHRUNv2i32
+ { 930, 5, 1, 42, "VQSHRUNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #930 = VQSHRUNv4i16
+ { 931, 5, 1, 42, "VQSHRUNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #931 = VQSHRUNv8i8
+ { 932, 5, 1, 4, "VQSUBsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #932 = VQSUBsv16i8
+ { 933, 5, 1, 3, "VQSUBsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #933 = VQSUBsv1i64
+ { 934, 5, 1, 3, "VQSUBsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #934 = VQSUBsv2i32
+ { 935, 5, 1, 4, "VQSUBsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #935 = VQSUBsv2i64
+ { 936, 5, 1, 3, "VQSUBsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #936 = VQSUBsv4i16
+ { 937, 5, 1, 4, "VQSUBsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #937 = VQSUBsv4i32
+ { 938, 5, 1, 4, "VQSUBsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #938 = VQSUBsv8i16
+ { 939, 5, 1, 3, "VQSUBsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #939 = VQSUBsv8i8
+ { 940, 5, 1, 4, "VQSUBuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #940 = VQSUBuv16i8
+ { 941, 5, 1, 3, "VQSUBuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #941 = VQSUBuv1i64
+ { 942, 5, 1, 3, "VQSUBuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #942 = VQSUBuv2i32
+ { 943, 5, 1, 4, "VQSUBuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #943 = VQSUBuv2i64
+ { 944, 5, 1, 3, "VQSUBuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #944 = VQSUBuv4i16
+ { 945, 5, 1, 4, "VQSUBuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #945 = VQSUBuv4i32
+ { 946, 5, 1, 4, "VQSUBuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #946 = VQSUBuv8i16
+ { 947, 5, 1, 3, "VQSUBuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #947 = VQSUBuv8i8
+ { 948, 5, 1, 3, "VRADDHNv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #948 = VRADDHNv2i32
+ { 949, 5, 1, 3, "VRADDHNv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #949 = VRADDHNv4i16
+ { 950, 5, 1, 3, "VRADDHNv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #950 = VRADDHNv8i8
+ { 951, 4, 1, 57, "VRECPEd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #951 = VRECPEd
+ { 952, 4, 1, 57, "VRECPEfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #952 = VRECPEfd
+ { 953, 4, 1, 58, "VRECPEfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #953 = VRECPEfq
+ { 954, 4, 1, 58, "VRECPEq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #954 = VRECPEq
+ { 955, 5, 1, 40, "VRECPSfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #955 = VRECPSfd
+ { 956, 5, 1, 41, "VRECPSfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #956 = VRECPSfq
+ { 957, 4, 1, 21, "VREV16d8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #957 = VREV16d8
+ { 958, 4, 1, 21, "VREV16q8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #958 = VREV16q8
+ { 959, 4, 1, 21, "VREV32d16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #959 = VREV32d16
+ { 960, 4, 1, 21, "VREV32d8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #960 = VREV32d8
+ { 961, 4, 1, 21, "VREV32q16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #961 = VREV32q16
+ { 962, 4, 1, 21, "VREV32q8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #962 = VREV32q8
+ { 963, 4, 1, 21, "VREV64d16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #963 = VREV64d16
+ { 964, 4, 1, 21, "VREV64d32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #964 = VREV64d32
+ { 965, 4, 1, 21, "VREV64d8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #965 = VREV64d8
+ { 966, 4, 1, 21, "VREV64df", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #966 = VREV64df
+ { 967, 4, 1, 21, "VREV64q16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #967 = VREV64q16
+ { 968, 4, 1, 21, "VREV64q32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #968 = VREV64q32
+ { 969, 4, 1, 21, "VREV64q8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #969 = VREV64q8
+ { 970, 4, 1, 21, "VREV64qf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #970 = VREV64qf
+ { 971, 5, 1, 4, "VRHADDsv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #971 = VRHADDsv16i8
+ { 972, 5, 1, 3, "VRHADDsv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #972 = VRHADDsv2i32
+ { 973, 5, 1, 3, "VRHADDsv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #973 = VRHADDsv4i16
+ { 974, 5, 1, 4, "VRHADDsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #974 = VRHADDsv4i32
+ { 975, 5, 1, 4, "VRHADDsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #975 = VRHADDsv8i16
+ { 976, 5, 1, 3, "VRHADDsv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #976 = VRHADDsv8i8
+ { 977, 5, 1, 4, "VRHADDuv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #977 = VRHADDuv16i8
+ { 978, 5, 1, 3, "VRHADDuv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #978 = VRHADDuv2i32
+ { 979, 5, 1, 3, "VRHADDuv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #979 = VRHADDuv4i16
+ { 980, 5, 1, 4, "VRHADDuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #980 = VRHADDuv4i32
+ { 981, 5, 1, 4, "VRHADDuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #981 = VRHADDuv8i16
+ { 982, 5, 1, 3, "VRHADDuv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #982 = VRHADDuv8i8
+ { 983, 5, 1, 43, "VRSHLsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #983 = VRSHLsv16i8
+ { 984, 5, 1, 42, "VRSHLsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #984 = VRSHLsv1i64
+ { 985, 5, 1, 42, "VRSHLsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #985 = VRSHLsv2i32
+ { 986, 5, 1, 43, "VRSHLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #986 = VRSHLsv2i64
+ { 987, 5, 1, 42, "VRSHLsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #987 = VRSHLsv4i16
+ { 988, 5, 1, 43, "VRSHLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #988 = VRSHLsv4i32
+ { 989, 5, 1, 43, "VRSHLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #989 = VRSHLsv8i16
+ { 990, 5, 1, 42, "VRSHLsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #990 = VRSHLsv8i8
+ { 991, 5, 1, 43, "VRSHLuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #991 = VRSHLuv16i8
+ { 992, 5, 1, 42, "VRSHLuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #992 = VRSHLuv1i64
+ { 993, 5, 1, 42, "VRSHLuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #993 = VRSHLuv2i32
+ { 994, 5, 1, 43, "VRSHLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #994 = VRSHLuv2i64
+ { 995, 5, 1, 42, "VRSHLuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #995 = VRSHLuv4i16
+ { 996, 5, 1, 43, "VRSHLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #996 = VRSHLuv4i32
+ { 997, 5, 1, 43, "VRSHLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #997 = VRSHLuv8i16
+ { 998, 5, 1, 42, "VRSHLuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #998 = VRSHLuv8i8
+ { 999, 5, 1, 42, "VRSHRNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #999 = VRSHRNv2i32
+ { 1000, 5, 1, 42, "VRSHRNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #1000 = VRSHRNv4i16
+ { 1001, 5, 1, 42, "VRSHRNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #1001 = VRSHRNv8i8
+ { 1002, 5, 1, 42, "VRSHRsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #1002 = VRSHRsv16i8
+ { 1003, 5, 1, 42, "VRSHRsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1003 = VRSHRsv1i64
+ { 1004, 5, 1, 42, "VRSHRsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1004 = VRSHRsv2i32
+ { 1005, 5, 1, 42, "VRSHRsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #1005 = VRSHRsv2i64
+ { 1006, 5, 1, 42, "VRSHRsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1006 = VRSHRsv4i16
+ { 1007, 5, 1, 42, "VRSHRsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #1007 = VRSHRsv4i32
+ { 1008, 5, 1, 42, "VRSHRsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #1008 = VRSHRsv8i16
+ { 1009, 5, 1, 42, "VRSHRsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1009 = VRSHRsv8i8
+ { 1010, 5, 1, 42, "VRSHRuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #1010 = VRSHRuv16i8
+ { 1011, 5, 1, 42, "VRSHRuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1011 = VRSHRuv1i64
+ { 1012, 5, 1, 42, "VRSHRuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1012 = VRSHRuv2i32
+ { 1013, 5, 1, 42, "VRSHRuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #1013 = VRSHRuv2i64
+ { 1014, 5, 1, 42, "VRSHRuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1014 = VRSHRuv4i16
+ { 1015, 5, 1, 42, "VRSHRuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #1015 = VRSHRuv4i32
+ { 1016, 5, 1, 42, "VRSHRuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #1016 = VRSHRuv8i16
+ { 1017, 5, 1, 42, "VRSHRuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1017 = VRSHRuv8i8
+ { 1018, 4, 1, 57, "VRSQRTEd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #1018 = VRSQRTEd
+ { 1019, 4, 1, 57, "VRSQRTEfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #1019 = VRSQRTEfd
+ { 1020, 4, 1, 58, "VRSQRTEfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #1020 = VRSQRTEfq
+ { 1021, 4, 1, 58, "VRSQRTEq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #1021 = VRSQRTEq
+ { 1022, 5, 1, 40, "VRSQRTSfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #1022 = VRSQRTSfd
+ { 1023, 5, 1, 41, "VRSQRTSfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #1023 = VRSQRTSfq
+ { 1024, 6, 1, 33, "VRSRAsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1024 = VRSRAsv16i8
+ { 1025, 6, 1, 33, "VRSRAsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1025 = VRSRAsv1i64
+ { 1026, 6, 1, 33, "VRSRAsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1026 = VRSRAsv2i32
+ { 1027, 6, 1, 33, "VRSRAsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1027 = VRSRAsv2i64
+ { 1028, 6, 1, 33, "VRSRAsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1028 = VRSRAsv4i16
+ { 1029, 6, 1, 33, "VRSRAsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1029 = VRSRAsv4i32
+ { 1030, 6, 1, 33, "VRSRAsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1030 = VRSRAsv8i16
+ { 1031, 6, 1, 33, "VRSRAsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1031 = VRSRAsv8i8
+ { 1032, 6, 1, 33, "VRSRAuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1032 = VRSRAuv16i8
+ { 1033, 6, 1, 33, "VRSRAuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1033 = VRSRAuv1i64
+ { 1034, 6, 1, 33, "VRSRAuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1034 = VRSRAuv2i32
+ { 1035, 6, 1, 33, "VRSRAuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1035 = VRSRAuv2i64
+ { 1036, 6, 1, 33, "VRSRAuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1036 = VRSRAuv4i16
+ { 1037, 6, 1, 33, "VRSRAuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1037 = VRSRAuv4i32
+ { 1038, 6, 1, 33, "VRSRAuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1038 = VRSRAuv8i16
+ { 1039, 6, 1, 33, "VRSRAuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1039 = VRSRAuv8i8
+ { 1040, 5, 1, 3, "VRSUBHNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #1040 = VRSUBHNv2i32
+ { 1041, 5, 1, 3, "VRSUBHNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #1041 = VRSUBHNv4i16
+ { 1042, 5, 1, 3, "VRSUBHNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #1042 = VRSUBHNv8i8
+ { 1043, 6, 1, 25, "VSETLNi16", 0|(1<<TID::Predicable), 0|(3<<4)|(26<<9), NULL, NULL, NULL, OperandInfo119 }, // Inst #1043 = VSETLNi16
+ { 1044, 6, 1, 25, "VSETLNi32", 0|(1<<TID::Predicable), 0|(3<<4)|(26<<9), NULL, NULL, NULL, OperandInfo119 }, // Inst #1044 = VSETLNi32
+ { 1045, 6, 1, 25, "VSETLNi8", 0|(1<<TID::Predicable), 0|(3<<4)|(26<<9), NULL, NULL, NULL, OperandInfo119 }, // Inst #1045 = VSETLNi8
+ { 1046, 5, 1, 44, "VSHLLi16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo73 }, // Inst #1046 = VSHLLi16
+ { 1047, 5, 1, 44, "VSHLLi32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo73 }, // Inst #1047 = VSHLLi32
+ { 1048, 5, 1, 44, "VSHLLi8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo73 }, // Inst #1048 = VSHLLi8
+ { 1049, 5, 1, 44, "VSHLLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo73 }, // Inst #1049 = VSHLLsv2i64
+ { 1050, 5, 1, 44, "VSHLLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo73 }, // Inst #1050 = VSHLLsv4i32
+ { 1051, 5, 1, 44, "VSHLLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo73 }, // Inst #1051 = VSHLLsv8i16
+ { 1052, 5, 1, 44, "VSHLLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo73 }, // Inst #1052 = VSHLLuv2i64
+ { 1053, 5, 1, 44, "VSHLLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo73 }, // Inst #1053 = VSHLLuv4i32
+ { 1054, 5, 1, 44, "VSHLLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo73 }, // Inst #1054 = VSHLLuv8i16
+ { 1055, 5, 1, 44, "VSHLiv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #1055 = VSHLiv16i8
+ { 1056, 5, 1, 44, "VSHLiv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1056 = VSHLiv1i64
+ { 1057, 5, 1, 44, "VSHLiv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1057 = VSHLiv2i32
+ { 1058, 5, 1, 44, "VSHLiv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #1058 = VSHLiv2i64
+ { 1059, 5, 1, 44, "VSHLiv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1059 = VSHLiv4i16
+ { 1060, 5, 1, 44, "VSHLiv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #1060 = VSHLiv4i32
+ { 1061, 5, 1, 44, "VSHLiv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #1061 = VSHLiv8i16
+ { 1062, 5, 1, 44, "VSHLiv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1062 = VSHLiv8i8
+ { 1063, 5, 1, 45, "VSHLsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #1063 = VSHLsv16i8
+ { 1064, 5, 1, 44, "VSHLsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #1064 = VSHLsv1i64
+ { 1065, 5, 1, 44, "VSHLsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #1065 = VSHLsv2i32
+ { 1066, 5, 1, 45, "VSHLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #1066 = VSHLsv2i64
+ { 1067, 5, 1, 44, "VSHLsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #1067 = VSHLsv4i16
+ { 1068, 5, 1, 45, "VSHLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #1068 = VSHLsv4i32
+ { 1069, 5, 1, 45, "VSHLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #1069 = VSHLsv8i16
+ { 1070, 5, 1, 44, "VSHLsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #1070 = VSHLsv8i8
+ { 1071, 5, 1, 45, "VSHLuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #1071 = VSHLuv16i8
+ { 1072, 5, 1, 44, "VSHLuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #1072 = VSHLuv1i64
+ { 1073, 5, 1, 44, "VSHLuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #1073 = VSHLuv2i32
+ { 1074, 5, 1, 45, "VSHLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #1074 = VSHLuv2i64
+ { 1075, 5, 1, 44, "VSHLuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #1075 = VSHLuv4i16
+ { 1076, 5, 1, 45, "VSHLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #1076 = VSHLuv4i32
+ { 1077, 5, 1, 45, "VSHLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #1077 = VSHLuv8i16
+ { 1078, 5, 1, 44, "VSHLuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #1078 = VSHLuv8i8
+ { 1079, 5, 1, 44, "VSHRNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #1079 = VSHRNv2i32
+ { 1080, 5, 1, 44, "VSHRNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #1080 = VSHRNv4i16
+ { 1081, 5, 1, 44, "VSHRNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #1081 = VSHRNv8i8
+ { 1082, 5, 1, 44, "VSHRsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #1082 = VSHRsv16i8
+ { 1083, 5, 1, 44, "VSHRsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1083 = VSHRsv1i64
+ { 1084, 5, 1, 44, "VSHRsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1084 = VSHRsv2i32
+ { 1085, 5, 1, 44, "VSHRsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #1085 = VSHRsv2i64
+ { 1086, 5, 1, 44, "VSHRsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1086 = VSHRsv4i16
+ { 1087, 5, 1, 44, "VSHRsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #1087 = VSHRsv4i32
+ { 1088, 5, 1, 44, "VSHRsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #1088 = VSHRsv8i16
+ { 1089, 5, 1, 44, "VSHRsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1089 = VSHRsv8i8
+ { 1090, 5, 1, 44, "VSHRuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #1090 = VSHRuv16i8
+ { 1091, 5, 1, 44, "VSHRuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1091 = VSHRuv1i64
+ { 1092, 5, 1, 44, "VSHRuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1092 = VSHRuv2i32
+ { 1093, 5, 1, 44, "VSHRuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #1093 = VSHRuv2i64
+ { 1094, 5, 1, 44, "VSHRuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1094 = VSHRuv4i16
+ { 1095, 5, 1, 44, "VSHRuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #1095 = VSHRuv4i32
+ { 1096, 5, 1, 44, "VSHRuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #1096 = VSHRuv8i16
+ { 1097, 5, 1, 44, "VSHRuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1097 = VSHRuv8i8
+ { 1098, 5, 1, 67, "VSHTOD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo120 }, // Inst #1098 = VSHTOD
+ { 1099, 5, 1, 68, "VSHTOS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo121 }, // Inst #1099 = VSHTOS
+ { 1100, 4, 1, 67, "VSITOD", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo67 }, // Inst #1100 = VSITOD
+ { 1101, 4, 1, 68, "VSITOS", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo58 }, // Inst #1101 = VSITOS
+ { 1102, 6, 1, 45, "VSLIv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1102 = VSLIv16i8
+ { 1103, 6, 1, 44, "VSLIv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1103 = VSLIv1i64
+ { 1104, 6, 1, 44, "VSLIv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1104 = VSLIv2i32
+ { 1105, 6, 1, 45, "VSLIv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1105 = VSLIv2i64
+ { 1106, 6, 1, 44, "VSLIv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1106 = VSLIv4i16
+ { 1107, 6, 1, 45, "VSLIv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1107 = VSLIv4i32
+ { 1108, 6, 1, 45, "VSLIv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1108 = VSLIv8i16
+ { 1109, 6, 1, 44, "VSLIv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1109 = VSLIv8i8
+ { 1110, 5, 1, 67, "VSLTOD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo120 }, // Inst #1110 = VSLTOD
+ { 1111, 5, 1, 68, "VSLTOS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo121 }, // Inst #1111 = VSLTOS
+ { 1112, 4, 1, 81, "VSQRTD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo57 }, // Inst #1112 = VSQRTD
+ { 1113, 4, 1, 80, "VSQRTS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo58 }, // Inst #1113 = VSQRTS
+ { 1114, 6, 1, 33, "VSRAsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1114 = VSRAsv16i8
+ { 1115, 6, 1, 33, "VSRAsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1115 = VSRAsv1i64
+ { 1116, 6, 1, 33, "VSRAsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1116 = VSRAsv2i32
+ { 1117, 6, 1, 33, "VSRAsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1117 = VSRAsv2i64
+ { 1118, 6, 1, 33, "VSRAsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1118 = VSRAsv4i16
+ { 1119, 6, 1, 33, "VSRAsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1119 = VSRAsv4i32
+ { 1120, 6, 1, 33, "VSRAsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1120 = VSRAsv8i16
+ { 1121, 6, 1, 33, "VSRAsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1121 = VSRAsv8i8
+ { 1122, 6, 1, 33, "VSRAuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1122 = VSRAuv16i8
+ { 1123, 6, 1, 33, "VSRAuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1123 = VSRAuv1i64
+ { 1124, 6, 1, 33, "VSRAuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1124 = VSRAuv2i32
+ { 1125, 6, 1, 33, "VSRAuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1125 = VSRAuv2i64
+ { 1126, 6, 1, 33, "VSRAuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1126 = VSRAuv4i16
+ { 1127, 6, 1, 33, "VSRAuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1127 = VSRAuv4i32
+ { 1128, 6, 1, 33, "VSRAuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1128 = VSRAuv8i16
+ { 1129, 6, 1, 33, "VSRAuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1129 = VSRAuv8i8
+ { 1130, 6, 1, 45, "VSRIv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1130 = VSRIv16i8
+ { 1131, 6, 1, 44, "VSRIv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1131 = VSRIv1i64
+ { 1132, 6, 1, 44, "VSRIv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1132 = VSRIv2i32
+ { 1133, 6, 1, 45, "VSRIv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1133 = VSRIv2i64
+ { 1134, 6, 1, 44, "VSRIv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1134 = VSRIv4i16
+ { 1135, 6, 1, 45, "VSRIv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1135 = VSRIv4i32
+ { 1136, 6, 1, 45, "VSRIv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1136 = VSRIv8i16
+ { 1137, 6, 1, 44, "VSRIv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1137 = VSRIv8i8
+ { 1138, 7, 0, 46, "VST1d16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo122 }, // Inst #1138 = VST1d16
+ { 1139, 7, 0, 46, "VST1d32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo122 }, // Inst #1139 = VST1d32
+ { 1140, 7, 0, 46, "VST1d64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo122 }, // Inst #1140 = VST1d64
+ { 1141, 7, 0, 46, "VST1d8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo122 }, // Inst #1141 = VST1d8
+ { 1142, 7, 0, 46, "VST1df", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo122 }, // Inst #1142 = VST1df
+ { 1143, 7, 0, 46, "VST1q16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo123 }, // Inst #1143 = VST1q16
+ { 1144, 7, 0, 46, "VST1q32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo123 }, // Inst #1144 = VST1q32
+ { 1145, 7, 0, 46, "VST1q64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo123 }, // Inst #1145 = VST1q64
+ { 1146, 7, 0, 46, "VST1q8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo123 }, // Inst #1146 = VST1q8
+ { 1147, 7, 0, 46, "VST1qf", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo123 }, // Inst #1147 = VST1qf
+ { 1148, 9, 0, 46, "VST2LNd16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1148 = VST2LNd16
+ { 1149, 9, 0, 46, "VST2LNd32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1149 = VST2LNd32
+ { 1150, 9, 0, 46, "VST2LNd8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1150 = VST2LNd8
+ { 1151, 9, 0, 46, "VST2LNq16a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1151 = VST2LNq16a
+ { 1152, 9, 0, 46, "VST2LNq16b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1152 = VST2LNq16b
+ { 1153, 9, 0, 46, "VST2LNq32a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1153 = VST2LNq32a
+ { 1154, 9, 0, 46, "VST2LNq32b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1154 = VST2LNq32b
+ { 1155, 8, 0, 46, "VST2d16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1155 = VST2d16
+ { 1156, 8, 0, 46, "VST2d32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1156 = VST2d32
+ { 1157, 8, 0, 46, "VST2d64", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1157 = VST2d64
+ { 1158, 8, 0, 46, "VST2d8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1158 = VST2d8
+ { 1159, 10, 0, 46, "VST2q16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1159 = VST2q16
+ { 1160, 10, 0, 46, "VST2q32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1160 = VST2q32
+ { 1161, 10, 0, 46, "VST2q8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1161 = VST2q8
+ { 1162, 10, 0, 46, "VST3LNd16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo127 }, // Inst #1162 = VST3LNd16
+ { 1163, 10, 0, 46, "VST3LNd32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo127 }, // Inst #1163 = VST3LNd32
+ { 1164, 10, 0, 46, "VST3LNd8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo127 }, // Inst #1164 = VST3LNd8
+ { 1165, 10, 0, 46, "VST3LNq16a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo127 }, // Inst #1165 = VST3LNq16a
+ { 1166, 10, 0, 46, "VST3LNq16b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo127 }, // Inst #1166 = VST3LNq16b
+ { 1167, 10, 0, 46, "VST3LNq32a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo127 }, // Inst #1167 = VST3LNq32a
+ { 1168, 10, 0, 46, "VST3LNq32b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo127 }, // Inst #1168 = VST3LNq32b
+ { 1169, 9, 0, 46, "VST3d16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo128 }, // Inst #1169 = VST3d16
+ { 1170, 9, 0, 46, "VST3d32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo128 }, // Inst #1170 = VST3d32
+ { 1171, 9, 0, 46, "VST3d64", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo128 }, // Inst #1171 = VST3d64
+ { 1172, 9, 0, 46, "VST3d8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo128 }, // Inst #1172 = VST3d8
+ { 1173, 10, 1, 46, "VST3q16a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo129 }, // Inst #1173 = VST3q16a
+ { 1174, 10, 1, 46, "VST3q16b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo129 }, // Inst #1174 = VST3q16b
+ { 1175, 10, 1, 46, "VST3q32a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo129 }, // Inst #1175 = VST3q32a
+ { 1176, 10, 1, 46, "VST3q32b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo129 }, // Inst #1176 = VST3q32b
+ { 1177, 10, 1, 46, "VST3q8a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo129 }, // Inst #1177 = VST3q8a
+ { 1178, 10, 1, 46, "VST3q8b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo129 }, // Inst #1178 = VST3q8b
+ { 1179, 11, 0, 46, "VST4LNd16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo130 }, // Inst #1179 = VST4LNd16
+ { 1180, 11, 0, 46, "VST4LNd32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo130 }, // Inst #1180 = VST4LNd32
+ { 1181, 11, 0, 46, "VST4LNd8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo130 }, // Inst #1181 = VST4LNd8
+ { 1182, 11, 0, 46, "VST4LNq16a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo130 }, // Inst #1182 = VST4LNq16a
+ { 1183, 11, 0, 46, "VST4LNq16b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo130 }, // Inst #1183 = VST4LNq16b
+ { 1184, 11, 0, 46, "VST4LNq32a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo130 }, // Inst #1184 = VST4LNq32a
+ { 1185, 11, 0, 46, "VST4LNq32b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo130 }, // Inst #1185 = VST4LNq32b
+ { 1186, 10, 0, 46, "VST4d16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1186 = VST4d16
+ { 1187, 10, 0, 46, "VST4d32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1187 = VST4d32
+ { 1188, 10, 0, 46, "VST4d64", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1188 = VST4d64
+ { 1189, 10, 0, 46, "VST4d8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1189 = VST4d8
+ { 1190, 11, 1, 46, "VST4q16a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo131 }, // Inst #1190 = VST4q16a
+ { 1191, 11, 1, 46, "VST4q16b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo131 }, // Inst #1191 = VST4q16b
+ { 1192, 11, 1, 46, "VST4q32a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo131 }, // Inst #1192 = VST4q32a
+ { 1193, 11, 1, 46, "VST4q32b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo131 }, // Inst #1193 = VST4q32b
+ { 1194, 11, 1, 46, "VST4q8a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo131 }, // Inst #1194 = VST4q8a
+ { 1195, 11, 1, 46, "VST4q8b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo131 }, // Inst #1195 = VST4q8b
+ { 1196, 5, 0, 85, "VSTMD", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|5|(3<<4)|(21<<9)|(3<<17), NULL, NULL, NULL, OperandInfo32 }, // Inst #1196 = VSTMD
+ { 1197, 5, 0, 85, "VSTMS", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|5|(3<<4)|(21<<9)|(1<<17), NULL, NULL, NULL, OperandInfo32 }, // Inst #1197 = VSTMS
+ { 1198, 5, 0, 84, "VSTRD", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|5|(3<<4)|(20<<9)|(3<<17), NULL, NULL, NULL, OperandInfo88 }, // Inst #1198 = VSTRD
+ { 1199, 5, 0, 85, "VSTRQ", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|4|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo89 }, // Inst #1199 = VSTRQ
+ { 1200, 5, 0, 83, "VSTRS", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|5|(3<<4)|(20<<9)|(1<<17), NULL, NULL, NULL, OperandInfo90 }, // Inst #1200 = VSTRS
+ { 1201, 5, 1, 62, "VSUBD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #1201 = VSUBD
+ { 1202, 5, 1, 3, "VSUBHNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #1202 = VSUBHNv2i32
+ { 1203, 5, 1, 3, "VSUBHNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #1203 = VSUBHNv4i16
+ { 1204, 5, 1, 3, "VSUBHNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #1204 = VSUBHNv8i8
+ { 1205, 5, 1, 44, "VSUBLsv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #1205 = VSUBLsv2i64
+ { 1206, 5, 1, 44, "VSUBLsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #1206 = VSUBLsv4i32
+ { 1207, 5, 1, 44, "VSUBLsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #1207 = VSUBLsv8i16
+ { 1208, 5, 1, 44, "VSUBLuv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #1208 = VSUBLuv2i64
+ { 1209, 5, 1, 44, "VSUBLuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #1209 = VSUBLuv4i32
+ { 1210, 5, 1, 44, "VSUBLuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #1210 = VSUBLuv8i16
+ { 1211, 5, 1, 61, "VSUBS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #1211 = VSUBS
+ { 1212, 5, 1, 47, "VSUBWsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1212 = VSUBWsv2i64
+ { 1213, 5, 1, 47, "VSUBWsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1213 = VSUBWsv4i32
+ { 1214, 5, 1, 47, "VSUBWsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1214 = VSUBWsv8i16
+ { 1215, 5, 1, 47, "VSUBWuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1215 = VSUBWuv2i64
+ { 1216, 5, 1, 47, "VSUBWuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1216 = VSUBWuv4i32
+ { 1217, 5, 1, 47, "VSUBWuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1217 = VSUBWuv8i16
+ { 1218, 5, 1, 1, "VSUBfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #1218 = VSUBfd
+ { 1219, 5, 1, 1, "VSUBfd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1219 = VSUBfd_sfp
+ { 1220, 5, 1, 2, "VSUBfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #1220 = VSUBfq
+ { 1221, 5, 1, 48, "VSUBv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #1221 = VSUBv16i8
+ { 1222, 5, 1, 47, "VSUBv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #1222 = VSUBv1i64
+ { 1223, 5, 1, 47, "VSUBv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #1223 = VSUBv2i32
+ { 1224, 5, 1, 48, "VSUBv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #1224 = VSUBv2i64
+ { 1225, 5, 1, 47, "VSUBv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #1225 = VSUBv4i16
+ { 1226, 5, 1, 48, "VSUBv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #1226 = VSUBv4i32
+ { 1227, 5, 1, 48, "VSUBv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #1227 = VSUBv8i16
+ { 1228, 5, 1, 47, "VSUBv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #1228 = VSUBv8i8
+ { 1229, 5, 1, 49, "VTBL1", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #1229 = VTBL1
+ { 1230, 6, 1, 50, "VTBL2", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo132 }, // Inst #1230 = VTBL2
+ { 1231, 7, 1, 51, "VTBL3", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo133 }, // Inst #1231 = VTBL3
+ { 1232, 8, 1, 52, "VTBL4", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo134 }, // Inst #1232 = VTBL4
+ { 1233, 6, 1, 53, "VTBX1", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #1233 = VTBX1
+ { 1234, 7, 1, 54, "VTBX2", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo135 }, // Inst #1234 = VTBX2
+ { 1235, 8, 1, 55, "VTBX3", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo136 }, // Inst #1235 = VTBX3
+ { 1236, 9, 1, 56, "VTBX4", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo137 }, // Inst #1236 = VTBX4
+ { 1237, 5, 1, 65, "VTOSHD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo120 }, // Inst #1237 = VTOSHD
+ { 1238, 5, 1, 70, "VTOSHS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo121 }, // Inst #1238 = VTOSHS
+ { 1239, 4, 1, 65, "VTOSIRD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #1239 = VTOSIRD
+ { 1240, 4, 1, 70, "VTOSIRS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo58 }, // Inst #1240 = VTOSIRS
+ { 1241, 4, 1, 65, "VTOSIZD", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #1241 = VTOSIZD
+ { 1242, 4, 1, 70, "VTOSIZS", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo58 }, // Inst #1242 = VTOSIZS
+ { 1243, 5, 1, 65, "VTOSLD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo120 }, // Inst #1243 = VTOSLD
+ { 1244, 5, 1, 70, "VTOSLS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo121 }, // Inst #1244 = VTOSLS
+ { 1245, 5, 1, 65, "VTOUHD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo120 }, // Inst #1245 = VTOUHD
+ { 1246, 5, 1, 70, "VTOUHS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo121 }, // Inst #1246 = VTOUHS
+ { 1247, 4, 1, 65, "VTOUIRD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #1247 = VTOUIRD
+ { 1248, 4, 1, 70, "VTOUIRS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo58 }, // Inst #1248 = VTOUIRS
+ { 1249, 4, 1, 65, "VTOUIZD", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #1249 = VTOUIZD
+ { 1250, 4, 1, 70, "VTOUIZS", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo58 }, // Inst #1250 = VTOUIZS
+ { 1251, 5, 1, 65, "VTOULD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo120 }, // Inst #1251 = VTOULD
+ { 1252, 5, 1, 70, "VTOULS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo121 }, // Inst #1252 = VTOULS
+ { 1253, 6, 2, 35, "VTRNd16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo138 }, // Inst #1253 = VTRNd16
+ { 1254, 6, 2, 35, "VTRNd32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo138 }, // Inst #1254 = VTRNd32
+ { 1255, 6, 2, 35, "VTRNd8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo138 }, // Inst #1255 = VTRNd8
+ { 1256, 6, 2, 36, "VTRNq16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo139 }, // Inst #1256 = VTRNq16
+ { 1257, 6, 2, 36, "VTRNq32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo139 }, // Inst #1257 = VTRNq32
+ { 1258, 6, 2, 36, "VTRNq8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo139 }, // Inst #1258 = VTRNq8
+ { 1259, 5, 1, 4, "VTSTv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #1259 = VTSTv16i8
+ { 1260, 5, 1, 3, "VTSTv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #1260 = VTSTv2i32
+ { 1261, 5, 1, 3, "VTSTv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #1261 = VTSTv4i16
+ { 1262, 5, 1, 4, "VTSTv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #1262 = VTSTv4i32
+ { 1263, 5, 1, 4, "VTSTv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #1263 = VTSTv8i16
+ { 1264, 5, 1, 3, "VTSTv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #1264 = VTSTv8i8
+ { 1265, 5, 1, 67, "VUHTOD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo120 }, // Inst #1265 = VUHTOD
+ { 1266, 5, 1, 68, "VUHTOS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo121 }, // Inst #1266 = VUHTOS
+ { 1267, 4, 1, 67, "VUITOD", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo67 }, // Inst #1267 = VUITOD
+ { 1268, 4, 1, 68, "VUITOS", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo58 }, // Inst #1268 = VUITOS
+ { 1269, 5, 1, 67, "VULTOD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo120 }, // Inst #1269 = VULTOD
+ { 1270, 5, 1, 68, "VULTOS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo121 }, // Inst #1270 = VULTOS
+ { 1271, 6, 2, 35, "VUZPd16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo138 }, // Inst #1271 = VUZPd16
+ { 1272, 6, 2, 35, "VUZPd32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo138 }, // Inst #1272 = VUZPd32
+ { 1273, 6, 2, 35, "VUZPd8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo138 }, // Inst #1273 = VUZPd8
+ { 1274, 6, 2, 37, "VUZPq16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo139 }, // Inst #1274 = VUZPq16
+ { 1275, 6, 2, 37, "VUZPq32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo139 }, // Inst #1275 = VUZPq32
+ { 1276, 6, 2, 37, "VUZPq8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo139 }, // Inst #1276 = VUZPq8
+ { 1277, 6, 2, 35, "VZIPd16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo138 }, // Inst #1277 = VZIPd16
+ { 1278, 6, 2, 35, "VZIPd32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo138 }, // Inst #1278 = VZIPd32
+ { 1279, 6, 2, 35, "VZIPd8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo138 }, // Inst #1279 = VZIPd8
+ { 1280, 6, 2, 37, "VZIPq16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo139 }, // Inst #1280 = VZIPq16
+ { 1281, 6, 2, 37, "VZIPq32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo139 }, // Inst #1281 = VZIPq32
+ { 1282, 6, 2, 37, "VZIPq8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo139 }, // Inst #1282 = VZIPq8
+ { 1283, 2, 0, 128, "WFE", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1283 = WFE
+ { 1284, 2, 0, 128, "WFI", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1284 = WFI
+ { 1285, 2, 0, 128, "YIELD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1285 = YIELD
+ { 1286, 3, 1, 88, "t2ADCSri", 0, 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #1286 = t2ADCSri
+ { 1287, 3, 1, 89, "t2ADCSrr", 0|(1<<TID::Commutable), 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #1287 = t2ADCSrr
+ { 1288, 4, 1, 90, "t2ADCSrs", 0, 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo140 }, // Inst #1288 = t2ADCSrs
+ { 1289, 6, 1, 88, "t2ADCri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #1289 = t2ADCri
+ { 1290, 6, 1, 89, "t2ADCrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo6 }, // Inst #1290 = t2ADCrr
+ { 1291, 7, 1, 90, "t2ADCrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo45 }, // Inst #1291 = t2ADCrs
+ { 1292, 5, 1, 88, "t2ADDSri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1292 = t2ADDSri
+ { 1293, 5, 1, 89, "t2ADDSrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #1293 = t2ADDSrr
+ { 1294, 6, 1, 90, "t2ADDSrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo26 }, // Inst #1294 = t2ADDSrs
+ { 1295, 6, 1, 88, "t2ADDrSPi", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1295 = t2ADDrSPi
+ { 1296, 5, 1, 88, "t2ADDrSPi12", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1296 = t2ADDrSPi12
+ { 1297, 7, 1, 90, "t2ADDrSPs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo45 }, // Inst #1297 = t2ADDrSPs
+ { 1298, 6, 1, 88, "t2ADDri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1298 = t2ADDri
+ { 1299, 6, 1, 88, "t2ADDri12", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1299 = t2ADDri12
+ { 1300, 6, 1, 89, "t2ADDrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1300 = t2ADDrr
+ { 1301, 7, 1, 90, "t2ADDrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo45 }, // Inst #1301 = t2ADDrs
+ { 1302, 6, 1, 88, "t2ANDri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1302 = t2ANDri
+ { 1303, 6, 1, 89, "t2ANDrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1303 = t2ANDrr
+ { 1304, 7, 1, 90, "t2ANDrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo45 }, // Inst #1304 = t2ANDrs
+ { 1305, 6, 1, 113, "t2ASRri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1305 = t2ASRri
+ { 1306, 6, 1, 114, "t2ASRrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1306 = t2ASRrr
+ { 1307, 1, 0, 0, "t2B", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Predicable)|(1<<TID::Terminator), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo14 }, // Inst #1307 = t2B
+ { 1308, 5, 1, 126, "t2BFC", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo15 }, // Inst #1308 = t2BFC
+ { 1309, 6, 1, 88, "t2BFI", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo46 }, // Inst #1309 = t2BFI
+ { 1310, 6, 1, 88, "t2BICri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1310 = t2BICri
+ { 1311, 6, 1, 89, "t2BICrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1311 = t2BICrr
+ { 1312, 7, 1, 90, "t2BICrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo45 }, // Inst #1312 = t2BICrs
+ { 1313, 4, 0, 0, "t2BR_JT", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::NotDuplicable), 0|(1<<4)|(23<<9), NULL, NULL, NULL, OperandInfo17 }, // Inst #1313 = t2BR_JT
+ { 1314, 3, 0, 0, "t2Bcc", 0|(1<<TID::Branch)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #1314 = t2Bcc
+ { 1315, 4, 1, 125, "t2CLZ", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #1315 = t2CLZ
+ { 1316, 4, 0, 97, "t2CMNzri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 }, // Inst #1316 = t2CMNzri
+ { 1317, 4, 0, 98, "t2CMNzrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo24 }, // Inst #1317 = t2CMNzrr
+ { 1318, 5, 0, 99, "t2CMNzrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1318 = t2CMNzrs
+ { 1319, 4, 0, 97, "t2CMPri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 }, // Inst #1319 = t2CMPri
+ { 1320, 4, 0, 98, "t2CMPrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo24 }, // Inst #1320 = t2CMPrr
+ { 1321, 5, 0, 99, "t2CMPrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1321 = t2CMPrs
+ { 1322, 4, 0, 97, "t2CMPzri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 }, // Inst #1322 = t2CMPzri
+ { 1323, 4, 0, 98, "t2CMPzrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo24 }, // Inst #1323 = t2CMPzrr
+ { 1324, 5, 0, 99, "t2CMPzrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1324 = t2CMPzrs
+ { 1325, 6, 1, 88, "t2EORri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1325 = t2EORri
+ { 1326, 6, 1, 89, "t2EORrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1326 = t2EORrr
+ { 1327, 7, 1, 90, "t2EORrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo45 }, // Inst #1327 = t2EORrs
+ { 1328, 2, 0, 92, "t2IT", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo141 }, // Inst #1328 = t2IT
+ { 1329, 0, 0, 128, "t2Int_MemBarrierV7", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, 0 }, // Inst #1329 = t2Int_MemBarrierV7
+ { 1330, 0, 0, 128, "t2Int_SyncBarrierV7", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, 0 }, // Inst #1330 = t2Int_SyncBarrierV7
+ { 1331, 2, 0, 128, "t2Int_eh_sjlj_setjmp", 0, 0|(1<<4)|(23<<9), NULL, ImplicitList6, Barriers3, OperandInfo142 }, // Inst #1331 = t2Int_eh_sjlj_setjmp
+ { 1332, 5, 0, 103, "t2LDM", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1332 = t2LDM
+ { 1333, 5, 0, 0, "t2LDM_RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1333 = t2LDM_RET
+ { 1334, 6, 2, 102, "t2LDRB_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo143 }, // Inst #1334 = t2LDRB_POST
+ { 1335, 6, 2, 102, "t2LDRB_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo143 }, // Inst #1335 = t2LDRB_PRE
+ { 1336, 5, 1, 101, "t2LDRBi12", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1336 = t2LDRBi12
+ { 1337, 5, 1, 101, "t2LDRBi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1337 = t2LDRBi8
+ { 1338, 4, 1, 101, "t2LDRBpci", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|14|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1338 = t2LDRBpci
+ { 1339, 6, 1, 104, "t2LDRBs", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1339 = t2LDRBs
+ { 1340, 6, 2, 101, "t2LDRDi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|15|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1340 = t2LDRDi8
+ { 1341, 5, 2, 101, "t2LDRDpci", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|15|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1341 = t2LDRDpci
+ { 1342, 4, 1, 128, "t2LDREX", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #1342 = t2LDREX
+ { 1343, 4, 1, 128, "t2LDREXB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #1343 = t2LDREXB
+ { 1344, 5, 2, 128, "t2LDREXD", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1344 = t2LDREXD
+ { 1345, 4, 1, 128, "t2LDREXH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #1345 = t2LDREXH
+ { 1346, 6, 2, 102, "t2LDRH_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo143 }, // Inst #1346 = t2LDRH_POST
+ { 1347, 6, 2, 102, "t2LDRH_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo143 }, // Inst #1347 = t2LDRH_PRE
+ { 1348, 5, 1, 101, "t2LDRHi12", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1348 = t2LDRHi12
+ { 1349, 5, 1, 101, "t2LDRHi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1349 = t2LDRHi8
+ { 1350, 4, 1, 101, "t2LDRHpci", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|14|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1350 = t2LDRHpci
+ { 1351, 6, 1, 104, "t2LDRHs", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1351 = t2LDRHs
+ { 1352, 6, 2, 102, "t2LDRSB_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo143 }, // Inst #1352 = t2LDRSB_POST
+ { 1353, 6, 2, 102, "t2LDRSB_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo143 }, // Inst #1353 = t2LDRSB_PRE
+ { 1354, 5, 1, 101, "t2LDRSBi12", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1354 = t2LDRSBi12
+ { 1355, 5, 1, 101, "t2LDRSBi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1355 = t2LDRSBi8
+ { 1356, 4, 1, 101, "t2LDRSBpci", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|14|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1356 = t2LDRSBpci
+ { 1357, 6, 1, 104, "t2LDRSBs", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1357 = t2LDRSBs
+ { 1358, 6, 2, 102, "t2LDRSH_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo143 }, // Inst #1358 = t2LDRSH_POST
+ { 1359, 6, 2, 102, "t2LDRSH_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo143 }, // Inst #1359 = t2LDRSH_PRE
+ { 1360, 5, 1, 101, "t2LDRSHi12", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1360 = t2LDRSHi12
+ { 1361, 5, 1, 101, "t2LDRSHi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1361 = t2LDRSHi8
+ { 1362, 4, 1, 101, "t2LDRSHpci", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|14|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1362 = t2LDRSHpci
+ { 1363, 6, 1, 104, "t2LDRSHs", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1363 = t2LDRSHs
+ { 1364, 6, 2, 102, "t2LDR_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo143 }, // Inst #1364 = t2LDR_POST
+ { 1365, 6, 2, 102, "t2LDR_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo143 }, // Inst #1365 = t2LDR_PRE
+ { 1366, 5, 1, 101, "t2LDRi12", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1366 = t2LDRi12
+ { 1367, 5, 1, 101, "t2LDRi8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1367 = t2LDRi8
+ { 1368, 4, 1, 101, "t2LDRpci", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|14|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1368 = t2LDRpci
+ { 1369, 3, 1, 128, "t2LDRpci_pic", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|(1<<4), NULL, NULL, NULL, OperandInfo19 }, // Inst #1369 = t2LDRpci_pic
+ { 1370, 6, 1, 104, "t2LDRs", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1370 = t2LDRs
+ { 1371, 4, 1, 88, "t2LEApcrel", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1371 = t2LEApcrel
+ { 1372, 5, 1, 88, "t2LEApcrelJT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo34 }, // Inst #1372 = t2LEApcrelJT
+ { 1373, 6, 1, 113, "t2LSLri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1373 = t2LSLri
+ { 1374, 6, 1, 114, "t2LSLrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1374 = t2LSLrr
+ { 1375, 6, 1, 113, "t2LSRri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1375 = t2LSRri
+ { 1376, 6, 1, 114, "t2LSRrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1376 = t2LSRrr
+ { 1377, 6, 1, 109, "t2MLA", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #1377 = t2MLA
+ { 1378, 6, 1, 109, "t2MLS", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #1378 = t2MLS
+ { 1379, 6, 1, 95, "t2MOVCCasr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo144 }, // Inst #1379 = t2MOVCCasr
+ { 1380, 5, 1, 93, "t2MOVCCi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo15 }, // Inst #1380 = t2MOVCCi
+ { 1381, 6, 1, 95, "t2MOVCClsl", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo144 }, // Inst #1381 = t2MOVCClsl
+ { 1382, 6, 1, 95, "t2MOVCClsr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo144 }, // Inst #1382 = t2MOVCClsr
+ { 1383, 5, 1, 94, "t2MOVCCr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo41 }, // Inst #1383 = t2MOVCCr
+ { 1384, 6, 1, 95, "t2MOVCCror", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo144 }, // Inst #1384 = t2MOVCCror
+ { 1385, 5, 1, 111, "t2MOVTi16", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo15 }, // Inst #1385 = t2MOVTi16
+ { 1386, 5, 1, 111, "t2MOVi", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::HasOptionalDef)|(1<<TID::CheapAsAMove), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1386 = t2MOVi
+ { 1387, 4, 1, 111, "t2MOVi16", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1387 = t2MOVi16
+ { 1388, 4, 1, 111, "t2MOVi32imm", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|(2<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1388 = t2MOVi32imm
+ { 1389, 5, 1, 112, "t2MOVr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo44 }, // Inst #1389 = t2MOVr
+ { 1390, 5, 1, 113, "t2MOVrx", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo44 }, // Inst #1390 = t2MOVrx
+ { 1391, 2, 1, 113, "t2MOVsra_flag", 0, 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo31 }, // Inst #1391 = t2MOVsra_flag
+ { 1392, 2, 1, 113, "t2MOVsrl_flag", 0, 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo31 }, // Inst #1392 = t2MOVsrl_flag
+ { 1393, 5, 1, 116, "t2MUL", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1393 = t2MUL
+ { 1394, 5, 1, 111, "t2MVNi", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::HasOptionalDef)|(1<<TID::CheapAsAMove), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1394 = t2MVNi
+ { 1395, 4, 1, 112, "t2MVNr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #1395 = t2MVNr
+ { 1396, 5, 1, 113, "t2MVNs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1396 = t2MVNs
+ { 1397, 6, 1, 88, "t2ORNri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1397 = t2ORNri
+ { 1398, 6, 1, 89, "t2ORNrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1398 = t2ORNrr
+ { 1399, 7, 1, 90, "t2ORNrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo45 }, // Inst #1399 = t2ORNrs
+ { 1400, 6, 1, 88, "t2ORRri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1400 = t2ORRri
+ { 1401, 6, 1, 89, "t2ORRrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1401 = t2ORRrr
+ { 1402, 7, 1, 90, "t2ORRrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo45 }, // Inst #1402 = t2ORRrs
+ { 1403, 6, 1, 90, "t2PKHBT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1403 = t2PKHBT
+ { 1404, 6, 1, 90, "t2PKHTB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1404 = t2PKHTB
+ { 1405, 4, 1, 125, "t2RBIT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #1405 = t2RBIT
+ { 1406, 4, 1, 125, "t2REV", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #1406 = t2REV
+ { 1407, 4, 1, 125, "t2REV16", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #1407 = t2REV16
+ { 1408, 4, 1, 125, "t2REVSH", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #1408 = t2REVSH
+ { 1409, 6, 1, 113, "t2RORri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1409 = t2RORri
+ { 1410, 6, 1, 114, "t2RORrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1410 = t2RORrr
+ { 1411, 4, 1, 88, "t2RSBSri", 0|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo145 }, // Inst #1411 = t2RSBSri
+ { 1412, 5, 1, 90, "t2RSBSrs", 0|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo146 }, // Inst #1412 = t2RSBSrs
+ { 1413, 5, 1, 88, "t2RSBri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1413 = t2RSBri
+ { 1414, 6, 1, 90, "t2RSBrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1414 = t2RSBrs
+ { 1415, 3, 1, 88, "t2SBCSri", 0, 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #1415 = t2SBCSri
+ { 1416, 3, 1, 89, "t2SBCSrr", 0, 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #1416 = t2SBCSrr
+ { 1417, 4, 1, 90, "t2SBCSrs", 0, 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo140 }, // Inst #1417 = t2SBCSrs
+ { 1418, 6, 1, 88, "t2SBCri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #1418 = t2SBCri
+ { 1419, 6, 1, 89, "t2SBCrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo6 }, // Inst #1419 = t2SBCrr
+ { 1420, 7, 1, 90, "t2SBCrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo45 }, // Inst #1420 = t2SBCrs
+ { 1421, 6, 1, 88, "t2SBFX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo46 }, // Inst #1421 = t2SBFX
+ { 1422, 6, 1, 108, "t2SMLABB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #1422 = t2SMLABB
+ { 1423, 6, 1, 108, "t2SMLABT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #1423 = t2SMLABT
+ { 1424, 6, 2, 110, "t2SMLAL", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #1424 = t2SMLAL
+ { 1425, 6, 1, 108, "t2SMLATB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #1425 = t2SMLATB
+ { 1426, 6, 1, 108, "t2SMLATT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #1426 = t2SMLATT
+ { 1427, 6, 1, 108, "t2SMLAWB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #1427 = t2SMLAWB
+ { 1428, 6, 1, 108, "t2SMLAWT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #1428 = t2SMLAWT
+ { 1429, 6, 1, 109, "t2SMMLA", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #1429 = t2SMMLA
+ { 1430, 6, 1, 109, "t2SMMLS", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #1430 = t2SMMLS
+ { 1431, 5, 1, 116, "t2SMMUL", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1431 = t2SMMUL
+ { 1432, 5, 1, 116, "t2SMULBB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1432 = t2SMULBB
+ { 1433, 5, 1, 116, "t2SMULBT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1433 = t2SMULBT
+ { 1434, 6, 2, 117, "t2SMULL", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #1434 = t2SMULL
+ { 1435, 5, 1, 116, "t2SMULTB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1435 = t2SMULTB
+ { 1436, 5, 1, 116, "t2SMULTT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1436 = t2SMULTT
+ { 1437, 5, 1, 115, "t2SMULWB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1437 = t2SMULWB
+ { 1438, 5, 1, 115, "t2SMULWT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1438 = t2SMULWT
+ { 1439, 5, 0, 120, "t2STM", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1439 = t2STM
+ { 1440, 6, 1, 119, "t2STRB_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo147 }, // Inst #1440 = t2STRB_POST
+ { 1441, 6, 1, 119, "t2STRB_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo147 }, // Inst #1441 = t2STRB_PRE
+ { 1442, 5, 0, 118, "t2STRBi12", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1442 = t2STRBi12
+ { 1443, 5, 0, 118, "t2STRBi8", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1443 = t2STRBi8
+ { 1444, 6, 0, 121, "t2STRBs", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1444 = t2STRBs
+ { 1445, 6, 0, 121, "t2STRDi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|15|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1445 = t2STRDi8
+ { 1446, 5, 1, 128, "t2STREX", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo48 }, // Inst #1446 = t2STREX
+ { 1447, 5, 1, 128, "t2STREXB", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo48 }, // Inst #1447 = t2STREXB
+ { 1448, 6, 1, 128, "t2STREXD", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo49 }, // Inst #1448 = t2STREXD
+ { 1449, 5, 1, 128, "t2STREXH", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo48 }, // Inst #1449 = t2STREXH
+ { 1450, 6, 1, 119, "t2STRH_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo147 }, // Inst #1450 = t2STRH_POST
+ { 1451, 6, 1, 119, "t2STRH_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo147 }, // Inst #1451 = t2STRH_PRE
+ { 1452, 5, 0, 118, "t2STRHi12", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1452 = t2STRHi12
+ { 1453, 5, 0, 118, "t2STRHi8", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1453 = t2STRHi8
+ { 1454, 6, 0, 121, "t2STRHs", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1454 = t2STRHs
+ { 1455, 6, 1, 119, "t2STR_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo147 }, // Inst #1455 = t2STR_POST
+ { 1456, 6, 1, 119, "t2STR_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo147 }, // Inst #1456 = t2STR_PRE
+ { 1457, 5, 0, 118, "t2STRi12", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1457 = t2STRi12
+ { 1458, 5, 0, 118, "t2STRi8", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1458 = t2STRi8
+ { 1459, 6, 0, 121, "t2STRs", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1459 = t2STRs
+ { 1460, 5, 1, 88, "t2SUBSri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1460 = t2SUBSri
+ { 1461, 5, 1, 89, "t2SUBSrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #1461 = t2SUBSrr
+ { 1462, 6, 1, 90, "t2SUBSrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo26 }, // Inst #1462 = t2SUBSrs
+ { 1463, 6, 1, 88, "t2SUBrSPi", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1463 = t2SUBrSPi
+ { 1464, 5, 1, 88, "t2SUBrSPi12", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1464 = t2SUBrSPi12
+ { 1465, 3, 1, 128, "t2SUBrSPi12_", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo2 }, // Inst #1465 = t2SUBrSPi12_
+ { 1466, 3, 1, 128, "t2SUBrSPi_", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo2 }, // Inst #1466 = t2SUBrSPi_
+ { 1467, 7, 1, 90, "t2SUBrSPs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo45 }, // Inst #1467 = t2SUBrSPs
+ { 1468, 4, 1, 128, "t2SUBrSPs_", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo140 }, // Inst #1468 = t2SUBrSPs_
+ { 1469, 6, 1, 88, "t2SUBri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1469 = t2SUBri
+ { 1470, 6, 1, 88, "t2SUBri12", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1470 = t2SUBri12
+ { 1471, 6, 1, 89, "t2SUBrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1471 = t2SUBrr
+ { 1472, 7, 1, 90, "t2SUBrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo45 }, // Inst #1472 = t2SUBrs
+ { 1473, 5, 1, 89, "t2SXTABrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1473 = t2SXTABrr
+ { 1474, 6, 1, 91, "t2SXTABrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1474 = t2SXTABrr_rot
+ { 1475, 5, 1, 89, "t2SXTAHrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1475 = t2SXTAHrr
+ { 1476, 6, 1, 91, "t2SXTAHrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1476 = t2SXTAHrr_rot
+ { 1477, 4, 1, 125, "t2SXTBr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #1477 = t2SXTBr
+ { 1478, 5, 1, 126, "t2SXTBr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1478 = t2SXTBr_rot
+ { 1479, 4, 1, 125, "t2SXTHr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #1479 = t2SXTHr
+ { 1480, 5, 1, 126, "t2SXTHr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1480 = t2SXTHr_rot
+ { 1481, 3, 0, 0, "t2TBB", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::NotDuplicable)|(1<<TID::UnmodeledSideEffects), 0|(1<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #1481 = t2TBB
+ { 1482, 3, 0, 0, "t2TBH", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::NotDuplicable)|(1<<TID::UnmodeledSideEffects), 0|(1<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #1482 = t2TBH
+ { 1483, 4, 0, 97, "t2TEQri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 }, // Inst #1483 = t2TEQri
+ { 1484, 4, 0, 98, "t2TEQrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo24 }, // Inst #1484 = t2TEQrr
+ { 1485, 5, 0, 99, "t2TEQrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1485 = t2TEQrs
+ { 1486, 0, 0, 0, "t2TPsoft", 0|(1<<TID::Call), 0|(3<<4)|(23<<9), NULL, ImplicitList7, Barriers1, 0 }, // Inst #1486 = t2TPsoft
+ { 1487, 4, 0, 97, "t2TSTri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 }, // Inst #1487 = t2TSTri
+ { 1488, 4, 0, 98, "t2TSTrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo24 }, // Inst #1488 = t2TSTrr
+ { 1489, 5, 0, 99, "t2TSTrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1489 = t2TSTrs
+ { 1490, 6, 1, 88, "t2UBFX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo46 }, // Inst #1490 = t2UBFX
+ { 1491, 6, 2, 110, "t2UMAAL", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #1491 = t2UMAAL
+ { 1492, 6, 2, 110, "t2UMLAL", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #1492 = t2UMLAL
+ { 1493, 6, 2, 117, "t2UMULL", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #1493 = t2UMULL
+ { 1494, 5, 1, 89, "t2UXTABrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1494 = t2UXTABrr
+ { 1495, 6, 1, 91, "t2UXTABrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1495 = t2UXTABrr_rot
+ { 1496, 5, 1, 89, "t2UXTAHrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1496 = t2UXTAHrr
+ { 1497, 6, 1, 91, "t2UXTAHrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1497 = t2UXTAHrr_rot
+ { 1498, 4, 1, 125, "t2UXTB16r", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #1498 = t2UXTB16r
+ { 1499, 5, 1, 126, "t2UXTB16r_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1499 = t2UXTB16r_rot
+ { 1500, 4, 1, 125, "t2UXTBr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #1500 = t2UXTBr
+ { 1501, 5, 1, 126, "t2UXTBr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1501 = t2UXTBr_rot
+ { 1502, 4, 1, 125, "t2UXTHr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #1502 = t2UXTHr
+ { 1503, 5, 1, 126, "t2UXTHr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1503 = t2UXTHr_rot
+ { 1504, 6, 2, 89, "tADC", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo148 }, // Inst #1504 = tADC
+ { 1505, 5, 1, 89, "tADDhirr", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo41 }, // Inst #1505 = tADDhirr
+ { 1506, 6, 2, 88, "tADDi3", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo149 }, // Inst #1506 = tADDi3
+ { 1507, 6, 2, 88, "tADDi8", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo150 }, // Inst #1507 = tADDi8
+ { 1508, 2, 1, 88, "tADDrPCi", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo151 }, // Inst #1508 = tADDrPCi
+ { 1509, 3, 1, 89, "tADDrSP", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo152 }, // Inst #1509 = tADDrSP
+ { 1510, 3, 1, 88, "tADDrSPi", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo153 }, // Inst #1510 = tADDrSPi
+ { 1511, 6, 2, 89, "tADDrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo154 }, // Inst #1511 = tADDrr
+ { 1512, 3, 1, 88, "tADDspi", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo155 }, // Inst #1512 = tADDspi
+ { 1513, 3, 1, 89, "tADDspr", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo152 }, // Inst #1513 = tADDspr
+ { 1514, 3, 1, 128, "tADDspr_", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo3 }, // Inst #1514 = tADDspr_
+ { 1515, 1, 0, 128, "tADJCALLSTACKDOWN", 0, 0|(1<<4), ImplicitList2, ImplicitList2, NULL, OperandInfo14 }, // Inst #1515 = tADJCALLSTACKDOWN
+ { 1516, 2, 0, 128, "tADJCALLSTACKUP", 0, 0|(1<<4), ImplicitList2, ImplicitList2, NULL, OperandInfo141 }, // Inst #1516 = tADJCALLSTACKUP
+ { 1517, 6, 2, 89, "tAND", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo148 }, // Inst #1517 = tAND
+ { 1518, 3, 1, 128, "tANDsp", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, ImplicitList1, Barriers1, OperandInfo156 }, // Inst #1518 = tANDsp
+ { 1519, 6, 2, 113, "tASRri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo149 }, // Inst #1519 = tASRri
+ { 1520, 6, 2, 114, "tASRrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo148 }, // Inst #1520 = tASRrr
+ { 1521, 1, 0, 0, "tB", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Predicable)|(1<<TID::Terminator), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo14 }, // Inst #1521 = tB
+ { 1522, 6, 2, 89, "tBIC", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo148 }, // Inst #1522 = tBIC
+ { 1523, 1, 0, 128, "tBKPT", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo14 }, // Inst #1523 = tBKPT
+ { 1524, 1, 0, 0, "tBL", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList3, Barriers2, OperandInfo14 }, // Inst #1524 = tBL
+ { 1525, 1, 0, 0, "tBLXi", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList3, Barriers2, OperandInfo14 }, // Inst #1525 = tBLXi
+ { 1526, 1, 0, 0, "tBLXi_r9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList4, Barriers2, OperandInfo14 }, // Inst #1526 = tBLXi_r9
+ { 1527, 1, 0, 0, "tBLXr", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(4<<4)|(23<<9), NULL, ImplicitList3, Barriers2, OperandInfo16 }, // Inst #1527 = tBLXr
+ { 1528, 1, 0, 0, "tBLXr_r9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(4<<4)|(23<<9), NULL, ImplicitList4, Barriers2, OperandInfo16 }, // Inst #1528 = tBLXr_r9
+ { 1529, 1, 0, 0, "tBLr9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList4, Barriers2, OperandInfo14 }, // Inst #1529 = tBLr9
+ { 1530, 1, 0, 0, "tBRIND", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo16 }, // Inst #1530 = tBRIND
+ { 1531, 3, 0, 0, "tBR_JTr", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|(1<<4)|(23<<9), NULL, NULL, NULL, OperandInfo157 }, // Inst #1531 = tBR_JTr
+ { 1532, 1, 0, 0, "tBX", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList3, Barriers2, OperandInfo158 }, // Inst #1532 = tBX
+ { 1533, 0, 0, 0, "tBX_RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|(4<<4)|(23<<9), NULL, NULL, NULL, 0 }, // Inst #1533 = tBX_RET
+ { 1534, 1, 0, 0, "tBX_RET_vararg", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo158 }, // Inst #1534 = tBX_RET_vararg
+ { 1535, 1, 0, 0, "tBXr9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList4, Barriers2, OperandInfo158 }, // Inst #1535 = tBXr9
+ { 1536, 3, 0, 0, "tBcc", 0|(1<<TID::Branch)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #1536 = tBcc
+ { 1537, 1, 0, 0, "tBfar", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, ImplicitList8, NULL, OperandInfo14 }, // Inst #1537 = tBfar
+ { 1538, 2, 0, 0, "tCBNZ", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo151 }, // Inst #1538 = tCBNZ
+ { 1539, 2, 0, 0, "tCBZ", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo151 }, // Inst #1539 = tCBZ
+ { 1540, 4, 0, 98, "tCMNz", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo159 }, // Inst #1540 = tCMNz
+ { 1541, 4, 0, 98, "tCMPhir", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo24 }, // Inst #1541 = tCMPhir
+ { 1542, 4, 0, 97, "tCMPi8", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo160 }, // Inst #1542 = tCMPi8
+ { 1543, 4, 0, 98, "tCMPr", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo159 }, // Inst #1543 = tCMPr
+ { 1544, 4, 0, 98, "tCMPzhir", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo24 }, // Inst #1544 = tCMPzhir
+ { 1545, 4, 0, 97, "tCMPzi8", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo160 }, // Inst #1545 = tCMPzi8
+ { 1546, 4, 0, 98, "tCMPzr", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo159 }, // Inst #1546 = tCMPzr
+ { 1547, 6, 2, 89, "tEOR", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo148 }, // Inst #1547 = tEOR
+ { 1548, 2, 0, 128, "tInt_eh_sjlj_setjmp", 0, 0|(1<<4)|(23<<9), NULL, ImplicitList9, Barriers4, OperandInfo161 }, // Inst #1548 = tInt_eh_sjlj_setjmp
+ { 1549, 5, 0, 103, "tLDM", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1549 = tLDM
+ { 1550, 6, 1, 104, "tLDR", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|9|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo162 }, // Inst #1550 = tLDR
+ { 1551, 6, 1, 104, "tLDRB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|7|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo162 }, // Inst #1551 = tLDRB
+ { 1552, 6, 1, 104, "tLDRBi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|7|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo162 }, // Inst #1552 = tLDRBi
+ { 1553, 6, 1, 104, "tLDRH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|8|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo162 }, // Inst #1553 = tLDRH
+ { 1554, 6, 1, 104, "tLDRHi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|8|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo162 }, // Inst #1554 = tLDRHi
+ { 1555, 5, 1, 104, "tLDRSB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|7|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo163 }, // Inst #1555 = tLDRSB
+ { 1556, 5, 1, 104, "tLDRSH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|8|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo163 }, // Inst #1556 = tLDRSH
+ { 1557, 4, 1, 101, "tLDRcp", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::UnmodeledSideEffects), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo160 }, // Inst #1557 = tLDRcp
+ { 1558, 6, 1, 104, "tLDRi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|9|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo162 }, // Inst #1558 = tLDRi
+ { 1559, 4, 1, 101, "tLDRpci", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo160 }, // Inst #1559 = tLDRpci
+ { 1560, 3, 1, 128, "tLDRpci_pic", 0|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|(1<<4), NULL, NULL, NULL, OperandInfo19 }, // Inst #1560 = tLDRpci_pic
+ { 1561, 5, 1, 101, "tLDRspi", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo164 }, // Inst #1561 = tLDRspi
+ { 1562, 4, 1, 88, "tLEApcrel", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo160 }, // Inst #1562 = tLEApcrel
+ { 1563, 5, 1, 88, "tLEApcrelJT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo165 }, // Inst #1563 = tLEApcrelJT
+ { 1564, 6, 2, 113, "tLSLri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo149 }, // Inst #1564 = tLSLri
+ { 1565, 6, 2, 114, "tLSLrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo148 }, // Inst #1565 = tLSLrr
+ { 1566, 6, 2, 113, "tLSRri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo149 }, // Inst #1566 = tLSRri
+ { 1567, 6, 2, 114, "tLSRrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo148 }, // Inst #1567 = tLSRrr
+ { 1568, 5, 1, 93, "tMOVCCi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo166 }, // Inst #1568 = tMOVCCi
+ { 1569, 5, 1, 94, "tMOVCCr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo41 }, // Inst #1569 = tMOVCCr
+ { 1570, 5, 1, 128, "tMOVCCr_pseudo", 0|(1<<TID::Predicable)|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo163 }, // Inst #1570 = tMOVCCr_pseudo
+ { 1571, 2, 1, 112, "tMOVSr", 0, 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo161 }, // Inst #1571 = tMOVSr
+ { 1572, 2, 1, 112, "tMOVgpr2gpr", 0, 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo31 }, // Inst #1572 = tMOVgpr2gpr
+ { 1573, 2, 1, 112, "tMOVgpr2tgpr", 0, 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo167 }, // Inst #1573 = tMOVgpr2tgpr
+ { 1574, 5, 2, 111, "tMOVi8", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo168 }, // Inst #1574 = tMOVi8
+ { 1575, 2, 1, 112, "tMOVr", 0, 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo161 }, // Inst #1575 = tMOVr
+ { 1576, 2, 1, 112, "tMOVtgpr2gpr", 0, 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo142 }, // Inst #1576 = tMOVtgpr2gpr
+ { 1577, 6, 2, 116, "tMUL", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo148 }, // Inst #1577 = tMUL
+ { 1578, 5, 2, 112, "tMVN", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo169 }, // Inst #1578 = tMVN
+ { 1579, 6, 2, 89, "tORR", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo148 }, // Inst #1579 = tORR
+ { 1580, 3, 1, 89, "tPICADD", 0|(1<<TID::NotDuplicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo155 }, // Inst #1580 = tPICADD
+ { 1581, 3, 0, 0, "tPOP", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|(4<<4)|(23<<9), ImplicitList2, ImplicitList2, NULL, OperandInfo170 }, // Inst #1581 = tPOP
+ { 1582, 3, 0, 0, "tPOP_RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo170 }, // Inst #1582 = tPOP_RET
+ { 1583, 3, 0, 0, "tPUSH", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|(4<<4)|(23<<9), ImplicitList2, ImplicitList2, NULL, OperandInfo170 }, // Inst #1583 = tPUSH
+ { 1584, 4, 1, 125, "tREV", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo159 }, // Inst #1584 = tREV
+ { 1585, 4, 1, 125, "tREV16", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo159 }, // Inst #1585 = tREV16
+ { 1586, 4, 1, 125, "tREVSH", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo159 }, // Inst #1586 = tREVSH
+ { 1587, 6, 2, 114, "tROR", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo148 }, // Inst #1587 = tROR
+ { 1588, 5, 2, 88, "tRSB", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo169 }, // Inst #1588 = tRSB
+ { 1589, 5, 1, 101, "tRestore", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo164 }, // Inst #1589 = tRestore
+ { 1590, 6, 2, 89, "tSBC", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo148 }, // Inst #1590 = tSBC
+ { 1591, 5, 0, 120, "tSTM", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1591 = tSTM
+ { 1592, 6, 0, 121, "tSTR", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|9|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo162 }, // Inst #1592 = tSTR
+ { 1593, 6, 0, 121, "tSTRB", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|7|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo162 }, // Inst #1593 = tSTRB
+ { 1594, 6, 0, 121, "tSTRBi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|7|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo162 }, // Inst #1594 = tSTRBi
+ { 1595, 6, 0, 121, "tSTRH", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|8|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo162 }, // Inst #1595 = tSTRH
+ { 1596, 6, 0, 121, "tSTRHi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|8|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo162 }, // Inst #1596 = tSTRHi
+ { 1597, 6, 0, 121, "tSTRi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|9|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo162 }, // Inst #1597 = tSTRi
+ { 1598, 5, 0, 118, "tSTRspi", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo164 }, // Inst #1598 = tSTRspi
+ { 1599, 6, 2, 88, "tSUBi3", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo149 }, // Inst #1599 = tSUBi3
+ { 1600, 6, 2, 88, "tSUBi8", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo150 }, // Inst #1600 = tSUBi8
+ { 1601, 6, 2, 89, "tSUBrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo154 }, // Inst #1601 = tSUBrr
+ { 1602, 3, 1, 88, "tSUBspi", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo155 }, // Inst #1602 = tSUBspi
+ { 1603, 3, 1, 128, "tSUBspi_", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo2 }, // Inst #1603 = tSUBspi_
+ { 1604, 4, 1, 125, "tSXTB", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo159 }, // Inst #1604 = tSXTB
+ { 1605, 4, 1, 125, "tSXTH", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo159 }, // Inst #1605 = tSXTH
+ { 1606, 5, 0, 118, "tSpill", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo164 }, // Inst #1606 = tSpill
+ { 1607, 0, 0, 0, "tTPsoft", 0|(1<<TID::Call), 0|(3<<4)|(23<<9), NULL, ImplicitList10, NULL, 0 }, // Inst #1607 = tTPsoft
+ { 1608, 4, 0, 98, "tTST", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo159 }, // Inst #1608 = tTST
+ { 1609, 4, 1, 125, "tUXTB", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo159 }, // Inst #1609 = tUXTB
+ { 1610, 4, 1, 125, "tUXTH", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo159 }, // Inst #1610 = tUXTH
};
} // End llvm namespace
diff --git a/libclamav/c++/ARMGenInstrNames.inc b/libclamav/c++/ARMGenInstrNames.inc
index 6fe2c7f..223aa5c 100644
--- a/libclamav/c++/ARMGenInstrNames.inc
+++ b/libclamav/c++/ARMGenInstrNames.inc
@@ -21,7 +21,7 @@ namespace ARM {
IMPLICIT_DEF = 8,
SUBREG_TO_REG = 9,
COPY_TO_REGCLASS = 10,
- DEBUG_VALUE = 11,
+ DBG_VALUE = 11,
ADCSSri = 12,
ADCSSrr = 13,
ADCSSrs = 14,
@@ -68,1469 +68,1560 @@ namespace ARM {
BICri = 55,
BICrr = 56,
BICrs = 57,
- BL = 58,
- BLX = 59,
- BLXr9 = 60,
- BL_pred = 61,
- BLr9 = 62,
- BLr9_pred = 63,
- BRIND = 64,
- BR_JTadd = 65,
- BR_JTm = 66,
- BR_JTr = 67,
- BX = 68,
- BX_RET = 69,
- BXr9 = 70,
- Bcc = 71,
- CLZ = 72,
- CMNzri = 73,
- CMNzrr = 74,
- CMNzrs = 75,
- CMPri = 76,
- CMPrr = 77,
- CMPrs = 78,
- CMPzri = 79,
- CMPzrr = 80,
- CMPzrs = 81,
- CONSTPOOL_ENTRY = 82,
- EORri = 83,
- EORrr = 84,
- EORrs = 85,
- FCONSTD = 86,
- FCONSTS = 87,
- FMSTAT = 88,
- Int_MemBarrierV6 = 89,
- Int_MemBarrierV7 = 90,
- Int_SyncBarrierV6 = 91,
- Int_SyncBarrierV7 = 92,
- Int_eh_sjlj_setjmp = 93,
- LDM = 94,
- LDM_RET = 95,
- LDR = 96,
- LDRB = 97,
- LDRB_POST = 98,
- LDRB_PRE = 99,
- LDRD = 100,
- LDREX = 101,
- LDREXB = 102,
- LDREXD = 103,
- LDREXH = 104,
- LDRH = 105,
- LDRH_POST = 106,
- LDRH_PRE = 107,
- LDRSB = 108,
- LDRSB_POST = 109,
- LDRSB_PRE = 110,
- LDRSH = 111,
- LDRSH_POST = 112,
- LDRSH_PRE = 113,
- LDR_POST = 114,
- LDR_PRE = 115,
- LDRcp = 116,
- LEApcrel = 117,
- LEApcrelJT = 118,
- MLA = 119,
- MLS = 120,
- MOVCCi = 121,
- MOVCCr = 122,
- MOVCCs = 123,
- MOVTi16 = 124,
- MOVi = 125,
- MOVi16 = 126,
- MOVi2pieces = 127,
- MOVi32imm = 128,
- MOVr = 129,
- MOVrx = 130,
- MOVs = 131,
- MOVsra_flag = 132,
- MOVsrl_flag = 133,
- MUL = 134,
- MVNi = 135,
- MVNr = 136,
- MVNs = 137,
- ORRri = 138,
- ORRrr = 139,
- ORRrs = 140,
- PICADD = 141,
- PICLDR = 142,
- PICLDRB = 143,
- PICLDRH = 144,
- PICLDRSB = 145,
- PICLDRSH = 146,
- PICSTR = 147,
- PICSTRB = 148,
- PICSTRH = 149,
- PKHBT = 150,
- PKHTB = 151,
- RBIT = 152,
- REV = 153,
- REV16 = 154,
- REVSH = 155,
- RSBSri = 156,
- RSBSrs = 157,
- RSBri = 158,
- RSBrs = 159,
- RSCSri = 160,
- RSCSrs = 161,
- RSCri = 162,
- RSCrs = 163,
- SBCSSri = 164,
- SBCSSrr = 165,
- SBCSSrs = 166,
- SBCri = 167,
- SBCrr = 168,
- SBCrs = 169,
- SBFX = 170,
- SMLABB = 171,
- SMLABT = 172,
- SMLAL = 173,
- SMLATB = 174,
- SMLATT = 175,
- SMLAWB = 176,
- SMLAWT = 177,
- SMMLA = 178,
- SMMLS = 179,
- SMMUL = 180,
- SMULBB = 181,
- SMULBT = 182,
- SMULL = 183,
- SMULTB = 184,
- SMULTT = 185,
- SMULWB = 186,
- SMULWT = 187,
- STM = 188,
- STR = 189,
- STRB = 190,
- STRB_POST = 191,
- STRB_PRE = 192,
- STRD = 193,
- STREX = 194,
- STREXB = 195,
- STREXD = 196,
- STREXH = 197,
- STRH = 198,
- STRH_POST = 199,
- STRH_PRE = 200,
- STR_POST = 201,
- STR_PRE = 202,
- SUBSri = 203,
- SUBSrr = 204,
- SUBSrs = 205,
- SUBri = 206,
- SUBrr = 207,
- SUBrs = 208,
- SXTABrr = 209,
- SXTABrr_rot = 210,
- SXTAHrr = 211,
- SXTAHrr_rot = 212,
- SXTBr = 213,
- SXTBr_rot = 214,
- SXTHr = 215,
- SXTHr_rot = 216,
- TEQri = 217,
- TEQrr = 218,
- TEQrs = 219,
- TPsoft = 220,
- TSTri = 221,
- TSTrr = 222,
- TSTrs = 223,
- UBFX = 224,
- UMAAL = 225,
- UMLAL = 226,
- UMULL = 227,
- UXTABrr = 228,
- UXTABrr_rot = 229,
- UXTAHrr = 230,
- UXTAHrr_rot = 231,
- UXTB16r = 232,
- UXTB16r_rot = 233,
- UXTBr = 234,
- UXTBr_rot = 235,
- UXTHr = 236,
- UXTHr_rot = 237,
- VABALsv2i64 = 238,
- VABALsv4i32 = 239,
- VABALsv8i16 = 240,
- VABALuv2i64 = 241,
- VABALuv4i32 = 242,
- VABALuv8i16 = 243,
- VABAsv16i8 = 244,
- VABAsv2i32 = 245,
- VABAsv4i16 = 246,
- VABAsv4i32 = 247,
- VABAsv8i16 = 248,
- VABAsv8i8 = 249,
- VABAuv16i8 = 250,
- VABAuv2i32 = 251,
- VABAuv4i16 = 252,
- VABAuv4i32 = 253,
- VABAuv8i16 = 254,
- VABAuv8i8 = 255,
- VABDLsv2i64 = 256,
- VABDLsv4i32 = 257,
- VABDLsv8i16 = 258,
- VABDLuv2i64 = 259,
- VABDLuv4i32 = 260,
- VABDLuv8i16 = 261,
- VABDfd = 262,
- VABDfq = 263,
- VABDsv16i8 = 264,
- VABDsv2i32 = 265,
- VABDsv4i16 = 266,
- VABDsv4i32 = 267,
- VABDsv8i16 = 268,
- VABDsv8i8 = 269,
- VABDuv16i8 = 270,
- VABDuv2i32 = 271,
- VABDuv4i16 = 272,
- VABDuv4i32 = 273,
- VABDuv8i16 = 274,
- VABDuv8i8 = 275,
- VABSD = 276,
- VABSS = 277,
- VABSfd = 278,
- VABSfd_sfp = 279,
- VABSfq = 280,
- VABSv16i8 = 281,
- VABSv2i32 = 282,
- VABSv4i16 = 283,
- VABSv4i32 = 284,
- VABSv8i16 = 285,
- VABSv8i8 = 286,
- VACGEd = 287,
- VACGEq = 288,
- VACGTd = 289,
- VACGTq = 290,
- VADDD = 291,
- VADDHNv2i32 = 292,
- VADDHNv4i16 = 293,
- VADDHNv8i8 = 294,
- VADDLsv2i64 = 295,
- VADDLsv4i32 = 296,
- VADDLsv8i16 = 297,
- VADDLuv2i64 = 298,
- VADDLuv4i32 = 299,
- VADDLuv8i16 = 300,
- VADDS = 301,
- VADDWsv2i64 = 302,
- VADDWsv4i32 = 303,
- VADDWsv8i16 = 304,
- VADDWuv2i64 = 305,
- VADDWuv4i32 = 306,
- VADDWuv8i16 = 307,
- VADDfd = 308,
- VADDfd_sfp = 309,
- VADDfq = 310,
- VADDv16i8 = 311,
- VADDv1i64 = 312,
- VADDv2i32 = 313,
- VADDv2i64 = 314,
- VADDv4i16 = 315,
- VADDv4i32 = 316,
- VADDv8i16 = 317,
- VADDv8i8 = 318,
- VANDd = 319,
- VANDq = 320,
- VBICd = 321,
- VBICq = 322,
- VBSLd = 323,
- VBSLq = 324,
- VCEQfd = 325,
- VCEQfq = 326,
- VCEQv16i8 = 327,
- VCEQv2i32 = 328,
- VCEQv4i16 = 329,
- VCEQv4i32 = 330,
- VCEQv8i16 = 331,
- VCEQv8i8 = 332,
- VCGEfd = 333,
- VCGEfq = 334,
- VCGEsv16i8 = 335,
- VCGEsv2i32 = 336,
- VCGEsv4i16 = 337,
- VCGEsv4i32 = 338,
- VCGEsv8i16 = 339,
- VCGEsv8i8 = 340,
- VCGEuv16i8 = 341,
- VCGEuv2i32 = 342,
- VCGEuv4i16 = 343,
- VCGEuv4i32 = 344,
- VCGEuv8i16 = 345,
- VCGEuv8i8 = 346,
- VCGTfd = 347,
- VCGTfq = 348,
- VCGTsv16i8 = 349,
- VCGTsv2i32 = 350,
- VCGTsv4i16 = 351,
- VCGTsv4i32 = 352,
- VCGTsv8i16 = 353,
- VCGTsv8i8 = 354,
- VCGTuv16i8 = 355,
- VCGTuv2i32 = 356,
- VCGTuv4i16 = 357,
- VCGTuv4i32 = 358,
- VCGTuv8i16 = 359,
- VCGTuv8i8 = 360,
- VCLSv16i8 = 361,
- VCLSv2i32 = 362,
- VCLSv4i16 = 363,
- VCLSv4i32 = 364,
- VCLSv8i16 = 365,
- VCLSv8i8 = 366,
- VCLZv16i8 = 367,
- VCLZv2i32 = 368,
- VCLZv4i16 = 369,
- VCLZv4i32 = 370,
- VCLZv8i16 = 371,
- VCLZv8i8 = 372,
- VCMPED = 373,
- VCMPES = 374,
- VCMPEZD = 375,
- VCMPEZS = 376,
- VCNTd = 377,
- VCNTq = 378,
- VCVTDS = 379,
- VCVTSD = 380,
- VCVTf2sd = 381,
- VCVTf2sd_sfp = 382,
- VCVTf2sq = 383,
- VCVTf2ud = 384,
- VCVTf2ud_sfp = 385,
- VCVTf2uq = 386,
- VCVTf2xsd = 387,
- VCVTf2xsq = 388,
- VCVTf2xud = 389,
- VCVTf2xuq = 390,
- VCVTs2fd = 391,
- VCVTs2fd_sfp = 392,
- VCVTs2fq = 393,
- VCVTu2fd = 394,
- VCVTu2fd_sfp = 395,
- VCVTu2fq = 396,
- VCVTxs2fd = 397,
- VCVTxs2fq = 398,
- VCVTxu2fd = 399,
- VCVTxu2fq = 400,
- VDIVD = 401,
- VDIVS = 402,
- VDUP16d = 403,
- VDUP16q = 404,
- VDUP32d = 405,
- VDUP32q = 406,
- VDUP8d = 407,
- VDUP8q = 408,
- VDUPLN16d = 409,
- VDUPLN16q = 410,
- VDUPLN32d = 411,
- VDUPLN32q = 412,
- VDUPLN8d = 413,
- VDUPLN8q = 414,
- VDUPLNfd = 415,
- VDUPLNfq = 416,
- VDUPfd = 417,
- VDUPfdf = 418,
- VDUPfq = 419,
- VDUPfqf = 420,
- VEORd = 421,
- VEORq = 422,
- VEXTd16 = 423,
- VEXTd32 = 424,
- VEXTd8 = 425,
- VEXTdf = 426,
- VEXTq16 = 427,
- VEXTq32 = 428,
- VEXTq8 = 429,
- VEXTqf = 430,
- VGETLNi32 = 431,
- VGETLNs16 = 432,
- VGETLNs8 = 433,
- VGETLNu16 = 434,
- VGETLNu8 = 435,
- VHADDsv16i8 = 436,
- VHADDsv2i32 = 437,
- VHADDsv4i16 = 438,
- VHADDsv4i32 = 439,
- VHADDsv8i16 = 440,
- VHADDsv8i8 = 441,
- VHADDuv16i8 = 442,
- VHADDuv2i32 = 443,
- VHADDuv4i16 = 444,
- VHADDuv4i32 = 445,
- VHADDuv8i16 = 446,
- VHADDuv8i8 = 447,
- VHSUBsv16i8 = 448,
- VHSUBsv2i32 = 449,
- VHSUBsv4i16 = 450,
- VHSUBsv4i32 = 451,
- VHSUBsv8i16 = 452,
- VHSUBsv8i8 = 453,
- VHSUBuv16i8 = 454,
- VHSUBuv2i32 = 455,
- VHSUBuv4i16 = 456,
- VHSUBuv4i32 = 457,
- VHSUBuv8i16 = 458,
- VHSUBuv8i8 = 459,
- VLD1d16 = 460,
- VLD1d32 = 461,
- VLD1d64 = 462,
- VLD1d8 = 463,
- VLD1df = 464,
- VLD1q16 = 465,
- VLD1q32 = 466,
- VLD1q64 = 467,
- VLD1q8 = 468,
- VLD1qf = 469,
- VLD2LNd16 = 470,
- VLD2LNd32 = 471,
- VLD2LNd8 = 472,
- VLD2LNq16a = 473,
- VLD2LNq16b = 474,
- VLD2LNq32a = 475,
- VLD2LNq32b = 476,
- VLD2d16 = 477,
- VLD2d32 = 478,
- VLD2d64 = 479,
- VLD2d8 = 480,
- VLD2q16 = 481,
- VLD2q32 = 482,
- VLD2q8 = 483,
- VLD3LNd16 = 484,
- VLD3LNd32 = 485,
- VLD3LNd8 = 486,
- VLD3LNq16a = 487,
- VLD3LNq16b = 488,
- VLD3LNq32a = 489,
- VLD3LNq32b = 490,
- VLD3d16 = 491,
- VLD3d32 = 492,
- VLD3d64 = 493,
- VLD3d8 = 494,
- VLD3q16a = 495,
- VLD3q16b = 496,
- VLD3q32a = 497,
- VLD3q32b = 498,
- VLD3q8a = 499,
- VLD3q8b = 500,
- VLD4LNd16 = 501,
- VLD4LNd32 = 502,
- VLD4LNd8 = 503,
- VLD4LNq16a = 504,
- VLD4LNq16b = 505,
- VLD4LNq32a = 506,
- VLD4LNq32b = 507,
- VLD4d16 = 508,
- VLD4d32 = 509,
- VLD4d64 = 510,
- VLD4d8 = 511,
- VLD4q16a = 512,
- VLD4q16b = 513,
- VLD4q32a = 514,
- VLD4q32b = 515,
- VLD4q8a = 516,
- VLD4q8b = 517,
- VLDMD = 518,
- VLDMS = 519,
- VLDRD = 520,
- VLDRQ = 521,
- VLDRS = 522,
- VMAXfd = 523,
- VMAXfq = 524,
- VMAXsv16i8 = 525,
- VMAXsv2i32 = 526,
- VMAXsv4i16 = 527,
- VMAXsv4i32 = 528,
- VMAXsv8i16 = 529,
- VMAXsv8i8 = 530,
- VMAXuv16i8 = 531,
- VMAXuv2i32 = 532,
- VMAXuv4i16 = 533,
- VMAXuv4i32 = 534,
- VMAXuv8i16 = 535,
- VMAXuv8i8 = 536,
- VMINfd = 537,
- VMINfq = 538,
- VMINsv16i8 = 539,
- VMINsv2i32 = 540,
- VMINsv4i16 = 541,
- VMINsv4i32 = 542,
- VMINsv8i16 = 543,
- VMINsv8i8 = 544,
- VMINuv16i8 = 545,
- VMINuv2i32 = 546,
- VMINuv4i16 = 547,
- VMINuv4i32 = 548,
- VMINuv8i16 = 549,
- VMINuv8i8 = 550,
- VMLAD = 551,
- VMLALslsv2i32 = 552,
- VMLALslsv4i16 = 553,
- VMLALsluv2i32 = 554,
- VMLALsluv4i16 = 555,
- VMLALsv2i64 = 556,
- VMLALsv4i32 = 557,
- VMLALsv8i16 = 558,
- VMLALuv2i64 = 559,
- VMLALuv4i32 = 560,
- VMLALuv8i16 = 561,
- VMLAS = 562,
- VMLAfd = 563,
- VMLAfq = 564,
- VMLAslfd = 565,
- VMLAslfq = 566,
- VMLAslv2i32 = 567,
- VMLAslv4i16 = 568,
- VMLAslv4i32 = 569,
- VMLAslv8i16 = 570,
- VMLAv16i8 = 571,
- VMLAv2i32 = 572,
- VMLAv4i16 = 573,
- VMLAv4i32 = 574,
- VMLAv8i16 = 575,
- VMLAv8i8 = 576,
- VMLSD = 577,
- VMLSLslsv2i32 = 578,
- VMLSLslsv4i16 = 579,
- VMLSLsluv2i32 = 580,
- VMLSLsluv4i16 = 581,
- VMLSLsv2i64 = 582,
- VMLSLsv4i32 = 583,
- VMLSLsv8i16 = 584,
- VMLSLuv2i64 = 585,
- VMLSLuv4i32 = 586,
- VMLSLuv8i16 = 587,
- VMLSS = 588,
- VMLSfd = 589,
- VMLSfq = 590,
- VMLSslfd = 591,
- VMLSslfq = 592,
- VMLSslv2i32 = 593,
- VMLSslv4i16 = 594,
- VMLSslv4i32 = 595,
- VMLSslv8i16 = 596,
- VMLSv16i8 = 597,
- VMLSv2i32 = 598,
- VMLSv4i16 = 599,
- VMLSv4i32 = 600,
- VMLSv8i16 = 601,
- VMLSv8i8 = 602,
- VMOVD = 603,
- VMOVDRR = 604,
- VMOVDcc = 605,
- VMOVDneon = 606,
- VMOVLsv2i64 = 607,
- VMOVLsv4i32 = 608,
- VMOVLsv8i16 = 609,
- VMOVLuv2i64 = 610,
- VMOVLuv4i32 = 611,
- VMOVLuv8i16 = 612,
- VMOVNv2i32 = 613,
- VMOVNv4i16 = 614,
- VMOVNv8i8 = 615,
- VMOVQ = 616,
- VMOVRRD = 617,
- VMOVRS = 618,
- VMOVS = 619,
- VMOVSR = 620,
- VMOVScc = 621,
- VMOVv16i8 = 622,
- VMOVv1i64 = 623,
- VMOVv2i32 = 624,
- VMOVv2i64 = 625,
- VMOVv4i16 = 626,
- VMOVv4i32 = 627,
- VMOVv8i16 = 628,
- VMOVv8i8 = 629,
- VMULD = 630,
- VMULLp = 631,
- VMULLslsv2i32 = 632,
- VMULLslsv4i16 = 633,
- VMULLsluv2i32 = 634,
- VMULLsluv4i16 = 635,
- VMULLsv2i64 = 636,
- VMULLsv4i32 = 637,
- VMULLsv8i16 = 638,
- VMULLuv2i64 = 639,
- VMULLuv4i32 = 640,
- VMULLuv8i16 = 641,
- VMULS = 642,
- VMULfd = 643,
- VMULfd_sfp = 644,
- VMULfq = 645,
- VMULpd = 646,
- VMULpq = 647,
- VMULslfd = 648,
- VMULslfq = 649,
- VMULslv2i32 = 650,
- VMULslv4i16 = 651,
- VMULslv4i32 = 652,
- VMULslv8i16 = 653,
- VMULv16i8 = 654,
- VMULv2i32 = 655,
- VMULv4i16 = 656,
- VMULv4i32 = 657,
- VMULv8i16 = 658,
- VMULv8i8 = 659,
- VMVNd = 660,
- VMVNq = 661,
- VNEGD = 662,
- VNEGDcc = 663,
- VNEGS = 664,
- VNEGScc = 665,
- VNEGf32d = 666,
- VNEGf32d_sfp = 667,
- VNEGf32q = 668,
- VNEGs16d = 669,
- VNEGs16q = 670,
- VNEGs32d = 671,
- VNEGs32q = 672,
- VNEGs8d = 673,
- VNEGs8q = 674,
- VNMLAD = 675,
- VNMLAS = 676,
- VNMLSD = 677,
- VNMLSS = 678,
- VNMULD = 679,
- VNMULS = 680,
- VORNd = 681,
- VORNq = 682,
- VORRd = 683,
- VORRq = 684,
- VPADALsv16i8 = 685,
- VPADALsv2i32 = 686,
- VPADALsv4i16 = 687,
- VPADALsv4i32 = 688,
- VPADALsv8i16 = 689,
- VPADALsv8i8 = 690,
- VPADALuv16i8 = 691,
- VPADALuv2i32 = 692,
- VPADALuv4i16 = 693,
- VPADALuv4i32 = 694,
- VPADALuv8i16 = 695,
- VPADALuv8i8 = 696,
- VPADDLsv16i8 = 697,
- VPADDLsv2i32 = 698,
- VPADDLsv4i16 = 699,
- VPADDLsv4i32 = 700,
- VPADDLsv8i16 = 701,
- VPADDLsv8i8 = 702,
- VPADDLuv16i8 = 703,
- VPADDLuv2i32 = 704,
- VPADDLuv4i16 = 705,
- VPADDLuv4i32 = 706,
- VPADDLuv8i16 = 707,
- VPADDLuv8i8 = 708,
- VPADDf = 709,
- VPADDi16 = 710,
- VPADDi32 = 711,
- VPADDi8 = 712,
- VPMAXf = 713,
- VPMAXs16 = 714,
- VPMAXs32 = 715,
- VPMAXs8 = 716,
- VPMAXu16 = 717,
- VPMAXu32 = 718,
- VPMAXu8 = 719,
- VPMINf = 720,
- VPMINs16 = 721,
- VPMINs32 = 722,
- VPMINs8 = 723,
- VPMINu16 = 724,
- VPMINu32 = 725,
- VPMINu8 = 726,
- VQABSv16i8 = 727,
- VQABSv2i32 = 728,
- VQABSv4i16 = 729,
- VQABSv4i32 = 730,
- VQABSv8i16 = 731,
- VQABSv8i8 = 732,
- VQADDsv16i8 = 733,
- VQADDsv1i64 = 734,
- VQADDsv2i32 = 735,
- VQADDsv2i64 = 736,
- VQADDsv4i16 = 737,
- VQADDsv4i32 = 738,
- VQADDsv8i16 = 739,
- VQADDsv8i8 = 740,
- VQADDuv16i8 = 741,
- VQADDuv1i64 = 742,
- VQADDuv2i32 = 743,
- VQADDuv2i64 = 744,
- VQADDuv4i16 = 745,
- VQADDuv4i32 = 746,
- VQADDuv8i16 = 747,
- VQADDuv8i8 = 748,
- VQDMLALslv2i32 = 749,
- VQDMLALslv4i16 = 750,
- VQDMLALv2i64 = 751,
- VQDMLALv4i32 = 752,
- VQDMLSLslv2i32 = 753,
- VQDMLSLslv4i16 = 754,
- VQDMLSLv2i64 = 755,
- VQDMLSLv4i32 = 756,
- VQDMULHslv2i32 = 757,
- VQDMULHslv4i16 = 758,
- VQDMULHslv4i32 = 759,
- VQDMULHslv8i16 = 760,
- VQDMULHv2i32 = 761,
- VQDMULHv4i16 = 762,
- VQDMULHv4i32 = 763,
- VQDMULHv8i16 = 764,
- VQDMULLslv2i32 = 765,
- VQDMULLslv4i16 = 766,
- VQDMULLv2i64 = 767,
- VQDMULLv4i32 = 768,
- VQMOVNsuv2i32 = 769,
- VQMOVNsuv4i16 = 770,
- VQMOVNsuv8i8 = 771,
- VQMOVNsv2i32 = 772,
- VQMOVNsv4i16 = 773,
- VQMOVNsv8i8 = 774,
- VQMOVNuv2i32 = 775,
- VQMOVNuv4i16 = 776,
- VQMOVNuv8i8 = 777,
- VQNEGv16i8 = 778,
- VQNEGv2i32 = 779,
- VQNEGv4i16 = 780,
- VQNEGv4i32 = 781,
- VQNEGv8i16 = 782,
- VQNEGv8i8 = 783,
- VQRDMULHslv2i32 = 784,
- VQRDMULHslv4i16 = 785,
- VQRDMULHslv4i32 = 786,
- VQRDMULHslv8i16 = 787,
- VQRDMULHv2i32 = 788,
- VQRDMULHv4i16 = 789,
- VQRDMULHv4i32 = 790,
- VQRDMULHv8i16 = 791,
- VQRSHLsv16i8 = 792,
- VQRSHLsv1i64 = 793,
- VQRSHLsv2i32 = 794,
- VQRSHLsv2i64 = 795,
- VQRSHLsv4i16 = 796,
- VQRSHLsv4i32 = 797,
- VQRSHLsv8i16 = 798,
- VQRSHLsv8i8 = 799,
- VQRSHLuv16i8 = 800,
- VQRSHLuv1i64 = 801,
- VQRSHLuv2i32 = 802,
- VQRSHLuv2i64 = 803,
- VQRSHLuv4i16 = 804,
- VQRSHLuv4i32 = 805,
- VQRSHLuv8i16 = 806,
- VQRSHLuv8i8 = 807,
- VQRSHRNsv2i32 = 808,
- VQRSHRNsv4i16 = 809,
- VQRSHRNsv8i8 = 810,
- VQRSHRNuv2i32 = 811,
- VQRSHRNuv4i16 = 812,
- VQRSHRNuv8i8 = 813,
- VQRSHRUNv2i32 = 814,
- VQRSHRUNv4i16 = 815,
- VQRSHRUNv8i8 = 816,
- VQSHLsiv16i8 = 817,
- VQSHLsiv1i64 = 818,
- VQSHLsiv2i32 = 819,
- VQSHLsiv2i64 = 820,
- VQSHLsiv4i16 = 821,
- VQSHLsiv4i32 = 822,
- VQSHLsiv8i16 = 823,
- VQSHLsiv8i8 = 824,
- VQSHLsuv16i8 = 825,
- VQSHLsuv1i64 = 826,
- VQSHLsuv2i32 = 827,
- VQSHLsuv2i64 = 828,
- VQSHLsuv4i16 = 829,
- VQSHLsuv4i32 = 830,
- VQSHLsuv8i16 = 831,
- VQSHLsuv8i8 = 832,
- VQSHLsv16i8 = 833,
- VQSHLsv1i64 = 834,
- VQSHLsv2i32 = 835,
- VQSHLsv2i64 = 836,
- VQSHLsv4i16 = 837,
- VQSHLsv4i32 = 838,
- VQSHLsv8i16 = 839,
- VQSHLsv8i8 = 840,
- VQSHLuiv16i8 = 841,
- VQSHLuiv1i64 = 842,
- VQSHLuiv2i32 = 843,
- VQSHLuiv2i64 = 844,
- VQSHLuiv4i16 = 845,
- VQSHLuiv4i32 = 846,
- VQSHLuiv8i16 = 847,
- VQSHLuiv8i8 = 848,
- VQSHLuv16i8 = 849,
- VQSHLuv1i64 = 850,
- VQSHLuv2i32 = 851,
- VQSHLuv2i64 = 852,
- VQSHLuv4i16 = 853,
- VQSHLuv4i32 = 854,
- VQSHLuv8i16 = 855,
- VQSHLuv8i8 = 856,
- VQSHRNsv2i32 = 857,
- VQSHRNsv4i16 = 858,
- VQSHRNsv8i8 = 859,
- VQSHRNuv2i32 = 860,
- VQSHRNuv4i16 = 861,
- VQSHRNuv8i8 = 862,
- VQSHRUNv2i32 = 863,
- VQSHRUNv4i16 = 864,
- VQSHRUNv8i8 = 865,
- VQSUBsv16i8 = 866,
- VQSUBsv1i64 = 867,
- VQSUBsv2i32 = 868,
- VQSUBsv2i64 = 869,
- VQSUBsv4i16 = 870,
- VQSUBsv4i32 = 871,
- VQSUBsv8i16 = 872,
- VQSUBsv8i8 = 873,
- VQSUBuv16i8 = 874,
- VQSUBuv1i64 = 875,
- VQSUBuv2i32 = 876,
- VQSUBuv2i64 = 877,
- VQSUBuv4i16 = 878,
- VQSUBuv4i32 = 879,
- VQSUBuv8i16 = 880,
- VQSUBuv8i8 = 881,
- VRADDHNv2i32 = 882,
- VRADDHNv4i16 = 883,
- VRADDHNv8i8 = 884,
- VRECPEd = 885,
- VRECPEfd = 886,
- VRECPEfq = 887,
- VRECPEq = 888,
- VRECPSfd = 889,
- VRECPSfq = 890,
- VREV16d8 = 891,
- VREV16q8 = 892,
- VREV32d16 = 893,
- VREV32d8 = 894,
- VREV32q16 = 895,
- VREV32q8 = 896,
- VREV64d16 = 897,
- VREV64d32 = 898,
- VREV64d8 = 899,
- VREV64df = 900,
- VREV64q16 = 901,
- VREV64q32 = 902,
- VREV64q8 = 903,
- VREV64qf = 904,
- VRHADDsv16i8 = 905,
- VRHADDsv2i32 = 906,
- VRHADDsv4i16 = 907,
- VRHADDsv4i32 = 908,
- VRHADDsv8i16 = 909,
- VRHADDsv8i8 = 910,
- VRHADDuv16i8 = 911,
- VRHADDuv2i32 = 912,
- VRHADDuv4i16 = 913,
- VRHADDuv4i32 = 914,
- VRHADDuv8i16 = 915,
- VRHADDuv8i8 = 916,
- VRSHLsv16i8 = 917,
- VRSHLsv1i64 = 918,
- VRSHLsv2i32 = 919,
- VRSHLsv2i64 = 920,
- VRSHLsv4i16 = 921,
- VRSHLsv4i32 = 922,
- VRSHLsv8i16 = 923,
- VRSHLsv8i8 = 924,
- VRSHLuv16i8 = 925,
- VRSHLuv1i64 = 926,
- VRSHLuv2i32 = 927,
- VRSHLuv2i64 = 928,
- VRSHLuv4i16 = 929,
- VRSHLuv4i32 = 930,
- VRSHLuv8i16 = 931,
- VRSHLuv8i8 = 932,
- VRSHRNv2i32 = 933,
- VRSHRNv4i16 = 934,
- VRSHRNv8i8 = 935,
- VRSHRsv16i8 = 936,
- VRSHRsv1i64 = 937,
- VRSHRsv2i32 = 938,
- VRSHRsv2i64 = 939,
- VRSHRsv4i16 = 940,
- VRSHRsv4i32 = 941,
- VRSHRsv8i16 = 942,
- VRSHRsv8i8 = 943,
- VRSHRuv16i8 = 944,
- VRSHRuv1i64 = 945,
- VRSHRuv2i32 = 946,
- VRSHRuv2i64 = 947,
- VRSHRuv4i16 = 948,
- VRSHRuv4i32 = 949,
- VRSHRuv8i16 = 950,
- VRSHRuv8i8 = 951,
- VRSQRTEd = 952,
- VRSQRTEfd = 953,
- VRSQRTEfq = 954,
- VRSQRTEq = 955,
- VRSQRTSfd = 956,
- VRSQRTSfq = 957,
- VRSRAsv16i8 = 958,
- VRSRAsv1i64 = 959,
- VRSRAsv2i32 = 960,
- VRSRAsv2i64 = 961,
- VRSRAsv4i16 = 962,
- VRSRAsv4i32 = 963,
- VRSRAsv8i16 = 964,
- VRSRAsv8i8 = 965,
- VRSRAuv16i8 = 966,
- VRSRAuv1i64 = 967,
- VRSRAuv2i32 = 968,
- VRSRAuv2i64 = 969,
- VRSRAuv4i16 = 970,
- VRSRAuv4i32 = 971,
- VRSRAuv8i16 = 972,
- VRSRAuv8i8 = 973,
- VRSUBHNv2i32 = 974,
- VRSUBHNv4i16 = 975,
- VRSUBHNv8i8 = 976,
- VSETLNi16 = 977,
- VSETLNi32 = 978,
- VSETLNi8 = 979,
- VSHLLi16 = 980,
- VSHLLi32 = 981,
- VSHLLi8 = 982,
- VSHLLsv2i64 = 983,
- VSHLLsv4i32 = 984,
- VSHLLsv8i16 = 985,
- VSHLLuv2i64 = 986,
- VSHLLuv4i32 = 987,
- VSHLLuv8i16 = 988,
- VSHLiv16i8 = 989,
- VSHLiv1i64 = 990,
- VSHLiv2i32 = 991,
- VSHLiv2i64 = 992,
- VSHLiv4i16 = 993,
- VSHLiv4i32 = 994,
- VSHLiv8i16 = 995,
- VSHLiv8i8 = 996,
- VSHLsv16i8 = 997,
- VSHLsv1i64 = 998,
- VSHLsv2i32 = 999,
- VSHLsv2i64 = 1000,
- VSHLsv4i16 = 1001,
- VSHLsv4i32 = 1002,
- VSHLsv8i16 = 1003,
- VSHLsv8i8 = 1004,
- VSHLuv16i8 = 1005,
- VSHLuv1i64 = 1006,
- VSHLuv2i32 = 1007,
- VSHLuv2i64 = 1008,
- VSHLuv4i16 = 1009,
- VSHLuv4i32 = 1010,
- VSHLuv8i16 = 1011,
- VSHLuv8i8 = 1012,
- VSHRNv2i32 = 1013,
- VSHRNv4i16 = 1014,
- VSHRNv8i8 = 1015,
- VSHRsv16i8 = 1016,
- VSHRsv1i64 = 1017,
- VSHRsv2i32 = 1018,
- VSHRsv2i64 = 1019,
- VSHRsv4i16 = 1020,
- VSHRsv4i32 = 1021,
- VSHRsv8i16 = 1022,
- VSHRsv8i8 = 1023,
- VSHRuv16i8 = 1024,
- VSHRuv1i64 = 1025,
- VSHRuv2i32 = 1026,
- VSHRuv2i64 = 1027,
- VSHRuv4i16 = 1028,
- VSHRuv4i32 = 1029,
- VSHRuv8i16 = 1030,
- VSHRuv8i8 = 1031,
- VSITOD = 1032,
- VSITOS = 1033,
- VSLIv16i8 = 1034,
- VSLIv1i64 = 1035,
- VSLIv2i32 = 1036,
- VSLIv2i64 = 1037,
- VSLIv4i16 = 1038,
- VSLIv4i32 = 1039,
- VSLIv8i16 = 1040,
- VSLIv8i8 = 1041,
- VSQRTD = 1042,
- VSQRTS = 1043,
- VSRAsv16i8 = 1044,
- VSRAsv1i64 = 1045,
- VSRAsv2i32 = 1046,
- VSRAsv2i64 = 1047,
- VSRAsv4i16 = 1048,
- VSRAsv4i32 = 1049,
- VSRAsv8i16 = 1050,
- VSRAsv8i8 = 1051,
- VSRAuv16i8 = 1052,
- VSRAuv1i64 = 1053,
- VSRAuv2i32 = 1054,
- VSRAuv2i64 = 1055,
- VSRAuv4i16 = 1056,
- VSRAuv4i32 = 1057,
- VSRAuv8i16 = 1058,
- VSRAuv8i8 = 1059,
- VSRIv16i8 = 1060,
- VSRIv1i64 = 1061,
- VSRIv2i32 = 1062,
- VSRIv2i64 = 1063,
- VSRIv4i16 = 1064,
- VSRIv4i32 = 1065,
- VSRIv8i16 = 1066,
- VSRIv8i8 = 1067,
- VST1d16 = 1068,
- VST1d32 = 1069,
- VST1d64 = 1070,
- VST1d8 = 1071,
- VST1df = 1072,
- VST1q16 = 1073,
- VST1q32 = 1074,
- VST1q64 = 1075,
- VST1q8 = 1076,
- VST1qf = 1077,
- VST2LNd16 = 1078,
- VST2LNd32 = 1079,
- VST2LNd8 = 1080,
- VST2LNq16a = 1081,
- VST2LNq16b = 1082,
- VST2LNq32a = 1083,
- VST2LNq32b = 1084,
- VST2d16 = 1085,
- VST2d32 = 1086,
- VST2d64 = 1087,
- VST2d8 = 1088,
- VST2q16 = 1089,
- VST2q32 = 1090,
- VST2q8 = 1091,
- VST3LNd16 = 1092,
- VST3LNd32 = 1093,
- VST3LNd8 = 1094,
- VST3LNq16a = 1095,
- VST3LNq16b = 1096,
- VST3LNq32a = 1097,
- VST3LNq32b = 1098,
- VST3d16 = 1099,
- VST3d32 = 1100,
- VST3d64 = 1101,
- VST3d8 = 1102,
- VST3q16a = 1103,
- VST3q16b = 1104,
- VST3q32a = 1105,
- VST3q32b = 1106,
- VST3q8a = 1107,
- VST3q8b = 1108,
- VST4LNd16 = 1109,
- VST4LNd32 = 1110,
- VST4LNd8 = 1111,
- VST4LNq16a = 1112,
- VST4LNq16b = 1113,
- VST4LNq32a = 1114,
- VST4LNq32b = 1115,
- VST4d16 = 1116,
- VST4d32 = 1117,
- VST4d64 = 1118,
- VST4d8 = 1119,
- VST4q16a = 1120,
- VST4q16b = 1121,
- VST4q32a = 1122,
- VST4q32b = 1123,
- VST4q8a = 1124,
- VST4q8b = 1125,
- VSTMD = 1126,
- VSTMS = 1127,
- VSTRD = 1128,
- VSTRQ = 1129,
- VSTRS = 1130,
- VSUBD = 1131,
- VSUBHNv2i32 = 1132,
- VSUBHNv4i16 = 1133,
- VSUBHNv8i8 = 1134,
- VSUBLsv2i64 = 1135,
- VSUBLsv4i32 = 1136,
- VSUBLsv8i16 = 1137,
- VSUBLuv2i64 = 1138,
- VSUBLuv4i32 = 1139,
- VSUBLuv8i16 = 1140,
- VSUBS = 1141,
- VSUBWsv2i64 = 1142,
- VSUBWsv4i32 = 1143,
- VSUBWsv8i16 = 1144,
- VSUBWuv2i64 = 1145,
- VSUBWuv4i32 = 1146,
- VSUBWuv8i16 = 1147,
- VSUBfd = 1148,
- VSUBfd_sfp = 1149,
- VSUBfq = 1150,
- VSUBv16i8 = 1151,
- VSUBv1i64 = 1152,
- VSUBv2i32 = 1153,
- VSUBv2i64 = 1154,
- VSUBv4i16 = 1155,
- VSUBv4i32 = 1156,
- VSUBv8i16 = 1157,
- VSUBv8i8 = 1158,
- VTBL1 = 1159,
- VTBL2 = 1160,
- VTBL3 = 1161,
- VTBL4 = 1162,
- VTBX1 = 1163,
- VTBX2 = 1164,
- VTBX3 = 1165,
- VTBX4 = 1166,
- VTOSIZD = 1167,
- VTOSIZS = 1168,
- VTOUIZD = 1169,
- VTOUIZS = 1170,
- VTRNd16 = 1171,
- VTRNd32 = 1172,
- VTRNd8 = 1173,
- VTRNq16 = 1174,
- VTRNq32 = 1175,
- VTRNq8 = 1176,
- VTSTv16i8 = 1177,
- VTSTv2i32 = 1178,
- VTSTv4i16 = 1179,
- VTSTv4i32 = 1180,
- VTSTv8i16 = 1181,
- VTSTv8i8 = 1182,
- VUITOD = 1183,
- VUITOS = 1184,
- VUZPd16 = 1185,
- VUZPd32 = 1186,
- VUZPd8 = 1187,
- VUZPq16 = 1188,
- VUZPq32 = 1189,
- VUZPq8 = 1190,
- VZIPd16 = 1191,
- VZIPd32 = 1192,
- VZIPd8 = 1193,
- VZIPq16 = 1194,
- VZIPq32 = 1195,
- VZIPq8 = 1196,
- t2ADCSri = 1197,
- t2ADCSrr = 1198,
- t2ADCSrs = 1199,
- t2ADCri = 1200,
- t2ADCrr = 1201,
- t2ADCrs = 1202,
- t2ADDSri = 1203,
- t2ADDSrr = 1204,
- t2ADDSrs = 1205,
- t2ADDrSPi = 1206,
- t2ADDrSPi12 = 1207,
- t2ADDrSPs = 1208,
- t2ADDri = 1209,
- t2ADDri12 = 1210,
- t2ADDrr = 1211,
- t2ADDrs = 1212,
- t2ANDri = 1213,
- t2ANDrr = 1214,
- t2ANDrs = 1215,
- t2ASRri = 1216,
- t2ASRrr = 1217,
- t2B = 1218,
- t2BFC = 1219,
- t2BICri = 1220,
- t2BICrr = 1221,
- t2BICrs = 1222,
- t2BR_JT = 1223,
- t2Bcc = 1224,
- t2CLZ = 1225,
- t2CMNzri = 1226,
- t2CMNzrr = 1227,
- t2CMNzrs = 1228,
- t2CMPri = 1229,
- t2CMPrr = 1230,
- t2CMPrs = 1231,
- t2CMPzri = 1232,
- t2CMPzrr = 1233,
- t2CMPzrs = 1234,
- t2EORri = 1235,
- t2EORrr = 1236,
- t2EORrs = 1237,
- t2IT = 1238,
- t2Int_MemBarrierV7 = 1239,
- t2Int_SyncBarrierV7 = 1240,
- t2Int_eh_sjlj_setjmp = 1241,
- t2LDM = 1242,
- t2LDM_RET = 1243,
- t2LDRB_POST = 1244,
- t2LDRB_PRE = 1245,
- t2LDRBi12 = 1246,
- t2LDRBi8 = 1247,
- t2LDRBpci = 1248,
- t2LDRBs = 1249,
- t2LDRDi8 = 1250,
- t2LDRDpci = 1251,
- t2LDREX = 1252,
- t2LDREXB = 1253,
- t2LDREXD = 1254,
- t2LDREXH = 1255,
- t2LDRH_POST = 1256,
- t2LDRH_PRE = 1257,
- t2LDRHi12 = 1258,
- t2LDRHi8 = 1259,
- t2LDRHpci = 1260,
- t2LDRHs = 1261,
- t2LDRSB_POST = 1262,
- t2LDRSB_PRE = 1263,
- t2LDRSBi12 = 1264,
- t2LDRSBi8 = 1265,
- t2LDRSBpci = 1266,
- t2LDRSBs = 1267,
- t2LDRSH_POST = 1268,
- t2LDRSH_PRE = 1269,
- t2LDRSHi12 = 1270,
- t2LDRSHi8 = 1271,
- t2LDRSHpci = 1272,
- t2LDRSHs = 1273,
- t2LDR_POST = 1274,
- t2LDR_PRE = 1275,
- t2LDRi12 = 1276,
- t2LDRi8 = 1277,
- t2LDRpci = 1278,
- t2LDRpci_pic = 1279,
- t2LDRs = 1280,
- t2LEApcrel = 1281,
- t2LEApcrelJT = 1282,
- t2LSLri = 1283,
- t2LSLrr = 1284,
- t2LSRri = 1285,
- t2LSRrr = 1286,
- t2MLA = 1287,
- t2MLS = 1288,
- t2MOVCCasr = 1289,
- t2MOVCCi = 1290,
- t2MOVCClsl = 1291,
- t2MOVCClsr = 1292,
- t2MOVCCr = 1293,
- t2MOVCCror = 1294,
- t2MOVTi16 = 1295,
- t2MOVi = 1296,
- t2MOVi16 = 1297,
- t2MOVi32imm = 1298,
- t2MOVr = 1299,
- t2MOVrx = 1300,
- t2MOVsra_flag = 1301,
- t2MOVsrl_flag = 1302,
- t2MUL = 1303,
- t2MVNi = 1304,
- t2MVNr = 1305,
- t2MVNs = 1306,
- t2ORNri = 1307,
- t2ORNrr = 1308,
- t2ORNrs = 1309,
- t2ORRri = 1310,
- t2ORRrr = 1311,
- t2ORRrs = 1312,
- t2PKHBT = 1313,
- t2PKHTB = 1314,
- t2RBIT = 1315,
- t2REV = 1316,
- t2REV16 = 1317,
- t2REVSH = 1318,
- t2RORri = 1319,
- t2RORrr = 1320,
- t2RSBSri = 1321,
- t2RSBSrs = 1322,
- t2RSBri = 1323,
- t2RSBrs = 1324,
- t2SBCSri = 1325,
- t2SBCSrr = 1326,
- t2SBCSrs = 1327,
- t2SBCri = 1328,
- t2SBCrr = 1329,
- t2SBCrs = 1330,
- t2SBFX = 1331,
- t2SMLABB = 1332,
- t2SMLABT = 1333,
- t2SMLAL = 1334,
- t2SMLATB = 1335,
- t2SMLATT = 1336,
- t2SMLAWB = 1337,
- t2SMLAWT = 1338,
- t2SMMLA = 1339,
- t2SMMLS = 1340,
- t2SMMUL = 1341,
- t2SMULBB = 1342,
- t2SMULBT = 1343,
- t2SMULL = 1344,
- t2SMULTB = 1345,
- t2SMULTT = 1346,
- t2SMULWB = 1347,
- t2SMULWT = 1348,
- t2STM = 1349,
- t2STRB_POST = 1350,
- t2STRB_PRE = 1351,
- t2STRBi12 = 1352,
- t2STRBi8 = 1353,
- t2STRBs = 1354,
- t2STRDi8 = 1355,
- t2STREX = 1356,
- t2STREXB = 1357,
- t2STREXD = 1358,
- t2STREXH = 1359,
- t2STRH_POST = 1360,
- t2STRH_PRE = 1361,
- t2STRHi12 = 1362,
- t2STRHi8 = 1363,
- t2STRHs = 1364,
- t2STR_POST = 1365,
- t2STR_PRE = 1366,
- t2STRi12 = 1367,
- t2STRi8 = 1368,
- t2STRs = 1369,
- t2SUBSri = 1370,
- t2SUBSrr = 1371,
- t2SUBSrs = 1372,
- t2SUBrSPi = 1373,
- t2SUBrSPi12 = 1374,
- t2SUBrSPi12_ = 1375,
- t2SUBrSPi_ = 1376,
- t2SUBrSPs = 1377,
- t2SUBrSPs_ = 1378,
- t2SUBri = 1379,
- t2SUBri12 = 1380,
- t2SUBrr = 1381,
- t2SUBrs = 1382,
- t2SXTABrr = 1383,
- t2SXTABrr_rot = 1384,
- t2SXTAHrr = 1385,
- t2SXTAHrr_rot = 1386,
- t2SXTBr = 1387,
- t2SXTBr_rot = 1388,
- t2SXTHr = 1389,
- t2SXTHr_rot = 1390,
- t2TBB = 1391,
- t2TBH = 1392,
- t2TEQri = 1393,
- t2TEQrr = 1394,
- t2TEQrs = 1395,
- t2TPsoft = 1396,
- t2TSTri = 1397,
- t2TSTrr = 1398,
- t2TSTrs = 1399,
- t2UBFX = 1400,
- t2UMAAL = 1401,
- t2UMLAL = 1402,
- t2UMULL = 1403,
- t2UXTABrr = 1404,
- t2UXTABrr_rot = 1405,
- t2UXTAHrr = 1406,
- t2UXTAHrr_rot = 1407,
- t2UXTB16r = 1408,
- t2UXTB16r_rot = 1409,
- t2UXTBr = 1410,
- t2UXTBr_rot = 1411,
- t2UXTHr = 1412,
- t2UXTHr_rot = 1413,
- tADC = 1414,
- tADDhirr = 1415,
- tADDi3 = 1416,
- tADDi8 = 1417,
- tADDrPCi = 1418,
- tADDrSP = 1419,
- tADDrSPi = 1420,
- tADDrr = 1421,
- tADDspi = 1422,
- tADDspr = 1423,
- tADDspr_ = 1424,
- tADJCALLSTACKDOWN = 1425,
- tADJCALLSTACKUP = 1426,
- tAND = 1427,
- tANDsp = 1428,
- tASRri = 1429,
- tASRrr = 1430,
- tB = 1431,
- tBIC = 1432,
- tBL = 1433,
- tBLXi = 1434,
- tBLXi_r9 = 1435,
- tBLXr = 1436,
- tBLXr_r9 = 1437,
- tBLr9 = 1438,
- tBRIND = 1439,
- tBR_JTr = 1440,
- tBX = 1441,
- tBX_RET = 1442,
- tBX_RET_vararg = 1443,
- tBXr9 = 1444,
- tBcc = 1445,
- tBfar = 1446,
- tCBNZ = 1447,
- tCBZ = 1448,
- tCMNz = 1449,
- tCMPhir = 1450,
- tCMPi8 = 1451,
- tCMPr = 1452,
- tCMPzhir = 1453,
- tCMPzi8 = 1454,
- tCMPzr = 1455,
- tEOR = 1456,
- tInt_eh_sjlj_setjmp = 1457,
- tLDM = 1458,
- tLDR = 1459,
- tLDRB = 1460,
- tLDRBi = 1461,
- tLDRH = 1462,
- tLDRHi = 1463,
- tLDRSB = 1464,
- tLDRSH = 1465,
- tLDRcp = 1466,
- tLDRi = 1467,
- tLDRpci = 1468,
- tLDRpci_pic = 1469,
- tLDRspi = 1470,
- tLEApcrel = 1471,
- tLEApcrelJT = 1472,
- tLSLri = 1473,
- tLSLrr = 1474,
- tLSRri = 1475,
- tLSRrr = 1476,
- tMOVCCi = 1477,
- tMOVCCr = 1478,
- tMOVCCr_pseudo = 1479,
- tMOVSr = 1480,
- tMOVgpr2gpr = 1481,
- tMOVgpr2tgpr = 1482,
- tMOVi8 = 1483,
- tMOVr = 1484,
- tMOVtgpr2gpr = 1485,
- tMUL = 1486,
- tMVN = 1487,
- tORR = 1488,
- tPICADD = 1489,
- tPOP = 1490,
- tPOP_RET = 1491,
- tPUSH = 1492,
- tREV = 1493,
- tREV16 = 1494,
- tREVSH = 1495,
- tROR = 1496,
- tRSB = 1497,
- tRestore = 1498,
- tSBC = 1499,
- tSTM = 1500,
- tSTR = 1501,
- tSTRB = 1502,
- tSTRBi = 1503,
- tSTRH = 1504,
- tSTRHi = 1505,
- tSTRi = 1506,
- tSTRspi = 1507,
- tSUBi3 = 1508,
- tSUBi8 = 1509,
- tSUBrr = 1510,
- tSUBspi = 1511,
- tSUBspi_ = 1512,
- tSXTB = 1513,
- tSXTH = 1514,
- tSpill = 1515,
- tTPsoft = 1516,
- tTST = 1517,
- tUXTB = 1518,
- tUXTH = 1519,
- INSTRUCTION_LIST_END = 1520
+ BKPT = 58,
+ BL = 59,
+ BLX = 60,
+ BLXr9 = 61,
+ BL_pred = 62,
+ BLr9 = 63,
+ BLr9_pred = 64,
+ BRIND = 65,
+ BR_JTadd = 66,
+ BR_JTm = 67,
+ BR_JTr = 68,
+ BX = 69,
+ BXJ = 70,
+ BX_RET = 71,
+ BXr9 = 72,
+ Bcc = 73,
+ CDP = 74,
+ CDP2 = 75,
+ CLZ = 76,
+ CMNzri = 77,
+ CMNzrr = 78,
+ CMNzrs = 79,
+ CMPri = 80,
+ CMPrr = 81,
+ CMPrs = 82,
+ CMPzri = 83,
+ CMPzrr = 84,
+ CMPzrs = 85,
+ CONSTPOOL_ENTRY = 86,
+ CPS = 87,
+ DBG = 88,
+ EORri = 89,
+ EORrr = 90,
+ EORrs = 91,
+ FCONSTD = 92,
+ FCONSTS = 93,
+ FMSTAT = 94,
+ Int_MemBarrierV6 = 95,
+ Int_MemBarrierV7 = 96,
+ Int_SyncBarrierV6 = 97,
+ Int_SyncBarrierV7 = 98,
+ Int_eh_sjlj_setjmp = 99,
+ LDM = 100,
+ LDM_RET = 101,
+ LDR = 102,
+ LDRB = 103,
+ LDRBT = 104,
+ LDRB_POST = 105,
+ LDRB_PRE = 106,
+ LDRD = 107,
+ LDREX = 108,
+ LDREXB = 109,
+ LDREXD = 110,
+ LDREXH = 111,
+ LDRH = 112,
+ LDRH_POST = 113,
+ LDRH_PRE = 114,
+ LDRSB = 115,
+ LDRSB_POST = 116,
+ LDRSB_PRE = 117,
+ LDRSH = 118,
+ LDRSH_POST = 119,
+ LDRSH_PRE = 120,
+ LDRT = 121,
+ LDR_POST = 122,
+ LDR_PRE = 123,
+ LDRcp = 124,
+ LEApcrel = 125,
+ LEApcrelJT = 126,
+ MCR = 127,
+ MCR2 = 128,
+ MCRR = 129,
+ MCRR2 = 130,
+ MLA = 131,
+ MLS = 132,
+ MOVCCi = 133,
+ MOVCCr = 134,
+ MOVCCs = 135,
+ MOVTi16 = 136,
+ MOVi = 137,
+ MOVi16 = 138,
+ MOVi2pieces = 139,
+ MOVi32imm = 140,
+ MOVr = 141,
+ MOVrx = 142,
+ MOVs = 143,
+ MOVsra_flag = 144,
+ MOVsrl_flag = 145,
+ MRC = 146,
+ MRC2 = 147,
+ MRRC = 148,
+ MRRC2 = 149,
+ MRS = 150,
+ MRSsys = 151,
+ MSR = 152,
+ MSRsys = 153,
+ MUL = 154,
+ MVNi = 155,
+ MVNr = 156,
+ MVNs = 157,
+ NOP = 158,
+ ORRri = 159,
+ ORRrr = 160,
+ ORRrs = 161,
+ PICADD = 162,
+ PICLDR = 163,
+ PICLDRB = 164,
+ PICLDRH = 165,
+ PICLDRSB = 166,
+ PICLDRSH = 167,
+ PICSTR = 168,
+ PICSTRB = 169,
+ PICSTRH = 170,
+ PKHBT = 171,
+ PKHTB = 172,
+ QADD = 173,
+ QADD16 = 174,
+ QADD8 = 175,
+ QASX = 176,
+ QDADD = 177,
+ QDSUB = 178,
+ QSAX = 179,
+ QSUB = 180,
+ QSUB16 = 181,
+ QSUB8 = 182,
+ RBIT = 183,
+ REV = 184,
+ REV16 = 185,
+ REVSH = 186,
+ RSBSri = 187,
+ RSBSrs = 188,
+ RSBri = 189,
+ RSBrs = 190,
+ RSCSri = 191,
+ RSCSrs = 192,
+ RSCri = 193,
+ RSCrs = 194,
+ SBCSSri = 195,
+ SBCSSrr = 196,
+ SBCSSrs = 197,
+ SBCri = 198,
+ SBCrr = 199,
+ SBCrs = 200,
+ SBFX = 201,
+ SETENDBE = 202,
+ SETENDLE = 203,
+ SEV = 204,
+ SMLABB = 205,
+ SMLABT = 206,
+ SMLAL = 207,
+ SMLALBB = 208,
+ SMLALBT = 209,
+ SMLALTB = 210,
+ SMLALTT = 211,
+ SMLATB = 212,
+ SMLATT = 213,
+ SMLAWB = 214,
+ SMLAWT = 215,
+ SMMLA = 216,
+ SMMLS = 217,
+ SMMUL = 218,
+ SMULBB = 219,
+ SMULBT = 220,
+ SMULL = 221,
+ SMULTB = 222,
+ SMULTT = 223,
+ SMULWB = 224,
+ SMULWT = 225,
+ STM = 226,
+ STR = 227,
+ STRB = 228,
+ STRBT = 229,
+ STRB_POST = 230,
+ STRB_PRE = 231,
+ STRD = 232,
+ STREX = 233,
+ STREXB = 234,
+ STREXD = 235,
+ STREXH = 236,
+ STRH = 237,
+ STRH_POST = 238,
+ STRH_PRE = 239,
+ STRT = 240,
+ STR_POST = 241,
+ STR_PRE = 242,
+ SUBSri = 243,
+ SUBSrr = 244,
+ SUBSrs = 245,
+ SUBri = 246,
+ SUBrr = 247,
+ SUBrs = 248,
+ SVC = 249,
+ SWP = 250,
+ SWPB = 251,
+ SXTABrr = 252,
+ SXTABrr_rot = 253,
+ SXTAHrr = 254,
+ SXTAHrr_rot = 255,
+ SXTBr = 256,
+ SXTBr_rot = 257,
+ SXTHr = 258,
+ SXTHr_rot = 259,
+ TEQri = 260,
+ TEQrr = 261,
+ TEQrs = 262,
+ TPsoft = 263,
+ TRAP = 264,
+ TSTri = 265,
+ TSTrr = 266,
+ TSTrs = 267,
+ UBFX = 268,
+ UMAAL = 269,
+ UMLAL = 270,
+ UMULL = 271,
+ UQADD16 = 272,
+ UQADD8 = 273,
+ UQASX = 274,
+ UQSAX = 275,
+ UQSUB16 = 276,
+ UQSUB8 = 277,
+ UXTABrr = 278,
+ UXTABrr_rot = 279,
+ UXTAHrr = 280,
+ UXTAHrr_rot = 281,
+ UXTB16r = 282,
+ UXTB16r_rot = 283,
+ UXTBr = 284,
+ UXTBr_rot = 285,
+ UXTHr = 286,
+ UXTHr_rot = 287,
+ VABALsv2i64 = 288,
+ VABALsv4i32 = 289,
+ VABALsv8i16 = 290,
+ VABALuv2i64 = 291,
+ VABALuv4i32 = 292,
+ VABALuv8i16 = 293,
+ VABAsv16i8 = 294,
+ VABAsv2i32 = 295,
+ VABAsv4i16 = 296,
+ VABAsv4i32 = 297,
+ VABAsv8i16 = 298,
+ VABAsv8i8 = 299,
+ VABAuv16i8 = 300,
+ VABAuv2i32 = 301,
+ VABAuv4i16 = 302,
+ VABAuv4i32 = 303,
+ VABAuv8i16 = 304,
+ VABAuv8i8 = 305,
+ VABDLsv2i64 = 306,
+ VABDLsv4i32 = 307,
+ VABDLsv8i16 = 308,
+ VABDLuv2i64 = 309,
+ VABDLuv4i32 = 310,
+ VABDLuv8i16 = 311,
+ VABDfd = 312,
+ VABDfq = 313,
+ VABDsv16i8 = 314,
+ VABDsv2i32 = 315,
+ VABDsv4i16 = 316,
+ VABDsv4i32 = 317,
+ VABDsv8i16 = 318,
+ VABDsv8i8 = 319,
+ VABDuv16i8 = 320,
+ VABDuv2i32 = 321,
+ VABDuv4i16 = 322,
+ VABDuv4i32 = 323,
+ VABDuv8i16 = 324,
+ VABDuv8i8 = 325,
+ VABSD = 326,
+ VABSS = 327,
+ VABSfd = 328,
+ VABSfd_sfp = 329,
+ VABSfq = 330,
+ VABSv16i8 = 331,
+ VABSv2i32 = 332,
+ VABSv4i16 = 333,
+ VABSv4i32 = 334,
+ VABSv8i16 = 335,
+ VABSv8i8 = 336,
+ VACGEd = 337,
+ VACGEq = 338,
+ VACGTd = 339,
+ VACGTq = 340,
+ VADDD = 341,
+ VADDHNv2i32 = 342,
+ VADDHNv4i16 = 343,
+ VADDHNv8i8 = 344,
+ VADDLsv2i64 = 345,
+ VADDLsv4i32 = 346,
+ VADDLsv8i16 = 347,
+ VADDLuv2i64 = 348,
+ VADDLuv4i32 = 349,
+ VADDLuv8i16 = 350,
+ VADDS = 351,
+ VADDWsv2i64 = 352,
+ VADDWsv4i32 = 353,
+ VADDWsv8i16 = 354,
+ VADDWuv2i64 = 355,
+ VADDWuv4i32 = 356,
+ VADDWuv8i16 = 357,
+ VADDfd = 358,
+ VADDfd_sfp = 359,
+ VADDfq = 360,
+ VADDv16i8 = 361,
+ VADDv1i64 = 362,
+ VADDv2i32 = 363,
+ VADDv2i64 = 364,
+ VADDv4i16 = 365,
+ VADDv4i32 = 366,
+ VADDv8i16 = 367,
+ VADDv8i8 = 368,
+ VANDd = 369,
+ VANDq = 370,
+ VBICd = 371,
+ VBICq = 372,
+ VBIFd = 373,
+ VBIFq = 374,
+ VBITd = 375,
+ VBITq = 376,
+ VBSLd = 377,
+ VBSLq = 378,
+ VCEQfd = 379,
+ VCEQfq = 380,
+ VCEQv16i8 = 381,
+ VCEQv2i32 = 382,
+ VCEQv4i16 = 383,
+ VCEQv4i32 = 384,
+ VCEQv8i16 = 385,
+ VCEQv8i8 = 386,
+ VCGEfd = 387,
+ VCGEfq = 388,
+ VCGEsv16i8 = 389,
+ VCGEsv2i32 = 390,
+ VCGEsv4i16 = 391,
+ VCGEsv4i32 = 392,
+ VCGEsv8i16 = 393,
+ VCGEsv8i8 = 394,
+ VCGEuv16i8 = 395,
+ VCGEuv2i32 = 396,
+ VCGEuv4i16 = 397,
+ VCGEuv4i32 = 398,
+ VCGEuv8i16 = 399,
+ VCGEuv8i8 = 400,
+ VCGTfd = 401,
+ VCGTfq = 402,
+ VCGTsv16i8 = 403,
+ VCGTsv2i32 = 404,
+ VCGTsv4i16 = 405,
+ VCGTsv4i32 = 406,
+ VCGTsv8i16 = 407,
+ VCGTsv8i8 = 408,
+ VCGTuv16i8 = 409,
+ VCGTuv2i32 = 410,
+ VCGTuv4i16 = 411,
+ VCGTuv4i32 = 412,
+ VCGTuv8i16 = 413,
+ VCGTuv8i8 = 414,
+ VCLSv16i8 = 415,
+ VCLSv2i32 = 416,
+ VCLSv4i16 = 417,
+ VCLSv4i32 = 418,
+ VCLSv8i16 = 419,
+ VCLSv8i8 = 420,
+ VCLZv16i8 = 421,
+ VCLZv2i32 = 422,
+ VCLZv4i16 = 423,
+ VCLZv4i32 = 424,
+ VCLZv8i16 = 425,
+ VCLZv8i8 = 426,
+ VCMPD = 427,
+ VCMPED = 428,
+ VCMPES = 429,
+ VCMPEZD = 430,
+ VCMPEZS = 431,
+ VCMPS = 432,
+ VCMPZD = 433,
+ VCMPZS = 434,
+ VCNTd = 435,
+ VCNTq = 436,
+ VCVTBHS = 437,
+ VCVTBSH = 438,
+ VCVTDS = 439,
+ VCVTSD = 440,
+ VCVTTHS = 441,
+ VCVTTSH = 442,
+ VCVTf2sd = 443,
+ VCVTf2sd_sfp = 444,
+ VCVTf2sq = 445,
+ VCVTf2ud = 446,
+ VCVTf2ud_sfp = 447,
+ VCVTf2uq = 448,
+ VCVTf2xsd = 449,
+ VCVTf2xsq = 450,
+ VCVTf2xud = 451,
+ VCVTf2xuq = 452,
+ VCVTs2fd = 453,
+ VCVTs2fd_sfp = 454,
+ VCVTs2fq = 455,
+ VCVTu2fd = 456,
+ VCVTu2fd_sfp = 457,
+ VCVTu2fq = 458,
+ VCVTxs2fd = 459,
+ VCVTxs2fq = 460,
+ VCVTxu2fd = 461,
+ VCVTxu2fq = 462,
+ VDIVD = 463,
+ VDIVS = 464,
+ VDUP16d = 465,
+ VDUP16q = 466,
+ VDUP32d = 467,
+ VDUP32q = 468,
+ VDUP8d = 469,
+ VDUP8q = 470,
+ VDUPLN16d = 471,
+ VDUPLN16q = 472,
+ VDUPLN32d = 473,
+ VDUPLN32q = 474,
+ VDUPLN8d = 475,
+ VDUPLN8q = 476,
+ VDUPLNfd = 477,
+ VDUPLNfq = 478,
+ VDUPfd = 479,
+ VDUPfdf = 480,
+ VDUPfq = 481,
+ VDUPfqf = 482,
+ VEORd = 483,
+ VEORq = 484,
+ VEXTd16 = 485,
+ VEXTd32 = 486,
+ VEXTd8 = 487,
+ VEXTdf = 488,
+ VEXTq16 = 489,
+ VEXTq32 = 490,
+ VEXTq8 = 491,
+ VEXTqf = 492,
+ VGETLNi32 = 493,
+ VGETLNs16 = 494,
+ VGETLNs8 = 495,
+ VGETLNu16 = 496,
+ VGETLNu8 = 497,
+ VHADDsv16i8 = 498,
+ VHADDsv2i32 = 499,
+ VHADDsv4i16 = 500,
+ VHADDsv4i32 = 501,
+ VHADDsv8i16 = 502,
+ VHADDsv8i8 = 503,
+ VHADDuv16i8 = 504,
+ VHADDuv2i32 = 505,
+ VHADDuv4i16 = 506,
+ VHADDuv4i32 = 507,
+ VHADDuv8i16 = 508,
+ VHADDuv8i8 = 509,
+ VHSUBsv16i8 = 510,
+ VHSUBsv2i32 = 511,
+ VHSUBsv4i16 = 512,
+ VHSUBsv4i32 = 513,
+ VHSUBsv8i16 = 514,
+ VHSUBsv8i8 = 515,
+ VHSUBuv16i8 = 516,
+ VHSUBuv2i32 = 517,
+ VHSUBuv4i16 = 518,
+ VHSUBuv4i32 = 519,
+ VHSUBuv8i16 = 520,
+ VHSUBuv8i8 = 521,
+ VLD1d16 = 522,
+ VLD1d32 = 523,
+ VLD1d64 = 524,
+ VLD1d8 = 525,
+ VLD1df = 526,
+ VLD1q16 = 527,
+ VLD1q32 = 528,
+ VLD1q64 = 529,
+ VLD1q8 = 530,
+ VLD1qf = 531,
+ VLD2LNd16 = 532,
+ VLD2LNd32 = 533,
+ VLD2LNd8 = 534,
+ VLD2LNq16a = 535,
+ VLD2LNq16b = 536,
+ VLD2LNq32a = 537,
+ VLD2LNq32b = 538,
+ VLD2d16 = 539,
+ VLD2d32 = 540,
+ VLD2d64 = 541,
+ VLD2d8 = 542,
+ VLD2q16 = 543,
+ VLD2q32 = 544,
+ VLD2q8 = 545,
+ VLD3LNd16 = 546,
+ VLD3LNd32 = 547,
+ VLD3LNd8 = 548,
+ VLD3LNq16a = 549,
+ VLD3LNq16b = 550,
+ VLD3LNq32a = 551,
+ VLD3LNq32b = 552,
+ VLD3d16 = 553,
+ VLD3d32 = 554,
+ VLD3d64 = 555,
+ VLD3d8 = 556,
+ VLD3q16a = 557,
+ VLD3q16b = 558,
+ VLD3q32a = 559,
+ VLD3q32b = 560,
+ VLD3q8a = 561,
+ VLD3q8b = 562,
+ VLD4LNd16 = 563,
+ VLD4LNd32 = 564,
+ VLD4LNd8 = 565,
+ VLD4LNq16a = 566,
+ VLD4LNq16b = 567,
+ VLD4LNq32a = 568,
+ VLD4LNq32b = 569,
+ VLD4d16 = 570,
+ VLD4d32 = 571,
+ VLD4d64 = 572,
+ VLD4d8 = 573,
+ VLD4q16a = 574,
+ VLD4q16b = 575,
+ VLD4q32a = 576,
+ VLD4q32b = 577,
+ VLD4q8a = 578,
+ VLD4q8b = 579,
+ VLDMD = 580,
+ VLDMS = 581,
+ VLDRD = 582,
+ VLDRQ = 583,
+ VLDRS = 584,
+ VMAXfd = 585,
+ VMAXfq = 586,
+ VMAXsv16i8 = 587,
+ VMAXsv2i32 = 588,
+ VMAXsv4i16 = 589,
+ VMAXsv4i32 = 590,
+ VMAXsv8i16 = 591,
+ VMAXsv8i8 = 592,
+ VMAXuv16i8 = 593,
+ VMAXuv2i32 = 594,
+ VMAXuv4i16 = 595,
+ VMAXuv4i32 = 596,
+ VMAXuv8i16 = 597,
+ VMAXuv8i8 = 598,
+ VMINfd = 599,
+ VMINfq = 600,
+ VMINsv16i8 = 601,
+ VMINsv2i32 = 602,
+ VMINsv4i16 = 603,
+ VMINsv4i32 = 604,
+ VMINsv8i16 = 605,
+ VMINsv8i8 = 606,
+ VMINuv16i8 = 607,
+ VMINuv2i32 = 608,
+ VMINuv4i16 = 609,
+ VMINuv4i32 = 610,
+ VMINuv8i16 = 611,
+ VMINuv8i8 = 612,
+ VMLAD = 613,
+ VMLALslsv2i32 = 614,
+ VMLALslsv4i16 = 615,
+ VMLALsluv2i32 = 616,
+ VMLALsluv4i16 = 617,
+ VMLALsv2i64 = 618,
+ VMLALsv4i32 = 619,
+ VMLALsv8i16 = 620,
+ VMLALuv2i64 = 621,
+ VMLALuv4i32 = 622,
+ VMLALuv8i16 = 623,
+ VMLAS = 624,
+ VMLAfd = 625,
+ VMLAfq = 626,
+ VMLAslfd = 627,
+ VMLAslfq = 628,
+ VMLAslv2i32 = 629,
+ VMLAslv4i16 = 630,
+ VMLAslv4i32 = 631,
+ VMLAslv8i16 = 632,
+ VMLAv16i8 = 633,
+ VMLAv2i32 = 634,
+ VMLAv4i16 = 635,
+ VMLAv4i32 = 636,
+ VMLAv8i16 = 637,
+ VMLAv8i8 = 638,
+ VMLSD = 639,
+ VMLSLslsv2i32 = 640,
+ VMLSLslsv4i16 = 641,
+ VMLSLsluv2i32 = 642,
+ VMLSLsluv4i16 = 643,
+ VMLSLsv2i64 = 644,
+ VMLSLsv4i32 = 645,
+ VMLSLsv8i16 = 646,
+ VMLSLuv2i64 = 647,
+ VMLSLuv4i32 = 648,
+ VMLSLuv8i16 = 649,
+ VMLSS = 650,
+ VMLSfd = 651,
+ VMLSfq = 652,
+ VMLSslfd = 653,
+ VMLSslfq = 654,
+ VMLSslv2i32 = 655,
+ VMLSslv4i16 = 656,
+ VMLSslv4i32 = 657,
+ VMLSslv8i16 = 658,
+ VMLSv16i8 = 659,
+ VMLSv2i32 = 660,
+ VMLSv4i16 = 661,
+ VMLSv4i32 = 662,
+ VMLSv8i16 = 663,
+ VMLSv8i8 = 664,
+ VMOVD = 665,
+ VMOVDRR = 666,
+ VMOVDcc = 667,
+ VMOVDneon = 668,
+ VMOVLsv2i64 = 669,
+ VMOVLsv4i32 = 670,
+ VMOVLsv8i16 = 671,
+ VMOVLuv2i64 = 672,
+ VMOVLuv4i32 = 673,
+ VMOVLuv8i16 = 674,
+ VMOVNv2i32 = 675,
+ VMOVNv4i16 = 676,
+ VMOVNv8i8 = 677,
+ VMOVQ = 678,
+ VMOVRRD = 679,
+ VMOVRRS = 680,
+ VMOVRS = 681,
+ VMOVS = 682,
+ VMOVSR = 683,
+ VMOVSRR = 684,
+ VMOVScc = 685,
+ VMOVv16i8 = 686,
+ VMOVv1i64 = 687,
+ VMOVv2i32 = 688,
+ VMOVv2i64 = 689,
+ VMOVv4i16 = 690,
+ VMOVv4i32 = 691,
+ VMOVv8i16 = 692,
+ VMOVv8i8 = 693,
+ VMRS = 694,
+ VMSR = 695,
+ VMULD = 696,
+ VMULLp = 697,
+ VMULLslsv2i32 = 698,
+ VMULLslsv4i16 = 699,
+ VMULLsluv2i32 = 700,
+ VMULLsluv4i16 = 701,
+ VMULLsv2i64 = 702,
+ VMULLsv4i32 = 703,
+ VMULLsv8i16 = 704,
+ VMULLuv2i64 = 705,
+ VMULLuv4i32 = 706,
+ VMULLuv8i16 = 707,
+ VMULS = 708,
+ VMULfd = 709,
+ VMULfd_sfp = 710,
+ VMULfq = 711,
+ VMULpd = 712,
+ VMULpq = 713,
+ VMULslfd = 714,
+ VMULslfq = 715,
+ VMULslv2i32 = 716,
+ VMULslv4i16 = 717,
+ VMULslv4i32 = 718,
+ VMULslv8i16 = 719,
+ VMULv16i8 = 720,
+ VMULv2i32 = 721,
+ VMULv4i16 = 722,
+ VMULv4i32 = 723,
+ VMULv8i16 = 724,
+ VMULv8i8 = 725,
+ VMVNd = 726,
+ VMVNq = 727,
+ VNEGD = 728,
+ VNEGDcc = 729,
+ VNEGS = 730,
+ VNEGScc = 731,
+ VNEGf32d = 732,
+ VNEGf32d_sfp = 733,
+ VNEGf32q = 734,
+ VNEGs16d = 735,
+ VNEGs16q = 736,
+ VNEGs32d = 737,
+ VNEGs32q = 738,
+ VNEGs8d = 739,
+ VNEGs8q = 740,
+ VNMLAD = 741,
+ VNMLAS = 742,
+ VNMLSD = 743,
+ VNMLSS = 744,
+ VNMULD = 745,
+ VNMULS = 746,
+ VORNd = 747,
+ VORNq = 748,
+ VORRd = 749,
+ VORRq = 750,
+ VPADALsv16i8 = 751,
+ VPADALsv2i32 = 752,
+ VPADALsv4i16 = 753,
+ VPADALsv4i32 = 754,
+ VPADALsv8i16 = 755,
+ VPADALsv8i8 = 756,
+ VPADALuv16i8 = 757,
+ VPADALuv2i32 = 758,
+ VPADALuv4i16 = 759,
+ VPADALuv4i32 = 760,
+ VPADALuv8i16 = 761,
+ VPADALuv8i8 = 762,
+ VPADDLsv16i8 = 763,
+ VPADDLsv2i32 = 764,
+ VPADDLsv4i16 = 765,
+ VPADDLsv4i32 = 766,
+ VPADDLsv8i16 = 767,
+ VPADDLsv8i8 = 768,
+ VPADDLuv16i8 = 769,
+ VPADDLuv2i32 = 770,
+ VPADDLuv4i16 = 771,
+ VPADDLuv4i32 = 772,
+ VPADDLuv8i16 = 773,
+ VPADDLuv8i8 = 774,
+ VPADDf = 775,
+ VPADDi16 = 776,
+ VPADDi32 = 777,
+ VPADDi8 = 778,
+ VPMAXf = 779,
+ VPMAXs16 = 780,
+ VPMAXs32 = 781,
+ VPMAXs8 = 782,
+ VPMAXu16 = 783,
+ VPMAXu32 = 784,
+ VPMAXu8 = 785,
+ VPMINf = 786,
+ VPMINs16 = 787,
+ VPMINs32 = 788,
+ VPMINs8 = 789,
+ VPMINu16 = 790,
+ VPMINu32 = 791,
+ VPMINu8 = 792,
+ VQABSv16i8 = 793,
+ VQABSv2i32 = 794,
+ VQABSv4i16 = 795,
+ VQABSv4i32 = 796,
+ VQABSv8i16 = 797,
+ VQABSv8i8 = 798,
+ VQADDsv16i8 = 799,
+ VQADDsv1i64 = 800,
+ VQADDsv2i32 = 801,
+ VQADDsv2i64 = 802,
+ VQADDsv4i16 = 803,
+ VQADDsv4i32 = 804,
+ VQADDsv8i16 = 805,
+ VQADDsv8i8 = 806,
+ VQADDuv16i8 = 807,
+ VQADDuv1i64 = 808,
+ VQADDuv2i32 = 809,
+ VQADDuv2i64 = 810,
+ VQADDuv4i16 = 811,
+ VQADDuv4i32 = 812,
+ VQADDuv8i16 = 813,
+ VQADDuv8i8 = 814,
+ VQDMLALslv2i32 = 815,
+ VQDMLALslv4i16 = 816,
+ VQDMLALv2i64 = 817,
+ VQDMLALv4i32 = 818,
+ VQDMLSLslv2i32 = 819,
+ VQDMLSLslv4i16 = 820,
+ VQDMLSLv2i64 = 821,
+ VQDMLSLv4i32 = 822,
+ VQDMULHslv2i32 = 823,
+ VQDMULHslv4i16 = 824,
+ VQDMULHslv4i32 = 825,
+ VQDMULHslv8i16 = 826,
+ VQDMULHv2i32 = 827,
+ VQDMULHv4i16 = 828,
+ VQDMULHv4i32 = 829,
+ VQDMULHv8i16 = 830,
+ VQDMULLslv2i32 = 831,
+ VQDMULLslv4i16 = 832,
+ VQDMULLv2i64 = 833,
+ VQDMULLv4i32 = 834,
+ VQMOVNsuv2i32 = 835,
+ VQMOVNsuv4i16 = 836,
+ VQMOVNsuv8i8 = 837,
+ VQMOVNsv2i32 = 838,
+ VQMOVNsv4i16 = 839,
+ VQMOVNsv8i8 = 840,
+ VQMOVNuv2i32 = 841,
+ VQMOVNuv4i16 = 842,
+ VQMOVNuv8i8 = 843,
+ VQNEGv16i8 = 844,
+ VQNEGv2i32 = 845,
+ VQNEGv4i16 = 846,
+ VQNEGv4i32 = 847,
+ VQNEGv8i16 = 848,
+ VQNEGv8i8 = 849,
+ VQRDMULHslv2i32 = 850,
+ VQRDMULHslv4i16 = 851,
+ VQRDMULHslv4i32 = 852,
+ VQRDMULHslv8i16 = 853,
+ VQRDMULHv2i32 = 854,
+ VQRDMULHv4i16 = 855,
+ VQRDMULHv4i32 = 856,
+ VQRDMULHv8i16 = 857,
+ VQRSHLsv16i8 = 858,
+ VQRSHLsv1i64 = 859,
+ VQRSHLsv2i32 = 860,
+ VQRSHLsv2i64 = 861,
+ VQRSHLsv4i16 = 862,
+ VQRSHLsv4i32 = 863,
+ VQRSHLsv8i16 = 864,
+ VQRSHLsv8i8 = 865,
+ VQRSHLuv16i8 = 866,
+ VQRSHLuv1i64 = 867,
+ VQRSHLuv2i32 = 868,
+ VQRSHLuv2i64 = 869,
+ VQRSHLuv4i16 = 870,
+ VQRSHLuv4i32 = 871,
+ VQRSHLuv8i16 = 872,
+ VQRSHLuv8i8 = 873,
+ VQRSHRNsv2i32 = 874,
+ VQRSHRNsv4i16 = 875,
+ VQRSHRNsv8i8 = 876,
+ VQRSHRNuv2i32 = 877,
+ VQRSHRNuv4i16 = 878,
+ VQRSHRNuv8i8 = 879,
+ VQRSHRUNv2i32 = 880,
+ VQRSHRUNv4i16 = 881,
+ VQRSHRUNv8i8 = 882,
+ VQSHLsiv16i8 = 883,
+ VQSHLsiv1i64 = 884,
+ VQSHLsiv2i32 = 885,
+ VQSHLsiv2i64 = 886,
+ VQSHLsiv4i16 = 887,
+ VQSHLsiv4i32 = 888,
+ VQSHLsiv8i16 = 889,
+ VQSHLsiv8i8 = 890,
+ VQSHLsuv16i8 = 891,
+ VQSHLsuv1i64 = 892,
+ VQSHLsuv2i32 = 893,
+ VQSHLsuv2i64 = 894,
+ VQSHLsuv4i16 = 895,
+ VQSHLsuv4i32 = 896,
+ VQSHLsuv8i16 = 897,
+ VQSHLsuv8i8 = 898,
+ VQSHLsv16i8 = 899,
+ VQSHLsv1i64 = 900,
+ VQSHLsv2i32 = 901,
+ VQSHLsv2i64 = 902,
+ VQSHLsv4i16 = 903,
+ VQSHLsv4i32 = 904,
+ VQSHLsv8i16 = 905,
+ VQSHLsv8i8 = 906,
+ VQSHLuiv16i8 = 907,
+ VQSHLuiv1i64 = 908,
+ VQSHLuiv2i32 = 909,
+ VQSHLuiv2i64 = 910,
+ VQSHLuiv4i16 = 911,
+ VQSHLuiv4i32 = 912,
+ VQSHLuiv8i16 = 913,
+ VQSHLuiv8i8 = 914,
+ VQSHLuv16i8 = 915,
+ VQSHLuv1i64 = 916,
+ VQSHLuv2i32 = 917,
+ VQSHLuv2i64 = 918,
+ VQSHLuv4i16 = 919,
+ VQSHLuv4i32 = 920,
+ VQSHLuv8i16 = 921,
+ VQSHLuv8i8 = 922,
+ VQSHRNsv2i32 = 923,
+ VQSHRNsv4i16 = 924,
+ VQSHRNsv8i8 = 925,
+ VQSHRNuv2i32 = 926,
+ VQSHRNuv4i16 = 927,
+ VQSHRNuv8i8 = 928,
+ VQSHRUNv2i32 = 929,
+ VQSHRUNv4i16 = 930,
+ VQSHRUNv8i8 = 931,
+ VQSUBsv16i8 = 932,
+ VQSUBsv1i64 = 933,
+ VQSUBsv2i32 = 934,
+ VQSUBsv2i64 = 935,
+ VQSUBsv4i16 = 936,
+ VQSUBsv4i32 = 937,
+ VQSUBsv8i16 = 938,
+ VQSUBsv8i8 = 939,
+ VQSUBuv16i8 = 940,
+ VQSUBuv1i64 = 941,
+ VQSUBuv2i32 = 942,
+ VQSUBuv2i64 = 943,
+ VQSUBuv4i16 = 944,
+ VQSUBuv4i32 = 945,
+ VQSUBuv8i16 = 946,
+ VQSUBuv8i8 = 947,
+ VRADDHNv2i32 = 948,
+ VRADDHNv4i16 = 949,
+ VRADDHNv8i8 = 950,
+ VRECPEd = 951,
+ VRECPEfd = 952,
+ VRECPEfq = 953,
+ VRECPEq = 954,
+ VRECPSfd = 955,
+ VRECPSfq = 956,
+ VREV16d8 = 957,
+ VREV16q8 = 958,
+ VREV32d16 = 959,
+ VREV32d8 = 960,
+ VREV32q16 = 961,
+ VREV32q8 = 962,
+ VREV64d16 = 963,
+ VREV64d32 = 964,
+ VREV64d8 = 965,
+ VREV64df = 966,
+ VREV64q16 = 967,
+ VREV64q32 = 968,
+ VREV64q8 = 969,
+ VREV64qf = 970,
+ VRHADDsv16i8 = 971,
+ VRHADDsv2i32 = 972,
+ VRHADDsv4i16 = 973,
+ VRHADDsv4i32 = 974,
+ VRHADDsv8i16 = 975,
+ VRHADDsv8i8 = 976,
+ VRHADDuv16i8 = 977,
+ VRHADDuv2i32 = 978,
+ VRHADDuv4i16 = 979,
+ VRHADDuv4i32 = 980,
+ VRHADDuv8i16 = 981,
+ VRHADDuv8i8 = 982,
+ VRSHLsv16i8 = 983,
+ VRSHLsv1i64 = 984,
+ VRSHLsv2i32 = 985,
+ VRSHLsv2i64 = 986,
+ VRSHLsv4i16 = 987,
+ VRSHLsv4i32 = 988,
+ VRSHLsv8i16 = 989,
+ VRSHLsv8i8 = 990,
+ VRSHLuv16i8 = 991,
+ VRSHLuv1i64 = 992,
+ VRSHLuv2i32 = 993,
+ VRSHLuv2i64 = 994,
+ VRSHLuv4i16 = 995,
+ VRSHLuv4i32 = 996,
+ VRSHLuv8i16 = 997,
+ VRSHLuv8i8 = 998,
+ VRSHRNv2i32 = 999,
+ VRSHRNv4i16 = 1000,
+ VRSHRNv8i8 = 1001,
+ VRSHRsv16i8 = 1002,
+ VRSHRsv1i64 = 1003,
+ VRSHRsv2i32 = 1004,
+ VRSHRsv2i64 = 1005,
+ VRSHRsv4i16 = 1006,
+ VRSHRsv4i32 = 1007,
+ VRSHRsv8i16 = 1008,
+ VRSHRsv8i8 = 1009,
+ VRSHRuv16i8 = 1010,
+ VRSHRuv1i64 = 1011,
+ VRSHRuv2i32 = 1012,
+ VRSHRuv2i64 = 1013,
+ VRSHRuv4i16 = 1014,
+ VRSHRuv4i32 = 1015,
+ VRSHRuv8i16 = 1016,
+ VRSHRuv8i8 = 1017,
+ VRSQRTEd = 1018,
+ VRSQRTEfd = 1019,
+ VRSQRTEfq = 1020,
+ VRSQRTEq = 1021,
+ VRSQRTSfd = 1022,
+ VRSQRTSfq = 1023,
+ VRSRAsv16i8 = 1024,
+ VRSRAsv1i64 = 1025,
+ VRSRAsv2i32 = 1026,
+ VRSRAsv2i64 = 1027,
+ VRSRAsv4i16 = 1028,
+ VRSRAsv4i32 = 1029,
+ VRSRAsv8i16 = 1030,
+ VRSRAsv8i8 = 1031,
+ VRSRAuv16i8 = 1032,
+ VRSRAuv1i64 = 1033,
+ VRSRAuv2i32 = 1034,
+ VRSRAuv2i64 = 1035,
+ VRSRAuv4i16 = 1036,
+ VRSRAuv4i32 = 1037,
+ VRSRAuv8i16 = 1038,
+ VRSRAuv8i8 = 1039,
+ VRSUBHNv2i32 = 1040,
+ VRSUBHNv4i16 = 1041,
+ VRSUBHNv8i8 = 1042,
+ VSETLNi16 = 1043,
+ VSETLNi32 = 1044,
+ VSETLNi8 = 1045,
+ VSHLLi16 = 1046,
+ VSHLLi32 = 1047,
+ VSHLLi8 = 1048,
+ VSHLLsv2i64 = 1049,
+ VSHLLsv4i32 = 1050,
+ VSHLLsv8i16 = 1051,
+ VSHLLuv2i64 = 1052,
+ VSHLLuv4i32 = 1053,
+ VSHLLuv8i16 = 1054,
+ VSHLiv16i8 = 1055,
+ VSHLiv1i64 = 1056,
+ VSHLiv2i32 = 1057,
+ VSHLiv2i64 = 1058,
+ VSHLiv4i16 = 1059,
+ VSHLiv4i32 = 1060,
+ VSHLiv8i16 = 1061,
+ VSHLiv8i8 = 1062,
+ VSHLsv16i8 = 1063,
+ VSHLsv1i64 = 1064,
+ VSHLsv2i32 = 1065,
+ VSHLsv2i64 = 1066,
+ VSHLsv4i16 = 1067,
+ VSHLsv4i32 = 1068,
+ VSHLsv8i16 = 1069,
+ VSHLsv8i8 = 1070,
+ VSHLuv16i8 = 1071,
+ VSHLuv1i64 = 1072,
+ VSHLuv2i32 = 1073,
+ VSHLuv2i64 = 1074,
+ VSHLuv4i16 = 1075,
+ VSHLuv4i32 = 1076,
+ VSHLuv8i16 = 1077,
+ VSHLuv8i8 = 1078,
+ VSHRNv2i32 = 1079,
+ VSHRNv4i16 = 1080,
+ VSHRNv8i8 = 1081,
+ VSHRsv16i8 = 1082,
+ VSHRsv1i64 = 1083,
+ VSHRsv2i32 = 1084,
+ VSHRsv2i64 = 1085,
+ VSHRsv4i16 = 1086,
+ VSHRsv4i32 = 1087,
+ VSHRsv8i16 = 1088,
+ VSHRsv8i8 = 1089,
+ VSHRuv16i8 = 1090,
+ VSHRuv1i64 = 1091,
+ VSHRuv2i32 = 1092,
+ VSHRuv2i64 = 1093,
+ VSHRuv4i16 = 1094,
+ VSHRuv4i32 = 1095,
+ VSHRuv8i16 = 1096,
+ VSHRuv8i8 = 1097,
+ VSHTOD = 1098,
+ VSHTOS = 1099,
+ VSITOD = 1100,
+ VSITOS = 1101,
+ VSLIv16i8 = 1102,
+ VSLIv1i64 = 1103,
+ VSLIv2i32 = 1104,
+ VSLIv2i64 = 1105,
+ VSLIv4i16 = 1106,
+ VSLIv4i32 = 1107,
+ VSLIv8i16 = 1108,
+ VSLIv8i8 = 1109,
+ VSLTOD = 1110,
+ VSLTOS = 1111,
+ VSQRTD = 1112,
+ VSQRTS = 1113,
+ VSRAsv16i8 = 1114,
+ VSRAsv1i64 = 1115,
+ VSRAsv2i32 = 1116,
+ VSRAsv2i64 = 1117,
+ VSRAsv4i16 = 1118,
+ VSRAsv4i32 = 1119,
+ VSRAsv8i16 = 1120,
+ VSRAsv8i8 = 1121,
+ VSRAuv16i8 = 1122,
+ VSRAuv1i64 = 1123,
+ VSRAuv2i32 = 1124,
+ VSRAuv2i64 = 1125,
+ VSRAuv4i16 = 1126,
+ VSRAuv4i32 = 1127,
+ VSRAuv8i16 = 1128,
+ VSRAuv8i8 = 1129,
+ VSRIv16i8 = 1130,
+ VSRIv1i64 = 1131,
+ VSRIv2i32 = 1132,
+ VSRIv2i64 = 1133,
+ VSRIv4i16 = 1134,
+ VSRIv4i32 = 1135,
+ VSRIv8i16 = 1136,
+ VSRIv8i8 = 1137,
+ VST1d16 = 1138,
+ VST1d32 = 1139,
+ VST1d64 = 1140,
+ VST1d8 = 1141,
+ VST1df = 1142,
+ VST1q16 = 1143,
+ VST1q32 = 1144,
+ VST1q64 = 1145,
+ VST1q8 = 1146,
+ VST1qf = 1147,
+ VST2LNd16 = 1148,
+ VST2LNd32 = 1149,
+ VST2LNd8 = 1150,
+ VST2LNq16a = 1151,
+ VST2LNq16b = 1152,
+ VST2LNq32a = 1153,
+ VST2LNq32b = 1154,
+ VST2d16 = 1155,
+ VST2d32 = 1156,
+ VST2d64 = 1157,
+ VST2d8 = 1158,
+ VST2q16 = 1159,
+ VST2q32 = 1160,
+ VST2q8 = 1161,
+ VST3LNd16 = 1162,
+ VST3LNd32 = 1163,
+ VST3LNd8 = 1164,
+ VST3LNq16a = 1165,
+ VST3LNq16b = 1166,
+ VST3LNq32a = 1167,
+ VST3LNq32b = 1168,
+ VST3d16 = 1169,
+ VST3d32 = 1170,
+ VST3d64 = 1171,
+ VST3d8 = 1172,
+ VST3q16a = 1173,
+ VST3q16b = 1174,
+ VST3q32a = 1175,
+ VST3q32b = 1176,
+ VST3q8a = 1177,
+ VST3q8b = 1178,
+ VST4LNd16 = 1179,
+ VST4LNd32 = 1180,
+ VST4LNd8 = 1181,
+ VST4LNq16a = 1182,
+ VST4LNq16b = 1183,
+ VST4LNq32a = 1184,
+ VST4LNq32b = 1185,
+ VST4d16 = 1186,
+ VST4d32 = 1187,
+ VST4d64 = 1188,
+ VST4d8 = 1189,
+ VST4q16a = 1190,
+ VST4q16b = 1191,
+ VST4q32a = 1192,
+ VST4q32b = 1193,
+ VST4q8a = 1194,
+ VST4q8b = 1195,
+ VSTMD = 1196,
+ VSTMS = 1197,
+ VSTRD = 1198,
+ VSTRQ = 1199,
+ VSTRS = 1200,
+ VSUBD = 1201,
+ VSUBHNv2i32 = 1202,
+ VSUBHNv4i16 = 1203,
+ VSUBHNv8i8 = 1204,
+ VSUBLsv2i64 = 1205,
+ VSUBLsv4i32 = 1206,
+ VSUBLsv8i16 = 1207,
+ VSUBLuv2i64 = 1208,
+ VSUBLuv4i32 = 1209,
+ VSUBLuv8i16 = 1210,
+ VSUBS = 1211,
+ VSUBWsv2i64 = 1212,
+ VSUBWsv4i32 = 1213,
+ VSUBWsv8i16 = 1214,
+ VSUBWuv2i64 = 1215,
+ VSUBWuv4i32 = 1216,
+ VSUBWuv8i16 = 1217,
+ VSUBfd = 1218,
+ VSUBfd_sfp = 1219,
+ VSUBfq = 1220,
+ VSUBv16i8 = 1221,
+ VSUBv1i64 = 1222,
+ VSUBv2i32 = 1223,
+ VSUBv2i64 = 1224,
+ VSUBv4i16 = 1225,
+ VSUBv4i32 = 1226,
+ VSUBv8i16 = 1227,
+ VSUBv8i8 = 1228,
+ VTBL1 = 1229,
+ VTBL2 = 1230,
+ VTBL3 = 1231,
+ VTBL4 = 1232,
+ VTBX1 = 1233,
+ VTBX2 = 1234,
+ VTBX3 = 1235,
+ VTBX4 = 1236,
+ VTOSHD = 1237,
+ VTOSHS = 1238,
+ VTOSIRD = 1239,
+ VTOSIRS = 1240,
+ VTOSIZD = 1241,
+ VTOSIZS = 1242,
+ VTOSLD = 1243,
+ VTOSLS = 1244,
+ VTOUHD = 1245,
+ VTOUHS = 1246,
+ VTOUIRD = 1247,
+ VTOUIRS = 1248,
+ VTOUIZD = 1249,
+ VTOUIZS = 1250,
+ VTOULD = 1251,
+ VTOULS = 1252,
+ VTRNd16 = 1253,
+ VTRNd32 = 1254,
+ VTRNd8 = 1255,
+ VTRNq16 = 1256,
+ VTRNq32 = 1257,
+ VTRNq8 = 1258,
+ VTSTv16i8 = 1259,
+ VTSTv2i32 = 1260,
+ VTSTv4i16 = 1261,
+ VTSTv4i32 = 1262,
+ VTSTv8i16 = 1263,
+ VTSTv8i8 = 1264,
+ VUHTOD = 1265,
+ VUHTOS = 1266,
+ VUITOD = 1267,
+ VUITOS = 1268,
+ VULTOD = 1269,
+ VULTOS = 1270,
+ VUZPd16 = 1271,
+ VUZPd32 = 1272,
+ VUZPd8 = 1273,
+ VUZPq16 = 1274,
+ VUZPq32 = 1275,
+ VUZPq8 = 1276,
+ VZIPd16 = 1277,
+ VZIPd32 = 1278,
+ VZIPd8 = 1279,
+ VZIPq16 = 1280,
+ VZIPq32 = 1281,
+ VZIPq8 = 1282,
+ WFE = 1283,
+ WFI = 1284,
+ YIELD = 1285,
+ t2ADCSri = 1286,
+ t2ADCSrr = 1287,
+ t2ADCSrs = 1288,
+ t2ADCri = 1289,
+ t2ADCrr = 1290,
+ t2ADCrs = 1291,
+ t2ADDSri = 1292,
+ t2ADDSrr = 1293,
+ t2ADDSrs = 1294,
+ t2ADDrSPi = 1295,
+ t2ADDrSPi12 = 1296,
+ t2ADDrSPs = 1297,
+ t2ADDri = 1298,
+ t2ADDri12 = 1299,
+ t2ADDrr = 1300,
+ t2ADDrs = 1301,
+ t2ANDri = 1302,
+ t2ANDrr = 1303,
+ t2ANDrs = 1304,
+ t2ASRri = 1305,
+ t2ASRrr = 1306,
+ t2B = 1307,
+ t2BFC = 1308,
+ t2BFI = 1309,
+ t2BICri = 1310,
+ t2BICrr = 1311,
+ t2BICrs = 1312,
+ t2BR_JT = 1313,
+ t2Bcc = 1314,
+ t2CLZ = 1315,
+ t2CMNzri = 1316,
+ t2CMNzrr = 1317,
+ t2CMNzrs = 1318,
+ t2CMPri = 1319,
+ t2CMPrr = 1320,
+ t2CMPrs = 1321,
+ t2CMPzri = 1322,
+ t2CMPzrr = 1323,
+ t2CMPzrs = 1324,
+ t2EORri = 1325,
+ t2EORrr = 1326,
+ t2EORrs = 1327,
+ t2IT = 1328,
+ t2Int_MemBarrierV7 = 1329,
+ t2Int_SyncBarrierV7 = 1330,
+ t2Int_eh_sjlj_setjmp = 1331,
+ t2LDM = 1332,
+ t2LDM_RET = 1333,
+ t2LDRB_POST = 1334,
+ t2LDRB_PRE = 1335,
+ t2LDRBi12 = 1336,
+ t2LDRBi8 = 1337,
+ t2LDRBpci = 1338,
+ t2LDRBs = 1339,
+ t2LDRDi8 = 1340,
+ t2LDRDpci = 1341,
+ t2LDREX = 1342,
+ t2LDREXB = 1343,
+ t2LDREXD = 1344,
+ t2LDREXH = 1345,
+ t2LDRH_POST = 1346,
+ t2LDRH_PRE = 1347,
+ t2LDRHi12 = 1348,
+ t2LDRHi8 = 1349,
+ t2LDRHpci = 1350,
+ t2LDRHs = 1351,
+ t2LDRSB_POST = 1352,
+ t2LDRSB_PRE = 1353,
+ t2LDRSBi12 = 1354,
+ t2LDRSBi8 = 1355,
+ t2LDRSBpci = 1356,
+ t2LDRSBs = 1357,
+ t2LDRSH_POST = 1358,
+ t2LDRSH_PRE = 1359,
+ t2LDRSHi12 = 1360,
+ t2LDRSHi8 = 1361,
+ t2LDRSHpci = 1362,
+ t2LDRSHs = 1363,
+ t2LDR_POST = 1364,
+ t2LDR_PRE = 1365,
+ t2LDRi12 = 1366,
+ t2LDRi8 = 1367,
+ t2LDRpci = 1368,
+ t2LDRpci_pic = 1369,
+ t2LDRs = 1370,
+ t2LEApcrel = 1371,
+ t2LEApcrelJT = 1372,
+ t2LSLri = 1373,
+ t2LSLrr = 1374,
+ t2LSRri = 1375,
+ t2LSRrr = 1376,
+ t2MLA = 1377,
+ t2MLS = 1378,
+ t2MOVCCasr = 1379,
+ t2MOVCCi = 1380,
+ t2MOVCClsl = 1381,
+ t2MOVCClsr = 1382,
+ t2MOVCCr = 1383,
+ t2MOVCCror = 1384,
+ t2MOVTi16 = 1385,
+ t2MOVi = 1386,
+ t2MOVi16 = 1387,
+ t2MOVi32imm = 1388,
+ t2MOVr = 1389,
+ t2MOVrx = 1390,
+ t2MOVsra_flag = 1391,
+ t2MOVsrl_flag = 1392,
+ t2MUL = 1393,
+ t2MVNi = 1394,
+ t2MVNr = 1395,
+ t2MVNs = 1396,
+ t2ORNri = 1397,
+ t2ORNrr = 1398,
+ t2ORNrs = 1399,
+ t2ORRri = 1400,
+ t2ORRrr = 1401,
+ t2ORRrs = 1402,
+ t2PKHBT = 1403,
+ t2PKHTB = 1404,
+ t2RBIT = 1405,
+ t2REV = 1406,
+ t2REV16 = 1407,
+ t2REVSH = 1408,
+ t2RORri = 1409,
+ t2RORrr = 1410,
+ t2RSBSri = 1411,
+ t2RSBSrs = 1412,
+ t2RSBri = 1413,
+ t2RSBrs = 1414,
+ t2SBCSri = 1415,
+ t2SBCSrr = 1416,
+ t2SBCSrs = 1417,
+ t2SBCri = 1418,
+ t2SBCrr = 1419,
+ t2SBCrs = 1420,
+ t2SBFX = 1421,
+ t2SMLABB = 1422,
+ t2SMLABT = 1423,
+ t2SMLAL = 1424,
+ t2SMLATB = 1425,
+ t2SMLATT = 1426,
+ t2SMLAWB = 1427,
+ t2SMLAWT = 1428,
+ t2SMMLA = 1429,
+ t2SMMLS = 1430,
+ t2SMMUL = 1431,
+ t2SMULBB = 1432,
+ t2SMULBT = 1433,
+ t2SMULL = 1434,
+ t2SMULTB = 1435,
+ t2SMULTT = 1436,
+ t2SMULWB = 1437,
+ t2SMULWT = 1438,
+ t2STM = 1439,
+ t2STRB_POST = 1440,
+ t2STRB_PRE = 1441,
+ t2STRBi12 = 1442,
+ t2STRBi8 = 1443,
+ t2STRBs = 1444,
+ t2STRDi8 = 1445,
+ t2STREX = 1446,
+ t2STREXB = 1447,
+ t2STREXD = 1448,
+ t2STREXH = 1449,
+ t2STRH_POST = 1450,
+ t2STRH_PRE = 1451,
+ t2STRHi12 = 1452,
+ t2STRHi8 = 1453,
+ t2STRHs = 1454,
+ t2STR_POST = 1455,
+ t2STR_PRE = 1456,
+ t2STRi12 = 1457,
+ t2STRi8 = 1458,
+ t2STRs = 1459,
+ t2SUBSri = 1460,
+ t2SUBSrr = 1461,
+ t2SUBSrs = 1462,
+ t2SUBrSPi = 1463,
+ t2SUBrSPi12 = 1464,
+ t2SUBrSPi12_ = 1465,
+ t2SUBrSPi_ = 1466,
+ t2SUBrSPs = 1467,
+ t2SUBrSPs_ = 1468,
+ t2SUBri = 1469,
+ t2SUBri12 = 1470,
+ t2SUBrr = 1471,
+ t2SUBrs = 1472,
+ t2SXTABrr = 1473,
+ t2SXTABrr_rot = 1474,
+ t2SXTAHrr = 1475,
+ t2SXTAHrr_rot = 1476,
+ t2SXTBr = 1477,
+ t2SXTBr_rot = 1478,
+ t2SXTHr = 1479,
+ t2SXTHr_rot = 1480,
+ t2TBB = 1481,
+ t2TBH = 1482,
+ t2TEQri = 1483,
+ t2TEQrr = 1484,
+ t2TEQrs = 1485,
+ t2TPsoft = 1486,
+ t2TSTri = 1487,
+ t2TSTrr = 1488,
+ t2TSTrs = 1489,
+ t2UBFX = 1490,
+ t2UMAAL = 1491,
+ t2UMLAL = 1492,
+ t2UMULL = 1493,
+ t2UXTABrr = 1494,
+ t2UXTABrr_rot = 1495,
+ t2UXTAHrr = 1496,
+ t2UXTAHrr_rot = 1497,
+ t2UXTB16r = 1498,
+ t2UXTB16r_rot = 1499,
+ t2UXTBr = 1500,
+ t2UXTBr_rot = 1501,
+ t2UXTHr = 1502,
+ t2UXTHr_rot = 1503,
+ tADC = 1504,
+ tADDhirr = 1505,
+ tADDi3 = 1506,
+ tADDi8 = 1507,
+ tADDrPCi = 1508,
+ tADDrSP = 1509,
+ tADDrSPi = 1510,
+ tADDrr = 1511,
+ tADDspi = 1512,
+ tADDspr = 1513,
+ tADDspr_ = 1514,
+ tADJCALLSTACKDOWN = 1515,
+ tADJCALLSTACKUP = 1516,
+ tAND = 1517,
+ tANDsp = 1518,
+ tASRri = 1519,
+ tASRrr = 1520,
+ tB = 1521,
+ tBIC = 1522,
+ tBKPT = 1523,
+ tBL = 1524,
+ tBLXi = 1525,
+ tBLXi_r9 = 1526,
+ tBLXr = 1527,
+ tBLXr_r9 = 1528,
+ tBLr9 = 1529,
+ tBRIND = 1530,
+ tBR_JTr = 1531,
+ tBX = 1532,
+ tBX_RET = 1533,
+ tBX_RET_vararg = 1534,
+ tBXr9 = 1535,
+ tBcc = 1536,
+ tBfar = 1537,
+ tCBNZ = 1538,
+ tCBZ = 1539,
+ tCMNz = 1540,
+ tCMPhir = 1541,
+ tCMPi8 = 1542,
+ tCMPr = 1543,
+ tCMPzhir = 1544,
+ tCMPzi8 = 1545,
+ tCMPzr = 1546,
+ tEOR = 1547,
+ tInt_eh_sjlj_setjmp = 1548,
+ tLDM = 1549,
+ tLDR = 1550,
+ tLDRB = 1551,
+ tLDRBi = 1552,
+ tLDRH = 1553,
+ tLDRHi = 1554,
+ tLDRSB = 1555,
+ tLDRSH = 1556,
+ tLDRcp = 1557,
+ tLDRi = 1558,
+ tLDRpci = 1559,
+ tLDRpci_pic = 1560,
+ tLDRspi = 1561,
+ tLEApcrel = 1562,
+ tLEApcrelJT = 1563,
+ tLSLri = 1564,
+ tLSLrr = 1565,
+ tLSRri = 1566,
+ tLSRrr = 1567,
+ tMOVCCi = 1568,
+ tMOVCCr = 1569,
+ tMOVCCr_pseudo = 1570,
+ tMOVSr = 1571,
+ tMOVgpr2gpr = 1572,
+ tMOVgpr2tgpr = 1573,
+ tMOVi8 = 1574,
+ tMOVr = 1575,
+ tMOVtgpr2gpr = 1576,
+ tMUL = 1577,
+ tMVN = 1578,
+ tORR = 1579,
+ tPICADD = 1580,
+ tPOP = 1581,
+ tPOP_RET = 1582,
+ tPUSH = 1583,
+ tREV = 1584,
+ tREV16 = 1585,
+ tREVSH = 1586,
+ tROR = 1587,
+ tRSB = 1588,
+ tRestore = 1589,
+ tSBC = 1590,
+ tSTM = 1591,
+ tSTR = 1592,
+ tSTRB = 1593,
+ tSTRBi = 1594,
+ tSTRH = 1595,
+ tSTRHi = 1596,
+ tSTRi = 1597,
+ tSTRspi = 1598,
+ tSUBi3 = 1599,
+ tSUBi8 = 1600,
+ tSUBrr = 1601,
+ tSUBspi = 1602,
+ tSUBspi_ = 1603,
+ tSXTB = 1604,
+ tSXTH = 1605,
+ tSpill = 1606,
+ tTPsoft = 1607,
+ tTST = 1608,
+ tUXTB = 1609,
+ tUXTH = 1610,
+ INSTRUCTION_LIST_END = 1611
};
}
} // End llvm namespace
diff --git a/libclamav/c++/ARMGenRegisterInfo.inc b/libclamav/c++/ARMGenRegisterInfo.inc
index ec628fb..9e40132 100644
--- a/libclamav/c++/ARMGenRegisterInfo.inc
+++ b/libclamav/c++/ARMGenRegisterInfo.inc
@@ -2648,7 +2648,7 @@ ARM::NoRegister, ARM::NoRegister };
const unsigned D10_AliasSet[] = { ARM::S20, ARM::S21, ARM::Q5, 0 };
const unsigned D11_AliasSet[] = { ARM::S22, ARM::S23, ARM::Q5, 0 };
const unsigned D12_AliasSet[] = { ARM::S24, ARM::S25, ARM::Q6, 0 };
- const unsigned D13_AliasSet[] = { ARM::S27, ARM::S26, ARM::Q6, 0 };
+ const unsigned D13_AliasSet[] = { ARM::S26, ARM::S27, ARM::Q6, 0 };
const unsigned D14_AliasSet[] = { ARM::S28, ARM::S29, ARM::Q7, 0 };
const unsigned D15_AliasSet[] = { ARM::S30, ARM::S31, ARM::Q7, 0 };
const unsigned D16_AliasSet[] = { ARM::Q8, 0 };
@@ -2690,7 +2690,7 @@ ARM::NoRegister, ARM::NoRegister };
const unsigned Q3_AliasSet[] = { ARM::S12, ARM::S13, ARM::S14, ARM::S15, ARM::D6, ARM::D7, 0 };
const unsigned Q4_AliasSet[] = { ARM::S16, ARM::S17, ARM::S18, ARM::S19, ARM::D8, ARM::D9, 0 };
const unsigned Q5_AliasSet[] = { ARM::S20, ARM::S21, ARM::S22, ARM::S23, ARM::D10, ARM::D11, 0 };
- const unsigned Q6_AliasSet[] = { ARM::S27, ARM::S24, ARM::S25, ARM::S26, ARM::D12, ARM::D13, 0 };
+ const unsigned Q6_AliasSet[] = { ARM::S24, ARM::S25, ARM::S26, ARM::S27, ARM::D12, ARM::D13, 0 };
const unsigned Q7_AliasSet[] = { ARM::S28, ARM::S29, ARM::S30, ARM::S31, ARM::D14, ARM::D15, 0 };
const unsigned Q8_AliasSet[] = { ARM::D16, ARM::D17, 0 };
const unsigned Q9_AliasSet[] = { ARM::D18, ARM::D19, 0 };
@@ -2751,7 +2751,7 @@ ARM::NoRegister, ARM::NoRegister };
const unsigned D10_SubRegsSet[] = { ARM::S20, ARM::S21, 0 };
const unsigned D11_SubRegsSet[] = { ARM::S22, ARM::S23, 0 };
const unsigned D12_SubRegsSet[] = { ARM::S24, ARM::S25, 0 };
- const unsigned D13_SubRegsSet[] = { ARM::S27, ARM::S26, 0 };
+ const unsigned D13_SubRegsSet[] = { ARM::S26, ARM::S27, 0 };
const unsigned D14_SubRegsSet[] = { ARM::S28, ARM::S29, 0 };
const unsigned D15_SubRegsSet[] = { ARM::S30, ARM::S31, 0 };
const unsigned D16_SubRegsSet[] = { 0 };
@@ -2793,7 +2793,7 @@ ARM::NoRegister, ARM::NoRegister };
const unsigned Q3_SubRegsSet[] = { ARM::S12, ARM::S13, ARM::D7, ARM::S14, ARM::S15, ARM::D6, 0 };
const unsigned Q4_SubRegsSet[] = { ARM::S16, ARM::S17, ARM::D9, ARM::S18, ARM::S19, ARM::D8, 0 };
const unsigned Q5_SubRegsSet[] = { ARM::S20, ARM::S21, ARM::D11, ARM::S22, ARM::S23, ARM::D10, 0 };
- const unsigned Q6_SubRegsSet[] = { ARM::D13, ARM::S27, ARM::S24, ARM::S25, ARM::S26, ARM::D12, 0 };
+ const unsigned Q6_SubRegsSet[] = { ARM::S24, ARM::S25, ARM::D13, ARM::S26, ARM::S27, ARM::D12, 0 };
const unsigned Q7_SubRegsSet[] = { ARM::S28, ARM::S29, ARM::D15, ARM::S30, ARM::S31, ARM::D14, 0 };
const unsigned Q8_SubRegsSet[] = { ARM::D16, ARM::D17, 0 };
const unsigned Q9_SubRegsSet[] = { ARM::D18, ARM::D19, 0 };
diff --git a/libclamav/c++/Makefile.am b/libclamav/c++/Makefile.am
index b980d9a..24b27b6 100644
--- a/libclamav/c++/Makefile.am
+++ b/libclamav/c++/Makefile.am
@@ -143,7 +143,6 @@ libllvmsupport_la_SOURCES=\
llvm/lib/Support/regexec.c\
llvm/lib/Support/regfree.c\
llvm/lib/Support/regstrlcpy.c
-
if MAINTAINER_MODE
BUILT_SOURCES+=$(TBLGENFILES)
noinst_PROGRAMS = tblgen
@@ -157,14 +156,19 @@ tblgen_LDFLAGS=-pthread -Wl,--version-script, at top_srcdir@/llvm/autoconf/ExportMa
tblgen_SOURCES=\
llvm/utils/TableGen/AsmMatcherEmitter.cpp\
llvm/utils/TableGen/AsmWriterEmitter.cpp\
+ llvm/utils/TableGen/AsmWriterInst.cpp\
llvm/utils/TableGen/CallingConvEmitter.cpp\
llvm/utils/TableGen/ClangDiagnosticsEmitter.cpp\
llvm/utils/TableGen/CodeEmitterGen.cpp\
llvm/utils/TableGen/CodeGenDAGPatterns.cpp\
llvm/utils/TableGen/CodeGenInstruction.cpp\
llvm/utils/TableGen/CodeGenTarget.cpp\
- llvm/utils/TableGen/DisassemblerEmitter.cpp\
llvm/utils/TableGen/DAGISelEmitter.cpp\
+ llvm/utils/TableGen/DAGISelMatcher.cpp\
+ llvm/utils/TableGen/DAGISelMatcherEmitter.cpp\
+ llvm/utils/TableGen/DAGISelMatcherGen.cpp\
+ llvm/utils/TableGen/DisassemblerEmitter.cpp\
+ llvm/utils/TableGen/EDEmitter.cpp\
llvm/utils/TableGen/FastISelEmitter.cpp\
llvm/utils/TableGen/InstrEnumEmitter.cpp\
llvm/utils/TableGen/InstrInfoEmitter.cpp\
@@ -359,7 +363,6 @@ endif
if BUILD_X86
libllvmx86codegen_la_CPPFLAGS=$(LLVM_INCLUDES) $(LLVM_DEFS) -I$(top_builddir) -I$(top_srcdir)/llvm/lib/Target/X86
libllvmx86codegen_la_SOURCES=\
- llvm/lib/CodeGen/DeadMachineInstructionElim.cpp\
llvm/lib/CodeGen/MachineModuleInfoImpls.cpp\
llvm/lib/MC/MCAsmInfoCOFF.cpp\
llvm/lib/MC/MCCodeEmitter.cpp\
@@ -376,6 +379,8 @@ libllvmx86codegen_la_SOURCES=\
llvm/lib/Target/X86/X86InstrInfo.cpp\
llvm/lib/Target/X86/X86JITInfo.cpp\
llvm/lib/Target/X86/X86MCAsmInfo.cpp\
+ llvm/lib/Target/X86/X86MCCodeEmitter.cpp\
+ llvm/lib/Target/X86/X86MCTargetExpr.cpp\
llvm/lib/Target/X86/X86RegisterInfo.cpp\
llvm/lib/Target/X86/X86Subtarget.cpp\
llvm/lib/Target/X86/X86TargetMachine.cpp\
@@ -515,6 +520,7 @@ libllvmjit_la_SOURCES=\
llvm/lib/VMCore/Core.cpp\
llvm/lib/VMCore/Dominators.cpp\
llvm/lib/VMCore/Function.cpp\
+ llvm/lib/VMCore/GVMaterializer.cpp\
llvm/lib/VMCore/Globals.cpp\
llvm/lib/VMCore/IRBuilder.cpp\
llvm/lib/VMCore/InlineAsm.cpp\
@@ -525,7 +531,6 @@ libllvmjit_la_SOURCES=\
llvm/lib/VMCore/LeakDetector.cpp\
llvm/lib/VMCore/Metadata.cpp\
llvm/lib/VMCore/Module.cpp\
- llvm/lib/VMCore/ModuleProvider.cpp\
llvm/lib/VMCore/Pass.cpp\
llvm/lib/VMCore/PassManager.cpp\
llvm/lib/VMCore/PrintModulePass.cpp\
@@ -561,6 +566,7 @@ libllvmcodegen_la_SOURCES=\
llvm/lib/CodeGen/CalcSpillWeights.cpp\
llvm/lib/CodeGen/CodePlacementOpt.cpp\
llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp\
+ llvm/lib/CodeGen/DeadMachineInstructionElim.cpp\
llvm/lib/CodeGen/DwarfEHPrepare.cpp\
llvm/lib/CodeGen/ExactHazardRecognizer.cpp\
llvm/lib/CodeGen/GCMetadata.cpp\
@@ -572,7 +578,6 @@ libllvmcodegen_la_SOURCES=\
llvm/lib/CodeGen/LiveStackAnalysis.cpp\
llvm/lib/CodeGen/LiveVariables.cpp\
llvm/lib/CodeGen/LowerSubregs.cpp\
- llvm/lib/CodeGen/MachOWriter.cpp\
llvm/lib/CodeGen/MachineDominators.cpp\
llvm/lib/CodeGen/MachineLICM.cpp\
llvm/lib/CodeGen/MachineLoopInfo.cpp\
@@ -581,6 +586,7 @@ libllvmcodegen_la_SOURCES=\
llvm/lib/CodeGen/MachineSink.cpp\
llvm/lib/CodeGen/MachineVerifier.cpp\
llvm/lib/CodeGen/OptimizeExts.cpp\
+ llvm/lib/CodeGen/OptimizePHIs.cpp\
llvm/lib/CodeGen/PHIElimination.cpp\
llvm/lib/CodeGen/Passes.cpp\
llvm/lib/CodeGen/PostRASchedulerList.cpp\
@@ -633,6 +639,7 @@ libllvmcodegen_la_SOURCES=\
llvm/lib/MC/MCAssembler.cpp\
llvm/lib/MC/MCInst.cpp\
llvm/lib/MC/MCMachOStreamer.cpp\
+ llvm/lib/MC/MCNullStreamer.cpp\
llvm/lib/MC/MCStreamer.cpp\
llvm/lib/Target/TargetFrameInfo.cpp\
llvm/lib/Target/TargetSubtarget.cpp\
@@ -656,6 +663,7 @@ libllvmcodegen_la_SOURCES=\
llvm/lib/Transforms/Utils/UnifyFunctionExitNodes.cpp
+
# Used only by make check
libllvmbitreader_la_SOURCES=\
@@ -796,7 +804,6 @@ libllvmasmprinter_la_SOURCES+= llvm/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
endif
libllvmfullcodegen_la_SOURCES=\
- llvm/lib/CodeGen/DeadMachineInstructionElim.cpp\
llvm/lib/CodeGen/GCMetadataPrinter.cpp\
llvm/lib/CodeGen/IfConversion.cpp\
llvm/lib/CodeGen/IntrinsicLowering.cpp\
@@ -811,8 +818,7 @@ libllvmfullcodegen_la_SOURCES=\
llvm/lib/Target/Target.cpp\
llvm/lib/Target/TargetAsmLexer.cpp\
llvm/lib/Target/TargetELFWriterInfo.cpp\
- llvm/lib/Target/TargetIntrinsicInfo.cpp\
- llvm/lib/Target/TargetMachOWriterInfo.cpp
+ llvm/lib/Target/TargetIntrinsicInfo.cpp
lli_LDADD+=libllvmfullcodegen.la libllvmcodegen.la libllvmjit.la libllvmsupport.la libllvmsystem.la
lli_SOURCES=\
diff --git a/libclamav/c++/Makefile.in b/libclamav/c++/Makefile.in
index 7525337..3d22bed 100644
--- a/libclamav/c++/Makefile.in
+++ b/libclamav/c++/Makefile.in
@@ -229,14 +229,14 @@ am_libllvmcodegen_la_OBJECTS = AliasSetTracker.lo ConstantFolding.lo \
AggressiveAntiDepBreaker.lo AsmPrinter.lo DIE.lo DwarfDebug.lo \
DwarfException.lo DwarfLabel.lo DwarfPrinter.lo DwarfWriter.lo \
BranchFolding.lo CalcSpillWeights.lo CodePlacementOpt.lo \
- CriticalAntiDepBreaker.lo DwarfEHPrepare.lo \
- ExactHazardRecognizer.lo GCMetadata.lo GCStrategy.lo \
- LLVMTargetMachine.lo LatencyPriorityQueue.lo LiveInterval.lo \
- LiveIntervalAnalysis.lo LiveStackAnalysis.lo LiveVariables.lo \
- LowerSubregs.lo MachOWriter.lo MachineDominators.lo \
+ CriticalAntiDepBreaker.lo DeadMachineInstructionElim.lo \
+ DwarfEHPrepare.lo ExactHazardRecognizer.lo GCMetadata.lo \
+ GCStrategy.lo LLVMTargetMachine.lo LatencyPriorityQueue.lo \
+ LiveInterval.lo LiveIntervalAnalysis.lo LiveStackAnalysis.lo \
+ LiveVariables.lo LowerSubregs.lo MachineDominators.lo \
MachineLICM.lo MachineLoopInfo.lo MachinePassRegistry.lo \
MachineSSAUpdater.lo MachineSink.lo MachineVerifier.lo \
- OptimizeExts.lo PHIElimination.lo Passes.lo \
+ OptimizeExts.lo OptimizePHIs.lo PHIElimination.lo Passes.lo \
PostRASchedulerList.lo PreAllocSplitting.lo \
ProcessImplicitDefs.lo PrologEpilogInserter.lo \
RegAllocLinearScan.lo RegisterCoalescer.lo \
@@ -256,22 +256,21 @@ am_libllvmcodegen_la_OBJECTS = AliasSetTracker.lo ConstantFolding.lo \
TwoAddressInstructionPass.lo UnreachableBlockElim.lo \
VirtRegMap.lo VirtRegRewriter.lo MCAsmInfoDarwin.lo \
MCAsmStreamer.lo MCAssembler.lo MCInst.lo MCMachOStreamer.lo \
- MCStreamer.lo TargetFrameInfo.lo TargetSubtarget.lo \
- CodeGenPrepare.lo GEPSplitter.lo GVN.lo LoopStrengthReduce.lo \
- AddrModeMatcher.lo BasicBlockUtils.lo BreakCriticalEdges.lo \
- DemoteRegToStack.lo LCSSA.lo Local.lo LoopSimplify.lo \
- LowerInvoke.lo LowerSwitch.lo Mem2Reg.lo \
+ MCNullStreamer.lo MCStreamer.lo TargetFrameInfo.lo \
+ TargetSubtarget.lo CodeGenPrepare.lo GEPSplitter.lo GVN.lo \
+ LoopStrengthReduce.lo AddrModeMatcher.lo BasicBlockUtils.lo \
+ BreakCriticalEdges.lo DemoteRegToStack.lo LCSSA.lo Local.lo \
+ LoopSimplify.lo LowerInvoke.lo LowerSwitch.lo Mem2Reg.lo \
PromoteMemoryToRegister.lo SSAUpdater.lo SimplifyCFG.lo \
UnifyFunctionExitNodes.lo
libllvmcodegen_la_OBJECTS = $(am_libllvmcodegen_la_OBJECTS)
libllvmfullcodegen_la_LIBADD =
-am_libllvmfullcodegen_la_OBJECTS = DeadMachineInstructionElim.lo \
- GCMetadataPrinter.lo IfConversion.lo IntrinsicLowering.lo \
- MachineModuleInfoImpls.lo OcamlGC.lo RegAllocLocal.lo \
- RegAllocPBQP.lo ShadowStackGC.lo Execution.lo \
- ExternalFunctions.lo Interpreter.lo Target.lo \
+am_libllvmfullcodegen_la_OBJECTS = GCMetadataPrinter.lo \
+ IfConversion.lo IntrinsicLowering.lo MachineModuleInfoImpls.lo \
+ OcamlGC.lo RegAllocLocal.lo RegAllocPBQP.lo ShadowStackGC.lo \
+ Execution.lo ExternalFunctions.lo Interpreter.lo Target.lo \
TargetAsmLexer.lo TargetELFWriterInfo.lo \
- TargetIntrinsicInfo.lo TargetMachOWriterInfo.lo
+ TargetIntrinsicInfo.lo
libllvmfullcodegen_la_OBJECTS = $(am_libllvmfullcodegen_la_OBJECTS)
libllvminterpreter_la_LIBADD =
am_libllvminterpreter_la_OBJECTS = Execution.lo ExternalFunctions.lo \
@@ -302,11 +301,11 @@ am_libllvmjit_la_OBJECTS = AliasAnalysis.lo BasicAliasAnalysis.lo \
TargetLoweringObjectFile.lo TargetMachine.lo \
TargetRegisterInfo.lo AsmWriter.lo Attributes.lo \
AutoUpgrade.lo BasicBlock.lo ConstantFold.lo Constants.lo \
- Core.lo Dominators.lo Function.lo Globals.lo IRBuilder.lo \
- InlineAsm.lo Instruction.lo Instructions.lo IntrinsicInst.lo \
- LLVMContext.lo LeakDetector.lo Metadata.lo Module.lo \
- ModuleProvider.lo Pass.lo PassManager.lo PrintModulePass.lo \
- Type.lo TypeSymbolTable.lo Use.lo Value.lo ValueSymbolTable.lo \
+ Core.lo Dominators.lo Function.lo GVMaterializer.lo Globals.lo \
+ IRBuilder.lo InlineAsm.lo Instruction.lo Instructions.lo \
+ IntrinsicInst.lo LLVMContext.lo LeakDetector.lo Metadata.lo \
+ Module.lo Pass.lo PassManager.lo PrintModulePass.lo Type.lo \
+ TypeSymbolTable.lo Use.lo Value.lo ValueSymbolTable.lo \
ValueTypes.lo Verifier.lo
libllvmjit_la_OBJECTS = $(am_libllvmjit_la_OBJECTS)
libllvmpowerpccodegen_la_LIBADD =
@@ -371,7 +370,6 @@ libllvmsystem_la_LINK = $(LIBTOOL) $(AM_V_lt) --tag=CXX \
$(LDFLAGS) -o $@
libllvmx86codegen_la_LIBADD =
am__libllvmx86codegen_la_SOURCES_DIST = \
- llvm/lib/CodeGen/DeadMachineInstructionElim.cpp \
llvm/lib/CodeGen/MachineModuleInfoImpls.cpp \
llvm/lib/MC/MCAsmInfoCOFF.cpp llvm/lib/MC/MCCodeEmitter.cpp \
llvm/lib/Target/TargetELFWriterInfo.cpp \
@@ -387,12 +385,13 @@ am__libllvmx86codegen_la_SOURCES_DIST = \
llvm/lib/Target/X86/X86InstrInfo.cpp \
llvm/lib/Target/X86/X86JITInfo.cpp \
llvm/lib/Target/X86/X86MCAsmInfo.cpp \
+ llvm/lib/Target/X86/X86MCCodeEmitter.cpp \
+ llvm/lib/Target/X86/X86MCTargetExpr.cpp \
llvm/lib/Target/X86/X86RegisterInfo.cpp \
llvm/lib/Target/X86/X86Subtarget.cpp \
llvm/lib/Target/X86/X86TargetMachine.cpp \
llvm/lib/Target/X86/X86TargetObjectFile.cpp
- at BUILD_X86_TRUE@am_libllvmx86codegen_la_OBJECTS = libllvmx86codegen_la-DeadMachineInstructionElim.lo \
- at BUILD_X86_TRUE@ libllvmx86codegen_la-MachineModuleInfoImpls.lo \
+ at BUILD_X86_TRUE@am_libllvmx86codegen_la_OBJECTS = libllvmx86codegen_la-MachineModuleInfoImpls.lo \
@BUILD_X86_TRUE@ libllvmx86codegen_la-MCAsmInfoCOFF.lo \
@BUILD_X86_TRUE@ libllvmx86codegen_la-MCCodeEmitter.lo \
@BUILD_X86_TRUE@ libllvmx86codegen_la-TargetELFWriterInfo.lo \
@@ -408,6 +407,8 @@ am__libllvmx86codegen_la_SOURCES_DIST = \
@BUILD_X86_TRUE@ libllvmx86codegen_la-X86InstrInfo.lo \
@BUILD_X86_TRUE@ libllvmx86codegen_la-X86JITInfo.lo \
@BUILD_X86_TRUE@ libllvmx86codegen_la-X86MCAsmInfo.lo \
+ at BUILD_X86_TRUE@ libllvmx86codegen_la-X86MCCodeEmitter.lo \
+ at BUILD_X86_TRUE@ libllvmx86codegen_la-X86MCTargetExpr.lo \
@BUILD_X86_TRUE@ libllvmx86codegen_la-X86RegisterInfo.lo \
@BUILD_X86_TRUE@ libllvmx86codegen_la-X86Subtarget.lo \
@BUILD_X86_TRUE@ libllvmx86codegen_la-X86TargetMachine.lo \
@@ -511,14 +512,19 @@ not_LINK = $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) \
$(CXXFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
am__tblgen_SOURCES_DIST = llvm/utils/TableGen/AsmMatcherEmitter.cpp \
llvm/utils/TableGen/AsmWriterEmitter.cpp \
+ llvm/utils/TableGen/AsmWriterInst.cpp \
llvm/utils/TableGen/CallingConvEmitter.cpp \
llvm/utils/TableGen/ClangDiagnosticsEmitter.cpp \
llvm/utils/TableGen/CodeEmitterGen.cpp \
llvm/utils/TableGen/CodeGenDAGPatterns.cpp \
llvm/utils/TableGen/CodeGenInstruction.cpp \
llvm/utils/TableGen/CodeGenTarget.cpp \
- llvm/utils/TableGen/DisassemblerEmitter.cpp \
llvm/utils/TableGen/DAGISelEmitter.cpp \
+ llvm/utils/TableGen/DAGISelMatcher.cpp \
+ llvm/utils/TableGen/DAGISelMatcherEmitter.cpp \
+ llvm/utils/TableGen/DAGISelMatcherGen.cpp \
+ llvm/utils/TableGen/DisassemblerEmitter.cpp \
+ llvm/utils/TableGen/EDEmitter.cpp \
llvm/utils/TableGen/FastISelEmitter.cpp \
llvm/utils/TableGen/InstrEnumEmitter.cpp \
llvm/utils/TableGen/InstrInfoEmitter.cpp \
@@ -578,14 +584,19 @@ am__tblgen_SOURCES_DIST = llvm/utils/TableGen/AsmMatcherEmitter.cpp \
@MAINTAINER_MODE_TRUE at am_tblgen_OBJECTS = \
@MAINTAINER_MODE_TRUE@ tblgen-AsmMatcherEmitter.$(OBJEXT) \
@MAINTAINER_MODE_TRUE@ tblgen-AsmWriterEmitter.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-AsmWriterInst.$(OBJEXT) \
@MAINTAINER_MODE_TRUE@ tblgen-CallingConvEmitter.$(OBJEXT) \
@MAINTAINER_MODE_TRUE@ tblgen-ClangDiagnosticsEmitter.$(OBJEXT) \
@MAINTAINER_MODE_TRUE@ tblgen-CodeEmitterGen.$(OBJEXT) \
@MAINTAINER_MODE_TRUE@ tblgen-CodeGenDAGPatterns.$(OBJEXT) \
@MAINTAINER_MODE_TRUE@ tblgen-CodeGenInstruction.$(OBJEXT) \
@MAINTAINER_MODE_TRUE@ tblgen-CodeGenTarget.$(OBJEXT) \
- at MAINTAINER_MODE_TRUE@ tblgen-DisassemblerEmitter.$(OBJEXT) \
@MAINTAINER_MODE_TRUE@ tblgen-DAGISelEmitter.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-DAGISelMatcher.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-DAGISelMatcherEmitter.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-DAGISelMatcherGen.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-DisassemblerEmitter.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-EDEmitter.$(OBJEXT) \
@MAINTAINER_MODE_TRUE@ tblgen-FastISelEmitter.$(OBJEXT) \
@MAINTAINER_MODE_TRUE@ tblgen-InstrEnumEmitter.$(OBJEXT) \
@MAINTAINER_MODE_TRUE@ tblgen-InstrInfoEmitter.$(OBJEXT) \
@@ -1011,14 +1022,19 @@ libllvmsupport_la_SOURCES = \
@MAINTAINER_MODE_TRUE at tblgen_SOURCES = \
@MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/AsmMatcherEmitter.cpp\
@MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/AsmWriterEmitter.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/AsmWriterInst.cpp\
@MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/CallingConvEmitter.cpp\
@MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/ClangDiagnosticsEmitter.cpp\
@MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/CodeEmitterGen.cpp\
@MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/CodeGenDAGPatterns.cpp\
@MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/CodeGenInstruction.cpp\
@MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/CodeGenTarget.cpp\
- at MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/DisassemblerEmitter.cpp\
@MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/DAGISelEmitter.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/DAGISelMatcher.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/DAGISelMatcherEmitter.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/DAGISelMatcherGen.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/DisassemblerEmitter.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/EDEmitter.cpp\
@MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/FastISelEmitter.cpp\
@MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/InstrEnumEmitter.cpp\
@MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/InstrInfoEmitter.cpp\
@@ -1111,7 +1127,6 @@ libllvmsupport_la_SOURCES = \
@MAINTAINER_MODE_TRUE at TBLGEN_FLAGS_ARM = $(TBLGEN_FLAGS) -I$(top_srcdir)/llvm/lib/Target/ARM
@BUILD_X86_TRUE at libllvmx86codegen_la_CPPFLAGS = $(LLVM_INCLUDES) $(LLVM_DEFS) -I$(top_builddir) -I$(top_srcdir)/llvm/lib/Target/X86
@BUILD_X86_TRUE at libllvmx86codegen_la_SOURCES = \
- at BUILD_X86_TRUE@ llvm/lib/CodeGen/DeadMachineInstructionElim.cpp\
@BUILD_X86_TRUE@ llvm/lib/CodeGen/MachineModuleInfoImpls.cpp\
@BUILD_X86_TRUE@ llvm/lib/MC/MCAsmInfoCOFF.cpp\
@BUILD_X86_TRUE@ llvm/lib/MC/MCCodeEmitter.cpp\
@@ -1128,6 +1143,8 @@ libllvmsupport_la_SOURCES = \
@BUILD_X86_TRUE@ llvm/lib/Target/X86/X86InstrInfo.cpp\
@BUILD_X86_TRUE@ llvm/lib/Target/X86/X86JITInfo.cpp\
@BUILD_X86_TRUE@ llvm/lib/Target/X86/X86MCAsmInfo.cpp\
+ at BUILD_X86_TRUE@ llvm/lib/Target/X86/X86MCCodeEmitter.cpp\
+ at BUILD_X86_TRUE@ llvm/lib/Target/X86/X86MCTargetExpr.cpp\
@BUILD_X86_TRUE@ llvm/lib/Target/X86/X86RegisterInfo.cpp\
@BUILD_X86_TRUE@ llvm/lib/Target/X86/X86Subtarget.cpp\
@BUILD_X86_TRUE@ llvm/lib/Target/X86/X86TargetMachine.cpp\
@@ -1261,6 +1278,7 @@ libllvmjit_la_SOURCES = \
llvm/lib/VMCore/Core.cpp\
llvm/lib/VMCore/Dominators.cpp\
llvm/lib/VMCore/Function.cpp\
+ llvm/lib/VMCore/GVMaterializer.cpp\
llvm/lib/VMCore/Globals.cpp\
llvm/lib/VMCore/IRBuilder.cpp\
llvm/lib/VMCore/InlineAsm.cpp\
@@ -1271,7 +1289,6 @@ libllvmjit_la_SOURCES = \
llvm/lib/VMCore/LeakDetector.cpp\
llvm/lib/VMCore/Metadata.cpp\
llvm/lib/VMCore/Module.cpp\
- llvm/lib/VMCore/ModuleProvider.cpp\
llvm/lib/VMCore/Pass.cpp\
llvm/lib/VMCore/PassManager.cpp\
llvm/lib/VMCore/PrintModulePass.cpp\
@@ -1307,6 +1324,7 @@ libllvmcodegen_la_SOURCES = \
llvm/lib/CodeGen/CalcSpillWeights.cpp\
llvm/lib/CodeGen/CodePlacementOpt.cpp\
llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp\
+ llvm/lib/CodeGen/DeadMachineInstructionElim.cpp\
llvm/lib/CodeGen/DwarfEHPrepare.cpp\
llvm/lib/CodeGen/ExactHazardRecognizer.cpp\
llvm/lib/CodeGen/GCMetadata.cpp\
@@ -1318,7 +1336,6 @@ libllvmcodegen_la_SOURCES = \
llvm/lib/CodeGen/LiveStackAnalysis.cpp\
llvm/lib/CodeGen/LiveVariables.cpp\
llvm/lib/CodeGen/LowerSubregs.cpp\
- llvm/lib/CodeGen/MachOWriter.cpp\
llvm/lib/CodeGen/MachineDominators.cpp\
llvm/lib/CodeGen/MachineLICM.cpp\
llvm/lib/CodeGen/MachineLoopInfo.cpp\
@@ -1327,6 +1344,7 @@ libllvmcodegen_la_SOURCES = \
llvm/lib/CodeGen/MachineSink.cpp\
llvm/lib/CodeGen/MachineVerifier.cpp\
llvm/lib/CodeGen/OptimizeExts.cpp\
+ llvm/lib/CodeGen/OptimizePHIs.cpp\
llvm/lib/CodeGen/PHIElimination.cpp\
llvm/lib/CodeGen/Passes.cpp\
llvm/lib/CodeGen/PostRASchedulerList.cpp\
@@ -1379,6 +1397,7 @@ libllvmcodegen_la_SOURCES = \
llvm/lib/MC/MCAssembler.cpp\
llvm/lib/MC/MCInst.cpp\
llvm/lib/MC/MCMachOStreamer.cpp\
+ llvm/lib/MC/MCNullStreamer.cpp\
llvm/lib/MC/MCStreamer.cpp\
llvm/lib/Target/TargetFrameInfo.cpp\
llvm/lib/Target/TargetSubtarget.cpp\
@@ -1519,7 +1538,6 @@ libllvmasmprinter_la_SOURCES = \
llvm/lib/CodeGen/MachOWriter.cpp $(am__append_14) \
$(am__append_15) $(am__append_16)
libllvmfullcodegen_la_SOURCES = \
- llvm/lib/CodeGen/DeadMachineInstructionElim.cpp\
llvm/lib/CodeGen/GCMetadataPrinter.cpp\
llvm/lib/CodeGen/IfConversion.cpp\
llvm/lib/CodeGen/IntrinsicLowering.cpp\
@@ -1534,8 +1552,7 @@ libllvmfullcodegen_la_SOURCES = \
llvm/lib/Target/Target.cpp\
llvm/lib/Target/TargetAsmLexer.cpp\
llvm/lib/Target/TargetELFWriterInfo.cpp\
- llvm/lib/Target/TargetIntrinsicInfo.cpp\
- llvm/lib/Target/TargetMachOWriterInfo.cpp
+ llvm/lib/Target/TargetIntrinsicInfo.cpp
lli_SOURCES = \
llvm/tools/lli/lli.cpp
@@ -1799,6 +1816,7 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/GCMetadataPrinter.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/GCStrategy.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/GEPSplitter.Plo at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/GVMaterializer.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/GVN.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/Globals.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/GraphWriter.Plo at am__quote@
@@ -1857,12 +1875,12 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/MCExpr.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/MCInst.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/MCMachOStreamer.Plo at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/MCNullStreamer.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/MCSection.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/MCSectionELF.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/MCSectionMachO.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/MCStreamer.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/MCSymbol.Plo at am__quote@
- at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/MachOWriter.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/MachineBasicBlock.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/MachineDominators.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/MachineFunction.Plo at am__quote@
@@ -1888,12 +1906,12 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/MemoryObject.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/Metadata.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/Module.Plo at am__quote@
- at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/ModuleProvider.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/Mutex.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/OProfileJITEventListener.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/ObjectCodeEmitter.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/OcamlGC.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/OptimizeExts.Plo at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/OptimizePHIs.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/PHIElimination.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/PHITransAddr.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/Parser.Plo at am__quote@
@@ -1969,7 +1987,6 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/TargetIntrinsicInfo.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/TargetLowering.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/TargetLoweringObjectFile.Plo at am__quote@
- at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/TargetMachOWriterInfo.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/TargetMachine.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/TargetRegisterInfo.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/TargetRegistry.Plo at am__quote@
@@ -2059,7 +2076,6 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/libllvmpowerpccodegen_la-PPCTargetMachine.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/libllvmpowerpccodegen_la-PowerPCTargetInfo.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/libllvmpowerpccodegen_la-TargetMachOWriterInfo.Plo at am__quote@
- at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/libllvmx86codegen_la-DeadMachineInstructionElim.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/libllvmx86codegen_la-MCAsmInfoCOFF.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/libllvmx86codegen_la-MCCodeEmitter.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/libllvmx86codegen_la-MachineModuleInfoImpls.Plo at am__quote@
@@ -2075,6 +2091,8 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/libllvmx86codegen_la-X86InstrInfo.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/libllvmx86codegen_la-X86JITInfo.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/libllvmx86codegen_la-X86MCAsmInfo.Plo at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/libllvmx86codegen_la-X86MCCodeEmitter.Plo at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/libllvmx86codegen_la-X86MCTargetExpr.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/libllvmx86codegen_la-X86RegisterInfo.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/libllvmx86codegen_la-X86Subtarget.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/libllvmx86codegen_la-X86TargetInfo.Plo at am__quote@
@@ -2131,6 +2149,7 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-Allocator.Po at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-AsmMatcherEmitter.Po at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-AsmWriterEmitter.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-AsmWriterInst.Po at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-Atomic.Po at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-CallingConvEmitter.Po at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-ClangDiagnosticsEmitter.Po at am__quote@
@@ -2141,12 +2160,16 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-CommandLine.Po at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-ConstantRange.Po at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-DAGISelEmitter.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-DAGISelMatcher.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-DAGISelMatcherEmitter.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-DAGISelMatcherGen.Po at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-Debug.Po at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-DeltaAlgorithm.Po at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-Disassembler.Po at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-DisassemblerEmitter.Po at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-Dwarf.Po at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-DynamicLibrary.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-EDEmitter.Po at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-Errno.Po at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-ErrorHandling.Po at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-FastISelEmitter.Po at am__quote@
@@ -3028,6 +3051,14 @@ CriticalAntiDepBreaker.lo: llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp
@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o CriticalAntiDepBreaker.lo `test -f 'llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp
+DeadMachineInstructionElim.lo: llvm/lib/CodeGen/DeadMachineInstructionElim.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT DeadMachineInstructionElim.lo -MD -MP -MF $(DEPDIR)/DeadMachineInstructionElim.Tpo -c -o DeadMachineInstructionElim.lo `test -f 'llvm/lib/CodeGen/DeadMachineInstructionElim.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/DeadMachineInstructionElim.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/DeadMachineInstructionElim.Tpo $(DEPDIR)/DeadMachineInstructionElim.Plo
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/CodeGen/DeadMachineInstructionElim.cpp' object='DeadMachineInstructionElim.lo' libtool=yes @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o DeadMachineInstructionElim.lo `test -f 'llvm/lib/CodeGen/DeadMachineInstructionElim.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/DeadMachineInstructionElim.cpp
+
DwarfEHPrepare.lo: llvm/lib/CodeGen/DwarfEHPrepare.cpp
@am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT DwarfEHPrepare.lo -MD -MP -MF $(DEPDIR)/DwarfEHPrepare.Tpo -c -o DwarfEHPrepare.lo `test -f 'llvm/lib/CodeGen/DwarfEHPrepare.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/DwarfEHPrepare.cpp
@am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/DwarfEHPrepare.Tpo $(DEPDIR)/DwarfEHPrepare.Plo
@@ -3116,14 +3147,6 @@ LowerSubregs.lo: llvm/lib/CodeGen/LowerSubregs.cpp
@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o LowerSubregs.lo `test -f 'llvm/lib/CodeGen/LowerSubregs.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/LowerSubregs.cpp
-MachOWriter.lo: llvm/lib/CodeGen/MachOWriter.cpp
- at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT MachOWriter.lo -MD -MP -MF $(DEPDIR)/MachOWriter.Tpo -c -o MachOWriter.lo `test -f 'llvm/lib/CodeGen/MachOWriter.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/MachOWriter.cpp
- at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/MachOWriter.Tpo $(DEPDIR)/MachOWriter.Plo
- at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
- at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/CodeGen/MachOWriter.cpp' object='MachOWriter.lo' libtool=yes @AMDEPBACKSLASH@
- at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
- at am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o MachOWriter.lo `test -f 'llvm/lib/CodeGen/MachOWriter.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/MachOWriter.cpp
-
MachineDominators.lo: llvm/lib/CodeGen/MachineDominators.cpp
@am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT MachineDominators.lo -MD -MP -MF $(DEPDIR)/MachineDominators.Tpo -c -o MachineDominators.lo `test -f 'llvm/lib/CodeGen/MachineDominators.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/MachineDominators.cpp
@am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/MachineDominators.Tpo $(DEPDIR)/MachineDominators.Plo
@@ -3188,6 +3211,14 @@ OptimizeExts.lo: llvm/lib/CodeGen/OptimizeExts.cpp
@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o OptimizeExts.lo `test -f 'llvm/lib/CodeGen/OptimizeExts.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/OptimizeExts.cpp
+OptimizePHIs.lo: llvm/lib/CodeGen/OptimizePHIs.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT OptimizePHIs.lo -MD -MP -MF $(DEPDIR)/OptimizePHIs.Tpo -c -o OptimizePHIs.lo `test -f 'llvm/lib/CodeGen/OptimizePHIs.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/OptimizePHIs.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/OptimizePHIs.Tpo $(DEPDIR)/OptimizePHIs.Plo
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/CodeGen/OptimizePHIs.cpp' object='OptimizePHIs.lo' libtool=yes @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o OptimizePHIs.lo `test -f 'llvm/lib/CodeGen/OptimizePHIs.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/OptimizePHIs.cpp
+
PHIElimination.lo: llvm/lib/CodeGen/PHIElimination.cpp
@am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT PHIElimination.lo -MD -MP -MF $(DEPDIR)/PHIElimination.Tpo -c -o PHIElimination.lo `test -f 'llvm/lib/CodeGen/PHIElimination.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/PHIElimination.cpp
@am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/PHIElimination.Tpo $(DEPDIR)/PHIElimination.Plo
@@ -3604,6 +3635,14 @@ MCMachOStreamer.lo: llvm/lib/MC/MCMachOStreamer.cpp
@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o MCMachOStreamer.lo `test -f 'llvm/lib/MC/MCMachOStreamer.cpp' || echo '$(srcdir)/'`llvm/lib/MC/MCMachOStreamer.cpp
+MCNullStreamer.lo: llvm/lib/MC/MCNullStreamer.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT MCNullStreamer.lo -MD -MP -MF $(DEPDIR)/MCNullStreamer.Tpo -c -o MCNullStreamer.lo `test -f 'llvm/lib/MC/MCNullStreamer.cpp' || echo '$(srcdir)/'`llvm/lib/MC/MCNullStreamer.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/MCNullStreamer.Tpo $(DEPDIR)/MCNullStreamer.Plo
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/MC/MCNullStreamer.cpp' object='MCNullStreamer.lo' libtool=yes @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o MCNullStreamer.lo `test -f 'llvm/lib/MC/MCNullStreamer.cpp' || echo '$(srcdir)/'`llvm/lib/MC/MCNullStreamer.cpp
+
MCStreamer.lo: llvm/lib/MC/MCStreamer.cpp
@am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT MCStreamer.lo -MD -MP -MF $(DEPDIR)/MCStreamer.Tpo -c -o MCStreamer.lo `test -f 'llvm/lib/MC/MCStreamer.cpp' || echo '$(srcdir)/'`llvm/lib/MC/MCStreamer.cpp
@am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/MCStreamer.Tpo $(DEPDIR)/MCStreamer.Plo
@@ -3772,14 +3811,6 @@ UnifyFunctionExitNodes.lo: llvm/lib/Transforms/Utils/UnifyFunctionExitNodes.cpp
@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o UnifyFunctionExitNodes.lo `test -f 'llvm/lib/Transforms/Utils/UnifyFunctionExitNodes.cpp' || echo '$(srcdir)/'`llvm/lib/Transforms/Utils/UnifyFunctionExitNodes.cpp
-DeadMachineInstructionElim.lo: llvm/lib/CodeGen/DeadMachineInstructionElim.cpp
- at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT DeadMachineInstructionElim.lo -MD -MP -MF $(DEPDIR)/DeadMachineInstructionElim.Tpo -c -o DeadMachineInstructionElim.lo `test -f 'llvm/lib/CodeGen/DeadMachineInstructionElim.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/DeadMachineInstructionElim.cpp
- at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/DeadMachineInstructionElim.Tpo $(DEPDIR)/DeadMachineInstructionElim.Plo
- at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
- at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/CodeGen/DeadMachineInstructionElim.cpp' object='DeadMachineInstructionElim.lo' libtool=yes @AMDEPBACKSLASH@
- at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
- at am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o DeadMachineInstructionElim.lo `test -f 'llvm/lib/CodeGen/DeadMachineInstructionElim.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/DeadMachineInstructionElim.cpp
-
GCMetadataPrinter.lo: llvm/lib/CodeGen/GCMetadataPrinter.cpp
@am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT GCMetadataPrinter.lo -MD -MP -MF $(DEPDIR)/GCMetadataPrinter.Tpo -c -o GCMetadataPrinter.lo `test -f 'llvm/lib/CodeGen/GCMetadataPrinter.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/GCMetadataPrinter.cpp
@am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/GCMetadataPrinter.Tpo $(DEPDIR)/GCMetadataPrinter.Plo
@@ -3900,14 +3931,6 @@ TargetIntrinsicInfo.lo: llvm/lib/Target/TargetIntrinsicInfo.cpp
@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o TargetIntrinsicInfo.lo `test -f 'llvm/lib/Target/TargetIntrinsicInfo.cpp' || echo '$(srcdir)/'`llvm/lib/Target/TargetIntrinsicInfo.cpp
-TargetMachOWriterInfo.lo: llvm/lib/Target/TargetMachOWriterInfo.cpp
- at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT TargetMachOWriterInfo.lo -MD -MP -MF $(DEPDIR)/TargetMachOWriterInfo.Tpo -c -o TargetMachOWriterInfo.lo `test -f 'llvm/lib/Target/TargetMachOWriterInfo.cpp' || echo '$(srcdir)/'`llvm/lib/Target/TargetMachOWriterInfo.cpp
- at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/TargetMachOWriterInfo.Tpo $(DEPDIR)/TargetMachOWriterInfo.Plo
- at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
- at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/Target/TargetMachOWriterInfo.cpp' object='TargetMachOWriterInfo.lo' libtool=yes @AMDEPBACKSLASH@
- at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
- at am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o TargetMachOWriterInfo.lo `test -f 'llvm/lib/Target/TargetMachOWriterInfo.cpp' || echo '$(srcdir)/'`llvm/lib/Target/TargetMachOWriterInfo.cpp
-
AliasAnalysis.lo: llvm/lib/Analysis/AliasAnalysis.cpp
@am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT AliasAnalysis.lo -MD -MP -MF $(DEPDIR)/AliasAnalysis.Tpo -c -o AliasAnalysis.lo `test -f 'llvm/lib/Analysis/AliasAnalysis.cpp' || echo '$(srcdir)/'`llvm/lib/Analysis/AliasAnalysis.cpp
@am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/AliasAnalysis.Tpo $(DEPDIR)/AliasAnalysis.Plo
@@ -4540,6 +4563,14 @@ Function.lo: llvm/lib/VMCore/Function.cpp
@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o Function.lo `test -f 'llvm/lib/VMCore/Function.cpp' || echo '$(srcdir)/'`llvm/lib/VMCore/Function.cpp
+GVMaterializer.lo: llvm/lib/VMCore/GVMaterializer.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT GVMaterializer.lo -MD -MP -MF $(DEPDIR)/GVMaterializer.Tpo -c -o GVMaterializer.lo `test -f 'llvm/lib/VMCore/GVMaterializer.cpp' || echo '$(srcdir)/'`llvm/lib/VMCore/GVMaterializer.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/GVMaterializer.Tpo $(DEPDIR)/GVMaterializer.Plo
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/VMCore/GVMaterializer.cpp' object='GVMaterializer.lo' libtool=yes @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o GVMaterializer.lo `test -f 'llvm/lib/VMCore/GVMaterializer.cpp' || echo '$(srcdir)/'`llvm/lib/VMCore/GVMaterializer.cpp
+
Globals.lo: llvm/lib/VMCore/Globals.cpp
@am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT Globals.lo -MD -MP -MF $(DEPDIR)/Globals.Tpo -c -o Globals.lo `test -f 'llvm/lib/VMCore/Globals.cpp' || echo '$(srcdir)/'`llvm/lib/VMCore/Globals.cpp
@am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/Globals.Tpo $(DEPDIR)/Globals.Plo
@@ -4620,14 +4651,6 @@ Module.lo: llvm/lib/VMCore/Module.cpp
@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o Module.lo `test -f 'llvm/lib/VMCore/Module.cpp' || echo '$(srcdir)/'`llvm/lib/VMCore/Module.cpp
-ModuleProvider.lo: llvm/lib/VMCore/ModuleProvider.cpp
- at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT ModuleProvider.lo -MD -MP -MF $(DEPDIR)/ModuleProvider.Tpo -c -o ModuleProvider.lo `test -f 'llvm/lib/VMCore/ModuleProvider.cpp' || echo '$(srcdir)/'`llvm/lib/VMCore/ModuleProvider.cpp
- at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/ModuleProvider.Tpo $(DEPDIR)/ModuleProvider.Plo
- at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
- at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/VMCore/ModuleProvider.cpp' object='ModuleProvider.lo' libtool=yes @AMDEPBACKSLASH@
- at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
- at am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o ModuleProvider.lo `test -f 'llvm/lib/VMCore/ModuleProvider.cpp' || echo '$(srcdir)/'`llvm/lib/VMCore/ModuleProvider.cpp
-
Pass.lo: llvm/lib/VMCore/Pass.cpp
@am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT Pass.lo -MD -MP -MF $(DEPDIR)/Pass.Tpo -c -o Pass.lo `test -f 'llvm/lib/VMCore/Pass.cpp' || echo '$(srcdir)/'`llvm/lib/VMCore/Pass.cpp
@am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/Pass.Tpo $(DEPDIR)/Pass.Plo
@@ -5052,14 +5075,6 @@ TimeValue.lo: llvm/lib/System/TimeValue.cpp
@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o TimeValue.lo `test -f 'llvm/lib/System/TimeValue.cpp' || echo '$(srcdir)/'`llvm/lib/System/TimeValue.cpp
-libllvmx86codegen_la-DeadMachineInstructionElim.lo: llvm/lib/CodeGen/DeadMachineInstructionElim.cpp
- at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libllvmx86codegen_la_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT libllvmx86codegen_la-DeadMachineInstructionElim.lo -MD -MP -MF $(DEPDIR)/libllvmx86codegen_la-DeadMachineInstructionElim.Tpo -c -o libllvmx86codegen_la-DeadMachineInstructionElim.lo `test -f 'llvm/lib/CodeGen/DeadMachineInstructionElim.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/DeadMachineInstructionElim.cpp
- at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/libllvmx86codegen_la-DeadMachineInstructionElim.Tpo $(DEPDIR)/libllvmx86codegen_la-DeadMachineInstructionElim.Plo
- at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
- at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/CodeGen/DeadMachineInstructionElim.cpp' object='libllvmx86codegen_la-DeadMachineInstructionElim.lo' libtool=yes @AMDEPBACKSLASH@
- at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
- at am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libllvmx86codegen_la_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o libllvmx86codegen_la-DeadMachineInstructionElim.lo `test -f 'llvm/lib/CodeGen/DeadMachineInstructionElim.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/DeadMachineInstructionElim.cpp
-
libllvmx86codegen_la-MachineModuleInfoImpls.lo: llvm/lib/CodeGen/MachineModuleInfoImpls.cpp
@am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libllvmx86codegen_la_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT libllvmx86codegen_la-MachineModuleInfoImpls.lo -MD -MP -MF $(DEPDIR)/libllvmx86codegen_la-MachineModuleInfoImpls.Tpo -c -o libllvmx86codegen_la-MachineModuleInfoImpls.lo `test -f 'llvm/lib/CodeGen/MachineModuleInfoImpls.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/MachineModuleInfoImpls.cpp
@am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/libllvmx86codegen_la-MachineModuleInfoImpls.Tpo $(DEPDIR)/libllvmx86codegen_la-MachineModuleInfoImpls.Plo
@@ -5188,6 +5203,22 @@ libllvmx86codegen_la-X86MCAsmInfo.lo: llvm/lib/Target/X86/X86MCAsmInfo.cpp
@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libllvmx86codegen_la_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o libllvmx86codegen_la-X86MCAsmInfo.lo `test -f 'llvm/lib/Target/X86/X86MCAsmInfo.cpp' || echo '$(srcdir)/'`llvm/lib/Target/X86/X86MCAsmInfo.cpp
+libllvmx86codegen_la-X86MCCodeEmitter.lo: llvm/lib/Target/X86/X86MCCodeEmitter.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libllvmx86codegen_la_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT libllvmx86codegen_la-X86MCCodeEmitter.lo -MD -MP -MF $(DEPDIR)/libllvmx86codegen_la-X86MCCodeEmitter.Tpo -c -o libllvmx86codegen_la-X86MCCodeEmitter.lo `test -f 'llvm/lib/Target/X86/X86MCCodeEmitter.cpp' || echo '$(srcdir)/'`llvm/lib/Target/X86/X86MCCodeEmitter.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/libllvmx86codegen_la-X86MCCodeEmitter.Tpo $(DEPDIR)/libllvmx86codegen_la-X86MCCodeEmitter.Plo
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/Target/X86/X86MCCodeEmitter.cpp' object='libllvmx86codegen_la-X86MCCodeEmitter.lo' libtool=yes @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libllvmx86codegen_la_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o libllvmx86codegen_la-X86MCCodeEmitter.lo `test -f 'llvm/lib/Target/X86/X86MCCodeEmitter.cpp' || echo '$(srcdir)/'`llvm/lib/Target/X86/X86MCCodeEmitter.cpp
+
+libllvmx86codegen_la-X86MCTargetExpr.lo: llvm/lib/Target/X86/X86MCTargetExpr.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libllvmx86codegen_la_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT libllvmx86codegen_la-X86MCTargetExpr.lo -MD -MP -MF $(DEPDIR)/libllvmx86codegen_la-X86MCTargetExpr.Tpo -c -o libllvmx86codegen_la-X86MCTargetExpr.lo `test -f 'llvm/lib/Target/X86/X86MCTargetExpr.cpp' || echo '$(srcdir)/'`llvm/lib/Target/X86/X86MCTargetExpr.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/libllvmx86codegen_la-X86MCTargetExpr.Tpo $(DEPDIR)/libllvmx86codegen_la-X86MCTargetExpr.Plo
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/Target/X86/X86MCTargetExpr.cpp' object='libllvmx86codegen_la-X86MCTargetExpr.lo' libtool=yes @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libllvmx86codegen_la_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o libllvmx86codegen_la-X86MCTargetExpr.lo `test -f 'llvm/lib/Target/X86/X86MCTargetExpr.cpp' || echo '$(srcdir)/'`llvm/lib/Target/X86/X86MCTargetExpr.cpp
+
libllvmx86codegen_la-X86RegisterInfo.lo: llvm/lib/Target/X86/X86RegisterInfo.cpp
@am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libllvmx86codegen_la_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT libllvmx86codegen_la-X86RegisterInfo.lo -MD -MP -MF $(DEPDIR)/libllvmx86codegen_la-X86RegisterInfo.Tpo -c -o libllvmx86codegen_la-X86RegisterInfo.lo `test -f 'llvm/lib/Target/X86/X86RegisterInfo.cpp' || echo '$(srcdir)/'`llvm/lib/Target/X86/X86RegisterInfo.cpp
@am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/libllvmx86codegen_la-X86RegisterInfo.Tpo $(DEPDIR)/libllvmx86codegen_la-X86RegisterInfo.Plo
@@ -5860,6 +5891,22 @@ tblgen-AsmWriterEmitter.obj: llvm/utils/TableGen/AsmWriterEmitter.cpp
@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-AsmWriterEmitter.obj `if test -f 'llvm/utils/TableGen/AsmWriterEmitter.cpp'; then $(CYGPATH_W) 'llvm/utils/TableGen/AsmWriterEmitter.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/utils/TableGen/AsmWriterEmitter.cpp'; fi`
+tblgen-AsmWriterInst.o: llvm/utils/TableGen/AsmWriterInst.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-AsmWriterInst.o -MD -MP -MF $(DEPDIR)/tblgen-AsmWriterInst.Tpo -c -o tblgen-AsmWriterInst.o `test -f 'llvm/utils/TableGen/AsmWriterInst.cpp' || echo '$(srcdir)/'`llvm/utils/TableGen/AsmWriterInst.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-AsmWriterInst.Tpo $(DEPDIR)/tblgen-AsmWriterInst.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/utils/TableGen/AsmWriterInst.cpp' object='tblgen-AsmWriterInst.o' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-AsmWriterInst.o `test -f 'llvm/utils/TableGen/AsmWriterInst.cpp' || echo '$(srcdir)/'`llvm/utils/TableGen/AsmWriterInst.cpp
+
+tblgen-AsmWriterInst.obj: llvm/utils/TableGen/AsmWriterInst.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-AsmWriterInst.obj -MD -MP -MF $(DEPDIR)/tblgen-AsmWriterInst.Tpo -c -o tblgen-AsmWriterInst.obj `if test -f 'llvm/utils/TableGen/AsmWriterInst.cpp'; then $(CYGPATH_W) 'llvm/utils/TableGen/AsmWriterInst.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/utils/TableGen/AsmWriterInst.cpp'; fi`
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-AsmWriterInst.Tpo $(DEPDIR)/tblgen-AsmWriterInst.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/utils/TableGen/AsmWriterInst.cpp' object='tblgen-AsmWriterInst.obj' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-AsmWriterInst.obj `if test -f 'llvm/utils/TableGen/AsmWriterInst.cpp'; then $(CYGPATH_W) 'llvm/utils/TableGen/AsmWriterInst.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/utils/TableGen/AsmWriterInst.cpp'; fi`
+
tblgen-CallingConvEmitter.o: llvm/utils/TableGen/CallingConvEmitter.cpp
@am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-CallingConvEmitter.o -MD -MP -MF $(DEPDIR)/tblgen-CallingConvEmitter.Tpo -c -o tblgen-CallingConvEmitter.o `test -f 'llvm/utils/TableGen/CallingConvEmitter.cpp' || echo '$(srcdir)/'`llvm/utils/TableGen/CallingConvEmitter.cpp
@am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-CallingConvEmitter.Tpo $(DEPDIR)/tblgen-CallingConvEmitter.Po
@@ -5956,6 +6003,70 @@ tblgen-CodeGenTarget.obj: llvm/utils/TableGen/CodeGenTarget.cpp
@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-CodeGenTarget.obj `if test -f 'llvm/utils/TableGen/CodeGenTarget.cpp'; then $(CYGPATH_W) 'llvm/utils/TableGen/CodeGenTarget.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/utils/TableGen/CodeGenTarget.cpp'; fi`
+tblgen-DAGISelEmitter.o: llvm/utils/TableGen/DAGISelEmitter.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-DAGISelEmitter.o -MD -MP -MF $(DEPDIR)/tblgen-DAGISelEmitter.Tpo -c -o tblgen-DAGISelEmitter.o `test -f 'llvm/utils/TableGen/DAGISelEmitter.cpp' || echo '$(srcdir)/'`llvm/utils/TableGen/DAGISelEmitter.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-DAGISelEmitter.Tpo $(DEPDIR)/tblgen-DAGISelEmitter.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/utils/TableGen/DAGISelEmitter.cpp' object='tblgen-DAGISelEmitter.o' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-DAGISelEmitter.o `test -f 'llvm/utils/TableGen/DAGISelEmitter.cpp' || echo '$(srcdir)/'`llvm/utils/TableGen/DAGISelEmitter.cpp
+
+tblgen-DAGISelEmitter.obj: llvm/utils/TableGen/DAGISelEmitter.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-DAGISelEmitter.obj -MD -MP -MF $(DEPDIR)/tblgen-DAGISelEmitter.Tpo -c -o tblgen-DAGISelEmitter.obj `if test -f 'llvm/utils/TableGen/DAGISelEmitter.cpp'; then $(CYGPATH_W) 'llvm/utils/TableGen/DAGISelEmitter.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/utils/TableGen/DAGISelEmitter.cpp'; fi`
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-DAGISelEmitter.Tpo $(DEPDIR)/tblgen-DAGISelEmitter.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/utils/TableGen/DAGISelEmitter.cpp' object='tblgen-DAGISelEmitter.obj' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-DAGISelEmitter.obj `if test -f 'llvm/utils/TableGen/DAGISelEmitter.cpp'; then $(CYGPATH_W) 'llvm/utils/TableGen/DAGISelEmitter.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/utils/TableGen/DAGISelEmitter.cpp'; fi`
+
+tblgen-DAGISelMatcher.o: llvm/utils/TableGen/DAGISelMatcher.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-DAGISelMatcher.o -MD -MP -MF $(DEPDIR)/tblgen-DAGISelMatcher.Tpo -c -o tblgen-DAGISelMatcher.o `test -f 'llvm/utils/TableGen/DAGISelMatcher.cpp' || echo '$(srcdir)/'`llvm/utils/TableGen/DAGISelMatcher.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-DAGISelMatcher.Tpo $(DEPDIR)/tblgen-DAGISelMatcher.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/utils/TableGen/DAGISelMatcher.cpp' object='tblgen-DAGISelMatcher.o' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-DAGISelMatcher.o `test -f 'llvm/utils/TableGen/DAGISelMatcher.cpp' || echo '$(srcdir)/'`llvm/utils/TableGen/DAGISelMatcher.cpp
+
+tblgen-DAGISelMatcher.obj: llvm/utils/TableGen/DAGISelMatcher.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-DAGISelMatcher.obj -MD -MP -MF $(DEPDIR)/tblgen-DAGISelMatcher.Tpo -c -o tblgen-DAGISelMatcher.obj `if test -f 'llvm/utils/TableGen/DAGISelMatcher.cpp'; then $(CYGPATH_W) 'llvm/utils/TableGen/DAGISelMatcher.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/utils/TableGen/DAGISelMatcher.cpp'; fi`
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-DAGISelMatcher.Tpo $(DEPDIR)/tblgen-DAGISelMatcher.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/utils/TableGen/DAGISelMatcher.cpp' object='tblgen-DAGISelMatcher.obj' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-DAGISelMatcher.obj `if test -f 'llvm/utils/TableGen/DAGISelMatcher.cpp'; then $(CYGPATH_W) 'llvm/utils/TableGen/DAGISelMatcher.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/utils/TableGen/DAGISelMatcher.cpp'; fi`
+
+tblgen-DAGISelMatcherEmitter.o: llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-DAGISelMatcherEmitter.o -MD -MP -MF $(DEPDIR)/tblgen-DAGISelMatcherEmitter.Tpo -c -o tblgen-DAGISelMatcherEmitter.o `test -f 'llvm/utils/TableGen/DAGISelMatcherEmitter.cpp' || echo '$(srcdir)/'`llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-DAGISelMatcherEmitter.Tpo $(DEPDIR)/tblgen-DAGISelMatcherEmitter.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/utils/TableGen/DAGISelMatcherEmitter.cpp' object='tblgen-DAGISelMatcherEmitter.o' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-DAGISelMatcherEmitter.o `test -f 'llvm/utils/TableGen/DAGISelMatcherEmitter.cpp' || echo '$(srcdir)/'`llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
+
+tblgen-DAGISelMatcherEmitter.obj: llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-DAGISelMatcherEmitter.obj -MD -MP -MF $(DEPDIR)/tblgen-DAGISelMatcherEmitter.Tpo -c -o tblgen-DAGISelMatcherEmitter.obj `if test -f 'llvm/utils/TableGen/DAGISelMatcherEmitter.cpp'; then $(CYGPATH_W) 'llvm/utils/TableGen/DAGISelMatcherEmitter.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp'; fi`
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-DAGISelMatcherEmitter.Tpo $(DEPDIR)/tblgen-DAGISelMatcherEmitter.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/utils/TableGen/DAGISelMatcherEmitter.cpp' object='tblgen-DAGISelMatcherEmitter.obj' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-DAGISelMatcherEmitter.obj `if test -f 'llvm/utils/TableGen/DAGISelMatcherEmitter.cpp'; then $(CYGPATH_W) 'llvm/utils/TableGen/DAGISelMatcherEmitter.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp'; fi`
+
+tblgen-DAGISelMatcherGen.o: llvm/utils/TableGen/DAGISelMatcherGen.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-DAGISelMatcherGen.o -MD -MP -MF $(DEPDIR)/tblgen-DAGISelMatcherGen.Tpo -c -o tblgen-DAGISelMatcherGen.o `test -f 'llvm/utils/TableGen/DAGISelMatcherGen.cpp' || echo '$(srcdir)/'`llvm/utils/TableGen/DAGISelMatcherGen.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-DAGISelMatcherGen.Tpo $(DEPDIR)/tblgen-DAGISelMatcherGen.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/utils/TableGen/DAGISelMatcherGen.cpp' object='tblgen-DAGISelMatcherGen.o' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-DAGISelMatcherGen.o `test -f 'llvm/utils/TableGen/DAGISelMatcherGen.cpp' || echo '$(srcdir)/'`llvm/utils/TableGen/DAGISelMatcherGen.cpp
+
+tblgen-DAGISelMatcherGen.obj: llvm/utils/TableGen/DAGISelMatcherGen.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-DAGISelMatcherGen.obj -MD -MP -MF $(DEPDIR)/tblgen-DAGISelMatcherGen.Tpo -c -o tblgen-DAGISelMatcherGen.obj `if test -f 'llvm/utils/TableGen/DAGISelMatcherGen.cpp'; then $(CYGPATH_W) 'llvm/utils/TableGen/DAGISelMatcherGen.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/utils/TableGen/DAGISelMatcherGen.cpp'; fi`
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-DAGISelMatcherGen.Tpo $(DEPDIR)/tblgen-DAGISelMatcherGen.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/utils/TableGen/DAGISelMatcherGen.cpp' object='tblgen-DAGISelMatcherGen.obj' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-DAGISelMatcherGen.obj `if test -f 'llvm/utils/TableGen/DAGISelMatcherGen.cpp'; then $(CYGPATH_W) 'llvm/utils/TableGen/DAGISelMatcherGen.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/utils/TableGen/DAGISelMatcherGen.cpp'; fi`
+
tblgen-DisassemblerEmitter.o: llvm/utils/TableGen/DisassemblerEmitter.cpp
@am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-DisassemblerEmitter.o -MD -MP -MF $(DEPDIR)/tblgen-DisassemblerEmitter.Tpo -c -o tblgen-DisassemblerEmitter.o `test -f 'llvm/utils/TableGen/DisassemblerEmitter.cpp' || echo '$(srcdir)/'`llvm/utils/TableGen/DisassemblerEmitter.cpp
@am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-DisassemblerEmitter.Tpo $(DEPDIR)/tblgen-DisassemblerEmitter.Po
@@ -5972,21 +6083,21 @@ tblgen-DisassemblerEmitter.obj: llvm/utils/TableGen/DisassemblerEmitter.cpp
@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-DisassemblerEmitter.obj `if test -f 'llvm/utils/TableGen/DisassemblerEmitter.cpp'; then $(CYGPATH_W) 'llvm/utils/TableGen/DisassemblerEmitter.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/utils/TableGen/DisassemblerEmitter.cpp'; fi`
-tblgen-DAGISelEmitter.o: llvm/utils/TableGen/DAGISelEmitter.cpp
- at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-DAGISelEmitter.o -MD -MP -MF $(DEPDIR)/tblgen-DAGISelEmitter.Tpo -c -o tblgen-DAGISelEmitter.o `test -f 'llvm/utils/TableGen/DAGISelEmitter.cpp' || echo '$(srcdir)/'`llvm/utils/TableGen/DAGISelEmitter.cpp
- at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-DAGISelEmitter.Tpo $(DEPDIR)/tblgen-DAGISelEmitter.Po
+tblgen-EDEmitter.o: llvm/utils/TableGen/EDEmitter.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-EDEmitter.o -MD -MP -MF $(DEPDIR)/tblgen-EDEmitter.Tpo -c -o tblgen-EDEmitter.o `test -f 'llvm/utils/TableGen/EDEmitter.cpp' || echo '$(srcdir)/'`llvm/utils/TableGen/EDEmitter.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-EDEmitter.Tpo $(DEPDIR)/tblgen-EDEmitter.Po
@am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
- at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/utils/TableGen/DAGISelEmitter.cpp' object='tblgen-DAGISelEmitter.o' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/utils/TableGen/EDEmitter.cpp' object='tblgen-EDEmitter.o' libtool=no @AMDEPBACKSLASH@
@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
- at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-DAGISelEmitter.o `test -f 'llvm/utils/TableGen/DAGISelEmitter.cpp' || echo '$(srcdir)/'`llvm/utils/TableGen/DAGISelEmitter.cpp
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-EDEmitter.o `test -f 'llvm/utils/TableGen/EDEmitter.cpp' || echo '$(srcdir)/'`llvm/utils/TableGen/EDEmitter.cpp
-tblgen-DAGISelEmitter.obj: llvm/utils/TableGen/DAGISelEmitter.cpp
- at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-DAGISelEmitter.obj -MD -MP -MF $(DEPDIR)/tblgen-DAGISelEmitter.Tpo -c -o tblgen-DAGISelEmitter.obj `if test -f 'llvm/utils/TableGen/DAGISelEmitter.cpp'; then $(CYGPATH_W) 'llvm/utils/TableGen/DAGISelEmitter.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/utils/TableGen/DAGISelEmitter.cpp'; fi`
- at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-DAGISelEmitter.Tpo $(DEPDIR)/tblgen-DAGISelEmitter.Po
+tblgen-EDEmitter.obj: llvm/utils/TableGen/EDEmitter.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-EDEmitter.obj -MD -MP -MF $(DEPDIR)/tblgen-EDEmitter.Tpo -c -o tblgen-EDEmitter.obj `if test -f 'llvm/utils/TableGen/EDEmitter.cpp'; then $(CYGPATH_W) 'llvm/utils/TableGen/EDEmitter.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/utils/TableGen/EDEmitter.cpp'; fi`
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-EDEmitter.Tpo $(DEPDIR)/tblgen-EDEmitter.Po
@am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
- at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/utils/TableGen/DAGISelEmitter.cpp' object='tblgen-DAGISelEmitter.obj' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/utils/TableGen/EDEmitter.cpp' object='tblgen-EDEmitter.obj' libtool=no @AMDEPBACKSLASH@
@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
- at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-DAGISelEmitter.obj `if test -f 'llvm/utils/TableGen/DAGISelEmitter.cpp'; then $(CYGPATH_W) 'llvm/utils/TableGen/DAGISelEmitter.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/utils/TableGen/DAGISelEmitter.cpp'; fi`
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-EDEmitter.obj `if test -f 'llvm/utils/TableGen/EDEmitter.cpp'; then $(CYGPATH_W) 'llvm/utils/TableGen/EDEmitter.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/utils/TableGen/EDEmitter.cpp'; fi`
tblgen-FastISelEmitter.o: llvm/utils/TableGen/FastISelEmitter.cpp
@am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-FastISelEmitter.o -MD -MP -MF $(DEPDIR)/tblgen-FastISelEmitter.Tpo -c -o tblgen-FastISelEmitter.o `test -f 'llvm/utils/TableGen/FastISelEmitter.cpp' || echo '$(srcdir)/'`llvm/utils/TableGen/FastISelEmitter.cpp
diff --git a/libclamav/c++/PPCGenAsmWriter.inc b/libclamav/c++/PPCGenAsmWriter.inc
index 6cc8ccf..142ebe1 100644
--- a/libclamav/c++/PPCGenAsmWriter.inc
+++ b/libclamav/c++/PPCGenAsmWriter.inc
@@ -21,523 +21,523 @@ void PPCAsmPrinter::printInstruction(const MachineInstr *MI) {
0U, // IMPLICIT_DEF
0U, // SUBREG_TO_REG
0U, // COPY_TO_REGCLASS
- 1U, // DEBUG_VALUE
- 268435469U, // ADD4
- 268435469U, // ADD8
- 268435474U, // ADDC
- 268435474U, // ADDC8
- 268435480U, // ADDE
- 268435480U, // ADDE8
- 268439582U, // ADDI
- 268439582U, // ADDI8
- 268439588U, // ADDIC
- 268439588U, // ADDIC8
- 268439595U, // ADDICo
- 268443699U, // ADDIS
- 268443699U, // ADDIS8
- 268468282U, // ADDME
- 268468282U, // ADDME8
- 268468289U, // ADDZE
- 268468289U, // ADDZE8
- 541065288U, // ADJCALLSTACKDOWN
- 545259592U, // ADJCALLSTACKUP
- 268435529U, // AND
- 268435529U, // AND8
- 268435534U, // ANDC
- 268435534U, // ANDC8
- 268447828U, // ANDISo
- 268447828U, // ANDISo8
- 268447836U, // ANDIo
- 268447836U, // ANDIo8
- 549453896U, // ATOMIC_CMP_SWAP_I16
- 553648200U, // ATOMIC_CMP_SWAP_I32
- 557842504U, // ATOMIC_CMP_SWAP_I64
- 562036808U, // ATOMIC_CMP_SWAP_I8
- 566231112U, // ATOMIC_LOAD_ADD_I16
- 570425416U, // ATOMIC_LOAD_ADD_I32
- 574619720U, // ATOMIC_LOAD_ADD_I64
- 578814024U, // ATOMIC_LOAD_ADD_I8
- 583008328U, // ATOMIC_LOAD_AND_I16
- 587202632U, // ATOMIC_LOAD_AND_I32
- 591396936U, // ATOMIC_LOAD_AND_I64
- 595591240U, // ATOMIC_LOAD_AND_I8
- 599785544U, // ATOMIC_LOAD_NAND_I16
- 603979848U, // ATOMIC_LOAD_NAND_I32
- 608174152U, // ATOMIC_LOAD_NAND_I64
- 612368456U, // ATOMIC_LOAD_NAND_I8
- 616562760U, // ATOMIC_LOAD_OR_I16
- 620757064U, // ATOMIC_LOAD_OR_I32
- 624951368U, // ATOMIC_LOAD_OR_I64
- 629145672U, // ATOMIC_LOAD_OR_I8
- 633339976U, // ATOMIC_LOAD_SUB_I16
- 637534280U, // ATOMIC_LOAD_SUB_I32
- 641728584U, // ATOMIC_LOAD_SUB_I64
- 645922888U, // ATOMIC_LOAD_SUB_I8
- 650117192U, // ATOMIC_LOAD_XOR_I16
- 654311496U, // ATOMIC_LOAD_XOR_I32
- 658505800U, // ATOMIC_LOAD_XOR_I64
- 662700104U, // ATOMIC_LOAD_XOR_I8
- 666894408U, // ATOMIC_SWAP_I16
- 671088712U, // ATOMIC_SWAP_I32
- 675283016U, // ATOMIC_SWAP_I64
- 679477320U, // ATOMIC_SWAP_I8
- 805306467U, // B
- 1220804710U, // BCC
- 104U, // BCTR
- 109U, // BCTRL8_Darwin
- 109U, // BCTRL8_ELF
- 109U, // BCTRL_Darwin
- 109U, // BCTRL_SVR4
- 1493172339U, // BL8_Darwin
- 1493172339U, // BL8_ELF
- 1761607799U, // BLA8_Darwin
- 1761607799U, // BLA8_ELF
- 1761607799U, // BLA_Darwin
- 1761607799U, // BLA_SVR4
- 1228931174U, // BLR
- 1493172339U, // BL_Darwin
- 1493172339U, // BL_SVR4
- 268435580U, // CMPD
- 268439682U, // CMPDI
- 268435593U, // CMPLD
- 268447888U, // CMPLDI
- 268435608U, // CMPLW
- 268447903U, // CMPLWI
- 268435623U, // CMPW
- 268439725U, // CMPWI
- 268468404U, // CNTLZD
- 268468412U, // CNTLZW
- 268435652U, // CREQV
- 268435659U, // CROR
- 268959940U, // CRSET
- 1879048401U, // DCBA
- 1879048407U, // DCBF
- 1879048413U, // DCBI
- 1879048419U, // DCBST
- 1879048426U, // DCBT
- 1879048432U, // DCBTST
- 1879048440U, // DCBZ
- 1879048446U, // DCBZL
- 268435717U, // DIVD
- 268435723U, // DIVDU
- 268435730U, // DIVW
- 268435736U, // DIVWU
- 2147483935U, // DSS
- 292U, // DSSALL
- 2415919403U, // DST
- 2415919403U, // DST64
- 2415919408U, // DSTST
- 2415919408U, // DSTST64
- 2415919415U, // DSTSTT
- 2415919415U, // DSTSTT64
- 2415919423U, // DSTT
- 2415919423U, // DSTT64
- 696254536U, // DYNALLOC
- 700448840U, // DYNALLOC8
- 268435781U, // EQV
- 268435781U, // EQV8
- 268468554U, // EXTSB
- 268468554U, // EXTSB8
- 268468561U, // EXTSH
- 268468561U, // EXTSH8
- 268468568U, // EXTSW
- 268468568U, // EXTSW_32
- 268468568U, // EXTSW_32_64
- 268468575U, // FABSD
- 268468575U, // FABSS
- 268435813U, // FADD
- 268435819U, // FADDS
- 268435813U, // FADDrtz
- 268468594U, // FCFID
- 268435833U, // FCMPUD
- 268435833U, // FCMPUS
- 268468608U, // FCTIDZ
- 268468616U, // FCTIWZ
- 268435856U, // FDIV
- 268435862U, // FDIVS
- 268435869U, // FMADD
- 268435876U, // FMADDS
- 268468652U, // FMRD
- 268468652U, // FMRS
- 268468652U, // FMRSD
- 268435889U, // FMSUB
- 268435896U, // FMSUBS
- 268435904U, // FMUL
- 268435910U, // FMULS
- 268468685U, // FNABSD
- 268468685U, // FNABSS
- 268468692U, // FNEGD
- 268468692U, // FNEGS
- 268435930U, // FNMADD
- 268435938U, // FNMADDS
- 268435947U, // FNMSUB
- 268435955U, // FNMSUBS
- 268468732U, // FRSP
- 268435970U, // FSELD
- 268435970U, // FSELS
- 268468744U, // FSQRT
- 268468751U, // FSQRTS
- 268435991U, // FSUB
- 268435997U, // FSUBS
- 269287972U, // LA
- 269484584U, // LBZ
- 269484584U, // LBZ8
- 269746733U, // LBZU
- 269746733U, // LBZU8
- 270008883U, // LBZX
- 270008883U, // LBZX8
- 270271033U, // LD
- 270008893U, // LDARX
- 270533188U, // LDU
- 270008905U, // LDX
- 436208206U, // LDinto_toc
- 270795321U, // LDtoc
- 599U, // LDtoc_restore
- 269484643U, // LFD
- 269746787U, // LFDU
- 270008936U, // LFDX
- 269484654U, // LFS
- 269746798U, // LFSU
- 270008947U, // LFSX
- 269484665U, // LHA
- 269484665U, // LHA8
- 269746814U, // LHAU
- 269320830U, // LHAU8
- 270008964U, // LHAX
- 270008964U, // LHAX8
- 270008970U, // LHBRX
- 269484689U, // LHZ
- 269484689U, // LHZ8
- 269746838U, // LHZU
- 269746838U, // LHZU8
- 270008988U, // LHZX
- 270008988U, // LHZX8
- 271057570U, // LI
- 271057570U, // LI8
- 271319718U, // LIS
- 271319718U, // LIS8
- 270009003U, // LVEBX
- 270009010U, // LVEHX
- 270009017U, // LVEWX
- 270009024U, // LVSL
- 270009030U, // LVSR
- 270009036U, // LVX
- 270009041U, // LVXL
- 270271191U, // LWA
- 270009052U, // LWARX
- 270009059U, // LWAX
- 270009065U, // LWBRX
- 269484784U, // LWZ
- 269484784U, // LWZ8
- 269746933U, // LWZU
- 269746933U, // LWZU8
- 270009083U, // LWZX
- 270009083U, // LWZX8
- 268468993U, // MCRF
- 419431175U, // MFCR
- 419431181U, // MFCTR
- 419431181U, // MFCTR8
- 419431188U, // MFFS
- 419431194U, // MFLR
- 419431194U, // MFLR8
- 271581959U, // MFOCRF
- 440402720U, // MFVRSAVE
- 419431207U, // MFVSCR
- 2684355375U, // MTCRF
- 419431222U, // MTCTR
- 419431222U, // MTCTR8
- 2952790845U, // MTFSB0
- 2952790853U, // MTFSB1
- 3397387085U, // MTFSF
- 419431252U, // MTLR
- 419431252U, // MTLR8
- 419431258U, // MTVRSAVE
- 419431270U, // MTVSCR
- 268436334U, // MULHD
- 268436341U, // MULHDU
- 268436349U, // MULHW
- 268436356U, // MULHWU
- 268436364U, // MULLD
- 268440467U, // MULLI
- 268436378U, // MULLW
- 3489661043U, // MovePCtoLR
- 3489661043U, // MovePCtoLR8
- 268436385U, // NAND
- 268436385U, // NAND8
- 268469159U, // NEG
- 268469159U, // NEG8
- 940U, // NOP
- 268436400U, // NOR
- 268436400U, // NOR8
- 268436405U, // OR
- 268436405U, // OR4To8
- 268436405U, // OR8
- 268436405U, // OR8To4
- 268436409U, // ORC
- 268436409U, // ORC8
- 268448702U, // ORI
- 268448702U, // ORI8
- 268448707U, // ORIS
- 268448707U, // ORIS8
- 268436425U, // RLDCL
- 268452816U, // RLDICL
- 268452824U, // RLDICR
- 271975392U, // RLDIMI
- 272008168U, // RLWIMI
- 268456944U, // RLWINM
- 268456952U, // RLWINMo
- 268436481U, // RLWNM
- 717226056U, // SELECT_CC_F4
- 717226056U, // SELECT_CC_F8
- 717226056U, // SELECT_CC_I4
- 717226056U, // SELECT_CC_I8
- 717226056U, // SELECT_CC_VRRC
- 268436488U, // SLD
- 268436493U, // SLW
- 721420360U, // SPILL_CR
- 268436498U, // SRAD
- 268452888U, // SRADI
- 268436511U, // SRAW
- 268456997U, // SRAWI
- 268436524U, // SRD
- 268436529U, // SRW
- 269485110U, // STB
- 269485110U, // STB8
- 3409970235U, // STBU
- 3409970235U, // STBU8
- 270009409U, // STBX
- 270009409U, // STBX8
- 270271559U, // STD
- 270009420U, // STDCX
- 3414164564U, // STDU
- 270009434U, // STDUX
- 270009441U, // STDX
- 270009441U, // STDX_32
- 270271559U, // STD_32
- 269485159U, // STFD
- 3409970285U, // STFDU
- 270009460U, // STFDX
- 270009467U, // STFIWX
- 269485187U, // STFS
- 3409970313U, // STFSU
- 270009488U, // STFSX
- 269485207U, // STH
- 269485207U, // STH8
- 270009500U, // STHBRX
- 3409970340U, // STHU
- 3409970340U, // STHU8
- 270009514U, // STHX
- 270009514U, // STHX8
- 270009520U, // STVEBX
- 270009528U, // STVEHX
- 270009536U, // STVEWX
- 270009544U, // STVX
- 270009550U, // STVXL
- 269485269U, // STW
- 269485269U, // STW8
- 270009562U, // STWBRX
- 270009570U, // STWCX
- 3409970410U, // STWU
- 3409970410U, // STWU8
- 268436720U, // STWUX
- 270009591U, // STWX
- 270009591U, // STWX8
- 268436733U, // SUBF
- 268436733U, // SUBF8
- 268436739U, // SUBFC
- 268436739U, // SUBFC8
- 268436746U, // SUBFE
- 268436746U, // SUBFE8
- 268440849U, // SUBFIC
- 268440849U, // SUBFIC8
- 268469529U, // SUBFME
- 268469529U, // SUBFME8
- 268469537U, // SUBFZE
- 268469537U, // SUBFZE8
- 1321U, // SYNC
- 1493172323U, // TAILB
- 1493172323U, // TAILB8
- 1761609006U, // TAILBA
- 1761609006U, // TAILBA8
- 104U, // TAILBCTR
- 104U, // TAILBCTR8
- 1757447474U, // TCRETURNai
- 1757447487U, // TCRETURNai8
- 1489012045U, // TCRETURNdi
- 1489012058U, // TCRETURNdi8
- 415270248U, // TCRETURNri
- 415270261U, // TCRETURNri8
- 1411U, // TRAP
- 268469640U, // UPDATE_VRSAVE
- 268436887U, // VADDCUW
- 268436896U, // VADDFP
- 268436904U, // VADDSBS
- 268436913U, // VADDSHS
- 268436922U, // VADDSWS
- 268436931U, // VADDUBM
- 268436940U, // VADDUBS
- 268436949U, // VADDUHM
- 268436958U, // VADDUHS
- 268436967U, // VADDUWM
- 268436976U, // VADDUWS
- 268436985U, // VAND
- 268436991U, // VANDC
- 268436998U, // VAVGSB
- 268437006U, // VAVGSH
- 268437014U, // VAVGSW
- 268437022U, // VAVGUB
- 268437030U, // VAVGUH
- 268437038U, // VAVGUW
- 272041526U, // VCFSX
- 272041533U, // VCFUX
- 268437060U, // VCMPBFP
- 268437069U, // VCMPBFPo
- 268437079U, // VCMPEQFP
- 268437089U, // VCMPEQFPo
- 268437100U, // VCMPEQUB
- 268437110U, // VCMPEQUBo
- 268437121U, // VCMPEQUH
- 268437131U, // VCMPEQUHo
- 268437142U, // VCMPEQUW
- 268437152U, // VCMPEQUWo
- 268437163U, // VCMPGEFP
- 268437173U, // VCMPGEFPo
- 268437184U, // VCMPGTFP
- 268437194U, // VCMPGTFPo
- 268437205U, // VCMPGTSB
- 268437215U, // VCMPGTSBo
- 268437226U, // VCMPGTSH
- 268437236U, // VCMPGTSHo
- 268437247U, // VCMPGTSW
- 268437257U, // VCMPGTSWo
- 268437268U, // VCMPGTUB
- 268437278U, // VCMPGTUBo
- 268437289U, // VCMPGTUH
- 268437299U, // VCMPGTUHo
- 268437310U, // VCMPGTUW
- 268437320U, // VCMPGTUWo
- 272041811U, // VCTSXS
- 272041819U, // VCTUXS
- 268470115U, // VEXPTEFP
- 268470125U, // VLOGEFP
- 268437366U, // VMADDFP
- 268437375U, // VMAXFP
- 268437383U, // VMAXSB
- 268437391U, // VMAXSH
- 268437399U, // VMAXSW
- 268437407U, // VMAXUB
- 268437415U, // VMAXUH
- 268437423U, // VMAXUW
- 268437431U, // VMHADDSHS
- 268437442U, // VMHRADDSHS
- 268437454U, // VMINFP
- 268437462U, // VMINSB
- 268437470U, // VMINSH
- 268437478U, // VMINSW
- 268437486U, // VMINUB
- 268437494U, // VMINUH
- 268437502U, // VMINUW
- 268437510U, // VMLADDUHM
- 268437521U, // VMRGHB
- 268437529U, // VMRGHH
- 268437537U, // VMRGHW
- 268437545U, // VMRGLB
- 268437553U, // VMRGLH
- 268437561U, // VMRGLW
- 268437569U, // VMSUMMBM
- 268437579U, // VMSUMSHM
- 268437589U, // VMSUMSHS
- 268437599U, // VMSUMUBM
- 268437609U, // VMSUMUHM
- 268437619U, // VMSUMUHS
- 268437629U, // VMULESB
- 268437638U, // VMULESH
- 268437647U, // VMULEUB
- 268437656U, // VMULEUH
- 268437665U, // VMULOSB
- 268437674U, // VMULOSH
- 268437683U, // VMULOUB
- 268437692U, // VMULOUH
- 268437701U, // VNMSUBFP
- 268437711U, // VNOR
- 268437717U, // VOR
- 268437722U, // VPERM
- 268437729U, // VPKPX
- 268437736U, // VPKSHSS
- 268437745U, // VPKSHUS
- 268437754U, // VPKSWSS
- 268437763U, // VPKSWUS
- 268437772U, // VPKUHUM
- 268437781U, // VPKUHUS
- 268437790U, // VPKUWUM
- 268437799U, // VPKUWUS
- 268470576U, // VREFP
- 268470583U, // VRFIM
- 268470590U, // VRFIN
- 268470597U, // VRFIP
- 268470604U, // VRFIZ
- 268437843U, // VRLB
- 268437849U, // VRLH
- 268437855U, // VRLW
- 268470629U, // VRSQRTEFP
- 268437872U, // VSEL
- 268437878U, // VSL
- 268437883U, // VSLB
- 268437889U, // VSLDOI
- 268437897U, // VSLH
- 268437903U, // VSLO
- 268437909U, // VSLW
- 272042395U, // VSPLTB
- 272042403U, // VSPLTH
- 272107947U, // VSPLTISB
- 272107957U, // VSPLTISH
- 272107967U, // VSPLTISW
- 272042441U, // VSPLTW
- 268437969U, // VSR
- 268437974U, // VSRAB
- 268437981U, // VSRAH
- 268437988U, // VSRAW
- 268437995U, // VSRB
- 268438001U, // VSRH
- 268438007U, // VSRO
- 268438013U, // VSRW
- 268438019U, // VSUBCUW
- 268438028U, // VSUBFP
- 268438036U, // VSUBSBS
- 268438045U, // VSUBSHS
- 268438054U, // VSUBSWS
- 268438063U, // VSUBUBM
- 268438072U, // VSUBUBS
- 268438081U, // VSUBUHM
- 268438090U, // VSUBUHS
- 268438099U, // VSUBUWM
- 268438108U, // VSUBUWS
- 268438117U, // VSUM2SWS
- 268438127U, // VSUM4SBS
- 268438137U, // VSUM4SHS
- 268438147U, // VSUM4UBS
- 268438157U, // VSUMSWS
- 268470934U, // VUPKHPX
- 268470943U, // VUPKHSB
- 268470952U, // VUPKHSH
- 268470961U, // VUPKLPX
- 268470970U, // VUPKLSB
- 268470979U, // VUPKLSH
- 268438220U, // VXOR
- 268962508U, // V_SET0
- 268438226U, // XOR
- 268438226U, // XOR8
- 268450519U, // XORI
- 268450519U, // XORI8
- 268450525U, // XORIS
- 268450525U, // XORIS8
+ 1U, // DBG_VALUE
+ 268435467U, // ADD4
+ 268435467U, // ADD8
+ 268435472U, // ADDC
+ 268435472U, // ADDC8
+ 268435478U, // ADDE
+ 268435478U, // ADDE8
+ 268439580U, // ADDI
+ 268439580U, // ADDI8
+ 268439586U, // ADDIC
+ 268439586U, // ADDIC8
+ 268439593U, // ADDICo
+ 268443697U, // ADDIS
+ 268443697U, // ADDIS8
+ 268468280U, // ADDME
+ 268468280U, // ADDME8
+ 268468287U, // ADDZE
+ 268468287U, // ADDZE8
+ 541065286U, // ADJCALLSTACKDOWN
+ 545259590U, // ADJCALLSTACKUP
+ 268435527U, // AND
+ 268435527U, // AND8
+ 268435532U, // ANDC
+ 268435532U, // ANDC8
+ 268447826U, // ANDISo
+ 268447826U, // ANDISo8
+ 268447834U, // ANDIo
+ 268447834U, // ANDIo8
+ 549453894U, // ATOMIC_CMP_SWAP_I16
+ 553648198U, // ATOMIC_CMP_SWAP_I32
+ 557842502U, // ATOMIC_CMP_SWAP_I64
+ 562036806U, // ATOMIC_CMP_SWAP_I8
+ 566231110U, // ATOMIC_LOAD_ADD_I16
+ 570425414U, // ATOMIC_LOAD_ADD_I32
+ 574619718U, // ATOMIC_LOAD_ADD_I64
+ 578814022U, // ATOMIC_LOAD_ADD_I8
+ 583008326U, // ATOMIC_LOAD_AND_I16
+ 587202630U, // ATOMIC_LOAD_AND_I32
+ 591396934U, // ATOMIC_LOAD_AND_I64
+ 595591238U, // ATOMIC_LOAD_AND_I8
+ 599785542U, // ATOMIC_LOAD_NAND_I16
+ 603979846U, // ATOMIC_LOAD_NAND_I32
+ 608174150U, // ATOMIC_LOAD_NAND_I64
+ 612368454U, // ATOMIC_LOAD_NAND_I8
+ 616562758U, // ATOMIC_LOAD_OR_I16
+ 620757062U, // ATOMIC_LOAD_OR_I32
+ 624951366U, // ATOMIC_LOAD_OR_I64
+ 629145670U, // ATOMIC_LOAD_OR_I8
+ 633339974U, // ATOMIC_LOAD_SUB_I16
+ 637534278U, // ATOMIC_LOAD_SUB_I32
+ 641728582U, // ATOMIC_LOAD_SUB_I64
+ 645922886U, // ATOMIC_LOAD_SUB_I8
+ 650117190U, // ATOMIC_LOAD_XOR_I16
+ 654311494U, // ATOMIC_LOAD_XOR_I32
+ 658505798U, // ATOMIC_LOAD_XOR_I64
+ 662700102U, // ATOMIC_LOAD_XOR_I8
+ 666894406U, // ATOMIC_SWAP_I16
+ 671088710U, // ATOMIC_SWAP_I32
+ 675283014U, // ATOMIC_SWAP_I64
+ 679477318U, // ATOMIC_SWAP_I8
+ 805306465U, // B
+ 1220804708U, // BCC
+ 102U, // BCTR
+ 107U, // BCTRL8_Darwin
+ 107U, // BCTRL8_ELF
+ 107U, // BCTRL_Darwin
+ 107U, // BCTRL_SVR4
+ 1493172337U, // BL8_Darwin
+ 1493172337U, // BL8_ELF
+ 1761607797U, // BLA8_Darwin
+ 1761607797U, // BLA8_ELF
+ 1761607797U, // BLA_Darwin
+ 1761607797U, // BLA_SVR4
+ 1228931172U, // BLR
+ 1493172337U, // BL_Darwin
+ 1493172337U, // BL_SVR4
+ 268435578U, // CMPD
+ 268439680U, // CMPDI
+ 268435591U, // CMPLD
+ 268447886U, // CMPLDI
+ 268435606U, // CMPLW
+ 268447901U, // CMPLWI
+ 268435621U, // CMPW
+ 268439723U, // CMPWI
+ 268468402U, // CNTLZD
+ 268468410U, // CNTLZW
+ 268435650U, // CREQV
+ 268435657U, // CROR
+ 268959938U, // CRSET
+ 1879048399U, // DCBA
+ 1879048405U, // DCBF
+ 1879048411U, // DCBI
+ 1879048417U, // DCBST
+ 1879048424U, // DCBT
+ 1879048430U, // DCBTST
+ 1879048438U, // DCBZ
+ 1879048444U, // DCBZL
+ 268435715U, // DIVD
+ 268435721U, // DIVDU
+ 268435728U, // DIVW
+ 268435734U, // DIVWU
+ 2147483933U, // DSS
+ 290U, // DSSALL
+ 2415919401U, // DST
+ 2415919401U, // DST64
+ 2415919406U, // DSTST
+ 2415919406U, // DSTST64
+ 2415919413U, // DSTSTT
+ 2415919413U, // DSTSTT64
+ 2415919421U, // DSTT
+ 2415919421U, // DSTT64
+ 696254534U, // DYNALLOC
+ 700448838U, // DYNALLOC8
+ 268435779U, // EQV
+ 268435779U, // EQV8
+ 268468552U, // EXTSB
+ 268468552U, // EXTSB8
+ 268468559U, // EXTSH
+ 268468559U, // EXTSH8
+ 268468566U, // EXTSW
+ 268468566U, // EXTSW_32
+ 268468566U, // EXTSW_32_64
+ 268468573U, // FABSD
+ 268468573U, // FABSS
+ 268435811U, // FADD
+ 268435817U, // FADDS
+ 268435811U, // FADDrtz
+ 268468592U, // FCFID
+ 268435831U, // FCMPUD
+ 268435831U, // FCMPUS
+ 268468606U, // FCTIDZ
+ 268468614U, // FCTIWZ
+ 268435854U, // FDIV
+ 268435860U, // FDIVS
+ 268435867U, // FMADD
+ 268435874U, // FMADDS
+ 268468650U, // FMRD
+ 268468650U, // FMRS
+ 268468650U, // FMRSD
+ 268435887U, // FMSUB
+ 268435894U, // FMSUBS
+ 268435902U, // FMUL
+ 268435908U, // FMULS
+ 268468683U, // FNABSD
+ 268468683U, // FNABSS
+ 268468690U, // FNEGD
+ 268468690U, // FNEGS
+ 268435928U, // FNMADD
+ 268435936U, // FNMADDS
+ 268435945U, // FNMSUB
+ 268435953U, // FNMSUBS
+ 268468730U, // FRSP
+ 268435968U, // FSELD
+ 268435968U, // FSELS
+ 268468742U, // FSQRT
+ 268468749U, // FSQRTS
+ 268435989U, // FSUB
+ 268435995U, // FSUBS
+ 269287970U, // LA
+ 269484582U, // LBZ
+ 269484582U, // LBZ8
+ 269746731U, // LBZU
+ 269746731U, // LBZU8
+ 270008881U, // LBZX
+ 270008881U, // LBZX8
+ 270271031U, // LD
+ 270008891U, // LDARX
+ 270533186U, // LDU
+ 270008903U, // LDX
+ 436208204U, // LDinto_toc
+ 270795319U, // LDtoc
+ 597U, // LDtoc_restore
+ 269484641U, // LFD
+ 269746785U, // LFDU
+ 270008934U, // LFDX
+ 269484652U, // LFS
+ 269746796U, // LFSU
+ 270008945U, // LFSX
+ 269484663U, // LHA
+ 269484663U, // LHA8
+ 269746812U, // LHAU
+ 269320828U, // LHAU8
+ 270008962U, // LHAX
+ 270008962U, // LHAX8
+ 270008968U, // LHBRX
+ 269484687U, // LHZ
+ 269484687U, // LHZ8
+ 269746836U, // LHZU
+ 269746836U, // LHZU8
+ 270008986U, // LHZX
+ 270008986U, // LHZX8
+ 271057568U, // LI
+ 271057568U, // LI8
+ 271319716U, // LIS
+ 271319716U, // LIS8
+ 270009001U, // LVEBX
+ 270009008U, // LVEHX
+ 270009015U, // LVEWX
+ 270009022U, // LVSL
+ 270009028U, // LVSR
+ 270009034U, // LVX
+ 270009039U, // LVXL
+ 270271189U, // LWA
+ 270009050U, // LWARX
+ 270009057U, // LWAX
+ 270009063U, // LWBRX
+ 269484782U, // LWZ
+ 269484782U, // LWZ8
+ 269746931U, // LWZU
+ 269746931U, // LWZU8
+ 270009081U, // LWZX
+ 270009081U, // LWZX8
+ 268468991U, // MCRF
+ 419431173U, // MFCR
+ 419431179U, // MFCTR
+ 419431179U, // MFCTR8
+ 419431186U, // MFFS
+ 419431192U, // MFLR
+ 419431192U, // MFLR8
+ 271581957U, // MFOCRF
+ 440402718U, // MFVRSAVE
+ 419431205U, // MFVSCR
+ 2684355373U, // MTCRF
+ 419431220U, // MTCTR
+ 419431220U, // MTCTR8
+ 2952790843U, // MTFSB0
+ 2952790851U, // MTFSB1
+ 3397387083U, // MTFSF
+ 419431250U, // MTLR
+ 419431250U, // MTLR8
+ 419431256U, // MTVRSAVE
+ 419431268U, // MTVSCR
+ 268436332U, // MULHD
+ 268436339U, // MULHDU
+ 268436347U, // MULHW
+ 268436354U, // MULHWU
+ 268436362U, // MULLD
+ 268440465U, // MULLI
+ 268436376U, // MULLW
+ 3489661041U, // MovePCtoLR
+ 3489661041U, // MovePCtoLR8
+ 268436383U, // NAND
+ 268436383U, // NAND8
+ 268469157U, // NEG
+ 268469157U, // NEG8
+ 938U, // NOP
+ 268436398U, // NOR
+ 268436398U, // NOR8
+ 268436403U, // OR
+ 268436403U, // OR4To8
+ 268436403U, // OR8
+ 268436403U, // OR8To4
+ 268436407U, // ORC
+ 268436407U, // ORC8
+ 268448700U, // ORI
+ 268448700U, // ORI8
+ 268448705U, // ORIS
+ 268448705U, // ORIS8
+ 268436423U, // RLDCL
+ 268452814U, // RLDICL
+ 268452822U, // RLDICR
+ 271975390U, // RLDIMI
+ 272008166U, // RLWIMI
+ 268456942U, // RLWINM
+ 268456950U, // RLWINMo
+ 268436479U, // RLWNM
+ 717226054U, // SELECT_CC_F4
+ 717226054U, // SELECT_CC_F8
+ 717226054U, // SELECT_CC_I4
+ 717226054U, // SELECT_CC_I8
+ 717226054U, // SELECT_CC_VRRC
+ 268436486U, // SLD
+ 268436491U, // SLW
+ 721420358U, // SPILL_CR
+ 268436496U, // SRAD
+ 268452886U, // SRADI
+ 268436509U, // SRAW
+ 268456995U, // SRAWI
+ 268436522U, // SRD
+ 268436527U, // SRW
+ 269485108U, // STB
+ 269485108U, // STB8
+ 3409970233U, // STBU
+ 3409970233U, // STBU8
+ 270009407U, // STBX
+ 270009407U, // STBX8
+ 270271557U, // STD
+ 270009418U, // STDCX
+ 3414164562U, // STDU
+ 270009432U, // STDUX
+ 270009439U, // STDX
+ 270009439U, // STDX_32
+ 270271557U, // STD_32
+ 269485157U, // STFD
+ 3409970283U, // STFDU
+ 270009458U, // STFDX
+ 270009465U, // STFIWX
+ 269485185U, // STFS
+ 3409970311U, // STFSU
+ 270009486U, // STFSX
+ 269485205U, // STH
+ 269485205U, // STH8
+ 270009498U, // STHBRX
+ 3409970338U, // STHU
+ 3409970338U, // STHU8
+ 270009512U, // STHX
+ 270009512U, // STHX8
+ 270009518U, // STVEBX
+ 270009526U, // STVEHX
+ 270009534U, // STVEWX
+ 270009542U, // STVX
+ 270009548U, // STVXL
+ 269485267U, // STW
+ 269485267U, // STW8
+ 270009560U, // STWBRX
+ 270009568U, // STWCX
+ 3409970408U, // STWU
+ 3409970408U, // STWU8
+ 268436718U, // STWUX
+ 270009589U, // STWX
+ 270009589U, // STWX8
+ 268436731U, // SUBF
+ 268436731U, // SUBF8
+ 268436737U, // SUBFC
+ 268436737U, // SUBFC8
+ 268436744U, // SUBFE
+ 268436744U, // SUBFE8
+ 268440847U, // SUBFIC
+ 268440847U, // SUBFIC8
+ 268469527U, // SUBFME
+ 268469527U, // SUBFME8
+ 268469535U, // SUBFZE
+ 268469535U, // SUBFZE8
+ 1319U, // SYNC
+ 1493172321U, // TAILB
+ 1493172321U, // TAILB8
+ 1761609004U, // TAILBA
+ 1761609004U, // TAILBA8
+ 102U, // TAILBCTR
+ 102U, // TAILBCTR8
+ 1757447472U, // TCRETURNai
+ 1757447485U, // TCRETURNai8
+ 1489012043U, // TCRETURNdi
+ 1489012056U, // TCRETURNdi8
+ 415270246U, // TCRETURNri
+ 415270259U, // TCRETURNri8
+ 1409U, // TRAP
+ 268469638U, // UPDATE_VRSAVE
+ 268436885U, // VADDCUW
+ 268436894U, // VADDFP
+ 268436902U, // VADDSBS
+ 268436911U, // VADDSHS
+ 268436920U, // VADDSWS
+ 268436929U, // VADDUBM
+ 268436938U, // VADDUBS
+ 268436947U, // VADDUHM
+ 268436956U, // VADDUHS
+ 268436965U, // VADDUWM
+ 268436974U, // VADDUWS
+ 268436983U, // VAND
+ 268436989U, // VANDC
+ 268436996U, // VAVGSB
+ 268437004U, // VAVGSH
+ 268437012U, // VAVGSW
+ 268437020U, // VAVGUB
+ 268437028U, // VAVGUH
+ 268437036U, // VAVGUW
+ 272041524U, // VCFSX
+ 272041531U, // VCFUX
+ 268437058U, // VCMPBFP
+ 268437067U, // VCMPBFPo
+ 268437077U, // VCMPEQFP
+ 268437087U, // VCMPEQFPo
+ 268437098U, // VCMPEQUB
+ 268437108U, // VCMPEQUBo
+ 268437119U, // VCMPEQUH
+ 268437129U, // VCMPEQUHo
+ 268437140U, // VCMPEQUW
+ 268437150U, // VCMPEQUWo
+ 268437161U, // VCMPGEFP
+ 268437171U, // VCMPGEFPo
+ 268437182U, // VCMPGTFP
+ 268437192U, // VCMPGTFPo
+ 268437203U, // VCMPGTSB
+ 268437213U, // VCMPGTSBo
+ 268437224U, // VCMPGTSH
+ 268437234U, // VCMPGTSHo
+ 268437245U, // VCMPGTSW
+ 268437255U, // VCMPGTSWo
+ 268437266U, // VCMPGTUB
+ 268437276U, // VCMPGTUBo
+ 268437287U, // VCMPGTUH
+ 268437297U, // VCMPGTUHo
+ 268437308U, // VCMPGTUW
+ 268437318U, // VCMPGTUWo
+ 272041809U, // VCTSXS
+ 272041817U, // VCTUXS
+ 268470113U, // VEXPTEFP
+ 268470123U, // VLOGEFP
+ 268437364U, // VMADDFP
+ 268437373U, // VMAXFP
+ 268437381U, // VMAXSB
+ 268437389U, // VMAXSH
+ 268437397U, // VMAXSW
+ 268437405U, // VMAXUB
+ 268437413U, // VMAXUH
+ 268437421U, // VMAXUW
+ 268437429U, // VMHADDSHS
+ 268437440U, // VMHRADDSHS
+ 268437452U, // VMINFP
+ 268437460U, // VMINSB
+ 268437468U, // VMINSH
+ 268437476U, // VMINSW
+ 268437484U, // VMINUB
+ 268437492U, // VMINUH
+ 268437500U, // VMINUW
+ 268437508U, // VMLADDUHM
+ 268437519U, // VMRGHB
+ 268437527U, // VMRGHH
+ 268437535U, // VMRGHW
+ 268437543U, // VMRGLB
+ 268437551U, // VMRGLH
+ 268437559U, // VMRGLW
+ 268437567U, // VMSUMMBM
+ 268437577U, // VMSUMSHM
+ 268437587U, // VMSUMSHS
+ 268437597U, // VMSUMUBM
+ 268437607U, // VMSUMUHM
+ 268437617U, // VMSUMUHS
+ 268437627U, // VMULESB
+ 268437636U, // VMULESH
+ 268437645U, // VMULEUB
+ 268437654U, // VMULEUH
+ 268437663U, // VMULOSB
+ 268437672U, // VMULOSH
+ 268437681U, // VMULOUB
+ 268437690U, // VMULOUH
+ 268437699U, // VNMSUBFP
+ 268437709U, // VNOR
+ 268437715U, // VOR
+ 268437720U, // VPERM
+ 268437727U, // VPKPX
+ 268437734U, // VPKSHSS
+ 268437743U, // VPKSHUS
+ 268437752U, // VPKSWSS
+ 268437761U, // VPKSWUS
+ 268437770U, // VPKUHUM
+ 268437779U, // VPKUHUS
+ 268437788U, // VPKUWUM
+ 268437797U, // VPKUWUS
+ 268470574U, // VREFP
+ 268470581U, // VRFIM
+ 268470588U, // VRFIN
+ 268470595U, // VRFIP
+ 268470602U, // VRFIZ
+ 268437841U, // VRLB
+ 268437847U, // VRLH
+ 268437853U, // VRLW
+ 268470627U, // VRSQRTEFP
+ 268437870U, // VSEL
+ 268437876U, // VSL
+ 268437881U, // VSLB
+ 268437887U, // VSLDOI
+ 268437895U, // VSLH
+ 268437901U, // VSLO
+ 268437907U, // VSLW
+ 272042393U, // VSPLTB
+ 272042401U, // VSPLTH
+ 272107945U, // VSPLTISB
+ 272107955U, // VSPLTISH
+ 272107965U, // VSPLTISW
+ 272042439U, // VSPLTW
+ 268437967U, // VSR
+ 268437972U, // VSRAB
+ 268437979U, // VSRAH
+ 268437986U, // VSRAW
+ 268437993U, // VSRB
+ 268437999U, // VSRH
+ 268438005U, // VSRO
+ 268438011U, // VSRW
+ 268438017U, // VSUBCUW
+ 268438026U, // VSUBFP
+ 268438034U, // VSUBSBS
+ 268438043U, // VSUBSHS
+ 268438052U, // VSUBSWS
+ 268438061U, // VSUBUBM
+ 268438070U, // VSUBUBS
+ 268438079U, // VSUBUHM
+ 268438088U, // VSUBUHS
+ 268438097U, // VSUBUWM
+ 268438106U, // VSUBUWS
+ 268438115U, // VSUM2SWS
+ 268438125U, // VSUM4SBS
+ 268438135U, // VSUM4SHS
+ 268438145U, // VSUM4UBS
+ 268438155U, // VSUMSWS
+ 268470932U, // VUPKHPX
+ 268470941U, // VUPKHSB
+ 268470950U, // VUPKHSH
+ 268470959U, // VUPKLPX
+ 268470968U, // VUPKLSB
+ 268470977U, // VUPKLSH
+ 268438218U, // VXOR
+ 268962506U, // V_SET0
+ 268438224U, // XOR
+ 268438224U, // XOR8
+ 268450517U, // XORI
+ 268450517U, // XORI8
+ 268450523U, // XORIS
+ 268450523U, // XORIS8
0U
};
const char *AsmStrs =
- "DEBUG_VALUE\000add \000addc \000adde \000addi \000addic \000addic. \000"
- "addis \000addme \000addze \000\000and \000andc \000andis. \000andi. \000"
- "b \000b\000bctr\000bctrl\000bl \000bla \000cmpd \000cmpdi \000cmpld \000"
+ "DBG_VALUE\000add \000addc \000adde \000addi \000addic \000addic. \000ad"
+ "dis \000addme \000addze \000\000and \000andc \000andis. \000andi. \000b"
+ " \000b\000bctr\000bctrl\000bl \000bla \000cmpd \000cmpdi \000cmpld \000"
"cmpldi \000cmplw \000cmplwi \000cmpw \000cmpwi \000cntlzd \000cntlzw \000"
"creqv \000cror \000dcba \000dcbf \000dcbi \000dcbst \000dcbt \000dcbtst"
" \000dcbz \000dcbzl \000divd \000divdu \000divw \000divwu \000dss \000d"
@@ -591,24 +591,6 @@ void PPCAsmPrinter::printInstruction(const MachineInstr *MI) {
" \000vupkhsb \000vupkhsh \000vupklpx \000vupklsb \000vupklsh \000vxor \000"
"xor \000xori \000xoris \000";
-
-#ifndef NO_ASM_WRITER_BOILERPLATE
- if (MI->getOpcode() == TargetInstrInfo::INLINEASM) {
- printInlineAsm(MI);
- return;
- } else if (MI->isLabel()) {
- printLabel(MI);
- return;
- } else if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
- printImplicitDef(MI);
- return;
- } else if (MI->getOpcode() == TargetInstrInfo::KILL) {
- printKill(MI);
- return;
- }
-
-
-#endif
O << "\t";
// Emit the opcode for the instruction.
@@ -621,7 +603,7 @@ void PPCAsmPrinter::printInstruction(const MachineInstr *MI) {
switch ((Bits >> 28) & 15) {
default: // unreachable.
case 0:
- // DEBUG_VALUE, BCTR, BCTRL8_Darwin, BCTRL8_ELF, BCTRL_Darwin, BCTRL_SVR4...
+ // DBG_VALUE, BCTR, BCTRL8_Darwin, BCTRL8_ELF, BCTRL_Darwin, BCTRL_SVR4, ...
return;
break;
case 1:
@@ -1414,3 +1396,138 @@ const char *PPCAsmPrinter::getRegisterName(unsigned RegNo) {
"3\000v30\000v31\000v4\000v5\000v6\000v7\000v8\000v9\000VRsave\000";
return AsmStrs+RegAsmOffset[RegNo-1];
}
+
+
+#ifdef GET_INSTRUCTION_NAME
+#undef GET_INSTRUCTION_NAME
+
+/// getInstructionName: This method is automatically generated by tblgen
+/// from the instruction set description. This returns the enum name of the
+/// specified instruction.
+const char *PPCAsmPrinter::getInstructionName(unsigned Opcode) {
+ assert(Opcode < 521 && "Invalid instruction number!");
+
+ static const unsigned InstAsmOffset[] = {
+ 0, 4, 14, 24, 33, 42, 47, 62, 76, 89, 103, 120, 130, 135,
+ 140, 145, 151, 156, 162, 167, 173, 179, 186, 193, 199, 206, 212, 219,
+ 225, 232, 249, 264, 268, 273, 278, 284, 291, 299, 305, 312, 332, 352,
+ 372, 391, 411, 431, 451, 470, 490, 510, 530, 549, 570, 591, 612, 632,
+ 651, 670, 689, 707, 727, 747, 767, 786, 806, 826, 846, 865, 881, 897,
+ 913, 928, 930, 934, 939, 953, 964, 977, 988, 999, 1007, 1019, 1028, 1039,
+ 1048, 1052, 1062, 1070, 1075, 1081, 1087, 1094, 1100, 1107, 1112, 1118, 1125, 1132,
+ 1138, 1143, 1149, 1154, 1159, 1164, 1170, 1175, 1182, 1187, 1193, 1198, 1204, 1209,
+ 1215, 1219, 1226, 1230, 1236, 1242, 1250, 1257, 1266, 1271, 1278, 1287, 1297, 1301,
+ 1306, 1312, 1319, 1325, 1332, 1338, 1347, 1359, 1365, 1371, 1376, 1382, 1390, 1396,
+ 1403, 1410, 1417, 1424, 1429, 1435, 1441, 1448, 1453, 1458, 1464, 1470, 1477, 1482,
+ 1488, 1495, 1502, 1508, 1514, 1521, 1529, 1536, 1544, 1549, 1555, 1561, 1567, 1574,
+ 1579, 1585, 1588, 1592, 1597, 1602, 1608, 1613, 1619, 1622, 1628, 1632, 1636, 1647,
+ 1653, 1667, 1671, 1676, 1681, 1685, 1690, 1695, 1699, 1704, 1709, 1715, 1720, 1726,
+ 1732, 1736, 1741, 1746, 1752, 1757, 1763, 1766, 1770, 1774, 1779, 1785, 1791, 1797,
+ 1802, 1807, 1811, 1816, 1820, 1826, 1831, 1837, 1841, 1846, 1851, 1857, 1862, 1868,
+ 1873, 1878, 1884, 1891, 1896, 1901, 1907, 1914, 1923, 1930, 1936, 1942, 1949, 1956,
+ 1963, 1969, 1974, 1980, 1989, 1996, 2002, 2009, 2015, 2022, 2028, 2034, 2040, 2051,
+ 2063, 2068, 2074, 2078, 2083, 2087, 2091, 2096, 2099, 2106, 2110, 2117, 2121, 2126,
+ 2130, 2135, 2140, 2146, 2152, 2159, 2166, 2173, 2180, 2187, 2195, 2201, 2214, 2227,
+ 2240, 2253, 2268, 2272, 2276, 2285, 2290, 2296, 2301, 2307, 2311, 2315, 2319, 2324,
+ 2329, 2335, 2340, 2346, 2350, 2356, 2361, 2367, 2372, 2380, 2387, 2392, 2398, 2404,
+ 2411, 2416, 2422, 2428, 2432, 2437, 2444, 2449, 2455, 2460, 2466, 2473, 2480, 2487,
+ 2492, 2498, 2502, 2507, 2514, 2520, 2525, 2531, 2537, 2542, 2548, 2553, 2559, 2565,
+ 2572, 2578, 2585, 2592, 2600, 2607, 2615, 2622, 2630, 2635, 2641, 2648, 2655, 2663,
+ 2672, 2682, 2693, 2705, 2716, 2728, 2739, 2751, 2756, 2770, 2778, 2785, 2793, 2801,
+ 2809, 2817, 2825, 2833, 2841, 2849, 2857, 2862, 2868, 2875, 2882, 2889, 2896, 2903,
+ 2910, 2916, 2922, 2930, 2939, 2948, 2958, 2967, 2977, 2986, 2996, 3005, 3015, 3024,
+ 3034, 3043, 3053, 3062, 3072, 3081, 3091, 3100, 3110, 3119, 3129, 3138, 3148, 3157,
+ 3167, 3174, 3181, 3190, 3198, 3206, 3213, 3220, 3227, 3234, 3241, 3248, 3255, 3265,
+ 3276, 3283, 3290, 3297, 3304, 3311, 3318, 3325, 3335, 3342, 3349, 3356, 3363, 3370,
+ 3377, 3386, 3395, 3404, 3413, 3422, 3431, 3439, 3447, 3455, 3463, 3471, 3479, 3487,
+ 3495, 3504, 3509, 3513, 3519, 3525, 3533, 3541, 3549, 3557, 3565, 3573, 3581, 3589,
+ 3595, 3601, 3607, 3613, 3619, 3624, 3629, 3634, 3644, 3649, 3653, 3658, 3665, 3670,
+ 3675, 3680, 3687, 3694, 3703, 3712, 3721, 3728, 3732, 3738, 3744, 3750, 3755, 3760,
+ 3765, 3770, 3778, 3785, 3793, 3801, 3809, 3817, 3825, 3833, 3841, 3849, 3857, 3866,
+ 3875, 3884, 3893, 3901, 3909, 3917, 3925, 3933, 3941, 3949, 3954, 3961, 3965, 3970,
+ 3975, 3981, 3987, 0
+ };
+
+ const char *Strs =
+ "PHI\000INLINEASM\000DBG_LABEL\000EH_LABEL\000GC_LABEL\000KILL\000EXTRAC"
+ "T_SUBREG\000INSERT_SUBREG\000IMPLICIT_DEF\000SUBREG_TO_REG\000COPY_TO_R"
+ "EGCLASS\000DBG_VALUE\000ADD4\000ADD8\000ADDC\000ADDC8\000ADDE\000ADDE8\000"
+ "ADDI\000ADDI8\000ADDIC\000ADDIC8\000ADDICo\000ADDIS\000ADDIS8\000ADDME\000"
+ "ADDME8\000ADDZE\000ADDZE8\000ADJCALLSTACKDOWN\000ADJCALLSTACKUP\000AND\000"
+ "AND8\000ANDC\000ANDC8\000ANDISo\000ANDISo8\000ANDIo\000ANDIo8\000ATOMIC"
+ "_CMP_SWAP_I16\000ATOMIC_CMP_SWAP_I32\000ATOMIC_CMP_SWAP_I64\000ATOMIC_C"
+ "MP_SWAP_I8\000ATOMIC_LOAD_ADD_I16\000ATOMIC_LOAD_ADD_I32\000ATOMIC_LOAD"
+ "_ADD_I64\000ATOMIC_LOAD_ADD_I8\000ATOMIC_LOAD_AND_I16\000ATOMIC_LOAD_AN"
+ "D_I32\000ATOMIC_LOAD_AND_I64\000ATOMIC_LOAD_AND_I8\000ATOMIC_LOAD_NAND_"
+ "I16\000ATOMIC_LOAD_NAND_I32\000ATOMIC_LOAD_NAND_I64\000ATOMIC_LOAD_NAND"
+ "_I8\000ATOMIC_LOAD_OR_I16\000ATOMIC_LOAD_OR_I32\000ATOMIC_LOAD_OR_I64\000"
+ "ATOMIC_LOAD_OR_I8\000ATOMIC_LOAD_SUB_I16\000ATOMIC_LOAD_SUB_I32\000ATOM"
+ "IC_LOAD_SUB_I64\000ATOMIC_LOAD_SUB_I8\000ATOMIC_LOAD_XOR_I16\000ATOMIC_"
+ "LOAD_XOR_I32\000ATOMIC_LOAD_XOR_I64\000ATOMIC_LOAD_XOR_I8\000ATOMIC_SWA"
+ "P_I16\000ATOMIC_SWAP_I32\000ATOMIC_SWAP_I64\000ATOMIC_SWAP_I8\000B\000B"
+ "CC\000BCTR\000BCTRL8_Darwin\000BCTRL8_ELF\000BCTRL_Darwin\000BCTRL_SVR4"
+ "\000BL8_Darwin\000BL8_ELF\000BLA8_Darwin\000BLA8_ELF\000BLA_Darwin\000B"
+ "LA_SVR4\000BLR\000BL_Darwin\000BL_SVR4\000CMPD\000CMPDI\000CMPLD\000CMP"
+ "LDI\000CMPLW\000CMPLWI\000CMPW\000CMPWI\000CNTLZD\000CNTLZW\000CREQV\000"
+ "CROR\000CRSET\000DCBA\000DCBF\000DCBI\000DCBST\000DCBT\000DCBTST\000DCB"
+ "Z\000DCBZL\000DIVD\000DIVDU\000DIVW\000DIVWU\000DSS\000DSSALL\000DST\000"
+ "DST64\000DSTST\000DSTST64\000DSTSTT\000DSTSTT64\000DSTT\000DSTT64\000DY"
+ "NALLOC\000DYNALLOC8\000EQV\000EQV8\000EXTSB\000EXTSB8\000EXTSH\000EXTSH"
+ "8\000EXTSW\000EXTSW_32\000EXTSW_32_64\000FABSD\000FABSS\000FADD\000FADD"
+ "S\000FADDrtz\000FCFID\000FCMPUD\000FCMPUS\000FCTIDZ\000FCTIWZ\000FDIV\000"
+ "FDIVS\000FMADD\000FMADDS\000FMRD\000FMRS\000FMRSD\000FMSUB\000FMSUBS\000"
+ "FMUL\000FMULS\000FNABSD\000FNABSS\000FNEGD\000FNEGS\000FNMADD\000FNMADD"
+ "S\000FNMSUB\000FNMSUBS\000FRSP\000FSELD\000FSELS\000FSQRT\000FSQRTS\000"
+ "FSUB\000FSUBS\000LA\000LBZ\000LBZ8\000LBZU\000LBZU8\000LBZX\000LBZX8\000"
+ "LD\000LDARX\000LDU\000LDX\000LDinto_toc\000LDtoc\000LDtoc_restore\000LF"
+ "D\000LFDU\000LFDX\000LFS\000LFSU\000LFSX\000LHA\000LHA8\000LHAU\000LHAU"
+ "8\000LHAX\000LHAX8\000LHBRX\000LHZ\000LHZ8\000LHZU\000LHZU8\000LHZX\000"
+ "LHZX8\000LI\000LI8\000LIS\000LIS8\000LVEBX\000LVEHX\000LVEWX\000LVSL\000"
+ "LVSR\000LVX\000LVXL\000LWA\000LWARX\000LWAX\000LWBRX\000LWZ\000LWZ8\000"
+ "LWZU\000LWZU8\000LWZX\000LWZX8\000MCRF\000MFCR\000MFCTR\000MFCTR8\000MF"
+ "FS\000MFLR\000MFLR8\000MFOCRF\000MFVRSAVE\000MFVSCR\000MTCRF\000MTCTR\000"
+ "MTCTR8\000MTFSB0\000MTFSB1\000MTFSF\000MTLR\000MTLR8\000MTVRSAVE\000MTV"
+ "SCR\000MULHD\000MULHDU\000MULHW\000MULHWU\000MULLD\000MULLI\000MULLW\000"
+ "MovePCtoLR\000MovePCtoLR8\000NAND\000NAND8\000NEG\000NEG8\000NOP\000NOR"
+ "\000NOR8\000OR\000OR4To8\000OR8\000OR8To4\000ORC\000ORC8\000ORI\000ORI8"
+ "\000ORIS\000ORIS8\000RLDCL\000RLDICL\000RLDICR\000RLDIMI\000RLWIMI\000R"
+ "LWINM\000RLWINMo\000RLWNM\000SELECT_CC_F4\000SELECT_CC_F8\000SELECT_CC_"
+ "I4\000SELECT_CC_I8\000SELECT_CC_VRRC\000SLD\000SLW\000SPILL_CR\000SRAD\000"
+ "SRADI\000SRAW\000SRAWI\000SRD\000SRW\000STB\000STB8\000STBU\000STBU8\000"
+ "STBX\000STBX8\000STD\000STDCX\000STDU\000STDUX\000STDX\000STDX_32\000ST"
+ "D_32\000STFD\000STFDU\000STFDX\000STFIWX\000STFS\000STFSU\000STFSX\000S"
+ "TH\000STH8\000STHBRX\000STHU\000STHU8\000STHX\000STHX8\000STVEBX\000STV"
+ "EHX\000STVEWX\000STVX\000STVXL\000STW\000STW8\000STWBRX\000STWCX\000STW"
+ "U\000STWU8\000STWUX\000STWX\000STWX8\000SUBF\000SUBF8\000SUBFC\000SUBFC"
+ "8\000SUBFE\000SUBFE8\000SUBFIC\000SUBFIC8\000SUBFME\000SUBFME8\000SUBFZ"
+ "E\000SUBFZE8\000SYNC\000TAILB\000TAILB8\000TAILBA\000TAILBA8\000TAILBCT"
+ "R\000TAILBCTR8\000TCRETURNai\000TCRETURNai8\000TCRETURNdi\000TCRETURNdi"
+ "8\000TCRETURNri\000TCRETURNri8\000TRAP\000UPDATE_VRSAVE\000VADDCUW\000V"
+ "ADDFP\000VADDSBS\000VADDSHS\000VADDSWS\000VADDUBM\000VADDUBS\000VADDUHM"
+ "\000VADDUHS\000VADDUWM\000VADDUWS\000VAND\000VANDC\000VAVGSB\000VAVGSH\000"
+ "VAVGSW\000VAVGUB\000VAVGUH\000VAVGUW\000VCFSX\000VCFUX\000VCMPBFP\000VC"
+ "MPBFPo\000VCMPEQFP\000VCMPEQFPo\000VCMPEQUB\000VCMPEQUBo\000VCMPEQUH\000"
+ "VCMPEQUHo\000VCMPEQUW\000VCMPEQUWo\000VCMPGEFP\000VCMPGEFPo\000VCMPGTFP"
+ "\000VCMPGTFPo\000VCMPGTSB\000VCMPGTSBo\000VCMPGTSH\000VCMPGTSHo\000VCMP"
+ "GTSW\000VCMPGTSWo\000VCMPGTUB\000VCMPGTUBo\000VCMPGTUH\000VCMPGTUHo\000"
+ "VCMPGTUW\000VCMPGTUWo\000VCTSXS\000VCTUXS\000VEXPTEFP\000VLOGEFP\000VMA"
+ "DDFP\000VMAXFP\000VMAXSB\000VMAXSH\000VMAXSW\000VMAXUB\000VMAXUH\000VMA"
+ "XUW\000VMHADDSHS\000VMHRADDSHS\000VMINFP\000VMINSB\000VMINSH\000VMINSW\000"
+ "VMINUB\000VMINUH\000VMINUW\000VMLADDUHM\000VMRGHB\000VMRGHH\000VMRGHW\000"
+ "VMRGLB\000VMRGLH\000VMRGLW\000VMSUMMBM\000VMSUMSHM\000VMSUMSHS\000VMSUM"
+ "UBM\000VMSUMUHM\000VMSUMUHS\000VMULESB\000VMULESH\000VMULEUB\000VMULEUH"
+ "\000VMULOSB\000VMULOSH\000VMULOUB\000VMULOUH\000VNMSUBFP\000VNOR\000VOR"
+ "\000VPERM\000VPKPX\000VPKSHSS\000VPKSHUS\000VPKSWSS\000VPKSWUS\000VPKUH"
+ "UM\000VPKUHUS\000VPKUWUM\000VPKUWUS\000VREFP\000VRFIM\000VRFIN\000VRFIP"
+ "\000VRFIZ\000VRLB\000VRLH\000VRLW\000VRSQRTEFP\000VSEL\000VSL\000VSLB\000"
+ "VSLDOI\000VSLH\000VSLO\000VSLW\000VSPLTB\000VSPLTH\000VSPLTISB\000VSPLT"
+ "ISH\000VSPLTISW\000VSPLTW\000VSR\000VSRAB\000VSRAH\000VSRAW\000VSRB\000"
+ "VSRH\000VSRO\000VSRW\000VSUBCUW\000VSUBFP\000VSUBSBS\000VSUBSHS\000VSUB"
+ "SWS\000VSUBUBM\000VSUBUBS\000VSUBUHM\000VSUBUHS\000VSUBUWM\000VSUBUWS\000"
+ "VSUM2SWS\000VSUM4SBS\000VSUM4SHS\000VSUM4UBS\000VSUMSWS\000VUPKHPX\000V"
+ "UPKHSB\000VUPKHSH\000VUPKLPX\000VUPKLSB\000VUPKLSH\000VXOR\000V_SET0\000"
+ "XOR\000XOR8\000XORI\000XORI8\000XORIS\000XORIS8\000";
+ return Strs+InstAsmOffset[Opcode];
+}
+
+#endif
diff --git a/libclamav/c++/PPCGenDAGISel.inc b/libclamav/c++/PPCGenDAGISel.inc
index 4ab2322..4a898f2 100644
--- a/libclamav/c++/PPCGenDAGISel.inc
+++ b/libclamav/c++/PPCGenDAGISel.inc
@@ -3098,10 +3098,10 @@ SDNode *Select_ISD_INTRINSIC_VOID(SDNode *N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_void:isVoid 335:iPTR, xoaddr:iPTR:$dst)
+ // Pattern: (intrinsic_void:isVoid 336:iPTR, xoaddr:iPTR:$dst)
// Emits: (DCBA:isVoid xoaddr:iPTR:$dst)
// Pattern complexity = 17 cost = 1 size = 0
- if (CN1 == INT64_C(335)) {
+ if (CN1 == INT64_C(336)) {
SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
@@ -3111,10 +3111,10 @@ SDNode *Select_ISD_INTRINSIC_VOID(SDNode *N) {
}
}
- // Pattern: (intrinsic_void:isVoid 336:iPTR, xoaddr:iPTR:$dst)
+ // Pattern: (intrinsic_void:isVoid 337:iPTR, xoaddr:iPTR:$dst)
// Emits: (DCBF:isVoid xoaddr:iPTR:$dst)
// Pattern complexity = 17 cost = 1 size = 0
- if (CN1 == INT64_C(336)) {
+ if (CN1 == INT64_C(337)) {
SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
@@ -3124,10 +3124,10 @@ SDNode *Select_ISD_INTRINSIC_VOID(SDNode *N) {
}
}
- // Pattern: (intrinsic_void:isVoid 337:iPTR, xoaddr:iPTR:$dst)
+ // Pattern: (intrinsic_void:isVoid 338:iPTR, xoaddr:iPTR:$dst)
// Emits: (DCBI:isVoid xoaddr:iPTR:$dst)
// Pattern complexity = 17 cost = 1 size = 0
- if (CN1 == INT64_C(337)) {
+ if (CN1 == INT64_C(338)) {
SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
@@ -3137,10 +3137,10 @@ SDNode *Select_ISD_INTRINSIC_VOID(SDNode *N) {
}
}
- // Pattern: (intrinsic_void:isVoid 338:iPTR, xoaddr:iPTR:$dst)
+ // Pattern: (intrinsic_void:isVoid 339:iPTR, xoaddr:iPTR:$dst)
// Emits: (DCBST:isVoid xoaddr:iPTR:$dst)
// Pattern complexity = 17 cost = 1 size = 0
- if (CN1 == INT64_C(338)) {
+ if (CN1 == INT64_C(339)) {
SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
@@ -3150,10 +3150,10 @@ SDNode *Select_ISD_INTRINSIC_VOID(SDNode *N) {
}
}
- // Pattern: (intrinsic_void:isVoid 339:iPTR, xoaddr:iPTR:$dst)
+ // Pattern: (intrinsic_void:isVoid 340:iPTR, xoaddr:iPTR:$dst)
// Emits: (DCBT:isVoid xoaddr:iPTR:$dst)
// Pattern complexity = 17 cost = 1 size = 0
- if (CN1 == INT64_C(339)) {
+ if (CN1 == INT64_C(340)) {
SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
@@ -3163,10 +3163,10 @@ SDNode *Select_ISD_INTRINSIC_VOID(SDNode *N) {
}
}
- // Pattern: (intrinsic_void:isVoid 340:iPTR, xoaddr:iPTR:$dst)
+ // Pattern: (intrinsic_void:isVoid 341:iPTR, xoaddr:iPTR:$dst)
// Emits: (DCBTST:isVoid xoaddr:iPTR:$dst)
// Pattern complexity = 17 cost = 1 size = 0
- if (CN1 == INT64_C(340)) {
+ if (CN1 == INT64_C(341)) {
SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
@@ -3176,10 +3176,10 @@ SDNode *Select_ISD_INTRINSIC_VOID(SDNode *N) {
}
}
- // Pattern: (intrinsic_void:isVoid 341:iPTR, xoaddr:iPTR:$dst)
+ // Pattern: (intrinsic_void:isVoid 342:iPTR, xoaddr:iPTR:$dst)
// Emits: (DCBZ:isVoid xoaddr:iPTR:$dst)
// Pattern complexity = 17 cost = 1 size = 0
- if (CN1 == INT64_C(341)) {
+ if (CN1 == INT64_C(342)) {
SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
@@ -3189,10 +3189,10 @@ SDNode *Select_ISD_INTRINSIC_VOID(SDNode *N) {
}
}
- // Pattern: (intrinsic_void:isVoid 342:iPTR, xoaddr:iPTR:$dst)
+ // Pattern: (intrinsic_void:isVoid 343:iPTR, xoaddr:iPTR:$dst)
// Emits: (DCBZL:isVoid xoaddr:iPTR:$dst)
// Pattern complexity = 17 cost = 1 size = 0
- if (CN1 == INT64_C(342)) {
+ if (CN1 == INT64_C(343)) {
SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
@@ -3202,10 +3202,10 @@ SDNode *Select_ISD_INTRINSIC_VOID(SDNode *N) {
}
}
- // Pattern: (intrinsic_void:isVoid 203:iPTR, VRRC:v16i8:$rS, xoaddr:iPTR:$dst)
+ // Pattern: (intrinsic_void:isVoid 204:iPTR, VRRC:v16i8:$rS, xoaddr:iPTR:$dst)
// Emits: (STVEBX:isVoid VRRC:v16i8:$rS, xoaddr:iPTR:$dst)
// Pattern complexity = 17 cost = 1 size = 0
- if (CN1 == INT64_C(203)) {
+ if (CN1 == INT64_C(204)) {
SDValue N2 = N->getOperand(2);
SDValue N3 = N->getOperand(3);
SDValue CPTmpN3_0;
@@ -3216,10 +3216,10 @@ SDNode *Select_ISD_INTRINSIC_VOID(SDNode *N) {
}
}
- // Pattern: (intrinsic_void:isVoid 204:iPTR, VRRC:v8i16:$rS, xoaddr:iPTR:$dst)
+ // Pattern: (intrinsic_void:isVoid 205:iPTR, VRRC:v8i16:$rS, xoaddr:iPTR:$dst)
// Emits: (STVEHX:isVoid VRRC:v8i16:$rS, xoaddr:iPTR:$dst)
// Pattern complexity = 17 cost = 1 size = 0
- if (CN1 == INT64_C(204)) {
+ if (CN1 == INT64_C(205)) {
SDValue N2 = N->getOperand(2);
SDValue N3 = N->getOperand(3);
SDValue CPTmpN3_0;
@@ -3230,10 +3230,10 @@ SDNode *Select_ISD_INTRINSIC_VOID(SDNode *N) {
}
}
- // Pattern: (intrinsic_void:isVoid 205:iPTR, VRRC:v4i32:$rS, xoaddr:iPTR:$dst)
+ // Pattern: (intrinsic_void:isVoid 206:iPTR, VRRC:v4i32:$rS, xoaddr:iPTR:$dst)
// Emits: (STVEWX:isVoid VRRC:v4i32:$rS, xoaddr:iPTR:$dst)
// Pattern complexity = 17 cost = 1 size = 0
- if (CN1 == INT64_C(205)) {
+ if (CN1 == INT64_C(206)) {
SDValue N2 = N->getOperand(2);
SDValue N3 = N->getOperand(3);
SDValue CPTmpN3_0;
@@ -3244,10 +3244,10 @@ SDNode *Select_ISD_INTRINSIC_VOID(SDNode *N) {
}
}
- // Pattern: (intrinsic_void:isVoid 206:iPTR, VRRC:v4i32:$rS, xoaddr:iPTR:$dst)
+ // Pattern: (intrinsic_void:isVoid 207:iPTR, VRRC:v4i32:$rS, xoaddr:iPTR:$dst)
// Emits: (STVX:isVoid VRRC:v4i32:$rS, xoaddr:iPTR:$dst)
// Pattern complexity = 17 cost = 1 size = 0
- if (CN1 == INT64_C(206)) {
+ if (CN1 == INT64_C(207)) {
SDValue N2 = N->getOperand(2);
SDValue N3 = N->getOperand(3);
SDValue CPTmpN3_0;
@@ -3258,10 +3258,10 @@ SDNode *Select_ISD_INTRINSIC_VOID(SDNode *N) {
}
}
- // Pattern: (intrinsic_void:isVoid 207:iPTR, VRRC:v4i32:$rS, xoaddr:iPTR:$dst)
+ // Pattern: (intrinsic_void:isVoid 208:iPTR, VRRC:v4i32:$rS, xoaddr:iPTR:$dst)
// Emits: (STVXL:isVoid VRRC:v4i32:$rS, xoaddr:iPTR:$dst)
// Pattern complexity = 17 cost = 1 size = 0
- if (CN1 == INT64_C(207)) {
+ if (CN1 == INT64_C(208)) {
SDValue N2 = N->getOperand(2);
SDValue N3 = N->getOperand(3);
SDValue CPTmpN3_0;
@@ -3272,10 +3272,10 @@ SDNode *Select_ISD_INTRINSIC_VOID(SDNode *N) {
}
}
- // Pattern: (intrinsic_void:isVoid 188:iPTR, (imm:i32):$STRM)
+ // Pattern: (intrinsic_void:isVoid 189:iPTR, (imm:i32):$STRM)
// Emits: (DSS:isVoid 0:i32, (imm:i32):$STRM, 0:i32, 0:i32)
// Pattern complexity = 11 cost = 1 size = 0
- if (CN1 == INT64_C(188)) {
+ if (CN1 == INT64_C(189)) {
SDValue N2 = N->getOperand(2);
if (N2.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_47(N, PPC::DSS);
@@ -3283,10 +3283,10 @@ SDNode *Select_ISD_INTRINSIC_VOID(SDNode *N) {
}
}
- // Pattern: (intrinsic_void:isVoid 190:iPTR, GPRC:i32:$rA, GPRC:i32:$rB, (imm:i32):$STRM)
+ // Pattern: (intrinsic_void:isVoid 191:iPTR, GPRC:i32:$rA, GPRC:i32:$rB, (imm:i32):$STRM)
// Emits: (DST:isVoid 0:i32, (imm:i32):$STRM, GPRC:i32:$rA, GPRC:i32:$rB)
// Pattern complexity = 11 cost = 1 size = 0
- if (CN1 == INT64_C(190)) {
+ if (CN1 == INT64_C(191)) {
SDValue N2 = N->getOperand(2);
SDValue N3 = N->getOperand(3);
SDValue N4 = N->getOperand(4);
@@ -3297,10 +3297,10 @@ SDNode *Select_ISD_INTRINSIC_VOID(SDNode *N) {
}
}
- // Pattern: (intrinsic_void:isVoid 193:iPTR, GPRC:i32:$rA, GPRC:i32:$rB, (imm:i32):$STRM)
+ // Pattern: (intrinsic_void:isVoid 194:iPTR, GPRC:i32:$rA, GPRC:i32:$rB, (imm:i32):$STRM)
// Emits: (DSTT:isVoid 1:i32, (imm:i32):$STRM, GPRC:i32:$rA, GPRC:i32:$rB)
// Pattern complexity = 11 cost = 1 size = 0
- if (CN1 == INT64_C(193)) {
+ if (CN1 == INT64_C(194)) {
SDValue N2 = N->getOperand(2);
SDValue N3 = N->getOperand(3);
SDValue N4 = N->getOperand(4);
@@ -3311,10 +3311,10 @@ SDNode *Select_ISD_INTRINSIC_VOID(SDNode *N) {
}
}
- // Pattern: (intrinsic_void:isVoid 191:iPTR, GPRC:i32:$rA, GPRC:i32:$rB, (imm:i32):$STRM)
+ // Pattern: (intrinsic_void:isVoid 192:iPTR, GPRC:i32:$rA, GPRC:i32:$rB, (imm:i32):$STRM)
// Emits: (DSTST:isVoid 0:i32, (imm:i32):$STRM, GPRC:i32:$rA, GPRC:i32:$rB)
// Pattern complexity = 11 cost = 1 size = 0
- if (CN1 == INT64_C(191)) {
+ if (CN1 == INT64_C(192)) {
SDValue N2 = N->getOperand(2);
SDValue N3 = N->getOperand(3);
SDValue N4 = N->getOperand(4);
@@ -3325,10 +3325,10 @@ SDNode *Select_ISD_INTRINSIC_VOID(SDNode *N) {
}
}
- // Pattern: (intrinsic_void:isVoid 192:iPTR, GPRC:i32:$rA, GPRC:i32:$rB, (imm:i32):$STRM)
+ // Pattern: (intrinsic_void:isVoid 193:iPTR, GPRC:i32:$rA, GPRC:i32:$rB, (imm:i32):$STRM)
// Emits: (DSTSTT:isVoid 1:i32, (imm:i32):$STRM, GPRC:i32:$rA, GPRC:i32:$rB)
// Pattern complexity = 11 cost = 1 size = 0
- if (CN1 == INT64_C(192)) {
+ if (CN1 == INT64_C(193)) {
SDValue N2 = N->getOperand(2);
SDValue N3 = N->getOperand(3);
SDValue N4 = N->getOperand(4);
@@ -3339,10 +3339,10 @@ SDNode *Select_ISD_INTRINSIC_VOID(SDNode *N) {
}
}
- // Pattern: (intrinsic_void:isVoid 190:iPTR, G8RC:i64:$rA, GPRC:i32:$rB, (imm:i32):$STRM)
+ // Pattern: (intrinsic_void:isVoid 191:iPTR, G8RC:i64:$rA, GPRC:i32:$rB, (imm:i32):$STRM)
// Emits: (DST64:isVoid 0:i32, (imm:i32):$STRM, G8RC:i64:$rA, GPRC:i32:$rB)
// Pattern complexity = 11 cost = 1 size = 0
- if (CN1 == INT64_C(190)) {
+ if (CN1 == INT64_C(191)) {
SDValue N2 = N->getOperand(2);
SDValue N3 = N->getOperand(3);
SDValue N4 = N->getOperand(4);
@@ -3353,10 +3353,10 @@ SDNode *Select_ISD_INTRINSIC_VOID(SDNode *N) {
}
}
- // Pattern: (intrinsic_void:isVoid 193:iPTR, G8RC:i64:$rA, GPRC:i32:$rB, (imm:i32):$STRM)
+ // Pattern: (intrinsic_void:isVoid 194:iPTR, G8RC:i64:$rA, GPRC:i32:$rB, (imm:i32):$STRM)
// Emits: (DSTT64:isVoid 1:i32, (imm:i32):$STRM, G8RC:i64:$rA, GPRC:i32:$rB)
// Pattern complexity = 11 cost = 1 size = 0
- if (CN1 == INT64_C(193)) {
+ if (CN1 == INT64_C(194)) {
SDValue N2 = N->getOperand(2);
SDValue N3 = N->getOperand(3);
SDValue N4 = N->getOperand(4);
@@ -3367,10 +3367,10 @@ SDNode *Select_ISD_INTRINSIC_VOID(SDNode *N) {
}
}
- // Pattern: (intrinsic_void:isVoid 191:iPTR, G8RC:i64:$rA, GPRC:i32:$rB, (imm:i32):$STRM)
+ // Pattern: (intrinsic_void:isVoid 192:iPTR, G8RC:i64:$rA, GPRC:i32:$rB, (imm:i32):$STRM)
// Emits: (DSTST64:isVoid 0:i32, (imm:i32):$STRM, G8RC:i64:$rA, GPRC:i32:$rB)
// Pattern complexity = 11 cost = 1 size = 0
- if (CN1 == INT64_C(191)) {
+ if (CN1 == INT64_C(192)) {
SDValue N2 = N->getOperand(2);
SDValue N3 = N->getOperand(3);
SDValue N4 = N->getOperand(4);
@@ -3381,10 +3381,10 @@ SDNode *Select_ISD_INTRINSIC_VOID(SDNode *N) {
}
}
- // Pattern: (intrinsic_void:isVoid 192:iPTR, G8RC:i64:$rA, GPRC:i32:$rB, (imm:i32):$STRM)
+ // Pattern: (intrinsic_void:isVoid 193:iPTR, G8RC:i64:$rA, GPRC:i32:$rB, (imm:i32):$STRM)
// Emits: (DSTSTT64:isVoid 1:i32, (imm:i32):$STRM, G8RC:i64:$rA, GPRC:i32:$rB)
// Pattern complexity = 11 cost = 1 size = 0
- if (CN1 == INT64_C(192)) {
+ if (CN1 == INT64_C(193)) {
SDValue N2 = N->getOperand(2);
SDValue N3 = N->getOperand(3);
SDValue N4 = N->getOperand(4);
@@ -3395,26 +3395,26 @@ SDNode *Select_ISD_INTRINSIC_VOID(SDNode *N) {
}
}
- // Pattern: (intrinsic_void:isVoid 343:iPTR)
+ // Pattern: (intrinsic_void:isVoid 344:iPTR)
// Emits: (SYNC:isVoid)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(343)) {
+ if (CN1 == INT64_C(344)) {
SDNode *Result = Emit_43(N, PPC::SYNC);
return Result;
}
- // Pattern: (intrinsic_void:isVoid 202:iPTR, VRRC:v4i32:$vB)
+ // Pattern: (intrinsic_void:isVoid 203:iPTR, VRRC:v4i32:$vB)
// Emits: (MTVSCR:isVoid VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(202)) {
+ if (CN1 == INT64_C(203)) {
SDNode *Result = Emit_44(N, PPC::MTVSCR);
return Result;
}
- // Pattern: (intrinsic_void:isVoid 189:iPTR)
+ // Pattern: (intrinsic_void:isVoid 190:iPTR)
// Emits: (DSSALL:isVoid 1:i32, 0:i32, 0:i32, 0:i32)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(189)) {
+ if (CN1 == INT64_C(190)) {
SDNode *Result = Emit_46(N, PPC::DSSALL);
return Result;
}
@@ -3441,10 +3441,10 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(SDNode *N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v16i8 197:iPTR, xoaddr:iPTR:$src)
+ // Pattern: (intrinsic_wo_chain:v16i8 198:iPTR, xoaddr:iPTR:$src)
// Emits: (LVSL:v16i8 xoaddr:iPTR:$src)
// Pattern complexity = 17 cost = 1 size = 0
- if (CN1 == INT64_C(197)) {
+ if (CN1 == INT64_C(198)) {
SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
@@ -3454,10 +3454,10 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(SDNode *N) {
}
}
- // Pattern: (intrinsic_wo_chain:v16i8 198:iPTR, xoaddr:iPTR:$src)
+ // Pattern: (intrinsic_wo_chain:v16i8 199:iPTR, xoaddr:iPTR:$src)
// Emits: (LVSR:v16i8 xoaddr:iPTR:$src)
// Pattern complexity = 17 cost = 1 size = 0
- if (CN1 == INT64_C(198)) {
+ if (CN1 == INT64_C(199)) {
SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
@@ -3467,146 +3467,146 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(SDNode *N) {
}
}
- // Pattern: (intrinsic_wo_chain:v16i8 209:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern: (intrinsic_wo_chain:v16i8 210:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Emits: (VADDSBS:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(209)) {
+ if (CN1 == INT64_C(210)) {
SDNode *Result = Emit_51(N, PPC::VADDSBS, MVT::v16i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v16i8 212:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern: (intrinsic_wo_chain:v16i8 213:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Emits: (VADDUBS:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(212)) {
+ if (CN1 == INT64_C(213)) {
SDNode *Result = Emit_51(N, PPC::VADDUBS, MVT::v16i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v16i8 215:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern: (intrinsic_wo_chain:v16i8 216:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Emits: (VAVGSB:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(215)) {
+ if (CN1 == INT64_C(216)) {
SDNode *Result = Emit_51(N, PPC::VAVGSB, MVT::v16i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v16i8 218:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern: (intrinsic_wo_chain:v16i8 219:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Emits: (VAVGUB:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(218)) {
+ if (CN1 == INT64_C(219)) {
SDNode *Result = Emit_51(N, PPC::VAVGUB, MVT::v16i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v16i8 255:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern: (intrinsic_wo_chain:v16i8 256:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Emits: (VMAXSB:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(255)) {
+ if (CN1 == INT64_C(256)) {
SDNode *Result = Emit_51(N, PPC::VMAXSB, MVT::v16i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v16i8 258:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern: (intrinsic_wo_chain:v16i8 259:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Emits: (VMAXUB:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(258)) {
+ if (CN1 == INT64_C(259)) {
SDNode *Result = Emit_51(N, PPC::VMAXUB, MVT::v16i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v16i8 264:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern: (intrinsic_wo_chain:v16i8 265:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Emits: (VMINSB:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(264)) {
+ if (CN1 == INT64_C(265)) {
SDNode *Result = Emit_51(N, PPC::VMINSB, MVT::v16i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v16i8 267:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern: (intrinsic_wo_chain:v16i8 268:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Emits: (VMINUB:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(267)) {
+ if (CN1 == INT64_C(268)) {
SDNode *Result = Emit_51(N, PPC::VMINUB, MVT::v16i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v16i8 318:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern: (intrinsic_wo_chain:v16i8 319:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Emits: (VSUBSBS:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(318)) {
+ if (CN1 == INT64_C(319)) {
SDNode *Result = Emit_51(N, PPC::VSUBSBS, MVT::v16i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v16i8 321:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern: (intrinsic_wo_chain:v16i8 322:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Emits: (VSUBUBS:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(321)) {
+ if (CN1 == INT64_C(322)) {
SDNode *Result = Emit_51(N, PPC::VSUBUBS, MVT::v16i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v16i8 299:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern: (intrinsic_wo_chain:v16i8 300:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Emits: (VRLB:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(299)) {
+ if (CN1 == INT64_C(300)) {
SDNode *Result = Emit_51(N, PPC::VRLB, MVT::v16i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v16i8 305:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern: (intrinsic_wo_chain:v16i8 306:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Emits: (VSLB:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(305)) {
+ if (CN1 == INT64_C(306)) {
SDNode *Result = Emit_51(N, PPC::VSLB, MVT::v16i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v16i8 310:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern: (intrinsic_wo_chain:v16i8 311:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Emits: (VSRAB:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(310)) {
+ if (CN1 == INT64_C(311)) {
SDNode *Result = Emit_51(N, PPC::VSRAB, MVT::v16i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v16i8 313:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern: (intrinsic_wo_chain:v16i8 314:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Emits: (VSRB:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(313)) {
+ if (CN1 == INT64_C(314)) {
SDNode *Result = Emit_51(N, PPC::VSRB, MVT::v16i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v16i8 288:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern: (intrinsic_wo_chain:v16i8 289:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Emits: (VPKSHSS:v16i8 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(288)) {
+ if (CN1 == INT64_C(289)) {
SDNode *Result = Emit_51(N, PPC::VPKSHSS, MVT::v16i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v16i8 289:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern: (intrinsic_wo_chain:v16i8 290:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Emits: (VPKSHUS:v16i8 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(289)) {
+ if (CN1 == INT64_C(290)) {
SDNode *Result = Emit_51(N, PPC::VPKSHUS, MVT::v16i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v16i8 290:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern: (intrinsic_wo_chain:v16i8 291:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Emits: (VPKSWSS:v16i8 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(290)) {
+ if (CN1 == INT64_C(291)) {
SDNode *Result = Emit_51(N, PPC::VPKSWSS, MVT::v16i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v16i8 292:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern: (intrinsic_wo_chain:v16i8 293:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Emits: (VPKUHUS:v16i8 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(292)) {
+ if (CN1 == INT64_C(293)) {
SDNode *Result = Emit_51(N, PPC::VPKUHUS, MVT::v16i8);
return Result;
}
@@ -3634,210 +3634,210 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(SDNode *N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v8i16 261:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v8i16:$vC)
+ // Pattern: (intrinsic_wo_chain:v8i16 262:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v8i16:$vC)
// Emits: (VMHADDSHS:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v8i16:$vC)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(261)) {
+ if (CN1 == INT64_C(262)) {
SDNode *Result = Emit_52(N, PPC::VMHADDSHS, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 262:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v8i16:$vC)
+ // Pattern: (intrinsic_wo_chain:v8i16 263:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v8i16:$vC)
// Emits: (VMHRADDSHS:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v8i16:$vC)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(262)) {
+ if (CN1 == INT64_C(263)) {
SDNode *Result = Emit_52(N, PPC::VMHRADDSHS, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 270:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v8i16:$vC)
+ // Pattern: (intrinsic_wo_chain:v8i16 271:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v8i16:$vC)
// Emits: (VMLADDUHM:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v8i16:$vC)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(270)) {
+ if (CN1 == INT64_C(271)) {
SDNode *Result = Emit_52(N, PPC::VMLADDUHM, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 210:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern: (intrinsic_wo_chain:v8i16 211:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Emits: (VADDSHS:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(210)) {
+ if (CN1 == INT64_C(211)) {
SDNode *Result = Emit_51(N, PPC::VADDSHS, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 213:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern: (intrinsic_wo_chain:v8i16 214:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Emits: (VADDUHS:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(213)) {
+ if (CN1 == INT64_C(214)) {
SDNode *Result = Emit_51(N, PPC::VADDUHS, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 216:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern: (intrinsic_wo_chain:v8i16 217:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Emits: (VAVGSH:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(216)) {
+ if (CN1 == INT64_C(217)) {
SDNode *Result = Emit_51(N, PPC::VAVGSH, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 219:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern: (intrinsic_wo_chain:v8i16 220:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Emits: (VAVGUH:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(219)) {
+ if (CN1 == INT64_C(220)) {
SDNode *Result = Emit_51(N, PPC::VAVGUH, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 256:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern: (intrinsic_wo_chain:v8i16 257:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Emits: (VMAXSH:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(256)) {
+ if (CN1 == INT64_C(257)) {
SDNode *Result = Emit_51(N, PPC::VMAXSH, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 259:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern: (intrinsic_wo_chain:v8i16 260:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Emits: (VMAXUH:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(259)) {
+ if (CN1 == INT64_C(260)) {
SDNode *Result = Emit_51(N, PPC::VMAXUH, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 265:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern: (intrinsic_wo_chain:v8i16 266:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Emits: (VMINSH:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(265)) {
+ if (CN1 == INT64_C(266)) {
SDNode *Result = Emit_51(N, PPC::VMINSH, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 268:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern: (intrinsic_wo_chain:v8i16 269:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Emits: (VMINUH:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(268)) {
+ if (CN1 == INT64_C(269)) {
SDNode *Result = Emit_51(N, PPC::VMINUH, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 277:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern: (intrinsic_wo_chain:v8i16 278:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Emits: (VMULESB:v8i16 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(277)) {
+ if (CN1 == INT64_C(278)) {
SDNode *Result = Emit_51(N, PPC::VMULESB, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 279:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern: (intrinsic_wo_chain:v8i16 280:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Emits: (VMULEUB:v8i16 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(279)) {
+ if (CN1 == INT64_C(280)) {
SDNode *Result = Emit_51(N, PPC::VMULEUB, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 281:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern: (intrinsic_wo_chain:v8i16 282:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Emits: (VMULOSB:v8i16 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(281)) {
+ if (CN1 == INT64_C(282)) {
SDNode *Result = Emit_51(N, PPC::VMULOSB, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 283:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern: (intrinsic_wo_chain:v8i16 284:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Emits: (VMULOUB:v8i16 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(283)) {
+ if (CN1 == INT64_C(284)) {
SDNode *Result = Emit_51(N, PPC::VMULOUB, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 319:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern: (intrinsic_wo_chain:v8i16 320:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Emits: (VSUBSHS:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(319)) {
+ if (CN1 == INT64_C(320)) {
SDNode *Result = Emit_51(N, PPC::VSUBSHS, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 322:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern: (intrinsic_wo_chain:v8i16 323:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Emits: (VSUBUHS:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(322)) {
+ if (CN1 == INT64_C(323)) {
SDNode *Result = Emit_51(N, PPC::VSUBUHS, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 300:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern: (intrinsic_wo_chain:v8i16 301:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Emits: (VRLH:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(300)) {
+ if (CN1 == INT64_C(301)) {
SDNode *Result = Emit_51(N, PPC::VRLH, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 306:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern: (intrinsic_wo_chain:v8i16 307:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Emits: (VSLH:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(306)) {
+ if (CN1 == INT64_C(307)) {
SDNode *Result = Emit_51(N, PPC::VSLH, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 311:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern: (intrinsic_wo_chain:v8i16 312:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Emits: (VSRAH:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(311)) {
+ if (CN1 == INT64_C(312)) {
SDNode *Result = Emit_51(N, PPC::VSRAH, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 314:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern: (intrinsic_wo_chain:v8i16 315:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Emits: (VSRH:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(314)) {
+ if (CN1 == INT64_C(315)) {
SDNode *Result = Emit_51(N, PPC::VSRH, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 287:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern: (intrinsic_wo_chain:v8i16 288:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Emits: (VPKPX:v8i16 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(287)) {
+ if (CN1 == INT64_C(288)) {
SDNode *Result = Emit_51(N, PPC::VPKPX, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 291:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern: (intrinsic_wo_chain:v8i16 292:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Emits: (VPKSWUS:v8i16 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(291)) {
+ if (CN1 == INT64_C(292)) {
SDNode *Result = Emit_51(N, PPC::VPKSWUS, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 293:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern: (intrinsic_wo_chain:v8i16 294:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Emits: (VPKUWUS:v8i16 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(293)) {
+ if (CN1 == INT64_C(294)) {
SDNode *Result = Emit_51(N, PPC::VPKUWUS, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 330:iPTR, VRRC:v16i8:$vB)
+ // Pattern: (intrinsic_wo_chain:v8i16 331:iPTR, VRRC:v16i8:$vB)
// Emits: (VUPKHSB:v8i16 VRRC:v16i8:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(330)) {
+ if (CN1 == INT64_C(331)) {
SDNode *Result = Emit_53(N, PPC::VUPKHSB, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 333:iPTR, VRRC:v16i8:$vB)
+ // Pattern: (intrinsic_wo_chain:v8i16 334:iPTR, VRRC:v16i8:$vB)
// Emits: (VUPKLSB:v8i16 VRRC:v16i8:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(333)) {
+ if (CN1 == INT64_C(334)) {
SDNode *Result = Emit_53(N, PPC::VUPKLSB, MVT::v8i16);
return Result;
}
@@ -3860,10 +3860,10 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(SDNode *N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v4i32 249:iPTR, VRRC:v4f32:$vB, (imm:i32):$UIMM)
+ // Pattern: (intrinsic_wo_chain:v4i32 250:iPTR, VRRC:v4f32:$vB, (imm:i32):$UIMM)
// Emits: (VCTSXS:v4i32 (imm:i32):$UIMM, VRRC:v4f32:$vB)
// Pattern complexity = 11 cost = 1 size = 0
- if (CN1 == INT64_C(249)) {
+ if (CN1 == INT64_C(250)) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
if (N2.getNode()->getOpcode() == ISD::Constant) {
@@ -3872,10 +3872,10 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(SDNode *N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4i32 250:iPTR, VRRC:v4f32:$vB, (imm:i32):$UIMM)
+ // Pattern: (intrinsic_wo_chain:v4i32 251:iPTR, VRRC:v4f32:$vB, (imm:i32):$UIMM)
// Emits: (VCTUXS:v4i32 (imm:i32):$UIMM, VRRC:v4f32:$vB)
// Pattern complexity = 11 cost = 1 size = 0
- if (CN1 == INT64_C(250)) {
+ if (CN1 == INT64_C(251)) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
if (N2.getNode()->getOpcode() == ISD::Constant) {
@@ -3884,330 +3884,330 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(SDNode *N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4i32 286:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB, VRRC:v16i8:$vC)
+ // Pattern: (intrinsic_wo_chain:v4i32 287:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB, VRRC:v16i8:$vC)
// Emits: (VPERM:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB, VRRC:v16i8:$vC)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(286)) {
+ if (CN1 == INT64_C(287)) {
SDNode *Result = Emit_52(N, PPC::VPERM, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 303:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB, VRRC:v4i32:$vC)
+ // Pattern: (intrinsic_wo_chain:v4i32 304:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB, VRRC:v4i32:$vC)
// Emits: (VSEL:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB, VRRC:v4i32:$vC)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(303)) {
+ if (CN1 == INT64_C(304)) {
SDNode *Result = Emit_52(N, PPC::VSEL, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 208:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 209:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Emits: (VADDCUW:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(208)) {
+ if (CN1 == INT64_C(209)) {
SDNode *Result = Emit_51(N, PPC::VADDCUW, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 211:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 212:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Emits: (VADDSWS:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(211)) {
+ if (CN1 == INT64_C(212)) {
SDNode *Result = Emit_51(N, PPC::VADDSWS, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 214:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 215:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Emits: (VADDUWS:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(214)) {
+ if (CN1 == INT64_C(215)) {
SDNode *Result = Emit_51(N, PPC::VADDUWS, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 217:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 218:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Emits: (VAVGSW:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(217)) {
+ if (CN1 == INT64_C(218)) {
SDNode *Result = Emit_51(N, PPC::VAVGSW, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 220:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 221:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Emits: (VAVGUW:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(220)) {
+ if (CN1 == INT64_C(221)) {
SDNode *Result = Emit_51(N, PPC::VAVGUW, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 257:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 258:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Emits: (VMAXSW:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(257)) {
+ if (CN1 == INT64_C(258)) {
SDNode *Result = Emit_51(N, PPC::VMAXSW, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 260:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 261:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Emits: (VMAXUW:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(260)) {
+ if (CN1 == INT64_C(261)) {
SDNode *Result = Emit_51(N, PPC::VMAXUW, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 266:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 267:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Emits: (VMINSW:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(266)) {
+ if (CN1 == INT64_C(267)) {
SDNode *Result = Emit_51(N, PPC::VMINSW, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 269:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 270:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Emits: (VMINUW:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(269)) {
+ if (CN1 == INT64_C(270)) {
SDNode *Result = Emit_51(N, PPC::VMINUW, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 271:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB, VRRC:v4i32:$vC)
+ // Pattern: (intrinsic_wo_chain:v4i32 272:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB, VRRC:v4i32:$vC)
// Emits: (VMSUMMBM:v4i32 VRRC:v16i8:$vA, VRRC:v16i8:$vB, VRRC:v4i32:$vC)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(271)) {
+ if (CN1 == INT64_C(272)) {
SDNode *Result = Emit_52(N, PPC::VMSUMMBM, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 272:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v4i32:$vC)
+ // Pattern: (intrinsic_wo_chain:v4i32 273:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v4i32:$vC)
// Emits: (VMSUMSHM:v4i32 VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v4i32:$vC)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(272)) {
+ if (CN1 == INT64_C(273)) {
SDNode *Result = Emit_52(N, PPC::VMSUMSHM, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 273:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v4i32:$vC)
+ // Pattern: (intrinsic_wo_chain:v4i32 274:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v4i32:$vC)
// Emits: (VMSUMSHS:v4i32 VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v4i32:$vC)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(273)) {
+ if (CN1 == INT64_C(274)) {
SDNode *Result = Emit_52(N, PPC::VMSUMSHS, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 274:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB, VRRC:v4i32:$vC)
+ // Pattern: (intrinsic_wo_chain:v4i32 275:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB, VRRC:v4i32:$vC)
// Emits: (VMSUMUBM:v4i32 VRRC:v16i8:$vA, VRRC:v16i8:$vB, VRRC:v4i32:$vC)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(274)) {
+ if (CN1 == INT64_C(275)) {
SDNode *Result = Emit_52(N, PPC::VMSUMUBM, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 275:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v4i32:$vC)
+ // Pattern: (intrinsic_wo_chain:v4i32 276:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v4i32:$vC)
// Emits: (VMSUMUHM:v4i32 VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v4i32:$vC)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(275)) {
+ if (CN1 == INT64_C(276)) {
SDNode *Result = Emit_52(N, PPC::VMSUMUHM, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 276:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v4i32:$vC)
+ // Pattern: (intrinsic_wo_chain:v4i32 277:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v4i32:$vC)
// Emits: (VMSUMUHS:v4i32 VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v4i32:$vC)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(276)) {
+ if (CN1 == INT64_C(277)) {
SDNode *Result = Emit_52(N, PPC::VMSUMUHS, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 278:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 279:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Emits: (VMULESH:v4i32 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(278)) {
+ if (CN1 == INT64_C(279)) {
SDNode *Result = Emit_51(N, PPC::VMULESH, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 280:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 281:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Emits: (VMULEUH:v4i32 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(280)) {
+ if (CN1 == INT64_C(281)) {
SDNode *Result = Emit_51(N, PPC::VMULEUH, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 282:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 283:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Emits: (VMULOSH:v4i32 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(282)) {
+ if (CN1 == INT64_C(283)) {
SDNode *Result = Emit_51(N, PPC::VMULOSH, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 284:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 285:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Emits: (VMULOUH:v4i32 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(284)) {
+ if (CN1 == INT64_C(285)) {
SDNode *Result = Emit_51(N, PPC::VMULOUH, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 317:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 318:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Emits: (VSUBCUW:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(317)) {
+ if (CN1 == INT64_C(318)) {
SDNode *Result = Emit_51(N, PPC::VSUBCUW, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 320:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 321:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Emits: (VSUBSWS:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(320)) {
+ if (CN1 == INT64_C(321)) {
SDNode *Result = Emit_51(N, PPC::VSUBSWS, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 323:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 324:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Emits: (VSUBUWS:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(323)) {
+ if (CN1 == INT64_C(324)) {
SDNode *Result = Emit_51(N, PPC::VSUBUWS, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 328:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 329:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Emits: (VSUMSWS:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(328)) {
+ if (CN1 == INT64_C(329)) {
SDNode *Result = Emit_51(N, PPC::VSUMSWS, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 324:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 325:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Emits: (VSUM2SWS:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(324)) {
+ if (CN1 == INT64_C(325)) {
SDNode *Result = Emit_51(N, PPC::VSUM2SWS, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 325:iPTR, VRRC:v16i8:$vA, VRRC:v4i32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 326:iPTR, VRRC:v16i8:$vA, VRRC:v4i32:$vB)
// Emits: (VSUM4SBS:v4i32 VRRC:v16i8:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(325)) {
+ if (CN1 == INT64_C(326)) {
SDNode *Result = Emit_51(N, PPC::VSUM4SBS, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 326:iPTR, VRRC:v8i16:$vA, VRRC:v4i32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 327:iPTR, VRRC:v8i16:$vA, VRRC:v4i32:$vB)
// Emits: (VSUM4SHS:v4i32 VRRC:v8i16:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(326)) {
+ if (CN1 == INT64_C(327)) {
SDNode *Result = Emit_51(N, PPC::VSUM4SHS, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 327:iPTR, VRRC:v16i8:$vA, VRRC:v4i32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 328:iPTR, VRRC:v16i8:$vA, VRRC:v4i32:$vB)
// Emits: (VSUM4UBS:v4i32 VRRC:v16i8:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(327)) {
+ if (CN1 == INT64_C(328)) {
SDNode *Result = Emit_51(N, PPC::VSUM4UBS, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 301:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 302:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Emits: (VRLW:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(301)) {
+ if (CN1 == INT64_C(302)) {
SDNode *Result = Emit_51(N, PPC::VRLW, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 304:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 305:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Emits: (VSL:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(304)) {
+ if (CN1 == INT64_C(305)) {
SDNode *Result = Emit_51(N, PPC::VSL, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 307:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 308:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Emits: (VSLO:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(307)) {
+ if (CN1 == INT64_C(308)) {
SDNode *Result = Emit_51(N, PPC::VSLO, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 308:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 309:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Emits: (VSLW:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(308)) {
+ if (CN1 == INT64_C(309)) {
SDNode *Result = Emit_51(N, PPC::VSLW, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 309:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 310:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Emits: (VSR:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(309)) {
+ if (CN1 == INT64_C(310)) {
SDNode *Result = Emit_51(N, PPC::VSR, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 315:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 316:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Emits: (VSRO:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(315)) {
+ if (CN1 == INT64_C(316)) {
SDNode *Result = Emit_51(N, PPC::VSRO, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 312:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 313:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Emits: (VSRAW:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(312)) {
+ if (CN1 == INT64_C(313)) {
SDNode *Result = Emit_51(N, PPC::VSRAW, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 316:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 317:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Emits: (VSRW:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(316)) {
+ if (CN1 == INT64_C(317)) {
SDNode *Result = Emit_51(N, PPC::VSRW, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 329:iPTR, VRRC:v8i16:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 330:iPTR, VRRC:v8i16:$vB)
// Emits: (VUPKHPX:v4i32 VRRC:v8i16:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(329)) {
+ if (CN1 == INT64_C(330)) {
SDNode *Result = Emit_53(N, PPC::VUPKHPX, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 331:iPTR, VRRC:v8i16:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 332:iPTR, VRRC:v8i16:$vB)
// Emits: (VUPKHSH:v4i32 VRRC:v8i16:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(331)) {
+ if (CN1 == INT64_C(332)) {
SDNode *Result = Emit_53(N, PPC::VUPKHSH, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 332:iPTR, VRRC:v8i16:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 333:iPTR, VRRC:v8i16:$vB)
// Emits: (VUPKLPX:v4i32 VRRC:v8i16:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(332)) {
+ if (CN1 == INT64_C(333)) {
SDNode *Result = Emit_53(N, PPC::VUPKLPX, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 334:iPTR, VRRC:v8i16:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 335:iPTR, VRRC:v8i16:$vB)
// Emits: (VUPKLSH:v4i32 VRRC:v8i16:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(334)) {
+ if (CN1 == INT64_C(335)) {
SDNode *Result = Emit_53(N, PPC::VUPKLSH, MVT::v4i32);
return Result;
}
@@ -4223,10 +4223,10 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(SDNode *N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v4f32 221:iPTR, VRRC:v4i32:$vB, (imm:i32):$UIMM)
+ // Pattern: (intrinsic_wo_chain:v4f32 222:iPTR, VRRC:v4i32:$vB, (imm:i32):$UIMM)
// Emits: (VCFSX:v4f32 (imm:i32):$UIMM, VRRC:v4i32:$vB)
// Pattern complexity = 11 cost = 1 size = 0
- if (CN1 == INT64_C(221)) {
+ if (CN1 == INT64_C(222)) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
if (N2.getNode()->getOpcode() == ISD::Constant) {
@@ -4235,10 +4235,10 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(SDNode *N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4f32 222:iPTR, VRRC:v4i32:$vB, (imm:i32):$UIMM)
+ // Pattern: (intrinsic_wo_chain:v4f32 223:iPTR, VRRC:v4i32:$vB, (imm:i32):$UIMM)
// Emits: (VCFUX:v4f32 (imm:i32):$UIMM, VRRC:v4i32:$vB)
// Pattern complexity = 11 cost = 1 size = 0
- if (CN1 == INT64_C(222)) {
+ if (CN1 == INT64_C(223)) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
if (N2.getNode()->getOpcode() == ISD::Constant) {
@@ -4247,98 +4247,98 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(SDNode *N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4f32 251:iPTR, VRRC:v4f32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4f32 252:iPTR, VRRC:v4f32:$vB)
// Emits: (VEXPTEFP:v4f32 VRRC:v4f32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(251)) {
+ if (CN1 == INT64_C(252)) {
SDNode *Result = Emit_53(N, PPC::VEXPTEFP, MVT::v4f32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4f32 252:iPTR, VRRC:v4f32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4f32 253:iPTR, VRRC:v4f32:$vB)
// Emits: (VLOGEFP:v4f32 VRRC:v4f32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(252)) {
+ if (CN1 == INT64_C(253)) {
SDNode *Result = Emit_53(N, PPC::VLOGEFP, MVT::v4f32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4f32 254:iPTR, VRRC:v4f32:$vA, VRRC:v4f32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4f32 255:iPTR, VRRC:v4f32:$vA, VRRC:v4f32:$vB)
// Emits: (VMAXFP:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(254)) {
+ if (CN1 == INT64_C(255)) {
SDNode *Result = Emit_51(N, PPC::VMAXFP, MVT::v4f32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4f32 263:iPTR, VRRC:v4f32:$vA, VRRC:v4f32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4f32 264:iPTR, VRRC:v4f32:$vA, VRRC:v4f32:$vB)
// Emits: (VMINFP:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(263)) {
+ if (CN1 == INT64_C(264)) {
SDNode *Result = Emit_51(N, PPC::VMINFP, MVT::v4f32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4f32 294:iPTR, VRRC:v4f32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4f32 295:iPTR, VRRC:v4f32:$vB)
// Emits: (VREFP:v4f32 VRRC:v4f32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(294)) {
+ if (CN1 == INT64_C(295)) {
SDNode *Result = Emit_53(N, PPC::VREFP, MVT::v4f32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4f32 295:iPTR, VRRC:v4f32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4f32 296:iPTR, VRRC:v4f32:$vB)
// Emits: (VRFIM:v4f32 VRRC:v4f32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(295)) {
+ if (CN1 == INT64_C(296)) {
SDNode *Result = Emit_53(N, PPC::VRFIM, MVT::v4f32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4f32 296:iPTR, VRRC:v4f32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4f32 297:iPTR, VRRC:v4f32:$vB)
// Emits: (VRFIN:v4f32 VRRC:v4f32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(296)) {
+ if (CN1 == INT64_C(297)) {
SDNode *Result = Emit_53(N, PPC::VRFIN, MVT::v4f32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4f32 297:iPTR, VRRC:v4f32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4f32 298:iPTR, VRRC:v4f32:$vB)
// Emits: (VRFIP:v4f32 VRRC:v4f32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(297)) {
+ if (CN1 == INT64_C(298)) {
SDNode *Result = Emit_53(N, PPC::VRFIP, MVT::v4f32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4f32 298:iPTR, VRRC:v4f32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4f32 299:iPTR, VRRC:v4f32:$vB)
// Emits: (VRFIZ:v4f32 VRRC:v4f32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(298)) {
+ if (CN1 == INT64_C(299)) {
SDNode *Result = Emit_53(N, PPC::VRFIZ, MVT::v4f32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4f32 302:iPTR, VRRC:v4f32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4f32 303:iPTR, VRRC:v4f32:$vB)
// Emits: (VRSQRTEFP:v4f32 VRRC:v4f32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(302)) {
+ if (CN1 == INT64_C(303)) {
SDNode *Result = Emit_53(N, PPC::VRSQRTEFP, MVT::v4f32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4f32 253:iPTR, VRRC:v4f32:$A, VRRC:v4f32:$B, VRRC:v4f32:$C)
+ // Pattern: (intrinsic_wo_chain:v4f32 254:iPTR, VRRC:v4f32:$A, VRRC:v4f32:$B, VRRC:v4f32:$C)
// Emits: (VMADDFP:v4f32 VRRC:v16i8:$A, VRRC:v16i8:$B, VRRC:v16i8:$C)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(253)) {
+ if (CN1 == INT64_C(254)) {
SDNode *Result = Emit_52(N, PPC::VMADDFP, MVT::v4f32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4f32 285:iPTR, VRRC:v4f32:$A, VRRC:v4f32:$B, VRRC:v4f32:$C)
+ // Pattern: (intrinsic_wo_chain:v4f32 286:iPTR, VRRC:v4f32:$A, VRRC:v4f32:$B, VRRC:v4f32:$C)
// Emits: (VNMSUBFP:v4f32 VRRC:v16i8:$A, VRRC:v16i8:$B, VRRC:v16i8:$C)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(285)) {
+ if (CN1 == INT64_C(286)) {
SDNode *Result = Emit_52(N, PPC::VNMSUBFP, MVT::v4f32);
return Result;
}
@@ -4360,7 +4360,7 @@ SDNode *Select_ISD_INTRINSIC_W_CHAIN_v16i8(SDNode *N) {
ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(194)) {
+ if (CN1 == INT64_C(195)) {
SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
@@ -4387,10 +4387,10 @@ SDNode *Select_ISD_INTRINSIC_W_CHAIN_v8i16(SDNode *N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_w_chain:v8i16 195:iPTR, xoaddr:iPTR:$src)
+ // Pattern: (intrinsic_w_chain:v8i16 196:iPTR, xoaddr:iPTR:$src)
// Emits: (LVEHX:v8i16 xoaddr:iPTR:$src)
// Pattern complexity = 17 cost = 1 size = 0
- if (CN1 == INT64_C(195)) {
+ if (CN1 == INT64_C(196)) {
SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
@@ -4400,10 +4400,10 @@ SDNode *Select_ISD_INTRINSIC_W_CHAIN_v8i16(SDNode *N) {
}
}
- // Pattern: (intrinsic_w_chain:v8i16 201:iPTR)
+ // Pattern: (intrinsic_w_chain:v8i16 202:iPTR)
// Emits: (MFVSCR:v8i16)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(201)) {
+ if (CN1 == INT64_C(202)) {
SDNode *Result = Emit_56(N, PPC::MFVSCR, MVT::v8i16);
return Result;
}
@@ -4420,10 +4420,10 @@ SDNode *Select_ISD_INTRINSIC_W_CHAIN_v4i32(SDNode *N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_w_chain:v4i32 196:iPTR, xoaddr:iPTR:$src)
+ // Pattern: (intrinsic_w_chain:v4i32 197:iPTR, xoaddr:iPTR:$src)
// Emits: (LVEWX:v4i32 xoaddr:iPTR:$src)
// Pattern complexity = 17 cost = 1 size = 0
- if (CN1 == INT64_C(196)) {
+ if (CN1 == INT64_C(197)) {
SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
@@ -4433,10 +4433,10 @@ SDNode *Select_ISD_INTRINSIC_W_CHAIN_v4i32(SDNode *N) {
}
}
- // Pattern: (intrinsic_w_chain:v4i32 199:iPTR, xoaddr:iPTR:$src)
+ // Pattern: (intrinsic_w_chain:v4i32 200:iPTR, xoaddr:iPTR:$src)
// Emits: (LVX:v4i32 xoaddr:iPTR:$src)
// Pattern complexity = 17 cost = 1 size = 0
- if (CN1 == INT64_C(199)) {
+ if (CN1 == INT64_C(200)) {
SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
@@ -4446,10 +4446,10 @@ SDNode *Select_ISD_INTRINSIC_W_CHAIN_v4i32(SDNode *N) {
}
}
- // Pattern: (intrinsic_w_chain:v4i32 200:iPTR, xoaddr:iPTR:$src)
+ // Pattern: (intrinsic_w_chain:v4i32 201:iPTR, xoaddr:iPTR:$src)
// Emits: (LVXL:v4i32 xoaddr:iPTR:$src)
// Pattern complexity = 17 cost = 1 size = 0
- if (CN1 == INT64_C(200)) {
+ if (CN1 == INT64_C(201)) {
SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
diff --git a/libclamav/c++/PPCGenInstrInfo.inc b/libclamav/c++/PPCGenInstrInfo.inc
index 0d5df7d..285bce1 100644
--- a/libclamav/c++/PPCGenInstrInfo.inc
+++ b/libclamav/c++/PPCGenInstrInfo.inc
@@ -132,7 +132,7 @@ static const TargetInstrDesc PPCInsts[] = {
{ 8, 1, 1, 52, "IMPLICIT_DEF", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0, NULL, NULL, NULL, OperandInfo8 }, // Inst #8 = IMPLICIT_DEF
{ 9, 4, 1, 52, "SUBREG_TO_REG", 0, 0, NULL, NULL, NULL, OperandInfo24 }, // Inst #9 = SUBREG_TO_REG
{ 10, 3, 1, 52, "COPY_TO_REGCLASS", 0|(1<<TID::CheapAsAMove), 0, NULL, NULL, NULL, OperandInfo20 }, // Inst #10 = COPY_TO_REGCLASS
- { 11, 0, 0, 52, "DEBUG_VALUE", 0|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::CheapAsAMove), 0, NULL, NULL, NULL, 0 }, // Inst #11 = DEBUG_VALUE
+ { 11, 0, 0, 52, "DBG_VALUE", 0|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::CheapAsAMove), 0, NULL, NULL, NULL, 0 }, // Inst #11 = DBG_VALUE
{ 12, 3, 1, 14, "ADD4", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #12 = ADD4
{ 13, 3, 1, 14, "ADD8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #13 = ADD8
{ 14, 3, 1, 14, "ADDC", 0, 0|(1<<2)|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #14 = ADDC
diff --git a/libclamav/c++/PPCGenInstrNames.inc b/libclamav/c++/PPCGenInstrNames.inc
index 06e0e36..792e4e5 100644
--- a/libclamav/c++/PPCGenInstrNames.inc
+++ b/libclamav/c++/PPCGenInstrNames.inc
@@ -21,7 +21,7 @@ namespace PPC {
IMPLICIT_DEF = 8,
SUBREG_TO_REG = 9,
COPY_TO_REGCLASS = 10,
- DEBUG_VALUE = 11,
+ DBG_VALUE = 11,
ADD4 = 12,
ADD8 = 13,
ADDC = 14,
diff --git a/libclamav/c++/X86GenAsmMatcher.inc b/libclamav/c++/X86GenAsmMatcher.inc
index da18185..5bc8928 100644
--- a/libclamav/c++/X86GenAsmMatcher.inc
+++ b/libclamav/c++/X86GenAsmMatcher.inc
@@ -6,7 +6,7 @@
//
//===----------------------------------------------------------------------===//
-static unsigned MatchRegisterName(const StringRef &Name) {
+static unsigned MatchRegisterName(StringRef Name) {
switch (Name.size()) {
default: break;
case 2: // 25 strings to match.
@@ -604,50 +604,48 @@ static unsigned MatchRegisterName(const StringRef &Name) {
enum ConversionKind {
Convert,
- Convert_Reg1_1Imp,
- Convert_Imm1_1,
- Convert_Mem5_1,
- Convert_Reg1_1,
- Convert_Reg1_2_ImpReg1_1,
- Convert_Mem5_2_Reg1_1,
- Convert_Reg1_2_ImpImm1_1,
- Convert_Mem5_2_Imm1_1,
- Convert_Reg1_2_ImpMem5_1,
- Convert_Reg1_2_ImpImmSExt81_1,
- Convert_Mem5_2_ImmSExt81_1,
- Convert_Reg1_2_Reg1_1,
- Convert_Reg1_2_Mem5_1,
- Convert_Reg1_2_ImmSExt81_1,
- Convert_Reg1_2,
- Convert_Mem5_2,
- Convert_Reg1_2_Imm1_1,
- Convert_ImpReg1_2_Reg1_1,
- Convert_ImpReg1_2_Mem5_1,
- Convert_Imm1_1_Imm1_2,
- Convert_ImmSExt81_1,
- Convert_Reg1_2_Mem4_1,
- Convert_Imm1_2,
- Convert_ImmSExt81_2,
- Convert_Reg1_2Imp,
- Convert_Mem5_2ImpImpImpImpImp,
- Convert_Mem5_2_ImpImpImpImpImpImm1_1,
- Convert_ImpReg1_1_Reg1_2,
- Convert_ImpReg1_1_Mem5_2,
- Convert_Reg1_3_ImpReg1_2_ImmSExt81_1,
- Convert_Reg1_3_ImpMem5_2_ImmSExt81_1,
- Convert_Reg1_3_ImpReg1_2,
- Convert_Reg1_3_ImpMem5_2,
- Convert_Reg1_3_Reg1_2_ImmSExt81_1,
- Convert_Mem5_3_Reg1_2_ImmSExt81_1,
- Convert_Reg1_3_Mem5_2_ImmSExt81_1,
- Convert_Reg1_3_Reg1_2_Imm1_1,
- Convert_Reg1_3_Mem5_2_Imm1_1,
- Convert_Reg1_3_ImpReg1_2_Imm1_1,
- Convert_Reg1_3_ImpMem5_2_Imm1_1,
- Convert_Mem5_3_Reg1_2,
- Convert_Mem5_3_Reg1_2_Imm1_1,
- Convert_Reg1_4_ImpReg1_3_Imm1_1,
- Convert_Reg1_4_ImpMem5_3_Imm1_1,
+ Convert__Reg1_1__Tie0,
+ Convert__Imm1_1,
+ Convert__AbsMem1_1,
+ Convert__Mem5_1,
+ Convert__Reg1_1,
+ Convert__Reg1_2__Tie0__Reg1_1,
+ Convert__Mem5_2__Reg1_1,
+ Convert__Reg1_2__Tie0__Imm1_1,
+ Convert__Mem5_2__Imm1_1,
+ Convert__Reg1_2__Tie0__Mem5_1,
+ Convert__Reg1_2__Tie0__ImmSExt81_1,
+ Convert__Mem5_2__ImmSExt81_1,
+ Convert__Reg1_2__Reg1_1,
+ Convert__Reg1_2__Mem5_1,
+ Convert__Reg1_2__ImmSExt81_1,
+ Convert__Reg1_2,
+ Convert__Mem5_2,
+ Convert__Reg1_2__Imm1_1,
+ Convert__Imm1_1__Imm1_2,
+ Convert__ImmSExt81_1,
+ Convert__Reg1_2__NoSegMem4_1,
+ Convert__Reg1_2__Mem4_1,
+ Convert__AbsMem1_2,
+ Convert__ImmSExt81_2,
+ Convert__Reg1_2__Tie0,
+ Convert__Reg1_1__Tie0__Reg1_2,
+ Convert__Reg1_1__Tie0__Mem5_2,
+ Convert__Reg1_3__Tie0__Reg1_2__ImmSExt81_1,
+ Convert__Reg1_3__Tie0__Mem5_2__ImmSExt81_1,
+ Convert__Reg1_3__Tie0__Reg1_2,
+ Convert__Reg1_3__Tie0__Mem5_2,
+ Convert__Reg1_3__Reg1_2__ImmSExt81_1,
+ Convert__Mem5_3__Reg1_2__ImmSExt81_1,
+ Convert__Reg1_3__Mem5_2__ImmSExt81_1,
+ Convert__Reg1_3__Reg1_2__Imm1_1,
+ Convert__Reg1_3__Mem5_2__Imm1_1,
+ Convert__Reg1_3__Tie0__Reg1_2__Imm1_1,
+ Convert__Reg1_3__Tie0__Mem5_2__Imm1_1,
+ Convert__Mem5_3__Reg1_2,
+ Convert__Mem5_3__Reg1_2__Imm1_1,
+ Convert__Reg1_4__Tie0__Reg1_3__Imm1_1,
+ Convert__Reg1_4__Tie0__Mem5_3__Imm1_1,
NumConversionVariants
};
@@ -658,208 +656,188 @@ static bool ConvertToMCInst(ConversionKind Kind, MCInst &Inst, unsigned Opcode,
default:
case Convert:
break;
- case Convert_Reg1_1Imp:
+ case Convert__Reg1_1__Tie0:
((X86Operand*)Operands[1])->addRegOperands(Inst, 1);
- Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(Inst.getOperand(0));
break;
- case Convert_Imm1_1:
+ case Convert__Imm1_1:
((X86Operand*)Operands[1])->addImmOperands(Inst, 1);
break;
- case Convert_Mem5_1:
+ case Convert__AbsMem1_1:
+ ((X86Operand*)Operands[1])->addAbsMemOperands(Inst, 1);
+ break;
+ case Convert__Mem5_1:
((X86Operand*)Operands[1])->addMemOperands(Inst, 5);
break;
- case Convert_Reg1_1:
+ case Convert__Reg1_1:
((X86Operand*)Operands[1])->addRegOperands(Inst, 1);
break;
- case Convert_Reg1_2_ImpReg1_1:
+ case Convert__Reg1_2__Tie0__Reg1_1:
((X86Operand*)Operands[2])->addRegOperands(Inst, 1);
- Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(Inst.getOperand(0));
((X86Operand*)Operands[1])->addRegOperands(Inst, 1);
break;
- case Convert_Mem5_2_Reg1_1:
+ case Convert__Mem5_2__Reg1_1:
((X86Operand*)Operands[2])->addMemOperands(Inst, 5);
((X86Operand*)Operands[1])->addRegOperands(Inst, 1);
break;
- case Convert_Reg1_2_ImpImm1_1:
+ case Convert__Reg1_2__Tie0__Imm1_1:
((X86Operand*)Operands[2])->addRegOperands(Inst, 1);
- Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(Inst.getOperand(0));
((X86Operand*)Operands[1])->addImmOperands(Inst, 1);
break;
- case Convert_Mem5_2_Imm1_1:
+ case Convert__Mem5_2__Imm1_1:
((X86Operand*)Operands[2])->addMemOperands(Inst, 5);
((X86Operand*)Operands[1])->addImmOperands(Inst, 1);
break;
- case Convert_Reg1_2_ImpMem5_1:
+ case Convert__Reg1_2__Tie0__Mem5_1:
((X86Operand*)Operands[2])->addRegOperands(Inst, 1);
- Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(Inst.getOperand(0));
((X86Operand*)Operands[1])->addMemOperands(Inst, 5);
break;
- case Convert_Reg1_2_ImpImmSExt81_1:
+ case Convert__Reg1_2__Tie0__ImmSExt81_1:
((X86Operand*)Operands[2])->addRegOperands(Inst, 1);
- Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(Inst.getOperand(0));
((X86Operand*)Operands[1])->addImmSExt8Operands(Inst, 1);
break;
- case Convert_Mem5_2_ImmSExt81_1:
+ case Convert__Mem5_2__ImmSExt81_1:
((X86Operand*)Operands[2])->addMemOperands(Inst, 5);
((X86Operand*)Operands[1])->addImmSExt8Operands(Inst, 1);
break;
- case Convert_Reg1_2_Reg1_1:
+ case Convert__Reg1_2__Reg1_1:
((X86Operand*)Operands[2])->addRegOperands(Inst, 1);
((X86Operand*)Operands[1])->addRegOperands(Inst, 1);
break;
- case Convert_Reg1_2_Mem5_1:
+ case Convert__Reg1_2__Mem5_1:
((X86Operand*)Operands[2])->addRegOperands(Inst, 1);
((X86Operand*)Operands[1])->addMemOperands(Inst, 5);
break;
- case Convert_Reg1_2_ImmSExt81_1:
+ case Convert__Reg1_2__ImmSExt81_1:
((X86Operand*)Operands[2])->addRegOperands(Inst, 1);
((X86Operand*)Operands[1])->addImmSExt8Operands(Inst, 1);
break;
- case Convert_Reg1_2:
+ case Convert__Reg1_2:
((X86Operand*)Operands[2])->addRegOperands(Inst, 1);
break;
- case Convert_Mem5_2:
+ case Convert__Mem5_2:
((X86Operand*)Operands[2])->addMemOperands(Inst, 5);
break;
- case Convert_Reg1_2_Imm1_1:
+ case Convert__Reg1_2__Imm1_1:
((X86Operand*)Operands[2])->addRegOperands(Inst, 1);
((X86Operand*)Operands[1])->addImmOperands(Inst, 1);
break;
- case Convert_ImpReg1_2_Reg1_1:
- Inst.addOperand(MCOperand::CreateReg(0));
- ((X86Operand*)Operands[2])->addRegOperands(Inst, 1);
- ((X86Operand*)Operands[1])->addRegOperands(Inst, 1);
- break;
- case Convert_ImpReg1_2_Mem5_1:
- Inst.addOperand(MCOperand::CreateReg(0));
- ((X86Operand*)Operands[2])->addRegOperands(Inst, 1);
- ((X86Operand*)Operands[1])->addMemOperands(Inst, 5);
- break;
- case Convert_Imm1_1_Imm1_2:
+ case Convert__Imm1_1__Imm1_2:
((X86Operand*)Operands[1])->addImmOperands(Inst, 1);
((X86Operand*)Operands[2])->addImmOperands(Inst, 1);
break;
- case Convert_ImmSExt81_1:
+ case Convert__ImmSExt81_1:
((X86Operand*)Operands[1])->addImmSExt8Operands(Inst, 1);
break;
- case Convert_Reg1_2_Mem4_1:
+ case Convert__Reg1_2__NoSegMem4_1:
+ ((X86Operand*)Operands[2])->addRegOperands(Inst, 1);
+ ((X86Operand*)Operands[1])->addNoSegMemOperands(Inst, 4);
+ break;
+ case Convert__Reg1_2__Mem4_1:
((X86Operand*)Operands[2])->addRegOperands(Inst, 1);
((X86Operand*)Operands[1])->addMemOperands(Inst, 4);
break;
- case Convert_Imm1_2:
- ((X86Operand*)Operands[2])->addImmOperands(Inst, 1);
+ case Convert__AbsMem1_2:
+ ((X86Operand*)Operands[2])->addAbsMemOperands(Inst, 1);
break;
- case Convert_ImmSExt81_2:
+ case Convert__ImmSExt81_2:
((X86Operand*)Operands[2])->addImmSExt8Operands(Inst, 1);
break;
- case Convert_Reg1_2Imp:
+ case Convert__Reg1_2__Tie0:
((X86Operand*)Operands[2])->addRegOperands(Inst, 1);
- Inst.addOperand(MCOperand::CreateReg(0));
- break;
- case Convert_Mem5_2ImpImpImpImpImp:
- ((X86Operand*)Operands[2])->addMemOperands(Inst, 5);
- Inst.addOperand(MCOperand::CreateReg(0));
- Inst.addOperand(MCOperand::CreateReg(0));
- Inst.addOperand(MCOperand::CreateReg(0));
- Inst.addOperand(MCOperand::CreateReg(0));
- Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(Inst.getOperand(0));
break;
- case Convert_Mem5_2_ImpImpImpImpImpImm1_1:
- ((X86Operand*)Operands[2])->addMemOperands(Inst, 5);
- Inst.addOperand(MCOperand::CreateReg(0));
- Inst.addOperand(MCOperand::CreateReg(0));
- Inst.addOperand(MCOperand::CreateReg(0));
- Inst.addOperand(MCOperand::CreateReg(0));
- Inst.addOperand(MCOperand::CreateReg(0));
- ((X86Operand*)Operands[1])->addImmOperands(Inst, 1);
- break;
- case Convert_ImpReg1_1_Reg1_2:
- Inst.addOperand(MCOperand::CreateReg(0));
+ case Convert__Reg1_1__Tie0__Reg1_2:
((X86Operand*)Operands[1])->addRegOperands(Inst, 1);
+ Inst.addOperand(Inst.getOperand(0));
((X86Operand*)Operands[2])->addRegOperands(Inst, 1);
break;
- case Convert_ImpReg1_1_Mem5_2:
- Inst.addOperand(MCOperand::CreateReg(0));
+ case Convert__Reg1_1__Tie0__Mem5_2:
((X86Operand*)Operands[1])->addRegOperands(Inst, 1);
+ Inst.addOperand(Inst.getOperand(0));
((X86Operand*)Operands[2])->addMemOperands(Inst, 5);
break;
- case Convert_Reg1_3_ImpReg1_2_ImmSExt81_1:
+ case Convert__Reg1_3__Tie0__Reg1_2__ImmSExt81_1:
((X86Operand*)Operands[3])->addRegOperands(Inst, 1);
- Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(Inst.getOperand(0));
((X86Operand*)Operands[2])->addRegOperands(Inst, 1);
((X86Operand*)Operands[1])->addImmSExt8Operands(Inst, 1);
break;
- case Convert_Reg1_3_ImpMem5_2_ImmSExt81_1:
+ case Convert__Reg1_3__Tie0__Mem5_2__ImmSExt81_1:
((X86Operand*)Operands[3])->addRegOperands(Inst, 1);
- Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(Inst.getOperand(0));
((X86Operand*)Operands[2])->addMemOperands(Inst, 5);
((X86Operand*)Operands[1])->addImmSExt8Operands(Inst, 1);
break;
- case Convert_Reg1_3_ImpReg1_2:
+ case Convert__Reg1_3__Tie0__Reg1_2:
((X86Operand*)Operands[3])->addRegOperands(Inst, 1);
- Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(Inst.getOperand(0));
((X86Operand*)Operands[2])->addRegOperands(Inst, 1);
break;
- case Convert_Reg1_3_ImpMem5_2:
+ case Convert__Reg1_3__Tie0__Mem5_2:
((X86Operand*)Operands[3])->addRegOperands(Inst, 1);
- Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(Inst.getOperand(0));
((X86Operand*)Operands[2])->addMemOperands(Inst, 5);
break;
- case Convert_Reg1_3_Reg1_2_ImmSExt81_1:
+ case Convert__Reg1_3__Reg1_2__ImmSExt81_1:
((X86Operand*)Operands[3])->addRegOperands(Inst, 1);
((X86Operand*)Operands[2])->addRegOperands(Inst, 1);
((X86Operand*)Operands[1])->addImmSExt8Operands(Inst, 1);
break;
- case Convert_Mem5_3_Reg1_2_ImmSExt81_1:
+ case Convert__Mem5_3__Reg1_2__ImmSExt81_1:
((X86Operand*)Operands[3])->addMemOperands(Inst, 5);
((X86Operand*)Operands[2])->addRegOperands(Inst, 1);
((X86Operand*)Operands[1])->addImmSExt8Operands(Inst, 1);
break;
- case Convert_Reg1_3_Mem5_2_ImmSExt81_1:
+ case Convert__Reg1_3__Mem5_2__ImmSExt81_1:
((X86Operand*)Operands[3])->addRegOperands(Inst, 1);
((X86Operand*)Operands[2])->addMemOperands(Inst, 5);
((X86Operand*)Operands[1])->addImmSExt8Operands(Inst, 1);
break;
- case Convert_Reg1_3_Reg1_2_Imm1_1:
+ case Convert__Reg1_3__Reg1_2__Imm1_1:
((X86Operand*)Operands[3])->addRegOperands(Inst, 1);
((X86Operand*)Operands[2])->addRegOperands(Inst, 1);
((X86Operand*)Operands[1])->addImmOperands(Inst, 1);
break;
- case Convert_Reg1_3_Mem5_2_Imm1_1:
+ case Convert__Reg1_3__Mem5_2__Imm1_1:
((X86Operand*)Operands[3])->addRegOperands(Inst, 1);
((X86Operand*)Operands[2])->addMemOperands(Inst, 5);
((X86Operand*)Operands[1])->addImmOperands(Inst, 1);
break;
- case Convert_Reg1_3_ImpReg1_2_Imm1_1:
+ case Convert__Reg1_3__Tie0__Reg1_2__Imm1_1:
((X86Operand*)Operands[3])->addRegOperands(Inst, 1);
- Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(Inst.getOperand(0));
((X86Operand*)Operands[2])->addRegOperands(Inst, 1);
((X86Operand*)Operands[1])->addImmOperands(Inst, 1);
break;
- case Convert_Reg1_3_ImpMem5_2_Imm1_1:
+ case Convert__Reg1_3__Tie0__Mem5_2__Imm1_1:
((X86Operand*)Operands[3])->addRegOperands(Inst, 1);
- Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(Inst.getOperand(0));
((X86Operand*)Operands[2])->addMemOperands(Inst, 5);
((X86Operand*)Operands[1])->addImmOperands(Inst, 1);
break;
- case Convert_Mem5_3_Reg1_2:
+ case Convert__Mem5_3__Reg1_2:
((X86Operand*)Operands[3])->addMemOperands(Inst, 5);
((X86Operand*)Operands[2])->addRegOperands(Inst, 1);
break;
- case Convert_Mem5_3_Reg1_2_Imm1_1:
+ case Convert__Mem5_3__Reg1_2__Imm1_1:
((X86Operand*)Operands[3])->addMemOperands(Inst, 5);
((X86Operand*)Operands[2])->addRegOperands(Inst, 1);
((X86Operand*)Operands[1])->addImmOperands(Inst, 1);
break;
- case Convert_Reg1_4_ImpReg1_3_Imm1_1:
+ case Convert__Reg1_4__Tie0__Reg1_3__Imm1_1:
((X86Operand*)Operands[4])->addRegOperands(Inst, 1);
- Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(Inst.getOperand(0));
((X86Operand*)Operands[3])->addRegOperands(Inst, 1);
((X86Operand*)Operands[1])->addImmOperands(Inst, 1);
break;
- case Convert_Reg1_4_ImpMem5_3_Imm1_1:
+ case Convert__Reg1_4__Tie0__Mem5_3__Imm1_1:
((X86Operand*)Operands[4])->addRegOperands(Inst, 1);
- Inst.addOperand(MCOperand::CreateReg(0));
+ Inst.addOperand(Inst.getOperand(0));
((X86Operand*)Operands[3])->addMemOperands(Inst, 5);
((X86Operand*)Operands[1])->addImmOperands(Inst, 1);
break;
@@ -1001,6 +979,7 @@ enum MatchClassKind {
MCK_cpuid, // 'cpuid'
MCK_cqto, // 'cqto'
MCK_crc32, // 'crc32'
+ MCK_cs, // 'cs'
MCK_cvtdq2pd, // 'cvtdq2pd'
MCK_cvtdq2ps, // 'cvtdq2ps'
MCK_cvtpd2dq, // 'cvtpd2dq'
@@ -1043,8 +1022,10 @@ enum MatchClassKind {
MCK_divw, // 'divw'
MCK_dppd, // 'dppd'
MCK_dpps, // 'dpps'
+ MCK_ds, // 'ds'
MCK_emms, // 'emms'
MCK_enter, // 'enter'
+ MCK_es, // 'es'
MCK_extractps, // 'extractps'
MCK_f2xm1, // 'f2xm1'
MCK_fabs, // 'fabs'
@@ -1142,6 +1123,7 @@ enum MatchClassKind {
MCK_fptan, // 'fptan'
MCK_frndint, // 'frndint'
MCK_frstor, // 'frstor'
+ MCK_fs, // 'fs'
MCK_fscale, // 'fscale'
MCK_fsin, // 'fsin'
MCK_fsincos, // 'fsincos'
@@ -1174,6 +1156,7 @@ enum MatchClassKind {
MCK_fxtract, // 'fxtract'
MCK_fyl2x, // 'fyl2x'
MCK_fyl2xp1, // 'fyl2xp1'
+ MCK_gs, // 'gs'
MCK_haddpd, // 'haddpd'
MCK_haddps, // 'haddps'
MCK_hlt, // 'hlt'
@@ -1257,6 +1240,7 @@ enum MatchClassKind {
MCK_ljmpw, // 'ljmpw'
MCK_lldtw, // 'lldtw'
MCK_lmsww, // 'lmsww'
+ MCK_lock, // 'lock'
MCK_lodsb, // 'lodsb'
MCK_lodsl, // 'lodsl'
MCK_lodsq, // 'lodsq'
@@ -1310,14 +1294,17 @@ enum MatchClassKind {
MCK_movntq, // 'movntq'
MCK_movq, // 'movq'
MCK_movq2dq, // 'movq2dq'
+ MCK_movsb, // 'movsb'
MCK_movsbl, // 'movsbl'
MCK_movsbq, // 'movsbq'
MCK_movsbw, // 'movsbw'
MCK_movsd, // 'movsd'
MCK_movshdup, // 'movshdup'
+ MCK_movsl, // 'movsl'
MCK_movsldup, // 'movsldup'
MCK_movslq, // 'movslq'
MCK_movss, // 'movss'
+ MCK_movsw, // 'movsw'
MCK_movswl, // 'movswl'
MCK_movswq, // 'movswq'
MCK_movupd, // 'movupd'
@@ -1516,14 +1503,11 @@ enum MatchClassKind {
MCK_rdmsr, // 'rdmsr'
MCK_rdpmc, // 'rdpmc'
MCK_rdtsc, // 'rdtsc'
- MCK_rep_59_movsb, // 'rep;movsb'
- MCK_rep_59_movsl, // 'rep;movsl'
+ MCK_rdtscp, // 'rdtscp'
+ MCK_rep, // 'rep'
MCK_rep_59_movsq, // 'rep;movsq'
- MCK_rep_59_movsw, // 'rep;movsw'
- MCK_rep_59_stosb, // 'rep;stosb'
- MCK_rep_59_stosl, // 'rep;stosl'
MCK_rep_59_stosq, // 'rep;stosq'
- MCK_rep_59_stosw, // 'rep;stosw'
+ MCK_repne, // 'repne'
MCK_ret, // 'ret'
MCK_rolb, // 'rolb'
MCK_roll, // 'roll'
@@ -1599,6 +1583,9 @@ enum MatchClassKind {
MCK_std, // 'std'
MCK_sti, // 'sti'
MCK_stmxcsr, // 'stmxcsr'
+ MCK_stosb, // 'stosb'
+ MCK_stosl, // 'stosl'
+ MCK_stosw, // 'stosw'
MCK_strw, // 'strw'
MCK_subb, // 'subb'
MCK_subl, // 'subl'
@@ -1608,7 +1595,7 @@ enum MatchClassKind {
MCK_subsd, // 'subsd'
MCK_subss, // 'subss'
MCK_subw, // 'subw'
- MCK_swpgs, // 'swpgs'
+ MCK_swapgs, // 'swapgs'
MCK_syscall, // 'syscall'
MCK_sysenter, // 'sysenter'
MCK_sysexit, // 'sysexit'
@@ -1671,14 +1658,14 @@ enum MatchClassKind {
MCK_GR32_AD, // register class 'GR32_AD'
MCK_GR32_ABCD, // register class 'GR32_ABCD'
MCK_Reg14, // derived register class
- MCK_GR32_NOSP, // register class 'GR32_NOSP'
MCK_GR32_NOREX, // register class 'GR32_NOREX'
+ MCK_GR32_NOSP, // register class 'GR32_NOSP'
MCK_GR32, // register class 'GR32'
MCK_RAX, // register class 'RAX'
MCK_GR64_ABCD, // register class 'GR64_ABCD'
MCK_GR64_NOREX_NOSP, // register class 'GR64_NOREX_NOSP'
- MCK_GR64_NOSP, // register class 'GR64_NOSP'
MCK_GR64_NOREX, // register class 'GR64_NOREX'
+ MCK_GR64_NOSP, // register class 'GR64_NOSP'
MCK_GR64, // register class 'GR64'
MCK_VR64, // register class 'VR64'
MCK_RFP32, // register class 'RFP32,RFP64,RFP80'
@@ -1696,13 +1683,15 @@ enum MatchClassKind {
MCK_CONTROL_REG_64, // register class 'CONTROL_REG_64'
MCK_ImmSExt8, // user defined class 'ImmSExt8AsmOperand'
MCK_Imm, // user defined class 'ImmAsmOperand'
+ MCK_AbsMem, // user defined class 'X86AbsMemAsmOperand'
+ MCK_NoSegMem, // user defined class 'X86NoSegMemAsmOperand'
MCK_Mem, // user defined class 'X86MemAsmOperand'
NumMatchClassKinds
};
}
-static MatchClassKind MatchTokenString(const StringRef &Name) {
+static MatchClassKind MatchTokenString(StringRef Name) {
switch (Name.size()) {
default: break;
case 1: // 3 strings to match.
@@ -1716,9 +1705,29 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
return MCK_3; // "3"
}
break;
- case 2: // 12 strings to match.
+ case 2: // 17 strings to match.
switch (Name[0]) {
default: break;
+ case 'c': // 1 strings to match.
+ if (Name[1] != 's')
+ break;
+ return MCK_cs; // "cs"
+ case 'd': // 1 strings to match.
+ if (Name[1] != 's')
+ break;
+ return MCK_ds; // "ds"
+ case 'e': // 1 strings to match.
+ if (Name[1] != 's')
+ break;
+ return MCK_es; // "es"
+ case 'f': // 1 strings to match.
+ if (Name[1] != 's')
+ break;
+ return MCK_fs; // "fs"
+ case 'g': // 1 strings to match.
+ if (Name[1] != 's')
+ break;
+ return MCK_gs; // "gs"
case 'j': // 8 strings to match.
switch (Name[1]) {
default: break;
@@ -1760,7 +1769,7 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
break;
}
break;
- case 3: // 36 strings to match.
+ case 3: // 37 strings to match.
switch (Name[0]) {
default: break;
case 'b': // 3 strings to match.
@@ -1894,13 +1903,18 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
if (Name.substr(1,2) != "or")
break;
return MCK_por; // "por"
- case 'r': // 2 strings to match.
+ case 'r': // 3 strings to match.
switch (Name[1]) {
default: break;
- case 'e': // 1 strings to match.
- if (Name[2] != 't')
- break;
- return MCK_ret; // "ret"
+ case 'e': // 2 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case 'p': // 1 strings to match.
+ return MCK_rep; // "rep"
+ case 't': // 1 strings to match.
+ return MCK_ret; // "ret"
+ }
+ break;
case 's': // 1 strings to match.
if (Name[2] != 'm')
break;
@@ -1926,7 +1940,7 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
return MCK_ud2; // "ud2"
}
break;
- case 4: // 195 strings to match.
+ case 4: // 196 strings to match.
switch (Name[0]) {
default: break;
case 'a': // 12 strings to match.
@@ -2321,7 +2335,7 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
break;
}
break;
- case 'l': // 28 strings to match.
+ case 'l': // 29 strings to match.
switch (Name[1]) {
default: break;
case 'a': // 4 strings to match.
@@ -2417,10 +2431,19 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
if (Name.substr(2,2) != "dt")
break;
return MCK_lidt; // "lidt"
- case 'o': // 1 strings to match.
- if (Name.substr(2,2) != "op")
- break;
- return MCK_loop; // "loop"
+ case 'o': // 2 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case 'c': // 1 strings to match.
+ if (Name[3] != 'k')
+ break;
+ return MCK_lock; // "lock"
+ case 'o': // 1 strings to match.
+ if (Name[3] != 'p')
+ break;
+ return MCK_loop; // "loop"
+ }
+ break;
case 'r': // 1 strings to match.
if (Name.substr(2,2) != "et")
break;
@@ -2819,7 +2842,7 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
break;
}
break;
- case 5: // 173 strings to match.
+ case 5: // 179 strings to match.
switch (Name[0]) {
default: break;
case 'a': // 6 strings to match.
@@ -3205,7 +3228,7 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
break;
}
break;
- case 'm': // 15 strings to match.
+ case 'm': // 18 strings to match.
switch (Name[1]) {
default: break;
case 'a': // 4 strings to match.
@@ -3258,15 +3281,21 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
break;
}
break;
- case 'o': // 2 strings to match.
+ case 'o': // 5 strings to match.
if (Name.substr(2,2) != "vs")
break;
switch (Name[4]) {
default: break;
+ case 'b': // 1 strings to match.
+ return MCK_movsb; // "movsb"
case 'd': // 1 strings to match.
return MCK_movsd; // "movsd"
+ case 'l': // 1 strings to match.
+ return MCK_movsl; // "movsl"
case 's': // 1 strings to match.
return MCK_movss; // "movss"
+ case 'w': // 1 strings to match.
+ return MCK_movsw; // "movsw"
}
break;
case 'u': // 4 strings to match.
@@ -3454,7 +3483,7 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
break;
}
break;
- case 'r': // 5 strings to match.
+ case 'r': // 6 strings to match.
switch (Name[1]) {
default: break;
case 'c': // 2 strings to match.
@@ -3489,9 +3518,13 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
return MCK_rdtsc; // "rdtsc"
}
break;
+ case 'e': // 1 strings to match.
+ if (Name.substr(2,3) != "pne")
+ break;
+ return MCK_repne; // "repne"
}
break;
- case 's': // 28 strings to match.
+ case 's': // 30 strings to match.
switch (Name[1]) {
default: break;
case 'c': // 4 strings to match.
@@ -3600,6 +3633,19 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
return MCK_smsww; // "smsww"
}
break;
+ case 't': // 3 strings to match.
+ if (Name.substr(2,2) != "os")
+ break;
+ switch (Name[4]) {
+ default: break;
+ case 'b': // 1 strings to match.
+ return MCK_stosb; // "stosb"
+ case 'l': // 1 strings to match.
+ return MCK_stosl; // "stosl"
+ case 'w': // 1 strings to match.
+ return MCK_stosw; // "stosw"
+ }
+ break;
case 'u': // 4 strings to match.
if (Name[2] != 'b')
break;
@@ -3625,10 +3671,6 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
break;
}
break;
- case 'w': // 1 strings to match.
- if (Name.substr(2,3) != "pgs")
- break;
- return MCK_swpgs; // "swpgs"
}
break;
case 't': // 4 strings to match.
@@ -3706,7 +3748,7 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
break;
}
break;
- case 6: // 163 strings to match.
+ case 6: // 165 strings to match.
switch (Name[0]) {
default: break;
case 'a': // 2 strings to match.
@@ -4535,7 +4577,11 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
break;
}
break;
- case 's': // 8 strings to match.
+ case 'r': // 1 strings to match.
+ if (Name.substr(1,5) != "dtscp")
+ break;
+ return MCK_rdtscp; // "rdtscp"
+ case 's': // 9 strings to match.
switch (Name[1]) {
default: break;
case 'f': // 1 strings to match.
@@ -4578,6 +4624,10 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
break;
}
break;
+ case 'w': // 1 strings to match.
+ if (Name.substr(2,4) != "apgs")
+ break;
+ return MCK_swapgs; // "swapgs"
case 'y': // 1 strings to match.
if (Name.substr(2,4) != "sret")
break;
@@ -5596,7 +5646,7 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
break;
}
break;
- case 9: // 31 strings to match.
+ case 9: // 25 strings to match.
switch (Name[0]) {
default: break;
case 'c': // 11 strings to match.
@@ -5775,41 +5825,19 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
break;
}
break;
- case 'r': // 8 strings to match.
+ case 'r': // 2 strings to match.
if (Name.substr(1,3) != "ep;")
break;
switch (Name[4]) {
default: break;
- case 'm': // 4 strings to match.
- if (Name.substr(5,3) != "ovs")
+ case 'm': // 1 strings to match.
+ if (Name.substr(5,4) != "ovsq")
break;
- switch (Name[8]) {
- default: break;
- case 'b': // 1 strings to match.
- return MCK_rep_59_movsb; // "rep;movsb"
- case 'l': // 1 strings to match.
- return MCK_rep_59_movsl; // "rep;movsl"
- case 'q': // 1 strings to match.
- return MCK_rep_59_movsq; // "rep;movsq"
- case 'w': // 1 strings to match.
- return MCK_rep_59_movsw; // "rep;movsw"
- }
- break;
- case 's': // 4 strings to match.
- if (Name.substr(5,3) != "tos")
+ return MCK_rep_59_movsq; // "rep;movsq"
+ case 's': // 1 strings to match.
+ if (Name.substr(5,4) != "tosq")
break;
- switch (Name[8]) {
- default: break;
- case 'b': // 1 strings to match.
- return MCK_rep_59_stosb; // "rep;stosb"
- case 'l': // 1 strings to match.
- return MCK_rep_59_stosl; // "rep;stosl"
- case 'q': // 1 strings to match.
- return MCK_rep_59_stosq; // "rep;stosq"
- case 'w': // 1 strings to match.
- return MCK_rep_59_stosw; // "rep;stosw"
- }
- break;
+ return MCK_rep_59_stosq; // "rep;stosq"
}
break;
}
@@ -5904,10 +5932,10 @@ static MatchClassKind ClassifyOperand(MCParsedAsmOperand *GOp) {
case X86::DL: return MCK_GR8_ABCD_L;
case X86::CL: return MCK_CL;
case X86::BL: return MCK_GR8_ABCD_L;
- case X86::SIL: return MCK_GR8_NOREX;
- case X86::DIL: return MCK_GR8_NOREX;
- case X86::BPL: return MCK_GR8_NOREX;
- case X86::SPL: return MCK_GR8_NOREX;
+ case X86::SIL: return MCK_GR8;
+ case X86::DIL: return MCK_GR8;
+ case X86::BPL: return MCK_GR8;
+ case X86::SPL: return MCK_GR8;
case X86::R8B: return MCK_GR8;
case X86::R9B: return MCK_GR8;
case X86::R10B: return MCK_GR8;
@@ -6070,6 +6098,18 @@ static MatchClassKind ClassifyOperand(MCParsedAsmOperand *GOp) {
return MCK_Imm;
}
+ // 'AbsMem' class, subclass of 'Mem'
+ if (Operand.isAbsMem()) {
+ assert(Operand.isMem() && "Invalid class relationship!");
+ return MCK_AbsMem;
+ }
+
+ // 'NoSegMem' class, subclass of 'Mem'
+ if (Operand.isNoSegMem()) {
+ assert(Operand.isMem() && "Invalid class relationship!");
+ return MCK_NoSegMem;
+ }
+
// 'Mem' class
if (Operand.isMem()) {
return MCK_Mem;
@@ -6152,8 +6192,8 @@ static bool IsSubclass(MatchClassKind A, MatchClassKind B) {
case MCK_GR32_AD: return true;
case MCK_GR32_ABCD: return true;
case MCK_Reg14: return true;
- case MCK_GR32_NOSP: return true;
case MCK_GR32_NOREX: return true;
+ case MCK_GR32_NOSP: return true;
case MCK_GR32: return true;
}
@@ -6162,8 +6202,8 @@ static bool IsSubclass(MatchClassKind A, MatchClassKind B) {
default: return false;
case MCK_GR32_ABCD: return true;
case MCK_Reg14: return true;
- case MCK_GR32_NOSP: return true;
case MCK_GR32_NOREX: return true;
+ case MCK_GR32_NOSP: return true;
case MCK_GR32: return true;
}
@@ -6171,23 +6211,23 @@ static bool IsSubclass(MatchClassKind A, MatchClassKind B) {
switch (B) {
default: return false;
case MCK_Reg14: return true;
- case MCK_GR32_NOSP: return true;
case MCK_GR32_NOREX: return true;
+ case MCK_GR32_NOSP: return true;
case MCK_GR32: return true;
}
case MCK_Reg14:
switch (B) {
default: return false;
- case MCK_GR32_NOSP: return true;
case MCK_GR32_NOREX: return true;
+ case MCK_GR32_NOSP: return true;
case MCK_GR32: return true;
}
- case MCK_GR32_NOSP:
+ case MCK_GR32_NOREX:
return B == MCK_GR32;
- case MCK_GR32_NOREX:
+ case MCK_GR32_NOSP:
return B == MCK_GR32;
case MCK_RAX:
@@ -6195,8 +6235,8 @@ static bool IsSubclass(MatchClassKind A, MatchClassKind B) {
default: return false;
case MCK_GR64_ABCD: return true;
case MCK_GR64_NOREX_NOSP: return true;
- case MCK_GR64_NOSP: return true;
case MCK_GR64_NOREX: return true;
+ case MCK_GR64_NOSP: return true;
case MCK_GR64: return true;
}
@@ -6204,23 +6244,23 @@ static bool IsSubclass(MatchClassKind A, MatchClassKind B) {
switch (B) {
default: return false;
case MCK_GR64_NOREX_NOSP: return true;
- case MCK_GR64_NOSP: return true;
case MCK_GR64_NOREX: return true;
+ case MCK_GR64_NOSP: return true;
case MCK_GR64: return true;
}
case MCK_GR64_NOREX_NOSP:
switch (B) {
default: return false;
- case MCK_GR64_NOSP: return true;
case MCK_GR64_NOREX: return true;
+ case MCK_GR64_NOSP: return true;
case MCK_GR64: return true;
}
- case MCK_GR64_NOSP:
+ case MCK_GR64_NOREX:
return B == MCK_GR64;
- case MCK_GR64_NOREX:
+ case MCK_GR64_NOSP:
return B == MCK_GR64;
case MCK_XMM0:
@@ -6237,6 +6277,12 @@ static bool IsSubclass(MatchClassKind A, MatchClassKind B) {
case MCK_ImmSExt8:
return B == MCK_Imm;
+
+ case MCK_AbsMem:
+ return B == MCK_Mem;
+
+ case MCK_NoSegMem:
+ return B == MCK_Mem;
}
}
@@ -6247,7 +6293,7 @@ MatchInstruction(const SmallVectorImpl<MCParsedAsmOperand*> &Operands,
unsigned Opcode;
ConversionKind ConvertFn;
MatchClassKind Classes[5];
- } MatchTable[2040] = {
+ } MatchTable[2049] = {
{ X86::CBW, Convert, { MCK_cbtw } },
{ X86::CLC, Convert, { MCK_clc } },
{ X86::CLD, Convert, { MCK_cld } },
@@ -6262,9 +6308,12 @@ MatchInstruction(const SmallVectorImpl<MCParsedAsmOperand*> &Operands,
{ X86::CMPS16, Convert, { MCK_cmpsw } },
{ X86::CPUID, Convert, { MCK_cpuid } },
{ X86::CQO, Convert, { MCK_cqto } },
+ { X86::CS_PREFIX, Convert, { MCK_cs } },
{ X86::CWD, Convert, { MCK_cwtd } },
{ X86::CWDE, Convert, { MCK_cwtl } },
+ { X86::DS_PREFIX, Convert, { MCK_ds } },
{ X86::MMX_EMMS, Convert, { MCK_emms } },
+ { X86::ES_PREFIX, Convert, { MCK_es } },
{ X86::F2XM1, Convert, { MCK_f2xm1 } },
{ X86::ABS_F, Convert, { MCK_fabs } },
{ X86::CHS_F, Convert, { MCK_fchs } },
@@ -6288,6 +6337,7 @@ MatchInstruction(const SmallVectorImpl<MCParsedAsmOperand*> &Operands,
{ X86::FPREM1, Convert, { MCK_fprem1 } },
{ X86::FPTAN, Convert, { MCK_fptan } },
{ X86::FRNDINT, Convert, { MCK_frndint } },
+ { X86::FS_PREFIX, Convert, { MCK_fs } },
{ X86::FSCALE, Convert, { MCK_fscale } },
{ X86::SIN_F, Convert, { MCK_fsin } },
{ X86::FSINCOS, Convert, { MCK_fsincos } },
@@ -6298,21 +6348,22 @@ MatchInstruction(const SmallVectorImpl<MCParsedAsmOperand*> &Operands,
{ X86::FXTRACT, Convert, { MCK_fxtract } },
{ X86::FYL2X, Convert, { MCK_fyl2x } },
{ X86::FYL2XP1, Convert, { MCK_fyl2xp1 } },
+ { X86::GS_PREFIX, Convert, { MCK_gs } },
{ X86::HLT, Convert, { MCK_hlt } },
{ X86::IN8, Convert, { MCK_insb } },
{ X86::IN32, Convert, { MCK_insl } },
{ X86::IN16, Convert, { MCK_insw } },
{ X86::INVD, Convert, { MCK_invd } },
{ X86::INVEPT, Convert, { MCK_invept } },
- { X86::INVLPG, Convert, { MCK_invlpg } },
{ X86::INVVPID, Convert, { MCK_invvpid } },
{ X86::IRET32, Convert, { MCK_iretl } },
{ X86::IRET64, Convert, { MCK_iretq } },
{ X86::IRET16, Convert, { MCK_iretw } },
{ X86::LAHF, Convert, { MCK_lahf } },
- { X86::LEAVE64, Convert, { MCK_leave } },
{ X86::LEAVE, Convert, { MCK_leave } },
+ { X86::LEAVE64, Convert, { MCK_leave } },
{ X86::LFENCE, Convert, { MCK_lfence } },
+ { X86::LOCK_PREFIX, Convert, { MCK_lock } },
{ X86::LODSB, Convert, { MCK_lodsb } },
{ X86::LODSD, Convert, { MCK_lodsl } },
{ X86::LODSQ, Convert, { MCK_lodsq } },
@@ -6320,6 +6371,9 @@ MatchInstruction(const SmallVectorImpl<MCParsedAsmOperand*> &Operands,
{ X86::LRET, Convert, { MCK_lret } },
{ X86::MFENCE, Convert, { MCK_mfence } },
{ X86::MONITOR, Convert, { MCK_monitor } },
+ { X86::MOVSB, Convert, { MCK_movsb } },
+ { X86::MOVSD, Convert, { MCK_movsl } },
+ { X86::MOVSW, Convert, { MCK_movsw } },
{ X86::MWAIT, Convert, { MCK_mwait } },
{ X86::NOOP, Convert, { MCK_nop } },
{ X86::OUTSB, Convert, { MCK_outsb } },
@@ -6334,14 +6388,11 @@ MatchInstruction(const SmallVectorImpl<MCParsedAsmOperand*> &Operands,
{ X86::RDMSR, Convert, { MCK_rdmsr } },
{ X86::RDPMC, Convert, { MCK_rdpmc } },
{ X86::RDTSC, Convert, { MCK_rdtsc } },
- { X86::REP_MOVSB, Convert, { MCK_rep_59_movsb } },
- { X86::REP_MOVSD, Convert, { MCK_rep_59_movsl } },
+ { X86::RDTSCP, Convert, { MCK_rdtscp } },
+ { X86::REP_PREFIX, Convert, { MCK_rep } },
{ X86::REP_MOVSQ, Convert, { MCK_rep_59_movsq } },
- { X86::REP_MOVSW, Convert, { MCK_rep_59_movsw } },
- { X86::REP_STOSB, Convert, { MCK_rep_59_stosb } },
- { X86::REP_STOSD, Convert, { MCK_rep_59_stosl } },
{ X86::REP_STOSQ, Convert, { MCK_rep_59_stosq } },
- { X86::REP_STOSW, Convert, { MCK_rep_59_stosw } },
+ { X86::REPNE_PREFIX, Convert, { MCK_repne } },
{ X86::RET, Convert, { MCK_ret } },
{ X86::RSM, Convert, { MCK_rsm } },
{ X86::SAHF, Convert, { MCK_sahf } },
@@ -6350,10 +6401,14 @@ MatchInstruction(const SmallVectorImpl<MCParsedAsmOperand*> &Operands,
{ X86::SCAS64, Convert, { MCK_scasq } },
{ X86::SCAS16, Convert, { MCK_scasw } },
{ X86::SFENCE, Convert, { MCK_sfence } },
+ { X86::SS_PREFIX, Convert, { MCK_ss } },
{ X86::STC, Convert, { MCK_stc } },
{ X86::STD, Convert, { MCK_std } },
{ X86::STI, Convert, { MCK_sti } },
- { X86::SWPGS, Convert, { MCK_swpgs } },
+ { X86::STOSB, Convert, { MCK_stosb } },
+ { X86::STOSD, Convert, { MCK_stosl } },
+ { X86::STOSW, Convert, { MCK_stosw } },
+ { X86::SWAPGS, Convert, { MCK_swapgs } },
{ X86::SYSCALL, Convert, { MCK_syscall } },
{ X86::SYSENTER, Convert, { MCK_sysenter } },
{ X86::SYSEXIT, Convert, { MCK_sysexit } },
@@ -6368,1926 +6423,1926 @@ MatchInstruction(const SmallVectorImpl<MCParsedAsmOperand*> &Operands,
{ X86::WBINVD, Convert, { MCK_wbinvd } },
{ X86::WRMSR, Convert, { MCK_wrmsr } },
{ X86::XLAT, Convert, { MCK_xlatb } },
- { X86::BSWAP32r, Convert_Reg1_1Imp, { MCK_bswapl, MCK_GR32 } },
- { X86::BSWAP64r, Convert_Reg1_1Imp, { MCK_bswapq, MCK_GR64 } },
- { X86::WINCALL64pcrel32, Convert_Imm1_1, { MCK_call, MCK_Imm } },
- { X86::CALLpcrel32, Convert_Imm1_1, { MCK_call, MCK_Imm } },
- { X86::CALL64pcrel32, Convert_Imm1_1, { MCK_callq, MCK_Imm } },
- { X86::CLFLUSH, Convert_Mem5_1, { MCK_clflush, MCK_Mem } },
- { X86::CMPXCHG16B, Convert_Mem5_1, { MCK_cmpxchg16b, MCK_Mem } },
- { X86::CMPXCHG8B, Convert_Mem5_1, { MCK_cmpxchg8b, MCK_Mem } },
- { X86::DEC8r, Convert_Reg1_1Imp, { MCK_decb, MCK_GR8 } },
- { X86::DEC8m, Convert_Mem5_1, { MCK_decb, MCK_Mem } },
- { X86::DEC64_32r, Convert_Reg1_1Imp, { MCK_decl, MCK_GR32 } },
- { X86::DEC32r, Convert_Reg1_1Imp, { MCK_decl, MCK_GR32 } },
- { X86::DEC64_32m, Convert_Mem5_1, { MCK_decl, MCK_Mem } },
- { X86::DEC32m, Convert_Mem5_1, { MCK_decl, MCK_Mem } },
- { X86::DEC64r, Convert_Reg1_1Imp, { MCK_decq, MCK_GR64 } },
- { X86::DEC64m, Convert_Mem5_1, { MCK_decq, MCK_Mem } },
- { X86::DEC64_16r, Convert_Reg1_1Imp, { MCK_decw, MCK_GR16 } },
- { X86::DEC16r, Convert_Reg1_1Imp, { MCK_decw, MCK_GR16 } },
- { X86::DEC64_16m, Convert_Mem5_1, { MCK_decw, MCK_Mem } },
- { X86::DEC16m, Convert_Mem5_1, { MCK_decw, MCK_Mem } },
- { X86::DIV8r, Convert_Reg1_1, { MCK_divb, MCK_GR8 } },
- { X86::DIV8m, Convert_Mem5_1, { MCK_divb, MCK_Mem } },
- { X86::DIV32r, Convert_Reg1_1, { MCK_divl, MCK_GR32 } },
- { X86::DIV32m, Convert_Mem5_1, { MCK_divl, MCK_Mem } },
- { X86::DIV64r, Convert_Reg1_1, { MCK_divq, MCK_GR64 } },
- { X86::DIV64m, Convert_Mem5_1, { MCK_divq, MCK_Mem } },
- { X86::DIV16r, Convert_Reg1_1, { MCK_divw, MCK_GR16 } },
- { X86::DIV16m, Convert_Mem5_1, { MCK_divw, MCK_Mem } },
- { X86::ADD_FST0r, Convert_Reg1_1, { MCK_fadd, MCK_RST } },
- { X86::ADD_F64m, Convert_Mem5_1, { MCK_faddl, MCK_Mem } },
- { X86::ADD_FPrST0, Convert_Reg1_1, { MCK_faddp, MCK_RST } },
- { X86::ADD_F32m, Convert_Mem5_1, { MCK_fadds, MCK_Mem } },
- { X86::FBLDm, Convert_Mem5_1, { MCK_fbld, MCK_Mem } },
- { X86::FBSTPm, Convert_Mem5_1, { MCK_fbstp, MCK_Mem } },
- { X86::COM_FST0r, Convert_Reg1_1, { MCK_fcom, MCK_RST } },
- { X86::FCOM32m, Convert_Mem5_1, { MCK_fcoml, MCK_Mem } },
- { X86::FCOM64m, Convert_Mem5_1, { MCK_fcomll, MCK_Mem } },
- { X86::COMP_FST0r, Convert_Reg1_1, { MCK_fcomp, MCK_RST } },
- { X86::FCOMP32m, Convert_Mem5_1, { MCK_fcompl, MCK_Mem } },
- { X86::FCOMP64m, Convert_Mem5_1, { MCK_fcompll, MCK_Mem } },
- { X86::DIV_FST0r, Convert_Reg1_1, { MCK_fdiv, MCK_RST } },
- { X86::DIV_F64m, Convert_Mem5_1, { MCK_fdivl, MCK_Mem } },
- { X86::DIVR_FPrST0, Convert_Reg1_1, { MCK_fdivp, MCK_RST } },
- { X86::DIVR_FST0r, Convert_Reg1_1, { MCK_fdivr, MCK_RST } },
- { X86::DIVR_F64m, Convert_Mem5_1, { MCK_fdivrl, MCK_Mem } },
- { X86::DIV_FPrST0, Convert_Reg1_1, { MCK_fdivrp, MCK_RST } },
- { X86::DIVR_F32m, Convert_Mem5_1, { MCK_fdivrs, MCK_Mem } },
- { X86::DIV_F32m, Convert_Mem5_1, { MCK_fdivs, MCK_Mem } },
- { X86::FFREE, Convert_Reg1_1, { MCK_ffree, MCK_RST } },
- { X86::ADD_FI32m, Convert_Mem5_1, { MCK_fiaddl, MCK_Mem } },
- { X86::ADD_FI16m, Convert_Mem5_1, { MCK_fiadds, MCK_Mem } },
- { X86::FICOM32m, Convert_Mem5_1, { MCK_ficoml, MCK_Mem } },
- { X86::FICOMP32m, Convert_Mem5_1, { MCK_ficompl, MCK_Mem } },
- { X86::FICOMP16m, Convert_Mem5_1, { MCK_ficompw, MCK_Mem } },
- { X86::FICOM16m, Convert_Mem5_1, { MCK_ficomw, MCK_Mem } },
- { X86::DIV_FI32m, Convert_Mem5_1, { MCK_fidivl, MCK_Mem } },
- { X86::DIVR_FI32m, Convert_Mem5_1, { MCK_fidivrl, MCK_Mem } },
- { X86::DIVR_FI16m, Convert_Mem5_1, { MCK_fidivrs, MCK_Mem } },
- { X86::DIV_FI16m, Convert_Mem5_1, { MCK_fidivs, MCK_Mem } },
- { X86::ILD_F32m, Convert_Mem5_1, { MCK_fildl, MCK_Mem } },
- { X86::ILD_F64m, Convert_Mem5_1, { MCK_fildll, MCK_Mem } },
- { X86::ILD_F16m, Convert_Mem5_1, { MCK_filds, MCK_Mem } },
- { X86::MUL_FI32m, Convert_Mem5_1, { MCK_fimull, MCK_Mem } },
- { X86::MUL_FI16m, Convert_Mem5_1, { MCK_fimuls, MCK_Mem } },
- { X86::IST_F32m, Convert_Mem5_1, { MCK_fistl, MCK_Mem } },
- { X86::IST_FP32m, Convert_Mem5_1, { MCK_fistpl, MCK_Mem } },
- { X86::IST_FP64m, Convert_Mem5_1, { MCK_fistpll, MCK_Mem } },
- { X86::IST_FP16m, Convert_Mem5_1, { MCK_fistps, MCK_Mem } },
- { X86::IST_F16m, Convert_Mem5_1, { MCK_fists, MCK_Mem } },
- { X86::ISTT_FP32m, Convert_Mem5_1, { MCK_fisttpl, MCK_Mem } },
- { X86::FISTTP32m, Convert_Mem5_1, { MCK_fisttpl, MCK_Mem } },
- { X86::ISTT_FP64m, Convert_Mem5_1, { MCK_fisttpll, MCK_Mem } },
- { X86::ISTT_FP16m, Convert_Mem5_1, { MCK_fisttps, MCK_Mem } },
- { X86::SUB_FI32m, Convert_Mem5_1, { MCK_fisubl, MCK_Mem } },
- { X86::SUBR_FI32m, Convert_Mem5_1, { MCK_fisubrl, MCK_Mem } },
- { X86::SUBR_FI16m, Convert_Mem5_1, { MCK_fisubrs, MCK_Mem } },
- { X86::SUB_FI16m, Convert_Mem5_1, { MCK_fisubs, MCK_Mem } },
- { X86::LD_Frr, Convert_Reg1_1, { MCK_fld, MCK_RST } },
- { X86::FLDCW16m, Convert_Mem5_1, { MCK_fldcw, MCK_Mem } },
- { X86::FLDENVm, Convert_Mem5_1, { MCK_fldenv, MCK_Mem } },
- { X86::LD_F64m, Convert_Mem5_1, { MCK_fldl, MCK_Mem } },
- { X86::LD_F32m, Convert_Mem5_1, { MCK_flds, MCK_Mem } },
- { X86::LD_F80m, Convert_Mem5_1, { MCK_fldt, MCK_Mem } },
- { X86::MUL_FST0r, Convert_Reg1_1, { MCK_fmul, MCK_RST } },
- { X86::MUL_F64m, Convert_Mem5_1, { MCK_fmull, MCK_Mem } },
- { X86::MUL_FPrST0, Convert_Reg1_1, { MCK_fmulp, MCK_RST } },
- { X86::MUL_F32m, Convert_Mem5_1, { MCK_fmuls, MCK_Mem } },
- { X86::FSAVEm, Convert_Mem5_1, { MCK_fnsave, MCK_Mem } },
- { X86::FNSTCW16m, Convert_Mem5_1, { MCK_fnstcw, MCK_Mem } },
- { X86::FSTENVm, Convert_Mem5_1, { MCK_fnstenv, MCK_Mem } },
+ { X86::BSWAP32r, Convert__Reg1_1__Tie0, { MCK_bswapl, MCK_GR32 } },
+ { X86::BSWAP64r, Convert__Reg1_1__Tie0, { MCK_bswapq, MCK_GR64 } },
+ { X86::WINCALL64pcrel32, Convert__Imm1_1, { MCK_call, MCK_Imm } },
+ { X86::CALLpcrel32, Convert__AbsMem1_1, { MCK_call, MCK_AbsMem } },
+ { X86::CALL64pcrel32, Convert__Imm1_1, { MCK_callq, MCK_Imm } },
+ { X86::CLFLUSH, Convert__Mem5_1, { MCK_clflush, MCK_Mem } },
+ { X86::CMPXCHG16B, Convert__Mem5_1, { MCK_cmpxchg16b, MCK_Mem } },
+ { X86::CMPXCHG8B, Convert__Mem5_1, { MCK_cmpxchg8b, MCK_Mem } },
+ { X86::DEC8r, Convert__Reg1_1__Tie0, { MCK_decb, MCK_GR8 } },
+ { X86::DEC8m, Convert__Mem5_1, { MCK_decb, MCK_Mem } },
+ { X86::DEC32r, Convert__Reg1_1__Tie0, { MCK_decl, MCK_GR32 } },
+ { X86::DEC64_32r, Convert__Reg1_1__Tie0, { MCK_decl, MCK_GR32 } },
+ { X86::DEC32m, Convert__Mem5_1, { MCK_decl, MCK_Mem } },
+ { X86::DEC64_32m, Convert__Mem5_1, { MCK_decl, MCK_Mem } },
+ { X86::DEC64r, Convert__Reg1_1__Tie0, { MCK_decq, MCK_GR64 } },
+ { X86::DEC64m, Convert__Mem5_1, { MCK_decq, MCK_Mem } },
+ { X86::DEC16r, Convert__Reg1_1__Tie0, { MCK_decw, MCK_GR16 } },
+ { X86::DEC64_16r, Convert__Reg1_1__Tie0, { MCK_decw, MCK_GR16 } },
+ { X86::DEC16m, Convert__Mem5_1, { MCK_decw, MCK_Mem } },
+ { X86::DEC64_16m, Convert__Mem5_1, { MCK_decw, MCK_Mem } },
+ { X86::DIV8r, Convert__Reg1_1, { MCK_divb, MCK_GR8 } },
+ { X86::DIV8m, Convert__Mem5_1, { MCK_divb, MCK_Mem } },
+ { X86::DIV32r, Convert__Reg1_1, { MCK_divl, MCK_GR32 } },
+ { X86::DIV32m, Convert__Mem5_1, { MCK_divl, MCK_Mem } },
+ { X86::DIV64r, Convert__Reg1_1, { MCK_divq, MCK_GR64 } },
+ { X86::DIV64m, Convert__Mem5_1, { MCK_divq, MCK_Mem } },
+ { X86::DIV16r, Convert__Reg1_1, { MCK_divw, MCK_GR16 } },
+ { X86::DIV16m, Convert__Mem5_1, { MCK_divw, MCK_Mem } },
+ { X86::ADD_FST0r, Convert__Reg1_1, { MCK_fadd, MCK_RST } },
+ { X86::ADD_F64m, Convert__Mem5_1, { MCK_faddl, MCK_Mem } },
+ { X86::ADD_FPrST0, Convert__Reg1_1, { MCK_faddp, MCK_RST } },
+ { X86::ADD_F32m, Convert__Mem5_1, { MCK_fadds, MCK_Mem } },
+ { X86::FBLDm, Convert__Mem5_1, { MCK_fbld, MCK_Mem } },
+ { X86::FBSTPm, Convert__Mem5_1, { MCK_fbstp, MCK_Mem } },
+ { X86::COM_FST0r, Convert__Reg1_1, { MCK_fcom, MCK_RST } },
+ { X86::FCOM32m, Convert__Mem5_1, { MCK_fcoml, MCK_Mem } },
+ { X86::FCOM64m, Convert__Mem5_1, { MCK_fcomll, MCK_Mem } },
+ { X86::COMP_FST0r, Convert__Reg1_1, { MCK_fcomp, MCK_RST } },
+ { X86::FCOMP32m, Convert__Mem5_1, { MCK_fcompl, MCK_Mem } },
+ { X86::FCOMP64m, Convert__Mem5_1, { MCK_fcompll, MCK_Mem } },
+ { X86::DIV_FST0r, Convert__Reg1_1, { MCK_fdiv, MCK_RST } },
+ { X86::DIV_F64m, Convert__Mem5_1, { MCK_fdivl, MCK_Mem } },
+ { X86::DIVR_FPrST0, Convert__Reg1_1, { MCK_fdivp, MCK_RST } },
+ { X86::DIVR_FST0r, Convert__Reg1_1, { MCK_fdivr, MCK_RST } },
+ { X86::DIVR_F64m, Convert__Mem5_1, { MCK_fdivrl, MCK_Mem } },
+ { X86::DIV_FPrST0, Convert__Reg1_1, { MCK_fdivrp, MCK_RST } },
+ { X86::DIVR_F32m, Convert__Mem5_1, { MCK_fdivrs, MCK_Mem } },
+ { X86::DIV_F32m, Convert__Mem5_1, { MCK_fdivs, MCK_Mem } },
+ { X86::FFREE, Convert__Reg1_1, { MCK_ffree, MCK_RST } },
+ { X86::ADD_FI32m, Convert__Mem5_1, { MCK_fiaddl, MCK_Mem } },
+ { X86::ADD_FI16m, Convert__Mem5_1, { MCK_fiadds, MCK_Mem } },
+ { X86::FICOM32m, Convert__Mem5_1, { MCK_ficoml, MCK_Mem } },
+ { X86::FICOMP32m, Convert__Mem5_1, { MCK_ficompl, MCK_Mem } },
+ { X86::FICOMP16m, Convert__Mem5_1, { MCK_ficompw, MCK_Mem } },
+ { X86::FICOM16m, Convert__Mem5_1, { MCK_ficomw, MCK_Mem } },
+ { X86::DIV_FI32m, Convert__Mem5_1, { MCK_fidivl, MCK_Mem } },
+ { X86::DIVR_FI32m, Convert__Mem5_1, { MCK_fidivrl, MCK_Mem } },
+ { X86::DIVR_FI16m, Convert__Mem5_1, { MCK_fidivrs, MCK_Mem } },
+ { X86::DIV_FI16m, Convert__Mem5_1, { MCK_fidivs, MCK_Mem } },
+ { X86::ILD_F32m, Convert__Mem5_1, { MCK_fildl, MCK_Mem } },
+ { X86::ILD_F64m, Convert__Mem5_1, { MCK_fildll, MCK_Mem } },
+ { X86::ILD_F16m, Convert__Mem5_1, { MCK_filds, MCK_Mem } },
+ { X86::MUL_FI32m, Convert__Mem5_1, { MCK_fimull, MCK_Mem } },
+ { X86::MUL_FI16m, Convert__Mem5_1, { MCK_fimuls, MCK_Mem } },
+ { X86::IST_F32m, Convert__Mem5_1, { MCK_fistl, MCK_Mem } },
+ { X86::IST_FP32m, Convert__Mem5_1, { MCK_fistpl, MCK_Mem } },
+ { X86::IST_FP64m, Convert__Mem5_1, { MCK_fistpll, MCK_Mem } },
+ { X86::IST_FP16m, Convert__Mem5_1, { MCK_fistps, MCK_Mem } },
+ { X86::IST_F16m, Convert__Mem5_1, { MCK_fists, MCK_Mem } },
+ { X86::ISTT_FP32m, Convert__Mem5_1, { MCK_fisttpl, MCK_Mem } },
+ { X86::ISTT_FP64m, Convert__Mem5_1, { MCK_fisttpll, MCK_Mem } },
+ { X86::ISTT_FP16m, Convert__Mem5_1, { MCK_fisttps, MCK_Mem } },
+ { X86::SUB_FI32m, Convert__Mem5_1, { MCK_fisubl, MCK_Mem } },
+ { X86::SUBR_FI32m, Convert__Mem5_1, { MCK_fisubrl, MCK_Mem } },
+ { X86::SUBR_FI16m, Convert__Mem5_1, { MCK_fisubrs, MCK_Mem } },
+ { X86::SUB_FI16m, Convert__Mem5_1, { MCK_fisubs, MCK_Mem } },
+ { X86::LD_Frr, Convert__Reg1_1, { MCK_fld, MCK_RST } },
+ { X86::FLDCW16m, Convert__Mem5_1, { MCK_fldcw, MCK_Mem } },
+ { X86::FLDENVm, Convert__Mem5_1, { MCK_fldenv, MCK_Mem } },
+ { X86::LD_F64m, Convert__Mem5_1, { MCK_fldl, MCK_Mem } },
+ { X86::LD_F32m, Convert__Mem5_1, { MCK_flds, MCK_Mem } },
+ { X86::LD_F80m, Convert__Mem5_1, { MCK_fldt, MCK_Mem } },
+ { X86::MUL_FST0r, Convert__Reg1_1, { MCK_fmul, MCK_RST } },
+ { X86::MUL_F64m, Convert__Mem5_1, { MCK_fmull, MCK_Mem } },
+ { X86::MUL_FPrST0, Convert__Reg1_1, { MCK_fmulp, MCK_RST } },
+ { X86::MUL_F32m, Convert__Mem5_1, { MCK_fmuls, MCK_Mem } },
+ { X86::FSAVEm, Convert__Mem5_1, { MCK_fnsave, MCK_Mem } },
+ { X86::FNSTCW16m, Convert__Mem5_1, { MCK_fnstcw, MCK_Mem } },
+ { X86::FSTENVm, Convert__Mem5_1, { MCK_fnstenv, MCK_Mem } },
{ X86::FNSTSW8r, Convert, { MCK_fnstsw, MCK_AX } },
- { X86::FNSTSWm, Convert_Mem5_1, { MCK_fnstsw, MCK_Mem } },
- { X86::FRSTORm, Convert_Mem5_1, { MCK_frstor, MCK_Mem } },
- { X86::ST_Frr, Convert_Reg1_1, { MCK_fst, MCK_RST } },
- { X86::ST_F64m, Convert_Mem5_1, { MCK_fstl, MCK_Mem } },
- { X86::ST_FPrr, Convert_Reg1_1, { MCK_fstp, MCK_RST } },
- { X86::ST_FP64m, Convert_Mem5_1, { MCK_fstpl, MCK_Mem } },
- { X86::ST_FP32m, Convert_Mem5_1, { MCK_fstps, MCK_Mem } },
- { X86::ST_FP80m, Convert_Mem5_1, { MCK_fstpt, MCK_Mem } },
- { X86::ST_F32m, Convert_Mem5_1, { MCK_fsts, MCK_Mem } },
- { X86::SUB_FST0r, Convert_Reg1_1, { MCK_fsub, MCK_RST } },
- { X86::SUB_F64m, Convert_Mem5_1, { MCK_fsubl, MCK_Mem } },
- { X86::SUBR_FPrST0, Convert_Reg1_1, { MCK_fsubp, MCK_RST } },
- { X86::SUBR_FST0r, Convert_Reg1_1, { MCK_fsubr, MCK_RST } },
- { X86::SUBR_F64m, Convert_Mem5_1, { MCK_fsubrl, MCK_Mem } },
- { X86::SUB_FPrST0, Convert_Reg1_1, { MCK_fsubrp, MCK_RST } },
- { X86::SUBR_F32m, Convert_Mem5_1, { MCK_fsubrs, MCK_Mem } },
- { X86::SUB_F32m, Convert_Mem5_1, { MCK_fsubs, MCK_Mem } },
- { X86::UCOM_Fr, Convert_Reg1_1, { MCK_fucom, MCK_RST } },
- { X86::UCOM_FPr, Convert_Reg1_1, { MCK_fucomp, MCK_RST } },
- { X86::XCH_F, Convert_Reg1_1, { MCK_fxch, MCK_RST } },
- { X86::FXRSTOR, Convert_Mem5_1, { MCK_fxrstor, MCK_Mem } },
- { X86::FXSAVE, Convert_Mem5_1, { MCK_fxsave, MCK_Mem } },
- { X86::IDIV8r, Convert_Reg1_1, { MCK_idivb, MCK_GR8 } },
- { X86::IDIV8m, Convert_Mem5_1, { MCK_idivb, MCK_Mem } },
- { X86::IDIV32r, Convert_Reg1_1, { MCK_idivl, MCK_GR32 } },
- { X86::IDIV32m, Convert_Mem5_1, { MCK_idivl, MCK_Mem } },
- { X86::IDIV64r, Convert_Reg1_1, { MCK_idivq, MCK_GR64 } },
- { X86::IDIV64m, Convert_Mem5_1, { MCK_idivq, MCK_Mem } },
- { X86::IDIV16r, Convert_Reg1_1, { MCK_idivw, MCK_GR16 } },
- { X86::IDIV16m, Convert_Mem5_1, { MCK_idivw, MCK_Mem } },
- { X86::IMUL8r, Convert_Reg1_1, { MCK_imulb, MCK_GR8 } },
- { X86::IMUL8m, Convert_Mem5_1, { MCK_imulb, MCK_Mem } },
- { X86::IMUL32r, Convert_Reg1_1, { MCK_imull, MCK_GR32 } },
- { X86::IMUL32m, Convert_Mem5_1, { MCK_imull, MCK_Mem } },
- { X86::IMUL64r, Convert_Reg1_1, { MCK_imulq, MCK_GR64 } },
- { X86::IMUL64m, Convert_Mem5_1, { MCK_imulq, MCK_Mem } },
- { X86::IMUL16r, Convert_Reg1_1, { MCK_imulw, MCK_GR16 } },
- { X86::IMUL16m, Convert_Mem5_1, { MCK_imulw, MCK_Mem } },
- { X86::INC8r, Convert_Reg1_1Imp, { MCK_incb, MCK_GR8 } },
- { X86::INC8m, Convert_Mem5_1, { MCK_incb, MCK_Mem } },
- { X86::INC32r, Convert_Reg1_1Imp, { MCK_incl, MCK_GR32 } },
- { X86::INC64_32r, Convert_Reg1_1Imp, { MCK_incl, MCK_GR32 } },
- { X86::INC32m, Convert_Mem5_1, { MCK_incl, MCK_Mem } },
- { X86::INC64_32m, Convert_Mem5_1, { MCK_incl, MCK_Mem } },
- { X86::INC64r, Convert_Reg1_1Imp, { MCK_incq, MCK_GR64 } },
- { X86::INC64m, Convert_Mem5_1, { MCK_incq, MCK_Mem } },
- { X86::INC16r, Convert_Reg1_1Imp, { MCK_incw, MCK_GR16 } },
- { X86::INC64_16r, Convert_Reg1_1Imp, { MCK_incw, MCK_GR16 } },
- { X86::INC16m, Convert_Mem5_1, { MCK_incw, MCK_Mem } },
- { X86::INC64_16m, Convert_Mem5_1, { MCK_incw, MCK_Mem } },
+ { X86::FNSTSWm, Convert__Mem5_1, { MCK_fnstsw, MCK_Mem } },
+ { X86::FRSTORm, Convert__Mem5_1, { MCK_frstor, MCK_Mem } },
+ { X86::ST_Frr, Convert__Reg1_1, { MCK_fst, MCK_RST } },
+ { X86::ST_F64m, Convert__Mem5_1, { MCK_fstl, MCK_Mem } },
+ { X86::ST_FPrr, Convert__Reg1_1, { MCK_fstp, MCK_RST } },
+ { X86::ST_FP64m, Convert__Mem5_1, { MCK_fstpl, MCK_Mem } },
+ { X86::ST_FP32m, Convert__Mem5_1, { MCK_fstps, MCK_Mem } },
+ { X86::ST_FP80m, Convert__Mem5_1, { MCK_fstpt, MCK_Mem } },
+ { X86::ST_F32m, Convert__Mem5_1, { MCK_fsts, MCK_Mem } },
+ { X86::SUB_FST0r, Convert__Reg1_1, { MCK_fsub, MCK_RST } },
+ { X86::SUB_F64m, Convert__Mem5_1, { MCK_fsubl, MCK_Mem } },
+ { X86::SUBR_FPrST0, Convert__Reg1_1, { MCK_fsubp, MCK_RST } },
+ { X86::SUBR_FST0r, Convert__Reg1_1, { MCK_fsubr, MCK_RST } },
+ { X86::SUBR_F64m, Convert__Mem5_1, { MCK_fsubrl, MCK_Mem } },
+ { X86::SUB_FPrST0, Convert__Reg1_1, { MCK_fsubrp, MCK_RST } },
+ { X86::SUBR_F32m, Convert__Mem5_1, { MCK_fsubrs, MCK_Mem } },
+ { X86::SUB_F32m, Convert__Mem5_1, { MCK_fsubs, MCK_Mem } },
+ { X86::UCOM_Fr, Convert__Reg1_1, { MCK_fucom, MCK_RST } },
+ { X86::UCOM_FPr, Convert__Reg1_1, { MCK_fucomp, MCK_RST } },
+ { X86::XCH_F, Convert__Reg1_1, { MCK_fxch, MCK_RST } },
+ { X86::FXRSTOR, Convert__Mem5_1, { MCK_fxrstor, MCK_Mem } },
+ { X86::FXSAVE, Convert__Mem5_1, { MCK_fxsave, MCK_Mem } },
+ { X86::IDIV8r, Convert__Reg1_1, { MCK_idivb, MCK_GR8 } },
+ { X86::IDIV8m, Convert__Mem5_1, { MCK_idivb, MCK_Mem } },
+ { X86::IDIV32r, Convert__Reg1_1, { MCK_idivl, MCK_GR32 } },
+ { X86::IDIV32m, Convert__Mem5_1, { MCK_idivl, MCK_Mem } },
+ { X86::IDIV64r, Convert__Reg1_1, { MCK_idivq, MCK_GR64 } },
+ { X86::IDIV64m, Convert__Mem5_1, { MCK_idivq, MCK_Mem } },
+ { X86::IDIV16r, Convert__Reg1_1, { MCK_idivw, MCK_GR16 } },
+ { X86::IDIV16m, Convert__Mem5_1, { MCK_idivw, MCK_Mem } },
+ { X86::IMUL8r, Convert__Reg1_1, { MCK_imulb, MCK_GR8 } },
+ { X86::IMUL8m, Convert__Mem5_1, { MCK_imulb, MCK_Mem } },
+ { X86::IMUL32r, Convert__Reg1_1, { MCK_imull, MCK_GR32 } },
+ { X86::IMUL32m, Convert__Mem5_1, { MCK_imull, MCK_Mem } },
+ { X86::IMUL64r, Convert__Reg1_1, { MCK_imulq, MCK_GR64 } },
+ { X86::IMUL64m, Convert__Mem5_1, { MCK_imulq, MCK_Mem } },
+ { X86::IMUL16r, Convert__Reg1_1, { MCK_imulw, MCK_GR16 } },
+ { X86::IMUL16m, Convert__Mem5_1, { MCK_imulw, MCK_Mem } },
+ { X86::INC8r, Convert__Reg1_1__Tie0, { MCK_incb, MCK_GR8 } },
+ { X86::INC8m, Convert__Mem5_1, { MCK_incb, MCK_Mem } },
+ { X86::INC32r, Convert__Reg1_1__Tie0, { MCK_incl, MCK_GR32 } },
+ { X86::INC64_32r, Convert__Reg1_1__Tie0, { MCK_incl, MCK_GR32 } },
+ { X86::INC32m, Convert__Mem5_1, { MCK_incl, MCK_Mem } },
+ { X86::INC64_32m, Convert__Mem5_1, { MCK_incl, MCK_Mem } },
+ { X86::INC64r, Convert__Reg1_1__Tie0, { MCK_incq, MCK_GR64 } },
+ { X86::INC64m, Convert__Mem5_1, { MCK_incq, MCK_Mem } },
+ { X86::INC16r, Convert__Reg1_1__Tie0, { MCK_incw, MCK_GR16 } },
+ { X86::INC64_16r, Convert__Reg1_1__Tie0, { MCK_incw, MCK_GR16 } },
+ { X86::INC16m, Convert__Mem5_1, { MCK_incw, MCK_Mem } },
+ { X86::INC64_16m, Convert__Mem5_1, { MCK_incw, MCK_Mem } },
{ X86::INT3, Convert, { MCK_int, MCK_3 } },
- { X86::INT, Convert_Imm1_1, { MCK_int, MCK_Imm } },
- { X86::JA8, Convert_Imm1_1, { MCK_ja, MCK_Imm } },
- { X86::JA, Convert_Imm1_1, { MCK_ja, MCK_Imm } },
- { X86::JAE, Convert_Imm1_1, { MCK_jae, MCK_Imm } },
- { X86::JAE8, Convert_Imm1_1, { MCK_jae, MCK_Imm } },
- { X86::JB, Convert_Imm1_1, { MCK_jb, MCK_Imm } },
- { X86::JB8, Convert_Imm1_1, { MCK_jb, MCK_Imm } },
- { X86::JBE, Convert_Imm1_1, { MCK_jbe, MCK_Imm } },
- { X86::JBE8, Convert_Imm1_1, { MCK_jbe, MCK_Imm } },
- { X86::JCXZ8, Convert_Imm1_1, { MCK_jcxz, MCK_Imm } },
- { X86::JE, Convert_Imm1_1, { MCK_je, MCK_Imm } },
- { X86::JE8, Convert_Imm1_1, { MCK_je, MCK_Imm } },
- { X86::JG, Convert_Imm1_1, { MCK_jg, MCK_Imm } },
- { X86::JG8, Convert_Imm1_1, { MCK_jg, MCK_Imm } },
- { X86::JGE, Convert_Imm1_1, { MCK_jge, MCK_Imm } },
- { X86::JGE8, Convert_Imm1_1, { MCK_jge, MCK_Imm } },
- { X86::JL8, Convert_Imm1_1, { MCK_jl, MCK_Imm } },
- { X86::JL, Convert_Imm1_1, { MCK_jl, MCK_Imm } },
- { X86::JLE, Convert_Imm1_1, { MCK_jle, MCK_Imm } },
- { X86::JLE8, Convert_Imm1_1, { MCK_jle, MCK_Imm } },
- { X86::JMP, Convert_Imm1_1, { MCK_jmp, MCK_Imm } },
- { X86::JMP8, Convert_Imm1_1, { MCK_jmp, MCK_Imm } },
- { X86::TAILJMPd, Convert_Imm1_1, { MCK_jmp, MCK_Imm } },
- { X86::JMP64pcrel32, Convert_Imm1_1, { MCK_jmpq, MCK_Imm } },
- { X86::JNE, Convert_Imm1_1, { MCK_jne, MCK_Imm } },
- { X86::JNE8, Convert_Imm1_1, { MCK_jne, MCK_Imm } },
- { X86::JNO, Convert_Imm1_1, { MCK_jno, MCK_Imm } },
- { X86::JNO8, Convert_Imm1_1, { MCK_jno, MCK_Imm } },
- { X86::JNP, Convert_Imm1_1, { MCK_jnp, MCK_Imm } },
- { X86::JNP8, Convert_Imm1_1, { MCK_jnp, MCK_Imm } },
- { X86::JNS, Convert_Imm1_1, { MCK_jns, MCK_Imm } },
- { X86::JNS8, Convert_Imm1_1, { MCK_jns, MCK_Imm } },
- { X86::JO, Convert_Imm1_1, { MCK_jo, MCK_Imm } },
- { X86::JO8, Convert_Imm1_1, { MCK_jo, MCK_Imm } },
- { X86::JP8, Convert_Imm1_1, { MCK_jp, MCK_Imm } },
- { X86::JP, Convert_Imm1_1, { MCK_jp, MCK_Imm } },
- { X86::JS8, Convert_Imm1_1, { MCK_js, MCK_Imm } },
- { X86::JS, Convert_Imm1_1, { MCK_js, MCK_Imm } },
- { X86::LDMXCSR, Convert_Mem5_1, { MCK_ldmxcsr, MCK_Mem } },
- { X86::LGDTm, Convert_Mem5_1, { MCK_lgdt, MCK_Mem } },
- { X86::LIDTm, Convert_Mem5_1, { MCK_lidt, MCK_Mem } },
- { X86::LLDT16r, Convert_Reg1_1, { MCK_lldtw, MCK_GR16 } },
- { X86::LLDT16m, Convert_Mem5_1, { MCK_lldtw, MCK_Mem } },
- { X86::LMSW16r, Convert_Reg1_1, { MCK_lmsww, MCK_GR16 } },
- { X86::LMSW16m, Convert_Mem5_1, { MCK_lmsww, MCK_Mem } },
- { X86::LOOP, Convert_Imm1_1, { MCK_loop, MCK_Imm } },
- { X86::LOOPE, Convert_Imm1_1, { MCK_loope, MCK_Imm } },
- { X86::LOOPNE, Convert_Imm1_1, { MCK_loopne, MCK_Imm } },
- { X86::LRETI, Convert_Imm1_1, { MCK_lret, MCK_Imm } },
- { X86::LTRr, Convert_Reg1_1, { MCK_ltrw, MCK_GR16 } },
- { X86::LTRm, Convert_Mem5_1, { MCK_ltrw, MCK_Mem } },
- { X86::MUL8r, Convert_Reg1_1, { MCK_mulb, MCK_GR8 } },
- { X86::MUL8m, Convert_Mem5_1, { MCK_mulb, MCK_Mem } },
- { X86::MUL32r, Convert_Reg1_1, { MCK_mull, MCK_GR32 } },
- { X86::MUL32m, Convert_Mem5_1, { MCK_mull, MCK_Mem } },
- { X86::MUL64r, Convert_Reg1_1, { MCK_mulq, MCK_GR64 } },
- { X86::MUL64m, Convert_Mem5_1, { MCK_mulq, MCK_Mem } },
- { X86::MUL16r, Convert_Reg1_1, { MCK_mulw, MCK_GR16 } },
- { X86::MUL16m, Convert_Mem5_1, { MCK_mulw, MCK_Mem } },
- { X86::NEG8r, Convert_Reg1_1Imp, { MCK_negb, MCK_GR8 } },
- { X86::NEG8m, Convert_Mem5_1, { MCK_negb, MCK_Mem } },
- { X86::NEG32r, Convert_Reg1_1Imp, { MCK_negl, MCK_GR32 } },
- { X86::NEG32m, Convert_Mem5_1, { MCK_negl, MCK_Mem } },
- { X86::NEG64r, Convert_Reg1_1Imp, { MCK_negq, MCK_GR64 } },
- { X86::NEG64m, Convert_Mem5_1, { MCK_negq, MCK_Mem } },
- { X86::NEG16r, Convert_Reg1_1Imp, { MCK_negw, MCK_GR16 } },
- { X86::NEG16m, Convert_Mem5_1, { MCK_negw, MCK_Mem } },
- { X86::NOOPL, Convert_Mem5_1, { MCK_nopl, MCK_Mem } },
- { X86::NOOPW, Convert_Mem5_1, { MCK_nopw, MCK_Mem } },
- { X86::NOT8r, Convert_Reg1_1Imp, { MCK_notb, MCK_GR8 } },
- { X86::NOT8m, Convert_Mem5_1, { MCK_notb, MCK_Mem } },
- { X86::NOT32r, Convert_Reg1_1Imp, { MCK_notl, MCK_GR32 } },
- { X86::NOT32m, Convert_Mem5_1, { MCK_notl, MCK_Mem } },
- { X86::NOT64r, Convert_Reg1_1Imp, { MCK_notq, MCK_GR64 } },
- { X86::NOT64m, Convert_Mem5_1, { MCK_notq, MCK_Mem } },
- { X86::NOT16r, Convert_Reg1_1Imp, { MCK_notw, MCK_GR16 } },
- { X86::NOT16m, Convert_Mem5_1, { MCK_notw, MCK_Mem } },
- { X86::POP32rmr, Convert_Reg1_1, { MCK_popl, MCK_GR32 } },
- { X86::POP32r, Convert_Reg1_1, { MCK_popl, MCK_GR32 } },
+ { X86::INT, Convert__Imm1_1, { MCK_int, MCK_Imm } },
+ { X86::INVLPG, Convert__Mem5_1, { MCK_invlpg, MCK_Mem } },
+ { X86::JA_1, Convert__AbsMem1_1, { MCK_ja, MCK_AbsMem } },
+ { X86::JA_4, Convert__AbsMem1_1, { MCK_ja, MCK_AbsMem } },
+ { X86::JAE_1, Convert__AbsMem1_1, { MCK_jae, MCK_AbsMem } },
+ { X86::JAE_4, Convert__AbsMem1_1, { MCK_jae, MCK_AbsMem } },
+ { X86::JB_1, Convert__AbsMem1_1, { MCK_jb, MCK_AbsMem } },
+ { X86::JB_4, Convert__AbsMem1_1, { MCK_jb, MCK_AbsMem } },
+ { X86::JBE_1, Convert__AbsMem1_1, { MCK_jbe, MCK_AbsMem } },
+ { X86::JBE_4, Convert__AbsMem1_1, { MCK_jbe, MCK_AbsMem } },
+ { X86::JCXZ8, Convert__AbsMem1_1, { MCK_jcxz, MCK_AbsMem } },
+ { X86::JE_1, Convert__AbsMem1_1, { MCK_je, MCK_AbsMem } },
+ { X86::JE_4, Convert__AbsMem1_1, { MCK_je, MCK_AbsMem } },
+ { X86::JG_1, Convert__AbsMem1_1, { MCK_jg, MCK_AbsMem } },
+ { X86::JG_4, Convert__AbsMem1_1, { MCK_jg, MCK_AbsMem } },
+ { X86::JGE_1, Convert__AbsMem1_1, { MCK_jge, MCK_AbsMem } },
+ { X86::JGE_4, Convert__AbsMem1_1, { MCK_jge, MCK_AbsMem } },
+ { X86::JL_1, Convert__AbsMem1_1, { MCK_jl, MCK_AbsMem } },
+ { X86::JL_4, Convert__AbsMem1_1, { MCK_jl, MCK_AbsMem } },
+ { X86::JLE_1, Convert__AbsMem1_1, { MCK_jle, MCK_AbsMem } },
+ { X86::JLE_4, Convert__AbsMem1_1, { MCK_jle, MCK_AbsMem } },
+ { X86::JMP_1, Convert__AbsMem1_1, { MCK_jmp, MCK_AbsMem } },
+ { X86::JMP_4, Convert__AbsMem1_1, { MCK_jmp, MCK_AbsMem } },
+ { X86::TAILJMPd, Convert__AbsMem1_1, { MCK_jmp, MCK_AbsMem } },
+ { X86::JMP64pcrel32, Convert__AbsMem1_1, { MCK_jmpq, MCK_AbsMem } },
+ { X86::JNE_1, Convert__AbsMem1_1, { MCK_jne, MCK_AbsMem } },
+ { X86::JNE_4, Convert__AbsMem1_1, { MCK_jne, MCK_AbsMem } },
+ { X86::JNO_1, Convert__AbsMem1_1, { MCK_jno, MCK_AbsMem } },
+ { X86::JNO_4, Convert__AbsMem1_1, { MCK_jno, MCK_AbsMem } },
+ { X86::JNP_1, Convert__AbsMem1_1, { MCK_jnp, MCK_AbsMem } },
+ { X86::JNP_4, Convert__AbsMem1_1, { MCK_jnp, MCK_AbsMem } },
+ { X86::JNS_1, Convert__AbsMem1_1, { MCK_jns, MCK_AbsMem } },
+ { X86::JNS_4, Convert__AbsMem1_1, { MCK_jns, MCK_AbsMem } },
+ { X86::JO_1, Convert__AbsMem1_1, { MCK_jo, MCK_AbsMem } },
+ { X86::JO_4, Convert__AbsMem1_1, { MCK_jo, MCK_AbsMem } },
+ { X86::JP_1, Convert__AbsMem1_1, { MCK_jp, MCK_AbsMem } },
+ { X86::JP_4, Convert__AbsMem1_1, { MCK_jp, MCK_AbsMem } },
+ { X86::JS_1, Convert__AbsMem1_1, { MCK_js, MCK_AbsMem } },
+ { X86::JS_4, Convert__AbsMem1_1, { MCK_js, MCK_AbsMem } },
+ { X86::LDMXCSR, Convert__Mem5_1, { MCK_ldmxcsr, MCK_Mem } },
+ { X86::LGDTm, Convert__Mem5_1, { MCK_lgdt, MCK_Mem } },
+ { X86::LIDTm, Convert__Mem5_1, { MCK_lidt, MCK_Mem } },
+ { X86::LLDT16r, Convert__Reg1_1, { MCK_lldtw, MCK_GR16 } },
+ { X86::LLDT16m, Convert__Mem5_1, { MCK_lldtw, MCK_Mem } },
+ { X86::LMSW16r, Convert__Reg1_1, { MCK_lmsww, MCK_GR16 } },
+ { X86::LMSW16m, Convert__Mem5_1, { MCK_lmsww, MCK_Mem } },
+ { X86::LOOP, Convert__AbsMem1_1, { MCK_loop, MCK_AbsMem } },
+ { X86::LOOPE, Convert__AbsMem1_1, { MCK_loope, MCK_AbsMem } },
+ { X86::LOOPNE, Convert__AbsMem1_1, { MCK_loopne, MCK_AbsMem } },
+ { X86::LRETI, Convert__Imm1_1, { MCK_lret, MCK_Imm } },
+ { X86::LTRr, Convert__Reg1_1, { MCK_ltrw, MCK_GR16 } },
+ { X86::LTRm, Convert__Mem5_1, { MCK_ltrw, MCK_Mem } },
+ { X86::MUL8r, Convert__Reg1_1, { MCK_mulb, MCK_GR8 } },
+ { X86::MUL8m, Convert__Mem5_1, { MCK_mulb, MCK_Mem } },
+ { X86::MUL32r, Convert__Reg1_1, { MCK_mull, MCK_GR32 } },
+ { X86::MUL32m, Convert__Mem5_1, { MCK_mull, MCK_Mem } },
+ { X86::MUL64r, Convert__Reg1_1, { MCK_mulq, MCK_GR64 } },
+ { X86::MUL64m, Convert__Mem5_1, { MCK_mulq, MCK_Mem } },
+ { X86::MUL16r, Convert__Reg1_1, { MCK_mulw, MCK_GR16 } },
+ { X86::MUL16m, Convert__Mem5_1, { MCK_mulw, MCK_Mem } },
+ { X86::NEG8r, Convert__Reg1_1__Tie0, { MCK_negb, MCK_GR8 } },
+ { X86::NEG8m, Convert__Mem5_1, { MCK_negb, MCK_Mem } },
+ { X86::NEG32r, Convert__Reg1_1__Tie0, { MCK_negl, MCK_GR32 } },
+ { X86::NEG32m, Convert__Mem5_1, { MCK_negl, MCK_Mem } },
+ { X86::NEG64r, Convert__Reg1_1__Tie0, { MCK_negq, MCK_GR64 } },
+ { X86::NEG64m, Convert__Mem5_1, { MCK_negq, MCK_Mem } },
+ { X86::NEG16r, Convert__Reg1_1__Tie0, { MCK_negw, MCK_GR16 } },
+ { X86::NEG16m, Convert__Mem5_1, { MCK_negw, MCK_Mem } },
+ { X86::NOOPL, Convert__Mem5_1, { MCK_nopl, MCK_Mem } },
+ { X86::NOOPW, Convert__Mem5_1, { MCK_nopw, MCK_Mem } },
+ { X86::NOT8r, Convert__Reg1_1__Tie0, { MCK_notb, MCK_GR8 } },
+ { X86::NOT8m, Convert__Mem5_1, { MCK_notb, MCK_Mem } },
+ { X86::NOT32r, Convert__Reg1_1__Tie0, { MCK_notl, MCK_GR32 } },
+ { X86::NOT32m, Convert__Mem5_1, { MCK_notl, MCK_Mem } },
+ { X86::NOT64r, Convert__Reg1_1__Tie0, { MCK_notq, MCK_GR64 } },
+ { X86::NOT64m, Convert__Mem5_1, { MCK_notq, MCK_Mem } },
+ { X86::NOT16r, Convert__Reg1_1__Tie0, { MCK_notw, MCK_GR16 } },
+ { X86::NOT16m, Convert__Mem5_1, { MCK_notw, MCK_Mem } },
+ { X86::POP32r, Convert__Reg1_1, { MCK_popl, MCK_GR32 } },
+ { X86::POP32rmr, Convert__Reg1_1, { MCK_popl, MCK_GR32 } },
{ X86::POPFS32, Convert, { MCK_popl, MCK_FS } },
{ X86::POPGS32, Convert, { MCK_popl, MCK_GS } },
- { X86::POP32rmm, Convert_Mem5_1, { MCK_popl, MCK_Mem } },
- { X86::POP64rmr, Convert_Reg1_1, { MCK_popq, MCK_GR64 } },
- { X86::POP64r, Convert_Reg1_1, { MCK_popq, MCK_GR64 } },
+ { X86::POP32rmm, Convert__Mem5_1, { MCK_popl, MCK_Mem } },
+ { X86::POP64r, Convert__Reg1_1, { MCK_popq, MCK_GR64 } },
+ { X86::POP64rmr, Convert__Reg1_1, { MCK_popq, MCK_GR64 } },
{ X86::POPFS64, Convert, { MCK_popq, MCK_FS } },
{ X86::POPGS64, Convert, { MCK_popq, MCK_GS } },
- { X86::POP64rmm, Convert_Mem5_1, { MCK_popq, MCK_Mem } },
- { X86::POP16r, Convert_Reg1_1, { MCK_popw, MCK_GR16 } },
- { X86::POP16rmr, Convert_Reg1_1, { MCK_popw, MCK_GR16 } },
+ { X86::POP64rmm, Convert__Mem5_1, { MCK_popq, MCK_Mem } },
+ { X86::POP16r, Convert__Reg1_1, { MCK_popw, MCK_GR16 } },
+ { X86::POP16rmr, Convert__Reg1_1, { MCK_popw, MCK_GR16 } },
{ X86::POPFS16, Convert, { MCK_popw, MCK_FS } },
{ X86::POPGS16, Convert, { MCK_popw, MCK_GS } },
- { X86::POP16rmm, Convert_Mem5_1, { MCK_popw, MCK_Mem } },
- { X86::PREFETCHNTA, Convert_Mem5_1, { MCK_prefetchnta, MCK_Mem } },
- { X86::PREFETCHT0, Convert_Mem5_1, { MCK_prefetcht0, MCK_Mem } },
- { X86::PREFETCHT1, Convert_Mem5_1, { MCK_prefetcht1, MCK_Mem } },
- { X86::PREFETCHT2, Convert_Mem5_1, { MCK_prefetcht2, MCK_Mem } },
- { X86::PUSH32r, Convert_Reg1_1, { MCK_pushl, MCK_GR32 } },
- { X86::PUSH32rmr, Convert_Reg1_1, { MCK_pushl, MCK_GR32 } },
+ { X86::POP16rmm, Convert__Mem5_1, { MCK_popw, MCK_Mem } },
+ { X86::PREFETCHNTA, Convert__Mem5_1, { MCK_prefetchnta, MCK_Mem } },
+ { X86::PREFETCHT0, Convert__Mem5_1, { MCK_prefetcht0, MCK_Mem } },
+ { X86::PREFETCHT1, Convert__Mem5_1, { MCK_prefetcht1, MCK_Mem } },
+ { X86::PREFETCHT2, Convert__Mem5_1, { MCK_prefetcht2, MCK_Mem } },
+ { X86::PUSH32r, Convert__Reg1_1, { MCK_pushl, MCK_GR32 } },
+ { X86::PUSH32rmr, Convert__Reg1_1, { MCK_pushl, MCK_GR32 } },
{ X86::PUSHFS32, Convert, { MCK_pushl, MCK_FS } },
{ X86::PUSHGS32, Convert, { MCK_pushl, MCK_GS } },
- { X86::PUSH32i32, Convert_Imm1_1, { MCK_pushl, MCK_Imm } },
- { X86::PUSH32i16, Convert_Imm1_1, { MCK_pushl, MCK_Imm } },
- { X86::PUSH32i8, Convert_Imm1_1, { MCK_pushl, MCK_Imm } },
- { X86::PUSH32rmm, Convert_Mem5_1, { MCK_pushl, MCK_Mem } },
- { X86::PUSH64r, Convert_Reg1_1, { MCK_pushq, MCK_GR64 } },
- { X86::PUSH64rmr, Convert_Reg1_1, { MCK_pushq, MCK_GR64 } },
+ { X86::PUSH32i16, Convert__Imm1_1, { MCK_pushl, MCK_Imm } },
+ { X86::PUSH32i32, Convert__Imm1_1, { MCK_pushl, MCK_Imm } },
+ { X86::PUSH32i8, Convert__Imm1_1, { MCK_pushl, MCK_Imm } },
+ { X86::PUSH32rmm, Convert__Mem5_1, { MCK_pushl, MCK_Mem } },
+ { X86::PUSH64r, Convert__Reg1_1, { MCK_pushq, MCK_GR64 } },
+ { X86::PUSH64rmr, Convert__Reg1_1, { MCK_pushq, MCK_GR64 } },
{ X86::PUSHFS64, Convert, { MCK_pushq, MCK_FS } },
{ X86::PUSHGS64, Convert, { MCK_pushq, MCK_GS } },
- { X86::PUSH64i8, Convert_Imm1_1, { MCK_pushq, MCK_Imm } },
- { X86::PUSH64i32, Convert_Imm1_1, { MCK_pushq, MCK_Imm } },
- { X86::PUSH64i16, Convert_Imm1_1, { MCK_pushq, MCK_Imm } },
- { X86::PUSH64rmm, Convert_Mem5_1, { MCK_pushq, MCK_Mem } },
- { X86::PUSH16r, Convert_Reg1_1, { MCK_pushw, MCK_GR16 } },
- { X86::PUSH16rmr, Convert_Reg1_1, { MCK_pushw, MCK_GR16 } },
+ { X86::PUSH64i16, Convert__Imm1_1, { MCK_pushq, MCK_Imm } },
+ { X86::PUSH64i32, Convert__Imm1_1, { MCK_pushq, MCK_Imm } },
+ { X86::PUSH64i8, Convert__Imm1_1, { MCK_pushq, MCK_Imm } },
+ { X86::PUSH64rmm, Convert__Mem5_1, { MCK_pushq, MCK_Mem } },
+ { X86::PUSH16r, Convert__Reg1_1, { MCK_pushw, MCK_GR16 } },
+ { X86::PUSH16rmr, Convert__Reg1_1, { MCK_pushw, MCK_GR16 } },
{ X86::PUSHFS16, Convert, { MCK_pushw, MCK_FS } },
{ X86::PUSHGS16, Convert, { MCK_pushw, MCK_GS } },
- { X86::PUSH16rmm, Convert_Mem5_1, { MCK_pushw, MCK_Mem } },
- { X86::RETI, Convert_Imm1_1, { MCK_ret, MCK_Imm } },
- { X86::ROL8r1, Convert_Reg1_1Imp, { MCK_rolb, MCK_GR8 } },
- { X86::ROL8m1, Convert_Mem5_1, { MCK_rolb, MCK_Mem } },
- { X86::ROL32r1, Convert_Reg1_1Imp, { MCK_roll, MCK_GR32 } },
- { X86::ROL32m1, Convert_Mem5_1, { MCK_roll, MCK_Mem } },
- { X86::ROL64r1, Convert_Reg1_1Imp, { MCK_rolq, MCK_GR64 } },
- { X86::ROL64m1, Convert_Mem5_1, { MCK_rolq, MCK_Mem } },
- { X86::ROL16r1, Convert_Reg1_1Imp, { MCK_rolw, MCK_GR16 } },
- { X86::ROL16m1, Convert_Mem5_1, { MCK_rolw, MCK_Mem } },
- { X86::ROR8r1, Convert_Reg1_1Imp, { MCK_rorb, MCK_GR8 } },
- { X86::ROR8m1, Convert_Mem5_1, { MCK_rorb, MCK_Mem } },
- { X86::ROR32r1, Convert_Reg1_1Imp, { MCK_rorl, MCK_GR32 } },
- { X86::ROR32m1, Convert_Mem5_1, { MCK_rorl, MCK_Mem } },
- { X86::ROR64r1, Convert_Reg1_1Imp, { MCK_rorq, MCK_GR64 } },
- { X86::ROR64m1, Convert_Mem5_1, { MCK_rorq, MCK_Mem } },
- { X86::ROR16r1, Convert_Reg1_1Imp, { MCK_rorw, MCK_GR16 } },
- { X86::ROR16m1, Convert_Mem5_1, { MCK_rorw, MCK_Mem } },
- { X86::SAR8r1, Convert_Reg1_1Imp, { MCK_sarb, MCK_GR8 } },
- { X86::SAR8m1, Convert_Mem5_1, { MCK_sarb, MCK_Mem } },
- { X86::SAR32r1, Convert_Reg1_1Imp, { MCK_sarl, MCK_GR32 } },
- { X86::SAR32m1, Convert_Mem5_1, { MCK_sarl, MCK_Mem } },
- { X86::SAR64r1, Convert_Reg1_1Imp, { MCK_sarq, MCK_GR64 } },
- { X86::SAR64m1, Convert_Mem5_1, { MCK_sarq, MCK_Mem } },
- { X86::SAR16r1, Convert_Reg1_1Imp, { MCK_sarw, MCK_GR16 } },
- { X86::SAR16m1, Convert_Mem5_1, { MCK_sarw, MCK_Mem } },
- { X86::SETAr, Convert_Reg1_1, { MCK_seta, MCK_GR8 } },
- { X86::SETAm, Convert_Mem5_1, { MCK_seta, MCK_Mem } },
- { X86::SETAEr, Convert_Reg1_1, { MCK_setae, MCK_GR8 } },
- { X86::SETAEm, Convert_Mem5_1, { MCK_setae, MCK_Mem } },
- { X86::SETBr, Convert_Reg1_1, { MCK_setb, MCK_GR8 } },
- { X86::SETBm, Convert_Mem5_1, { MCK_setb, MCK_Mem } },
- { X86::SETBEr, Convert_Reg1_1, { MCK_setbe, MCK_GR8 } },
- { X86::SETBEm, Convert_Mem5_1, { MCK_setbe, MCK_Mem } },
- { X86::SETEr, Convert_Reg1_1, { MCK_sete, MCK_GR8 } },
- { X86::SETEm, Convert_Mem5_1, { MCK_sete, MCK_Mem } },
- { X86::SETGr, Convert_Reg1_1, { MCK_setg, MCK_GR8 } },
- { X86::SETGm, Convert_Mem5_1, { MCK_setg, MCK_Mem } },
- { X86::SETGEr, Convert_Reg1_1, { MCK_setge, MCK_GR8 } },
- { X86::SETGEm, Convert_Mem5_1, { MCK_setge, MCK_Mem } },
- { X86::SETLr, Convert_Reg1_1, { MCK_setl, MCK_GR8 } },
- { X86::SETLm, Convert_Mem5_1, { MCK_setl, MCK_Mem } },
- { X86::SETLEr, Convert_Reg1_1, { MCK_setle, MCK_GR8 } },
- { X86::SETLEm, Convert_Mem5_1, { MCK_setle, MCK_Mem } },
- { X86::SETNEr, Convert_Reg1_1, { MCK_setne, MCK_GR8 } },
- { X86::SETNEm, Convert_Mem5_1, { MCK_setne, MCK_Mem } },
- { X86::SETNOr, Convert_Reg1_1, { MCK_setno, MCK_GR8 } },
- { X86::SETNOm, Convert_Mem5_1, { MCK_setno, MCK_Mem } },
- { X86::SETNPr, Convert_Reg1_1, { MCK_setnp, MCK_GR8 } },
- { X86::SETNPm, Convert_Mem5_1, { MCK_setnp, MCK_Mem } },
- { X86::SETNSr, Convert_Reg1_1, { MCK_setns, MCK_GR8 } },
- { X86::SETNSm, Convert_Mem5_1, { MCK_setns, MCK_Mem } },
- { X86::SETOr, Convert_Reg1_1, { MCK_seto, MCK_GR8 } },
- { X86::SETOm, Convert_Mem5_1, { MCK_seto, MCK_Mem } },
- { X86::SETPr, Convert_Reg1_1, { MCK_setp, MCK_GR8 } },
- { X86::SETPm, Convert_Mem5_1, { MCK_setp, MCK_Mem } },
- { X86::SETSr, Convert_Reg1_1, { MCK_sets, MCK_GR8 } },
- { X86::SETSm, Convert_Mem5_1, { MCK_sets, MCK_Mem } },
- { X86::SGDTm, Convert_Mem5_1, { MCK_sgdt, MCK_Mem } },
- { X86::SHL8r1, Convert_Reg1_1Imp, { MCK_shlb, MCK_GR8 } },
- { X86::SHL8m1, Convert_Mem5_1, { MCK_shlb, MCK_Mem } },
- { X86::SHL32r1, Convert_Reg1_1Imp, { MCK_shll, MCK_GR32 } },
- { X86::SHL32m1, Convert_Mem5_1, { MCK_shll, MCK_Mem } },
- { X86::SHL64r1, Convert_Reg1_1Imp, { MCK_shlq, MCK_GR64 } },
- { X86::SHL64m1, Convert_Mem5_1, { MCK_shlq, MCK_Mem } },
- { X86::SHL16r1, Convert_Reg1_1Imp, { MCK_shlw, MCK_GR16 } },
- { X86::SHL16m1, Convert_Mem5_1, { MCK_shlw, MCK_Mem } },
- { X86::SHR8r1, Convert_Reg1_1Imp, { MCK_shrb, MCK_GR8 } },
- { X86::SHR8m1, Convert_Mem5_1, { MCK_shrb, MCK_Mem } },
- { X86::SHR32r1, Convert_Reg1_1Imp, { MCK_shrl, MCK_GR32 } },
- { X86::SHR32m1, Convert_Mem5_1, { MCK_shrl, MCK_Mem } },
- { X86::SHR64r1, Convert_Reg1_1Imp, { MCK_shrq, MCK_GR64 } },
- { X86::SHR64m1, Convert_Mem5_1, { MCK_shrq, MCK_Mem } },
- { X86::SHR16r1, Convert_Reg1_1Imp, { MCK_shrw, MCK_GR16 } },
- { X86::SHR16m1, Convert_Mem5_1, { MCK_shrw, MCK_Mem } },
- { X86::SIDTm, Convert_Mem5_1, { MCK_sidt, MCK_Mem } },
- { X86::SLDT64r, Convert_Reg1_1, { MCK_sldtq, MCK_GR64 } },
- { X86::SLDT64m, Convert_Mem5_1, { MCK_sldtq, MCK_Mem } },
- { X86::SLDT16r, Convert_Reg1_1, { MCK_sldtw, MCK_GR16 } },
- { X86::SLDT16m, Convert_Mem5_1, { MCK_sldtw, MCK_Mem } },
- { X86::SMSW32r, Convert_Reg1_1, { MCK_smswl, MCK_GR32 } },
- { X86::SMSW64r, Convert_Reg1_1, { MCK_smswq, MCK_GR64 } },
- { X86::SMSW16r, Convert_Reg1_1, { MCK_smsww, MCK_GR16 } },
- { X86::SMSW16m, Convert_Mem5_1, { MCK_smsww, MCK_Mem } },
- { X86::STMXCSR, Convert_Mem5_1, { MCK_stmxcsr, MCK_Mem } },
- { X86::STRr, Convert_Reg1_1, { MCK_strw, MCK_GR16 } },
- { X86::STRm, Convert_Mem5_1, { MCK_strw, MCK_Mem } },
- { X86::VERRr, Convert_Reg1_1, { MCK_verr, MCK_GR16 } },
- { X86::VERRm, Convert_Mem5_1, { MCK_verr, MCK_Mem } },
- { X86::VERWr, Convert_Reg1_1, { MCK_verw, MCK_GR16 } },
- { X86::VERWm, Convert_Mem5_1, { MCK_verw, MCK_Mem } },
- { X86::VMCLEARm, Convert_Mem5_1, { MCK_vmclear, MCK_Mem } },
- { X86::VMPTRLDm, Convert_Mem5_1, { MCK_vmptrld, MCK_Mem } },
- { X86::VMPTRSTm, Convert_Mem5_1, { MCK_vmptrst, MCK_Mem } },
- { X86::VMXON, Convert_Mem5_1, { MCK_vmxon, MCK_Mem } },
- { X86::ADC8rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_adcb, MCK_GR8, MCK_GR8 } },
- { X86::ADC8rr, Convert_Reg1_2_ImpReg1_1, { MCK_adcb, MCK_GR8, MCK_GR8 } },
- { X86::ADC8mr, Convert_Mem5_2_Reg1_1, { MCK_adcb, MCK_GR8, MCK_Mem } },
- { X86::ADC8i8, Convert_Imm1_1, { MCK_adcb, MCK_Imm, MCK_AL } },
- { X86::ADC8ri, Convert_Reg1_2_ImpImm1_1, { MCK_adcb, MCK_Imm, MCK_GR8 } },
- { X86::ADC8mi, Convert_Mem5_2_Imm1_1, { MCK_adcb, MCK_Imm, MCK_Mem } },
- { X86::ADC8rm, Convert_Reg1_2_ImpMem5_1, { MCK_adcb, MCK_Mem, MCK_GR8 } },
- { X86::ADC32rr, Convert_Reg1_2_ImpReg1_1, { MCK_adcl, MCK_GR32, MCK_GR32 } },
- { X86::ADC32rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_adcl, MCK_GR32, MCK_GR32 } },
- { X86::ADC32mr, Convert_Mem5_2_Reg1_1, { MCK_adcl, MCK_GR32, MCK_Mem } },
- { X86::ADC32ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_adcl, MCK_ImmSExt8, MCK_GR32 } },
- { X86::ADC32mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_adcl, MCK_ImmSExt8, MCK_Mem } },
- { X86::ADC32i32, Convert_Imm1_1, { MCK_adcl, MCK_Imm, MCK_EAX } },
- { X86::ADC32ri, Convert_Reg1_2_ImpImm1_1, { MCK_adcl, MCK_Imm, MCK_GR32 } },
- { X86::ADC32mi, Convert_Mem5_2_Imm1_1, { MCK_adcl, MCK_Imm, MCK_Mem } },
- { X86::ADC32rm, Convert_Reg1_2_ImpMem5_1, { MCK_adcl, MCK_Mem, MCK_GR32 } },
- { X86::ADC64rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_adcq, MCK_GR64, MCK_GR32 } },
- { X86::ADC64rr, Convert_Reg1_2_ImpReg1_1, { MCK_adcq, MCK_GR64, MCK_GR64 } },
- { X86::ADC64mr, Convert_Mem5_2_Reg1_1, { MCK_adcq, MCK_GR64, MCK_Mem } },
- { X86::ADC64ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_adcq, MCK_ImmSExt8, MCK_GR64 } },
- { X86::ADC64mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_adcq, MCK_ImmSExt8, MCK_Mem } },
- { X86::ADC64i32, Convert_Imm1_1, { MCK_adcq, MCK_Imm, MCK_RAX } },
- { X86::ADC64ri32, Convert_Reg1_2_ImpImm1_1, { MCK_adcq, MCK_Imm, MCK_GR64 } },
- { X86::ADC64mi32, Convert_Mem5_2_Imm1_1, { MCK_adcq, MCK_Imm, MCK_Mem } },
- { X86::ADC64rm, Convert_Reg1_2_ImpMem5_1, { MCK_adcq, MCK_Mem, MCK_GR64 } },
- { X86::ADC16rr, Convert_Reg1_2_ImpReg1_1, { MCK_adcw, MCK_GR16, MCK_GR16 } },
- { X86::ADC16rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_adcw, MCK_GR16, MCK_GR16 } },
- { X86::ADC16mr, Convert_Mem5_2_Reg1_1, { MCK_adcw, MCK_GR16, MCK_Mem } },
- { X86::ADC16ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_adcw, MCK_ImmSExt8, MCK_GR16 } },
- { X86::ADC16mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_adcw, MCK_ImmSExt8, MCK_Mem } },
- { X86::ADC16i16, Convert_Imm1_1, { MCK_adcw, MCK_Imm, MCK_AX } },
- { X86::ADC16ri, Convert_Reg1_2_ImpImm1_1, { MCK_adcw, MCK_Imm, MCK_GR16 } },
- { X86::ADC16mi, Convert_Mem5_2_Imm1_1, { MCK_adcw, MCK_Imm, MCK_Mem } },
- { X86::ADC16rm, Convert_Reg1_2_ImpMem5_1, { MCK_adcw, MCK_Mem, MCK_GR16 } },
- { X86::ADD8mrmrr, Convert_Reg1_2_ImpReg1_1, { MCK_addb, MCK_GR8, MCK_GR8 } },
- { X86::ADD8rr, Convert_Reg1_2_ImpReg1_1, { MCK_addb, MCK_GR8, MCK_GR8 } },
- { X86::ADD8mr, Convert_Mem5_2_Reg1_1, { MCK_addb, MCK_GR8, MCK_Mem } },
- { X86::ADD8i8, Convert_Imm1_1, { MCK_addb, MCK_Imm, MCK_AL } },
- { X86::ADD8ri, Convert_Reg1_2_ImpImm1_1, { MCK_addb, MCK_Imm, MCK_GR8 } },
- { X86::ADD8mi, Convert_Mem5_2_Imm1_1, { MCK_addb, MCK_Imm, MCK_Mem } },
- { X86::ADD8rm, Convert_Reg1_2_ImpMem5_1, { MCK_addb, MCK_Mem, MCK_GR8 } },
- { X86::ADD32mrmrr, Convert_Reg1_2_ImpReg1_1, { MCK_addl, MCK_GR16, MCK_GR16 } },
- { X86::ADD32rr, Convert_Reg1_2_ImpReg1_1, { MCK_addl, MCK_GR32, MCK_GR32 } },
- { X86::ADD32mr, Convert_Mem5_2_Reg1_1, { MCK_addl, MCK_GR32, MCK_Mem } },
- { X86::ADD64mrmrr, Convert_Reg1_2_ImpReg1_1, { MCK_addl, MCK_GR64, MCK_GR64 } },
- { X86::ADD32ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_addl, MCK_ImmSExt8, MCK_GR32 } },
- { X86::ADD32mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_addl, MCK_ImmSExt8, MCK_Mem } },
- { X86::ADD32i32, Convert_Imm1_1, { MCK_addl, MCK_Imm, MCK_EAX } },
- { X86::ADD32ri, Convert_Reg1_2_ImpImm1_1, { MCK_addl, MCK_Imm, MCK_GR32 } },
- { X86::ADD32mi, Convert_Mem5_2_Imm1_1, { MCK_addl, MCK_Imm, MCK_Mem } },
- { X86::ADD32rm, Convert_Reg1_2_ImpMem5_1, { MCK_addl, MCK_Mem, MCK_GR32 } },
- { X86::ADDPDrr, Convert_Reg1_2_ImpReg1_1, { MCK_addpd, MCK_FR32, MCK_FR32 } },
- { X86::ADDPDrm, Convert_Reg1_2_ImpMem5_1, { MCK_addpd, MCK_Mem, MCK_FR32 } },
- { X86::ADDPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_addps, MCK_FR32, MCK_FR32 } },
- { X86::ADDPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_addps, MCK_Mem, MCK_FR32 } },
- { X86::ADD64rr, Convert_Reg1_2_ImpReg1_1, { MCK_addq, MCK_GR64, MCK_GR64 } },
- { X86::ADD64mr, Convert_Mem5_2_Reg1_1, { MCK_addq, MCK_GR64, MCK_Mem } },
- { X86::ADD64ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_addq, MCK_ImmSExt8, MCK_GR64 } },
- { X86::ADD64mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_addq, MCK_ImmSExt8, MCK_Mem } },
- { X86::ADD64i32, Convert_Imm1_1, { MCK_addq, MCK_Imm, MCK_RAX } },
- { X86::ADD64ri32, Convert_Reg1_2_ImpImm1_1, { MCK_addq, MCK_Imm, MCK_GR64 } },
- { X86::ADD64mi32, Convert_Mem5_2_Imm1_1, { MCK_addq, MCK_Imm, MCK_Mem } },
- { X86::ADD64rm, Convert_Reg1_2_ImpMem5_1, { MCK_addq, MCK_Mem, MCK_GR64 } },
- { X86::ADDSDrr, Convert_Reg1_2_ImpReg1_1, { MCK_addsd, MCK_FR32, MCK_FR32 } },
- { X86::ADDSDrm, Convert_Reg1_2_ImpMem5_1, { MCK_addsd, MCK_Mem, MCK_FR32 } },
- { X86::ADDSSrr, Convert_Reg1_2_ImpReg1_1, { MCK_addss, MCK_FR32, MCK_FR32 } },
- { X86::ADDSSrm, Convert_Reg1_2_ImpMem5_1, { MCK_addss, MCK_Mem, MCK_FR32 } },
- { X86::ADDSUBPDrr, Convert_Reg1_2_ImpReg1_1, { MCK_addsubpd, MCK_FR32, MCK_FR32 } },
- { X86::ADDSUBPDrm, Convert_Reg1_2_ImpMem5_1, { MCK_addsubpd, MCK_Mem, MCK_FR32 } },
- { X86::ADDSUBPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_addsubps, MCK_FR32, MCK_FR32 } },
- { X86::ADDSUBPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_addsubps, MCK_Mem, MCK_FR32 } },
- { X86::ADD16rr, Convert_Reg1_2_ImpReg1_1, { MCK_addw, MCK_GR16, MCK_GR16 } },
- { X86::ADD16mrmrr, Convert_Reg1_2_ImpReg1_1, { MCK_addw, MCK_GR16, MCK_GR16 } },
- { X86::ADD16mr, Convert_Mem5_2_Reg1_1, { MCK_addw, MCK_GR16, MCK_Mem } },
- { X86::ADD16ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_addw, MCK_ImmSExt8, MCK_GR16 } },
- { X86::ADD16mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_addw, MCK_ImmSExt8, MCK_Mem } },
- { X86::ADD16i16, Convert_Imm1_1, { MCK_addw, MCK_Imm, MCK_AX } },
- { X86::ADD16ri, Convert_Reg1_2_ImpImm1_1, { MCK_addw, MCK_Imm, MCK_GR16 } },
- { X86::ADD16mi, Convert_Mem5_2_Imm1_1, { MCK_addw, MCK_Imm, MCK_Mem } },
- { X86::ADD16rm, Convert_Reg1_2_ImpMem5_1, { MCK_addw, MCK_Mem, MCK_GR16 } },
- { X86::AND8rr, Convert_Reg1_2_ImpReg1_1, { MCK_andb, MCK_GR8, MCK_GR8 } },
- { X86::AND8rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_andb, MCK_GR8, MCK_GR8 } },
- { X86::AND8mr, Convert_Mem5_2_Reg1_1, { MCK_andb, MCK_GR8, MCK_Mem } },
- { X86::AND8i8, Convert_Imm1_1, { MCK_andb, MCK_Imm, MCK_AL } },
- { X86::AND8ri, Convert_Reg1_2_ImpImm1_1, { MCK_andb, MCK_Imm, MCK_GR8 } },
- { X86::AND8mi, Convert_Mem5_2_Imm1_1, { MCK_andb, MCK_Imm, MCK_Mem } },
- { X86::AND8rm, Convert_Reg1_2_ImpMem5_1, { MCK_andb, MCK_Mem, MCK_GR8 } },
- { X86::AND32rr, Convert_Reg1_2_ImpReg1_1, { MCK_andl, MCK_GR32, MCK_GR32 } },
- { X86::AND32rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_andl, MCK_GR32, MCK_GR32 } },
- { X86::AND32mr, Convert_Mem5_2_Reg1_1, { MCK_andl, MCK_GR32, MCK_Mem } },
- { X86::AND32ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_andl, MCK_ImmSExt8, MCK_GR32 } },
- { X86::AND32mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_andl, MCK_ImmSExt8, MCK_Mem } },
- { X86::AND32i32, Convert_Imm1_1, { MCK_andl, MCK_Imm, MCK_EAX } },
- { X86::AND32ri, Convert_Reg1_2_ImpImm1_1, { MCK_andl, MCK_Imm, MCK_GR32 } },
- { X86::AND32mi, Convert_Mem5_2_Imm1_1, { MCK_andl, MCK_Imm, MCK_Mem } },
- { X86::AND32rm, Convert_Reg1_2_ImpMem5_1, { MCK_andl, MCK_Mem, MCK_GR32 } },
- { X86::FsANDNPDrr, Convert_Reg1_2_ImpReg1_1, { MCK_andnpd, MCK_FR32, MCK_FR32 } },
- { X86::ANDNPDrr, Convert_Reg1_2_ImpReg1_1, { MCK_andnpd, MCK_FR32, MCK_FR32 } },
- { X86::ANDNPDrm, Convert_Reg1_2_ImpMem5_1, { MCK_andnpd, MCK_Mem, MCK_FR32 } },
- { X86::FsANDNPDrm, Convert_Reg1_2_ImpMem5_1, { MCK_andnpd, MCK_Mem, MCK_FR32 } },
- { X86::ANDNPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_andnps, MCK_FR32, MCK_FR32 } },
- { X86::FsANDNPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_andnps, MCK_FR32, MCK_FR32 } },
- { X86::ANDNPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_andnps, MCK_Mem, MCK_FR32 } },
- { X86::FsANDNPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_andnps, MCK_Mem, MCK_FR32 } },
- { X86::ANDPDrr, Convert_Reg1_2_ImpReg1_1, { MCK_andpd, MCK_FR32, MCK_FR32 } },
- { X86::FsANDPDrr, Convert_Reg1_2_ImpReg1_1, { MCK_andpd, MCK_FR32, MCK_FR32 } },
- { X86::ANDPDrm, Convert_Reg1_2_ImpMem5_1, { MCK_andpd, MCK_Mem, MCK_FR32 } },
- { X86::FsANDPDrm, Convert_Reg1_2_ImpMem5_1, { MCK_andpd, MCK_Mem, MCK_FR32 } },
- { X86::ANDPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_andps, MCK_FR32, MCK_FR32 } },
- { X86::FsANDPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_andps, MCK_FR32, MCK_FR32 } },
- { X86::ANDPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_andps, MCK_Mem, MCK_FR32 } },
- { X86::FsANDPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_andps, MCK_Mem, MCK_FR32 } },
- { X86::AND64rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_andq, MCK_GR64, MCK_GR64 } },
- { X86::AND64rr, Convert_Reg1_2_ImpReg1_1, { MCK_andq, MCK_GR64, MCK_GR64 } },
- { X86::AND64mr, Convert_Mem5_2_Reg1_1, { MCK_andq, MCK_GR64, MCK_Mem } },
- { X86::AND64ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_andq, MCK_ImmSExt8, MCK_GR64 } },
- { X86::AND64mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_andq, MCK_ImmSExt8, MCK_Mem } },
- { X86::AND64i32, Convert_Imm1_1, { MCK_andq, MCK_Imm, MCK_RAX } },
- { X86::AND64ri32, Convert_Reg1_2_ImpImm1_1, { MCK_andq, MCK_Imm, MCK_GR64 } },
- { X86::AND64mi32, Convert_Mem5_2_Imm1_1, { MCK_andq, MCK_Imm, MCK_Mem } },
- { X86::AND64rm, Convert_Reg1_2_ImpMem5_1, { MCK_andq, MCK_Mem, MCK_GR64 } },
- { X86::AND16rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_andw, MCK_GR16, MCK_GR16 } },
- { X86::AND16rr, Convert_Reg1_2_ImpReg1_1, { MCK_andw, MCK_GR16, MCK_GR16 } },
- { X86::AND16mr, Convert_Mem5_2_Reg1_1, { MCK_andw, MCK_GR16, MCK_Mem } },
- { X86::AND16ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_andw, MCK_ImmSExt8, MCK_GR16 } },
- { X86::AND16mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_andw, MCK_ImmSExt8, MCK_Mem } },
- { X86::AND16i16, Convert_Imm1_1, { MCK_andw, MCK_Imm, MCK_AX } },
- { X86::AND16ri, Convert_Reg1_2_ImpImm1_1, { MCK_andw, MCK_Imm, MCK_GR16 } },
- { X86::AND16mi, Convert_Mem5_2_Imm1_1, { MCK_andw, MCK_Imm, MCK_Mem } },
- { X86::AND16rm, Convert_Reg1_2_ImpMem5_1, { MCK_andw, MCK_Mem, MCK_GR16 } },
- { X86::BSF32rr, Convert_Reg1_2_Reg1_1, { MCK_bsfl, MCK_GR32, MCK_GR32 } },
- { X86::BSF32rm, Convert_Reg1_2_Mem5_1, { MCK_bsfl, MCK_Mem, MCK_GR32 } },
- { X86::BSF64rr, Convert_Reg1_2_Reg1_1, { MCK_bsfq, MCK_GR64, MCK_GR64 } },
- { X86::BSF64rm, Convert_Reg1_2_Mem5_1, { MCK_bsfq, MCK_Mem, MCK_GR64 } },
- { X86::BSF16rr, Convert_Reg1_2_Reg1_1, { MCK_bsfw, MCK_GR16, MCK_GR16 } },
- { X86::BSF16rm, Convert_Reg1_2_Mem5_1, { MCK_bsfw, MCK_Mem, MCK_GR16 } },
- { X86::BSR32rr, Convert_Reg1_2_Reg1_1, { MCK_bsrl, MCK_GR32, MCK_GR32 } },
- { X86::BSR32rm, Convert_Reg1_2_Mem5_1, { MCK_bsrl, MCK_Mem, MCK_GR32 } },
- { X86::BSR64rr, Convert_Reg1_2_Reg1_1, { MCK_bsrq, MCK_GR64, MCK_GR64 } },
- { X86::BSR64rm, Convert_Reg1_2_Mem5_1, { MCK_bsrq, MCK_Mem, MCK_GR64 } },
- { X86::BSR16rr, Convert_Reg1_2_Reg1_1, { MCK_bsrw, MCK_GR16, MCK_GR16 } },
- { X86::BSR16rm, Convert_Reg1_2_Mem5_1, { MCK_bsrw, MCK_Mem, MCK_GR16 } },
- { X86::BTC32rr, Convert_Reg1_2_Reg1_1, { MCK_btcl, MCK_GR32, MCK_GR32 } },
- { X86::BTC32mr, Convert_Mem5_2_Reg1_1, { MCK_btcl, MCK_GR32, MCK_Mem } },
- { X86::BTC32ri8, Convert_Reg1_2_ImmSExt81_1, { MCK_btcl, MCK_ImmSExt8, MCK_GR32 } },
- { X86::BTC32mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_btcl, MCK_ImmSExt8, MCK_Mem } },
- { X86::BTC64rr, Convert_Reg1_2_Reg1_1, { MCK_btcq, MCK_GR64, MCK_GR64 } },
- { X86::BTC64mr, Convert_Mem5_2_Reg1_1, { MCK_btcq, MCK_GR64, MCK_Mem } },
- { X86::BTC64ri8, Convert_Reg1_2_ImmSExt81_1, { MCK_btcq, MCK_ImmSExt8, MCK_GR64 } },
- { X86::BTC64mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_btcq, MCK_ImmSExt8, MCK_Mem } },
- { X86::BTC16rr, Convert_Reg1_2_Reg1_1, { MCK_btcw, MCK_GR16, MCK_GR16 } },
- { X86::BTC16mr, Convert_Mem5_2_Reg1_1, { MCK_btcw, MCK_GR16, MCK_Mem } },
- { X86::BTC16ri8, Convert_Reg1_2_ImmSExt81_1, { MCK_btcw, MCK_ImmSExt8, MCK_GR16 } },
- { X86::BTC16mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_btcw, MCK_ImmSExt8, MCK_Mem } },
- { X86::BT32rr, Convert_Reg1_2_Reg1_1, { MCK_btl, MCK_GR32, MCK_GR32 } },
- { X86::BT32mr, Convert_Mem5_2_Reg1_1, { MCK_btl, MCK_GR32, MCK_Mem } },
- { X86::BT32ri8, Convert_Reg1_2_ImmSExt81_1, { MCK_btl, MCK_ImmSExt8, MCK_GR32 } },
- { X86::BT32mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_btl, MCK_ImmSExt8, MCK_Mem } },
- { X86::BT64rr, Convert_Reg1_2_Reg1_1, { MCK_btq, MCK_GR64, MCK_GR64 } },
- { X86::BT64mr, Convert_Mem5_2_Reg1_1, { MCK_btq, MCK_GR64, MCK_Mem } },
- { X86::BT64ri8, Convert_Reg1_2_ImmSExt81_1, { MCK_btq, MCK_ImmSExt8, MCK_GR64 } },
- { X86::BT64mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_btq, MCK_ImmSExt8, MCK_Mem } },
- { X86::BTR32rr, Convert_Reg1_2_Reg1_1, { MCK_btrl, MCK_GR32, MCK_GR32 } },
- { X86::BTR32mr, Convert_Mem5_2_Reg1_1, { MCK_btrl, MCK_GR32, MCK_Mem } },
- { X86::BTR32ri8, Convert_Reg1_2_ImmSExt81_1, { MCK_btrl, MCK_ImmSExt8, MCK_GR32 } },
- { X86::BTR32mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_btrl, MCK_ImmSExt8, MCK_Mem } },
- { X86::BTR64rr, Convert_Reg1_2_Reg1_1, { MCK_btrq, MCK_GR64, MCK_GR64 } },
- { X86::BTR64mr, Convert_Mem5_2_Reg1_1, { MCK_btrq, MCK_GR64, MCK_Mem } },
- { X86::BTR64ri8, Convert_Reg1_2_ImmSExt81_1, { MCK_btrq, MCK_ImmSExt8, MCK_GR64 } },
- { X86::BTR64mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_btrq, MCK_ImmSExt8, MCK_Mem } },
- { X86::BTR16rr, Convert_Reg1_2_Reg1_1, { MCK_btrw, MCK_GR16, MCK_GR16 } },
- { X86::BTR16mr, Convert_Mem5_2_Reg1_1, { MCK_btrw, MCK_GR16, MCK_Mem } },
- { X86::BTR16ri8, Convert_Reg1_2_ImmSExt81_1, { MCK_btrw, MCK_ImmSExt8, MCK_GR16 } },
- { X86::BTR16mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_btrw, MCK_ImmSExt8, MCK_Mem } },
- { X86::BTS32rr, Convert_Reg1_2_Reg1_1, { MCK_btsl, MCK_GR32, MCK_GR32 } },
- { X86::BTS32mr, Convert_Mem5_2_Reg1_1, { MCK_btsl, MCK_GR32, MCK_Mem } },
- { X86::BTS32ri8, Convert_Reg1_2_ImmSExt81_1, { MCK_btsl, MCK_ImmSExt8, MCK_GR32 } },
- { X86::BTS32mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_btsl, MCK_ImmSExt8, MCK_Mem } },
- { X86::BTS64rr, Convert_Reg1_2_Reg1_1, { MCK_btsq, MCK_GR64, MCK_GR64 } },
- { X86::BTS64mr, Convert_Mem5_2_Reg1_1, { MCK_btsq, MCK_GR64, MCK_Mem } },
- { X86::BTS64ri8, Convert_Reg1_2_ImmSExt81_1, { MCK_btsq, MCK_ImmSExt8, MCK_GR64 } },
- { X86::BTS64mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_btsq, MCK_ImmSExt8, MCK_Mem } },
- { X86::BTS16rr, Convert_Reg1_2_Reg1_1, { MCK_btsw, MCK_GR16, MCK_GR16 } },
- { X86::BTS16mr, Convert_Mem5_2_Reg1_1, { MCK_btsw, MCK_GR16, MCK_Mem } },
- { X86::BTS16ri8, Convert_Reg1_2_ImmSExt81_1, { MCK_btsw, MCK_ImmSExt8, MCK_GR16 } },
- { X86::BTS16mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_btsw, MCK_ImmSExt8, MCK_Mem } },
- { X86::BT16rr, Convert_Reg1_2_Reg1_1, { MCK_btw, MCK_GR16, MCK_GR16 } },
- { X86::BT16mr, Convert_Mem5_2_Reg1_1, { MCK_btw, MCK_GR16, MCK_Mem } },
- { X86::BT16ri8, Convert_Reg1_2_ImmSExt81_1, { MCK_btw, MCK_ImmSExt8, MCK_GR16 } },
- { X86::BT16mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_btw, MCK_ImmSExt8, MCK_Mem } },
- { X86::CALL32r, Convert_Reg1_2, { MCK_call, MCK__STAR_, MCK_GR32 } },
- { X86::WINCALL64r, Convert_Reg1_2, { MCK_call, MCK__STAR_, MCK_GR64 } },
- { X86::CALL32m, Convert_Mem5_2, { MCK_call, MCK__STAR_, MCK_Mem } },
- { X86::WINCALL64m, Convert_Mem5_2, { MCK_call, MCK__STAR_, MCK_Mem } },
- { X86::CALL64r, Convert_Reg1_2, { MCK_callq, MCK__STAR_, MCK_GR64 } },
- { X86::CALL64m, Convert_Mem5_2, { MCK_callq, MCK__STAR_, MCK_Mem } },
- { X86::CMOVAE32rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovael, MCK_GR32, MCK_GR32 } },
- { X86::CMOVAE32rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovael, MCK_Mem, MCK_GR32 } },
- { X86::CMOVAE64rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovaeq, MCK_GR64, MCK_GR64 } },
- { X86::CMOVAE64rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovaeq, MCK_Mem, MCK_GR64 } },
- { X86::CMOVAE16rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovaew, MCK_GR16, MCK_GR16 } },
- { X86::CMOVAE16rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovaew, MCK_Mem, MCK_GR16 } },
- { X86::CMOVA32rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmoval, MCK_GR32, MCK_GR32 } },
- { X86::CMOVA32rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmoval, MCK_Mem, MCK_GR32 } },
- { X86::CMOVA64rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovaq, MCK_GR64, MCK_GR64 } },
- { X86::CMOVA64rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovaq, MCK_Mem, MCK_GR64 } },
- { X86::CMOVA16rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovaw, MCK_GR16, MCK_GR16 } },
- { X86::CMOVA16rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovaw, MCK_Mem, MCK_GR16 } },
- { X86::CMOVBE32rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovbel, MCK_GR32, MCK_GR32 } },
- { X86::CMOVBE32rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovbel, MCK_Mem, MCK_GR32 } },
- { X86::CMOVBE64rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovbeq, MCK_GR64, MCK_GR64 } },
- { X86::CMOVBE64rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovbeq, MCK_Mem, MCK_GR64 } },
- { X86::CMOVBE16rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovbew, MCK_GR16, MCK_GR16 } },
- { X86::CMOVBE16rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovbew, MCK_Mem, MCK_GR16 } },
- { X86::CMOVB32rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovbl, MCK_GR32, MCK_GR32 } },
- { X86::CMOVB32rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovbl, MCK_Mem, MCK_GR32 } },
- { X86::CMOVB64rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovbq, MCK_GR64, MCK_GR64 } },
- { X86::CMOVB64rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovbq, MCK_Mem, MCK_GR64 } },
- { X86::CMOVB16rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovbw, MCK_GR16, MCK_GR16 } },
- { X86::CMOVB16rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovbw, MCK_Mem, MCK_GR16 } },
- { X86::CMOVE32rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovel, MCK_GR32, MCK_GR32 } },
- { X86::CMOVE32rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovel, MCK_Mem, MCK_GR32 } },
- { X86::CMOVE64rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmoveq, MCK_GR64, MCK_GR64 } },
- { X86::CMOVE64rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmoveq, MCK_Mem, MCK_GR64 } },
- { X86::CMOVE16rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovew, MCK_GR16, MCK_GR16 } },
- { X86::CMOVE16rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovew, MCK_Mem, MCK_GR16 } },
- { X86::CMOVGE32rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovgel, MCK_GR32, MCK_GR32 } },
- { X86::CMOVGE32rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovgel, MCK_Mem, MCK_GR32 } },
- { X86::CMOVGE64rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovgeq, MCK_GR64, MCK_GR64 } },
- { X86::CMOVGE64rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovgeq, MCK_Mem, MCK_GR64 } },
- { X86::CMOVGE16rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovgew, MCK_GR16, MCK_GR16 } },
- { X86::CMOVGE16rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovgew, MCK_Mem, MCK_GR16 } },
- { X86::CMOVG32rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovgl, MCK_GR32, MCK_GR32 } },
- { X86::CMOVG32rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovgl, MCK_Mem, MCK_GR32 } },
- { X86::CMOVG64rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovgq, MCK_GR64, MCK_GR64 } },
- { X86::CMOVG64rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovgq, MCK_Mem, MCK_GR64 } },
- { X86::CMOVG16rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovgw, MCK_GR16, MCK_GR16 } },
- { X86::CMOVG16rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovgw, MCK_Mem, MCK_GR16 } },
- { X86::CMOVLE32rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovlel, MCK_GR32, MCK_GR32 } },
- { X86::CMOVLE32rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovlel, MCK_Mem, MCK_GR32 } },
- { X86::CMOVLE64rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovleq, MCK_GR64, MCK_GR64 } },
- { X86::CMOVLE64rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovleq, MCK_Mem, MCK_GR64 } },
- { X86::CMOVLE16rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovlew, MCK_GR16, MCK_GR16 } },
- { X86::CMOVLE16rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovlew, MCK_Mem, MCK_GR16 } },
- { X86::CMOVL32rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovll, MCK_GR32, MCK_GR32 } },
- { X86::CMOVL32rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovll, MCK_Mem, MCK_GR32 } },
- { X86::CMOVL64rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovlq, MCK_GR64, MCK_GR64 } },
- { X86::CMOVL64rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovlq, MCK_Mem, MCK_GR64 } },
- { X86::CMOVL16rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovlw, MCK_GR16, MCK_GR16 } },
- { X86::CMOVL16rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovlw, MCK_Mem, MCK_GR16 } },
- { X86::CMOVNE32rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovnel, MCK_GR32, MCK_GR32 } },
- { X86::CMOVNE32rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovnel, MCK_Mem, MCK_GR32 } },
- { X86::CMOVNE64rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovneq, MCK_GR64, MCK_GR64 } },
- { X86::CMOVNE64rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovneq, MCK_Mem, MCK_GR64 } },
- { X86::CMOVNE16rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovnew, MCK_GR16, MCK_GR16 } },
- { X86::CMOVNE16rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovnew, MCK_Mem, MCK_GR16 } },
- { X86::CMOVNO32rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovnol, MCK_GR32, MCK_GR32 } },
- { X86::CMOVNO32rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovnol, MCK_Mem, MCK_GR32 } },
- { X86::CMOVNO64rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovnoq, MCK_GR64, MCK_GR64 } },
- { X86::CMOVNO64rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovnoq, MCK_Mem, MCK_GR64 } },
- { X86::CMOVNO16rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovnow, MCK_GR16, MCK_GR16 } },
- { X86::CMOVNO16rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovnow, MCK_Mem, MCK_GR16 } },
- { X86::CMOVNP32rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovnpl, MCK_GR32, MCK_GR32 } },
- { X86::CMOVNP32rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovnpl, MCK_Mem, MCK_GR32 } },
- { X86::CMOVNP64rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovnpq, MCK_GR64, MCK_GR64 } },
- { X86::CMOVNP64rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovnpq, MCK_Mem, MCK_GR64 } },
- { X86::CMOVNP16rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovnpw, MCK_GR16, MCK_GR16 } },
- { X86::CMOVNP16rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovnpw, MCK_Mem, MCK_GR16 } },
- { X86::CMOVNS32rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovnsl, MCK_GR32, MCK_GR32 } },
- { X86::CMOVNS32rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovnsl, MCK_Mem, MCK_GR32 } },
- { X86::CMOVNS64rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovnsq, MCK_GR64, MCK_GR64 } },
- { X86::CMOVNS64rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovnsq, MCK_Mem, MCK_GR64 } },
- { X86::CMOVNS16rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovnsw, MCK_GR16, MCK_GR16 } },
- { X86::CMOVNS16rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovnsw, MCK_Mem, MCK_GR16 } },
- { X86::CMOVO32rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovol, MCK_GR32, MCK_GR32 } },
- { X86::CMOVO32rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovol, MCK_Mem, MCK_GR32 } },
- { X86::CMOVO64rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovoq, MCK_GR64, MCK_GR64 } },
- { X86::CMOVO64rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovoq, MCK_Mem, MCK_GR64 } },
- { X86::CMOVO16rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovow, MCK_GR16, MCK_GR16 } },
- { X86::CMOVO16rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovow, MCK_Mem, MCK_GR16 } },
- { X86::CMOVP32rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovpl, MCK_GR32, MCK_GR32 } },
- { X86::CMOVP32rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovpl, MCK_Mem, MCK_GR32 } },
- { X86::CMOVP64rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovpq, MCK_GR64, MCK_GR64 } },
- { X86::CMOVP64rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovpq, MCK_Mem, MCK_GR64 } },
- { X86::CMOVP16rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovpw, MCK_GR16, MCK_GR16 } },
- { X86::CMOVP16rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovpw, MCK_Mem, MCK_GR16 } },
- { X86::CMOVS32rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovsl, MCK_GR32, MCK_GR32 } },
- { X86::CMOVS32rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovsl, MCK_Mem, MCK_GR32 } },
- { X86::CMOVS64rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovsq, MCK_GR64, MCK_GR64 } },
- { X86::CMOVS64rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovsq, MCK_Mem, MCK_GR64 } },
- { X86::CMOVS16rr, Convert_Reg1_2_ImpReg1_1, { MCK_cmovsw, MCK_GR16, MCK_GR16 } },
- { X86::CMOVS16rm, Convert_Reg1_2_ImpMem5_1, { MCK_cmovsw, MCK_Mem, MCK_GR16 } },
- { X86::CMP8rr, Convert_Reg1_2_Reg1_1, { MCK_cmpb, MCK_GR8, MCK_GR8 } },
- { X86::CMP8mrmrr, Convert_Reg1_2_Reg1_1, { MCK_cmpb, MCK_GR8, MCK_GR8 } },
- { X86::CMP8mr, Convert_Mem5_2_Reg1_1, { MCK_cmpb, MCK_GR8, MCK_Mem } },
- { X86::CMP8i8, Convert_Imm1_1, { MCK_cmpb, MCK_Imm, MCK_AL } },
- { X86::CMP8ri, Convert_Reg1_2_Imm1_1, { MCK_cmpb, MCK_Imm, MCK_GR8 } },
- { X86::CMP8mi, Convert_Mem5_2_Imm1_1, { MCK_cmpb, MCK_Imm, MCK_Mem } },
- { X86::CMP8rm, Convert_Reg1_2_Mem5_1, { MCK_cmpb, MCK_Mem, MCK_GR8 } },
- { X86::CMP32mrmrr, Convert_Reg1_2_Reg1_1, { MCK_cmpl, MCK_GR32, MCK_GR32 } },
- { X86::CMP32rr, Convert_Reg1_2_Reg1_1, { MCK_cmpl, MCK_GR32, MCK_GR32 } },
- { X86::CMP32mr, Convert_Mem5_2_Reg1_1, { MCK_cmpl, MCK_GR32, MCK_Mem } },
- { X86::CMP32ri8, Convert_Reg1_2_ImmSExt81_1, { MCK_cmpl, MCK_ImmSExt8, MCK_GR32 } },
- { X86::CMP32mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_cmpl, MCK_ImmSExt8, MCK_Mem } },
- { X86::CMP32i32, Convert_Imm1_1, { MCK_cmpl, MCK_Imm, MCK_EAX } },
- { X86::CMP32ri, Convert_Reg1_2_Imm1_1, { MCK_cmpl, MCK_Imm, MCK_GR32 } },
- { X86::CMP32mi, Convert_Mem5_2_Imm1_1, { MCK_cmpl, MCK_Imm, MCK_Mem } },
- { X86::CMP32rm, Convert_Reg1_2_Mem5_1, { MCK_cmpl, MCK_Mem, MCK_GR32 } },
- { X86::CMP64rr, Convert_Reg1_2_Reg1_1, { MCK_cmpq, MCK_GR64, MCK_GR64 } },
- { X86::CMP64mrmrr, Convert_Reg1_2_Reg1_1, { MCK_cmpq, MCK_GR64, MCK_GR64 } },
- { X86::CMP64mr, Convert_Mem5_2_Reg1_1, { MCK_cmpq, MCK_GR64, MCK_Mem } },
- { X86::CMP64ri8, Convert_Reg1_2_ImmSExt81_1, { MCK_cmpq, MCK_ImmSExt8, MCK_GR64 } },
- { X86::CMP64mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_cmpq, MCK_ImmSExt8, MCK_Mem } },
- { X86::CMP64i32, Convert_Imm1_1, { MCK_cmpq, MCK_Imm, MCK_RAX } },
- { X86::CMP64ri32, Convert_Reg1_2_Imm1_1, { MCK_cmpq, MCK_Imm, MCK_GR64 } },
- { X86::CMP64mi32, Convert_Mem5_2_Imm1_1, { MCK_cmpq, MCK_Imm, MCK_Mem } },
- { X86::CMP64rm, Convert_Reg1_2_Mem5_1, { MCK_cmpq, MCK_Mem, MCK_GR64 } },
- { X86::CMP16mrmrr, Convert_Reg1_2_Reg1_1, { MCK_cmpw, MCK_GR16, MCK_GR16 } },
- { X86::CMP16rr, Convert_Reg1_2_Reg1_1, { MCK_cmpw, MCK_GR16, MCK_GR16 } },
- { X86::CMP16mr, Convert_Mem5_2_Reg1_1, { MCK_cmpw, MCK_GR16, MCK_Mem } },
- { X86::CMP16ri8, Convert_Reg1_2_ImmSExt81_1, { MCK_cmpw, MCK_ImmSExt8, MCK_GR16 } },
- { X86::CMP16mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_cmpw, MCK_ImmSExt8, MCK_Mem } },
- { X86::CMP16i16, Convert_Imm1_1, { MCK_cmpw, MCK_Imm, MCK_AX } },
- { X86::CMP16ri, Convert_Reg1_2_Imm1_1, { MCK_cmpw, MCK_Imm, MCK_GR16 } },
- { X86::CMP16mi, Convert_Mem5_2_Imm1_1, { MCK_cmpw, MCK_Imm, MCK_Mem } },
- { X86::CMP16rm, Convert_Reg1_2_Mem5_1, { MCK_cmpw, MCK_Mem, MCK_GR16 } },
- { X86::CMPXCHG8rr, Convert_Reg1_2_Reg1_1, { MCK_cmpxchgb, MCK_GR8, MCK_GR8 } },
- { X86::CMPXCHG8rm, Convert_Mem5_2_Reg1_1, { MCK_cmpxchgb, MCK_GR8, MCK_Mem } },
- { X86::CMPXCHG32rr, Convert_Reg1_2_Reg1_1, { MCK_cmpxchgl, MCK_GR32, MCK_GR32 } },
- { X86::CMPXCHG32rm, Convert_Mem5_2_Reg1_1, { MCK_cmpxchgl, MCK_GR32, MCK_Mem } },
- { X86::CMPXCHG64rr, Convert_Reg1_2_Reg1_1, { MCK_cmpxchgq, MCK_GR64, MCK_GR64 } },
- { X86::CMPXCHG64rm, Convert_Mem5_2_Reg1_1, { MCK_cmpxchgq, MCK_GR64, MCK_Mem } },
- { X86::CMPXCHG16rr, Convert_Reg1_2_Reg1_1, { MCK_cmpxchgw, MCK_GR16, MCK_GR16 } },
- { X86::CMPXCHG16rm, Convert_Mem5_2_Reg1_1, { MCK_cmpxchgw, MCK_GR16, MCK_Mem } },
- { X86::COMISDrr, Convert_Reg1_2_Reg1_1, { MCK_comisd, MCK_FR32, MCK_FR32 } },
- { X86::COMISDrm, Convert_Reg1_2_Mem5_1, { MCK_comisd, MCK_Mem, MCK_FR32 } },
- { X86::COMISSrr, Convert_Reg1_2_Reg1_1, { MCK_comiss, MCK_FR32, MCK_FR32 } },
- { X86::COMISSrm, Convert_Reg1_2_Mem5_1, { MCK_comiss, MCK_Mem, MCK_FR32 } },
- { X86::CRC32r8, Convert_ImpReg1_2_Reg1_1, { MCK_crc32, MCK_GR8, MCK_GR32 } },
- { X86::CRC32r16, Convert_ImpReg1_2_Reg1_1, { MCK_crc32, MCK_GR16, MCK_GR32 } },
- { X86::CRC32r32, Convert_ImpReg1_2_Reg1_1, { MCK_crc32, MCK_GR32, MCK_GR32 } },
- { X86::CRC64r64, Convert_ImpReg1_2_Reg1_1, { MCK_crc32, MCK_GR64, MCK_GR64 } },
- { X86::CRC32m8, Convert_ImpReg1_2_Mem5_1, { MCK_crc32, MCK_Mem, MCK_GR32 } },
- { X86::CRC32m32, Convert_ImpReg1_2_Mem5_1, { MCK_crc32, MCK_Mem, MCK_GR32 } },
- { X86::CRC32m16, Convert_ImpReg1_2_Mem5_1, { MCK_crc32, MCK_Mem, MCK_GR32 } },
- { X86::CRC64m64, Convert_ImpReg1_2_Mem5_1, { MCK_crc32, MCK_Mem, MCK_GR64 } },
- { X86::CVTDQ2PDrr, Convert_Reg1_2_Reg1_1, { MCK_cvtdq2pd, MCK_FR32, MCK_FR32 } },
- { X86::CVTDQ2PDrm, Convert_Reg1_2_Mem5_1, { MCK_cvtdq2pd, MCK_Mem, MCK_FR32 } },
- { X86::CVTDQ2PSrr, Convert_Reg1_2_Reg1_1, { MCK_cvtdq2ps, MCK_FR32, MCK_FR32 } },
- { X86::CVTDQ2PSrm, Convert_Reg1_2_Mem5_1, { MCK_cvtdq2ps, MCK_Mem, MCK_FR32 } },
- { X86::CVTPD2DQrr, Convert_Reg1_2_Reg1_1, { MCK_cvtpd2dq, MCK_FR32, MCK_FR32 } },
- { X86::CVTPD2DQrm, Convert_Reg1_2_Mem5_1, { MCK_cvtpd2dq, MCK_Mem, MCK_FR32 } },
- { X86::MMX_CVTPD2PIrr, Convert_Reg1_2_Reg1_1, { MCK_cvtpd2pi, MCK_FR32, MCK_VR64 } },
- { X86::MMX_CVTPD2PIrm, Convert_Reg1_2_Mem5_1, { MCK_cvtpd2pi, MCK_Mem, MCK_VR64 } },
- { X86::CVTPD2PSrr, Convert_Reg1_2_Reg1_1, { MCK_cvtpd2ps, MCK_FR32, MCK_FR32 } },
- { X86::CVTPD2PSrm, Convert_Reg1_2_Mem5_1, { MCK_cvtpd2ps, MCK_Mem, MCK_FR32 } },
- { X86::MMX_CVTPI2PDrr, Convert_Reg1_2_Reg1_1, { MCK_cvtpi2pd, MCK_VR64, MCK_FR32 } },
- { X86::MMX_CVTPI2PDrm, Convert_Reg1_2_Mem5_1, { MCK_cvtpi2pd, MCK_Mem, MCK_FR32 } },
- { X86::MMX_CVTPI2PSrr, Convert_Reg1_2_Reg1_1, { MCK_cvtpi2ps, MCK_VR64, MCK_FR32 } },
- { X86::MMX_CVTPI2PSrm, Convert_Reg1_2_Mem5_1, { MCK_cvtpi2ps, MCK_Mem, MCK_FR32 } },
- { X86::CVTPS2DQrr, Convert_Reg1_2_Reg1_1, { MCK_cvtps2dq, MCK_FR32, MCK_FR32 } },
- { X86::CVTPS2DQrm, Convert_Reg1_2_Mem5_1, { MCK_cvtps2dq, MCK_Mem, MCK_FR32 } },
- { X86::CVTPS2PDrr, Convert_Reg1_2_Reg1_1, { MCK_cvtps2pd, MCK_FR32, MCK_FR32 } },
- { X86::CVTPS2PDrm, Convert_Reg1_2_Mem5_1, { MCK_cvtps2pd, MCK_Mem, MCK_FR32 } },
- { X86::MMX_CVTPS2PIrr, Convert_Reg1_2_Reg1_1, { MCK_cvtps2pi, MCK_FR32, MCK_VR64 } },
- { X86::MMX_CVTPS2PIrm, Convert_Reg1_2_Mem5_1, { MCK_cvtps2pi, MCK_Mem, MCK_VR64 } },
- { X86::CVTSD2SI64rr, Convert_Reg1_2_Reg1_1, { MCK_cvtsd2siq, MCK_FR32, MCK_GR64 } },
- { X86::CVTSD2SI64rm, Convert_Reg1_2_Mem5_1, { MCK_cvtsd2siq, MCK_Mem, MCK_GR64 } },
- { X86::CVTSD2SSrr, Convert_Reg1_2_Reg1_1, { MCK_cvtsd2ss, MCK_FR32, MCK_FR32 } },
- { X86::CVTSD2SSrm, Convert_Reg1_2_Mem5_1, { MCK_cvtsd2ss, MCK_Mem, MCK_FR32 } },
- { X86::CVTSI2SDrr, Convert_Reg1_2_Reg1_1, { MCK_cvtsi2sd, MCK_GR32, MCK_FR32 } },
- { X86::CVTSI2SDrm, Convert_Reg1_2_Mem5_1, { MCK_cvtsi2sd, MCK_Mem, MCK_FR32 } },
- { X86::CVTSI2SD64rr, Convert_Reg1_2_Reg1_1, { MCK_cvtsi2sdq, MCK_GR64, MCK_FR32 } },
- { X86::CVTSI2SD64rm, Convert_Reg1_2_Mem5_1, { MCK_cvtsi2sdq, MCK_Mem, MCK_FR32 } },
- { X86::CVTSI2SSrr, Convert_Reg1_2_Reg1_1, { MCK_cvtsi2ss, MCK_GR32, MCK_FR32 } },
- { X86::CVTSI2SSrm, Convert_Reg1_2_Mem5_1, { MCK_cvtsi2ss, MCK_Mem, MCK_FR32 } },
- { X86::CVTSI2SS64rr, Convert_Reg1_2_Reg1_1, { MCK_cvtsi2ssq, MCK_GR64, MCK_FR32 } },
- { X86::CVTSI2SS64rm, Convert_Reg1_2_Mem5_1, { MCK_cvtsi2ssq, MCK_Mem, MCK_FR32 } },
- { X86::CVTSS2SDrr, Convert_Reg1_2_Reg1_1, { MCK_cvtss2sd, MCK_FR32, MCK_FR32 } },
- { X86::CVTSS2SDrm, Convert_Reg1_2_Mem5_1, { MCK_cvtss2sd, MCK_Mem, MCK_FR32 } },
- { X86::CVTSS2SIrr, Convert_Reg1_2_Reg1_1, { MCK_cvtss2sil, MCK_FR32, MCK_GR32 } },
- { X86::CVTSS2SIrm, Convert_Reg1_2_Mem5_1, { MCK_cvtss2sil, MCK_Mem, MCK_GR32 } },
- { X86::CVTSS2SI64rr, Convert_Reg1_2_Reg1_1, { MCK_cvtss2siq, MCK_FR32, MCK_GR64 } },
- { X86::CVTSS2SI64rm, Convert_Reg1_2_Mem5_1, { MCK_cvtss2siq, MCK_Mem, MCK_GR64 } },
- { X86::MMX_CVTTPD2PIrr, Convert_Reg1_2_Reg1_1, { MCK_cvttpd2pi, MCK_FR32, MCK_VR64 } },
- { X86::MMX_CVTTPD2PIrm, Convert_Reg1_2_Mem5_1, { MCK_cvttpd2pi, MCK_Mem, MCK_VR64 } },
- { X86::CVTTPS2DQrr, Convert_Reg1_2_Reg1_1, { MCK_cvttps2dq, MCK_FR32, MCK_FR32 } },
- { X86::CVTTPS2DQrm, Convert_Reg1_2_Mem5_1, { MCK_cvttps2dq, MCK_Mem, MCK_FR32 } },
- { X86::MMX_CVTTPS2PIrr, Convert_Reg1_2_Reg1_1, { MCK_cvttps2pi, MCK_FR32, MCK_VR64 } },
- { X86::MMX_CVTTPS2PIrm, Convert_Reg1_2_Mem5_1, { MCK_cvttps2pi, MCK_Mem, MCK_VR64 } },
- { X86::CVTTSD2SIrr, Convert_Reg1_2_Reg1_1, { MCK_cvttsd2si, MCK_FR32, MCK_GR32 } },
- { X86::CVTTSD2SIrm, Convert_Reg1_2_Mem5_1, { MCK_cvttsd2si, MCK_Mem, MCK_GR32 } },
- { X86::CVTTSD2SI64rr, Convert_Reg1_2_Reg1_1, { MCK_cvttsd2siq, MCK_FR32, MCK_GR64 } },
- { X86::CVTTSD2SI64rm, Convert_Reg1_2_Mem5_1, { MCK_cvttsd2siq, MCK_Mem, MCK_GR64 } },
- { X86::CVTTSS2SIrr, Convert_Reg1_2_Reg1_1, { MCK_cvttss2si, MCK_FR32, MCK_GR32 } },
- { X86::CVTTSS2SIrm, Convert_Reg1_2_Mem5_1, { MCK_cvttss2si, MCK_Mem, MCK_GR32 } },
- { X86::CVTTSS2SI64rr, Convert_Reg1_2_Reg1_1, { MCK_cvttss2siq, MCK_FR32, MCK_GR64 } },
- { X86::CVTTSS2SI64rm, Convert_Reg1_2_Mem5_1, { MCK_cvttss2siq, MCK_Mem, MCK_GR64 } },
- { X86::DIVPDrr, Convert_Reg1_2_ImpReg1_1, { MCK_divpd, MCK_FR32, MCK_FR32 } },
- { X86::DIVPDrm, Convert_Reg1_2_ImpMem5_1, { MCK_divpd, MCK_Mem, MCK_FR32 } },
- { X86::DIVPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_divps, MCK_FR32, MCK_FR32 } },
- { X86::DIVPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_divps, MCK_Mem, MCK_FR32 } },
- { X86::DIVSDrr, Convert_Reg1_2_ImpReg1_1, { MCK_divsd, MCK_FR32, MCK_FR32 } },
- { X86::DIVSDrm, Convert_Reg1_2_ImpMem5_1, { MCK_divsd, MCK_Mem, MCK_FR32 } },
- { X86::DIVSSrr, Convert_Reg1_2_ImpReg1_1, { MCK_divss, MCK_FR32, MCK_FR32 } },
- { X86::DIVSSrm, Convert_Reg1_2_ImpMem5_1, { MCK_divss, MCK_Mem, MCK_FR32 } },
- { X86::ENTER, Convert_Imm1_1_Imm1_2, { MCK_enter, MCK_Imm, MCK_Imm } },
- { X86::ADD_FrST0, Convert_Reg1_2, { MCK_fadd, MCK_ST0, MCK_RST } },
- { X86::CMOVB_F, Convert_Reg1_1, { MCK_fcmovb, MCK_RST, MCK_ST0 } },
- { X86::CMOVBE_F, Convert_Reg1_1, { MCK_fcmovbe, MCK_RST, MCK_ST0 } },
- { X86::CMOVE_F, Convert_Reg1_1, { MCK_fcmove, MCK_RST, MCK_ST0 } },
- { X86::CMOVNB_F, Convert_Reg1_1, { MCK_fcmovnb, MCK_RST, MCK_ST0 } },
- { X86::CMOVNBE_F, Convert_Reg1_1, { MCK_fcmovnbe, MCK_RST, MCK_ST0 } },
- { X86::CMOVNE_F, Convert_Reg1_1, { MCK_fcmovne, MCK_RST, MCK_ST0 } },
- { X86::CMOVNP_F, Convert_Reg1_1, { MCK_fcmovnu, MCK_RST, MCK_ST0 } },
- { X86::CMOVP_F, Convert_Reg1_1, { MCK_fcmovu, MCK_RST, MCK_ST0 } },
- { X86::COM_FIr, Convert_Reg1_1, { MCK_fcomi, MCK_RST, MCK_ST0 } },
- { X86::COM_FIPr, Convert_Reg1_1, { MCK_fcomip, MCK_RST, MCK_ST0 } },
- { X86::DIVR_FrST0, Convert_Reg1_2, { MCK_fdiv, MCK_ST0, MCK_RST } },
- { X86::DIV_FrST0, Convert_Reg1_2, { MCK_fdivr, MCK_ST0, MCK_RST } },
- { X86::MUL_FrST0, Convert_Reg1_2, { MCK_fmul, MCK_ST0, MCK_RST } },
- { X86::SUBR_FrST0, Convert_Reg1_2, { MCK_fsub, MCK_ST0, MCK_RST } },
- { X86::SUB_FrST0, Convert_Reg1_2, { MCK_fsubr, MCK_ST0, MCK_RST } },
- { X86::UCOM_FIr, Convert_Reg1_1, { MCK_fucomi, MCK_RST, MCK_ST0 } },
- { X86::UCOM_FIPr, Convert_Reg1_1, { MCK_fucomip, MCK_RST, MCK_ST0 } },
- { X86::HADDPDrr, Convert_Reg1_2_ImpReg1_1, { MCK_haddpd, MCK_FR32, MCK_FR32 } },
- { X86::HADDPDrm, Convert_Reg1_2_ImpMem5_1, { MCK_haddpd, MCK_Mem, MCK_FR32 } },
- { X86::HADDPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_haddps, MCK_FR32, MCK_FR32 } },
- { X86::HADDPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_haddps, MCK_Mem, MCK_FR32 } },
- { X86::HSUBPDrr, Convert_Reg1_2_ImpReg1_1, { MCK_hsubpd, MCK_FR32, MCK_FR32 } },
- { X86::HSUBPDrm, Convert_Reg1_2_ImpMem5_1, { MCK_hsubpd, MCK_Mem, MCK_FR32 } },
- { X86::HSUBPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_hsubps, MCK_FR32, MCK_FR32 } },
- { X86::HSUBPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_hsubps, MCK_Mem, MCK_FR32 } },
- { X86::IMUL32rr, Convert_Reg1_2_ImpReg1_1, { MCK_imull, MCK_GR32, MCK_GR32 } },
- { X86::IMUL32rm, Convert_Reg1_2_ImpMem5_1, { MCK_imull, MCK_Mem, MCK_GR32 } },
- { X86::IMUL64rr, Convert_Reg1_2_ImpReg1_1, { MCK_imulq, MCK_GR64, MCK_GR64 } },
- { X86::IMUL64rm, Convert_Reg1_2_ImpMem5_1, { MCK_imulq, MCK_Mem, MCK_GR64 } },
- { X86::IMUL16rr, Convert_Reg1_2_ImpReg1_1, { MCK_imulw, MCK_GR16, MCK_GR16 } },
- { X86::IMUL16rm, Convert_Reg1_2_ImpMem5_1, { MCK_imulw, MCK_Mem, MCK_GR16 } },
+ { X86::PUSH16rmm, Convert__Mem5_1, { MCK_pushw, MCK_Mem } },
+ { X86::RETI, Convert__Imm1_1, { MCK_ret, MCK_Imm } },
+ { X86::ROL8r1, Convert__Reg1_1__Tie0, { MCK_rolb, MCK_GR8 } },
+ { X86::ROL8m1, Convert__Mem5_1, { MCK_rolb, MCK_Mem } },
+ { X86::ROL32r1, Convert__Reg1_1__Tie0, { MCK_roll, MCK_GR32 } },
+ { X86::ROL32m1, Convert__Mem5_1, { MCK_roll, MCK_Mem } },
+ { X86::ROL64r1, Convert__Reg1_1__Tie0, { MCK_rolq, MCK_GR64 } },
+ { X86::ROL64m1, Convert__Mem5_1, { MCK_rolq, MCK_Mem } },
+ { X86::ROL16r1, Convert__Reg1_1__Tie0, { MCK_rolw, MCK_GR16 } },
+ { X86::ROL16m1, Convert__Mem5_1, { MCK_rolw, MCK_Mem } },
+ { X86::ROR8r1, Convert__Reg1_1__Tie0, { MCK_rorb, MCK_GR8 } },
+ { X86::ROR8m1, Convert__Mem5_1, { MCK_rorb, MCK_Mem } },
+ { X86::ROR32r1, Convert__Reg1_1__Tie0, { MCK_rorl, MCK_GR32 } },
+ { X86::ROR32m1, Convert__Mem5_1, { MCK_rorl, MCK_Mem } },
+ { X86::ROR64r1, Convert__Reg1_1__Tie0, { MCK_rorq, MCK_GR64 } },
+ { X86::ROR64m1, Convert__Mem5_1, { MCK_rorq, MCK_Mem } },
+ { X86::ROR16r1, Convert__Reg1_1__Tie0, { MCK_rorw, MCK_GR16 } },
+ { X86::ROR16m1, Convert__Mem5_1, { MCK_rorw, MCK_Mem } },
+ { X86::SAR8r1, Convert__Reg1_1__Tie0, { MCK_sarb, MCK_GR8 } },
+ { X86::SAR8m1, Convert__Mem5_1, { MCK_sarb, MCK_Mem } },
+ { X86::SAR32r1, Convert__Reg1_1__Tie0, { MCK_sarl, MCK_GR32 } },
+ { X86::SAR32m1, Convert__Mem5_1, { MCK_sarl, MCK_Mem } },
+ { X86::SAR64r1, Convert__Reg1_1__Tie0, { MCK_sarq, MCK_GR64 } },
+ { X86::SAR64m1, Convert__Mem5_1, { MCK_sarq, MCK_Mem } },
+ { X86::SAR16r1, Convert__Reg1_1__Tie0, { MCK_sarw, MCK_GR16 } },
+ { X86::SAR16m1, Convert__Mem5_1, { MCK_sarw, MCK_Mem } },
+ { X86::SETAr, Convert__Reg1_1, { MCK_seta, MCK_GR8 } },
+ { X86::SETAm, Convert__Mem5_1, { MCK_seta, MCK_Mem } },
+ { X86::SETAEr, Convert__Reg1_1, { MCK_setae, MCK_GR8 } },
+ { X86::SETAEm, Convert__Mem5_1, { MCK_setae, MCK_Mem } },
+ { X86::SETBr, Convert__Reg1_1, { MCK_setb, MCK_GR8 } },
+ { X86::SETBm, Convert__Mem5_1, { MCK_setb, MCK_Mem } },
+ { X86::SETBEr, Convert__Reg1_1, { MCK_setbe, MCK_GR8 } },
+ { X86::SETBEm, Convert__Mem5_1, { MCK_setbe, MCK_Mem } },
+ { X86::SETEr, Convert__Reg1_1, { MCK_sete, MCK_GR8 } },
+ { X86::SETEm, Convert__Mem5_1, { MCK_sete, MCK_Mem } },
+ { X86::SETGr, Convert__Reg1_1, { MCK_setg, MCK_GR8 } },
+ { X86::SETGm, Convert__Mem5_1, { MCK_setg, MCK_Mem } },
+ { X86::SETGEr, Convert__Reg1_1, { MCK_setge, MCK_GR8 } },
+ { X86::SETGEm, Convert__Mem5_1, { MCK_setge, MCK_Mem } },
+ { X86::SETLr, Convert__Reg1_1, { MCK_setl, MCK_GR8 } },
+ { X86::SETLm, Convert__Mem5_1, { MCK_setl, MCK_Mem } },
+ { X86::SETLEr, Convert__Reg1_1, { MCK_setle, MCK_GR8 } },
+ { X86::SETLEm, Convert__Mem5_1, { MCK_setle, MCK_Mem } },
+ { X86::SETNEr, Convert__Reg1_1, { MCK_setne, MCK_GR8 } },
+ { X86::SETNEm, Convert__Mem5_1, { MCK_setne, MCK_Mem } },
+ { X86::SETNOr, Convert__Reg1_1, { MCK_setno, MCK_GR8 } },
+ { X86::SETNOm, Convert__Mem5_1, { MCK_setno, MCK_Mem } },
+ { X86::SETNPr, Convert__Reg1_1, { MCK_setnp, MCK_GR8 } },
+ { X86::SETNPm, Convert__Mem5_1, { MCK_setnp, MCK_Mem } },
+ { X86::SETNSr, Convert__Reg1_1, { MCK_setns, MCK_GR8 } },
+ { X86::SETNSm, Convert__Mem5_1, { MCK_setns, MCK_Mem } },
+ { X86::SETOr, Convert__Reg1_1, { MCK_seto, MCK_GR8 } },
+ { X86::SETOm, Convert__Mem5_1, { MCK_seto, MCK_Mem } },
+ { X86::SETPr, Convert__Reg1_1, { MCK_setp, MCK_GR8 } },
+ { X86::SETPm, Convert__Mem5_1, { MCK_setp, MCK_Mem } },
+ { X86::SETSr, Convert__Reg1_1, { MCK_sets, MCK_GR8 } },
+ { X86::SETSm, Convert__Mem5_1, { MCK_sets, MCK_Mem } },
+ { X86::SGDTm, Convert__Mem5_1, { MCK_sgdt, MCK_Mem } },
+ { X86::SHL8r1, Convert__Reg1_1__Tie0, { MCK_shlb, MCK_GR8 } },
+ { X86::SHL8m1, Convert__Mem5_1, { MCK_shlb, MCK_Mem } },
+ { X86::SHL32r1, Convert__Reg1_1__Tie0, { MCK_shll, MCK_GR32 } },
+ { X86::SHL32m1, Convert__Mem5_1, { MCK_shll, MCK_Mem } },
+ { X86::SHL64r1, Convert__Reg1_1__Tie0, { MCK_shlq, MCK_GR64 } },
+ { X86::SHL64m1, Convert__Mem5_1, { MCK_shlq, MCK_Mem } },
+ { X86::SHL16r1, Convert__Reg1_1__Tie0, { MCK_shlw, MCK_GR16 } },
+ { X86::SHL16m1, Convert__Mem5_1, { MCK_shlw, MCK_Mem } },
+ { X86::SHR8r1, Convert__Reg1_1__Tie0, { MCK_shrb, MCK_GR8 } },
+ { X86::SHR8m1, Convert__Mem5_1, { MCK_shrb, MCK_Mem } },
+ { X86::SHR32r1, Convert__Reg1_1__Tie0, { MCK_shrl, MCK_GR32 } },
+ { X86::SHR32m1, Convert__Mem5_1, { MCK_shrl, MCK_Mem } },
+ { X86::SHR64r1, Convert__Reg1_1__Tie0, { MCK_shrq, MCK_GR64 } },
+ { X86::SHR64m1, Convert__Mem5_1, { MCK_shrq, MCK_Mem } },
+ { X86::SHR16r1, Convert__Reg1_1__Tie0, { MCK_shrw, MCK_GR16 } },
+ { X86::SHR16m1, Convert__Mem5_1, { MCK_shrw, MCK_Mem } },
+ { X86::SIDTm, Convert__Mem5_1, { MCK_sidt, MCK_Mem } },
+ { X86::SLDT64r, Convert__Reg1_1, { MCK_sldtq, MCK_GR64 } },
+ { X86::SLDT64m, Convert__Mem5_1, { MCK_sldtq, MCK_Mem } },
+ { X86::SLDT16r, Convert__Reg1_1, { MCK_sldtw, MCK_GR16 } },
+ { X86::SLDT16m, Convert__Mem5_1, { MCK_sldtw, MCK_Mem } },
+ { X86::SMSW32r, Convert__Reg1_1, { MCK_smswl, MCK_GR32 } },
+ { X86::SMSW64r, Convert__Reg1_1, { MCK_smswq, MCK_GR64 } },
+ { X86::SMSW16r, Convert__Reg1_1, { MCK_smsww, MCK_GR16 } },
+ { X86::SMSW16m, Convert__Mem5_1, { MCK_smsww, MCK_Mem } },
+ { X86::STMXCSR, Convert__Mem5_1, { MCK_stmxcsr, MCK_Mem } },
+ { X86::STRr, Convert__Reg1_1, { MCK_strw, MCK_GR16 } },
+ { X86::STRm, Convert__Mem5_1, { MCK_strw, MCK_Mem } },
+ { X86::VERRr, Convert__Reg1_1, { MCK_verr, MCK_GR16 } },
+ { X86::VERRm, Convert__Mem5_1, { MCK_verr, MCK_Mem } },
+ { X86::VERWr, Convert__Reg1_1, { MCK_verw, MCK_GR16 } },
+ { X86::VERWm, Convert__Mem5_1, { MCK_verw, MCK_Mem } },
+ { X86::VMCLEARm, Convert__Mem5_1, { MCK_vmclear, MCK_Mem } },
+ { X86::VMPTRLDm, Convert__Mem5_1, { MCK_vmptrld, MCK_Mem } },
+ { X86::VMPTRSTm, Convert__Mem5_1, { MCK_vmptrst, MCK_Mem } },
+ { X86::VMXON, Convert__Mem5_1, { MCK_vmxon, MCK_Mem } },
+ { X86::ADC8rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_adcb, MCK_GR8, MCK_GR8 } },
+ { X86::ADC8rr_REV, Convert__Reg1_2__Tie0__Reg1_1, { MCK_adcb, MCK_GR8, MCK_GR8 } },
+ { X86::ADC8mr, Convert__Mem5_2__Reg1_1, { MCK_adcb, MCK_GR8, MCK_Mem } },
+ { X86::ADC8i8, Convert__Imm1_1, { MCK_adcb, MCK_Imm, MCK_AL } },
+ { X86::ADC8ri, Convert__Reg1_2__Tie0__Imm1_1, { MCK_adcb, MCK_Imm, MCK_GR8 } },
+ { X86::ADC8mi, Convert__Mem5_2__Imm1_1, { MCK_adcb, MCK_Imm, MCK_Mem } },
+ { X86::ADC8rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_adcb, MCK_Mem, MCK_GR8 } },
+ { X86::ADC32rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_adcl, MCK_GR32, MCK_GR32 } },
+ { X86::ADC32rr_REV, Convert__Reg1_2__Tie0__Reg1_1, { MCK_adcl, MCK_GR32, MCK_GR32 } },
+ { X86::ADC32mr, Convert__Mem5_2__Reg1_1, { MCK_adcl, MCK_GR32, MCK_Mem } },
+ { X86::ADC32ri8, Convert__Reg1_2__Tie0__ImmSExt81_1, { MCK_adcl, MCK_ImmSExt8, MCK_GR32 } },
+ { X86::ADC32mi8, Convert__Mem5_2__ImmSExt81_1, { MCK_adcl, MCK_ImmSExt8, MCK_Mem } },
+ { X86::ADC32i32, Convert__Imm1_1, { MCK_adcl, MCK_Imm, MCK_EAX } },
+ { X86::ADC32ri, Convert__Reg1_2__Tie0__Imm1_1, { MCK_adcl, MCK_Imm, MCK_GR32 } },
+ { X86::ADC32mi, Convert__Mem5_2__Imm1_1, { MCK_adcl, MCK_Imm, MCK_Mem } },
+ { X86::ADC32rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_adcl, MCK_Mem, MCK_GR32 } },
+ { X86::ADC64rr_REV, Convert__Reg1_2__Tie0__Reg1_1, { MCK_adcq, MCK_GR64, MCK_GR32 } },
+ { X86::ADC64rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_adcq, MCK_GR64, MCK_GR64 } },
+ { X86::ADC64mr, Convert__Mem5_2__Reg1_1, { MCK_adcq, MCK_GR64, MCK_Mem } },
+ { X86::ADC64ri8, Convert__Reg1_2__Tie0__ImmSExt81_1, { MCK_adcq, MCK_ImmSExt8, MCK_GR64 } },
+ { X86::ADC64mi8, Convert__Mem5_2__ImmSExt81_1, { MCK_adcq, MCK_ImmSExt8, MCK_Mem } },
+ { X86::ADC64i32, Convert__Imm1_1, { MCK_adcq, MCK_Imm, MCK_RAX } },
+ { X86::ADC64ri32, Convert__Reg1_2__Tie0__Imm1_1, { MCK_adcq, MCK_Imm, MCK_GR64 } },
+ { X86::ADC64mi32, Convert__Mem5_2__Imm1_1, { MCK_adcq, MCK_Imm, MCK_Mem } },
+ { X86::ADC64rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_adcq, MCK_Mem, MCK_GR64 } },
+ { X86::ADC16rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_adcw, MCK_GR16, MCK_GR16 } },
+ { X86::ADC16rr_REV, Convert__Reg1_2__Tie0__Reg1_1, { MCK_adcw, MCK_GR16, MCK_GR16 } },
+ { X86::ADC16mr, Convert__Mem5_2__Reg1_1, { MCK_adcw, MCK_GR16, MCK_Mem } },
+ { X86::ADC16ri8, Convert__Reg1_2__Tie0__ImmSExt81_1, { MCK_adcw, MCK_ImmSExt8, MCK_GR16 } },
+ { X86::ADC16mi8, Convert__Mem5_2__ImmSExt81_1, { MCK_adcw, MCK_ImmSExt8, MCK_Mem } },
+ { X86::ADC16i16, Convert__Imm1_1, { MCK_adcw, MCK_Imm, MCK_AX } },
+ { X86::ADC16ri, Convert__Reg1_2__Tie0__Imm1_1, { MCK_adcw, MCK_Imm, MCK_GR16 } },
+ { X86::ADC16mi, Convert__Mem5_2__Imm1_1, { MCK_adcw, MCK_Imm, MCK_Mem } },
+ { X86::ADC16rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_adcw, MCK_Mem, MCK_GR16 } },
+ { X86::ADD8mrmrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_addb, MCK_GR8, MCK_GR8 } },
+ { X86::ADD8rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_addb, MCK_GR8, MCK_GR8 } },
+ { X86::ADD8mr, Convert__Mem5_2__Reg1_1, { MCK_addb, MCK_GR8, MCK_Mem } },
+ { X86::ADD8i8, Convert__Imm1_1, { MCK_addb, MCK_Imm, MCK_AL } },
+ { X86::ADD8ri, Convert__Reg1_2__Tie0__Imm1_1, { MCK_addb, MCK_Imm, MCK_GR8 } },
+ { X86::ADD8mi, Convert__Mem5_2__Imm1_1, { MCK_addb, MCK_Imm, MCK_Mem } },
+ { X86::ADD8rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_addb, MCK_Mem, MCK_GR8 } },
+ { X86::ADD32mrmrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_addl, MCK_GR16, MCK_GR16 } },
+ { X86::ADD32rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_addl, MCK_GR32, MCK_GR32 } },
+ { X86::ADD32mr, Convert__Mem5_2__Reg1_1, { MCK_addl, MCK_GR32, MCK_Mem } },
+ { X86::ADD64mrmrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_addl, MCK_GR64, MCK_GR64 } },
+ { X86::ADD32ri8, Convert__Reg1_2__Tie0__ImmSExt81_1, { MCK_addl, MCK_ImmSExt8, MCK_GR32 } },
+ { X86::ADD32mi8, Convert__Mem5_2__ImmSExt81_1, { MCK_addl, MCK_ImmSExt8, MCK_Mem } },
+ { X86::ADD32i32, Convert__Imm1_1, { MCK_addl, MCK_Imm, MCK_EAX } },
+ { X86::ADD32ri, Convert__Reg1_2__Tie0__Imm1_1, { MCK_addl, MCK_Imm, MCK_GR32 } },
+ { X86::ADD32mi, Convert__Mem5_2__Imm1_1, { MCK_addl, MCK_Imm, MCK_Mem } },
+ { X86::ADD32rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_addl, MCK_Mem, MCK_GR32 } },
+ { X86::ADDPDrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_addpd, MCK_FR32, MCK_FR32 } },
+ { X86::ADDPDrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_addpd, MCK_Mem, MCK_FR32 } },
+ { X86::ADDPSrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_addps, MCK_FR32, MCK_FR32 } },
+ { X86::ADDPSrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_addps, MCK_Mem, MCK_FR32 } },
+ { X86::ADD64rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_addq, MCK_GR64, MCK_GR64 } },
+ { X86::ADD64mr, Convert__Mem5_2__Reg1_1, { MCK_addq, MCK_GR64, MCK_Mem } },
+ { X86::ADD64ri8, Convert__Reg1_2__Tie0__ImmSExt81_1, { MCK_addq, MCK_ImmSExt8, MCK_GR64 } },
+ { X86::ADD64mi8, Convert__Mem5_2__ImmSExt81_1, { MCK_addq, MCK_ImmSExt8, MCK_Mem } },
+ { X86::ADD64i32, Convert__Imm1_1, { MCK_addq, MCK_Imm, MCK_RAX } },
+ { X86::ADD64ri32, Convert__Reg1_2__Tie0__Imm1_1, { MCK_addq, MCK_Imm, MCK_GR64 } },
+ { X86::ADD64mi32, Convert__Mem5_2__Imm1_1, { MCK_addq, MCK_Imm, MCK_Mem } },
+ { X86::ADD64rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_addq, MCK_Mem, MCK_GR64 } },
+ { X86::ADDSDrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_addsd, MCK_FR32, MCK_FR32 } },
+ { X86::ADDSDrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_addsd, MCK_Mem, MCK_FR32 } },
+ { X86::ADDSSrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_addss, MCK_FR32, MCK_FR32 } },
+ { X86::ADDSSrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_addss, MCK_Mem, MCK_FR32 } },
+ { X86::ADDSUBPDrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_addsubpd, MCK_FR32, MCK_FR32 } },
+ { X86::ADDSUBPDrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_addsubpd, MCK_Mem, MCK_FR32 } },
+ { X86::ADDSUBPSrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_addsubps, MCK_FR32, MCK_FR32 } },
+ { X86::ADDSUBPSrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_addsubps, MCK_Mem, MCK_FR32 } },
+ { X86::ADD16mrmrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_addw, MCK_GR16, MCK_GR16 } },
+ { X86::ADD16rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_addw, MCK_GR16, MCK_GR16 } },
+ { X86::ADD16mr, Convert__Mem5_2__Reg1_1, { MCK_addw, MCK_GR16, MCK_Mem } },
+ { X86::ADD16ri8, Convert__Reg1_2__Tie0__ImmSExt81_1, { MCK_addw, MCK_ImmSExt8, MCK_GR16 } },
+ { X86::ADD16mi8, Convert__Mem5_2__ImmSExt81_1, { MCK_addw, MCK_ImmSExt8, MCK_Mem } },
+ { X86::ADD16i16, Convert__Imm1_1, { MCK_addw, MCK_Imm, MCK_AX } },
+ { X86::ADD16ri, Convert__Reg1_2__Tie0__Imm1_1, { MCK_addw, MCK_Imm, MCK_GR16 } },
+ { X86::ADD16mi, Convert__Mem5_2__Imm1_1, { MCK_addw, MCK_Imm, MCK_Mem } },
+ { X86::ADD16rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_addw, MCK_Mem, MCK_GR16 } },
+ { X86::AND8rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_andb, MCK_GR8, MCK_GR8 } },
+ { X86::AND8rr_REV, Convert__Reg1_2__Tie0__Reg1_1, { MCK_andb, MCK_GR8, MCK_GR8 } },
+ { X86::AND8mr, Convert__Mem5_2__Reg1_1, { MCK_andb, MCK_GR8, MCK_Mem } },
+ { X86::AND8i8, Convert__Imm1_1, { MCK_andb, MCK_Imm, MCK_AL } },
+ { X86::AND8ri, Convert__Reg1_2__Tie0__Imm1_1, { MCK_andb, MCK_Imm, MCK_GR8 } },
+ { X86::AND8mi, Convert__Mem5_2__Imm1_1, { MCK_andb, MCK_Imm, MCK_Mem } },
+ { X86::AND8rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_andb, MCK_Mem, MCK_GR8 } },
+ { X86::AND32rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_andl, MCK_GR32, MCK_GR32 } },
+ { X86::AND32rr_REV, Convert__Reg1_2__Tie0__Reg1_1, { MCK_andl, MCK_GR32, MCK_GR32 } },
+ { X86::AND32mr, Convert__Mem5_2__Reg1_1, { MCK_andl, MCK_GR32, MCK_Mem } },
+ { X86::AND32ri8, Convert__Reg1_2__Tie0__ImmSExt81_1, { MCK_andl, MCK_ImmSExt8, MCK_GR32 } },
+ { X86::AND32mi8, Convert__Mem5_2__ImmSExt81_1, { MCK_andl, MCK_ImmSExt8, MCK_Mem } },
+ { X86::AND32i32, Convert__Imm1_1, { MCK_andl, MCK_Imm, MCK_EAX } },
+ { X86::AND32ri, Convert__Reg1_2__Tie0__Imm1_1, { MCK_andl, MCK_Imm, MCK_GR32 } },
+ { X86::AND32mi, Convert__Mem5_2__Imm1_1, { MCK_andl, MCK_Imm, MCK_Mem } },
+ { X86::AND32rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_andl, MCK_Mem, MCK_GR32 } },
+ { X86::ANDNPDrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_andnpd, MCK_FR32, MCK_FR32 } },
+ { X86::FsANDNPDrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_andnpd, MCK_FR32, MCK_FR32 } },
+ { X86::ANDNPDrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_andnpd, MCK_Mem, MCK_FR32 } },
+ { X86::FsANDNPDrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_andnpd, MCK_Mem, MCK_FR32 } },
+ { X86::ANDNPSrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_andnps, MCK_FR32, MCK_FR32 } },
+ { X86::FsANDNPSrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_andnps, MCK_FR32, MCK_FR32 } },
+ { X86::ANDNPSrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_andnps, MCK_Mem, MCK_FR32 } },
+ { X86::FsANDNPSrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_andnps, MCK_Mem, MCK_FR32 } },
+ { X86::ANDPDrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_andpd, MCK_FR32, MCK_FR32 } },
+ { X86::FsANDPDrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_andpd, MCK_FR32, MCK_FR32 } },
+ { X86::ANDPDrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_andpd, MCK_Mem, MCK_FR32 } },
+ { X86::FsANDPDrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_andpd, MCK_Mem, MCK_FR32 } },
+ { X86::ANDPSrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_andps, MCK_FR32, MCK_FR32 } },
+ { X86::FsANDPSrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_andps, MCK_FR32, MCK_FR32 } },
+ { X86::ANDPSrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_andps, MCK_Mem, MCK_FR32 } },
+ { X86::FsANDPSrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_andps, MCK_Mem, MCK_FR32 } },
+ { X86::AND64rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_andq, MCK_GR64, MCK_GR64 } },
+ { X86::AND64rr_REV, Convert__Reg1_2__Tie0__Reg1_1, { MCK_andq, MCK_GR64, MCK_GR64 } },
+ { X86::AND64mr, Convert__Mem5_2__Reg1_1, { MCK_andq, MCK_GR64, MCK_Mem } },
+ { X86::AND64ri8, Convert__Reg1_2__Tie0__ImmSExt81_1, { MCK_andq, MCK_ImmSExt8, MCK_GR64 } },
+ { X86::AND64mi8, Convert__Mem5_2__ImmSExt81_1, { MCK_andq, MCK_ImmSExt8, MCK_Mem } },
+ { X86::AND64i32, Convert__Imm1_1, { MCK_andq, MCK_Imm, MCK_RAX } },
+ { X86::AND64ri32, Convert__Reg1_2__Tie0__Imm1_1, { MCK_andq, MCK_Imm, MCK_GR64 } },
+ { X86::AND64mi32, Convert__Mem5_2__Imm1_1, { MCK_andq, MCK_Imm, MCK_Mem } },
+ { X86::AND64rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_andq, MCK_Mem, MCK_GR64 } },
+ { X86::AND16rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_andw, MCK_GR16, MCK_GR16 } },
+ { X86::AND16rr_REV, Convert__Reg1_2__Tie0__Reg1_1, { MCK_andw, MCK_GR16, MCK_GR16 } },
+ { X86::AND16mr, Convert__Mem5_2__Reg1_1, { MCK_andw, MCK_GR16, MCK_Mem } },
+ { X86::AND16ri8, Convert__Reg1_2__Tie0__ImmSExt81_1, { MCK_andw, MCK_ImmSExt8, MCK_GR16 } },
+ { X86::AND16mi8, Convert__Mem5_2__ImmSExt81_1, { MCK_andw, MCK_ImmSExt8, MCK_Mem } },
+ { X86::AND16i16, Convert__Imm1_1, { MCK_andw, MCK_Imm, MCK_AX } },
+ { X86::AND16ri, Convert__Reg1_2__Tie0__Imm1_1, { MCK_andw, MCK_Imm, MCK_GR16 } },
+ { X86::AND16mi, Convert__Mem5_2__Imm1_1, { MCK_andw, MCK_Imm, MCK_Mem } },
+ { X86::AND16rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_andw, MCK_Mem, MCK_GR16 } },
+ { X86::BSF32rr, Convert__Reg1_2__Reg1_1, { MCK_bsfl, MCK_GR32, MCK_GR32 } },
+ { X86::BSF32rm, Convert__Reg1_2__Mem5_1, { MCK_bsfl, MCK_Mem, MCK_GR32 } },
+ { X86::BSF64rr, Convert__Reg1_2__Reg1_1, { MCK_bsfq, MCK_GR64, MCK_GR64 } },
+ { X86::BSF64rm, Convert__Reg1_2__Mem5_1, { MCK_bsfq, MCK_Mem, MCK_GR64 } },
+ { X86::BSF16rr, Convert__Reg1_2__Reg1_1, { MCK_bsfw, MCK_GR16, MCK_GR16 } },
+ { X86::BSF16rm, Convert__Reg1_2__Mem5_1, { MCK_bsfw, MCK_Mem, MCK_GR16 } },
+ { X86::BSR32rr, Convert__Reg1_2__Reg1_1, { MCK_bsrl, MCK_GR32, MCK_GR32 } },
+ { X86::BSR32rm, Convert__Reg1_2__Mem5_1, { MCK_bsrl, MCK_Mem, MCK_GR32 } },
+ { X86::BSR64rr, Convert__Reg1_2__Reg1_1, { MCK_bsrq, MCK_GR64, MCK_GR64 } },
+ { X86::BSR64rm, Convert__Reg1_2__Mem5_1, { MCK_bsrq, MCK_Mem, MCK_GR64 } },
+ { X86::BSR16rr, Convert__Reg1_2__Reg1_1, { MCK_bsrw, MCK_GR16, MCK_GR16 } },
+ { X86::BSR16rm, Convert__Reg1_2__Mem5_1, { MCK_bsrw, MCK_Mem, MCK_GR16 } },
+ { X86::BTC32rr, Convert__Reg1_2__Reg1_1, { MCK_btcl, MCK_GR32, MCK_GR32 } },
+ { X86::BTC32mr, Convert__Mem5_2__Reg1_1, { MCK_btcl, MCK_GR32, MCK_Mem } },
+ { X86::BTC32ri8, Convert__Reg1_2__ImmSExt81_1, { MCK_btcl, MCK_ImmSExt8, MCK_GR32 } },
+ { X86::BTC32mi8, Convert__Mem5_2__ImmSExt81_1, { MCK_btcl, MCK_ImmSExt8, MCK_Mem } },
+ { X86::BTC64rr, Convert__Reg1_2__Reg1_1, { MCK_btcq, MCK_GR64, MCK_GR64 } },
+ { X86::BTC64mr, Convert__Mem5_2__Reg1_1, { MCK_btcq, MCK_GR64, MCK_Mem } },
+ { X86::BTC64ri8, Convert__Reg1_2__ImmSExt81_1, { MCK_btcq, MCK_ImmSExt8, MCK_GR64 } },
+ { X86::BTC64mi8, Convert__Mem5_2__ImmSExt81_1, { MCK_btcq, MCK_ImmSExt8, MCK_Mem } },
+ { X86::BTC16rr, Convert__Reg1_2__Reg1_1, { MCK_btcw, MCK_GR16, MCK_GR16 } },
+ { X86::BTC16mr, Convert__Mem5_2__Reg1_1, { MCK_btcw, MCK_GR16, MCK_Mem } },
+ { X86::BTC16ri8, Convert__Reg1_2__ImmSExt81_1, { MCK_btcw, MCK_ImmSExt8, MCK_GR16 } },
+ { X86::BTC16mi8, Convert__Mem5_2__ImmSExt81_1, { MCK_btcw, MCK_ImmSExt8, MCK_Mem } },
+ { X86::BT32rr, Convert__Reg1_2__Reg1_1, { MCK_btl, MCK_GR32, MCK_GR32 } },
+ { X86::BT32mr, Convert__Mem5_2__Reg1_1, { MCK_btl, MCK_GR32, MCK_Mem } },
+ { X86::BT32ri8, Convert__Reg1_2__ImmSExt81_1, { MCK_btl, MCK_ImmSExt8, MCK_GR32 } },
+ { X86::BT32mi8, Convert__Mem5_2__ImmSExt81_1, { MCK_btl, MCK_ImmSExt8, MCK_Mem } },
+ { X86::BT64rr, Convert__Reg1_2__Reg1_1, { MCK_btq, MCK_GR64, MCK_GR64 } },
+ { X86::BT64mr, Convert__Mem5_2__Reg1_1, { MCK_btq, MCK_GR64, MCK_Mem } },
+ { X86::BT64ri8, Convert__Reg1_2__ImmSExt81_1, { MCK_btq, MCK_ImmSExt8, MCK_GR64 } },
+ { X86::BT64mi8, Convert__Mem5_2__ImmSExt81_1, { MCK_btq, MCK_ImmSExt8, MCK_Mem } },
+ { X86::BTR32rr, Convert__Reg1_2__Reg1_1, { MCK_btrl, MCK_GR32, MCK_GR32 } },
+ { X86::BTR32mr, Convert__Mem5_2__Reg1_1, { MCK_btrl, MCK_GR32, MCK_Mem } },
+ { X86::BTR32ri8, Convert__Reg1_2__ImmSExt81_1, { MCK_btrl, MCK_ImmSExt8, MCK_GR32 } },
+ { X86::BTR32mi8, Convert__Mem5_2__ImmSExt81_1, { MCK_btrl, MCK_ImmSExt8, MCK_Mem } },
+ { X86::BTR64rr, Convert__Reg1_2__Reg1_1, { MCK_btrq, MCK_GR64, MCK_GR64 } },
+ { X86::BTR64mr, Convert__Mem5_2__Reg1_1, { MCK_btrq, MCK_GR64, MCK_Mem } },
+ { X86::BTR64ri8, Convert__Reg1_2__ImmSExt81_1, { MCK_btrq, MCK_ImmSExt8, MCK_GR64 } },
+ { X86::BTR64mi8, Convert__Mem5_2__ImmSExt81_1, { MCK_btrq, MCK_ImmSExt8, MCK_Mem } },
+ { X86::BTR16rr, Convert__Reg1_2__Reg1_1, { MCK_btrw, MCK_GR16, MCK_GR16 } },
+ { X86::BTR16mr, Convert__Mem5_2__Reg1_1, { MCK_btrw, MCK_GR16, MCK_Mem } },
+ { X86::BTR16ri8, Convert__Reg1_2__ImmSExt81_1, { MCK_btrw, MCK_ImmSExt8, MCK_GR16 } },
+ { X86::BTR16mi8, Convert__Mem5_2__ImmSExt81_1, { MCK_btrw, MCK_ImmSExt8, MCK_Mem } },
+ { X86::BTS32rr, Convert__Reg1_2__Reg1_1, { MCK_btsl, MCK_GR32, MCK_GR32 } },
+ { X86::BTS32mr, Convert__Mem5_2__Reg1_1, { MCK_btsl, MCK_GR32, MCK_Mem } },
+ { X86::BTS32ri8, Convert__Reg1_2__ImmSExt81_1, { MCK_btsl, MCK_ImmSExt8, MCK_GR32 } },
+ { X86::BTS32mi8, Convert__Mem5_2__ImmSExt81_1, { MCK_btsl, MCK_ImmSExt8, MCK_Mem } },
+ { X86::BTS64rr, Convert__Reg1_2__Reg1_1, { MCK_btsq, MCK_GR64, MCK_GR64 } },
+ { X86::BTS64mr, Convert__Mem5_2__Reg1_1, { MCK_btsq, MCK_GR64, MCK_Mem } },
+ { X86::BTS64ri8, Convert__Reg1_2__ImmSExt81_1, { MCK_btsq, MCK_ImmSExt8, MCK_GR64 } },
+ { X86::BTS64mi8, Convert__Mem5_2__ImmSExt81_1, { MCK_btsq, MCK_ImmSExt8, MCK_Mem } },
+ { X86::BTS16rr, Convert__Reg1_2__Reg1_1, { MCK_btsw, MCK_GR16, MCK_GR16 } },
+ { X86::BTS16mr, Convert__Mem5_2__Reg1_1, { MCK_btsw, MCK_GR16, MCK_Mem } },
+ { X86::BTS16ri8, Convert__Reg1_2__ImmSExt81_1, { MCK_btsw, MCK_ImmSExt8, MCK_GR16 } },
+ { X86::BTS16mi8, Convert__Mem5_2__ImmSExt81_1, { MCK_btsw, MCK_ImmSExt8, MCK_Mem } },
+ { X86::BT16rr, Convert__Reg1_2__Reg1_1, { MCK_btw, MCK_GR16, MCK_GR16 } },
+ { X86::BT16mr, Convert__Mem5_2__Reg1_1, { MCK_btw, MCK_GR16, MCK_Mem } },
+ { X86::BT16ri8, Convert__Reg1_2__ImmSExt81_1, { MCK_btw, MCK_ImmSExt8, MCK_GR16 } },
+ { X86::BT16mi8, Convert__Mem5_2__ImmSExt81_1, { MCK_btw, MCK_ImmSExt8, MCK_Mem } },
+ { X86::CALL32r, Convert__Reg1_2, { MCK_call, MCK__STAR_, MCK_GR32 } },
+ { X86::WINCALL64r, Convert__Reg1_2, { MCK_call, MCK__STAR_, MCK_GR64 } },
+ { X86::CALL32m, Convert__Mem5_2, { MCK_call, MCK__STAR_, MCK_Mem } },
+ { X86::WINCALL64m, Convert__Mem5_2, { MCK_call, MCK__STAR_, MCK_Mem } },
+ { X86::CALL64r, Convert__Reg1_2, { MCK_callq, MCK__STAR_, MCK_GR64 } },
+ { X86::CALL64m, Convert__Mem5_2, { MCK_callq, MCK__STAR_, MCK_Mem } },
+ { X86::CMOVAE32rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_cmovael, MCK_GR32, MCK_GR32 } },
+ { X86::CMOVAE32rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_cmovael, MCK_Mem, MCK_GR32 } },
+ { X86::CMOVAE64rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_cmovaeq, MCK_GR64, MCK_GR64 } },
+ { X86::CMOVAE64rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_cmovaeq, MCK_Mem, MCK_GR64 } },
+ { X86::CMOVAE16rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_cmovaew, MCK_GR16, MCK_GR16 } },
+ { X86::CMOVAE16rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_cmovaew, MCK_Mem, MCK_GR16 } },
+ { X86::CMOVA32rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_cmoval, MCK_GR32, MCK_GR32 } },
+ { X86::CMOVA32rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_cmoval, MCK_Mem, MCK_GR32 } },
+ { X86::CMOVA64rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_cmovaq, MCK_GR64, MCK_GR64 } },
+ { X86::CMOVA64rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_cmovaq, MCK_Mem, MCK_GR64 } },
+ { X86::CMOVA16rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_cmovaw, MCK_GR16, MCK_GR16 } },
+ { X86::CMOVA16rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_cmovaw, MCK_Mem, MCK_GR16 } },
+ { X86::CMOVBE32rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_cmovbel, MCK_GR32, MCK_GR32 } },
+ { X86::CMOVBE32rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_cmovbel, MCK_Mem, MCK_GR32 } },
+ { X86::CMOVBE64rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_cmovbeq, MCK_GR64, MCK_GR64 } },
+ { X86::CMOVBE64rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_cmovbeq, MCK_Mem, MCK_GR64 } },
+ { X86::CMOVBE16rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_cmovbew, MCK_GR16, MCK_GR16 } },
+ { X86::CMOVBE16rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_cmovbew, MCK_Mem, MCK_GR16 } },
+ { X86::CMOVB32rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_cmovbl, MCK_GR32, MCK_GR32 } },
+ { X86::CMOVB32rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_cmovbl, MCK_Mem, MCK_GR32 } },
+ { X86::CMOVB64rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_cmovbq, MCK_GR64, MCK_GR64 } },
+ { X86::CMOVB64rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_cmovbq, MCK_Mem, MCK_GR64 } },
+ { X86::CMOVB16rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_cmovbw, MCK_GR16, MCK_GR16 } },
+ { X86::CMOVB16rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_cmovbw, MCK_Mem, MCK_GR16 } },
+ { X86::CMOVE32rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_cmovel, MCK_GR32, MCK_GR32 } },
+ { X86::CMOVE32rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_cmovel, MCK_Mem, MCK_GR32 } },
+ { X86::CMOVE64rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_cmoveq, MCK_GR64, MCK_GR64 } },
+ { X86::CMOVE64rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_cmoveq, MCK_Mem, MCK_GR64 } },
+ { X86::CMOVE16rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_cmovew, MCK_GR16, MCK_GR16 } },
+ { X86::CMOVE16rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_cmovew, MCK_Mem, MCK_GR16 } },
+ { X86::CMOVGE32rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_cmovgel, MCK_GR32, MCK_GR32 } },
+ { X86::CMOVGE32rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_cmovgel, MCK_Mem, MCK_GR32 } },
+ { X86::CMOVGE64rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_cmovgeq, MCK_GR64, MCK_GR64 } },
+ { X86::CMOVGE64rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_cmovgeq, MCK_Mem, MCK_GR64 } },
+ { X86::CMOVGE16rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_cmovgew, MCK_GR16, MCK_GR16 } },
+ { X86::CMOVGE16rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_cmovgew, MCK_Mem, MCK_GR16 } },
+ { X86::CMOVG32rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_cmovgl, MCK_GR32, MCK_GR32 } },
+ { X86::CMOVG32rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_cmovgl, MCK_Mem, MCK_GR32 } },
+ { X86::CMOVG64rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_cmovgq, MCK_GR64, MCK_GR64 } },
+ { X86::CMOVG64rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_cmovgq, MCK_Mem, MCK_GR64 } },
+ { X86::CMOVG16rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_cmovgw, MCK_GR16, MCK_GR16 } },
+ { X86::CMOVG16rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_cmovgw, MCK_Mem, MCK_GR16 } },
+ { X86::CMOVLE32rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_cmovlel, MCK_GR32, MCK_GR32 } },
+ { X86::CMOVLE32rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_cmovlel, MCK_Mem, MCK_GR32 } },
+ { X86::CMOVLE64rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_cmovleq, MCK_GR64, MCK_GR64 } },
+ { X86::CMOVLE64rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_cmovleq, MCK_Mem, MCK_GR64 } },
+ { X86::CMOVLE16rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_cmovlew, MCK_GR16, MCK_GR16 } },
+ { X86::CMOVLE16rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_cmovlew, MCK_Mem, MCK_GR16 } },
+ { X86::CMOVL32rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_cmovll, MCK_GR32, MCK_GR32 } },
+ { X86::CMOVL32rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_cmovll, MCK_Mem, MCK_GR32 } },
+ { X86::CMOVL64rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_cmovlq, MCK_GR64, MCK_GR64 } },
+ { X86::CMOVL64rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_cmovlq, MCK_Mem, MCK_GR64 } },
+ { X86::CMOVL16rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_cmovlw, MCK_GR16, MCK_GR16 } },
+ { X86::CMOVL16rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_cmovlw, MCK_Mem, MCK_GR16 } },
+ { X86::CMOVNE32rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_cmovnel, MCK_GR32, MCK_GR32 } },
+ { X86::CMOVNE32rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_cmovnel, MCK_Mem, MCK_GR32 } },
+ { X86::CMOVNE64rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_cmovneq, MCK_GR64, MCK_GR64 } },
+ { X86::CMOVNE64rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_cmovneq, MCK_Mem, MCK_GR64 } },
+ { X86::CMOVNE16rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_cmovnew, MCK_GR16, MCK_GR16 } },
+ { X86::CMOVNE16rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_cmovnew, MCK_Mem, MCK_GR16 } },
+ { X86::CMOVNO32rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_cmovnol, MCK_GR32, MCK_GR32 } },
+ { X86::CMOVNO32rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_cmovnol, MCK_Mem, MCK_GR32 } },
+ { X86::CMOVNO64rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_cmovnoq, MCK_GR64, MCK_GR64 } },
+ { X86::CMOVNO64rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_cmovnoq, MCK_Mem, MCK_GR64 } },
+ { X86::CMOVNO16rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_cmovnow, MCK_GR16, MCK_GR16 } },
+ { X86::CMOVNO16rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_cmovnow, MCK_Mem, MCK_GR16 } },
+ { X86::CMOVNP32rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_cmovnpl, MCK_GR32, MCK_GR32 } },
+ { X86::CMOVNP32rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_cmovnpl, MCK_Mem, MCK_GR32 } },
+ { X86::CMOVNP64rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_cmovnpq, MCK_GR64, MCK_GR64 } },
+ { X86::CMOVNP64rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_cmovnpq, MCK_Mem, MCK_GR64 } },
+ { X86::CMOVNP16rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_cmovnpw, MCK_GR16, MCK_GR16 } },
+ { X86::CMOVNP16rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_cmovnpw, MCK_Mem, MCK_GR16 } },
+ { X86::CMOVNS32rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_cmovnsl, MCK_GR32, MCK_GR32 } },
+ { X86::CMOVNS32rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_cmovnsl, MCK_Mem, MCK_GR32 } },
+ { X86::CMOVNS64rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_cmovnsq, MCK_GR64, MCK_GR64 } },
+ { X86::CMOVNS64rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_cmovnsq, MCK_Mem, MCK_GR64 } },
+ { X86::CMOVNS16rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_cmovnsw, MCK_GR16, MCK_GR16 } },
+ { X86::CMOVNS16rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_cmovnsw, MCK_Mem, MCK_GR16 } },
+ { X86::CMOVO32rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_cmovol, MCK_GR32, MCK_GR32 } },
+ { X86::CMOVO32rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_cmovol, MCK_Mem, MCK_GR32 } },
+ { X86::CMOVO64rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_cmovoq, MCK_GR64, MCK_GR64 } },
+ { X86::CMOVO64rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_cmovoq, MCK_Mem, MCK_GR64 } },
+ { X86::CMOVO16rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_cmovow, MCK_GR16, MCK_GR16 } },
+ { X86::CMOVO16rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_cmovow, MCK_Mem, MCK_GR16 } },
+ { X86::CMOVP32rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_cmovpl, MCK_GR32, MCK_GR32 } },
+ { X86::CMOVP32rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_cmovpl, MCK_Mem, MCK_GR32 } },
+ { X86::CMOVP64rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_cmovpq, MCK_GR64, MCK_GR64 } },
+ { X86::CMOVP64rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_cmovpq, MCK_Mem, MCK_GR64 } },
+ { X86::CMOVP16rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_cmovpw, MCK_GR16, MCK_GR16 } },
+ { X86::CMOVP16rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_cmovpw, MCK_Mem, MCK_GR16 } },
+ { X86::CMOVS32rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_cmovsl, MCK_GR32, MCK_GR32 } },
+ { X86::CMOVS32rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_cmovsl, MCK_Mem, MCK_GR32 } },
+ { X86::CMOVS64rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_cmovsq, MCK_GR64, MCK_GR64 } },
+ { X86::CMOVS64rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_cmovsq, MCK_Mem, MCK_GR64 } },
+ { X86::CMOVS16rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_cmovsw, MCK_GR16, MCK_GR16 } },
+ { X86::CMOVS16rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_cmovsw, MCK_Mem, MCK_GR16 } },
+ { X86::CMP8mrmrr, Convert__Reg1_2__Reg1_1, { MCK_cmpb, MCK_GR8, MCK_GR8 } },
+ { X86::CMP8rr, Convert__Reg1_2__Reg1_1, { MCK_cmpb, MCK_GR8, MCK_GR8 } },
+ { X86::CMP8mr, Convert__Mem5_2__Reg1_1, { MCK_cmpb, MCK_GR8, MCK_Mem } },
+ { X86::CMP8i8, Convert__Imm1_1, { MCK_cmpb, MCK_Imm, MCK_AL } },
+ { X86::CMP8ri, Convert__Reg1_2__Imm1_1, { MCK_cmpb, MCK_Imm, MCK_GR8 } },
+ { X86::CMP8mi, Convert__Mem5_2__Imm1_1, { MCK_cmpb, MCK_Imm, MCK_Mem } },
+ { X86::CMP8rm, Convert__Reg1_2__Mem5_1, { MCK_cmpb, MCK_Mem, MCK_GR8 } },
+ { X86::CMP32mrmrr, Convert__Reg1_2__Reg1_1, { MCK_cmpl, MCK_GR32, MCK_GR32 } },
+ { X86::CMP32rr, Convert__Reg1_2__Reg1_1, { MCK_cmpl, MCK_GR32, MCK_GR32 } },
+ { X86::CMP32mr, Convert__Mem5_2__Reg1_1, { MCK_cmpl, MCK_GR32, MCK_Mem } },
+ { X86::CMP32ri8, Convert__Reg1_2__ImmSExt81_1, { MCK_cmpl, MCK_ImmSExt8, MCK_GR32 } },
+ { X86::CMP32mi8, Convert__Mem5_2__ImmSExt81_1, { MCK_cmpl, MCK_ImmSExt8, MCK_Mem } },
+ { X86::CMP32i32, Convert__Imm1_1, { MCK_cmpl, MCK_Imm, MCK_EAX } },
+ { X86::CMP32ri, Convert__Reg1_2__Imm1_1, { MCK_cmpl, MCK_Imm, MCK_GR32 } },
+ { X86::CMP32mi, Convert__Mem5_2__Imm1_1, { MCK_cmpl, MCK_Imm, MCK_Mem } },
+ { X86::CMP32rm, Convert__Reg1_2__Mem5_1, { MCK_cmpl, MCK_Mem, MCK_GR32 } },
+ { X86::CMP64mrmrr, Convert__Reg1_2__Reg1_1, { MCK_cmpq, MCK_GR64, MCK_GR64 } },
+ { X86::CMP64rr, Convert__Reg1_2__Reg1_1, { MCK_cmpq, MCK_GR64, MCK_GR64 } },
+ { X86::CMP64mr, Convert__Mem5_2__Reg1_1, { MCK_cmpq, MCK_GR64, MCK_Mem } },
+ { X86::CMP64ri8, Convert__Reg1_2__ImmSExt81_1, { MCK_cmpq, MCK_ImmSExt8, MCK_GR64 } },
+ { X86::CMP64mi8, Convert__Mem5_2__ImmSExt81_1, { MCK_cmpq, MCK_ImmSExt8, MCK_Mem } },
+ { X86::CMP64i32, Convert__Imm1_1, { MCK_cmpq, MCK_Imm, MCK_RAX } },
+ { X86::CMP64ri32, Convert__Reg1_2__Imm1_1, { MCK_cmpq, MCK_Imm, MCK_GR64 } },
+ { X86::CMP64mi32, Convert__Mem5_2__Imm1_1, { MCK_cmpq, MCK_Imm, MCK_Mem } },
+ { X86::CMP64rm, Convert__Reg1_2__Mem5_1, { MCK_cmpq, MCK_Mem, MCK_GR64 } },
+ { X86::CMP16mrmrr, Convert__Reg1_2__Reg1_1, { MCK_cmpw, MCK_GR16, MCK_GR16 } },
+ { X86::CMP16rr, Convert__Reg1_2__Reg1_1, { MCK_cmpw, MCK_GR16, MCK_GR16 } },
+ { X86::CMP16mr, Convert__Mem5_2__Reg1_1, { MCK_cmpw, MCK_GR16, MCK_Mem } },
+ { X86::CMP16ri8, Convert__Reg1_2__ImmSExt81_1, { MCK_cmpw, MCK_ImmSExt8, MCK_GR16 } },
+ { X86::CMP16mi8, Convert__Mem5_2__ImmSExt81_1, { MCK_cmpw, MCK_ImmSExt8, MCK_Mem } },
+ { X86::CMP16i16, Convert__Imm1_1, { MCK_cmpw, MCK_Imm, MCK_AX } },
+ { X86::CMP16ri, Convert__Reg1_2__Imm1_1, { MCK_cmpw, MCK_Imm, MCK_GR16 } },
+ { X86::CMP16mi, Convert__Mem5_2__Imm1_1, { MCK_cmpw, MCK_Imm, MCK_Mem } },
+ { X86::CMP16rm, Convert__Reg1_2__Mem5_1, { MCK_cmpw, MCK_Mem, MCK_GR16 } },
+ { X86::CMPXCHG8rr, Convert__Reg1_2__Reg1_1, { MCK_cmpxchgb, MCK_GR8, MCK_GR8 } },
+ { X86::CMPXCHG8rm, Convert__Mem5_2__Reg1_1, { MCK_cmpxchgb, MCK_GR8, MCK_Mem } },
+ { X86::CMPXCHG32rr, Convert__Reg1_2__Reg1_1, { MCK_cmpxchgl, MCK_GR32, MCK_GR32 } },
+ { X86::CMPXCHG32rm, Convert__Mem5_2__Reg1_1, { MCK_cmpxchgl, MCK_GR32, MCK_Mem } },
+ { X86::CMPXCHG64rr, Convert__Reg1_2__Reg1_1, { MCK_cmpxchgq, MCK_GR64, MCK_GR64 } },
+ { X86::CMPXCHG64rm, Convert__Mem5_2__Reg1_1, { MCK_cmpxchgq, MCK_GR64, MCK_Mem } },
+ { X86::CMPXCHG16rr, Convert__Reg1_2__Reg1_1, { MCK_cmpxchgw, MCK_GR16, MCK_GR16 } },
+ { X86::CMPXCHG16rm, Convert__Mem5_2__Reg1_1, { MCK_cmpxchgw, MCK_GR16, MCK_Mem } },
+ { X86::COMISDrr, Convert__Reg1_2__Reg1_1, { MCK_comisd, MCK_FR32, MCK_FR32 } },
+ { X86::COMISDrm, Convert__Reg1_2__Mem5_1, { MCK_comisd, MCK_Mem, MCK_FR32 } },
+ { X86::COMISSrr, Convert__Reg1_2__Reg1_1, { MCK_comiss, MCK_FR32, MCK_FR32 } },
+ { X86::COMISSrm, Convert__Reg1_2__Mem5_1, { MCK_comiss, MCK_Mem, MCK_FR32 } },
+ { X86::CRC32r8, Convert__Reg1_2__Tie0__Reg1_1, { MCK_crc32, MCK_GR8, MCK_GR32 } },
+ { X86::CRC32r16, Convert__Reg1_2__Tie0__Reg1_1, { MCK_crc32, MCK_GR16, MCK_GR32 } },
+ { X86::CRC32r32, Convert__Reg1_2__Tie0__Reg1_1, { MCK_crc32, MCK_GR32, MCK_GR32 } },
+ { X86::CRC64r64, Convert__Reg1_2__Tie0__Reg1_1, { MCK_crc32, MCK_GR64, MCK_GR64 } },
+ { X86::CRC32m16, Convert__Reg1_2__Tie0__Mem5_1, { MCK_crc32, MCK_Mem, MCK_GR32 } },
+ { X86::CRC32m32, Convert__Reg1_2__Tie0__Mem5_1, { MCK_crc32, MCK_Mem, MCK_GR32 } },
+ { X86::CRC32m8, Convert__Reg1_2__Tie0__Mem5_1, { MCK_crc32, MCK_Mem, MCK_GR32 } },
+ { X86::CRC64m64, Convert__Reg1_2__Tie0__Mem5_1, { MCK_crc32, MCK_Mem, MCK_GR64 } },
+ { X86::CVTDQ2PDrr, Convert__Reg1_2__Reg1_1, { MCK_cvtdq2pd, MCK_FR32, MCK_FR32 } },
+ { X86::CVTDQ2PDrm, Convert__Reg1_2__Mem5_1, { MCK_cvtdq2pd, MCK_Mem, MCK_FR32 } },
+ { X86::CVTDQ2PSrr, Convert__Reg1_2__Reg1_1, { MCK_cvtdq2ps, MCK_FR32, MCK_FR32 } },
+ { X86::CVTDQ2PSrm, Convert__Reg1_2__Mem5_1, { MCK_cvtdq2ps, MCK_Mem, MCK_FR32 } },
+ { X86::CVTPD2DQrr, Convert__Reg1_2__Reg1_1, { MCK_cvtpd2dq, MCK_FR32, MCK_FR32 } },
+ { X86::CVTPD2DQrm, Convert__Reg1_2__Mem5_1, { MCK_cvtpd2dq, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_CVTPD2PIrr, Convert__Reg1_2__Reg1_1, { MCK_cvtpd2pi, MCK_FR32, MCK_VR64 } },
+ { X86::MMX_CVTPD2PIrm, Convert__Reg1_2__Mem5_1, { MCK_cvtpd2pi, MCK_Mem, MCK_VR64 } },
+ { X86::CVTPD2PSrr, Convert__Reg1_2__Reg1_1, { MCK_cvtpd2ps, MCK_FR32, MCK_FR32 } },
+ { X86::CVTPD2PSrm, Convert__Reg1_2__Mem5_1, { MCK_cvtpd2ps, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_CVTPI2PDrr, Convert__Reg1_2__Reg1_1, { MCK_cvtpi2pd, MCK_VR64, MCK_FR32 } },
+ { X86::MMX_CVTPI2PDrm, Convert__Reg1_2__Mem5_1, { MCK_cvtpi2pd, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_CVTPI2PSrr, Convert__Reg1_2__Reg1_1, { MCK_cvtpi2ps, MCK_VR64, MCK_FR32 } },
+ { X86::MMX_CVTPI2PSrm, Convert__Reg1_2__Mem5_1, { MCK_cvtpi2ps, MCK_Mem, MCK_FR32 } },
+ { X86::CVTPS2DQrr, Convert__Reg1_2__Reg1_1, { MCK_cvtps2dq, MCK_FR32, MCK_FR32 } },
+ { X86::CVTPS2DQrm, Convert__Reg1_2__Mem5_1, { MCK_cvtps2dq, MCK_Mem, MCK_FR32 } },
+ { X86::CVTPS2PDrr, Convert__Reg1_2__Reg1_1, { MCK_cvtps2pd, MCK_FR32, MCK_FR32 } },
+ { X86::CVTPS2PDrm, Convert__Reg1_2__Mem5_1, { MCK_cvtps2pd, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_CVTPS2PIrr, Convert__Reg1_2__Reg1_1, { MCK_cvtps2pi, MCK_FR32, MCK_VR64 } },
+ { X86::MMX_CVTPS2PIrm, Convert__Reg1_2__Mem5_1, { MCK_cvtps2pi, MCK_Mem, MCK_VR64 } },
+ { X86::CVTSD2SI64rr, Convert__Reg1_2__Reg1_1, { MCK_cvtsd2siq, MCK_FR32, MCK_GR64 } },
+ { X86::CVTSD2SI64rm, Convert__Reg1_2__Mem5_1, { MCK_cvtsd2siq, MCK_Mem, MCK_GR64 } },
+ { X86::CVTSD2SSrr, Convert__Reg1_2__Reg1_1, { MCK_cvtsd2ss, MCK_FR32, MCK_FR32 } },
+ { X86::CVTSD2SSrm, Convert__Reg1_2__Mem5_1, { MCK_cvtsd2ss, MCK_Mem, MCK_FR32 } },
+ { X86::CVTSI2SDrr, Convert__Reg1_2__Reg1_1, { MCK_cvtsi2sd, MCK_GR32, MCK_FR32 } },
+ { X86::CVTSI2SDrm, Convert__Reg1_2__Mem5_1, { MCK_cvtsi2sd, MCK_Mem, MCK_FR32 } },
+ { X86::CVTSI2SD64rr, Convert__Reg1_2__Reg1_1, { MCK_cvtsi2sdq, MCK_GR64, MCK_FR32 } },
+ { X86::CVTSI2SD64rm, Convert__Reg1_2__Mem5_1, { MCK_cvtsi2sdq, MCK_Mem, MCK_FR32 } },
+ { X86::CVTSI2SSrr, Convert__Reg1_2__Reg1_1, { MCK_cvtsi2ss, MCK_GR32, MCK_FR32 } },
+ { X86::CVTSI2SSrm, Convert__Reg1_2__Mem5_1, { MCK_cvtsi2ss, MCK_Mem, MCK_FR32 } },
+ { X86::CVTSI2SS64rr, Convert__Reg1_2__Reg1_1, { MCK_cvtsi2ssq, MCK_GR64, MCK_FR32 } },
+ { X86::CVTSI2SS64rm, Convert__Reg1_2__Mem5_1, { MCK_cvtsi2ssq, MCK_Mem, MCK_FR32 } },
+ { X86::CVTSS2SDrr, Convert__Reg1_2__Reg1_1, { MCK_cvtss2sd, MCK_FR32, MCK_FR32 } },
+ { X86::CVTSS2SDrm, Convert__Reg1_2__Mem5_1, { MCK_cvtss2sd, MCK_Mem, MCK_FR32 } },
+ { X86::CVTSS2SIrr, Convert__Reg1_2__Reg1_1, { MCK_cvtss2sil, MCK_FR32, MCK_GR32 } },
+ { X86::CVTSS2SIrm, Convert__Reg1_2__Mem5_1, { MCK_cvtss2sil, MCK_Mem, MCK_GR32 } },
+ { X86::CVTSS2SI64rr, Convert__Reg1_2__Reg1_1, { MCK_cvtss2siq, MCK_FR32, MCK_GR64 } },
+ { X86::CVTSS2SI64rm, Convert__Reg1_2__Mem5_1, { MCK_cvtss2siq, MCK_Mem, MCK_GR64 } },
+ { X86::MMX_CVTTPD2PIrr, Convert__Reg1_2__Reg1_1, { MCK_cvttpd2pi, MCK_FR32, MCK_VR64 } },
+ { X86::MMX_CVTTPD2PIrm, Convert__Reg1_2__Mem5_1, { MCK_cvttpd2pi, MCK_Mem, MCK_VR64 } },
+ { X86::CVTTPS2DQrr, Convert__Reg1_2__Reg1_1, { MCK_cvttps2dq, MCK_FR32, MCK_FR32 } },
+ { X86::CVTTPS2DQrm, Convert__Reg1_2__Mem5_1, { MCK_cvttps2dq, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_CVTTPS2PIrr, Convert__Reg1_2__Reg1_1, { MCK_cvttps2pi, MCK_FR32, MCK_VR64 } },
+ { X86::MMX_CVTTPS2PIrm, Convert__Reg1_2__Mem5_1, { MCK_cvttps2pi, MCK_Mem, MCK_VR64 } },
+ { X86::CVTTSD2SIrr, Convert__Reg1_2__Reg1_1, { MCK_cvttsd2si, MCK_FR32, MCK_GR32 } },
+ { X86::CVTTSD2SIrm, Convert__Reg1_2__Mem5_1, { MCK_cvttsd2si, MCK_Mem, MCK_GR32 } },
+ { X86::CVTTSD2SI64rr, Convert__Reg1_2__Reg1_1, { MCK_cvttsd2siq, MCK_FR32, MCK_GR64 } },
+ { X86::CVTTSD2SI64rm, Convert__Reg1_2__Mem5_1, { MCK_cvttsd2siq, MCK_Mem, MCK_GR64 } },
+ { X86::CVTTSS2SIrr, Convert__Reg1_2__Reg1_1, { MCK_cvttss2si, MCK_FR32, MCK_GR32 } },
+ { X86::CVTTSS2SIrm, Convert__Reg1_2__Mem5_1, { MCK_cvttss2si, MCK_Mem, MCK_GR32 } },
+ { X86::CVTTSS2SI64rr, Convert__Reg1_2__Reg1_1, { MCK_cvttss2siq, MCK_FR32, MCK_GR64 } },
+ { X86::CVTTSS2SI64rm, Convert__Reg1_2__Mem5_1, { MCK_cvttss2siq, MCK_Mem, MCK_GR64 } },
+ { X86::DIVPDrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_divpd, MCK_FR32, MCK_FR32 } },
+ { X86::DIVPDrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_divpd, MCK_Mem, MCK_FR32 } },
+ { X86::DIVPSrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_divps, MCK_FR32, MCK_FR32 } },
+ { X86::DIVPSrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_divps, MCK_Mem, MCK_FR32 } },
+ { X86::DIVSDrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_divsd, MCK_FR32, MCK_FR32 } },
+ { X86::DIVSDrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_divsd, MCK_Mem, MCK_FR32 } },
+ { X86::DIVSSrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_divss, MCK_FR32, MCK_FR32 } },
+ { X86::DIVSSrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_divss, MCK_Mem, MCK_FR32 } },
+ { X86::ENTER, Convert__Imm1_1__Imm1_2, { MCK_enter, MCK_Imm, MCK_Imm } },
+ { X86::ADD_FrST0, Convert__Reg1_2, { MCK_fadd, MCK_ST0, MCK_RST } },
+ { X86::CMOVB_F, Convert__Reg1_1, { MCK_fcmovb, MCK_RST, MCK_ST0 } },
+ { X86::CMOVBE_F, Convert__Reg1_1, { MCK_fcmovbe, MCK_RST, MCK_ST0 } },
+ { X86::CMOVE_F, Convert__Reg1_1, { MCK_fcmove, MCK_RST, MCK_ST0 } },
+ { X86::CMOVNB_F, Convert__Reg1_1, { MCK_fcmovnb, MCK_RST, MCK_ST0 } },
+ { X86::CMOVNBE_F, Convert__Reg1_1, { MCK_fcmovnbe, MCK_RST, MCK_ST0 } },
+ { X86::CMOVNE_F, Convert__Reg1_1, { MCK_fcmovne, MCK_RST, MCK_ST0 } },
+ { X86::CMOVNP_F, Convert__Reg1_1, { MCK_fcmovnu, MCK_RST, MCK_ST0 } },
+ { X86::CMOVP_F, Convert__Reg1_1, { MCK_fcmovu, MCK_RST, MCK_ST0 } },
+ { X86::COM_FIr, Convert__Reg1_1, { MCK_fcomi, MCK_RST, MCK_ST0 } },
+ { X86::COM_FIPr, Convert__Reg1_1, { MCK_fcomip, MCK_RST, MCK_ST0 } },
+ { X86::DIVR_FrST0, Convert__Reg1_2, { MCK_fdiv, MCK_ST0, MCK_RST } },
+ { X86::DIV_FrST0, Convert__Reg1_2, { MCK_fdivr, MCK_ST0, MCK_RST } },
+ { X86::MUL_FrST0, Convert__Reg1_2, { MCK_fmul, MCK_ST0, MCK_RST } },
+ { X86::SUBR_FrST0, Convert__Reg1_2, { MCK_fsub, MCK_ST0, MCK_RST } },
+ { X86::SUB_FrST0, Convert__Reg1_2, { MCK_fsubr, MCK_ST0, MCK_RST } },
+ { X86::UCOM_FIr, Convert__Reg1_1, { MCK_fucomi, MCK_RST, MCK_ST0 } },
+ { X86::UCOM_FIPr, Convert__Reg1_1, { MCK_fucomip, MCK_RST, MCK_ST0 } },
+ { X86::HADDPDrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_haddpd, MCK_FR32, MCK_FR32 } },
+ { X86::HADDPDrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_haddpd, MCK_Mem, MCK_FR32 } },
+ { X86::HADDPSrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_haddps, MCK_FR32, MCK_FR32 } },
+ { X86::HADDPSrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_haddps, MCK_Mem, MCK_FR32 } },
+ { X86::HSUBPDrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_hsubpd, MCK_FR32, MCK_FR32 } },
+ { X86::HSUBPDrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_hsubpd, MCK_Mem, MCK_FR32 } },
+ { X86::HSUBPSrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_hsubps, MCK_FR32, MCK_FR32 } },
+ { X86::HSUBPSrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_hsubps, MCK_Mem, MCK_FR32 } },
+ { X86::IMUL32rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_imull, MCK_GR32, MCK_GR32 } },
+ { X86::IMUL32rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_imull, MCK_Mem, MCK_GR32 } },
+ { X86::IMUL64rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_imulq, MCK_GR64, MCK_GR64 } },
+ { X86::IMUL64rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_imulq, MCK_Mem, MCK_GR64 } },
+ { X86::IMUL16rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_imulw, MCK_GR16, MCK_GR16 } },
+ { X86::IMUL16rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_imulw, MCK_Mem, MCK_GR16 } },
{ X86::IN8rr, Convert, { MCK_inb, MCK_DX, MCK_AL } },
- { X86::IN8ri, Convert_ImmSExt81_1, { MCK_inb, MCK_ImmSExt8, MCK_AL } },
+ { X86::IN8ri, Convert__ImmSExt81_1, { MCK_inb, MCK_ImmSExt8, MCK_AL } },
{ X86::IN32rr, Convert, { MCK_inl, MCK_DX, MCK_EAX } },
- { X86::IN32ri, Convert_ImmSExt81_1, { MCK_inl, MCK_ImmSExt8, MCK_EAX } },
+ { X86::IN32ri, Convert__ImmSExt81_1, { MCK_inl, MCK_ImmSExt8, MCK_EAX } },
{ X86::IN16rr, Convert, { MCK_inw, MCK_DX, MCK_AX } },
- { X86::IN16ri, Convert_ImmSExt81_1, { MCK_inw, MCK_ImmSExt8, MCK_AX } },
- { X86::TAILJMPm, Convert_Mem5_2, { MCK_jmp, MCK__STAR_, MCK_Mem } },
- { X86::JMP32r, Convert_Reg1_2, { MCK_jmpl, MCK__STAR_, MCK_GR32 } },
- { X86::TAILJMPr, Convert_Reg1_2, { MCK_jmpl, MCK__STAR_, MCK_GR32 } },
- { X86::JMP32m, Convert_Mem5_2, { MCK_jmpl, MCK__STAR_, MCK_Mem } },
- { X86::JMP64r, Convert_Reg1_2, { MCK_jmpq, MCK__STAR_, MCK_GR64 } },
- { X86::TAILJMPr64, Convert_Reg1_2, { MCK_jmpq, MCK__STAR_, MCK_GR64 } },
- { X86::JMP64m, Convert_Mem5_2, { MCK_jmpq, MCK__STAR_, MCK_Mem } },
- { X86::LAR32rr, Convert_Reg1_2_Reg1_1, { MCK_larl, MCK_GR32, MCK_GR32 } },
- { X86::LAR32rm, Convert_Reg1_2_Mem5_1, { MCK_larl, MCK_Mem, MCK_GR32 } },
- { X86::LAR64rr, Convert_Reg1_2_Reg1_1, { MCK_larq, MCK_GR32, MCK_GR64 } },
- { X86::LAR64rm, Convert_Reg1_2_Mem5_1, { MCK_larq, MCK_Mem, MCK_GR64 } },
- { X86::LAR16rr, Convert_Reg1_2_Reg1_1, { MCK_larw, MCK_GR16, MCK_GR16 } },
- { X86::LAR16rm, Convert_Reg1_2_Mem5_1, { MCK_larw, MCK_Mem, MCK_GR16 } },
- { X86::FARCALL32m, Convert_Mem5_2, { MCK_lcalll, MCK__STAR_, MCK_Mem } },
- { X86::FARCALL32i, Convert_Imm1_1_Imm1_2, { MCK_lcalll, MCK_Imm, MCK_Imm } },
- { X86::FARCALL64, Convert_Mem5_2, { MCK_lcallq, MCK__STAR_, MCK_Mem } },
- { X86::FARCALL16m, Convert_Mem5_2, { MCK_lcallw, MCK__STAR_, MCK_Mem } },
- { X86::FARCALL16i, Convert_Imm1_1_Imm1_2, { MCK_lcallw, MCK_Imm, MCK_Imm } },
- { X86::LDDQUrm, Convert_Reg1_2_Mem5_1, { MCK_lddqu, MCK_Mem, MCK_FR32 } },
- { X86::LDS32rm, Convert_Reg1_2_Mem5_1, { MCK_ldsl, MCK_Mem, MCK_GR32 } },
- { X86::LDS16rm, Convert_Reg1_2_Mem5_1, { MCK_ldsw, MCK_Mem, MCK_GR16 } },
- { X86::LEA32r, Convert_Reg1_2_Mem4_1, { MCK_leal, MCK_Mem, MCK_GR32 } },
- { X86::LEA64_32r, Convert_Reg1_2_Mem4_1, { MCK_leal, MCK_Mem, MCK_GR32 } },
- { X86::LEA64r, Convert_Reg1_2_Mem4_1, { MCK_leaq, MCK_Mem, MCK_GR64 } },
- { X86::LEA16r, Convert_Reg1_2_Mem4_1, { MCK_leaw, MCK_Mem, MCK_GR16 } },
- { X86::LES32rm, Convert_Reg1_2_Mem5_1, { MCK_lesl, MCK_Mem, MCK_GR32 } },
- { X86::LES16rm, Convert_Reg1_2_Mem5_1, { MCK_lesw, MCK_Mem, MCK_GR16 } },
- { X86::LFS32rm, Convert_Reg1_2_Mem5_1, { MCK_lfsl, MCK_Mem, MCK_GR32 } },
- { X86::LFS64rm, Convert_Reg1_2_Mem5_1, { MCK_lfsq, MCK_Mem, MCK_GR64 } },
- { X86::LFS16rm, Convert_Reg1_2_Mem5_1, { MCK_lfsw, MCK_Mem, MCK_GR16 } },
- { X86::LGS32rm, Convert_Reg1_2_Mem5_1, { MCK_lgsl, MCK_Mem, MCK_GR32 } },
- { X86::LGS64rm, Convert_Reg1_2_Mem5_1, { MCK_lgsq, MCK_Mem, MCK_GR64 } },
- { X86::LGS16rm, Convert_Reg1_2_Mem5_1, { MCK_lgsw, MCK_Mem, MCK_GR16 } },
- { X86::FARJMP32m, Convert_Mem5_2, { MCK_ljmpl, MCK__STAR_, MCK_Mem } },
- { X86::FARJMP32i, Convert_Imm1_1_Imm1_2, { MCK_ljmpl, MCK_Imm, MCK_Imm } },
- { X86::FARJMP64, Convert_Mem5_2, { MCK_ljmpq, MCK__STAR_, MCK_Mem } },
- { X86::FARJMP16m, Convert_Mem5_2, { MCK_ljmpw, MCK__STAR_, MCK_Mem } },
- { X86::FARJMP16i, Convert_Imm1_1_Imm1_2, { MCK_ljmpw, MCK_Imm, MCK_Imm } },
- { X86::LSL32rr, Convert_Reg1_2_Reg1_1, { MCK_lsll, MCK_GR32, MCK_GR32 } },
- { X86::LSL32rm, Convert_Reg1_2_Mem5_1, { MCK_lsll, MCK_Mem, MCK_GR32 } },
- { X86::LSL64rr, Convert_Reg1_2_Reg1_1, { MCK_lslq, MCK_GR64, MCK_GR64 } },
- { X86::LSL64rm, Convert_Reg1_2_Mem5_1, { MCK_lslq, MCK_Mem, MCK_GR64 } },
- { X86::LSL16rr, Convert_Reg1_2_Reg1_1, { MCK_lslw, MCK_GR16, MCK_GR16 } },
- { X86::LSL16rm, Convert_Reg1_2_Mem5_1, { MCK_lslw, MCK_Mem, MCK_GR16 } },
- { X86::LSS32rm, Convert_Reg1_2_Mem5_1, { MCK_lssl, MCK_Mem, MCK_GR32 } },
- { X86::LSS64rm, Convert_Reg1_2_Mem5_1, { MCK_lssq, MCK_Mem, MCK_GR64 } },
- { X86::LSS16rm, Convert_Reg1_2_Mem5_1, { MCK_lssw, MCK_Mem, MCK_GR16 } },
- { X86::MASKMOVDQU, Convert_Reg1_2_Reg1_1, { MCK_maskmovdqu, MCK_FR32, MCK_FR32 } },
- { X86::MASKMOVDQU64, Convert_Reg1_2_Reg1_1, { MCK_maskmovdqu, MCK_FR32, MCK_FR32 } },
- { X86::MMX_MASKMOVQ, Convert_Reg1_2_Reg1_1, { MCK_maskmovq, MCK_VR64, MCK_VR64 } },
- { X86::MMX_MASKMOVQ64, Convert_Reg1_2_Reg1_1, { MCK_maskmovq, MCK_VR64, MCK_VR64 } },
- { X86::MAXPDrr, Convert_Reg1_2_ImpReg1_1, { MCK_maxpd, MCK_FR32, MCK_FR32 } },
- { X86::MAXPDrm, Convert_Reg1_2_ImpMem5_1, { MCK_maxpd, MCK_Mem, MCK_FR32 } },
- { X86::MAXPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_maxps, MCK_FR32, MCK_FR32 } },
- { X86::MAXPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_maxps, MCK_Mem, MCK_FR32 } },
- { X86::MAXSDrr, Convert_Reg1_2_ImpReg1_1, { MCK_maxsd, MCK_FR32, MCK_FR32 } },
- { X86::MAXSDrm, Convert_Reg1_2_ImpMem5_1, { MCK_maxsd, MCK_Mem, MCK_FR32 } },
- { X86::MAXSSrr, Convert_Reg1_2_ImpReg1_1, { MCK_maxss, MCK_FR32, MCK_FR32 } },
- { X86::MAXSSrm, Convert_Reg1_2_ImpMem5_1, { MCK_maxss, MCK_Mem, MCK_FR32 } },
- { X86::MINPDrr, Convert_Reg1_2_ImpReg1_1, { MCK_minpd, MCK_FR32, MCK_FR32 } },
- { X86::MINPDrm, Convert_Reg1_2_ImpMem5_1, { MCK_minpd, MCK_Mem, MCK_FR32 } },
- { X86::MINPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_minps, MCK_FR32, MCK_FR32 } },
- { X86::MINPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_minps, MCK_Mem, MCK_FR32 } },
- { X86::MINSDrr, Convert_Reg1_2_ImpReg1_1, { MCK_minsd, MCK_FR32, MCK_FR32 } },
- { X86::MINSDrm, Convert_Reg1_2_ImpMem5_1, { MCK_minsd, MCK_Mem, MCK_FR32 } },
- { X86::MINSSrr, Convert_Reg1_2_ImpReg1_1, { MCK_minss, MCK_FR32, MCK_FR32 } },
- { X86::MINSSrm, Convert_Reg1_2_ImpMem5_1, { MCK_minss, MCK_Mem, MCK_FR32 } },
- { X86::MOV64ri, Convert_Reg1_2_Imm1_1, { MCK_movabsq, MCK_Imm, MCK_GR64 } },
- { X86::FsMOVAPDrr, Convert_Reg1_2_Reg1_1, { MCK_movapd, MCK_FR32, MCK_FR32 } },
- { X86::MOVAPDrr, Convert_Reg1_2_Reg1_1, { MCK_movapd, MCK_FR32, MCK_FR32 } },
- { X86::MOVAPDmr, Convert_Mem5_2_Reg1_1, { MCK_movapd, MCK_FR32, MCK_Mem } },
- { X86::FsMOVAPDrm, Convert_Reg1_2_Mem5_1, { MCK_movapd, MCK_Mem, MCK_FR32 } },
- { X86::MOVAPDrm, Convert_Reg1_2_Mem5_1, { MCK_movapd, MCK_Mem, MCK_FR32 } },
- { X86::MOVAPSrr, Convert_Reg1_2_Reg1_1, { MCK_movaps, MCK_FR32, MCK_FR32 } },
- { X86::FsMOVAPSrr, Convert_Reg1_2_Reg1_1, { MCK_movaps, MCK_FR32, MCK_FR32 } },
- { X86::MOVAPSmr, Convert_Mem5_2_Reg1_1, { MCK_movaps, MCK_FR32, MCK_Mem } },
- { X86::MOVAPSrm, Convert_Reg1_2_Mem5_1, { MCK_movaps, MCK_Mem, MCK_FR32 } },
- { X86::FsMOVAPSrm, Convert_Reg1_2_Mem5_1, { MCK_movaps, MCK_Mem, MCK_FR32 } },
- { X86::MOV8ao8, Convert_Imm1_2, { MCK_movb, MCK_AL, MCK_Imm } },
- { X86::MOV8rr_NOREX, Convert_Reg1_2_Reg1_1, { MCK_movb, MCK_GR8_NOREX, MCK_GR8_NOREX } },
- { X86::MOV8mr_NOREX, Convert_Mem5_2_Reg1_1, { MCK_movb, MCK_GR8_NOREX, MCK_Mem } },
- { X86::MOV8rr, Convert_Reg1_2_Reg1_1, { MCK_movb, MCK_GR8, MCK_GR8 } },
- { X86::MOV8rr_REV, Convert_Reg1_2_Reg1_1, { MCK_movb, MCK_GR8, MCK_GR8 } },
- { X86::MOV8mr, Convert_Mem5_2_Reg1_1, { MCK_movb, MCK_GR8, MCK_Mem } },
- { X86::MOV8o8a, Convert_Imm1_1, { MCK_movb, MCK_Imm, MCK_AL } },
- { X86::MOV8ri, Convert_Reg1_2_Imm1_1, { MCK_movb, MCK_Imm, MCK_GR8 } },
- { X86::MOV8mi, Convert_Mem5_2_Imm1_1, { MCK_movb, MCK_Imm, MCK_Mem } },
- { X86::MOV8rm_NOREX, Convert_Reg1_2_Mem5_1, { MCK_movb, MCK_Mem, MCK_GR8_NOREX } },
- { X86::MOV8rm, Convert_Reg1_2_Mem5_1, { MCK_movb, MCK_Mem, MCK_GR8 } },
- { X86::MMX_MOVZDI2PDIrr, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_GR32, MCK_VR64 } },
- { X86::MMX_MOVD64rr, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_GR32, MCK_VR64 } },
- { X86::MOVDI2SSrr, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_GR32, MCK_FR32 } },
- { X86::MOVDI2PDIrr, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_GR32, MCK_FR32 } },
- { X86::MOVZDI2PDIrr, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_GR32, MCK_FR32 } },
- { X86::MMX_MOVD64to64rr, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_GR64, MCK_VR64 } },
- { X86::MMX_MOVD64rrv164, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_GR64, MCK_VR64 } },
- { X86::MOV64toPQIrr, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_GR64, MCK_FR32 } },
- { X86::MOVZQI2PQIrr, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_GR64, MCK_FR32 } },
- { X86::MOV64toSDrr, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_GR64, MCK_FR32 } },
- { X86::MMX_MOVD64grr, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_VR64, MCK_GR32 } },
- { X86::MMX_MOVD64from64rr, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_VR64, MCK_GR64 } },
- { X86::MMX_MOVD64mr, Convert_Mem5_2_Reg1_1, { MCK_movd, MCK_VR64, MCK_Mem } },
- { X86::MOVSS2DIrr, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_FR32, MCK_GR32 } },
- { X86::MOVPDI2DIrr, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_FR32, MCK_GR32 } },
- { X86::MOVPQIto64rr, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_FR32, MCK_GR64 } },
- { X86::MOVSDto64rr, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_FR32, MCK_GR64 } },
- { X86::MOVSS2DImr, Convert_Mem5_2_Reg1_1, { MCK_movd, MCK_FR32, MCK_Mem } },
- { X86::MOVPDI2DImr, Convert_Mem5_2_Reg1_1, { MCK_movd, MCK_FR32, MCK_Mem } },
- { X86::MMX_MOVZDI2PDIrm, Convert_Reg1_2_Mem5_1, { MCK_movd, MCK_Mem, MCK_VR64 } },
- { X86::MMX_MOVD64rm, Convert_Reg1_2_Mem5_1, { MCK_movd, MCK_Mem, MCK_VR64 } },
- { X86::MOVZDI2PDIrm, Convert_Reg1_2_Mem5_1, { MCK_movd, MCK_Mem, MCK_FR32 } },
- { X86::MOVDI2PDIrm, Convert_Reg1_2_Mem5_1, { MCK_movd, MCK_Mem, MCK_FR32 } },
- { X86::MOVDI2SSrm, Convert_Reg1_2_Mem5_1, { MCK_movd, MCK_Mem, MCK_FR32 } },
- { X86::MOVDDUPrr, Convert_Reg1_2_Reg1_1, { MCK_movddup, MCK_FR32, MCK_FR32 } },
- { X86::MOVDDUPrm, Convert_Reg1_2_Mem5_1, { MCK_movddup, MCK_Mem, MCK_FR32 } },
- { X86::MMX_MOVDQ2Qrr, Convert_Reg1_2_Reg1_1, { MCK_movdq2q, MCK_FR32, MCK_VR64 } },
- { X86::MOVDQArr, Convert_Reg1_2_Reg1_1, { MCK_movdqa, MCK_FR32, MCK_FR32 } },
- { X86::MOVDQAmr, Convert_Mem5_2_Reg1_1, { MCK_movdqa, MCK_FR32, MCK_Mem } },
- { X86::MOVDQArm, Convert_Reg1_2_Mem5_1, { MCK_movdqa, MCK_Mem, MCK_FR32 } },
- { X86::MOVDQUmr, Convert_Mem5_2_Reg1_1, { MCK_movdqu, MCK_FR32, MCK_Mem } },
- { X86::MOVDQUrm, Convert_Reg1_2_Mem5_1, { MCK_movdqu, MCK_Mem, MCK_FR32 } },
- { X86::MOVHLPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_movhlps, MCK_FR32, MCK_FR32 } },
- { X86::MOVHPDmr, Convert_Mem5_2_Reg1_1, { MCK_movhpd, MCK_FR32, MCK_Mem } },
- { X86::MOVHPDrm, Convert_Reg1_2_ImpMem5_1, { MCK_movhpd, MCK_Mem, MCK_FR32 } },
- { X86::MOVHPSmr, Convert_Mem5_2_Reg1_1, { MCK_movhps, MCK_FR32, MCK_Mem } },
- { X86::MOVHPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_movhps, MCK_Mem, MCK_FR32 } },
- { X86::MOV32ao32, Convert_Imm1_2, { MCK_movl, MCK_EAX, MCK_Imm } },
- { X86::MOV32rr, Convert_Reg1_2_Reg1_1, { MCK_movl, MCK_GR32, MCK_GR32 } },
- { X86::MOV32rr_REV, Convert_Reg1_2_Reg1_1, { MCK_movl, MCK_GR32, MCK_GR32 } },
- { X86::MOV32dr, Convert_Reg1_2_Reg1_1, { MCK_movl, MCK_GR32, MCK_DEBUG_REG } },
- { X86::MOV32mr, Convert_Mem5_2_Reg1_1, { MCK_movl, MCK_GR32, MCK_Mem } },
- { X86::MOV32rd, Convert_Reg1_2_Reg1_1, { MCK_movl, MCK_DEBUG_REG, MCK_GR32 } },
- { X86::MOV32o32a, Convert_Imm1_1, { MCK_movl, MCK_Imm, MCK_EAX } },
- { X86::MOV32ri, Convert_Reg1_2_Imm1_1, { MCK_movl, MCK_Imm, MCK_GR32 } },
- { X86::MOV32mi, Convert_Mem5_2_Imm1_1, { MCK_movl, MCK_Imm, MCK_Mem } },
- { X86::MOV32rm, Convert_Reg1_2_Mem5_1, { MCK_movl, MCK_Mem, MCK_GR32 } },
- { X86::MOVLHPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_movlhps, MCK_FR32, MCK_FR32 } },
- { X86::MOVLPDmr, Convert_Mem5_2_Reg1_1, { MCK_movlpd, MCK_FR32, MCK_Mem } },
- { X86::MOVLPDrm, Convert_Reg1_2_ImpMem5_1, { MCK_movlpd, MCK_Mem, MCK_FR32 } },
- { X86::MOVLPSmr, Convert_Mem5_2_Reg1_1, { MCK_movlps, MCK_FR32, MCK_Mem } },
- { X86::MOVLPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_movlps, MCK_Mem, MCK_FR32 } },
- { X86::MOVMSKPDrr, Convert_Reg1_2_Reg1_1, { MCK_movmskpd, MCK_FR32, MCK_GR32 } },
- { X86::MOVMSKPSrr, Convert_Reg1_2_Reg1_1, { MCK_movmskps, MCK_FR32, MCK_GR32 } },
- { X86::MOVNTDQmr, Convert_Mem5_2_Reg1_1, { MCK_movntdq, MCK_FR32, MCK_Mem } },
- { X86::MOVNTDQArm, Convert_Reg1_2_Mem5_1, { MCK_movntdqa, MCK_Mem, MCK_FR32 } },
- { X86::MOVNTImr, Convert_Mem5_2_Reg1_1, { MCK_movnti, MCK_GR32, MCK_Mem } },
- { X86::MOVNTPDmr, Convert_Mem5_2_Reg1_1, { MCK_movntpd, MCK_FR32, MCK_Mem } },
- { X86::MOVNTPSmr, Convert_Mem5_2_Reg1_1, { MCK_movntps, MCK_FR32, MCK_Mem } },
- { X86::MMX_MOVNTQmr, Convert_Mem5_2_Reg1_1, { MCK_movntq, MCK_VR64, MCK_Mem } },
- { X86::MOV32cr, Convert_Reg1_2_Reg1_1, { MCK_movq, MCK_GR32, MCK_CONTROL_REG_32 } },
- { X86::MOV64ao64, Convert_Imm1_2, { MCK_movq, MCK_RAX, MCK_Imm } },
- { X86::MOV64ao8, Convert_Imm1_2, { MCK_movq, MCK_RAX, MCK_Imm } },
- { X86::MOV64rr, Convert_Reg1_2_Reg1_1, { MCK_movq, MCK_GR64, MCK_GR64 } },
- { X86::MOV64rr_REV, Convert_Reg1_2_Reg1_1, { MCK_movq, MCK_GR64, MCK_GR64 } },
- { X86::MOV64sr, Convert_Reg1_2_Reg1_1, { MCK_movq, MCK_GR64, MCK_SEGMENT_REG } },
- { X86::MOV64dr, Convert_Reg1_2_Reg1_1, { MCK_movq, MCK_GR64, MCK_DEBUG_REG } },
- { X86::MOV64cr, Convert_Reg1_2_Reg1_1, { MCK_movq, MCK_GR64, MCK_CONTROL_REG_64 } },
- { X86::MOV64mr, Convert_Mem5_2_Reg1_1, { MCK_movq, MCK_GR64, MCK_Mem } },
- { X86::MMX_MOVQ64rr, Convert_Reg1_2_Reg1_1, { MCK_movq, MCK_VR64, MCK_VR64 } },
- { X86::MMX_MOVQ64mr, Convert_Mem5_2_Reg1_1, { MCK_movq, MCK_VR64, MCK_Mem } },
- { X86::MMX_MOVQ64gmr, Convert_Mem5_2_Reg1_1, { MCK_movq, MCK_VR64, MCK_Mem } },
- { X86::MOVQxrxr, Convert_Reg1_2_Reg1_1, { MCK_movq, MCK_FR32, MCK_FR32 } },
- { X86::MOVZPQILo2PQIrr, Convert_Reg1_2_Reg1_1, { MCK_movq, MCK_FR32, MCK_FR32 } },
- { X86::MOVSDto64mr, Convert_Mem5_2_Reg1_1, { MCK_movq, MCK_FR32, MCK_Mem } },
- { X86::MOVPQI2QImr, Convert_Mem5_2_Reg1_1, { MCK_movq, MCK_FR32, MCK_Mem } },
- { X86::MOVLQ128mr, Convert_Mem5_2_Reg1_1, { MCK_movq, MCK_FR32, MCK_Mem } },
- { X86::MOV64rs, Convert_Reg1_2_Reg1_1, { MCK_movq, MCK_SEGMENT_REG, MCK_GR64 } },
- { X86::MOV64ms, Convert_Mem5_2_Reg1_1, { MCK_movq, MCK_SEGMENT_REG, MCK_Mem } },
- { X86::MOV64rd, Convert_Reg1_2_Reg1_1, { MCK_movq, MCK_DEBUG_REG, MCK_GR64 } },
- { X86::MOV32rc, Convert_Reg1_2_Reg1_1, { MCK_movq, MCK_CONTROL_REG_32, MCK_GR32 } },
- { X86::MOV64rc, Convert_Reg1_2_Reg1_1, { MCK_movq, MCK_CONTROL_REG_64, MCK_GR64 } },
- { X86::MOV64o8a, Convert_Imm1_1, { MCK_movq, MCK_Imm, MCK_RAX } },
- { X86::MOV64o64a, Convert_Imm1_1, { MCK_movq, MCK_Imm, MCK_RAX } },
- { X86::MOV64ri32, Convert_Reg1_2_Imm1_1, { MCK_movq, MCK_Imm, MCK_GR64 } },
- { X86::MOV64mi32, Convert_Mem5_2_Imm1_1, { MCK_movq, MCK_Imm, MCK_Mem } },
- { X86::MOV64rm, Convert_Reg1_2_Mem5_1, { MCK_movq, MCK_Mem, MCK_GR64 } },
- { X86::MMX_MOVQ64rm, Convert_Reg1_2_Mem5_1, { MCK_movq, MCK_Mem, MCK_VR64 } },
- { X86::MOVQI2PQIrm, Convert_Reg1_2_Mem5_1, { MCK_movq, MCK_Mem, MCK_FR32 } },
- { X86::MOVZPQILo2PQIrm, Convert_Reg1_2_Mem5_1, { MCK_movq, MCK_Mem, MCK_FR32 } },
- { X86::MOVZQI2PQIrm, Convert_Reg1_2_Mem5_1, { MCK_movq, MCK_Mem, MCK_FR32 } },
- { X86::MOV64toSDrm, Convert_Reg1_2_Mem5_1, { MCK_movq, MCK_Mem, MCK_FR32 } },
- { X86::MOV64sm, Convert_Reg1_2_Mem5_1, { MCK_movq, MCK_Mem, MCK_SEGMENT_REG } },
- { X86::MMX_MOVQ2DQrr, Convert_Reg1_2_Reg1_1, { MCK_movq2dq, MCK_VR64, MCK_FR32 } },
- { X86::MMX_MOVQ2FR64rr, Convert_Reg1_2_Reg1_1, { MCK_movq2dq, MCK_VR64, MCK_FR32 } },
- { X86::MOVSX32rr8, Convert_Reg1_2_Reg1_1, { MCK_movsbl, MCK_GR8, MCK_GR32 } },
- { X86::MOVSX32rm8, Convert_Reg1_2_Mem5_1, { MCK_movsbl, MCK_Mem, MCK_GR32 } },
- { X86::MOVSX64rr8, Convert_Reg1_2_Reg1_1, { MCK_movsbq, MCK_GR8, MCK_GR64 } },
- { X86::MOVSX64rm8, Convert_Reg1_2_Mem5_1, { MCK_movsbq, MCK_Mem, MCK_GR64 } },
- { X86::MOVSX16rr8W, Convert_Reg1_2_Reg1_1, { MCK_movsbw, MCK_GR8, MCK_GR16 } },
- { X86::MOVSX16rm8W, Convert_Reg1_2_Mem5_1, { MCK_movsbw, MCK_Mem, MCK_GR16 } },
- { X86::MOVSDrr, Convert_Reg1_2_Reg1_1, { MCK_movsd, MCK_FR32, MCK_FR32 } },
- { X86::MOVLSD2PDrr, Convert_Reg1_2_ImpReg1_1, { MCK_movsd, MCK_FR32, MCK_FR32 } },
- { X86::MOVPD2SDrr, Convert_Reg1_2_Reg1_1, { MCK_movsd, MCK_FR32, MCK_FR32 } },
- { X86::MOVLPDrr, Convert_Reg1_2_ImpReg1_1, { MCK_movsd, MCK_FR32, MCK_FR32 } },
- { X86::MOVSD2PDrr, Convert_Reg1_2_Reg1_1, { MCK_movsd, MCK_FR32, MCK_FR32 } },
- { X86::MOVSDmr, Convert_Mem5_2_Reg1_1, { MCK_movsd, MCK_FR32, MCK_Mem } },
- { X86::MOVPD2SDmr, Convert_Mem5_2_Reg1_1, { MCK_movsd, MCK_FR32, MCK_Mem } },
- { X86::MOVSD2PDrm, Convert_Reg1_2_Mem5_1, { MCK_movsd, MCK_Mem, MCK_FR32 } },
- { X86::MOVZSD2PDrm, Convert_Reg1_2_Mem5_1, { MCK_movsd, MCK_Mem, MCK_FR32 } },
- { X86::MOVSDrm, Convert_Reg1_2_Mem5_1, { MCK_movsd, MCK_Mem, MCK_FR32 } },
- { X86::MOVSHDUPrr, Convert_Reg1_2_Reg1_1, { MCK_movshdup, MCK_FR32, MCK_FR32 } },
- { X86::MOVSHDUPrm, Convert_Reg1_2_Mem5_1, { MCK_movshdup, MCK_Mem, MCK_FR32 } },
- { X86::MOVSLDUPrr, Convert_Reg1_2_Reg1_1, { MCK_movsldup, MCK_FR32, MCK_FR32 } },
- { X86::MOVSLDUPrm, Convert_Reg1_2_Mem5_1, { MCK_movsldup, MCK_Mem, MCK_FR32 } },
- { X86::MOVSX64rr32, Convert_Reg1_2_Reg1_1, { MCK_movslq, MCK_GR32, MCK_GR64 } },
- { X86::MOVSX64rm32, Convert_Reg1_2_Mem5_1, { MCK_movslq, MCK_Mem, MCK_GR64 } },
- { X86::MOVPS2SSrr, Convert_Reg1_2_Reg1_1, { MCK_movss, MCK_FR32, MCK_FR32 } },
- { X86::MOVSS2PSrr, Convert_Reg1_2_Reg1_1, { MCK_movss, MCK_FR32, MCK_FR32 } },
- { X86::MOVSSrr, Convert_Reg1_2_Reg1_1, { MCK_movss, MCK_FR32, MCK_FR32 } },
- { X86::MOVLSS2PSrr, Convert_Reg1_2_ImpReg1_1, { MCK_movss, MCK_FR32, MCK_FR32 } },
- { X86::MOVLPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_movss, MCK_FR32, MCK_FR32 } },
- { X86::MOVPS2SSmr, Convert_Mem5_2_Reg1_1, { MCK_movss, MCK_FR32, MCK_Mem } },
- { X86::MOVSSmr, Convert_Mem5_2_Reg1_1, { MCK_movss, MCK_FR32, MCK_Mem } },
- { X86::MOVSS2PSrm, Convert_Reg1_2_Mem5_1, { MCK_movss, MCK_Mem, MCK_FR32 } },
- { X86::MOVSSrm, Convert_Reg1_2_Mem5_1, { MCK_movss, MCK_Mem, MCK_FR32 } },
- { X86::MOVZSS2PSrm, Convert_Reg1_2_Mem5_1, { MCK_movss, MCK_Mem, MCK_FR32 } },
- { X86::MOVSX32rr16, Convert_Reg1_2_Reg1_1, { MCK_movswl, MCK_GR16, MCK_GR32 } },
- { X86::MOVSX32rm16, Convert_Reg1_2_Mem5_1, { MCK_movswl, MCK_Mem, MCK_GR32 } },
- { X86::MOVSX64rr16, Convert_Reg1_2_Reg1_1, { MCK_movswq, MCK_GR16, MCK_GR64 } },
- { X86::MOVSX64rm16, Convert_Reg1_2_Mem5_1, { MCK_movswq, MCK_Mem, MCK_GR64 } },
- { X86::MOVUPDrr, Convert_Reg1_2_Reg1_1, { MCK_movupd, MCK_FR32, MCK_FR32 } },
- { X86::MOVUPDmr, Convert_Mem5_2_Reg1_1, { MCK_movupd, MCK_FR32, MCK_Mem } },
- { X86::MOVUPDrm, Convert_Reg1_2_Mem5_1, { MCK_movupd, MCK_Mem, MCK_FR32 } },
- { X86::MOVUPSrr, Convert_Reg1_2_Reg1_1, { MCK_movups, MCK_FR32, MCK_FR32 } },
- { X86::MOVUPSmr, Convert_Mem5_2_Reg1_1, { MCK_movups, MCK_FR32, MCK_Mem } },
- { X86::MOVUPSrm, Convert_Reg1_2_Mem5_1, { MCK_movups, MCK_Mem, MCK_FR32 } },
- { X86::MOV16ao16, Convert_Imm1_2, { MCK_movw, MCK_AX, MCK_Imm } },
- { X86::MOV16rr, Convert_Reg1_2_Reg1_1, { MCK_movw, MCK_GR16, MCK_GR16 } },
- { X86::MOV16rr_REV, Convert_Reg1_2_Reg1_1, { MCK_movw, MCK_GR16, MCK_GR16 } },
- { X86::MOV16sr, Convert_Reg1_2_Reg1_1, { MCK_movw, MCK_GR16, MCK_SEGMENT_REG } },
- { X86::MOV16mr, Convert_Mem5_2_Reg1_1, { MCK_movw, MCK_GR16, MCK_Mem } },
- { X86::MOV16rs, Convert_Reg1_2_Reg1_1, { MCK_movw, MCK_SEGMENT_REG, MCK_GR16 } },
- { X86::MOV16ms, Convert_Mem5_2_Reg1_1, { MCK_movw, MCK_SEGMENT_REG, MCK_Mem } },
- { X86::MOV16o16a, Convert_Imm1_1, { MCK_movw, MCK_Imm, MCK_AX } },
- { X86::MOV16ri, Convert_Reg1_2_Imm1_1, { MCK_movw, MCK_Imm, MCK_GR16 } },
- { X86::MOV16mi, Convert_Mem5_2_Imm1_1, { MCK_movw, MCK_Imm, MCK_Mem } },
- { X86::MOV16rm, Convert_Reg1_2_Mem5_1, { MCK_movw, MCK_Mem, MCK_GR16 } },
- { X86::MOV16sm, Convert_Reg1_2_Mem5_1, { MCK_movw, MCK_Mem, MCK_SEGMENT_REG } },
- { X86::MOVZX32_NOREXrr8, Convert_Reg1_2_Reg1_1, { MCK_movzbl, MCK_GR8, MCK_GR32_NOREX } },
- { X86::MOVZX32rr8, Convert_Reg1_2_Reg1_1, { MCK_movzbl, MCK_GR8, MCK_GR32 } },
- { X86::MOVZX32_NOREXrm8, Convert_Reg1_2_Mem5_1, { MCK_movzbl, MCK_Mem, MCK_GR32_NOREX } },
- { X86::MOVZX32rm8, Convert_Reg1_2_Mem5_1, { MCK_movzbl, MCK_Mem, MCK_GR32 } },
- { X86::MOVZX64rr8_Q, Convert_Reg1_2_Reg1_1, { MCK_movzbq, MCK_GR8, MCK_GR64 } },
- { X86::MOVZX64rm8_Q, Convert_Reg1_2_Mem5_1, { MCK_movzbq, MCK_Mem, MCK_GR64 } },
- { X86::MOVZX16rr8W, Convert_Reg1_2_Reg1_1, { MCK_movzbw, MCK_GR8, MCK_GR16 } },
- { X86::MOVZX16rm8W, Convert_Reg1_2_Mem5_1, { MCK_movzbw, MCK_Mem, MCK_GR16 } },
- { X86::MOVZX32rr16, Convert_Reg1_2_Reg1_1, { MCK_movzwl, MCK_GR16, MCK_GR32 } },
- { X86::MOVZX32rm16, Convert_Reg1_2_Mem5_1, { MCK_movzwl, MCK_Mem, MCK_GR32 } },
- { X86::MOVZX64rr16_Q, Convert_Reg1_2_Reg1_1, { MCK_movzwq, MCK_GR16, MCK_GR64 } },
- { X86::MOVZX64rm16_Q, Convert_Reg1_2_Mem5_1, { MCK_movzwq, MCK_Mem, MCK_GR64 } },
- { X86::MULPDrr, Convert_Reg1_2_ImpReg1_1, { MCK_mulpd, MCK_FR32, MCK_FR32 } },
- { X86::MULPDrm, Convert_Reg1_2_ImpMem5_1, { MCK_mulpd, MCK_Mem, MCK_FR32 } },
- { X86::MULPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_mulps, MCK_FR32, MCK_FR32 } },
- { X86::MULPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_mulps, MCK_Mem, MCK_FR32 } },
- { X86::MULSDrr, Convert_Reg1_2_ImpReg1_1, { MCK_mulsd, MCK_FR32, MCK_FR32 } },
- { X86::MULSDrm, Convert_Reg1_2_ImpMem5_1, { MCK_mulsd, MCK_Mem, MCK_FR32 } },
- { X86::MULSSrr, Convert_Reg1_2_ImpReg1_1, { MCK_mulss, MCK_FR32, MCK_FR32 } },
- { X86::MULSSrm, Convert_Reg1_2_ImpMem5_1, { MCK_mulss, MCK_Mem, MCK_FR32 } },
- { X86::OR8rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_orb, MCK_GR8, MCK_GR8 } },
- { X86::OR8rr, Convert_Reg1_2_ImpReg1_1, { MCK_orb, MCK_GR8, MCK_GR8 } },
- { X86::OR8mr, Convert_Mem5_2_Reg1_1, { MCK_orb, MCK_GR8, MCK_Mem } },
- { X86::OR8i8, Convert_Imm1_1, { MCK_orb, MCK_Imm, MCK_AL } },
- { X86::OR8ri, Convert_Reg1_2_ImpImm1_1, { MCK_orb, MCK_Imm, MCK_GR8 } },
- { X86::OR8mi, Convert_Mem5_2_Imm1_1, { MCK_orb, MCK_Imm, MCK_Mem } },
- { X86::OR8rm, Convert_Reg1_2_ImpMem5_1, { MCK_orb, MCK_Mem, MCK_GR8 } },
- { X86::OR32rr, Convert_Reg1_2_ImpReg1_1, { MCK_orl, MCK_GR32, MCK_GR32 } },
- { X86::OR32rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_orl, MCK_GR32, MCK_GR32 } },
- { X86::OR32mr, Convert_Mem5_2_Reg1_1, { MCK_orl, MCK_GR32, MCK_Mem } },
- { X86::OR32ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_orl, MCK_ImmSExt8, MCK_GR32 } },
- { X86::OR32mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_orl, MCK_ImmSExt8, MCK_Mem } },
- { X86::OR32i32, Convert_Imm1_1, { MCK_orl, MCK_Imm, MCK_EAX } },
- { X86::OR32ri, Convert_Reg1_2_ImpImm1_1, { MCK_orl, MCK_Imm, MCK_GR32 } },
- { X86::OR32mi, Convert_Mem5_2_Imm1_1, { MCK_orl, MCK_Imm, MCK_Mem } },
- { X86::OR32rm, Convert_Reg1_2_ImpMem5_1, { MCK_orl, MCK_Mem, MCK_GR32 } },
- { X86::ORPDrr, Convert_Reg1_2_ImpReg1_1, { MCK_orpd, MCK_FR32, MCK_FR32 } },
- { X86::FsORPDrr, Convert_Reg1_2_ImpReg1_1, { MCK_orpd, MCK_FR32, MCK_FR32 } },
- { X86::ORPDrm, Convert_Reg1_2_ImpMem5_1, { MCK_orpd, MCK_Mem, MCK_FR32 } },
- { X86::FsORPDrm, Convert_Reg1_2_ImpMem5_1, { MCK_orpd, MCK_Mem, MCK_FR32 } },
- { X86::FsORPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_orps, MCK_FR32, MCK_FR32 } },
- { X86::ORPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_orps, MCK_FR32, MCK_FR32 } },
- { X86::FsORPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_orps, MCK_Mem, MCK_FR32 } },
- { X86::ORPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_orps, MCK_Mem, MCK_FR32 } },
- { X86::OR64rr, Convert_Reg1_2_ImpReg1_1, { MCK_orq, MCK_GR64, MCK_GR64 } },
- { X86::OR64rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_orq, MCK_GR64, MCK_GR64 } },
- { X86::OR64mr, Convert_Mem5_2_Reg1_1, { MCK_orq, MCK_GR64, MCK_Mem } },
- { X86::OR64ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_orq, MCK_ImmSExt8, MCK_GR64 } },
- { X86::OR64mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_orq, MCK_ImmSExt8, MCK_Mem } },
- { X86::OR64i32, Convert_Imm1_1, { MCK_orq, MCK_Imm, MCK_RAX } },
- { X86::OR64ri32, Convert_Reg1_2_ImpImm1_1, { MCK_orq, MCK_Imm, MCK_GR64 } },
- { X86::OR64mi32, Convert_Mem5_2_Imm1_1, { MCK_orq, MCK_Imm, MCK_Mem } },
- { X86::OR64rm, Convert_Reg1_2_ImpMem5_1, { MCK_orq, MCK_Mem, MCK_GR64 } },
- { X86::OR16rr, Convert_Reg1_2_ImpReg1_1, { MCK_orw, MCK_GR16, MCK_GR16 } },
- { X86::OR16rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_orw, MCK_GR16, MCK_GR16 } },
- { X86::OR16mr, Convert_Mem5_2_Reg1_1, { MCK_orw, MCK_GR16, MCK_Mem } },
- { X86::OR16ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_orw, MCK_ImmSExt8, MCK_GR16 } },
- { X86::OR16mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_orw, MCK_ImmSExt8, MCK_Mem } },
- { X86::OR16i16, Convert_Imm1_1, { MCK_orw, MCK_Imm, MCK_AX } },
- { X86::OR16ri, Convert_Reg1_2_ImpImm1_1, { MCK_orw, MCK_Imm, MCK_GR16 } },
- { X86::OR16mi, Convert_Mem5_2_Imm1_1, { MCK_orw, MCK_Imm, MCK_Mem } },
- { X86::OR16rm, Convert_Reg1_2_ImpMem5_1, { MCK_orw, MCK_Mem, MCK_GR16 } },
+ { X86::IN16ri, Convert__ImmSExt81_1, { MCK_inw, MCK_ImmSExt8, MCK_AX } },
+ { X86::TAILJMPm, Convert__Mem5_2, { MCK_jmp, MCK__STAR_, MCK_Mem } },
+ { X86::JMP32r, Convert__Reg1_2, { MCK_jmpl, MCK__STAR_, MCK_GR32 } },
+ { X86::TAILJMPr, Convert__Reg1_2, { MCK_jmpl, MCK__STAR_, MCK_GR32 } },
+ { X86::JMP32m, Convert__Mem5_2, { MCK_jmpl, MCK__STAR_, MCK_Mem } },
+ { X86::JMP64r, Convert__Reg1_2, { MCK_jmpq, MCK__STAR_, MCK_GR64 } },
+ { X86::TAILJMPr64, Convert__Reg1_2, { MCK_jmpq, MCK__STAR_, MCK_GR64 } },
+ { X86::JMP64m, Convert__Mem5_2, { MCK_jmpq, MCK__STAR_, MCK_Mem } },
+ { X86::LAR32rr, Convert__Reg1_2__Reg1_1, { MCK_larl, MCK_GR32, MCK_GR32 } },
+ { X86::LAR32rm, Convert__Reg1_2__Mem5_1, { MCK_larl, MCK_Mem, MCK_GR32 } },
+ { X86::LAR64rr, Convert__Reg1_2__Reg1_1, { MCK_larq, MCK_GR32, MCK_GR64 } },
+ { X86::LAR64rm, Convert__Reg1_2__Mem5_1, { MCK_larq, MCK_Mem, MCK_GR64 } },
+ { X86::LAR16rr, Convert__Reg1_2__Reg1_1, { MCK_larw, MCK_GR16, MCK_GR16 } },
+ { X86::LAR16rm, Convert__Reg1_2__Mem5_1, { MCK_larw, MCK_Mem, MCK_GR16 } },
+ { X86::FARCALL32m, Convert__Mem5_2, { MCK_lcalll, MCK__STAR_, MCK_Mem } },
+ { X86::FARCALL32i, Convert__Imm1_1__Imm1_2, { MCK_lcalll, MCK_Imm, MCK_Imm } },
+ { X86::FARCALL64, Convert__Mem5_2, { MCK_lcallq, MCK__STAR_, MCK_Mem } },
+ { X86::FARCALL16m, Convert__Mem5_2, { MCK_lcallw, MCK__STAR_, MCK_Mem } },
+ { X86::FARCALL16i, Convert__Imm1_1__Imm1_2, { MCK_lcallw, MCK_Imm, MCK_Imm } },
+ { X86::LDDQUrm, Convert__Reg1_2__Mem5_1, { MCK_lddqu, MCK_Mem, MCK_FR32 } },
+ { X86::LDS32rm, Convert__Reg1_2__Mem5_1, { MCK_ldsl, MCK_Mem, MCK_GR32 } },
+ { X86::LDS16rm, Convert__Reg1_2__Mem5_1, { MCK_ldsw, MCK_Mem, MCK_GR16 } },
+ { X86::LEA32r, Convert__Reg1_2__NoSegMem4_1, { MCK_leal, MCK_NoSegMem, MCK_GR32 } },
+ { X86::LEA64_32r, Convert__Reg1_2__Mem4_1, { MCK_leal, MCK_Mem, MCK_GR32 } },
+ { X86::LEA64r, Convert__Reg1_2__Mem4_1, { MCK_leaq, MCK_Mem, MCK_GR64 } },
+ { X86::LEA16r, Convert__Reg1_2__NoSegMem4_1, { MCK_leaw, MCK_NoSegMem, MCK_GR16 } },
+ { X86::LES32rm, Convert__Reg1_2__Mem5_1, { MCK_lesl, MCK_Mem, MCK_GR32 } },
+ { X86::LES16rm, Convert__Reg1_2__Mem5_1, { MCK_lesw, MCK_Mem, MCK_GR16 } },
+ { X86::LFS32rm, Convert__Reg1_2__Mem5_1, { MCK_lfsl, MCK_Mem, MCK_GR32 } },
+ { X86::LFS64rm, Convert__Reg1_2__Mem5_1, { MCK_lfsq, MCK_Mem, MCK_GR64 } },
+ { X86::LFS16rm, Convert__Reg1_2__Mem5_1, { MCK_lfsw, MCK_Mem, MCK_GR16 } },
+ { X86::LGS32rm, Convert__Reg1_2__Mem5_1, { MCK_lgsl, MCK_Mem, MCK_GR32 } },
+ { X86::LGS64rm, Convert__Reg1_2__Mem5_1, { MCK_lgsq, MCK_Mem, MCK_GR64 } },
+ { X86::LGS16rm, Convert__Reg1_2__Mem5_1, { MCK_lgsw, MCK_Mem, MCK_GR16 } },
+ { X86::FARJMP32m, Convert__Mem5_2, { MCK_ljmpl, MCK__STAR_, MCK_Mem } },
+ { X86::FARJMP32i, Convert__Imm1_1__Imm1_2, { MCK_ljmpl, MCK_Imm, MCK_Imm } },
+ { X86::FARJMP64, Convert__Mem5_2, { MCK_ljmpq, MCK__STAR_, MCK_Mem } },
+ { X86::FARJMP16m, Convert__Mem5_2, { MCK_ljmpw, MCK__STAR_, MCK_Mem } },
+ { X86::FARJMP16i, Convert__Imm1_1__Imm1_2, { MCK_ljmpw, MCK_Imm, MCK_Imm } },
+ { X86::LSL32rr, Convert__Reg1_2__Reg1_1, { MCK_lsll, MCK_GR32, MCK_GR32 } },
+ { X86::LSL32rm, Convert__Reg1_2__Mem5_1, { MCK_lsll, MCK_Mem, MCK_GR32 } },
+ { X86::LSL64rr, Convert__Reg1_2__Reg1_1, { MCK_lslq, MCK_GR64, MCK_GR64 } },
+ { X86::LSL64rm, Convert__Reg1_2__Mem5_1, { MCK_lslq, MCK_Mem, MCK_GR64 } },
+ { X86::LSL16rr, Convert__Reg1_2__Reg1_1, { MCK_lslw, MCK_GR16, MCK_GR16 } },
+ { X86::LSL16rm, Convert__Reg1_2__Mem5_1, { MCK_lslw, MCK_Mem, MCK_GR16 } },
+ { X86::LSS32rm, Convert__Reg1_2__Mem5_1, { MCK_lssl, MCK_Mem, MCK_GR32 } },
+ { X86::LSS64rm, Convert__Reg1_2__Mem5_1, { MCK_lssq, MCK_Mem, MCK_GR64 } },
+ { X86::LSS16rm, Convert__Reg1_2__Mem5_1, { MCK_lssw, MCK_Mem, MCK_GR16 } },
+ { X86::MASKMOVDQU, Convert__Reg1_2__Reg1_1, { MCK_maskmovdqu, MCK_FR32, MCK_FR32 } },
+ { X86::MASKMOVDQU64, Convert__Reg1_2__Reg1_1, { MCK_maskmovdqu, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_MASKMOVQ, Convert__Reg1_2__Reg1_1, { MCK_maskmovq, MCK_VR64, MCK_VR64 } },
+ { X86::MMX_MASKMOVQ64, Convert__Reg1_2__Reg1_1, { MCK_maskmovq, MCK_VR64, MCK_VR64 } },
+ { X86::MAXPDrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_maxpd, MCK_FR32, MCK_FR32 } },
+ { X86::MAXPDrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_maxpd, MCK_Mem, MCK_FR32 } },
+ { X86::MAXPSrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_maxps, MCK_FR32, MCK_FR32 } },
+ { X86::MAXPSrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_maxps, MCK_Mem, MCK_FR32 } },
+ { X86::MAXSDrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_maxsd, MCK_FR32, MCK_FR32 } },
+ { X86::MAXSDrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_maxsd, MCK_Mem, MCK_FR32 } },
+ { X86::MAXSSrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_maxss, MCK_FR32, MCK_FR32 } },
+ { X86::MAXSSrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_maxss, MCK_Mem, MCK_FR32 } },
+ { X86::MINPDrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_minpd, MCK_FR32, MCK_FR32 } },
+ { X86::MINPDrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_minpd, MCK_Mem, MCK_FR32 } },
+ { X86::MINPSrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_minps, MCK_FR32, MCK_FR32 } },
+ { X86::MINPSrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_minps, MCK_Mem, MCK_FR32 } },
+ { X86::MINSDrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_minsd, MCK_FR32, MCK_FR32 } },
+ { X86::MINSDrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_minsd, MCK_Mem, MCK_FR32 } },
+ { X86::MINSSrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_minss, MCK_FR32, MCK_FR32 } },
+ { X86::MINSSrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_minss, MCK_Mem, MCK_FR32 } },
+ { X86::MOV64ri, Convert__Reg1_2__Imm1_1, { MCK_movabsq, MCK_Imm, MCK_GR64 } },
+ { X86::FsMOVAPDrr, Convert__Reg1_2__Reg1_1, { MCK_movapd, MCK_FR32, MCK_FR32 } },
+ { X86::MOVAPDrr, Convert__Reg1_2__Reg1_1, { MCK_movapd, MCK_FR32, MCK_FR32 } },
+ { X86::MOVAPDmr, Convert__Mem5_2__Reg1_1, { MCK_movapd, MCK_FR32, MCK_Mem } },
+ { X86::FsMOVAPDrm, Convert__Reg1_2__Mem5_1, { MCK_movapd, MCK_Mem, MCK_FR32 } },
+ { X86::MOVAPDrm, Convert__Reg1_2__Mem5_1, { MCK_movapd, MCK_Mem, MCK_FR32 } },
+ { X86::FsMOVAPSrr, Convert__Reg1_2__Reg1_1, { MCK_movaps, MCK_FR32, MCK_FR32 } },
+ { X86::MOVAPSrr, Convert__Reg1_2__Reg1_1, { MCK_movaps, MCK_FR32, MCK_FR32 } },
+ { X86::MOVAPSmr, Convert__Mem5_2__Reg1_1, { MCK_movaps, MCK_FR32, MCK_Mem } },
+ { X86::FsMOVAPSrm, Convert__Reg1_2__Mem5_1, { MCK_movaps, MCK_Mem, MCK_FR32 } },
+ { X86::MOVAPSrm, Convert__Reg1_2__Mem5_1, { MCK_movaps, MCK_Mem, MCK_FR32 } },
+ { X86::MOV8ao8, Convert__AbsMem1_2, { MCK_movb, MCK_AL, MCK_AbsMem } },
+ { X86::MOV8rr_NOREX, Convert__Reg1_2__Reg1_1, { MCK_movb, MCK_GR8_NOREX, MCK_GR8_NOREX } },
+ { X86::MOV8mr_NOREX, Convert__Mem5_2__Reg1_1, { MCK_movb, MCK_GR8_NOREX, MCK_Mem } },
+ { X86::MOV8rr, Convert__Reg1_2__Reg1_1, { MCK_movb, MCK_GR8, MCK_GR8 } },
+ { X86::MOV8rr_REV, Convert__Reg1_2__Reg1_1, { MCK_movb, MCK_GR8, MCK_GR8 } },
+ { X86::MOV8mr, Convert__Mem5_2__Reg1_1, { MCK_movb, MCK_GR8, MCK_Mem } },
+ { X86::MOV8ri, Convert__Reg1_2__Imm1_1, { MCK_movb, MCK_Imm, MCK_GR8 } },
+ { X86::MOV8mi, Convert__Mem5_2__Imm1_1, { MCK_movb, MCK_Imm, MCK_Mem } },
+ { X86::MOV8o8a, Convert__AbsMem1_1, { MCK_movb, MCK_AbsMem, MCK_AL } },
+ { X86::MOV8rm_NOREX, Convert__Reg1_2__Mem5_1, { MCK_movb, MCK_Mem, MCK_GR8_NOREX } },
+ { X86::MOV8rm, Convert__Reg1_2__Mem5_1, { MCK_movb, MCK_Mem, MCK_GR8 } },
+ { X86::MMX_MOVD64rr, Convert__Reg1_2__Reg1_1, { MCK_movd, MCK_GR32, MCK_VR64 } },
+ { X86::MMX_MOVZDI2PDIrr, Convert__Reg1_2__Reg1_1, { MCK_movd, MCK_GR32, MCK_VR64 } },
+ { X86::MOVDI2PDIrr, Convert__Reg1_2__Reg1_1, { MCK_movd, MCK_GR32, MCK_FR32 } },
+ { X86::MOVDI2SSrr, Convert__Reg1_2__Reg1_1, { MCK_movd, MCK_GR32, MCK_FR32 } },
+ { X86::MOVZDI2PDIrr, Convert__Reg1_2__Reg1_1, { MCK_movd, MCK_GR32, MCK_FR32 } },
+ { X86::MMX_MOVD64rrv164, Convert__Reg1_2__Reg1_1, { MCK_movd, MCK_GR64, MCK_VR64 } },
+ { X86::MMX_MOVD64to64rr, Convert__Reg1_2__Reg1_1, { MCK_movd, MCK_GR64, MCK_VR64 } },
+ { X86::MOV64toPQIrr, Convert__Reg1_2__Reg1_1, { MCK_movd, MCK_GR64, MCK_FR32 } },
+ { X86::MOV64toSDrr, Convert__Reg1_2__Reg1_1, { MCK_movd, MCK_GR64, MCK_FR32 } },
+ { X86::MOVZQI2PQIrr, Convert__Reg1_2__Reg1_1, { MCK_movd, MCK_GR64, MCK_FR32 } },
+ { X86::MMX_MOVD64grr, Convert__Reg1_2__Reg1_1, { MCK_movd, MCK_VR64, MCK_GR32 } },
+ { X86::MMX_MOVD64from64rr, Convert__Reg1_2__Reg1_1, { MCK_movd, MCK_VR64, MCK_GR64 } },
+ { X86::MMX_MOVD64mr, Convert__Mem5_2__Reg1_1, { MCK_movd, MCK_VR64, MCK_Mem } },
+ { X86::MOVPDI2DIrr, Convert__Reg1_2__Reg1_1, { MCK_movd, MCK_FR32, MCK_GR32 } },
+ { X86::MOVSS2DIrr, Convert__Reg1_2__Reg1_1, { MCK_movd, MCK_FR32, MCK_GR32 } },
+ { X86::MOVPQIto64rr, Convert__Reg1_2__Reg1_1, { MCK_movd, MCK_FR32, MCK_GR64 } },
+ { X86::MOVSDto64rr, Convert__Reg1_2__Reg1_1, { MCK_movd, MCK_FR32, MCK_GR64 } },
+ { X86::MOVPDI2DImr, Convert__Mem5_2__Reg1_1, { MCK_movd, MCK_FR32, MCK_Mem } },
+ { X86::MOVSS2DImr, Convert__Mem5_2__Reg1_1, { MCK_movd, MCK_FR32, MCK_Mem } },
+ { X86::MMX_MOVD64rm, Convert__Reg1_2__Mem5_1, { MCK_movd, MCK_Mem, MCK_VR64 } },
+ { X86::MMX_MOVZDI2PDIrm, Convert__Reg1_2__Mem5_1, { MCK_movd, MCK_Mem, MCK_VR64 } },
+ { X86::MOVDI2PDIrm, Convert__Reg1_2__Mem5_1, { MCK_movd, MCK_Mem, MCK_FR32 } },
+ { X86::MOVDI2SSrm, Convert__Reg1_2__Mem5_1, { MCK_movd, MCK_Mem, MCK_FR32 } },
+ { X86::MOVZDI2PDIrm, Convert__Reg1_2__Mem5_1, { MCK_movd, MCK_Mem, MCK_FR32 } },
+ { X86::MOVDDUPrr, Convert__Reg1_2__Reg1_1, { MCK_movddup, MCK_FR32, MCK_FR32 } },
+ { X86::MOVDDUPrm, Convert__Reg1_2__Mem5_1, { MCK_movddup, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_MOVDQ2Qrr, Convert__Reg1_2__Reg1_1, { MCK_movdq2q, MCK_FR32, MCK_VR64 } },
+ { X86::MOVDQArr, Convert__Reg1_2__Reg1_1, { MCK_movdqa, MCK_FR32, MCK_FR32 } },
+ { X86::MOVDQAmr, Convert__Mem5_2__Reg1_1, { MCK_movdqa, MCK_FR32, MCK_Mem } },
+ { X86::MOVDQArm, Convert__Reg1_2__Mem5_1, { MCK_movdqa, MCK_Mem, MCK_FR32 } },
+ { X86::MOVDQUmr, Convert__Mem5_2__Reg1_1, { MCK_movdqu, MCK_FR32, MCK_Mem } },
+ { X86::MOVDQUrm, Convert__Reg1_2__Mem5_1, { MCK_movdqu, MCK_Mem, MCK_FR32 } },
+ { X86::MOVHLPSrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_movhlps, MCK_FR32, MCK_FR32 } },
+ { X86::MOVHPDmr, Convert__Mem5_2__Reg1_1, { MCK_movhpd, MCK_FR32, MCK_Mem } },
+ { X86::MOVHPDrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_movhpd, MCK_Mem, MCK_FR32 } },
+ { X86::MOVHPSmr, Convert__Mem5_2__Reg1_1, { MCK_movhps, MCK_FR32, MCK_Mem } },
+ { X86::MOVHPSrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_movhps, MCK_Mem, MCK_FR32 } },
+ { X86::MOV32ao32, Convert__AbsMem1_2, { MCK_movl, MCK_EAX, MCK_AbsMem } },
+ { X86::MOV32rr, Convert__Reg1_2__Reg1_1, { MCK_movl, MCK_GR32, MCK_GR32 } },
+ { X86::MOV32rr_REV, Convert__Reg1_2__Reg1_1, { MCK_movl, MCK_GR32, MCK_GR32 } },
+ { X86::MOV32dr, Convert__Reg1_2__Reg1_1, { MCK_movl, MCK_GR32, MCK_DEBUG_REG } },
+ { X86::MOV32mr, Convert__Mem5_2__Reg1_1, { MCK_movl, MCK_GR32, MCK_Mem } },
+ { X86::MOV32rd, Convert__Reg1_2__Reg1_1, { MCK_movl, MCK_DEBUG_REG, MCK_GR32 } },
+ { X86::MOV32ri, Convert__Reg1_2__Imm1_1, { MCK_movl, MCK_Imm, MCK_GR32 } },
+ { X86::MOV32mi, Convert__Mem5_2__Imm1_1, { MCK_movl, MCK_Imm, MCK_Mem } },
+ { X86::MOV32o32a, Convert__AbsMem1_1, { MCK_movl, MCK_AbsMem, MCK_EAX } },
+ { X86::MOV32rm, Convert__Reg1_2__Mem5_1, { MCK_movl, MCK_Mem, MCK_GR32 } },
+ { X86::MOVLHPSrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_movlhps, MCK_FR32, MCK_FR32 } },
+ { X86::MOVLPDmr, Convert__Mem5_2__Reg1_1, { MCK_movlpd, MCK_FR32, MCK_Mem } },
+ { X86::MOVLPDrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_movlpd, MCK_Mem, MCK_FR32 } },
+ { X86::MOVLPSmr, Convert__Mem5_2__Reg1_1, { MCK_movlps, MCK_FR32, MCK_Mem } },
+ { X86::MOVLPSrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_movlps, MCK_Mem, MCK_FR32 } },
+ { X86::MOVMSKPDrr, Convert__Reg1_2__Reg1_1, { MCK_movmskpd, MCK_FR32, MCK_GR32 } },
+ { X86::MOVMSKPSrr, Convert__Reg1_2__Reg1_1, { MCK_movmskps, MCK_FR32, MCK_GR32 } },
+ { X86::MOVNTDQmr, Convert__Mem5_2__Reg1_1, { MCK_movntdq, MCK_FR32, MCK_Mem } },
+ { X86::MOVNTDQArm, Convert__Reg1_2__Mem5_1, { MCK_movntdqa, MCK_Mem, MCK_FR32 } },
+ { X86::MOVNTImr, Convert__Mem5_2__Reg1_1, { MCK_movnti, MCK_GR32, MCK_Mem } },
+ { X86::MOVNTPDmr, Convert__Mem5_2__Reg1_1, { MCK_movntpd, MCK_FR32, MCK_Mem } },
+ { X86::MOVNTPSmr, Convert__Mem5_2__Reg1_1, { MCK_movntps, MCK_FR32, MCK_Mem } },
+ { X86::MMX_MOVNTQmr, Convert__Mem5_2__Reg1_1, { MCK_movntq, MCK_VR64, MCK_Mem } },
+ { X86::MOV32cr, Convert__Reg1_2__Reg1_1, { MCK_movq, MCK_GR32, MCK_CONTROL_REG_32 } },
+ { X86::MOV64ao64, Convert__AbsMem1_2, { MCK_movq, MCK_RAX, MCK_AbsMem } },
+ { X86::MOV64ao8, Convert__AbsMem1_2, { MCK_movq, MCK_RAX, MCK_AbsMem } },
+ { X86::MOV64rr, Convert__Reg1_2__Reg1_1, { MCK_movq, MCK_GR64, MCK_GR64 } },
+ { X86::MOV64rr_REV, Convert__Reg1_2__Reg1_1, { MCK_movq, MCK_GR64, MCK_GR64 } },
+ { X86::MOV64sr, Convert__Reg1_2__Reg1_1, { MCK_movq, MCK_GR64, MCK_SEGMENT_REG } },
+ { X86::MOV64dr, Convert__Reg1_2__Reg1_1, { MCK_movq, MCK_GR64, MCK_DEBUG_REG } },
+ { X86::MOV64cr, Convert__Reg1_2__Reg1_1, { MCK_movq, MCK_GR64, MCK_CONTROL_REG_64 } },
+ { X86::MOV64mr, Convert__Mem5_2__Reg1_1, { MCK_movq, MCK_GR64, MCK_Mem } },
+ { X86::MMX_MOVQ64rr, Convert__Reg1_2__Reg1_1, { MCK_movq, MCK_VR64, MCK_VR64 } },
+ { X86::MMX_MOVQ64gmr, Convert__Mem5_2__Reg1_1, { MCK_movq, MCK_VR64, MCK_Mem } },
+ { X86::MMX_MOVQ64mr, Convert__Mem5_2__Reg1_1, { MCK_movq, MCK_VR64, MCK_Mem } },
+ { X86::MOVQxrxr, Convert__Reg1_2__Reg1_1, { MCK_movq, MCK_FR32, MCK_FR32 } },
+ { X86::MOVZPQILo2PQIrr, Convert__Reg1_2__Reg1_1, { MCK_movq, MCK_FR32, MCK_FR32 } },
+ { X86::MOVLQ128mr, Convert__Mem5_2__Reg1_1, { MCK_movq, MCK_FR32, MCK_Mem } },
+ { X86::MOVPQI2QImr, Convert__Mem5_2__Reg1_1, { MCK_movq, MCK_FR32, MCK_Mem } },
+ { X86::MOVSDto64mr, Convert__Mem5_2__Reg1_1, { MCK_movq, MCK_FR32, MCK_Mem } },
+ { X86::MOV64rs, Convert__Reg1_2__Reg1_1, { MCK_movq, MCK_SEGMENT_REG, MCK_GR64 } },
+ { X86::MOV64ms, Convert__Mem5_2__Reg1_1, { MCK_movq, MCK_SEGMENT_REG, MCK_Mem } },
+ { X86::MOV64rd, Convert__Reg1_2__Reg1_1, { MCK_movq, MCK_DEBUG_REG, MCK_GR64 } },
+ { X86::MOV32rc, Convert__Reg1_2__Reg1_1, { MCK_movq, MCK_CONTROL_REG_32, MCK_GR32 } },
+ { X86::MOV64rc, Convert__Reg1_2__Reg1_1, { MCK_movq, MCK_CONTROL_REG_64, MCK_GR64 } },
+ { X86::MOV64ri32, Convert__Reg1_2__Imm1_1, { MCK_movq, MCK_Imm, MCK_GR64 } },
+ { X86::MOV64mi32, Convert__Mem5_2__Imm1_1, { MCK_movq, MCK_Imm, MCK_Mem } },
+ { X86::MOV64o64a, Convert__AbsMem1_1, { MCK_movq, MCK_AbsMem, MCK_RAX } },
+ { X86::MOV64o8a, Convert__AbsMem1_1, { MCK_movq, MCK_AbsMem, MCK_RAX } },
+ { X86::MOV64rm, Convert__Reg1_2__Mem5_1, { MCK_movq, MCK_Mem, MCK_GR64 } },
+ { X86::MMX_MOVQ64rm, Convert__Reg1_2__Mem5_1, { MCK_movq, MCK_Mem, MCK_VR64 } },
+ { X86::MOV64toSDrm, Convert__Reg1_2__Mem5_1, { MCK_movq, MCK_Mem, MCK_FR32 } },
+ { X86::MOVQI2PQIrm, Convert__Reg1_2__Mem5_1, { MCK_movq, MCK_Mem, MCK_FR32 } },
+ { X86::MOVZPQILo2PQIrm, Convert__Reg1_2__Mem5_1, { MCK_movq, MCK_Mem, MCK_FR32 } },
+ { X86::MOVZQI2PQIrm, Convert__Reg1_2__Mem5_1, { MCK_movq, MCK_Mem, MCK_FR32 } },
+ { X86::MOV64sm, Convert__Reg1_2__Mem5_1, { MCK_movq, MCK_Mem, MCK_SEGMENT_REG } },
+ { X86::MMX_MOVQ2DQrr, Convert__Reg1_2__Reg1_1, { MCK_movq2dq, MCK_VR64, MCK_FR32 } },
+ { X86::MMX_MOVQ2FR64rr, Convert__Reg1_2__Reg1_1, { MCK_movq2dq, MCK_VR64, MCK_FR32 } },
+ { X86::MOVSX32rr8, Convert__Reg1_2__Reg1_1, { MCK_movsbl, MCK_GR8, MCK_GR32 } },
+ { X86::MOVSX32rm8, Convert__Reg1_2__Mem5_1, { MCK_movsbl, MCK_Mem, MCK_GR32 } },
+ { X86::MOVSX64rr8, Convert__Reg1_2__Reg1_1, { MCK_movsbq, MCK_GR8, MCK_GR64 } },
+ { X86::MOVSX64rm8, Convert__Reg1_2__Mem5_1, { MCK_movsbq, MCK_Mem, MCK_GR64 } },
+ { X86::MOVSX16rr8W, Convert__Reg1_2__Reg1_1, { MCK_movsbw, MCK_GR8, MCK_GR16 } },
+ { X86::MOVSX16rm8W, Convert__Reg1_2__Mem5_1, { MCK_movsbw, MCK_Mem, MCK_GR16 } },
+ { X86::MOVLPDrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_movsd, MCK_FR32, MCK_FR32 } },
+ { X86::MOVLSD2PDrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_movsd, MCK_FR32, MCK_FR32 } },
+ { X86::MOVPD2SDrr, Convert__Reg1_2__Reg1_1, { MCK_movsd, MCK_FR32, MCK_FR32 } },
+ { X86::MOVSD2PDrr, Convert__Reg1_2__Reg1_1, { MCK_movsd, MCK_FR32, MCK_FR32 } },
+ { X86::MOVSDrr, Convert__Reg1_2__Reg1_1, { MCK_movsd, MCK_FR32, MCK_FR32 } },
+ { X86::MOVPD2SDmr, Convert__Mem5_2__Reg1_1, { MCK_movsd, MCK_FR32, MCK_Mem } },
+ { X86::MOVSDmr, Convert__Mem5_2__Reg1_1, { MCK_movsd, MCK_FR32, MCK_Mem } },
+ { X86::MOVSD2PDrm, Convert__Reg1_2__Mem5_1, { MCK_movsd, MCK_Mem, MCK_FR32 } },
+ { X86::MOVSDrm, Convert__Reg1_2__Mem5_1, { MCK_movsd, MCK_Mem, MCK_FR32 } },
+ { X86::MOVZSD2PDrm, Convert__Reg1_2__Mem5_1, { MCK_movsd, MCK_Mem, MCK_FR32 } },
+ { X86::MOVSHDUPrr, Convert__Reg1_2__Reg1_1, { MCK_movshdup, MCK_FR32, MCK_FR32 } },
+ { X86::MOVSHDUPrm, Convert__Reg1_2__Mem5_1, { MCK_movshdup, MCK_Mem, MCK_FR32 } },
+ { X86::MOVSLDUPrr, Convert__Reg1_2__Reg1_1, { MCK_movsldup, MCK_FR32, MCK_FR32 } },
+ { X86::MOVSLDUPrm, Convert__Reg1_2__Mem5_1, { MCK_movsldup, MCK_Mem, MCK_FR32 } },
+ { X86::MOVSX64rr32, Convert__Reg1_2__Reg1_1, { MCK_movslq, MCK_GR32, MCK_GR64 } },
+ { X86::MOVSX64rm32, Convert__Reg1_2__Mem5_1, { MCK_movslq, MCK_Mem, MCK_GR64 } },
+ { X86::MOVLPSrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_movss, MCK_FR32, MCK_FR32 } },
+ { X86::MOVLSS2PSrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_movss, MCK_FR32, MCK_FR32 } },
+ { X86::MOVPS2SSrr, Convert__Reg1_2__Reg1_1, { MCK_movss, MCK_FR32, MCK_FR32 } },
+ { X86::MOVSS2PSrr, Convert__Reg1_2__Reg1_1, { MCK_movss, MCK_FR32, MCK_FR32 } },
+ { X86::MOVSSrr, Convert__Reg1_2__Reg1_1, { MCK_movss, MCK_FR32, MCK_FR32 } },
+ { X86::MOVPS2SSmr, Convert__Mem5_2__Reg1_1, { MCK_movss, MCK_FR32, MCK_Mem } },
+ { X86::MOVSSmr, Convert__Mem5_2__Reg1_1, { MCK_movss, MCK_FR32, MCK_Mem } },
+ { X86::MOVSS2PSrm, Convert__Reg1_2__Mem5_1, { MCK_movss, MCK_Mem, MCK_FR32 } },
+ { X86::MOVSSrm, Convert__Reg1_2__Mem5_1, { MCK_movss, MCK_Mem, MCK_FR32 } },
+ { X86::MOVZSS2PSrm, Convert__Reg1_2__Mem5_1, { MCK_movss, MCK_Mem, MCK_FR32 } },
+ { X86::MOVSX32rr16, Convert__Reg1_2__Reg1_1, { MCK_movswl, MCK_GR16, MCK_GR32 } },
+ { X86::MOVSX32rm16, Convert__Reg1_2__Mem5_1, { MCK_movswl, MCK_Mem, MCK_GR32 } },
+ { X86::MOVSX64rr16, Convert__Reg1_2__Reg1_1, { MCK_movswq, MCK_GR16, MCK_GR64 } },
+ { X86::MOVSX64rm16, Convert__Reg1_2__Mem5_1, { MCK_movswq, MCK_Mem, MCK_GR64 } },
+ { X86::MOVUPDrr, Convert__Reg1_2__Reg1_1, { MCK_movupd, MCK_FR32, MCK_FR32 } },
+ { X86::MOVUPDmr, Convert__Mem5_2__Reg1_1, { MCK_movupd, MCK_FR32, MCK_Mem } },
+ { X86::MOVUPDrm, Convert__Reg1_2__Mem5_1, { MCK_movupd, MCK_Mem, MCK_FR32 } },
+ { X86::MOVUPSrr, Convert__Reg1_2__Reg1_1, { MCK_movups, MCK_FR32, MCK_FR32 } },
+ { X86::MOVUPSmr, Convert__Mem5_2__Reg1_1, { MCK_movups, MCK_FR32, MCK_Mem } },
+ { X86::MOVUPSrm, Convert__Reg1_2__Mem5_1, { MCK_movups, MCK_Mem, MCK_FR32 } },
+ { X86::MOV16ao16, Convert__AbsMem1_2, { MCK_movw, MCK_AX, MCK_AbsMem } },
+ { X86::MOV16rr, Convert__Reg1_2__Reg1_1, { MCK_movw, MCK_GR16, MCK_GR16 } },
+ { X86::MOV16rr_REV, Convert__Reg1_2__Reg1_1, { MCK_movw, MCK_GR16, MCK_GR16 } },
+ { X86::MOV16sr, Convert__Reg1_2__Reg1_1, { MCK_movw, MCK_GR16, MCK_SEGMENT_REG } },
+ { X86::MOV16mr, Convert__Mem5_2__Reg1_1, { MCK_movw, MCK_GR16, MCK_Mem } },
+ { X86::MOV16rs, Convert__Reg1_2__Reg1_1, { MCK_movw, MCK_SEGMENT_REG, MCK_GR16 } },
+ { X86::MOV16ms, Convert__Mem5_2__Reg1_1, { MCK_movw, MCK_SEGMENT_REG, MCK_Mem } },
+ { X86::MOV16ri, Convert__Reg1_2__Imm1_1, { MCK_movw, MCK_Imm, MCK_GR16 } },
+ { X86::MOV16mi, Convert__Mem5_2__Imm1_1, { MCK_movw, MCK_Imm, MCK_Mem } },
+ { X86::MOV16o16a, Convert__AbsMem1_1, { MCK_movw, MCK_AbsMem, MCK_AX } },
+ { X86::MOV16rm, Convert__Reg1_2__Mem5_1, { MCK_movw, MCK_Mem, MCK_GR16 } },
+ { X86::MOV16sm, Convert__Reg1_2__Mem5_1, { MCK_movw, MCK_Mem, MCK_SEGMENT_REG } },
+ { X86::MOVZX32_NOREXrr8, Convert__Reg1_2__Reg1_1, { MCK_movzbl, MCK_GR8, MCK_GR32_NOREX } },
+ { X86::MOVZX32rr8, Convert__Reg1_2__Reg1_1, { MCK_movzbl, MCK_GR8, MCK_GR32 } },
+ { X86::MOVZX32_NOREXrm8, Convert__Reg1_2__Mem5_1, { MCK_movzbl, MCK_Mem, MCK_GR32_NOREX } },
+ { X86::MOVZX32rm8, Convert__Reg1_2__Mem5_1, { MCK_movzbl, MCK_Mem, MCK_GR32 } },
+ { X86::MOVZX64rr8_Q, Convert__Reg1_2__Reg1_1, { MCK_movzbq, MCK_GR8, MCK_GR64 } },
+ { X86::MOVZX64rm8_Q, Convert__Reg1_2__Mem5_1, { MCK_movzbq, MCK_Mem, MCK_GR64 } },
+ { X86::MOVZX16rr8W, Convert__Reg1_2__Reg1_1, { MCK_movzbw, MCK_GR8, MCK_GR16 } },
+ { X86::MOVZX16rm8W, Convert__Reg1_2__Mem5_1, { MCK_movzbw, MCK_Mem, MCK_GR16 } },
+ { X86::MOVZX32rr16, Convert__Reg1_2__Reg1_1, { MCK_movzwl, MCK_GR16, MCK_GR32 } },
+ { X86::MOVZX32rm16, Convert__Reg1_2__Mem5_1, { MCK_movzwl, MCK_Mem, MCK_GR32 } },
+ { X86::MOVZX64rr16_Q, Convert__Reg1_2__Reg1_1, { MCK_movzwq, MCK_GR16, MCK_GR64 } },
+ { X86::MOVZX64rm16_Q, Convert__Reg1_2__Mem5_1, { MCK_movzwq, MCK_Mem, MCK_GR64 } },
+ { X86::MULPDrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_mulpd, MCK_FR32, MCK_FR32 } },
+ { X86::MULPDrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_mulpd, MCK_Mem, MCK_FR32 } },
+ { X86::MULPSrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_mulps, MCK_FR32, MCK_FR32 } },
+ { X86::MULPSrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_mulps, MCK_Mem, MCK_FR32 } },
+ { X86::MULSDrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_mulsd, MCK_FR32, MCK_FR32 } },
+ { X86::MULSDrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_mulsd, MCK_Mem, MCK_FR32 } },
+ { X86::MULSSrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_mulss, MCK_FR32, MCK_FR32 } },
+ { X86::MULSSrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_mulss, MCK_Mem, MCK_FR32 } },
+ { X86::OR8rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_orb, MCK_GR8, MCK_GR8 } },
+ { X86::OR8rr_REV, Convert__Reg1_2__Tie0__Reg1_1, { MCK_orb, MCK_GR8, MCK_GR8 } },
+ { X86::OR8mr, Convert__Mem5_2__Reg1_1, { MCK_orb, MCK_GR8, MCK_Mem } },
+ { X86::OR8i8, Convert__Imm1_1, { MCK_orb, MCK_Imm, MCK_AL } },
+ { X86::OR8ri, Convert__Reg1_2__Tie0__Imm1_1, { MCK_orb, MCK_Imm, MCK_GR8 } },
+ { X86::OR8mi, Convert__Mem5_2__Imm1_1, { MCK_orb, MCK_Imm, MCK_Mem } },
+ { X86::OR8rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_orb, MCK_Mem, MCK_GR8 } },
+ { X86::OR32rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_orl, MCK_GR32, MCK_GR32 } },
+ { X86::OR32rr_REV, Convert__Reg1_2__Tie0__Reg1_1, { MCK_orl, MCK_GR32, MCK_GR32 } },
+ { X86::OR32mr, Convert__Mem5_2__Reg1_1, { MCK_orl, MCK_GR32, MCK_Mem } },
+ { X86::OR32ri8, Convert__Reg1_2__Tie0__ImmSExt81_1, { MCK_orl, MCK_ImmSExt8, MCK_GR32 } },
+ { X86::OR32mi8, Convert__Mem5_2__ImmSExt81_1, { MCK_orl, MCK_ImmSExt8, MCK_Mem } },
+ { X86::OR32i32, Convert__Imm1_1, { MCK_orl, MCK_Imm, MCK_EAX } },
+ { X86::OR32ri, Convert__Reg1_2__Tie0__Imm1_1, { MCK_orl, MCK_Imm, MCK_GR32 } },
+ { X86::OR32mi, Convert__Mem5_2__Imm1_1, { MCK_orl, MCK_Imm, MCK_Mem } },
+ { X86::OR32rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_orl, MCK_Mem, MCK_GR32 } },
+ { X86::FsORPDrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_orpd, MCK_FR32, MCK_FR32 } },
+ { X86::ORPDrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_orpd, MCK_FR32, MCK_FR32 } },
+ { X86::FsORPDrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_orpd, MCK_Mem, MCK_FR32 } },
+ { X86::ORPDrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_orpd, MCK_Mem, MCK_FR32 } },
+ { X86::FsORPSrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_orps, MCK_FR32, MCK_FR32 } },
+ { X86::ORPSrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_orps, MCK_FR32, MCK_FR32 } },
+ { X86::FsORPSrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_orps, MCK_Mem, MCK_FR32 } },
+ { X86::ORPSrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_orps, MCK_Mem, MCK_FR32 } },
+ { X86::OR64rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_orq, MCK_GR64, MCK_GR64 } },
+ { X86::OR64rr_REV, Convert__Reg1_2__Tie0__Reg1_1, { MCK_orq, MCK_GR64, MCK_GR64 } },
+ { X86::OR64mr, Convert__Mem5_2__Reg1_1, { MCK_orq, MCK_GR64, MCK_Mem } },
+ { X86::OR64ri8, Convert__Reg1_2__Tie0__ImmSExt81_1, { MCK_orq, MCK_ImmSExt8, MCK_GR64 } },
+ { X86::OR64mi8, Convert__Mem5_2__ImmSExt81_1, { MCK_orq, MCK_ImmSExt8, MCK_Mem } },
+ { X86::OR64i32, Convert__Imm1_1, { MCK_orq, MCK_Imm, MCK_RAX } },
+ { X86::OR64ri32, Convert__Reg1_2__Tie0__Imm1_1, { MCK_orq, MCK_Imm, MCK_GR64 } },
+ { X86::OR64mi32, Convert__Mem5_2__Imm1_1, { MCK_orq, MCK_Imm, MCK_Mem } },
+ { X86::OR64rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_orq, MCK_Mem, MCK_GR64 } },
+ { X86::OR16rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_orw, MCK_GR16, MCK_GR16 } },
+ { X86::OR16rr_REV, Convert__Reg1_2__Tie0__Reg1_1, { MCK_orw, MCK_GR16, MCK_GR16 } },
+ { X86::OR16mr, Convert__Mem5_2__Reg1_1, { MCK_orw, MCK_GR16, MCK_Mem } },
+ { X86::OR16ri8, Convert__Reg1_2__Tie0__ImmSExt81_1, { MCK_orw, MCK_ImmSExt8, MCK_GR16 } },
+ { X86::OR16mi8, Convert__Mem5_2__ImmSExt81_1, { MCK_orw, MCK_ImmSExt8, MCK_Mem } },
+ { X86::OR16i16, Convert__Imm1_1, { MCK_orw, MCK_Imm, MCK_AX } },
+ { X86::OR16ri, Convert__Reg1_2__Tie0__Imm1_1, { MCK_orw, MCK_Imm, MCK_GR16 } },
+ { X86::OR16mi, Convert__Mem5_2__Imm1_1, { MCK_orw, MCK_Imm, MCK_Mem } },
+ { X86::OR16rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_orw, MCK_Mem, MCK_GR16 } },
{ X86::OUT8rr, Convert, { MCK_outb, MCK_AL, MCK_DX } },
- { X86::OUT8ir, Convert_ImmSExt81_2, { MCK_outb, MCK_AL, MCK_ImmSExt8 } },
+ { X86::OUT8ir, Convert__ImmSExt81_2, { MCK_outb, MCK_AL, MCK_ImmSExt8 } },
{ X86::OUT32rr, Convert, { MCK_outl, MCK_EAX, MCK_DX } },
- { X86::OUT32ir, Convert_ImmSExt81_2, { MCK_outl, MCK_EAX, MCK_ImmSExt8 } },
+ { X86::OUT32ir, Convert__ImmSExt81_2, { MCK_outl, MCK_EAX, MCK_ImmSExt8 } },
{ X86::OUT16rr, Convert, { MCK_outw, MCK_AX, MCK_DX } },
- { X86::OUT16ir, Convert_ImmSExt81_2, { MCK_outw, MCK_AX, MCK_ImmSExt8 } },
- { X86::PABSBrr64, Convert_Reg1_2_Reg1_1, { MCK_pabsb, MCK_VR64, MCK_VR64 } },
- { X86::PABSBrr128, Convert_Reg1_2_Reg1_1, { MCK_pabsb, MCK_FR32, MCK_FR32 } },
- { X86::PABSBrm64, Convert_Reg1_2_Mem5_1, { MCK_pabsb, MCK_Mem, MCK_VR64 } },
- { X86::PABSBrm128, Convert_Reg1_2_Mem5_1, { MCK_pabsb, MCK_Mem, MCK_FR32 } },
- { X86::PABSDrr64, Convert_Reg1_2_Reg1_1, { MCK_pabsd, MCK_VR64, MCK_VR64 } },
- { X86::PABSDrr128, Convert_Reg1_2_Reg1_1, { MCK_pabsd, MCK_FR32, MCK_FR32 } },
- { X86::PABSDrm64, Convert_Reg1_2_Mem5_1, { MCK_pabsd, MCK_Mem, MCK_VR64 } },
- { X86::PABSDrm128, Convert_Reg1_2_Mem5_1, { MCK_pabsd, MCK_Mem, MCK_FR32 } },
- { X86::PABSWrr64, Convert_Reg1_2_Reg1_1, { MCK_pabsw, MCK_VR64, MCK_VR64 } },
- { X86::PABSWrr128, Convert_Reg1_2_Reg1_1, { MCK_pabsw, MCK_FR32, MCK_FR32 } },
- { X86::PABSWrm64, Convert_Reg1_2_Mem5_1, { MCK_pabsw, MCK_Mem, MCK_VR64 } },
- { X86::PABSWrm128, Convert_Reg1_2_Mem5_1, { MCK_pabsw, MCK_Mem, MCK_FR32 } },
- { X86::MMX_PACKSSDWrr, Convert_Reg1_2_ImpReg1_1, { MCK_packssdw, MCK_VR64, MCK_VR64 } },
- { X86::PACKSSDWrr, Convert_Reg1_2_ImpReg1_1, { MCK_packssdw, MCK_FR32, MCK_FR32 } },
- { X86::MMX_PACKSSDWrm, Convert_Reg1_2_ImpMem5_1, { MCK_packssdw, MCK_Mem, MCK_VR64 } },
- { X86::PACKSSDWrm, Convert_Reg1_2_ImpMem5_1, { MCK_packssdw, MCK_Mem, MCK_FR32 } },
- { X86::MMX_PACKSSWBrr, Convert_Reg1_2_ImpReg1_1, { MCK_packsswb, MCK_VR64, MCK_VR64 } },
- { X86::PACKSSWBrr, Convert_Reg1_2_ImpReg1_1, { MCK_packsswb, MCK_FR32, MCK_FR32 } },
- { X86::MMX_PACKSSWBrm, Convert_Reg1_2_ImpMem5_1, { MCK_packsswb, MCK_Mem, MCK_VR64 } },
- { X86::PACKSSWBrm, Convert_Reg1_2_ImpMem5_1, { MCK_packsswb, MCK_Mem, MCK_FR32 } },
- { X86::PACKUSDWrr, Convert_Reg1_2_ImpReg1_1, { MCK_packusdw, MCK_FR32, MCK_FR32 } },
- { X86::PACKUSDWrm, Convert_Reg1_2_ImpMem5_1, { MCK_packusdw, MCK_Mem, MCK_FR32 } },
- { X86::MMX_PACKUSWBrr, Convert_Reg1_2_ImpReg1_1, { MCK_packuswb, MCK_VR64, MCK_VR64 } },
- { X86::PACKUSWBrr, Convert_Reg1_2_ImpReg1_1, { MCK_packuswb, MCK_FR32, MCK_FR32 } },
- { X86::MMX_PACKUSWBrm, Convert_Reg1_2_ImpMem5_1, { MCK_packuswb, MCK_Mem, MCK_VR64 } },
- { X86::PACKUSWBrm, Convert_Reg1_2_ImpMem5_1, { MCK_packuswb, MCK_Mem, MCK_FR32 } },
- { X86::MMX_PADDBrr, Convert_Reg1_2_ImpReg1_1, { MCK_paddb, MCK_VR64, MCK_VR64 } },
- { X86::PADDBrr, Convert_Reg1_2_ImpReg1_1, { MCK_paddb, MCK_FR32, MCK_FR32 } },
- { X86::MMX_PADDBrm, Convert_Reg1_2_ImpMem5_1, { MCK_paddb, MCK_Mem, MCK_VR64 } },
- { X86::PADDBrm, Convert_Reg1_2_ImpMem5_1, { MCK_paddb, MCK_Mem, MCK_FR32 } },
- { X86::MMX_PADDDrr, Convert_Reg1_2_ImpReg1_1, { MCK_paddd, MCK_VR64, MCK_VR64 } },
- { X86::PADDDrr, Convert_Reg1_2_ImpReg1_1, { MCK_paddd, MCK_FR32, MCK_FR32 } },
- { X86::MMX_PADDDrm, Convert_Reg1_2_ImpMem5_1, { MCK_paddd, MCK_Mem, MCK_VR64 } },
- { X86::PADDDrm, Convert_Reg1_2_ImpMem5_1, { MCK_paddd, MCK_Mem, MCK_FR32 } },
- { X86::MMX_PADDQrr, Convert_Reg1_2_ImpReg1_1, { MCK_paddq, MCK_VR64, MCK_VR64 } },
- { X86::PADDQrr, Convert_Reg1_2_ImpReg1_1, { MCK_paddq, MCK_FR32, MCK_FR32 } },
- { X86::MMX_PADDQrm, Convert_Reg1_2_ImpMem5_1, { MCK_paddq, MCK_Mem, MCK_VR64 } },
- { X86::PADDQrm, Convert_Reg1_2_ImpMem5_1, { MCK_paddq, MCK_Mem, MCK_FR32 } },
- { X86::MMX_PADDSBrr, Convert_Reg1_2_ImpReg1_1, { MCK_paddsb, MCK_VR64, MCK_VR64 } },
- { X86::PADDSBrr, Convert_Reg1_2_ImpReg1_1, { MCK_paddsb, MCK_FR32, MCK_FR32 } },
- { X86::MMX_PADDSBrm, Convert_Reg1_2_ImpMem5_1, { MCK_paddsb, MCK_Mem, MCK_VR64 } },
- { X86::PADDSBrm, Convert_Reg1_2_ImpMem5_1, { MCK_paddsb, MCK_Mem, MCK_FR32 } },
- { X86::MMX_PADDSWrr, Convert_Reg1_2_ImpReg1_1, { MCK_paddsw, MCK_VR64, MCK_VR64 } },
- { X86::PADDSWrr, Convert_Reg1_2_ImpReg1_1, { MCK_paddsw, MCK_FR32, MCK_FR32 } },
- { X86::MMX_PADDSWrm, Convert_Reg1_2_ImpMem5_1, { MCK_paddsw, MCK_Mem, MCK_VR64 } },
- { X86::PADDSWrm, Convert_Reg1_2_ImpMem5_1, { MCK_paddsw, MCK_Mem, MCK_FR32 } },
- { X86::MMX_PADDUSBrr, Convert_Reg1_2_ImpReg1_1, { MCK_paddusb, MCK_VR64, MCK_VR64 } },
- { X86::PADDUSBrr, Convert_Reg1_2_ImpReg1_1, { MCK_paddusb, MCK_FR32, MCK_FR32 } },
- { X86::MMX_PADDUSBrm, Convert_Reg1_2_ImpMem5_1, { MCK_paddusb, MCK_Mem, MCK_VR64 } },
- { X86::PADDUSBrm, Convert_Reg1_2_ImpMem5_1, { MCK_paddusb, MCK_Mem, MCK_FR32 } },
- { X86::MMX_PADDUSWrr, Convert_Reg1_2_ImpReg1_1, { MCK_paddusw, MCK_VR64, MCK_VR64 } },
- { X86::PADDUSWrr, Convert_Reg1_2_ImpReg1_1, { MCK_paddusw, MCK_FR32, MCK_FR32 } },
- { X86::MMX_PADDUSWrm, Convert_Reg1_2_ImpMem5_1, { MCK_paddusw, MCK_Mem, MCK_VR64 } },
- { X86::PADDUSWrm, Convert_Reg1_2_ImpMem5_1, { MCK_paddusw, MCK_Mem, MCK_FR32 } },
- { X86::MMX_PADDWrr, Convert_Reg1_2_ImpReg1_1, { MCK_paddw, MCK_VR64, MCK_VR64 } },
- { X86::PADDWrr, Convert_Reg1_2_ImpReg1_1, { MCK_paddw, MCK_FR32, MCK_FR32 } },
- { X86::MMX_PADDWrm, Convert_Reg1_2_ImpMem5_1, { MCK_paddw, MCK_Mem, MCK_VR64 } },
- { X86::PADDWrm, Convert_Reg1_2_ImpMem5_1, { MCK_paddw, MCK_Mem, MCK_FR32 } },
- { X86::MMX_PANDrr, Convert_Reg1_2_ImpReg1_1, { MCK_pand, MCK_VR64, MCK_VR64 } },
- { X86::PANDrr, Convert_Reg1_2_ImpReg1_1, { MCK_pand, MCK_FR32, MCK_FR32 } },
- { X86::MMX_PANDrm, Convert_Reg1_2_ImpMem5_1, { MCK_pand, MCK_Mem, MCK_VR64 } },
- { X86::PANDrm, Convert_Reg1_2_ImpMem5_1, { MCK_pand, MCK_Mem, MCK_FR32 } },
- { X86::MMX_PANDNrr, Convert_Reg1_2_ImpReg1_1, { MCK_pandn, MCK_VR64, MCK_VR64 } },
- { X86::PANDNrr, Convert_Reg1_2_ImpReg1_1, { MCK_pandn, MCK_FR32, MCK_FR32 } },
- { X86::MMX_PANDNrm, Convert_Reg1_2_ImpMem5_1, { MCK_pandn, MCK_Mem, MCK_VR64 } },
- { X86::PANDNrm, Convert_Reg1_2_ImpMem5_1, { MCK_pandn, MCK_Mem, MCK_FR32 } },
- { X86::MMX_PAVGBrr, Convert_Reg1_2_ImpReg1_1, { MCK_pavgb, MCK_VR64, MCK_VR64 } },
- { X86::PAVGBrr, Convert_Reg1_2_ImpReg1_1, { MCK_pavgb, MCK_FR32, MCK_FR32 } },
- { X86::MMX_PAVGBrm, Convert_Reg1_2_ImpMem5_1, { MCK_pavgb, MCK_Mem, MCK_VR64 } },
- { X86::PAVGBrm, Convert_Reg1_2_ImpMem5_1, { MCK_pavgb, MCK_Mem, MCK_FR32 } },
- { X86::MMX_PAVGWrr, Convert_Reg1_2_ImpReg1_1, { MCK_pavgw, MCK_VR64, MCK_VR64 } },
- { X86::PAVGWrr, Convert_Reg1_2_ImpReg1_1, { MCK_pavgw, MCK_FR32, MCK_FR32 } },
- { X86::MMX_PAVGWrm, Convert_Reg1_2_ImpMem5_1, { MCK_pavgw, MCK_Mem, MCK_VR64 } },
- { X86::PAVGWrm, Convert_Reg1_2_ImpMem5_1, { MCK_pavgw, MCK_Mem, MCK_FR32 } },
- { X86::MMX_PCMPEQBrr, Convert_Reg1_2_ImpReg1_1, { MCK_pcmpeqb, MCK_VR64, MCK_VR64 } },
- { X86::PCMPEQBrr, Convert_Reg1_2_ImpReg1_1, { MCK_pcmpeqb, MCK_FR32, MCK_FR32 } },
- { X86::MMX_PCMPEQBrm, Convert_Reg1_2_ImpMem5_1, { MCK_pcmpeqb, MCK_Mem, MCK_VR64 } },
- { X86::PCMPEQBrm, Convert_Reg1_2_ImpMem5_1, { MCK_pcmpeqb, MCK_Mem, MCK_FR32 } },
- { X86::MMX_PCMPEQDrr, Convert_Reg1_2_ImpReg1_1, { MCK_pcmpeqd, MCK_VR64, MCK_VR64 } },
- { X86::PCMPEQDrr, Convert_Reg1_2_ImpReg1_1, { MCK_pcmpeqd, MCK_FR32, MCK_FR32 } },
- { X86::MMX_PCMPEQDrm, Convert_Reg1_2_ImpMem5_1, { MCK_pcmpeqd, MCK_Mem, MCK_VR64 } },
- { X86::PCMPEQDrm, Convert_Reg1_2_ImpMem5_1, { MCK_pcmpeqd, MCK_Mem, MCK_FR32 } },
- { X86::PCMPEQQrr, Convert_Reg1_2_ImpReg1_1, { MCK_pcmpeqq, MCK_FR32, MCK_FR32 } },
- { X86::PCMPEQQrm, Convert_Reg1_2_ImpMem5_1, { MCK_pcmpeqq, MCK_Mem, MCK_FR32 } },
- { X86::MMX_PCMPEQWrr, Convert_Reg1_2_ImpReg1_1, { MCK_pcmpeqw, MCK_VR64, MCK_VR64 } },
- { X86::PCMPEQWrr, Convert_Reg1_2_ImpReg1_1, { MCK_pcmpeqw, MCK_FR32, MCK_FR32 } },
- { X86::MMX_PCMPEQWrm, Convert_Reg1_2_ImpMem5_1, { MCK_pcmpeqw, MCK_Mem, MCK_VR64 } },
- { X86::PCMPEQWrm, Convert_Reg1_2_ImpMem5_1, { MCK_pcmpeqw, MCK_Mem, MCK_FR32 } },
- { X86::MMX_PCMPGTBrr, Convert_Reg1_2_ImpReg1_1, { MCK_pcmpgtb, MCK_VR64, MCK_VR64 } },
- { X86::PCMPGTBrr, Convert_Reg1_2_ImpReg1_1, { MCK_pcmpgtb, MCK_FR32, MCK_FR32 } },
- { X86::MMX_PCMPGTBrm, Convert_Reg1_2_ImpMem5_1, { MCK_pcmpgtb, MCK_Mem, MCK_VR64 } },
- { X86::PCMPGTBrm, Convert_Reg1_2_ImpMem5_1, { MCK_pcmpgtb, MCK_Mem, MCK_FR32 } },
- { X86::MMX_PCMPGTDrr, Convert_Reg1_2_ImpReg1_1, { MCK_pcmpgtd, MCK_VR64, MCK_VR64 } },
- { X86::PCMPGTDrr, Convert_Reg1_2_ImpReg1_1, { MCK_pcmpgtd, MCK_FR32, MCK_FR32 } },
- { X86::MMX_PCMPGTDrm, Convert_Reg1_2_ImpMem5_1, { MCK_pcmpgtd, MCK_Mem, MCK_VR64 } },
- { X86::PCMPGTDrm, Convert_Reg1_2_ImpMem5_1, { MCK_pcmpgtd, MCK_Mem, MCK_FR32 } },
- { X86::PCMPGTQrr, Convert_Reg1_2_ImpReg1_1, { MCK_pcmpgtq, MCK_FR32, MCK_FR32 } },
- { X86::PCMPGTQrm, Convert_Reg1_2_ImpMem5_1, { MCK_pcmpgtq, MCK_Mem, MCK_FR32 } },
- { X86::MMX_PCMPGTWrr, Convert_Reg1_2_ImpReg1_1, { MCK_pcmpgtw, MCK_VR64, MCK_VR64 } },
- { X86::PCMPGTWrr, Convert_Reg1_2_ImpReg1_1, { MCK_pcmpgtw, MCK_FR32, MCK_FR32 } },
- { X86::MMX_PCMPGTWrm, Convert_Reg1_2_ImpMem5_1, { MCK_pcmpgtw, MCK_Mem, MCK_VR64 } },
- { X86::PCMPGTWrm, Convert_Reg1_2_ImpMem5_1, { MCK_pcmpgtw, MCK_Mem, MCK_FR32 } },
- { X86::PHADDDrr64, Convert_Reg1_2_ImpReg1_1, { MCK_phaddd, MCK_VR64, MCK_VR64 } },
- { X86::PHADDDrr128, Convert_Reg1_2_ImpReg1_1, { MCK_phaddd, MCK_FR32, MCK_FR32 } },
- { X86::PHADDDrm64, Convert_Reg1_2_ImpMem5_1, { MCK_phaddd, MCK_Mem, MCK_VR64 } },
- { X86::PHADDDrm128, Convert_Reg1_2_ImpMem5_1, { MCK_phaddd, MCK_Mem, MCK_FR32 } },
- { X86::PHADDSWrr64, Convert_Reg1_2_ImpReg1_1, { MCK_phaddsw, MCK_VR64, MCK_VR64 } },
- { X86::PHADDSWrr128, Convert_Reg1_2_ImpReg1_1, { MCK_phaddsw, MCK_FR32, MCK_FR32 } },
- { X86::PHADDSWrm64, Convert_Reg1_2_ImpMem5_1, { MCK_phaddsw, MCK_Mem, MCK_VR64 } },
- { X86::PHADDSWrm128, Convert_Reg1_2_ImpMem5_1, { MCK_phaddsw, MCK_Mem, MCK_FR32 } },
- { X86::PHADDWrr64, Convert_Reg1_2_ImpReg1_1, { MCK_phaddw, MCK_VR64, MCK_VR64 } },
- { X86::PHADDWrr128, Convert_Reg1_2_ImpReg1_1, { MCK_phaddw, MCK_FR32, MCK_FR32 } },
- { X86::PHADDWrm64, Convert_Reg1_2_ImpMem5_1, { MCK_phaddw, MCK_Mem, MCK_VR64 } },
- { X86::PHADDWrm128, Convert_Reg1_2_ImpMem5_1, { MCK_phaddw, MCK_Mem, MCK_FR32 } },
- { X86::PHMINPOSUWrr128, Convert_Reg1_2_Reg1_1, { MCK_phminposuw, MCK_FR32, MCK_FR32 } },
- { X86::PHMINPOSUWrm128, Convert_Reg1_2_Mem5_1, { MCK_phminposuw, MCK_Mem, MCK_FR32 } },
- { X86::PHSUBDrr64, Convert_Reg1_2_ImpReg1_1, { MCK_phsubd, MCK_VR64, MCK_VR64 } },
- { X86::PHSUBDrr128, Convert_Reg1_2_ImpReg1_1, { MCK_phsubd, MCK_FR32, MCK_FR32 } },
- { X86::PHSUBDrm64, Convert_Reg1_2_ImpMem5_1, { MCK_phsubd, MCK_Mem, MCK_VR64 } },
- { X86::PHSUBDrm128, Convert_Reg1_2_ImpMem5_1, { MCK_phsubd, MCK_Mem, MCK_FR32 } },
- { X86::PHSUBSWrr64, Convert_Reg1_2_ImpReg1_1, { MCK_phsubsw, MCK_VR64, MCK_VR64 } },
- { X86::PHSUBSWrr128, Convert_Reg1_2_ImpReg1_1, { MCK_phsubsw, MCK_FR32, MCK_FR32 } },
- { X86::PHSUBSWrm64, Convert_Reg1_2_ImpMem5_1, { MCK_phsubsw, MCK_Mem, MCK_VR64 } },
- { X86::PHSUBSWrm128, Convert_Reg1_2_ImpMem5_1, { MCK_phsubsw, MCK_Mem, MCK_FR32 } },
- { X86::PHSUBWrr64, Convert_Reg1_2_ImpReg1_1, { MCK_phsubw, MCK_VR64, MCK_VR64 } },
- { X86::PHSUBWrr128, Convert_Reg1_2_ImpReg1_1, { MCK_phsubw, MCK_FR32, MCK_FR32 } },
- { X86::PHSUBWrm64, Convert_Reg1_2_ImpMem5_1, { MCK_phsubw, MCK_Mem, MCK_VR64 } },
- { X86::PHSUBWrm128, Convert_Reg1_2_ImpMem5_1, { MCK_phsubw, MCK_Mem, MCK_FR32 } },
- { X86::PMADDUBSWrr64, Convert_Reg1_2_ImpReg1_1, { MCK_pmaddubsw, MCK_VR64, MCK_VR64 } },
- { X86::PMADDUBSWrr128, Convert_Reg1_2_ImpReg1_1, { MCK_pmaddubsw, MCK_FR32, MCK_FR32 } },
- { X86::PMADDUBSWrm64, Convert_Reg1_2_ImpMem5_1, { MCK_pmaddubsw, MCK_Mem, MCK_VR64 } },
- { X86::PMADDUBSWrm128, Convert_Reg1_2_ImpMem5_1, { MCK_pmaddubsw, MCK_Mem, MCK_FR32 } },
- { X86::MMX_PMADDWDrr, Convert_Reg1_2_ImpReg1_1, { MCK_pmaddwd, MCK_VR64, MCK_VR64 } },
- { X86::PMADDWDrr, Convert_Reg1_2_ImpReg1_1, { MCK_pmaddwd, MCK_FR32, MCK_FR32 } },
- { X86::MMX_PMADDWDrm, Convert_Reg1_2_ImpMem5_1, { MCK_pmaddwd, MCK_Mem, MCK_VR64 } },
- { X86::PMADDWDrm, Convert_Reg1_2_ImpMem5_1, { MCK_pmaddwd, MCK_Mem, MCK_FR32 } },
- { X86::PMAXSBrr, Convert_Reg1_2_ImpReg1_1, { MCK_pmaxsb, MCK_FR32, MCK_FR32 } },
- { X86::PMAXSBrm, Convert_Reg1_2_ImpMem5_1, { MCK_pmaxsb, MCK_Mem, MCK_FR32 } },
- { X86::PMAXSDrr, Convert_Reg1_2_ImpReg1_1, { MCK_pmaxsd, MCK_FR32, MCK_FR32 } },
- { X86::PMAXSDrm, Convert_Reg1_2_ImpMem5_1, { MCK_pmaxsd, MCK_Mem, MCK_FR32 } },
- { X86::MMX_PMAXSWrr, Convert_Reg1_2_ImpReg1_1, { MCK_pmaxsw, MCK_VR64, MCK_VR64 } },
- { X86::PMAXSWrr, Convert_Reg1_2_ImpReg1_1, { MCK_pmaxsw, MCK_FR32, MCK_FR32 } },
- { X86::MMX_PMAXSWrm, Convert_Reg1_2_ImpMem5_1, { MCK_pmaxsw, MCK_Mem, MCK_VR64 } },
- { X86::PMAXSWrm, Convert_Reg1_2_ImpMem5_1, { MCK_pmaxsw, MCK_Mem, MCK_FR32 } },
- { X86::MMX_PMAXUBrr, Convert_Reg1_2_ImpReg1_1, { MCK_pmaxub, MCK_VR64, MCK_VR64 } },
- { X86::PMAXUBrr, Convert_Reg1_2_ImpReg1_1, { MCK_pmaxub, MCK_FR32, MCK_FR32 } },
- { X86::MMX_PMAXUBrm, Convert_Reg1_2_ImpMem5_1, { MCK_pmaxub, MCK_Mem, MCK_VR64 } },
- { X86::PMAXUBrm, Convert_Reg1_2_ImpMem5_1, { MCK_pmaxub, MCK_Mem, MCK_FR32 } },
- { X86::PMAXUDrr, Convert_Reg1_2_ImpReg1_1, { MCK_pmaxud, MCK_FR32, MCK_FR32 } },
- { X86::PMAXUDrm, Convert_Reg1_2_ImpMem5_1, { MCK_pmaxud, MCK_Mem, MCK_FR32 } },
- { X86::PMAXUWrr, Convert_Reg1_2_ImpReg1_1, { MCK_pmaxuw, MCK_FR32, MCK_FR32 } },
- { X86::PMAXUWrm, Convert_Reg1_2_ImpMem5_1, { MCK_pmaxuw, MCK_Mem, MCK_FR32 } },
- { X86::PMINSBrr, Convert_Reg1_2_ImpReg1_1, { MCK_pminsb, MCK_FR32, MCK_FR32 } },
- { X86::PMINSBrm, Convert_Reg1_2_ImpMem5_1, { MCK_pminsb, MCK_Mem, MCK_FR32 } },
- { X86::PMINSDrr, Convert_Reg1_2_ImpReg1_1, { MCK_pminsd, MCK_FR32, MCK_FR32 } },
- { X86::PMINSDrm, Convert_Reg1_2_ImpMem5_1, { MCK_pminsd, MCK_Mem, MCK_FR32 } },
- { X86::MMX_PMINSWrr, Convert_Reg1_2_ImpReg1_1, { MCK_pminsw, MCK_VR64, MCK_VR64 } },
- { X86::PMINSWrr, Convert_Reg1_2_ImpReg1_1, { MCK_pminsw, MCK_FR32, MCK_FR32 } },
- { X86::MMX_PMINSWrm, Convert_Reg1_2_ImpMem5_1, { MCK_pminsw, MCK_Mem, MCK_VR64 } },
- { X86::PMINSWrm, Convert_Reg1_2_ImpMem5_1, { MCK_pminsw, MCK_Mem, MCK_FR32 } },
- { X86::MMX_PMINUBrr, Convert_Reg1_2_ImpReg1_1, { MCK_pminub, MCK_VR64, MCK_VR64 } },
- { X86::PMINUBrr, Convert_Reg1_2_ImpReg1_1, { MCK_pminub, MCK_FR32, MCK_FR32 } },
- { X86::MMX_PMINUBrm, Convert_Reg1_2_ImpMem5_1, { MCK_pminub, MCK_Mem, MCK_VR64 } },
- { X86::PMINUBrm, Convert_Reg1_2_ImpMem5_1, { MCK_pminub, MCK_Mem, MCK_FR32 } },
- { X86::PMINUDrr, Convert_Reg1_2_ImpReg1_1, { MCK_pminud, MCK_FR32, MCK_FR32 } },
- { X86::PMINUDrm, Convert_Reg1_2_ImpMem5_1, { MCK_pminud, MCK_Mem, MCK_FR32 } },
- { X86::PMINUWrr, Convert_Reg1_2_ImpReg1_1, { MCK_pminuw, MCK_FR32, MCK_FR32 } },
- { X86::PMINUWrm, Convert_Reg1_2_ImpMem5_1, { MCK_pminuw, MCK_Mem, MCK_FR32 } },
- { X86::MMX_PMOVMSKBrr, Convert_Reg1_2_Reg1_1, { MCK_pmovmskb, MCK_VR64, MCK_GR32 } },
- { X86::PMOVMSKBrr, Convert_Reg1_2_Reg1_1, { MCK_pmovmskb, MCK_FR32, MCK_GR32 } },
- { X86::PMOVSXBDrr, Convert_Reg1_2_Reg1_1, { MCK_pmovsxbd, MCK_FR32, MCK_FR32 } },
- { X86::PMOVSXBDrm, Convert_Reg1_2_Mem5_1, { MCK_pmovsxbd, MCK_Mem, MCK_FR32 } },
- { X86::PMOVSXBQrr, Convert_Reg1_2_Reg1_1, { MCK_pmovsxbq, MCK_FR32, MCK_FR32 } },
- { X86::PMOVSXBQrm, Convert_Reg1_2_Mem5_1, { MCK_pmovsxbq, MCK_Mem, MCK_FR32 } },
- { X86::PMOVSXBWrr, Convert_Reg1_2_Reg1_1, { MCK_pmovsxbw, MCK_FR32, MCK_FR32 } },
- { X86::PMOVSXBWrm, Convert_Reg1_2_Mem5_1, { MCK_pmovsxbw, MCK_Mem, MCK_FR32 } },
- { X86::PMOVSXDQrr, Convert_Reg1_2_Reg1_1, { MCK_pmovsxdq, MCK_FR32, MCK_FR32 } },
- { X86::PMOVSXDQrm, Convert_Reg1_2_Mem5_1, { MCK_pmovsxdq, MCK_Mem, MCK_FR32 } },
- { X86::PMOVSXWDrr, Convert_Reg1_2_Reg1_1, { MCK_pmovsxwd, MCK_FR32, MCK_FR32 } },
- { X86::PMOVSXWDrm, Convert_Reg1_2_Mem5_1, { MCK_pmovsxwd, MCK_Mem, MCK_FR32 } },
- { X86::PMOVSXWQrr, Convert_Reg1_2_Reg1_1, { MCK_pmovsxwq, MCK_FR32, MCK_FR32 } },
- { X86::PMOVSXWQrm, Convert_Reg1_2_Mem5_1, { MCK_pmovsxwq, MCK_Mem, MCK_FR32 } },
- { X86::PMOVZXBDrr, Convert_Reg1_2_Reg1_1, { MCK_pmovzxbd, MCK_FR32, MCK_FR32 } },
- { X86::PMOVZXBDrm, Convert_Reg1_2_Mem5_1, { MCK_pmovzxbd, MCK_Mem, MCK_FR32 } },
- { X86::PMOVZXBQrr, Convert_Reg1_2_Reg1_1, { MCK_pmovzxbq, MCK_FR32, MCK_FR32 } },
- { X86::PMOVZXBQrm, Convert_Reg1_2_Mem5_1, { MCK_pmovzxbq, MCK_Mem, MCK_FR32 } },
- { X86::PMOVZXBWrr, Convert_Reg1_2_Reg1_1, { MCK_pmovzxbw, MCK_FR32, MCK_FR32 } },
- { X86::PMOVZXBWrm, Convert_Reg1_2_Mem5_1, { MCK_pmovzxbw, MCK_Mem, MCK_FR32 } },
- { X86::PMOVZXDQrr, Convert_Reg1_2_Reg1_1, { MCK_pmovzxdq, MCK_FR32, MCK_FR32 } },
- { X86::PMOVZXDQrm, Convert_Reg1_2_Mem5_1, { MCK_pmovzxdq, MCK_Mem, MCK_FR32 } },
- { X86::PMOVZXWDrr, Convert_Reg1_2_Reg1_1, { MCK_pmovzxwd, MCK_FR32, MCK_FR32 } },
- { X86::PMOVZXWDrm, Convert_Reg1_2_Mem5_1, { MCK_pmovzxwd, MCK_Mem, MCK_FR32 } },
- { X86::PMOVZXWQrr, Convert_Reg1_2_Reg1_1, { MCK_pmovzxwq, MCK_FR32, MCK_FR32 } },
- { X86::PMOVZXWQrm, Convert_Reg1_2_Mem5_1, { MCK_pmovzxwq, MCK_Mem, MCK_FR32 } },
- { X86::PMULDQrr, Convert_Reg1_2_ImpReg1_1, { MCK_pmuldq, MCK_FR32, MCK_FR32 } },
- { X86::PMULDQrm, Convert_Reg1_2_ImpMem5_1, { MCK_pmuldq, MCK_Mem, MCK_FR32 } },
- { X86::PMULHRSWrr64, Convert_Reg1_2_ImpReg1_1, { MCK_pmulhrsw, MCK_VR64, MCK_VR64 } },
- { X86::PMULHRSWrr128, Convert_Reg1_2_ImpReg1_1, { MCK_pmulhrsw, MCK_FR32, MCK_FR32 } },
- { X86::PMULHRSWrm64, Convert_Reg1_2_ImpMem5_1, { MCK_pmulhrsw, MCK_Mem, MCK_VR64 } },
- { X86::PMULHRSWrm128, Convert_Reg1_2_ImpMem5_1, { MCK_pmulhrsw, MCK_Mem, MCK_FR32 } },
- { X86::MMX_PMULHUWrr, Convert_Reg1_2_ImpReg1_1, { MCK_pmulhuw, MCK_VR64, MCK_VR64 } },
- { X86::PMULHUWrr, Convert_Reg1_2_ImpReg1_1, { MCK_pmulhuw, MCK_FR32, MCK_FR32 } },
- { X86::MMX_PMULHUWrm, Convert_Reg1_2_ImpMem5_1, { MCK_pmulhuw, MCK_Mem, MCK_VR64 } },
- { X86::PMULHUWrm, Convert_Reg1_2_ImpMem5_1, { MCK_pmulhuw, MCK_Mem, MCK_FR32 } },
- { X86::MMX_PMULHWrr, Convert_Reg1_2_ImpReg1_1, { MCK_pmulhw, MCK_VR64, MCK_VR64 } },
- { X86::PMULHWrr, Convert_Reg1_2_ImpReg1_1, { MCK_pmulhw, MCK_FR32, MCK_FR32 } },
- { X86::MMX_PMULHWrm, Convert_Reg1_2_ImpMem5_1, { MCK_pmulhw, MCK_Mem, MCK_VR64 } },
- { X86::PMULHWrm, Convert_Reg1_2_ImpMem5_1, { MCK_pmulhw, MCK_Mem, MCK_FR32 } },
- { X86::PMULLDrr, Convert_Reg1_2_ImpReg1_1, { MCK_pmulld, MCK_FR32, MCK_FR32 } },
- { X86::PMULLDrr_int, Convert_Reg1_2_ImpReg1_1, { MCK_pmulld, MCK_FR32, MCK_FR32 } },
- { X86::PMULLDrm, Convert_Reg1_2_ImpMem5_1, { MCK_pmulld, MCK_Mem, MCK_FR32 } },
- { X86::PMULLDrm_int, Convert_Reg1_2_ImpMem5_1, { MCK_pmulld, MCK_Mem, MCK_FR32 } },
- { X86::MMX_PMULLWrr, Convert_Reg1_2_ImpReg1_1, { MCK_pmullw, MCK_VR64, MCK_VR64 } },
- { X86::PMULLWrr, Convert_Reg1_2_ImpReg1_1, { MCK_pmullw, MCK_FR32, MCK_FR32 } },
- { X86::MMX_PMULLWrm, Convert_Reg1_2_ImpMem5_1, { MCK_pmullw, MCK_Mem, MCK_VR64 } },
- { X86::PMULLWrm, Convert_Reg1_2_ImpMem5_1, { MCK_pmullw, MCK_Mem, MCK_FR32 } },
- { X86::MMX_PMULUDQrr, Convert_Reg1_2_ImpReg1_1, { MCK_pmuludq, MCK_VR64, MCK_VR64 } },
- { X86::PMULUDQrr, Convert_Reg1_2_ImpReg1_1, { MCK_pmuludq, MCK_FR32, MCK_FR32 } },
- { X86::MMX_PMULUDQrm, Convert_Reg1_2_ImpMem5_1, { MCK_pmuludq, MCK_Mem, MCK_VR64 } },
- { X86::PMULUDQrm, Convert_Reg1_2_ImpMem5_1, { MCK_pmuludq, MCK_Mem, MCK_FR32 } },
- { X86::POPCNT32rr, Convert_Reg1_2_Reg1_1, { MCK_popcntl, MCK_GR32, MCK_GR32 } },
- { X86::POPCNT32rm, Convert_Reg1_2_Mem5_1, { MCK_popcntl, MCK_Mem, MCK_GR32 } },
- { X86::POPCNT64rr, Convert_Reg1_2_Reg1_1, { MCK_popcntq, MCK_GR64, MCK_GR64 } },
- { X86::POPCNT64rm, Convert_Reg1_2_Mem5_1, { MCK_popcntq, MCK_Mem, MCK_GR64 } },
- { X86::POPCNT16rr, Convert_Reg1_2_Reg1_1, { MCK_popcntw, MCK_GR16, MCK_GR16 } },
- { X86::POPCNT16rm, Convert_Reg1_2_Mem5_1, { MCK_popcntw, MCK_Mem, MCK_GR16 } },
- { X86::MMX_PORrr, Convert_Reg1_2_ImpReg1_1, { MCK_por, MCK_VR64, MCK_VR64 } },
- { X86::PORrr, Convert_Reg1_2_ImpReg1_1, { MCK_por, MCK_FR32, MCK_FR32 } },
- { X86::MMX_PORrm, Convert_Reg1_2_ImpMem5_1, { MCK_por, MCK_Mem, MCK_VR64 } },
- { X86::PORrm, Convert_Reg1_2_ImpMem5_1, { MCK_por, MCK_Mem, MCK_FR32 } },
- { X86::MMX_PSADBWrr, Convert_Reg1_2_ImpReg1_1, { MCK_psadbw, MCK_VR64, MCK_VR64 } },
- { X86::PSADBWrr, Convert_Reg1_2_ImpReg1_1, { MCK_psadbw, MCK_FR32, MCK_FR32 } },
- { X86::MMX_PSADBWrm, Convert_Reg1_2_ImpMem5_1, { MCK_psadbw, MCK_Mem, MCK_VR64 } },
- { X86::PSADBWrm, Convert_Reg1_2_ImpMem5_1, { MCK_psadbw, MCK_Mem, MCK_FR32 } },
- { X86::PSHUFBrr64, Convert_Reg1_2_ImpReg1_1, { MCK_pshufb, MCK_VR64, MCK_VR64 } },
- { X86::PSHUFBrr128, Convert_Reg1_2_ImpReg1_1, { MCK_pshufb, MCK_FR32, MCK_FR32 } },
- { X86::PSHUFBrm64, Convert_Reg1_2_ImpMem5_1, { MCK_pshufb, MCK_Mem, MCK_VR64 } },
- { X86::PSHUFBrm128, Convert_Reg1_2_ImpMem5_1, { MCK_pshufb, MCK_Mem, MCK_FR32 } },
- { X86::PSIGNBrr64, Convert_Reg1_2_ImpReg1_1, { MCK_psignb, MCK_VR64, MCK_VR64 } },
- { X86::PSIGNBrr128, Convert_Reg1_2_ImpReg1_1, { MCK_psignb, MCK_FR32, MCK_FR32 } },
- { X86::PSIGNBrm64, Convert_Reg1_2_ImpMem5_1, { MCK_psignb, MCK_Mem, MCK_VR64 } },
- { X86::PSIGNBrm128, Convert_Reg1_2_ImpMem5_1, { MCK_psignb, MCK_Mem, MCK_FR32 } },
- { X86::PSIGNDrr64, Convert_Reg1_2_ImpReg1_1, { MCK_psignd, MCK_VR64, MCK_VR64 } },
- { X86::PSIGNDrr128, Convert_Reg1_2_ImpReg1_1, { MCK_psignd, MCK_FR32, MCK_FR32 } },
- { X86::PSIGNDrm64, Convert_Reg1_2_ImpMem5_1, { MCK_psignd, MCK_Mem, MCK_VR64 } },
- { X86::PSIGNDrm128, Convert_Reg1_2_ImpMem5_1, { MCK_psignd, MCK_Mem, MCK_FR32 } },
- { X86::PSIGNWrr64, Convert_Reg1_2_ImpReg1_1, { MCK_psignw, MCK_VR64, MCK_VR64 } },
- { X86::PSIGNWrr128, Convert_Reg1_2_ImpReg1_1, { MCK_psignw, MCK_FR32, MCK_FR32 } },
- { X86::PSIGNWrm64, Convert_Reg1_2_ImpMem5_1, { MCK_psignw, MCK_Mem, MCK_VR64 } },
- { X86::PSIGNWrm128, Convert_Reg1_2_ImpMem5_1, { MCK_psignw, MCK_Mem, MCK_FR32 } },
- { X86::MMX_PSLLDrr, Convert_Reg1_2_ImpReg1_1, { MCK_pslld, MCK_VR64, MCK_VR64 } },
- { X86::PSLLDrr, Convert_Reg1_2_ImpReg1_1, { MCK_pslld, MCK_FR32, MCK_FR32 } },
- { X86::MMX_PSLLDri, Convert_Reg1_2_ImpImmSExt81_1, { MCK_pslld, MCK_ImmSExt8, MCK_VR64 } },
- { X86::PSLLDri, Convert_Reg1_2_ImpImmSExt81_1, { MCK_pslld, MCK_ImmSExt8, MCK_FR32 } },
- { X86::MMX_PSLLDrm, Convert_Reg1_2_ImpMem5_1, { MCK_pslld, MCK_Mem, MCK_VR64 } },
- { X86::PSLLDrm, Convert_Reg1_2_ImpMem5_1, { MCK_pslld, MCK_Mem, MCK_FR32 } },
- { X86::PSLLDQri, Convert_Reg1_2_ImpImmSExt81_1, { MCK_pslldq, MCK_ImmSExt8, MCK_FR32 } },
- { X86::MMX_PSLLQrr, Convert_Reg1_2_ImpReg1_1, { MCK_psllq, MCK_VR64, MCK_VR64 } },
- { X86::PSLLQrr, Convert_Reg1_2_ImpReg1_1, { MCK_psllq, MCK_FR32, MCK_FR32 } },
- { X86::MMX_PSLLQri, Convert_Reg1_2_ImpImmSExt81_1, { MCK_psllq, MCK_ImmSExt8, MCK_VR64 } },
- { X86::PSLLQri, Convert_Reg1_2_ImpImmSExt81_1, { MCK_psllq, MCK_ImmSExt8, MCK_FR32 } },
- { X86::MMX_PSLLQrm, Convert_Reg1_2_ImpMem5_1, { MCK_psllq, MCK_Mem, MCK_VR64 } },
- { X86::PSLLQrm, Convert_Reg1_2_ImpMem5_1, { MCK_psllq, MCK_Mem, MCK_FR32 } },
- { X86::MMX_PSLLWrr, Convert_Reg1_2_ImpReg1_1, { MCK_psllw, MCK_VR64, MCK_VR64 } },
- { X86::PSLLWrr, Convert_Reg1_2_ImpReg1_1, { MCK_psllw, MCK_FR32, MCK_FR32 } },
- { X86::MMX_PSLLWri, Convert_Reg1_2_ImpImmSExt81_1, { MCK_psllw, MCK_ImmSExt8, MCK_VR64 } },
- { X86::PSLLWri, Convert_Reg1_2_ImpImmSExt81_1, { MCK_psllw, MCK_ImmSExt8, MCK_FR32 } },
- { X86::MMX_PSLLWrm, Convert_Reg1_2_ImpMem5_1, { MCK_psllw, MCK_Mem, MCK_VR64 } },
- { X86::PSLLWrm, Convert_Reg1_2_ImpMem5_1, { MCK_psllw, MCK_Mem, MCK_FR32 } },
- { X86::MMX_PSRADrr, Convert_Reg1_2_ImpReg1_1, { MCK_psrad, MCK_VR64, MCK_VR64 } },
- { X86::PSRADrr, Convert_Reg1_2_ImpReg1_1, { MCK_psrad, MCK_FR32, MCK_FR32 } },
- { X86::MMX_PSRADri, Convert_Reg1_2_ImpImmSExt81_1, { MCK_psrad, MCK_ImmSExt8, MCK_VR64 } },
- { X86::PSRADri, Convert_Reg1_2_ImpImmSExt81_1, { MCK_psrad, MCK_ImmSExt8, MCK_FR32 } },
- { X86::MMX_PSRADrm, Convert_Reg1_2_ImpMem5_1, { MCK_psrad, MCK_Mem, MCK_VR64 } },
- { X86::PSRADrm, Convert_Reg1_2_ImpMem5_1, { MCK_psrad, MCK_Mem, MCK_FR32 } },
- { X86::MMX_PSRAWrr, Convert_Reg1_2_ImpReg1_1, { MCK_psraw, MCK_VR64, MCK_VR64 } },
- { X86::PSRAWrr, Convert_Reg1_2_ImpReg1_1, { MCK_psraw, MCK_FR32, MCK_FR32 } },
- { X86::MMX_PSRAWri, Convert_Reg1_2_ImpImmSExt81_1, { MCK_psraw, MCK_ImmSExt8, MCK_VR64 } },
- { X86::PSRAWri, Convert_Reg1_2_ImpImmSExt81_1, { MCK_psraw, MCK_ImmSExt8, MCK_FR32 } },
- { X86::MMX_PSRAWrm, Convert_Reg1_2_ImpMem5_1, { MCK_psraw, MCK_Mem, MCK_VR64 } },
- { X86::PSRAWrm, Convert_Reg1_2_ImpMem5_1, { MCK_psraw, MCK_Mem, MCK_FR32 } },
- { X86::MMX_PSRLDrr, Convert_Reg1_2_ImpReg1_1, { MCK_psrld, MCK_VR64, MCK_VR64 } },
- { X86::PSRLDrr, Convert_Reg1_2_ImpReg1_1, { MCK_psrld, MCK_FR32, MCK_FR32 } },
- { X86::MMX_PSRLDri, Convert_Reg1_2_ImpImmSExt81_1, { MCK_psrld, MCK_ImmSExt8, MCK_VR64 } },
- { X86::PSRLDri, Convert_Reg1_2_ImpImmSExt81_1, { MCK_psrld, MCK_ImmSExt8, MCK_FR32 } },
- { X86::MMX_PSRLDrm, Convert_Reg1_2_ImpMem5_1, { MCK_psrld, MCK_Mem, MCK_VR64 } },
- { X86::PSRLDrm, Convert_Reg1_2_ImpMem5_1, { MCK_psrld, MCK_Mem, MCK_FR32 } },
- { X86::PSRLDQri, Convert_Reg1_2_ImpImmSExt81_1, { MCK_psrldq, MCK_ImmSExt8, MCK_FR32 } },
- { X86::MMX_PSRLQrr, Convert_Reg1_2_ImpReg1_1, { MCK_psrlq, MCK_VR64, MCK_VR64 } },
- { X86::PSRLQrr, Convert_Reg1_2_ImpReg1_1, { MCK_psrlq, MCK_FR32, MCK_FR32 } },
- { X86::MMX_PSRLQri, Convert_Reg1_2_ImpImmSExt81_1, { MCK_psrlq, MCK_ImmSExt8, MCK_VR64 } },
- { X86::PSRLQri, Convert_Reg1_2_ImpImmSExt81_1, { MCK_psrlq, MCK_ImmSExt8, MCK_FR32 } },
- { X86::MMX_PSRLQrm, Convert_Reg1_2_ImpMem5_1, { MCK_psrlq, MCK_Mem, MCK_VR64 } },
- { X86::PSRLQrm, Convert_Reg1_2_ImpMem5_1, { MCK_psrlq, MCK_Mem, MCK_FR32 } },
- { X86::MMX_PSRLWrr, Convert_Reg1_2_ImpReg1_1, { MCK_psrlw, MCK_VR64, MCK_VR64 } },
- { X86::PSRLWrr, Convert_Reg1_2_ImpReg1_1, { MCK_psrlw, MCK_FR32, MCK_FR32 } },
- { X86::MMX_PSRLWri, Convert_Reg1_2_ImpImmSExt81_1, { MCK_psrlw, MCK_ImmSExt8, MCK_VR64 } },
- { X86::PSRLWri, Convert_Reg1_2_ImpImmSExt81_1, { MCK_psrlw, MCK_ImmSExt8, MCK_FR32 } },
- { X86::MMX_PSRLWrm, Convert_Reg1_2_ImpMem5_1, { MCK_psrlw, MCK_Mem, MCK_VR64 } },
- { X86::PSRLWrm, Convert_Reg1_2_ImpMem5_1, { MCK_psrlw, MCK_Mem, MCK_FR32 } },
- { X86::MMX_PSUBBrr, Convert_Reg1_2_ImpReg1_1, { MCK_psubb, MCK_VR64, MCK_VR64 } },
- { X86::PSUBBrr, Convert_Reg1_2_ImpReg1_1, { MCK_psubb, MCK_FR32, MCK_FR32 } },
- { X86::MMX_PSUBBrm, Convert_Reg1_2_ImpMem5_1, { MCK_psubb, MCK_Mem, MCK_VR64 } },
- { X86::PSUBBrm, Convert_Reg1_2_ImpMem5_1, { MCK_psubb, MCK_Mem, MCK_FR32 } },
- { X86::MMX_PSUBDrr, Convert_Reg1_2_ImpReg1_1, { MCK_psubd, MCK_VR64, MCK_VR64 } },
- { X86::PSUBDrr, Convert_Reg1_2_ImpReg1_1, { MCK_psubd, MCK_FR32, MCK_FR32 } },
- { X86::MMX_PSUBDrm, Convert_Reg1_2_ImpMem5_1, { MCK_psubd, MCK_Mem, MCK_VR64 } },
- { X86::PSUBDrm, Convert_Reg1_2_ImpMem5_1, { MCK_psubd, MCK_Mem, MCK_FR32 } },
- { X86::MMX_PSUBQrr, Convert_Reg1_2_ImpReg1_1, { MCK_psubq, MCK_VR64, MCK_VR64 } },
- { X86::PSUBQrr, Convert_Reg1_2_ImpReg1_1, { MCK_psubq, MCK_FR32, MCK_FR32 } },
- { X86::MMX_PSUBQrm, Convert_Reg1_2_ImpMem5_1, { MCK_psubq, MCK_Mem, MCK_VR64 } },
- { X86::PSUBQrm, Convert_Reg1_2_ImpMem5_1, { MCK_psubq, MCK_Mem, MCK_FR32 } },
- { X86::MMX_PSUBSBrr, Convert_Reg1_2_ImpReg1_1, { MCK_psubsb, MCK_VR64, MCK_VR64 } },
- { X86::PSUBSBrr, Convert_Reg1_2_ImpReg1_1, { MCK_psubsb, MCK_FR32, MCK_FR32 } },
- { X86::MMX_PSUBSBrm, Convert_Reg1_2_ImpMem5_1, { MCK_psubsb, MCK_Mem, MCK_VR64 } },
- { X86::PSUBSBrm, Convert_Reg1_2_ImpMem5_1, { MCK_psubsb, MCK_Mem, MCK_FR32 } },
- { X86::MMX_PSUBSWrr, Convert_Reg1_2_ImpReg1_1, { MCK_psubsw, MCK_VR64, MCK_VR64 } },
- { X86::PSUBSWrr, Convert_Reg1_2_ImpReg1_1, { MCK_psubsw, MCK_FR32, MCK_FR32 } },
- { X86::MMX_PSUBSWrm, Convert_Reg1_2_ImpMem5_1, { MCK_psubsw, MCK_Mem, MCK_VR64 } },
- { X86::PSUBSWrm, Convert_Reg1_2_ImpMem5_1, { MCK_psubsw, MCK_Mem, MCK_FR32 } },
- { X86::MMX_PSUBUSBrr, Convert_Reg1_2_ImpReg1_1, { MCK_psubusb, MCK_VR64, MCK_VR64 } },
- { X86::PSUBUSBrr, Convert_Reg1_2_ImpReg1_1, { MCK_psubusb, MCK_FR32, MCK_FR32 } },
- { X86::MMX_PSUBUSBrm, Convert_Reg1_2_ImpMem5_1, { MCK_psubusb, MCK_Mem, MCK_VR64 } },
- { X86::PSUBUSBrm, Convert_Reg1_2_ImpMem5_1, { MCK_psubusb, MCK_Mem, MCK_FR32 } },
- { X86::MMX_PSUBUSWrr, Convert_Reg1_2_ImpReg1_1, { MCK_psubusw, MCK_VR64, MCK_VR64 } },
- { X86::PSUBUSWrr, Convert_Reg1_2_ImpReg1_1, { MCK_psubusw, MCK_FR32, MCK_FR32 } },
- { X86::MMX_PSUBUSWrm, Convert_Reg1_2_ImpMem5_1, { MCK_psubusw, MCK_Mem, MCK_VR64 } },
- { X86::PSUBUSWrm, Convert_Reg1_2_ImpMem5_1, { MCK_psubusw, MCK_Mem, MCK_FR32 } },
- { X86::MMX_PSUBWrr, Convert_Reg1_2_ImpReg1_1, { MCK_psubw, MCK_VR64, MCK_VR64 } },
- { X86::PSUBWrr, Convert_Reg1_2_ImpReg1_1, { MCK_psubw, MCK_FR32, MCK_FR32 } },
- { X86::MMX_PSUBWrm, Convert_Reg1_2_ImpMem5_1, { MCK_psubw, MCK_Mem, MCK_VR64 } },
- { X86::PSUBWrm, Convert_Reg1_2_ImpMem5_1, { MCK_psubw, MCK_Mem, MCK_FR32 } },
- { X86::PTESTrr, Convert_Reg1_2_Reg1_1, { MCK_ptest, MCK_FR32, MCK_FR32 } },
- { X86::PTESTrm, Convert_Reg1_2_Mem5_1, { MCK_ptest, MCK_Mem, MCK_FR32 } },
- { X86::MMX_PUNPCKHBWrr, Convert_Reg1_2_ImpReg1_1, { MCK_punpckhbw, MCK_VR64, MCK_VR64 } },
- { X86::PUNPCKHBWrr, Convert_Reg1_2_ImpReg1_1, { MCK_punpckhbw, MCK_FR32, MCK_FR32 } },
- { X86::MMX_PUNPCKHBWrm, Convert_Reg1_2_ImpMem5_1, { MCK_punpckhbw, MCK_Mem, MCK_VR64 } },
- { X86::PUNPCKHBWrm, Convert_Reg1_2_ImpMem5_1, { MCK_punpckhbw, MCK_Mem, MCK_FR32 } },
- { X86::MMX_PUNPCKHDQrr, Convert_Reg1_2_ImpReg1_1, { MCK_punpckhdq, MCK_VR64, MCK_VR64 } },
- { X86::PUNPCKHDQrr, Convert_Reg1_2_ImpReg1_1, { MCK_punpckhdq, MCK_FR32, MCK_FR32 } },
- { X86::MMX_PUNPCKHDQrm, Convert_Reg1_2_ImpMem5_1, { MCK_punpckhdq, MCK_Mem, MCK_VR64 } },
- { X86::PUNPCKHDQrm, Convert_Reg1_2_ImpMem5_1, { MCK_punpckhdq, MCK_Mem, MCK_FR32 } },
- { X86::PUNPCKHQDQrr, Convert_Reg1_2_ImpReg1_1, { MCK_punpckhqdq, MCK_FR32, MCK_FR32 } },
- { X86::PUNPCKHQDQrm, Convert_Reg1_2_ImpMem5_1, { MCK_punpckhqdq, MCK_Mem, MCK_FR32 } },
- { X86::MMX_PUNPCKHWDrr, Convert_Reg1_2_ImpReg1_1, { MCK_punpckhwd, MCK_VR64, MCK_VR64 } },
- { X86::PUNPCKHWDrr, Convert_Reg1_2_ImpReg1_1, { MCK_punpckhwd, MCK_FR32, MCK_FR32 } },
- { X86::MMX_PUNPCKHWDrm, Convert_Reg1_2_ImpMem5_1, { MCK_punpckhwd, MCK_Mem, MCK_VR64 } },
- { X86::PUNPCKHWDrm, Convert_Reg1_2_ImpMem5_1, { MCK_punpckhwd, MCK_Mem, MCK_FR32 } },
- { X86::MMX_PUNPCKLBWrr, Convert_Reg1_2_ImpReg1_1, { MCK_punpcklbw, MCK_VR64, MCK_VR64 } },
- { X86::PUNPCKLBWrr, Convert_Reg1_2_ImpReg1_1, { MCK_punpcklbw, MCK_FR32, MCK_FR32 } },
- { X86::MMX_PUNPCKLBWrm, Convert_Reg1_2_ImpMem5_1, { MCK_punpcklbw, MCK_Mem, MCK_VR64 } },
- { X86::PUNPCKLBWrm, Convert_Reg1_2_ImpMem5_1, { MCK_punpcklbw, MCK_Mem, MCK_FR32 } },
- { X86::MMX_PUNPCKLDQrr, Convert_Reg1_2_ImpReg1_1, { MCK_punpckldq, MCK_VR64, MCK_VR64 } },
- { X86::PUNPCKLDQrr, Convert_Reg1_2_ImpReg1_1, { MCK_punpckldq, MCK_FR32, MCK_FR32 } },
- { X86::MMX_PUNPCKLDQrm, Convert_Reg1_2_ImpMem5_1, { MCK_punpckldq, MCK_Mem, MCK_VR64 } },
- { X86::PUNPCKLDQrm, Convert_Reg1_2_ImpMem5_1, { MCK_punpckldq, MCK_Mem, MCK_FR32 } },
- { X86::PUNPCKLQDQrr, Convert_Reg1_2_ImpReg1_1, { MCK_punpcklqdq, MCK_FR32, MCK_FR32 } },
- { X86::PUNPCKLQDQrm, Convert_Reg1_2_ImpMem5_1, { MCK_punpcklqdq, MCK_Mem, MCK_FR32 } },
- { X86::MMX_PUNPCKLWDrr, Convert_Reg1_2_ImpReg1_1, { MCK_punpcklwd, MCK_VR64, MCK_VR64 } },
- { X86::PUNPCKLWDrr, Convert_Reg1_2_ImpReg1_1, { MCK_punpcklwd, MCK_FR32, MCK_FR32 } },
- { X86::MMX_PUNPCKLWDrm, Convert_Reg1_2_ImpMem5_1, { MCK_punpcklwd, MCK_Mem, MCK_VR64 } },
- { X86::PUNPCKLWDrm, Convert_Reg1_2_ImpMem5_1, { MCK_punpcklwd, MCK_Mem, MCK_FR32 } },
- { X86::MMX_PXORrr, Convert_Reg1_2_ImpReg1_1, { MCK_pxor, MCK_VR64, MCK_VR64 } },
- { X86::PXORrr, Convert_Reg1_2_ImpReg1_1, { MCK_pxor, MCK_FR32, MCK_FR32 } },
- { X86::MMX_PXORrm, Convert_Reg1_2_ImpMem5_1, { MCK_pxor, MCK_Mem, MCK_VR64 } },
- { X86::PXORrm, Convert_Reg1_2_ImpMem5_1, { MCK_pxor, MCK_Mem, MCK_FR32 } },
- { X86::RCL8r1, Convert_Reg1_2Imp, { MCK_rclb, MCK_1, MCK_GR8 } },
- { X86::RCL8m1, Convert_Mem5_2ImpImpImpImpImp, { MCK_rclb, MCK_1, MCK_Mem } },
- { X86::RCL8rCL, Convert_Reg1_2Imp, { MCK_rclb, MCK_CL, MCK_GR8 } },
- { X86::RCL8mCL, Convert_Mem5_2ImpImpImpImpImp, { MCK_rclb, MCK_CL, MCK_Mem } },
- { X86::RCL8ri, Convert_Reg1_2_ImpImm1_1, { MCK_rclb, MCK_Imm, MCK_GR8 } },
- { X86::RCL8mi, Convert_Mem5_2_ImpImpImpImpImpImm1_1, { MCK_rclb, MCK_Imm, MCK_Mem } },
- { X86::RCL32r1, Convert_Reg1_2Imp, { MCK_rcll, MCK_1, MCK_GR32 } },
- { X86::RCL32m1, Convert_Mem5_2ImpImpImpImpImp, { MCK_rcll, MCK_1, MCK_Mem } },
- { X86::RCL32rCL, Convert_Reg1_2Imp, { MCK_rcll, MCK_CL, MCK_GR32 } },
- { X86::RCL32mCL, Convert_Mem5_2ImpImpImpImpImp, { MCK_rcll, MCK_CL, MCK_Mem } },
- { X86::RCL32ri, Convert_Reg1_2_ImpImm1_1, { MCK_rcll, MCK_Imm, MCK_GR32 } },
- { X86::RCL32mi, Convert_Mem5_2_ImpImpImpImpImpImm1_1, { MCK_rcll, MCK_Imm, MCK_Mem } },
- { X86::RCL64r1, Convert_Reg1_2Imp, { MCK_rclq, MCK_1, MCK_GR64 } },
- { X86::RCL64m1, Convert_Mem5_2ImpImpImpImpImp, { MCK_rclq, MCK_1, MCK_Mem } },
- { X86::RCL64rCL, Convert_Reg1_2Imp, { MCK_rclq, MCK_CL, MCK_GR64 } },
- { X86::RCL64mCL, Convert_Mem5_2ImpImpImpImpImp, { MCK_rclq, MCK_CL, MCK_Mem } },
- { X86::RCL64ri, Convert_Reg1_2_ImpImm1_1, { MCK_rclq, MCK_Imm, MCK_GR64 } },
- { X86::RCL64mi, Convert_Mem5_2_ImpImpImpImpImpImm1_1, { MCK_rclq, MCK_Imm, MCK_Mem } },
- { X86::RCL16r1, Convert_Reg1_2Imp, { MCK_rclw, MCK_1, MCK_GR16 } },
- { X86::RCL16m1, Convert_Mem5_2ImpImpImpImpImp, { MCK_rclw, MCK_1, MCK_Mem } },
- { X86::RCL16rCL, Convert_Reg1_2Imp, { MCK_rclw, MCK_CL, MCK_GR16 } },
- { X86::RCL16mCL, Convert_Mem5_2ImpImpImpImpImp, { MCK_rclw, MCK_CL, MCK_Mem } },
- { X86::RCL16ri, Convert_Reg1_2_ImpImm1_1, { MCK_rclw, MCK_Imm, MCK_GR16 } },
- { X86::RCL16mi, Convert_Mem5_2_ImpImpImpImpImpImm1_1, { MCK_rclw, MCK_Imm, MCK_Mem } },
- { X86::RCPPSr, Convert_Reg1_2_Reg1_1, { MCK_rcpps, MCK_FR32, MCK_FR32 } },
- { X86::RCPPSm, Convert_Reg1_2_Mem5_1, { MCK_rcpps, MCK_Mem, MCK_FR32 } },
- { X86::RCPSSr, Convert_Reg1_2_Reg1_1, { MCK_rcpss, MCK_FR32, MCK_FR32 } },
- { X86::RCPSSm, Convert_Reg1_2_Mem5_1, { MCK_rcpss, MCK_Mem, MCK_FR32 } },
- { X86::RCR8r1, Convert_Reg1_2Imp, { MCK_rcrb, MCK_1, MCK_GR8 } },
- { X86::RCR8m1, Convert_Mem5_2ImpImpImpImpImp, { MCK_rcrb, MCK_1, MCK_Mem } },
- { X86::RCR8rCL, Convert_Reg1_2Imp, { MCK_rcrb, MCK_CL, MCK_GR8 } },
- { X86::RCR8mCL, Convert_Mem5_2ImpImpImpImpImp, { MCK_rcrb, MCK_CL, MCK_Mem } },
- { X86::RCR8ri, Convert_Reg1_2_ImpImm1_1, { MCK_rcrb, MCK_Imm, MCK_GR8 } },
- { X86::RCR8mi, Convert_Mem5_2_ImpImpImpImpImpImm1_1, { MCK_rcrb, MCK_Imm, MCK_Mem } },
- { X86::RCR32r1, Convert_Reg1_2Imp, { MCK_rcrl, MCK_1, MCK_GR32 } },
- { X86::RCR32m1, Convert_Mem5_2ImpImpImpImpImp, { MCK_rcrl, MCK_1, MCK_Mem } },
- { X86::RCR32rCL, Convert_Reg1_2Imp, { MCK_rcrl, MCK_CL, MCK_GR32 } },
- { X86::RCR32mCL, Convert_Mem5_2ImpImpImpImpImp, { MCK_rcrl, MCK_CL, MCK_Mem } },
- { X86::RCR32ri, Convert_Reg1_2_ImpImm1_1, { MCK_rcrl, MCK_Imm, MCK_GR32 } },
- { X86::RCR32mi, Convert_Mem5_2_ImpImpImpImpImpImm1_1, { MCK_rcrl, MCK_Imm, MCK_Mem } },
- { X86::RCR64r1, Convert_Reg1_2Imp, { MCK_rcrq, MCK_1, MCK_GR64 } },
- { X86::RCR64m1, Convert_Mem5_2ImpImpImpImpImp, { MCK_rcrq, MCK_1, MCK_Mem } },
- { X86::RCR64rCL, Convert_Reg1_2Imp, { MCK_rcrq, MCK_CL, MCK_GR64 } },
- { X86::RCR64mCL, Convert_Mem5_2ImpImpImpImpImp, { MCK_rcrq, MCK_CL, MCK_Mem } },
- { X86::RCR64ri, Convert_Reg1_2_ImpImm1_1, { MCK_rcrq, MCK_Imm, MCK_GR64 } },
- { X86::RCR64mi, Convert_Mem5_2_ImpImpImpImpImpImm1_1, { MCK_rcrq, MCK_Imm, MCK_Mem } },
- { X86::RCR16r1, Convert_Reg1_2Imp, { MCK_rcrw, MCK_1, MCK_GR16 } },
- { X86::RCR16m1, Convert_Mem5_2ImpImpImpImpImp, { MCK_rcrw, MCK_1, MCK_Mem } },
- { X86::RCR16rCL, Convert_Reg1_2Imp, { MCK_rcrw, MCK_CL, MCK_GR16 } },
- { X86::RCR16mCL, Convert_Mem5_2ImpImpImpImpImp, { MCK_rcrw, MCK_CL, MCK_Mem } },
- { X86::RCR16ri, Convert_Reg1_2_ImpImm1_1, { MCK_rcrw, MCK_Imm, MCK_GR16 } },
- { X86::RCR16mi, Convert_Mem5_2_ImpImpImpImpImpImm1_1, { MCK_rcrw, MCK_Imm, MCK_Mem } },
- { X86::ROL8rCL, Convert_Reg1_2Imp, { MCK_rolb, MCK_CL, MCK_GR8 } },
- { X86::ROL8mCL, Convert_Mem5_2, { MCK_rolb, MCK_CL, MCK_Mem } },
- { X86::ROL8ri, Convert_Reg1_2_ImpImm1_1, { MCK_rolb, MCK_Imm, MCK_GR8 } },
- { X86::ROL8mi, Convert_Mem5_2_Imm1_1, { MCK_rolb, MCK_Imm, MCK_Mem } },
- { X86::ROL32rCL, Convert_Reg1_2Imp, { MCK_roll, MCK_CL, MCK_GR32 } },
- { X86::ROL32mCL, Convert_Mem5_2, { MCK_roll, MCK_CL, MCK_Mem } },
- { X86::ROL32ri, Convert_Reg1_2_ImpImm1_1, { MCK_roll, MCK_Imm, MCK_GR32 } },
- { X86::ROL32mi, Convert_Mem5_2_Imm1_1, { MCK_roll, MCK_Imm, MCK_Mem } },
- { X86::ROL64rCL, Convert_Reg1_2Imp, { MCK_rolq, MCK_CL, MCK_GR64 } },
- { X86::ROL64mCL, Convert_Mem5_2, { MCK_rolq, MCK_CL, MCK_Mem } },
- { X86::ROL64ri, Convert_Reg1_2_ImpImm1_1, { MCK_rolq, MCK_Imm, MCK_GR64 } },
- { X86::ROL64mi, Convert_Mem5_2_Imm1_1, { MCK_rolq, MCK_Imm, MCK_Mem } },
- { X86::ROL16rCL, Convert_Reg1_2Imp, { MCK_rolw, MCK_CL, MCK_GR16 } },
- { X86::ROL16mCL, Convert_Mem5_2, { MCK_rolw, MCK_CL, MCK_Mem } },
- { X86::ROL16ri, Convert_Reg1_2_ImpImm1_1, { MCK_rolw, MCK_Imm, MCK_GR16 } },
- { X86::ROL16mi, Convert_Mem5_2_Imm1_1, { MCK_rolw, MCK_Imm, MCK_Mem } },
- { X86::ROR8rCL, Convert_Reg1_2Imp, { MCK_rorb, MCK_CL, MCK_GR8 } },
- { X86::ROR8mCL, Convert_Mem5_2, { MCK_rorb, MCK_CL, MCK_Mem } },
- { X86::ROR8ri, Convert_Reg1_2_ImpImm1_1, { MCK_rorb, MCK_Imm, MCK_GR8 } },
- { X86::ROR8mi, Convert_Mem5_2_Imm1_1, { MCK_rorb, MCK_Imm, MCK_Mem } },
- { X86::ROR32rCL, Convert_Reg1_2Imp, { MCK_rorl, MCK_CL, MCK_GR32 } },
- { X86::ROR32mCL, Convert_Mem5_2, { MCK_rorl, MCK_CL, MCK_Mem } },
- { X86::ROR32ri, Convert_Reg1_2_ImpImm1_1, { MCK_rorl, MCK_Imm, MCK_GR32 } },
- { X86::ROR32mi, Convert_Mem5_2_Imm1_1, { MCK_rorl, MCK_Imm, MCK_Mem } },
- { X86::ROR64rCL, Convert_Reg1_2Imp, { MCK_rorq, MCK_CL, MCK_GR64 } },
- { X86::ROR64mCL, Convert_Mem5_2, { MCK_rorq, MCK_CL, MCK_Mem } },
- { X86::ROR64ri, Convert_Reg1_2_ImpImm1_1, { MCK_rorq, MCK_Imm, MCK_GR64 } },
- { X86::ROR64mi, Convert_Mem5_2_Imm1_1, { MCK_rorq, MCK_Imm, MCK_Mem } },
- { X86::ROR16rCL, Convert_Reg1_2Imp, { MCK_rorw, MCK_CL, MCK_GR16 } },
- { X86::ROR16mCL, Convert_Mem5_2, { MCK_rorw, MCK_CL, MCK_Mem } },
- { X86::ROR16ri, Convert_Reg1_2_ImpImm1_1, { MCK_rorw, MCK_Imm, MCK_GR16 } },
- { X86::ROR16mi, Convert_Mem5_2_Imm1_1, { MCK_rorw, MCK_Imm, MCK_Mem } },
- { X86::RSQRTPSr, Convert_Reg1_2_Reg1_1, { MCK_rsqrtps, MCK_FR32, MCK_FR32 } },
- { X86::RSQRTPSm, Convert_Reg1_2_Mem5_1, { MCK_rsqrtps, MCK_Mem, MCK_FR32 } },
- { X86::RSQRTSSr, Convert_Reg1_2_Reg1_1, { MCK_rsqrtss, MCK_FR32, MCK_FR32 } },
- { X86::RSQRTSSm, Convert_Reg1_2_Mem5_1, { MCK_rsqrtss, MCK_Mem, MCK_FR32 } },
- { X86::SAR8rCL, Convert_Reg1_2Imp, { MCK_sarb, MCK_CL, MCK_GR8 } },
- { X86::SAR8mCL, Convert_Mem5_2, { MCK_sarb, MCK_CL, MCK_Mem } },
- { X86::SAR8ri, Convert_Reg1_2_ImpImm1_1, { MCK_sarb, MCK_Imm, MCK_GR8 } },
- { X86::SAR8mi, Convert_Mem5_2_Imm1_1, { MCK_sarb, MCK_Imm, MCK_Mem } },
- { X86::SAR32rCL, Convert_Reg1_2Imp, { MCK_sarl, MCK_CL, MCK_GR32 } },
- { X86::SAR32mCL, Convert_Mem5_2, { MCK_sarl, MCK_CL, MCK_Mem } },
- { X86::SAR32ri, Convert_Reg1_2_ImpImm1_1, { MCK_sarl, MCK_Imm, MCK_GR32 } },
- { X86::SAR32mi, Convert_Mem5_2_Imm1_1, { MCK_sarl, MCK_Imm, MCK_Mem } },
- { X86::SAR64rCL, Convert_Reg1_2Imp, { MCK_sarq, MCK_CL, MCK_GR64 } },
- { X86::SAR64mCL, Convert_Mem5_2, { MCK_sarq, MCK_CL, MCK_Mem } },
- { X86::SAR64ri, Convert_Reg1_2_ImpImm1_1, { MCK_sarq, MCK_Imm, MCK_GR64 } },
- { X86::SAR64mi, Convert_Mem5_2_Imm1_1, { MCK_sarq, MCK_Imm, MCK_Mem } },
- { X86::SAR16rCL, Convert_Reg1_2Imp, { MCK_sarw, MCK_CL, MCK_GR16 } },
- { X86::SAR16mCL, Convert_Mem5_2, { MCK_sarw, MCK_CL, MCK_Mem } },
- { X86::SAR16ri, Convert_Reg1_2_ImpImm1_1, { MCK_sarw, MCK_Imm, MCK_GR16 } },
- { X86::SAR16mi, Convert_Mem5_2_Imm1_1, { MCK_sarw, MCK_Imm, MCK_Mem } },
- { X86::SBB8rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_sbbb, MCK_GR8, MCK_GR8 } },
- { X86::SBB8rr, Convert_Reg1_2_ImpReg1_1, { MCK_sbbb, MCK_GR8, MCK_GR8 } },
- { X86::SBB8mr, Convert_Mem5_2_Reg1_1, { MCK_sbbb, MCK_GR8, MCK_Mem } },
- { X86::SBB8i8, Convert_Imm1_1, { MCK_sbbb, MCK_Imm, MCK_AL } },
- { X86::SBB8ri, Convert_Reg1_2_ImpImm1_1, { MCK_sbbb, MCK_Imm, MCK_GR8 } },
- { X86::SBB8mi, Convert_Mem5_2_Imm1_1, { MCK_sbbb, MCK_Imm, MCK_Mem } },
- { X86::SBB8rm, Convert_Reg1_2_ImpMem5_1, { MCK_sbbb, MCK_Mem, MCK_GR8 } },
- { X86::SBB32rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_sbbl, MCK_GR32, MCK_GR32 } },
- { X86::SBB32rr, Convert_Reg1_2_ImpReg1_1, { MCK_sbbl, MCK_GR32, MCK_GR32 } },
- { X86::SBB32mr, Convert_Mem5_2_Reg1_1, { MCK_sbbl, MCK_GR32, MCK_Mem } },
- { X86::SBB32ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_sbbl, MCK_ImmSExt8, MCK_GR32 } },
- { X86::SBB32mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_sbbl, MCK_ImmSExt8, MCK_Mem } },
- { X86::SBB32i32, Convert_Imm1_1, { MCK_sbbl, MCK_Imm, MCK_EAX } },
- { X86::SBB32ri, Convert_Reg1_2_ImpImm1_1, { MCK_sbbl, MCK_Imm, MCK_GR32 } },
- { X86::SBB32mi, Convert_Mem5_2_Imm1_1, { MCK_sbbl, MCK_Imm, MCK_Mem } },
- { X86::SBB32rm, Convert_Reg1_2_ImpMem5_1, { MCK_sbbl, MCK_Mem, MCK_GR32 } },
- { X86::SBB64rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_sbbq, MCK_GR64, MCK_GR64 } },
- { X86::SBB64rr, Convert_Reg1_2_ImpReg1_1, { MCK_sbbq, MCK_GR64, MCK_GR64 } },
- { X86::SBB64mr, Convert_Mem5_2_Reg1_1, { MCK_sbbq, MCK_GR64, MCK_Mem } },
- { X86::SBB64ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_sbbq, MCK_ImmSExt8, MCK_GR64 } },
- { X86::SBB64mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_sbbq, MCK_ImmSExt8, MCK_Mem } },
- { X86::SBB64i32, Convert_Imm1_1, { MCK_sbbq, MCK_Imm, MCK_RAX } },
- { X86::SBB64ri32, Convert_Reg1_2_ImpImm1_1, { MCK_sbbq, MCK_Imm, MCK_GR64 } },
- { X86::SBB64mi32, Convert_Mem5_2_Imm1_1, { MCK_sbbq, MCK_Imm, MCK_Mem } },
- { X86::SBB64rm, Convert_Reg1_2_ImpMem5_1, { MCK_sbbq, MCK_Mem, MCK_GR64 } },
- { X86::SBB16rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_sbbw, MCK_GR16, MCK_GR16 } },
- { X86::SBB16rr, Convert_Reg1_2_ImpReg1_1, { MCK_sbbw, MCK_GR16, MCK_GR16 } },
- { X86::SBB16mr, Convert_Mem5_2_Reg1_1, { MCK_sbbw, MCK_GR16, MCK_Mem } },
- { X86::SBB16ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_sbbw, MCK_ImmSExt8, MCK_GR16 } },
- { X86::SBB16mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_sbbw, MCK_ImmSExt8, MCK_Mem } },
- { X86::SBB16i16, Convert_Imm1_1, { MCK_sbbw, MCK_Imm, MCK_AX } },
- { X86::SBB16ri, Convert_Reg1_2_ImpImm1_1, { MCK_sbbw, MCK_Imm, MCK_GR16 } },
- { X86::SBB16mi, Convert_Mem5_2_Imm1_1, { MCK_sbbw, MCK_Imm, MCK_Mem } },
- { X86::SBB16rm, Convert_Reg1_2_ImpMem5_1, { MCK_sbbw, MCK_Mem, MCK_GR16 } },
- { X86::SHL8rCL, Convert_Reg1_2Imp, { MCK_shlb, MCK_CL, MCK_GR8 } },
- { X86::SHL8mCL, Convert_Mem5_2, { MCK_shlb, MCK_CL, MCK_Mem } },
- { X86::SHL8ri, Convert_Reg1_2_ImpImm1_1, { MCK_shlb, MCK_Imm, MCK_GR8 } },
- { X86::SHL8mi, Convert_Mem5_2_Imm1_1, { MCK_shlb, MCK_Imm, MCK_Mem } },
- { X86::SHL32rCL, Convert_Reg1_2Imp, { MCK_shll, MCK_CL, MCK_GR32 } },
- { X86::SHL32mCL, Convert_Mem5_2, { MCK_shll, MCK_CL, MCK_Mem } },
- { X86::SHL32ri, Convert_Reg1_2_ImpImm1_1, { MCK_shll, MCK_Imm, MCK_GR32 } },
- { X86::SHL32mi, Convert_Mem5_2_Imm1_1, { MCK_shll, MCK_Imm, MCK_Mem } },
- { X86::SHL64rCL, Convert_Reg1_2Imp, { MCK_shlq, MCK_CL, MCK_GR64 } },
- { X86::SHL64mCL, Convert_Mem5_2, { MCK_shlq, MCK_CL, MCK_Mem } },
- { X86::SHL64ri, Convert_Reg1_2_ImpImm1_1, { MCK_shlq, MCK_Imm, MCK_GR64 } },
- { X86::SHL64mi, Convert_Mem5_2_Imm1_1, { MCK_shlq, MCK_Imm, MCK_Mem } },
- { X86::SHL16rCL, Convert_Reg1_2Imp, { MCK_shlw, MCK_CL, MCK_GR16 } },
- { X86::SHL16mCL, Convert_Mem5_2, { MCK_shlw, MCK_CL, MCK_Mem } },
- { X86::SHL16ri, Convert_Reg1_2_ImpImm1_1, { MCK_shlw, MCK_Imm, MCK_GR16 } },
- { X86::SHL16mi, Convert_Mem5_2_Imm1_1, { MCK_shlw, MCK_Imm, MCK_Mem } },
- { X86::SHR8rCL, Convert_Reg1_2Imp, { MCK_shrb, MCK_CL, MCK_GR8 } },
- { X86::SHR8mCL, Convert_Mem5_2, { MCK_shrb, MCK_CL, MCK_Mem } },
- { X86::SHR8ri, Convert_Reg1_2_ImpImm1_1, { MCK_shrb, MCK_Imm, MCK_GR8 } },
- { X86::SHR8mi, Convert_Mem5_2_Imm1_1, { MCK_shrb, MCK_Imm, MCK_Mem } },
- { X86::SHR32rCL, Convert_Reg1_2Imp, { MCK_shrl, MCK_CL, MCK_GR32 } },
- { X86::SHR32mCL, Convert_Mem5_2, { MCK_shrl, MCK_CL, MCK_Mem } },
- { X86::SHR32ri, Convert_Reg1_2_ImpImm1_1, { MCK_shrl, MCK_Imm, MCK_GR32 } },
- { X86::SHR32mi, Convert_Mem5_2_Imm1_1, { MCK_shrl, MCK_Imm, MCK_Mem } },
- { X86::SHR64rCL, Convert_Reg1_2Imp, { MCK_shrq, MCK_CL, MCK_GR64 } },
- { X86::SHR64mCL, Convert_Mem5_2, { MCK_shrq, MCK_CL, MCK_Mem } },
- { X86::SHR64ri, Convert_Reg1_2_ImpImm1_1, { MCK_shrq, MCK_Imm, MCK_GR64 } },
- { X86::SHR64mi, Convert_Mem5_2_Imm1_1, { MCK_shrq, MCK_Imm, MCK_Mem } },
- { X86::SHR16rCL, Convert_Reg1_2Imp, { MCK_shrw, MCK_CL, MCK_GR16 } },
- { X86::SHR16mCL, Convert_Mem5_2, { MCK_shrw, MCK_CL, MCK_Mem } },
- { X86::SHR16ri, Convert_Reg1_2_ImpImm1_1, { MCK_shrw, MCK_Imm, MCK_GR16 } },
- { X86::SHR16mi, Convert_Mem5_2_Imm1_1, { MCK_shrw, MCK_Imm, MCK_Mem } },
- { X86::SQRTPDr, Convert_Reg1_2_Reg1_1, { MCK_sqrtpd, MCK_FR32, MCK_FR32 } },
- { X86::SQRTPDm, Convert_Reg1_2_Mem5_1, { MCK_sqrtpd, MCK_Mem, MCK_FR32 } },
- { X86::SQRTPSr, Convert_Reg1_2_Reg1_1, { MCK_sqrtps, MCK_FR32, MCK_FR32 } },
- { X86::SQRTPSm, Convert_Reg1_2_Mem5_1, { MCK_sqrtps, MCK_Mem, MCK_FR32 } },
- { X86::SQRTSDr, Convert_Reg1_2_Reg1_1, { MCK_sqrtsd, MCK_FR32, MCK_FR32 } },
- { X86::SQRTSDm, Convert_Reg1_2_Mem5_1, { MCK_sqrtsd, MCK_Mem, MCK_FR32 } },
- { X86::SQRTSSr, Convert_Reg1_2_Reg1_1, { MCK_sqrtss, MCK_FR32, MCK_FR32 } },
- { X86::SQRTSSm, Convert_Reg1_2_Mem5_1, { MCK_sqrtss, MCK_Mem, MCK_FR32 } },
- { X86::SUB8rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_subb, MCK_GR8, MCK_GR8 } },
- { X86::SUB8rr, Convert_Reg1_2_ImpReg1_1, { MCK_subb, MCK_GR8, MCK_GR8 } },
- { X86::SUB8mr, Convert_Mem5_2_Reg1_1, { MCK_subb, MCK_GR8, MCK_Mem } },
- { X86::SUB8i8, Convert_Imm1_1, { MCK_subb, MCK_Imm, MCK_AL } },
- { X86::SUB8ri, Convert_Reg1_2_ImpImm1_1, { MCK_subb, MCK_Imm, MCK_GR8 } },
- { X86::SUB8mi, Convert_Mem5_2_Imm1_1, { MCK_subb, MCK_Imm, MCK_Mem } },
- { X86::SUB8rm, Convert_Reg1_2_ImpMem5_1, { MCK_subb, MCK_Mem, MCK_GR8 } },
- { X86::SUB32rr, Convert_Reg1_2_ImpReg1_1, { MCK_subl, MCK_GR32, MCK_GR32 } },
- { X86::SUB32rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_subl, MCK_GR32, MCK_GR32 } },
- { X86::SUB32mr, Convert_Mem5_2_Reg1_1, { MCK_subl, MCK_GR32, MCK_Mem } },
- { X86::SUB32ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_subl, MCK_ImmSExt8, MCK_GR32 } },
- { X86::SUB32mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_subl, MCK_ImmSExt8, MCK_Mem } },
- { X86::SUB32i32, Convert_Imm1_1, { MCK_subl, MCK_Imm, MCK_EAX } },
- { X86::SUB32ri, Convert_Reg1_2_ImpImm1_1, { MCK_subl, MCK_Imm, MCK_GR32 } },
- { X86::SUB32mi, Convert_Mem5_2_Imm1_1, { MCK_subl, MCK_Imm, MCK_Mem } },
- { X86::SUB32rm, Convert_Reg1_2_ImpMem5_1, { MCK_subl, MCK_Mem, MCK_GR32 } },
- { X86::SUBPDrr, Convert_Reg1_2_ImpReg1_1, { MCK_subpd, MCK_FR32, MCK_FR32 } },
- { X86::SUBPDrm, Convert_Reg1_2_ImpMem5_1, { MCK_subpd, MCK_Mem, MCK_FR32 } },
- { X86::SUBPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_subps, MCK_FR32, MCK_FR32 } },
- { X86::SUBPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_subps, MCK_Mem, MCK_FR32 } },
- { X86::SUB64rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_subq, MCK_GR64, MCK_GR64 } },
- { X86::SUB64rr, Convert_Reg1_2_ImpReg1_1, { MCK_subq, MCK_GR64, MCK_GR64 } },
- { X86::SUB64mr, Convert_Mem5_2_Reg1_1, { MCK_subq, MCK_GR64, MCK_Mem } },
- { X86::SUB64ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_subq, MCK_ImmSExt8, MCK_GR64 } },
- { X86::SUB64mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_subq, MCK_ImmSExt8, MCK_Mem } },
- { X86::SUB64i32, Convert_Imm1_1, { MCK_subq, MCK_Imm, MCK_RAX } },
- { X86::SUB64ri32, Convert_Reg1_2_ImpImm1_1, { MCK_subq, MCK_Imm, MCK_GR64 } },
- { X86::SUB64mi32, Convert_Mem5_2_Imm1_1, { MCK_subq, MCK_Imm, MCK_Mem } },
- { X86::SUB64rm, Convert_Reg1_2_ImpMem5_1, { MCK_subq, MCK_Mem, MCK_GR64 } },
- { X86::SUBSDrr, Convert_Reg1_2_ImpReg1_1, { MCK_subsd, MCK_FR32, MCK_FR32 } },
- { X86::SUBSDrm, Convert_Reg1_2_ImpMem5_1, { MCK_subsd, MCK_Mem, MCK_FR32 } },
- { X86::SUBSSrr, Convert_Reg1_2_ImpReg1_1, { MCK_subss, MCK_FR32, MCK_FR32 } },
- { X86::SUBSSrm, Convert_Reg1_2_ImpMem5_1, { MCK_subss, MCK_Mem, MCK_FR32 } },
- { X86::SUB16rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_subw, MCK_GR16, MCK_GR16 } },
- { X86::SUB16rr, Convert_Reg1_2_ImpReg1_1, { MCK_subw, MCK_GR16, MCK_GR16 } },
- { X86::SUB16mr, Convert_Mem5_2_Reg1_1, { MCK_subw, MCK_GR16, MCK_Mem } },
- { X86::SUB16ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_subw, MCK_ImmSExt8, MCK_GR16 } },
- { X86::SUB16mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_subw, MCK_ImmSExt8, MCK_Mem } },
- { X86::SUB16i16, Convert_Imm1_1, { MCK_subw, MCK_Imm, MCK_AX } },
- { X86::SUB16ri, Convert_Reg1_2_ImpImm1_1, { MCK_subw, MCK_Imm, MCK_GR16 } },
- { X86::SUB16mi, Convert_Mem5_2_Imm1_1, { MCK_subw, MCK_Imm, MCK_Mem } },
- { X86::SUB16rm, Convert_Reg1_2_ImpMem5_1, { MCK_subw, MCK_Mem, MCK_GR16 } },
- { X86::TEST8rr, Convert_Reg1_2_Reg1_1, { MCK_testb, MCK_GR8, MCK_GR8 } },
- { X86::TEST8i8, Convert_Imm1_1, { MCK_testb, MCK_Imm, MCK_AL } },
- { X86::TEST8ri, Convert_Reg1_2_Imm1_1, { MCK_testb, MCK_Imm, MCK_GR8 } },
- { X86::TEST8mi, Convert_Mem5_2_Imm1_1, { MCK_testb, MCK_Imm, MCK_Mem } },
- { X86::TEST8rm, Convert_Reg1_2_Mem5_1, { MCK_testb, MCK_Mem, MCK_GR8 } },
- { X86::TEST32rr, Convert_Reg1_2_Reg1_1, { MCK_testl, MCK_GR32, MCK_GR32 } },
- { X86::TEST32i32, Convert_Imm1_1, { MCK_testl, MCK_Imm, MCK_EAX } },
- { X86::TEST32ri, Convert_Reg1_2_Imm1_1, { MCK_testl, MCK_Imm, MCK_GR32 } },
- { X86::TEST32mi, Convert_Mem5_2_Imm1_1, { MCK_testl, MCK_Imm, MCK_Mem } },
- { X86::TEST32rm, Convert_Reg1_2_Mem5_1, { MCK_testl, MCK_Mem, MCK_GR32 } },
- { X86::TEST64rr, Convert_Reg1_2_Reg1_1, { MCK_testq, MCK_GR64, MCK_GR64 } },
- { X86::TEST64i32, Convert_Imm1_1, { MCK_testq, MCK_Imm, MCK_RAX } },
- { X86::TEST64ri32, Convert_Reg1_2_Imm1_1, { MCK_testq, MCK_Imm, MCK_GR64 } },
- { X86::TEST64mi32, Convert_Mem5_2_Imm1_1, { MCK_testq, MCK_Imm, MCK_Mem } },
- { X86::TEST64rm, Convert_Reg1_2_Mem5_1, { MCK_testq, MCK_Mem, MCK_GR64 } },
- { X86::TEST16rr, Convert_Reg1_2_Reg1_1, { MCK_testw, MCK_GR16, MCK_GR16 } },
- { X86::TEST16i16, Convert_Imm1_1, { MCK_testw, MCK_Imm, MCK_AX } },
- { X86::TEST16ri, Convert_Reg1_2_Imm1_1, { MCK_testw, MCK_Imm, MCK_GR16 } },
- { X86::TEST16mi, Convert_Mem5_2_Imm1_1, { MCK_testw, MCK_Imm, MCK_Mem } },
- { X86::TEST16rm, Convert_Reg1_2_Mem5_1, { MCK_testw, MCK_Mem, MCK_GR16 } },
- { X86::UCOMISDrr, Convert_Reg1_2_Reg1_1, { MCK_ucomisd, MCK_FR32, MCK_FR32 } },
- { X86::UCOMISDrm, Convert_Reg1_2_Mem5_1, { MCK_ucomisd, MCK_Mem, MCK_FR32 } },
- { X86::UCOMISSrr, Convert_Reg1_2_Reg1_1, { MCK_ucomiss, MCK_FR32, MCK_FR32 } },
- { X86::UCOMISSrm, Convert_Reg1_2_Mem5_1, { MCK_ucomiss, MCK_Mem, MCK_FR32 } },
- { X86::UNPCKHPDrr, Convert_Reg1_2_ImpReg1_1, { MCK_unpckhpd, MCK_FR32, MCK_FR32 } },
- { X86::UNPCKHPDrm, Convert_Reg1_2_ImpMem5_1, { MCK_unpckhpd, MCK_Mem, MCK_FR32 } },
- { X86::UNPCKHPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_unpckhps, MCK_FR32, MCK_FR32 } },
- { X86::UNPCKHPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_unpckhps, MCK_Mem, MCK_FR32 } },
- { X86::UNPCKLPDrr, Convert_Reg1_2_ImpReg1_1, { MCK_unpcklpd, MCK_FR32, MCK_FR32 } },
- { X86::UNPCKLPDrm, Convert_Reg1_2_ImpMem5_1, { MCK_unpcklpd, MCK_Mem, MCK_FR32 } },
- { X86::UNPCKLPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_unpcklps, MCK_FR32, MCK_FR32 } },
- { X86::UNPCKLPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_unpcklps, MCK_Mem, MCK_FR32 } },
- { X86::VMREAD32rr, Convert_Reg1_2_Reg1_1, { MCK_vmreadl, MCK_GR32, MCK_GR32 } },
- { X86::VMREAD32rm, Convert_Mem5_2_Reg1_1, { MCK_vmreadl, MCK_GR32, MCK_Mem } },
- { X86::VMREAD64rr, Convert_Reg1_2_Reg1_1, { MCK_vmreadq, MCK_GR64, MCK_GR64 } },
- { X86::VMREAD64rm, Convert_Mem5_2_Reg1_1, { MCK_vmreadq, MCK_GR64, MCK_Mem } },
- { X86::VMWRITE32rr, Convert_Reg1_2_Reg1_1, { MCK_vmwritel, MCK_GR32, MCK_GR32 } },
- { X86::VMWRITE32rm, Convert_Reg1_2_Mem5_1, { MCK_vmwritel, MCK_Mem, MCK_GR32 } },
- { X86::VMWRITE64rr, Convert_Reg1_2_Reg1_1, { MCK_vmwriteq, MCK_GR64, MCK_GR64 } },
- { X86::VMWRITE64rm, Convert_Reg1_2_Mem5_1, { MCK_vmwriteq, MCK_Mem, MCK_GR64 } },
- { X86::XADD8rr, Convert_Reg1_2_Reg1_1, { MCK_xaddb, MCK_GR8, MCK_GR8 } },
- { X86::XADD8rm, Convert_Mem5_2_Reg1_1, { MCK_xaddb, MCK_GR8, MCK_Mem } },
- { X86::XADD32rr, Convert_Reg1_2_Reg1_1, { MCK_xaddl, MCK_GR32, MCK_GR32 } },
- { X86::XADD32rm, Convert_Mem5_2_Reg1_1, { MCK_xaddl, MCK_GR32, MCK_Mem } },
- { X86::XADD64rr, Convert_Reg1_2_Reg1_1, { MCK_xaddq, MCK_GR64, MCK_GR64 } },
- { X86::XADD64rm, Convert_Mem5_2_Reg1_1, { MCK_xaddq, MCK_GR64, MCK_Mem } },
- { X86::XADD16rr, Convert_Reg1_2_Reg1_1, { MCK_xaddw, MCK_GR16, MCK_GR16 } },
- { X86::XADD16rm, Convert_Mem5_2_Reg1_1, { MCK_xaddw, MCK_GR16, MCK_Mem } },
- { X86::XCHG8rr, Convert_ImpReg1_1_Reg1_2, { MCK_xchgb, MCK_GR8, MCK_GR8 } },
- { X86::XCHG8rm, Convert_ImpReg1_1_Mem5_2, { MCK_xchgb, MCK_GR8, MCK_Mem } },
- { X86::XCHG32ar, Convert_Reg1_1, { MCK_xchgl, MCK_GR32, MCK_EAX } },
- { X86::XCHG32rr, Convert_ImpReg1_1_Reg1_2, { MCK_xchgl, MCK_GR32, MCK_GR32 } },
- { X86::XCHG32rm, Convert_ImpReg1_1_Mem5_2, { MCK_xchgl, MCK_GR32, MCK_Mem } },
- { X86::XCHG64ar, Convert_Reg1_1, { MCK_xchgq, MCK_GR64, MCK_RAX } },
- { X86::XCHG64rr, Convert_ImpReg1_1_Reg1_2, { MCK_xchgq, MCK_GR64, MCK_GR64 } },
- { X86::XCHG64rm, Convert_ImpReg1_1_Mem5_2, { MCK_xchgq, MCK_GR64, MCK_Mem } },
- { X86::XCHG16ar, Convert_Reg1_1, { MCK_xchgw, MCK_GR16, MCK_AX } },
- { X86::XCHG16rr, Convert_ImpReg1_1_Reg1_2, { MCK_xchgw, MCK_GR16, MCK_GR16 } },
- { X86::XCHG16rm, Convert_ImpReg1_1_Mem5_2, { MCK_xchgw, MCK_GR16, MCK_Mem } },
- { X86::XOR8rr, Convert_Reg1_2_ImpReg1_1, { MCK_xorb, MCK_GR8, MCK_GR8 } },
- { X86::XOR8rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_xorb, MCK_GR8, MCK_GR8 } },
- { X86::XOR8mr, Convert_Mem5_2_Reg1_1, { MCK_xorb, MCK_GR8, MCK_Mem } },
- { X86::XOR8i8, Convert_Imm1_1, { MCK_xorb, MCK_Imm, MCK_AL } },
- { X86::XOR8ri, Convert_Reg1_2_ImpImm1_1, { MCK_xorb, MCK_Imm, MCK_GR8 } },
- { X86::XOR8mi, Convert_Mem5_2_Imm1_1, { MCK_xorb, MCK_Imm, MCK_Mem } },
- { X86::XOR8rm, Convert_Reg1_2_ImpMem5_1, { MCK_xorb, MCK_Mem, MCK_GR8 } },
- { X86::XOR32rr, Convert_Reg1_2_ImpReg1_1, { MCK_xorl, MCK_GR32, MCK_GR32 } },
- { X86::XOR32rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_xorl, MCK_GR32, MCK_GR32 } },
- { X86::XOR32mr, Convert_Mem5_2_Reg1_1, { MCK_xorl, MCK_GR32, MCK_Mem } },
- { X86::XOR32ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_xorl, MCK_ImmSExt8, MCK_GR32 } },
- { X86::XOR32mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_xorl, MCK_ImmSExt8, MCK_Mem } },
- { X86::XOR32i32, Convert_Imm1_1, { MCK_xorl, MCK_Imm, MCK_EAX } },
- { X86::XOR32ri, Convert_Reg1_2_ImpImm1_1, { MCK_xorl, MCK_Imm, MCK_GR32 } },
- { X86::XOR32mi, Convert_Mem5_2_Imm1_1, { MCK_xorl, MCK_Imm, MCK_Mem } },
- { X86::XOR32rm, Convert_Reg1_2_ImpMem5_1, { MCK_xorl, MCK_Mem, MCK_GR32 } },
- { X86::XORPDrr, Convert_Reg1_2_ImpReg1_1, { MCK_xorpd, MCK_FR32, MCK_FR32 } },
- { X86::FsXORPDrr, Convert_Reg1_2_ImpReg1_1, { MCK_xorpd, MCK_FR32, MCK_FR32 } },
- { X86::FsXORPDrm, Convert_Reg1_2_ImpMem5_1, { MCK_xorpd, MCK_Mem, MCK_FR32 } },
- { X86::XORPDrm, Convert_Reg1_2_ImpMem5_1, { MCK_xorpd, MCK_Mem, MCK_FR32 } },
- { X86::FsXORPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_xorps, MCK_FR32, MCK_FR32 } },
- { X86::XORPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_xorps, MCK_FR32, MCK_FR32 } },
- { X86::XORPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_xorps, MCK_Mem, MCK_FR32 } },
- { X86::FsXORPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_xorps, MCK_Mem, MCK_FR32 } },
- { X86::XOR64rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_xorq, MCK_GR64, MCK_GR64 } },
- { X86::XOR64rr, Convert_Reg1_2_ImpReg1_1, { MCK_xorq, MCK_GR64, MCK_GR64 } },
- { X86::XOR64mr, Convert_Mem5_2_Reg1_1, { MCK_xorq, MCK_GR64, MCK_Mem } },
- { X86::XOR64ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_xorq, MCK_ImmSExt8, MCK_GR64 } },
- { X86::XOR64mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_xorq, MCK_ImmSExt8, MCK_Mem } },
- { X86::XOR64i32, Convert_Imm1_1, { MCK_xorq, MCK_Imm, MCK_RAX } },
- { X86::XOR64ri32, Convert_Reg1_2_ImpImm1_1, { MCK_xorq, MCK_Imm, MCK_GR64 } },
- { X86::XOR64mi32, Convert_Mem5_2_Imm1_1, { MCK_xorq, MCK_Imm, MCK_Mem } },
- { X86::XOR64rm, Convert_Reg1_2_ImpMem5_1, { MCK_xorq, MCK_Mem, MCK_GR64 } },
- { X86::XOR16rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_xorw, MCK_GR16, MCK_GR16 } },
- { X86::XOR16rr, Convert_Reg1_2_ImpReg1_1, { MCK_xorw, MCK_GR16, MCK_GR16 } },
- { X86::XOR16mr, Convert_Mem5_2_Reg1_1, { MCK_xorw, MCK_GR16, MCK_Mem } },
- { X86::XOR16ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_xorw, MCK_ImmSExt8, MCK_GR16 } },
- { X86::XOR16mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_xorw, MCK_ImmSExt8, MCK_Mem } },
- { X86::XOR16i16, Convert_Imm1_1, { MCK_xorw, MCK_Imm, MCK_AX } },
- { X86::XOR16ri, Convert_Reg1_2_ImpImm1_1, { MCK_xorw, MCK_Imm, MCK_GR16 } },
- { X86::XOR16mi, Convert_Mem5_2_Imm1_1, { MCK_xorw, MCK_Imm, MCK_Mem } },
- { X86::XOR16rm, Convert_Reg1_2_ImpMem5_1, { MCK_xorw, MCK_Mem, MCK_GR16 } },
- { X86::BLENDPDrri, Convert_Reg1_3_ImpReg1_2_ImmSExt81_1, { MCK_blendpd, MCK_ImmSExt8, MCK_FR32, MCK_FR32 } },
- { X86::BLENDPDrmi, Convert_Reg1_3_ImpMem5_2_ImmSExt81_1, { MCK_blendpd, MCK_ImmSExt8, MCK_Mem, MCK_FR32 } },
- { X86::BLENDPSrri, Convert_Reg1_3_ImpReg1_2_ImmSExt81_1, { MCK_blendps, MCK_ImmSExt8, MCK_FR32, MCK_FR32 } },
- { X86::BLENDPSrmi, Convert_Reg1_3_ImpMem5_2_ImmSExt81_1, { MCK_blendps, MCK_ImmSExt8, MCK_Mem, MCK_FR32 } },
- { X86::BLENDVPDrr0, Convert_Reg1_3_ImpReg1_2, { MCK_blendvpd, MCK_XMM0, MCK_FR32, MCK_FR32 } },
- { X86::BLENDVPDrm0, Convert_Reg1_3_ImpMem5_2, { MCK_blendvpd, MCK_XMM0, MCK_Mem, MCK_FR32 } },
- { X86::BLENDVPSrr0, Convert_Reg1_3_ImpReg1_2, { MCK_blendvps, MCK_XMM0, MCK_FR32, MCK_FR32 } },
- { X86::BLENDVPSrm0, Convert_Reg1_3_ImpMem5_2, { MCK_blendvps, MCK_XMM0, MCK_Mem, MCK_FR32 } },
- { X86::DPPDrri, Convert_Reg1_3_ImpReg1_2_ImmSExt81_1, { MCK_dppd, MCK_ImmSExt8, MCK_FR32, MCK_FR32 } },
- { X86::DPPDrmi, Convert_Reg1_3_ImpMem5_2_ImmSExt81_1, { MCK_dppd, MCK_ImmSExt8, MCK_Mem, MCK_FR32 } },
- { X86::DPPSrri, Convert_Reg1_3_ImpReg1_2_ImmSExt81_1, { MCK_dpps, MCK_ImmSExt8, MCK_FR32, MCK_FR32 } },
- { X86::DPPSrmi, Convert_Reg1_3_ImpMem5_2_ImmSExt81_1, { MCK_dpps, MCK_ImmSExt8, MCK_Mem, MCK_FR32 } },
- { X86::EXTRACTPSrr, Convert_Reg1_3_Reg1_2_ImmSExt81_1, { MCK_extractps, MCK_ImmSExt8, MCK_FR32, MCK_GR32 } },
- { X86::EXTRACTPSmr, Convert_Mem5_3_Reg1_2_ImmSExt81_1, { MCK_extractps, MCK_ImmSExt8, MCK_FR32, MCK_Mem } },
- { X86::IMUL32rri8, Convert_Reg1_3_Reg1_2_ImmSExt81_1, { MCK_imull, MCK_ImmSExt8, MCK_GR32, MCK_GR32 } },
- { X86::IMUL32rmi8, Convert_Reg1_3_Mem5_2_ImmSExt81_1, { MCK_imull, MCK_ImmSExt8, MCK_Mem, MCK_GR32 } },
- { X86::IMUL32rri, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_imull, MCK_Imm, MCK_GR32, MCK_GR32 } },
- { X86::IMUL32rmi, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_imull, MCK_Imm, MCK_Mem, MCK_GR32 } },
- { X86::IMUL64rri8, Convert_Reg1_3_Reg1_2_ImmSExt81_1, { MCK_imulq, MCK_ImmSExt8, MCK_GR64, MCK_GR64 } },
- { X86::IMUL64rmi8, Convert_Reg1_3_Mem5_2_ImmSExt81_1, { MCK_imulq, MCK_ImmSExt8, MCK_Mem, MCK_GR64 } },
- { X86::IMUL64rri32, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_imulq, MCK_Imm, MCK_GR64, MCK_GR64 } },
- { X86::IMUL64rmi32, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_imulq, MCK_Imm, MCK_Mem, MCK_GR64 } },
- { X86::IMUL16rri8, Convert_Reg1_3_Reg1_2_ImmSExt81_1, { MCK_imulw, MCK_ImmSExt8, MCK_GR16, MCK_GR16 } },
- { X86::IMUL16rmi8, Convert_Reg1_3_Mem5_2_ImmSExt81_1, { MCK_imulw, MCK_ImmSExt8, MCK_Mem, MCK_GR16 } },
- { X86::IMUL16rri, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_imulw, MCK_Imm, MCK_GR16, MCK_GR16 } },
- { X86::IMUL16rmi, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_imulw, MCK_Imm, MCK_Mem, MCK_GR16 } },
- { X86::INSERTPSrr, Convert_Reg1_3_ImpReg1_2_ImmSExt81_1, { MCK_insertps, MCK_ImmSExt8, MCK_FR32, MCK_FR32 } },
- { X86::INSERTPSrm, Convert_Reg1_3_ImpMem5_2_ImmSExt81_1, { MCK_insertps, MCK_ImmSExt8, MCK_Mem, MCK_FR32 } },
- { X86::MPSADBWrri, Convert_Reg1_3_ImpReg1_2_ImmSExt81_1, { MCK_mpsadbw, MCK_ImmSExt8, MCK_FR32, MCK_FR32 } },
- { X86::MPSADBWrmi, Convert_Reg1_3_ImpMem5_2_ImmSExt81_1, { MCK_mpsadbw, MCK_ImmSExt8, MCK_Mem, MCK_FR32 } },
- { X86::PALIGNR64rr, Convert_Reg1_3_ImpReg1_2_Imm1_1, { MCK_palignr, MCK_Imm, MCK_VR64, MCK_VR64 } },
- { X86::PALIGNR128rr, Convert_Reg1_3_ImpReg1_2_Imm1_1, { MCK_palignr, MCK_Imm, MCK_FR32, MCK_FR32 } },
- { X86::PALIGNR64rm, Convert_Reg1_3_ImpMem5_2_Imm1_1, { MCK_palignr, MCK_Imm, MCK_Mem, MCK_VR64 } },
- { X86::PALIGNR128rm, Convert_Reg1_3_ImpMem5_2_Imm1_1, { MCK_palignr, MCK_Imm, MCK_Mem, MCK_FR32 } },
- { X86::PBLENDVBrr0, Convert_Reg1_3_ImpReg1_2, { MCK_pblendvb, MCK_XMM0, MCK_FR32, MCK_FR32 } },
- { X86::PBLENDVBrm0, Convert_Reg1_3_ImpMem5_2, { MCK_pblendvb, MCK_XMM0, MCK_Mem, MCK_FR32 } },
- { X86::PBLENDWrri, Convert_Reg1_3_ImpReg1_2_ImmSExt81_1, { MCK_pblendw, MCK_ImmSExt8, MCK_FR32, MCK_FR32 } },
- { X86::PBLENDWrmi, Convert_Reg1_3_ImpMem5_2_ImmSExt81_1, { MCK_pblendw, MCK_ImmSExt8, MCK_Mem, MCK_FR32 } },
- { X86::PCMPESTRIOrr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_FR32, MCK_FR32 } },
- { X86::PCMPESTRISrr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_FR32, MCK_FR32 } },
- { X86::PCMPESTRIZrr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_FR32, MCK_FR32 } },
- { X86::PCMPESTRIrr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_FR32, MCK_FR32 } },
- { X86::PCMPESTRICrr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_FR32, MCK_FR32 } },
- { X86::PCMPESTRIArr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_FR32, MCK_FR32 } },
- { X86::PCMPESTRIOrm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_Mem, MCK_FR32 } },
- { X86::PCMPESTRIrm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_Mem, MCK_FR32 } },
- { X86::PCMPESTRIZrm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_Mem, MCK_FR32 } },
- { X86::PCMPESTRISrm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_Mem, MCK_FR32 } },
- { X86::PCMPESTRIArm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_Mem, MCK_FR32 } },
- { X86::PCMPESTRICrm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_Mem, MCK_FR32 } },
- { X86::PCMPESTRM128rr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpestrm, MCK_Imm, MCK_FR32, MCK_FR32 } },
- { X86::PCMPESTRM128rm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpestrm, MCK_Imm, MCK_Mem, MCK_FR32 } },
- { X86::PCMPISTRIArr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_FR32, MCK_FR32 } },
- { X86::PCMPISTRICrr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_FR32, MCK_FR32 } },
- { X86::PCMPISTRIrr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_FR32, MCK_FR32 } },
- { X86::PCMPISTRIOrr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_FR32, MCK_FR32 } },
- { X86::PCMPISTRISrr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_FR32, MCK_FR32 } },
- { X86::PCMPISTRIZrr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_FR32, MCK_FR32 } },
- { X86::PCMPISTRIArm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_Mem, MCK_FR32 } },
- { X86::PCMPISTRICrm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_Mem, MCK_FR32 } },
- { X86::PCMPISTRIrm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_Mem, MCK_FR32 } },
- { X86::PCMPISTRIOrm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_Mem, MCK_FR32 } },
- { X86::PCMPISTRISrm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_Mem, MCK_FR32 } },
- { X86::PCMPISTRIZrm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_Mem, MCK_FR32 } },
- { X86::PCMPISTRM128rr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpistrm, MCK_Imm, MCK_FR32, MCK_FR32 } },
- { X86::PCMPISTRM128rm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpistrm, MCK_Imm, MCK_Mem, MCK_FR32 } },
- { X86::PEXTRBrr, Convert_Reg1_3_Reg1_2_ImmSExt81_1, { MCK_pextrb, MCK_ImmSExt8, MCK_FR32, MCK_GR32 } },
- { X86::PEXTRBmr, Convert_Mem5_3_Reg1_2_ImmSExt81_1, { MCK_pextrb, MCK_ImmSExt8, MCK_FR32, MCK_Mem } },
- { X86::PEXTRDrr, Convert_Reg1_3_Reg1_2_ImmSExt81_1, { MCK_pextrd, MCK_ImmSExt8, MCK_FR32, MCK_GR32 } },
- { X86::PEXTRDmr, Convert_Mem5_3_Reg1_2_ImmSExt81_1, { MCK_pextrd, MCK_ImmSExt8, MCK_FR32, MCK_Mem } },
- { X86::PEXTRQrr, Convert_Reg1_3_Reg1_2_ImmSExt81_1, { MCK_pextrq, MCK_ImmSExt8, MCK_FR32, MCK_GR64 } },
- { X86::PEXTRQmr, Convert_Mem5_3_Reg1_2_ImmSExt81_1, { MCK_pextrq, MCK_ImmSExt8, MCK_FR32, MCK_Mem } },
- { X86::MMX_PEXTRWri, Convert_Reg1_3_Reg1_2_ImmSExt81_1, { MCK_pextrw, MCK_ImmSExt8, MCK_VR64, MCK_GR32 } },
- { X86::PEXTRWri, Convert_Reg1_3_Reg1_2_ImmSExt81_1, { MCK_pextrw, MCK_ImmSExt8, MCK_FR32, MCK_GR32 } },
- { X86::PEXTRWmr, Convert_Mem5_3_Reg1_2_ImmSExt81_1, { MCK_pextrw, MCK_ImmSExt8, MCK_FR32, MCK_Mem } },
- { X86::PINSRBrr, Convert_Reg1_3_ImpReg1_2_ImmSExt81_1, { MCK_pinsrb, MCK_ImmSExt8, MCK_GR32, MCK_FR32 } },
- { X86::PINSRBrm, Convert_Reg1_3_ImpMem5_2_ImmSExt81_1, { MCK_pinsrb, MCK_ImmSExt8, MCK_Mem, MCK_FR32 } },
- { X86::PINSRDrr, Convert_Reg1_3_ImpReg1_2_ImmSExt81_1, { MCK_pinsrd, MCK_ImmSExt8, MCK_GR32, MCK_FR32 } },
- { X86::PINSRDrm, Convert_Reg1_3_ImpMem5_2_ImmSExt81_1, { MCK_pinsrd, MCK_ImmSExt8, MCK_Mem, MCK_FR32 } },
- { X86::PINSRQrr, Convert_Reg1_3_ImpReg1_2_ImmSExt81_1, { MCK_pinsrq, MCK_ImmSExt8, MCK_GR64, MCK_FR32 } },
- { X86::PINSRQrm, Convert_Reg1_3_ImpMem5_2_ImmSExt81_1, { MCK_pinsrq, MCK_ImmSExt8, MCK_Mem, MCK_FR32 } },
- { X86::MMX_PINSRWrri, Convert_Reg1_3_ImpReg1_2_ImmSExt81_1, { MCK_pinsrw, MCK_ImmSExt8, MCK_GR32, MCK_VR64 } },
- { X86::PINSRWrri, Convert_Reg1_3_ImpReg1_2_ImmSExt81_1, { MCK_pinsrw, MCK_ImmSExt8, MCK_GR32, MCK_FR32 } },
- { X86::MMX_PINSRWrmi, Convert_Reg1_3_ImpMem5_2_ImmSExt81_1, { MCK_pinsrw, MCK_ImmSExt8, MCK_Mem, MCK_VR64 } },
- { X86::PINSRWrmi, Convert_Reg1_3_ImpMem5_2_ImmSExt81_1, { MCK_pinsrw, MCK_ImmSExt8, MCK_Mem, MCK_FR32 } },
- { X86::PSHUFDri, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pshufd, MCK_Imm, MCK_FR32, MCK_FR32 } },
- { X86::PSHUFDmi, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pshufd, MCK_Imm, MCK_Mem, MCK_FR32 } },
- { X86::PSHUFHWri, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pshufhw, MCK_Imm, MCK_FR32, MCK_FR32 } },
- { X86::PSHUFHWmi, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pshufhw, MCK_Imm, MCK_Mem, MCK_FR32 } },
- { X86::PSHUFLWri, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pshuflw, MCK_Imm, MCK_FR32, MCK_FR32 } },
- { X86::PSHUFLWmi, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pshuflw, MCK_Imm, MCK_Mem, MCK_FR32 } },
- { X86::MMX_PSHUFWri, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pshufw, MCK_Imm, MCK_VR64, MCK_VR64 } },
- { X86::MMX_PSHUFWmi, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pshufw, MCK_Imm, MCK_Mem, MCK_VR64 } },
- { X86::SHLD32rrCL, Convert_Reg1_3_ImpReg1_2, { MCK_shldl, MCK_CL, MCK_GR32, MCK_GR32 } },
- { X86::SHLD32mrCL, Convert_Mem5_3_Reg1_2, { MCK_shldl, MCK_CL, MCK_GR32, MCK_Mem } },
- { X86::SHLD32rri8, Convert_Reg1_3_ImpReg1_2_Imm1_1, { MCK_shldl, MCK_Imm, MCK_GR32, MCK_GR32 } },
- { X86::SHLD32mri8, Convert_Mem5_3_Reg1_2_Imm1_1, { MCK_shldl, MCK_Imm, MCK_GR32, MCK_Mem } },
- { X86::SHLD64rrCL, Convert_Reg1_3_ImpReg1_2, { MCK_shldq, MCK_CL, MCK_GR64, MCK_GR64 } },
- { X86::SHLD64mrCL, Convert_Mem5_3_Reg1_2, { MCK_shldq, MCK_CL, MCK_GR64, MCK_Mem } },
- { X86::SHLD64rri8, Convert_Reg1_3_ImpReg1_2_Imm1_1, { MCK_shldq, MCK_Imm, MCK_GR64, MCK_GR64 } },
- { X86::SHLD64mri8, Convert_Mem5_3_Reg1_2_Imm1_1, { MCK_shldq, MCK_Imm, MCK_GR64, MCK_Mem } },
- { X86::SHLD16rrCL, Convert_Reg1_3_ImpReg1_2, { MCK_shldw, MCK_CL, MCK_GR16, MCK_GR16 } },
- { X86::SHLD16mrCL, Convert_Mem5_3_Reg1_2, { MCK_shldw, MCK_CL, MCK_GR16, MCK_Mem } },
- { X86::SHLD16rri8, Convert_Reg1_3_ImpReg1_2_Imm1_1, { MCK_shldw, MCK_Imm, MCK_GR16, MCK_GR16 } },
- { X86::SHLD16mri8, Convert_Mem5_3_Reg1_2_Imm1_1, { MCK_shldw, MCK_Imm, MCK_GR16, MCK_Mem } },
- { X86::SHRD32rrCL, Convert_Reg1_3_ImpReg1_2, { MCK_shrdl, MCK_CL, MCK_GR32, MCK_GR32 } },
- { X86::SHRD32mrCL, Convert_Mem5_3_Reg1_2, { MCK_shrdl, MCK_CL, MCK_GR32, MCK_Mem } },
- { X86::SHRD32rri8, Convert_Reg1_3_ImpReg1_2_Imm1_1, { MCK_shrdl, MCK_Imm, MCK_GR32, MCK_GR32 } },
- { X86::SHRD32mri8, Convert_Mem5_3_Reg1_2_Imm1_1, { MCK_shrdl, MCK_Imm, MCK_GR32, MCK_Mem } },
- { X86::SHRD64rrCL, Convert_Reg1_3_ImpReg1_2, { MCK_shrdq, MCK_CL, MCK_GR64, MCK_GR64 } },
- { X86::SHRD64mrCL, Convert_Mem5_3_Reg1_2, { MCK_shrdq, MCK_CL, MCK_GR64, MCK_Mem } },
- { X86::SHRD64rri8, Convert_Reg1_3_ImpReg1_2_Imm1_1, { MCK_shrdq, MCK_Imm, MCK_GR64, MCK_GR64 } },
- { X86::SHRD64mri8, Convert_Mem5_3_Reg1_2_Imm1_1, { MCK_shrdq, MCK_Imm, MCK_GR64, MCK_Mem } },
- { X86::SHRD16rrCL, Convert_Reg1_3_ImpReg1_2, { MCK_shrdw, MCK_CL, MCK_GR16, MCK_GR16 } },
- { X86::SHRD16mrCL, Convert_Mem5_3_Reg1_2, { MCK_shrdw, MCK_CL, MCK_GR16, MCK_Mem } },
- { X86::SHRD16rri8, Convert_Reg1_3_ImpReg1_2_Imm1_1, { MCK_shrdw, MCK_Imm, MCK_GR16, MCK_GR16 } },
- { X86::SHRD16mri8, Convert_Mem5_3_Reg1_2_Imm1_1, { MCK_shrdw, MCK_Imm, MCK_GR16, MCK_Mem } },
- { X86::SHUFPDrri, Convert_Reg1_3_ImpReg1_2_Imm1_1, { MCK_shufpd, MCK_Imm, MCK_FR32, MCK_FR32 } },
- { X86::SHUFPDrmi, Convert_Reg1_3_ImpMem5_2_Imm1_1, { MCK_shufpd, MCK_Imm, MCK_Mem, MCK_FR32 } },
- { X86::SHUFPSrri, Convert_Reg1_3_ImpReg1_2_Imm1_1, { MCK_shufps, MCK_Imm, MCK_FR32, MCK_FR32 } },
- { X86::SHUFPSrmi, Convert_Reg1_3_ImpMem5_2_Imm1_1, { MCK_shufps, MCK_Imm, MCK_Mem, MCK_FR32 } },
- { X86::CMPPDrri, Convert_Reg1_4_ImpReg1_3_Imm1_1, { MCK_cmp, MCK_Imm, MCK_pd, MCK_FR32, MCK_FR32 } },
- { X86::CMPPDrmi, Convert_Reg1_4_ImpMem5_3_Imm1_1, { MCK_cmp, MCK_Imm, MCK_pd, MCK_Mem, MCK_FR32 } },
- { X86::CMPPSrri, Convert_Reg1_4_ImpReg1_3_Imm1_1, { MCK_cmp, MCK_Imm, MCK_ps, MCK_FR32, MCK_FR32 } },
- { X86::CMPPSrmi, Convert_Reg1_4_ImpMem5_3_Imm1_1, { MCK_cmp, MCK_Imm, MCK_ps, MCK_Mem, MCK_FR32 } },
- { X86::CMPSDrr, Convert_Reg1_4_ImpReg1_3_Imm1_1, { MCK_cmp, MCK_Imm, MCK_sd, MCK_FR32, MCK_FR32 } },
- { X86::CMPSDrm, Convert_Reg1_4_ImpMem5_3_Imm1_1, { MCK_cmp, MCK_Imm, MCK_sd, MCK_Mem, MCK_FR32 } },
- { X86::CMPSSrr, Convert_Reg1_4_ImpReg1_3_Imm1_1, { MCK_cmp, MCK_Imm, MCK_ss, MCK_FR32, MCK_FR32 } },
- { X86::CMPSSrm, Convert_Reg1_4_ImpMem5_3_Imm1_1, { MCK_cmp, MCK_Imm, MCK_ss, MCK_Mem, MCK_FR32 } },
+ { X86::OUT16ir, Convert__ImmSExt81_2, { MCK_outw, MCK_AX, MCK_ImmSExt8 } },
+ { X86::PABSBrr64, Convert__Reg1_2__Reg1_1, { MCK_pabsb, MCK_VR64, MCK_VR64 } },
+ { X86::PABSBrr128, Convert__Reg1_2__Reg1_1, { MCK_pabsb, MCK_FR32, MCK_FR32 } },
+ { X86::PABSBrm64, Convert__Reg1_2__Mem5_1, { MCK_pabsb, MCK_Mem, MCK_VR64 } },
+ { X86::PABSBrm128, Convert__Reg1_2__Mem5_1, { MCK_pabsb, MCK_Mem, MCK_FR32 } },
+ { X86::PABSDrr64, Convert__Reg1_2__Reg1_1, { MCK_pabsd, MCK_VR64, MCK_VR64 } },
+ { X86::PABSDrr128, Convert__Reg1_2__Reg1_1, { MCK_pabsd, MCK_FR32, MCK_FR32 } },
+ { X86::PABSDrm64, Convert__Reg1_2__Mem5_1, { MCK_pabsd, MCK_Mem, MCK_VR64 } },
+ { X86::PABSDrm128, Convert__Reg1_2__Mem5_1, { MCK_pabsd, MCK_Mem, MCK_FR32 } },
+ { X86::PABSWrr64, Convert__Reg1_2__Reg1_1, { MCK_pabsw, MCK_VR64, MCK_VR64 } },
+ { X86::PABSWrr128, Convert__Reg1_2__Reg1_1, { MCK_pabsw, MCK_FR32, MCK_FR32 } },
+ { X86::PABSWrm64, Convert__Reg1_2__Mem5_1, { MCK_pabsw, MCK_Mem, MCK_VR64 } },
+ { X86::PABSWrm128, Convert__Reg1_2__Mem5_1, { MCK_pabsw, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PACKSSDWrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_packssdw, MCK_VR64, MCK_VR64 } },
+ { X86::PACKSSDWrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_packssdw, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PACKSSDWrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_packssdw, MCK_Mem, MCK_VR64 } },
+ { X86::PACKSSDWrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_packssdw, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PACKSSWBrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_packsswb, MCK_VR64, MCK_VR64 } },
+ { X86::PACKSSWBrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_packsswb, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PACKSSWBrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_packsswb, MCK_Mem, MCK_VR64 } },
+ { X86::PACKSSWBrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_packsswb, MCK_Mem, MCK_FR32 } },
+ { X86::PACKUSDWrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_packusdw, MCK_FR32, MCK_FR32 } },
+ { X86::PACKUSDWrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_packusdw, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PACKUSWBrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_packuswb, MCK_VR64, MCK_VR64 } },
+ { X86::PACKUSWBrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_packuswb, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PACKUSWBrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_packuswb, MCK_Mem, MCK_VR64 } },
+ { X86::PACKUSWBrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_packuswb, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PADDBrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_paddb, MCK_VR64, MCK_VR64 } },
+ { X86::PADDBrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_paddb, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PADDBrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_paddb, MCK_Mem, MCK_VR64 } },
+ { X86::PADDBrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_paddb, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PADDDrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_paddd, MCK_VR64, MCK_VR64 } },
+ { X86::PADDDrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_paddd, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PADDDrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_paddd, MCK_Mem, MCK_VR64 } },
+ { X86::PADDDrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_paddd, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PADDQrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_paddq, MCK_VR64, MCK_VR64 } },
+ { X86::PADDQrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_paddq, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PADDQrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_paddq, MCK_Mem, MCK_VR64 } },
+ { X86::PADDQrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_paddq, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PADDSBrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_paddsb, MCK_VR64, MCK_VR64 } },
+ { X86::PADDSBrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_paddsb, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PADDSBrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_paddsb, MCK_Mem, MCK_VR64 } },
+ { X86::PADDSBrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_paddsb, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PADDSWrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_paddsw, MCK_VR64, MCK_VR64 } },
+ { X86::PADDSWrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_paddsw, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PADDSWrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_paddsw, MCK_Mem, MCK_VR64 } },
+ { X86::PADDSWrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_paddsw, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PADDUSBrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_paddusb, MCK_VR64, MCK_VR64 } },
+ { X86::PADDUSBrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_paddusb, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PADDUSBrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_paddusb, MCK_Mem, MCK_VR64 } },
+ { X86::PADDUSBrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_paddusb, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PADDUSWrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_paddusw, MCK_VR64, MCK_VR64 } },
+ { X86::PADDUSWrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_paddusw, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PADDUSWrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_paddusw, MCK_Mem, MCK_VR64 } },
+ { X86::PADDUSWrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_paddusw, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PADDWrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_paddw, MCK_VR64, MCK_VR64 } },
+ { X86::PADDWrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_paddw, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PADDWrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_paddw, MCK_Mem, MCK_VR64 } },
+ { X86::PADDWrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_paddw, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PANDrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_pand, MCK_VR64, MCK_VR64 } },
+ { X86::PANDrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_pand, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PANDrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_pand, MCK_Mem, MCK_VR64 } },
+ { X86::PANDrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_pand, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PANDNrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_pandn, MCK_VR64, MCK_VR64 } },
+ { X86::PANDNrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_pandn, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PANDNrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_pandn, MCK_Mem, MCK_VR64 } },
+ { X86::PANDNrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_pandn, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PAVGBrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_pavgb, MCK_VR64, MCK_VR64 } },
+ { X86::PAVGBrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_pavgb, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PAVGBrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_pavgb, MCK_Mem, MCK_VR64 } },
+ { X86::PAVGBrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_pavgb, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PAVGWrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_pavgw, MCK_VR64, MCK_VR64 } },
+ { X86::PAVGWrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_pavgw, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PAVGWrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_pavgw, MCK_Mem, MCK_VR64 } },
+ { X86::PAVGWrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_pavgw, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PCMPEQBrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_pcmpeqb, MCK_VR64, MCK_VR64 } },
+ { X86::PCMPEQBrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_pcmpeqb, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PCMPEQBrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_pcmpeqb, MCK_Mem, MCK_VR64 } },
+ { X86::PCMPEQBrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_pcmpeqb, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PCMPEQDrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_pcmpeqd, MCK_VR64, MCK_VR64 } },
+ { X86::PCMPEQDrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_pcmpeqd, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PCMPEQDrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_pcmpeqd, MCK_Mem, MCK_VR64 } },
+ { X86::PCMPEQDrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_pcmpeqd, MCK_Mem, MCK_FR32 } },
+ { X86::PCMPEQQrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_pcmpeqq, MCK_FR32, MCK_FR32 } },
+ { X86::PCMPEQQrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_pcmpeqq, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PCMPEQWrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_pcmpeqw, MCK_VR64, MCK_VR64 } },
+ { X86::PCMPEQWrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_pcmpeqw, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PCMPEQWrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_pcmpeqw, MCK_Mem, MCK_VR64 } },
+ { X86::PCMPEQWrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_pcmpeqw, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PCMPGTBrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_pcmpgtb, MCK_VR64, MCK_VR64 } },
+ { X86::PCMPGTBrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_pcmpgtb, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PCMPGTBrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_pcmpgtb, MCK_Mem, MCK_VR64 } },
+ { X86::PCMPGTBrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_pcmpgtb, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PCMPGTDrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_pcmpgtd, MCK_VR64, MCK_VR64 } },
+ { X86::PCMPGTDrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_pcmpgtd, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PCMPGTDrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_pcmpgtd, MCK_Mem, MCK_VR64 } },
+ { X86::PCMPGTDrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_pcmpgtd, MCK_Mem, MCK_FR32 } },
+ { X86::PCMPGTQrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_pcmpgtq, MCK_FR32, MCK_FR32 } },
+ { X86::PCMPGTQrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_pcmpgtq, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PCMPGTWrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_pcmpgtw, MCK_VR64, MCK_VR64 } },
+ { X86::PCMPGTWrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_pcmpgtw, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PCMPGTWrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_pcmpgtw, MCK_Mem, MCK_VR64 } },
+ { X86::PCMPGTWrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_pcmpgtw, MCK_Mem, MCK_FR32 } },
+ { X86::PHADDDrr64, Convert__Reg1_2__Tie0__Reg1_1, { MCK_phaddd, MCK_VR64, MCK_VR64 } },
+ { X86::PHADDDrr128, Convert__Reg1_2__Tie0__Reg1_1, { MCK_phaddd, MCK_FR32, MCK_FR32 } },
+ { X86::PHADDDrm64, Convert__Reg1_2__Tie0__Mem5_1, { MCK_phaddd, MCK_Mem, MCK_VR64 } },
+ { X86::PHADDDrm128, Convert__Reg1_2__Tie0__Mem5_1, { MCK_phaddd, MCK_Mem, MCK_FR32 } },
+ { X86::PHADDSWrr64, Convert__Reg1_2__Tie0__Reg1_1, { MCK_phaddsw, MCK_VR64, MCK_VR64 } },
+ { X86::PHADDSWrr128, Convert__Reg1_2__Tie0__Reg1_1, { MCK_phaddsw, MCK_FR32, MCK_FR32 } },
+ { X86::PHADDSWrm64, Convert__Reg1_2__Tie0__Mem5_1, { MCK_phaddsw, MCK_Mem, MCK_VR64 } },
+ { X86::PHADDSWrm128, Convert__Reg1_2__Tie0__Mem5_1, { MCK_phaddsw, MCK_Mem, MCK_FR32 } },
+ { X86::PHADDWrr64, Convert__Reg1_2__Tie0__Reg1_1, { MCK_phaddw, MCK_VR64, MCK_VR64 } },
+ { X86::PHADDWrr128, Convert__Reg1_2__Tie0__Reg1_1, { MCK_phaddw, MCK_FR32, MCK_FR32 } },
+ { X86::PHADDWrm64, Convert__Reg1_2__Tie0__Mem5_1, { MCK_phaddw, MCK_Mem, MCK_VR64 } },
+ { X86::PHADDWrm128, Convert__Reg1_2__Tie0__Mem5_1, { MCK_phaddw, MCK_Mem, MCK_FR32 } },
+ { X86::PHMINPOSUWrr128, Convert__Reg1_2__Reg1_1, { MCK_phminposuw, MCK_FR32, MCK_FR32 } },
+ { X86::PHMINPOSUWrm128, Convert__Reg1_2__Mem5_1, { MCK_phminposuw, MCK_Mem, MCK_FR32 } },
+ { X86::PHSUBDrr64, Convert__Reg1_2__Tie0__Reg1_1, { MCK_phsubd, MCK_VR64, MCK_VR64 } },
+ { X86::PHSUBDrr128, Convert__Reg1_2__Tie0__Reg1_1, { MCK_phsubd, MCK_FR32, MCK_FR32 } },
+ { X86::PHSUBDrm64, Convert__Reg1_2__Tie0__Mem5_1, { MCK_phsubd, MCK_Mem, MCK_VR64 } },
+ { X86::PHSUBDrm128, Convert__Reg1_2__Tie0__Mem5_1, { MCK_phsubd, MCK_Mem, MCK_FR32 } },
+ { X86::PHSUBSWrr64, Convert__Reg1_2__Tie0__Reg1_1, { MCK_phsubsw, MCK_VR64, MCK_VR64 } },
+ { X86::PHSUBSWrr128, Convert__Reg1_2__Tie0__Reg1_1, { MCK_phsubsw, MCK_FR32, MCK_FR32 } },
+ { X86::PHSUBSWrm64, Convert__Reg1_2__Tie0__Mem5_1, { MCK_phsubsw, MCK_Mem, MCK_VR64 } },
+ { X86::PHSUBSWrm128, Convert__Reg1_2__Tie0__Mem5_1, { MCK_phsubsw, MCK_Mem, MCK_FR32 } },
+ { X86::PHSUBWrr64, Convert__Reg1_2__Tie0__Reg1_1, { MCK_phsubw, MCK_VR64, MCK_VR64 } },
+ { X86::PHSUBWrr128, Convert__Reg1_2__Tie0__Reg1_1, { MCK_phsubw, MCK_FR32, MCK_FR32 } },
+ { X86::PHSUBWrm64, Convert__Reg1_2__Tie0__Mem5_1, { MCK_phsubw, MCK_Mem, MCK_VR64 } },
+ { X86::PHSUBWrm128, Convert__Reg1_2__Tie0__Mem5_1, { MCK_phsubw, MCK_Mem, MCK_FR32 } },
+ { X86::PMADDUBSWrr64, Convert__Reg1_2__Tie0__Reg1_1, { MCK_pmaddubsw, MCK_VR64, MCK_VR64 } },
+ { X86::PMADDUBSWrr128, Convert__Reg1_2__Tie0__Reg1_1, { MCK_pmaddubsw, MCK_FR32, MCK_FR32 } },
+ { X86::PMADDUBSWrm64, Convert__Reg1_2__Tie0__Mem5_1, { MCK_pmaddubsw, MCK_Mem, MCK_VR64 } },
+ { X86::PMADDUBSWrm128, Convert__Reg1_2__Tie0__Mem5_1, { MCK_pmaddubsw, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PMADDWDrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_pmaddwd, MCK_VR64, MCK_VR64 } },
+ { X86::PMADDWDrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_pmaddwd, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PMADDWDrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_pmaddwd, MCK_Mem, MCK_VR64 } },
+ { X86::PMADDWDrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_pmaddwd, MCK_Mem, MCK_FR32 } },
+ { X86::PMAXSBrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_pmaxsb, MCK_FR32, MCK_FR32 } },
+ { X86::PMAXSBrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_pmaxsb, MCK_Mem, MCK_FR32 } },
+ { X86::PMAXSDrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_pmaxsd, MCK_FR32, MCK_FR32 } },
+ { X86::PMAXSDrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_pmaxsd, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PMAXSWrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_pmaxsw, MCK_VR64, MCK_VR64 } },
+ { X86::PMAXSWrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_pmaxsw, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PMAXSWrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_pmaxsw, MCK_Mem, MCK_VR64 } },
+ { X86::PMAXSWrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_pmaxsw, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PMAXUBrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_pmaxub, MCK_VR64, MCK_VR64 } },
+ { X86::PMAXUBrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_pmaxub, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PMAXUBrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_pmaxub, MCK_Mem, MCK_VR64 } },
+ { X86::PMAXUBrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_pmaxub, MCK_Mem, MCK_FR32 } },
+ { X86::PMAXUDrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_pmaxud, MCK_FR32, MCK_FR32 } },
+ { X86::PMAXUDrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_pmaxud, MCK_Mem, MCK_FR32 } },
+ { X86::PMAXUWrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_pmaxuw, MCK_FR32, MCK_FR32 } },
+ { X86::PMAXUWrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_pmaxuw, MCK_Mem, MCK_FR32 } },
+ { X86::PMINSBrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_pminsb, MCK_FR32, MCK_FR32 } },
+ { X86::PMINSBrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_pminsb, MCK_Mem, MCK_FR32 } },
+ { X86::PMINSDrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_pminsd, MCK_FR32, MCK_FR32 } },
+ { X86::PMINSDrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_pminsd, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PMINSWrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_pminsw, MCK_VR64, MCK_VR64 } },
+ { X86::PMINSWrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_pminsw, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PMINSWrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_pminsw, MCK_Mem, MCK_VR64 } },
+ { X86::PMINSWrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_pminsw, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PMINUBrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_pminub, MCK_VR64, MCK_VR64 } },
+ { X86::PMINUBrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_pminub, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PMINUBrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_pminub, MCK_Mem, MCK_VR64 } },
+ { X86::PMINUBrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_pminub, MCK_Mem, MCK_FR32 } },
+ { X86::PMINUDrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_pminud, MCK_FR32, MCK_FR32 } },
+ { X86::PMINUDrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_pminud, MCK_Mem, MCK_FR32 } },
+ { X86::PMINUWrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_pminuw, MCK_FR32, MCK_FR32 } },
+ { X86::PMINUWrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_pminuw, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PMOVMSKBrr, Convert__Reg1_2__Reg1_1, { MCK_pmovmskb, MCK_VR64, MCK_GR32 } },
+ { X86::PMOVMSKBrr, Convert__Reg1_2__Reg1_1, { MCK_pmovmskb, MCK_FR32, MCK_GR32 } },
+ { X86::PMOVSXBDrr, Convert__Reg1_2__Reg1_1, { MCK_pmovsxbd, MCK_FR32, MCK_FR32 } },
+ { X86::PMOVSXBDrm, Convert__Reg1_2__Mem5_1, { MCK_pmovsxbd, MCK_Mem, MCK_FR32 } },
+ { X86::PMOVSXBQrr, Convert__Reg1_2__Reg1_1, { MCK_pmovsxbq, MCK_FR32, MCK_FR32 } },
+ { X86::PMOVSXBQrm, Convert__Reg1_2__Mem5_1, { MCK_pmovsxbq, MCK_Mem, MCK_FR32 } },
+ { X86::PMOVSXBWrr, Convert__Reg1_2__Reg1_1, { MCK_pmovsxbw, MCK_FR32, MCK_FR32 } },
+ { X86::PMOVSXBWrm, Convert__Reg1_2__Mem5_1, { MCK_pmovsxbw, MCK_Mem, MCK_FR32 } },
+ { X86::PMOVSXDQrr, Convert__Reg1_2__Reg1_1, { MCK_pmovsxdq, MCK_FR32, MCK_FR32 } },
+ { X86::PMOVSXDQrm, Convert__Reg1_2__Mem5_1, { MCK_pmovsxdq, MCK_Mem, MCK_FR32 } },
+ { X86::PMOVSXWDrr, Convert__Reg1_2__Reg1_1, { MCK_pmovsxwd, MCK_FR32, MCK_FR32 } },
+ { X86::PMOVSXWDrm, Convert__Reg1_2__Mem5_1, { MCK_pmovsxwd, MCK_Mem, MCK_FR32 } },
+ { X86::PMOVSXWQrr, Convert__Reg1_2__Reg1_1, { MCK_pmovsxwq, MCK_FR32, MCK_FR32 } },
+ { X86::PMOVSXWQrm, Convert__Reg1_2__Mem5_1, { MCK_pmovsxwq, MCK_Mem, MCK_FR32 } },
+ { X86::PMOVZXBDrr, Convert__Reg1_2__Reg1_1, { MCK_pmovzxbd, MCK_FR32, MCK_FR32 } },
+ { X86::PMOVZXBDrm, Convert__Reg1_2__Mem5_1, { MCK_pmovzxbd, MCK_Mem, MCK_FR32 } },
+ { X86::PMOVZXBQrr, Convert__Reg1_2__Reg1_1, { MCK_pmovzxbq, MCK_FR32, MCK_FR32 } },
+ { X86::PMOVZXBQrm, Convert__Reg1_2__Mem5_1, { MCK_pmovzxbq, MCK_Mem, MCK_FR32 } },
+ { X86::PMOVZXBWrr, Convert__Reg1_2__Reg1_1, { MCK_pmovzxbw, MCK_FR32, MCK_FR32 } },
+ { X86::PMOVZXBWrm, Convert__Reg1_2__Mem5_1, { MCK_pmovzxbw, MCK_Mem, MCK_FR32 } },
+ { X86::PMOVZXDQrr, Convert__Reg1_2__Reg1_1, { MCK_pmovzxdq, MCK_FR32, MCK_FR32 } },
+ { X86::PMOVZXDQrm, Convert__Reg1_2__Mem5_1, { MCK_pmovzxdq, MCK_Mem, MCK_FR32 } },
+ { X86::PMOVZXWDrr, Convert__Reg1_2__Reg1_1, { MCK_pmovzxwd, MCK_FR32, MCK_FR32 } },
+ { X86::PMOVZXWDrm, Convert__Reg1_2__Mem5_1, { MCK_pmovzxwd, MCK_Mem, MCK_FR32 } },
+ { X86::PMOVZXWQrr, Convert__Reg1_2__Reg1_1, { MCK_pmovzxwq, MCK_FR32, MCK_FR32 } },
+ { X86::PMOVZXWQrm, Convert__Reg1_2__Mem5_1, { MCK_pmovzxwq, MCK_Mem, MCK_FR32 } },
+ { X86::PMULDQrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_pmuldq, MCK_FR32, MCK_FR32 } },
+ { X86::PMULDQrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_pmuldq, MCK_Mem, MCK_FR32 } },
+ { X86::PMULHRSWrr64, Convert__Reg1_2__Tie0__Reg1_1, { MCK_pmulhrsw, MCK_VR64, MCK_VR64 } },
+ { X86::PMULHRSWrr128, Convert__Reg1_2__Tie0__Reg1_1, { MCK_pmulhrsw, MCK_FR32, MCK_FR32 } },
+ { X86::PMULHRSWrm64, Convert__Reg1_2__Tie0__Mem5_1, { MCK_pmulhrsw, MCK_Mem, MCK_VR64 } },
+ { X86::PMULHRSWrm128, Convert__Reg1_2__Tie0__Mem5_1, { MCK_pmulhrsw, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PMULHUWrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_pmulhuw, MCK_VR64, MCK_VR64 } },
+ { X86::PMULHUWrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_pmulhuw, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PMULHUWrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_pmulhuw, MCK_Mem, MCK_VR64 } },
+ { X86::PMULHUWrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_pmulhuw, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PMULHWrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_pmulhw, MCK_VR64, MCK_VR64 } },
+ { X86::PMULHWrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_pmulhw, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PMULHWrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_pmulhw, MCK_Mem, MCK_VR64 } },
+ { X86::PMULHWrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_pmulhw, MCK_Mem, MCK_FR32 } },
+ { X86::PMULLDrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_pmulld, MCK_FR32, MCK_FR32 } },
+ { X86::PMULLDrr_int, Convert__Reg1_2__Tie0__Reg1_1, { MCK_pmulld, MCK_FR32, MCK_FR32 } },
+ { X86::PMULLDrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_pmulld, MCK_Mem, MCK_FR32 } },
+ { X86::PMULLDrm_int, Convert__Reg1_2__Tie0__Mem5_1, { MCK_pmulld, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PMULLWrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_pmullw, MCK_VR64, MCK_VR64 } },
+ { X86::PMULLWrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_pmullw, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PMULLWrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_pmullw, MCK_Mem, MCK_VR64 } },
+ { X86::PMULLWrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_pmullw, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PMULUDQrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_pmuludq, MCK_VR64, MCK_VR64 } },
+ { X86::PMULUDQrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_pmuludq, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PMULUDQrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_pmuludq, MCK_Mem, MCK_VR64 } },
+ { X86::PMULUDQrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_pmuludq, MCK_Mem, MCK_FR32 } },
+ { X86::POPCNT32rr, Convert__Reg1_2__Reg1_1, { MCK_popcntl, MCK_GR32, MCK_GR32 } },
+ { X86::POPCNT32rm, Convert__Reg1_2__Mem5_1, { MCK_popcntl, MCK_Mem, MCK_GR32 } },
+ { X86::POPCNT64rr, Convert__Reg1_2__Reg1_1, { MCK_popcntq, MCK_GR64, MCK_GR64 } },
+ { X86::POPCNT64rm, Convert__Reg1_2__Mem5_1, { MCK_popcntq, MCK_Mem, MCK_GR64 } },
+ { X86::POPCNT16rr, Convert__Reg1_2__Reg1_1, { MCK_popcntw, MCK_GR16, MCK_GR16 } },
+ { X86::POPCNT16rm, Convert__Reg1_2__Mem5_1, { MCK_popcntw, MCK_Mem, MCK_GR16 } },
+ { X86::MMX_PORrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_por, MCK_VR64, MCK_VR64 } },
+ { X86::PORrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_por, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PORrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_por, MCK_Mem, MCK_VR64 } },
+ { X86::PORrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_por, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PSADBWrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_psadbw, MCK_VR64, MCK_VR64 } },
+ { X86::PSADBWrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_psadbw, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PSADBWrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_psadbw, MCK_Mem, MCK_VR64 } },
+ { X86::PSADBWrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_psadbw, MCK_Mem, MCK_FR32 } },
+ { X86::PSHUFBrr64, Convert__Reg1_2__Tie0__Reg1_1, { MCK_pshufb, MCK_VR64, MCK_VR64 } },
+ { X86::PSHUFBrr128, Convert__Reg1_2__Tie0__Reg1_1, { MCK_pshufb, MCK_FR32, MCK_FR32 } },
+ { X86::PSHUFBrm64, Convert__Reg1_2__Tie0__Mem5_1, { MCK_pshufb, MCK_Mem, MCK_VR64 } },
+ { X86::PSHUFBrm128, Convert__Reg1_2__Tie0__Mem5_1, { MCK_pshufb, MCK_Mem, MCK_FR32 } },
+ { X86::PSIGNBrr64, Convert__Reg1_2__Tie0__Reg1_1, { MCK_psignb, MCK_VR64, MCK_VR64 } },
+ { X86::PSIGNBrr128, Convert__Reg1_2__Tie0__Reg1_1, { MCK_psignb, MCK_FR32, MCK_FR32 } },
+ { X86::PSIGNBrm64, Convert__Reg1_2__Tie0__Mem5_1, { MCK_psignb, MCK_Mem, MCK_VR64 } },
+ { X86::PSIGNBrm128, Convert__Reg1_2__Tie0__Mem5_1, { MCK_psignb, MCK_Mem, MCK_FR32 } },
+ { X86::PSIGNDrr64, Convert__Reg1_2__Tie0__Reg1_1, { MCK_psignd, MCK_VR64, MCK_VR64 } },
+ { X86::PSIGNDrr128, Convert__Reg1_2__Tie0__Reg1_1, { MCK_psignd, MCK_FR32, MCK_FR32 } },
+ { X86::PSIGNDrm64, Convert__Reg1_2__Tie0__Mem5_1, { MCK_psignd, MCK_Mem, MCK_VR64 } },
+ { X86::PSIGNDrm128, Convert__Reg1_2__Tie0__Mem5_1, { MCK_psignd, MCK_Mem, MCK_FR32 } },
+ { X86::PSIGNWrr64, Convert__Reg1_2__Tie0__Reg1_1, { MCK_psignw, MCK_VR64, MCK_VR64 } },
+ { X86::PSIGNWrr128, Convert__Reg1_2__Tie0__Reg1_1, { MCK_psignw, MCK_FR32, MCK_FR32 } },
+ { X86::PSIGNWrm64, Convert__Reg1_2__Tie0__Mem5_1, { MCK_psignw, MCK_Mem, MCK_VR64 } },
+ { X86::PSIGNWrm128, Convert__Reg1_2__Tie0__Mem5_1, { MCK_psignw, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PSLLDrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_pslld, MCK_VR64, MCK_VR64 } },
+ { X86::PSLLDrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_pslld, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PSLLDri, Convert__Reg1_2__Tie0__ImmSExt81_1, { MCK_pslld, MCK_ImmSExt8, MCK_VR64 } },
+ { X86::PSLLDri, Convert__Reg1_2__Tie0__ImmSExt81_1, { MCK_pslld, MCK_ImmSExt8, MCK_FR32 } },
+ { X86::MMX_PSLLDrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_pslld, MCK_Mem, MCK_VR64 } },
+ { X86::PSLLDrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_pslld, MCK_Mem, MCK_FR32 } },
+ { X86::PSLLDQri, Convert__Reg1_2__Tie0__ImmSExt81_1, { MCK_pslldq, MCK_ImmSExt8, MCK_FR32 } },
+ { X86::MMX_PSLLQrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_psllq, MCK_VR64, MCK_VR64 } },
+ { X86::PSLLQrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_psllq, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PSLLQri, Convert__Reg1_2__Tie0__ImmSExt81_1, { MCK_psllq, MCK_ImmSExt8, MCK_VR64 } },
+ { X86::PSLLQri, Convert__Reg1_2__Tie0__ImmSExt81_1, { MCK_psllq, MCK_ImmSExt8, MCK_FR32 } },
+ { X86::MMX_PSLLQrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_psllq, MCK_Mem, MCK_VR64 } },
+ { X86::PSLLQrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_psllq, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PSLLWrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_psllw, MCK_VR64, MCK_VR64 } },
+ { X86::PSLLWrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_psllw, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PSLLWri, Convert__Reg1_2__Tie0__ImmSExt81_1, { MCK_psllw, MCK_ImmSExt8, MCK_VR64 } },
+ { X86::PSLLWri, Convert__Reg1_2__Tie0__ImmSExt81_1, { MCK_psllw, MCK_ImmSExt8, MCK_FR32 } },
+ { X86::MMX_PSLLWrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_psllw, MCK_Mem, MCK_VR64 } },
+ { X86::PSLLWrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_psllw, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PSRADrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_psrad, MCK_VR64, MCK_VR64 } },
+ { X86::PSRADrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_psrad, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PSRADri, Convert__Reg1_2__Tie0__ImmSExt81_1, { MCK_psrad, MCK_ImmSExt8, MCK_VR64 } },
+ { X86::PSRADri, Convert__Reg1_2__Tie0__ImmSExt81_1, { MCK_psrad, MCK_ImmSExt8, MCK_FR32 } },
+ { X86::MMX_PSRADrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_psrad, MCK_Mem, MCK_VR64 } },
+ { X86::PSRADrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_psrad, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PSRAWrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_psraw, MCK_VR64, MCK_VR64 } },
+ { X86::PSRAWrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_psraw, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PSRAWri, Convert__Reg1_2__Tie0__ImmSExt81_1, { MCK_psraw, MCK_ImmSExt8, MCK_VR64 } },
+ { X86::PSRAWri, Convert__Reg1_2__Tie0__ImmSExt81_1, { MCK_psraw, MCK_ImmSExt8, MCK_FR32 } },
+ { X86::MMX_PSRAWrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_psraw, MCK_Mem, MCK_VR64 } },
+ { X86::PSRAWrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_psraw, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PSRLDrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_psrld, MCK_VR64, MCK_VR64 } },
+ { X86::PSRLDrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_psrld, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PSRLDri, Convert__Reg1_2__Tie0__ImmSExt81_1, { MCK_psrld, MCK_ImmSExt8, MCK_VR64 } },
+ { X86::PSRLDri, Convert__Reg1_2__Tie0__ImmSExt81_1, { MCK_psrld, MCK_ImmSExt8, MCK_FR32 } },
+ { X86::MMX_PSRLDrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_psrld, MCK_Mem, MCK_VR64 } },
+ { X86::PSRLDrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_psrld, MCK_Mem, MCK_FR32 } },
+ { X86::PSRLDQri, Convert__Reg1_2__Tie0__ImmSExt81_1, { MCK_psrldq, MCK_ImmSExt8, MCK_FR32 } },
+ { X86::MMX_PSRLQrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_psrlq, MCK_VR64, MCK_VR64 } },
+ { X86::PSRLQrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_psrlq, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PSRLQri, Convert__Reg1_2__Tie0__ImmSExt81_1, { MCK_psrlq, MCK_ImmSExt8, MCK_VR64 } },
+ { X86::PSRLQri, Convert__Reg1_2__Tie0__ImmSExt81_1, { MCK_psrlq, MCK_ImmSExt8, MCK_FR32 } },
+ { X86::MMX_PSRLQrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_psrlq, MCK_Mem, MCK_VR64 } },
+ { X86::PSRLQrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_psrlq, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PSRLWrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_psrlw, MCK_VR64, MCK_VR64 } },
+ { X86::PSRLWrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_psrlw, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PSRLWri, Convert__Reg1_2__Tie0__ImmSExt81_1, { MCK_psrlw, MCK_ImmSExt8, MCK_VR64 } },
+ { X86::PSRLWri, Convert__Reg1_2__Tie0__ImmSExt81_1, { MCK_psrlw, MCK_ImmSExt8, MCK_FR32 } },
+ { X86::MMX_PSRLWrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_psrlw, MCK_Mem, MCK_VR64 } },
+ { X86::PSRLWrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_psrlw, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PSUBBrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_psubb, MCK_VR64, MCK_VR64 } },
+ { X86::PSUBBrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_psubb, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PSUBBrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_psubb, MCK_Mem, MCK_VR64 } },
+ { X86::PSUBBrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_psubb, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PSUBDrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_psubd, MCK_VR64, MCK_VR64 } },
+ { X86::PSUBDrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_psubd, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PSUBDrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_psubd, MCK_Mem, MCK_VR64 } },
+ { X86::PSUBDrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_psubd, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PSUBQrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_psubq, MCK_VR64, MCK_VR64 } },
+ { X86::PSUBQrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_psubq, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PSUBQrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_psubq, MCK_Mem, MCK_VR64 } },
+ { X86::PSUBQrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_psubq, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PSUBSBrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_psubsb, MCK_VR64, MCK_VR64 } },
+ { X86::PSUBSBrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_psubsb, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PSUBSBrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_psubsb, MCK_Mem, MCK_VR64 } },
+ { X86::PSUBSBrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_psubsb, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PSUBSWrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_psubsw, MCK_VR64, MCK_VR64 } },
+ { X86::PSUBSWrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_psubsw, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PSUBSWrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_psubsw, MCK_Mem, MCK_VR64 } },
+ { X86::PSUBSWrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_psubsw, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PSUBUSBrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_psubusb, MCK_VR64, MCK_VR64 } },
+ { X86::PSUBUSBrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_psubusb, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PSUBUSBrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_psubusb, MCK_Mem, MCK_VR64 } },
+ { X86::PSUBUSBrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_psubusb, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PSUBUSWrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_psubusw, MCK_VR64, MCK_VR64 } },
+ { X86::PSUBUSWrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_psubusw, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PSUBUSWrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_psubusw, MCK_Mem, MCK_VR64 } },
+ { X86::PSUBUSWrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_psubusw, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PSUBWrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_psubw, MCK_VR64, MCK_VR64 } },
+ { X86::PSUBWrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_psubw, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PSUBWrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_psubw, MCK_Mem, MCK_VR64 } },
+ { X86::PSUBWrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_psubw, MCK_Mem, MCK_FR32 } },
+ { X86::PTESTrr, Convert__Reg1_2__Reg1_1, { MCK_ptest, MCK_FR32, MCK_FR32 } },
+ { X86::PTESTrm, Convert__Reg1_2__Mem5_1, { MCK_ptest, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PUNPCKHBWrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_punpckhbw, MCK_VR64, MCK_VR64 } },
+ { X86::PUNPCKHBWrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_punpckhbw, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PUNPCKHBWrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_punpckhbw, MCK_Mem, MCK_VR64 } },
+ { X86::PUNPCKHBWrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_punpckhbw, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PUNPCKHDQrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_punpckhdq, MCK_VR64, MCK_VR64 } },
+ { X86::PUNPCKHDQrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_punpckhdq, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PUNPCKHDQrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_punpckhdq, MCK_Mem, MCK_VR64 } },
+ { X86::PUNPCKHDQrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_punpckhdq, MCK_Mem, MCK_FR32 } },
+ { X86::PUNPCKHQDQrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_punpckhqdq, MCK_FR32, MCK_FR32 } },
+ { X86::PUNPCKHQDQrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_punpckhqdq, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PUNPCKHWDrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_punpckhwd, MCK_VR64, MCK_VR64 } },
+ { X86::PUNPCKHWDrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_punpckhwd, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PUNPCKHWDrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_punpckhwd, MCK_Mem, MCK_VR64 } },
+ { X86::PUNPCKHWDrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_punpckhwd, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PUNPCKLBWrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_punpcklbw, MCK_VR64, MCK_VR64 } },
+ { X86::PUNPCKLBWrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_punpcklbw, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PUNPCKLBWrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_punpcklbw, MCK_Mem, MCK_VR64 } },
+ { X86::PUNPCKLBWrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_punpcklbw, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PUNPCKLDQrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_punpckldq, MCK_VR64, MCK_VR64 } },
+ { X86::PUNPCKLDQrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_punpckldq, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PUNPCKLDQrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_punpckldq, MCK_Mem, MCK_VR64 } },
+ { X86::PUNPCKLDQrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_punpckldq, MCK_Mem, MCK_FR32 } },
+ { X86::PUNPCKLQDQrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_punpcklqdq, MCK_FR32, MCK_FR32 } },
+ { X86::PUNPCKLQDQrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_punpcklqdq, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PUNPCKLWDrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_punpcklwd, MCK_VR64, MCK_VR64 } },
+ { X86::PUNPCKLWDrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_punpcklwd, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PUNPCKLWDrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_punpcklwd, MCK_Mem, MCK_VR64 } },
+ { X86::PUNPCKLWDrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_punpcklwd, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PXORrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_pxor, MCK_VR64, MCK_VR64 } },
+ { X86::PXORrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_pxor, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_PXORrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_pxor, MCK_Mem, MCK_VR64 } },
+ { X86::PXORrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_pxor, MCK_Mem, MCK_FR32 } },
+ { X86::RCL8r1, Convert__Reg1_2__Tie0, { MCK_rclb, MCK_1, MCK_GR8 } },
+ { X86::RCL8m1, Convert__Mem5_2, { MCK_rclb, MCK_1, MCK_Mem } },
+ { X86::RCL8rCL, Convert__Reg1_2__Tie0, { MCK_rclb, MCK_CL, MCK_GR8 } },
+ { X86::RCL8mCL, Convert__Mem5_2, { MCK_rclb, MCK_CL, MCK_Mem } },
+ { X86::RCL8ri, Convert__Reg1_2__Tie0__Imm1_1, { MCK_rclb, MCK_Imm, MCK_GR8 } },
+ { X86::RCL8mi, Convert__Mem5_2__Imm1_1, { MCK_rclb, MCK_Imm, MCK_Mem } },
+ { X86::RCL32r1, Convert__Reg1_2__Tie0, { MCK_rcll, MCK_1, MCK_GR32 } },
+ { X86::RCL32m1, Convert__Mem5_2, { MCK_rcll, MCK_1, MCK_Mem } },
+ { X86::RCL32rCL, Convert__Reg1_2__Tie0, { MCK_rcll, MCK_CL, MCK_GR32 } },
+ { X86::RCL32mCL, Convert__Mem5_2, { MCK_rcll, MCK_CL, MCK_Mem } },
+ { X86::RCL32ri, Convert__Reg1_2__Tie0__Imm1_1, { MCK_rcll, MCK_Imm, MCK_GR32 } },
+ { X86::RCL32mi, Convert__Mem5_2__Imm1_1, { MCK_rcll, MCK_Imm, MCK_Mem } },
+ { X86::RCL64r1, Convert__Reg1_2__Tie0, { MCK_rclq, MCK_1, MCK_GR64 } },
+ { X86::RCL64m1, Convert__Mem5_2, { MCK_rclq, MCK_1, MCK_Mem } },
+ { X86::RCL64rCL, Convert__Reg1_2__Tie0, { MCK_rclq, MCK_CL, MCK_GR64 } },
+ { X86::RCL64mCL, Convert__Mem5_2, { MCK_rclq, MCK_CL, MCK_Mem } },
+ { X86::RCL64ri, Convert__Reg1_2__Tie0__Imm1_1, { MCK_rclq, MCK_Imm, MCK_GR64 } },
+ { X86::RCL64mi, Convert__Mem5_2__Imm1_1, { MCK_rclq, MCK_Imm, MCK_Mem } },
+ { X86::RCL16r1, Convert__Reg1_2__Tie0, { MCK_rclw, MCK_1, MCK_GR16 } },
+ { X86::RCL16m1, Convert__Mem5_2, { MCK_rclw, MCK_1, MCK_Mem } },
+ { X86::RCL16rCL, Convert__Reg1_2__Tie0, { MCK_rclw, MCK_CL, MCK_GR16 } },
+ { X86::RCL16mCL, Convert__Mem5_2, { MCK_rclw, MCK_CL, MCK_Mem } },
+ { X86::RCL16ri, Convert__Reg1_2__Tie0__Imm1_1, { MCK_rclw, MCK_Imm, MCK_GR16 } },
+ { X86::RCL16mi, Convert__Mem5_2__Imm1_1, { MCK_rclw, MCK_Imm, MCK_Mem } },
+ { X86::RCPPSr, Convert__Reg1_2__Reg1_1, { MCK_rcpps, MCK_FR32, MCK_FR32 } },
+ { X86::RCPPSm, Convert__Reg1_2__Mem5_1, { MCK_rcpps, MCK_Mem, MCK_FR32 } },
+ { X86::RCPSSr, Convert__Reg1_2__Reg1_1, { MCK_rcpss, MCK_FR32, MCK_FR32 } },
+ { X86::RCPSSm, Convert__Reg1_2__Mem5_1, { MCK_rcpss, MCK_Mem, MCK_FR32 } },
+ { X86::RCR8r1, Convert__Reg1_2__Tie0, { MCK_rcrb, MCK_1, MCK_GR8 } },
+ { X86::RCR8m1, Convert__Mem5_2, { MCK_rcrb, MCK_1, MCK_Mem } },
+ { X86::RCR8rCL, Convert__Reg1_2__Tie0, { MCK_rcrb, MCK_CL, MCK_GR8 } },
+ { X86::RCR8mCL, Convert__Mem5_2, { MCK_rcrb, MCK_CL, MCK_Mem } },
+ { X86::RCR8ri, Convert__Reg1_2__Tie0__Imm1_1, { MCK_rcrb, MCK_Imm, MCK_GR8 } },
+ { X86::RCR8mi, Convert__Mem5_2__Imm1_1, { MCK_rcrb, MCK_Imm, MCK_Mem } },
+ { X86::RCR32r1, Convert__Reg1_2__Tie0, { MCK_rcrl, MCK_1, MCK_GR32 } },
+ { X86::RCR32m1, Convert__Mem5_2, { MCK_rcrl, MCK_1, MCK_Mem } },
+ { X86::RCR32rCL, Convert__Reg1_2__Tie0, { MCK_rcrl, MCK_CL, MCK_GR32 } },
+ { X86::RCR32mCL, Convert__Mem5_2, { MCK_rcrl, MCK_CL, MCK_Mem } },
+ { X86::RCR32ri, Convert__Reg1_2__Tie0__Imm1_1, { MCK_rcrl, MCK_Imm, MCK_GR32 } },
+ { X86::RCR32mi, Convert__Mem5_2__Imm1_1, { MCK_rcrl, MCK_Imm, MCK_Mem } },
+ { X86::RCR64r1, Convert__Reg1_2__Tie0, { MCK_rcrq, MCK_1, MCK_GR64 } },
+ { X86::RCR64m1, Convert__Mem5_2, { MCK_rcrq, MCK_1, MCK_Mem } },
+ { X86::RCR64rCL, Convert__Reg1_2__Tie0, { MCK_rcrq, MCK_CL, MCK_GR64 } },
+ { X86::RCR64mCL, Convert__Mem5_2, { MCK_rcrq, MCK_CL, MCK_Mem } },
+ { X86::RCR64ri, Convert__Reg1_2__Tie0__Imm1_1, { MCK_rcrq, MCK_Imm, MCK_GR64 } },
+ { X86::RCR64mi, Convert__Mem5_2__Imm1_1, { MCK_rcrq, MCK_Imm, MCK_Mem } },
+ { X86::RCR16r1, Convert__Reg1_2__Tie0, { MCK_rcrw, MCK_1, MCK_GR16 } },
+ { X86::RCR16m1, Convert__Mem5_2, { MCK_rcrw, MCK_1, MCK_Mem } },
+ { X86::RCR16rCL, Convert__Reg1_2__Tie0, { MCK_rcrw, MCK_CL, MCK_GR16 } },
+ { X86::RCR16mCL, Convert__Mem5_2, { MCK_rcrw, MCK_CL, MCK_Mem } },
+ { X86::RCR16ri, Convert__Reg1_2__Tie0__Imm1_1, { MCK_rcrw, MCK_Imm, MCK_GR16 } },
+ { X86::RCR16mi, Convert__Mem5_2__Imm1_1, { MCK_rcrw, MCK_Imm, MCK_Mem } },
+ { X86::ROL8rCL, Convert__Reg1_2__Tie0, { MCK_rolb, MCK_CL, MCK_GR8 } },
+ { X86::ROL8mCL, Convert__Mem5_2, { MCK_rolb, MCK_CL, MCK_Mem } },
+ { X86::ROL8ri, Convert__Reg1_2__Tie0__Imm1_1, { MCK_rolb, MCK_Imm, MCK_GR8 } },
+ { X86::ROL8mi, Convert__Mem5_2__Imm1_1, { MCK_rolb, MCK_Imm, MCK_Mem } },
+ { X86::ROL32rCL, Convert__Reg1_2__Tie0, { MCK_roll, MCK_CL, MCK_GR32 } },
+ { X86::ROL32mCL, Convert__Mem5_2, { MCK_roll, MCK_CL, MCK_Mem } },
+ { X86::ROL32ri, Convert__Reg1_2__Tie0__Imm1_1, { MCK_roll, MCK_Imm, MCK_GR32 } },
+ { X86::ROL32mi, Convert__Mem5_2__Imm1_1, { MCK_roll, MCK_Imm, MCK_Mem } },
+ { X86::ROL64rCL, Convert__Reg1_2__Tie0, { MCK_rolq, MCK_CL, MCK_GR64 } },
+ { X86::ROL64mCL, Convert__Mem5_2, { MCK_rolq, MCK_CL, MCK_Mem } },
+ { X86::ROL64ri, Convert__Reg1_2__Tie0__Imm1_1, { MCK_rolq, MCK_Imm, MCK_GR64 } },
+ { X86::ROL64mi, Convert__Mem5_2__Imm1_1, { MCK_rolq, MCK_Imm, MCK_Mem } },
+ { X86::ROL16rCL, Convert__Reg1_2__Tie0, { MCK_rolw, MCK_CL, MCK_GR16 } },
+ { X86::ROL16mCL, Convert__Mem5_2, { MCK_rolw, MCK_CL, MCK_Mem } },
+ { X86::ROL16ri, Convert__Reg1_2__Tie0__Imm1_1, { MCK_rolw, MCK_Imm, MCK_GR16 } },
+ { X86::ROL16mi, Convert__Mem5_2__Imm1_1, { MCK_rolw, MCK_Imm, MCK_Mem } },
+ { X86::ROR8rCL, Convert__Reg1_2__Tie0, { MCK_rorb, MCK_CL, MCK_GR8 } },
+ { X86::ROR8mCL, Convert__Mem5_2, { MCK_rorb, MCK_CL, MCK_Mem } },
+ { X86::ROR8ri, Convert__Reg1_2__Tie0__Imm1_1, { MCK_rorb, MCK_Imm, MCK_GR8 } },
+ { X86::ROR8mi, Convert__Mem5_2__Imm1_1, { MCK_rorb, MCK_Imm, MCK_Mem } },
+ { X86::ROR32rCL, Convert__Reg1_2__Tie0, { MCK_rorl, MCK_CL, MCK_GR32 } },
+ { X86::ROR32mCL, Convert__Mem5_2, { MCK_rorl, MCK_CL, MCK_Mem } },
+ { X86::ROR32ri, Convert__Reg1_2__Tie0__Imm1_1, { MCK_rorl, MCK_Imm, MCK_GR32 } },
+ { X86::ROR32mi, Convert__Mem5_2__Imm1_1, { MCK_rorl, MCK_Imm, MCK_Mem } },
+ { X86::ROR64rCL, Convert__Reg1_2__Tie0, { MCK_rorq, MCK_CL, MCK_GR64 } },
+ { X86::ROR64mCL, Convert__Mem5_2, { MCK_rorq, MCK_CL, MCK_Mem } },
+ { X86::ROR64ri, Convert__Reg1_2__Tie0__Imm1_1, { MCK_rorq, MCK_Imm, MCK_GR64 } },
+ { X86::ROR64mi, Convert__Mem5_2__Imm1_1, { MCK_rorq, MCK_Imm, MCK_Mem } },
+ { X86::ROR16rCL, Convert__Reg1_2__Tie0, { MCK_rorw, MCK_CL, MCK_GR16 } },
+ { X86::ROR16mCL, Convert__Mem5_2, { MCK_rorw, MCK_CL, MCK_Mem } },
+ { X86::ROR16ri, Convert__Reg1_2__Tie0__Imm1_1, { MCK_rorw, MCK_Imm, MCK_GR16 } },
+ { X86::ROR16mi, Convert__Mem5_2__Imm1_1, { MCK_rorw, MCK_Imm, MCK_Mem } },
+ { X86::RSQRTPSr, Convert__Reg1_2__Reg1_1, { MCK_rsqrtps, MCK_FR32, MCK_FR32 } },
+ { X86::RSQRTPSm, Convert__Reg1_2__Mem5_1, { MCK_rsqrtps, MCK_Mem, MCK_FR32 } },
+ { X86::RSQRTSSr, Convert__Reg1_2__Reg1_1, { MCK_rsqrtss, MCK_FR32, MCK_FR32 } },
+ { X86::RSQRTSSm, Convert__Reg1_2__Mem5_1, { MCK_rsqrtss, MCK_Mem, MCK_FR32 } },
+ { X86::SAR8rCL, Convert__Reg1_2__Tie0, { MCK_sarb, MCK_CL, MCK_GR8 } },
+ { X86::SAR8mCL, Convert__Mem5_2, { MCK_sarb, MCK_CL, MCK_Mem } },
+ { X86::SAR8ri, Convert__Reg1_2__Tie0__Imm1_1, { MCK_sarb, MCK_Imm, MCK_GR8 } },
+ { X86::SAR8mi, Convert__Mem5_2__Imm1_1, { MCK_sarb, MCK_Imm, MCK_Mem } },
+ { X86::SAR32rCL, Convert__Reg1_2__Tie0, { MCK_sarl, MCK_CL, MCK_GR32 } },
+ { X86::SAR32mCL, Convert__Mem5_2, { MCK_sarl, MCK_CL, MCK_Mem } },
+ { X86::SAR32ri, Convert__Reg1_2__Tie0__Imm1_1, { MCK_sarl, MCK_Imm, MCK_GR32 } },
+ { X86::SAR32mi, Convert__Mem5_2__Imm1_1, { MCK_sarl, MCK_Imm, MCK_Mem } },
+ { X86::SAR64rCL, Convert__Reg1_2__Tie0, { MCK_sarq, MCK_CL, MCK_GR64 } },
+ { X86::SAR64mCL, Convert__Mem5_2, { MCK_sarq, MCK_CL, MCK_Mem } },
+ { X86::SAR64ri, Convert__Reg1_2__Tie0__Imm1_1, { MCK_sarq, MCK_Imm, MCK_GR64 } },
+ { X86::SAR64mi, Convert__Mem5_2__Imm1_1, { MCK_sarq, MCK_Imm, MCK_Mem } },
+ { X86::SAR16rCL, Convert__Reg1_2__Tie0, { MCK_sarw, MCK_CL, MCK_GR16 } },
+ { X86::SAR16mCL, Convert__Mem5_2, { MCK_sarw, MCK_CL, MCK_Mem } },
+ { X86::SAR16ri, Convert__Reg1_2__Tie0__Imm1_1, { MCK_sarw, MCK_Imm, MCK_GR16 } },
+ { X86::SAR16mi, Convert__Mem5_2__Imm1_1, { MCK_sarw, MCK_Imm, MCK_Mem } },
+ { X86::SBB8rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_sbbb, MCK_GR8, MCK_GR8 } },
+ { X86::SBB8rr_REV, Convert__Reg1_2__Tie0__Reg1_1, { MCK_sbbb, MCK_GR8, MCK_GR8 } },
+ { X86::SBB8mr, Convert__Mem5_2__Reg1_1, { MCK_sbbb, MCK_GR8, MCK_Mem } },
+ { X86::SBB8i8, Convert__Imm1_1, { MCK_sbbb, MCK_Imm, MCK_AL } },
+ { X86::SBB8ri, Convert__Reg1_2__Tie0__Imm1_1, { MCK_sbbb, MCK_Imm, MCK_GR8 } },
+ { X86::SBB8mi, Convert__Mem5_2__Imm1_1, { MCK_sbbb, MCK_Imm, MCK_Mem } },
+ { X86::SBB8rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_sbbb, MCK_Mem, MCK_GR8 } },
+ { X86::SBB32rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_sbbl, MCK_GR32, MCK_GR32 } },
+ { X86::SBB32rr_REV, Convert__Reg1_2__Tie0__Reg1_1, { MCK_sbbl, MCK_GR32, MCK_GR32 } },
+ { X86::SBB32mr, Convert__Mem5_2__Reg1_1, { MCK_sbbl, MCK_GR32, MCK_Mem } },
+ { X86::SBB32ri8, Convert__Reg1_2__Tie0__ImmSExt81_1, { MCK_sbbl, MCK_ImmSExt8, MCK_GR32 } },
+ { X86::SBB32mi8, Convert__Mem5_2__ImmSExt81_1, { MCK_sbbl, MCK_ImmSExt8, MCK_Mem } },
+ { X86::SBB32i32, Convert__Imm1_1, { MCK_sbbl, MCK_Imm, MCK_EAX } },
+ { X86::SBB32ri, Convert__Reg1_2__Tie0__Imm1_1, { MCK_sbbl, MCK_Imm, MCK_GR32 } },
+ { X86::SBB32mi, Convert__Mem5_2__Imm1_1, { MCK_sbbl, MCK_Imm, MCK_Mem } },
+ { X86::SBB32rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_sbbl, MCK_Mem, MCK_GR32 } },
+ { X86::SBB64rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_sbbq, MCK_GR64, MCK_GR64 } },
+ { X86::SBB64rr_REV, Convert__Reg1_2__Tie0__Reg1_1, { MCK_sbbq, MCK_GR64, MCK_GR64 } },
+ { X86::SBB64mr, Convert__Mem5_2__Reg1_1, { MCK_sbbq, MCK_GR64, MCK_Mem } },
+ { X86::SBB64ri8, Convert__Reg1_2__Tie0__ImmSExt81_1, { MCK_sbbq, MCK_ImmSExt8, MCK_GR64 } },
+ { X86::SBB64mi8, Convert__Mem5_2__ImmSExt81_1, { MCK_sbbq, MCK_ImmSExt8, MCK_Mem } },
+ { X86::SBB64i32, Convert__Imm1_1, { MCK_sbbq, MCK_Imm, MCK_RAX } },
+ { X86::SBB64ri32, Convert__Reg1_2__Tie0__Imm1_1, { MCK_sbbq, MCK_Imm, MCK_GR64 } },
+ { X86::SBB64mi32, Convert__Mem5_2__Imm1_1, { MCK_sbbq, MCK_Imm, MCK_Mem } },
+ { X86::SBB64rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_sbbq, MCK_Mem, MCK_GR64 } },
+ { X86::SBB16rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_sbbw, MCK_GR16, MCK_GR16 } },
+ { X86::SBB16rr_REV, Convert__Reg1_2__Tie0__Reg1_1, { MCK_sbbw, MCK_GR16, MCK_GR16 } },
+ { X86::SBB16mr, Convert__Mem5_2__Reg1_1, { MCK_sbbw, MCK_GR16, MCK_Mem } },
+ { X86::SBB16ri8, Convert__Reg1_2__Tie0__ImmSExt81_1, { MCK_sbbw, MCK_ImmSExt8, MCK_GR16 } },
+ { X86::SBB16mi8, Convert__Mem5_2__ImmSExt81_1, { MCK_sbbw, MCK_ImmSExt8, MCK_Mem } },
+ { X86::SBB16i16, Convert__Imm1_1, { MCK_sbbw, MCK_Imm, MCK_AX } },
+ { X86::SBB16ri, Convert__Reg1_2__Tie0__Imm1_1, { MCK_sbbw, MCK_Imm, MCK_GR16 } },
+ { X86::SBB16mi, Convert__Mem5_2__Imm1_1, { MCK_sbbw, MCK_Imm, MCK_Mem } },
+ { X86::SBB16rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_sbbw, MCK_Mem, MCK_GR16 } },
+ { X86::SHL8rCL, Convert__Reg1_2__Tie0, { MCK_shlb, MCK_CL, MCK_GR8 } },
+ { X86::SHL8mCL, Convert__Mem5_2, { MCK_shlb, MCK_CL, MCK_Mem } },
+ { X86::SHL8ri, Convert__Reg1_2__Tie0__Imm1_1, { MCK_shlb, MCK_Imm, MCK_GR8 } },
+ { X86::SHL8mi, Convert__Mem5_2__Imm1_1, { MCK_shlb, MCK_Imm, MCK_Mem } },
+ { X86::SHL32rCL, Convert__Reg1_2__Tie0, { MCK_shll, MCK_CL, MCK_GR32 } },
+ { X86::SHL32mCL, Convert__Mem5_2, { MCK_shll, MCK_CL, MCK_Mem } },
+ { X86::SHL32ri, Convert__Reg1_2__Tie0__Imm1_1, { MCK_shll, MCK_Imm, MCK_GR32 } },
+ { X86::SHL32mi, Convert__Mem5_2__Imm1_1, { MCK_shll, MCK_Imm, MCK_Mem } },
+ { X86::SHL64rCL, Convert__Reg1_2__Tie0, { MCK_shlq, MCK_CL, MCK_GR64 } },
+ { X86::SHL64mCL, Convert__Mem5_2, { MCK_shlq, MCK_CL, MCK_Mem } },
+ { X86::SHL64ri, Convert__Reg1_2__Tie0__Imm1_1, { MCK_shlq, MCK_Imm, MCK_GR64 } },
+ { X86::SHL64mi, Convert__Mem5_2__Imm1_1, { MCK_shlq, MCK_Imm, MCK_Mem } },
+ { X86::SHL16rCL, Convert__Reg1_2__Tie0, { MCK_shlw, MCK_CL, MCK_GR16 } },
+ { X86::SHL16mCL, Convert__Mem5_2, { MCK_shlw, MCK_CL, MCK_Mem } },
+ { X86::SHL16ri, Convert__Reg1_2__Tie0__Imm1_1, { MCK_shlw, MCK_Imm, MCK_GR16 } },
+ { X86::SHL16mi, Convert__Mem5_2__Imm1_1, { MCK_shlw, MCK_Imm, MCK_Mem } },
+ { X86::SHR8rCL, Convert__Reg1_2__Tie0, { MCK_shrb, MCK_CL, MCK_GR8 } },
+ { X86::SHR8mCL, Convert__Mem5_2, { MCK_shrb, MCK_CL, MCK_Mem } },
+ { X86::SHR8ri, Convert__Reg1_2__Tie0__Imm1_1, { MCK_shrb, MCK_Imm, MCK_GR8 } },
+ { X86::SHR8mi, Convert__Mem5_2__Imm1_1, { MCK_shrb, MCK_Imm, MCK_Mem } },
+ { X86::SHR32rCL, Convert__Reg1_2__Tie0, { MCK_shrl, MCK_CL, MCK_GR32 } },
+ { X86::SHR32mCL, Convert__Mem5_2, { MCK_shrl, MCK_CL, MCK_Mem } },
+ { X86::SHR32ri, Convert__Reg1_2__Tie0__Imm1_1, { MCK_shrl, MCK_Imm, MCK_GR32 } },
+ { X86::SHR32mi, Convert__Mem5_2__Imm1_1, { MCK_shrl, MCK_Imm, MCK_Mem } },
+ { X86::SHR64rCL, Convert__Reg1_2__Tie0, { MCK_shrq, MCK_CL, MCK_GR64 } },
+ { X86::SHR64mCL, Convert__Mem5_2, { MCK_shrq, MCK_CL, MCK_Mem } },
+ { X86::SHR64ri, Convert__Reg1_2__Tie0__Imm1_1, { MCK_shrq, MCK_Imm, MCK_GR64 } },
+ { X86::SHR64mi, Convert__Mem5_2__Imm1_1, { MCK_shrq, MCK_Imm, MCK_Mem } },
+ { X86::SHR16rCL, Convert__Reg1_2__Tie0, { MCK_shrw, MCK_CL, MCK_GR16 } },
+ { X86::SHR16mCL, Convert__Mem5_2, { MCK_shrw, MCK_CL, MCK_Mem } },
+ { X86::SHR16ri, Convert__Reg1_2__Tie0__Imm1_1, { MCK_shrw, MCK_Imm, MCK_GR16 } },
+ { X86::SHR16mi, Convert__Mem5_2__Imm1_1, { MCK_shrw, MCK_Imm, MCK_Mem } },
+ { X86::SQRTPDr, Convert__Reg1_2__Reg1_1, { MCK_sqrtpd, MCK_FR32, MCK_FR32 } },
+ { X86::SQRTPDm, Convert__Reg1_2__Mem5_1, { MCK_sqrtpd, MCK_Mem, MCK_FR32 } },
+ { X86::SQRTPSr, Convert__Reg1_2__Reg1_1, { MCK_sqrtps, MCK_FR32, MCK_FR32 } },
+ { X86::SQRTPSm, Convert__Reg1_2__Mem5_1, { MCK_sqrtps, MCK_Mem, MCK_FR32 } },
+ { X86::SQRTSDr, Convert__Reg1_2__Reg1_1, { MCK_sqrtsd, MCK_FR32, MCK_FR32 } },
+ { X86::SQRTSDm, Convert__Reg1_2__Mem5_1, { MCK_sqrtsd, MCK_Mem, MCK_FR32 } },
+ { X86::SQRTSSr, Convert__Reg1_2__Reg1_1, { MCK_sqrtss, MCK_FR32, MCK_FR32 } },
+ { X86::SQRTSSm, Convert__Reg1_2__Mem5_1, { MCK_sqrtss, MCK_Mem, MCK_FR32 } },
+ { X86::SUB8rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_subb, MCK_GR8, MCK_GR8 } },
+ { X86::SUB8rr_REV, Convert__Reg1_2__Tie0__Reg1_1, { MCK_subb, MCK_GR8, MCK_GR8 } },
+ { X86::SUB8mr, Convert__Mem5_2__Reg1_1, { MCK_subb, MCK_GR8, MCK_Mem } },
+ { X86::SUB8i8, Convert__Imm1_1, { MCK_subb, MCK_Imm, MCK_AL } },
+ { X86::SUB8ri, Convert__Reg1_2__Tie0__Imm1_1, { MCK_subb, MCK_Imm, MCK_GR8 } },
+ { X86::SUB8mi, Convert__Mem5_2__Imm1_1, { MCK_subb, MCK_Imm, MCK_Mem } },
+ { X86::SUB8rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_subb, MCK_Mem, MCK_GR8 } },
+ { X86::SUB32rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_subl, MCK_GR32, MCK_GR32 } },
+ { X86::SUB32rr_REV, Convert__Reg1_2__Tie0__Reg1_1, { MCK_subl, MCK_GR32, MCK_GR32 } },
+ { X86::SUB32mr, Convert__Mem5_2__Reg1_1, { MCK_subl, MCK_GR32, MCK_Mem } },
+ { X86::SUB32ri8, Convert__Reg1_2__Tie0__ImmSExt81_1, { MCK_subl, MCK_ImmSExt8, MCK_GR32 } },
+ { X86::SUB32mi8, Convert__Mem5_2__ImmSExt81_1, { MCK_subl, MCK_ImmSExt8, MCK_Mem } },
+ { X86::SUB32i32, Convert__Imm1_1, { MCK_subl, MCK_Imm, MCK_EAX } },
+ { X86::SUB32ri, Convert__Reg1_2__Tie0__Imm1_1, { MCK_subl, MCK_Imm, MCK_GR32 } },
+ { X86::SUB32mi, Convert__Mem5_2__Imm1_1, { MCK_subl, MCK_Imm, MCK_Mem } },
+ { X86::SUB32rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_subl, MCK_Mem, MCK_GR32 } },
+ { X86::SUBPDrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_subpd, MCK_FR32, MCK_FR32 } },
+ { X86::SUBPDrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_subpd, MCK_Mem, MCK_FR32 } },
+ { X86::SUBPSrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_subps, MCK_FR32, MCK_FR32 } },
+ { X86::SUBPSrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_subps, MCK_Mem, MCK_FR32 } },
+ { X86::SUB64rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_subq, MCK_GR64, MCK_GR64 } },
+ { X86::SUB64rr_REV, Convert__Reg1_2__Tie0__Reg1_1, { MCK_subq, MCK_GR64, MCK_GR64 } },
+ { X86::SUB64mr, Convert__Mem5_2__Reg1_1, { MCK_subq, MCK_GR64, MCK_Mem } },
+ { X86::SUB64ri8, Convert__Reg1_2__Tie0__ImmSExt81_1, { MCK_subq, MCK_ImmSExt8, MCK_GR64 } },
+ { X86::SUB64mi8, Convert__Mem5_2__ImmSExt81_1, { MCK_subq, MCK_ImmSExt8, MCK_Mem } },
+ { X86::SUB64i32, Convert__Imm1_1, { MCK_subq, MCK_Imm, MCK_RAX } },
+ { X86::SUB64ri32, Convert__Reg1_2__Tie0__Imm1_1, { MCK_subq, MCK_Imm, MCK_GR64 } },
+ { X86::SUB64mi32, Convert__Mem5_2__Imm1_1, { MCK_subq, MCK_Imm, MCK_Mem } },
+ { X86::SUB64rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_subq, MCK_Mem, MCK_GR64 } },
+ { X86::SUBSDrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_subsd, MCK_FR32, MCK_FR32 } },
+ { X86::SUBSDrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_subsd, MCK_Mem, MCK_FR32 } },
+ { X86::SUBSSrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_subss, MCK_FR32, MCK_FR32 } },
+ { X86::SUBSSrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_subss, MCK_Mem, MCK_FR32 } },
+ { X86::SUB16rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_subw, MCK_GR16, MCK_GR16 } },
+ { X86::SUB16rr_REV, Convert__Reg1_2__Tie0__Reg1_1, { MCK_subw, MCK_GR16, MCK_GR16 } },
+ { X86::SUB16mr, Convert__Mem5_2__Reg1_1, { MCK_subw, MCK_GR16, MCK_Mem } },
+ { X86::SUB16ri8, Convert__Reg1_2__Tie0__ImmSExt81_1, { MCK_subw, MCK_ImmSExt8, MCK_GR16 } },
+ { X86::SUB16mi8, Convert__Mem5_2__ImmSExt81_1, { MCK_subw, MCK_ImmSExt8, MCK_Mem } },
+ { X86::SUB16i16, Convert__Imm1_1, { MCK_subw, MCK_Imm, MCK_AX } },
+ { X86::SUB16ri, Convert__Reg1_2__Tie0__Imm1_1, { MCK_subw, MCK_Imm, MCK_GR16 } },
+ { X86::SUB16mi, Convert__Mem5_2__Imm1_1, { MCK_subw, MCK_Imm, MCK_Mem } },
+ { X86::SUB16rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_subw, MCK_Mem, MCK_GR16 } },
+ { X86::TEST8rr, Convert__Reg1_2__Reg1_1, { MCK_testb, MCK_GR8, MCK_GR8 } },
+ { X86::TEST8i8, Convert__Imm1_1, { MCK_testb, MCK_Imm, MCK_AL } },
+ { X86::TEST8ri, Convert__Reg1_2__Imm1_1, { MCK_testb, MCK_Imm, MCK_GR8 } },
+ { X86::TEST8mi, Convert__Mem5_2__Imm1_1, { MCK_testb, MCK_Imm, MCK_Mem } },
+ { X86::TEST8rm, Convert__Reg1_2__Mem5_1, { MCK_testb, MCK_Mem, MCK_GR8 } },
+ { X86::TEST32rr, Convert__Reg1_2__Reg1_1, { MCK_testl, MCK_GR32, MCK_GR32 } },
+ { X86::TEST32i32, Convert__Imm1_1, { MCK_testl, MCK_Imm, MCK_EAX } },
+ { X86::TEST32ri, Convert__Reg1_2__Imm1_1, { MCK_testl, MCK_Imm, MCK_GR32 } },
+ { X86::TEST32mi, Convert__Mem5_2__Imm1_1, { MCK_testl, MCK_Imm, MCK_Mem } },
+ { X86::TEST32rm, Convert__Reg1_2__Mem5_1, { MCK_testl, MCK_Mem, MCK_GR32 } },
+ { X86::TEST64rr, Convert__Reg1_2__Reg1_1, { MCK_testq, MCK_GR64, MCK_GR64 } },
+ { X86::TEST64i32, Convert__Imm1_1, { MCK_testq, MCK_Imm, MCK_RAX } },
+ { X86::TEST64ri32, Convert__Reg1_2__Imm1_1, { MCK_testq, MCK_Imm, MCK_GR64 } },
+ { X86::TEST64mi32, Convert__Mem5_2__Imm1_1, { MCK_testq, MCK_Imm, MCK_Mem } },
+ { X86::TEST64rm, Convert__Reg1_2__Mem5_1, { MCK_testq, MCK_Mem, MCK_GR64 } },
+ { X86::TEST16rr, Convert__Reg1_2__Reg1_1, { MCK_testw, MCK_GR16, MCK_GR16 } },
+ { X86::TEST16i16, Convert__Imm1_1, { MCK_testw, MCK_Imm, MCK_AX } },
+ { X86::TEST16ri, Convert__Reg1_2__Imm1_1, { MCK_testw, MCK_Imm, MCK_GR16 } },
+ { X86::TEST16mi, Convert__Mem5_2__Imm1_1, { MCK_testw, MCK_Imm, MCK_Mem } },
+ { X86::TEST16rm, Convert__Reg1_2__Mem5_1, { MCK_testw, MCK_Mem, MCK_GR16 } },
+ { X86::UCOMISDrr, Convert__Reg1_2__Reg1_1, { MCK_ucomisd, MCK_FR32, MCK_FR32 } },
+ { X86::UCOMISDrm, Convert__Reg1_2__Mem5_1, { MCK_ucomisd, MCK_Mem, MCK_FR32 } },
+ { X86::UCOMISSrr, Convert__Reg1_2__Reg1_1, { MCK_ucomiss, MCK_FR32, MCK_FR32 } },
+ { X86::UCOMISSrm, Convert__Reg1_2__Mem5_1, { MCK_ucomiss, MCK_Mem, MCK_FR32 } },
+ { X86::UNPCKHPDrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_unpckhpd, MCK_FR32, MCK_FR32 } },
+ { X86::UNPCKHPDrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_unpckhpd, MCK_Mem, MCK_FR32 } },
+ { X86::UNPCKHPSrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_unpckhps, MCK_FR32, MCK_FR32 } },
+ { X86::UNPCKHPSrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_unpckhps, MCK_Mem, MCK_FR32 } },
+ { X86::UNPCKLPDrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_unpcklpd, MCK_FR32, MCK_FR32 } },
+ { X86::UNPCKLPDrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_unpcklpd, MCK_Mem, MCK_FR32 } },
+ { X86::UNPCKLPSrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_unpcklps, MCK_FR32, MCK_FR32 } },
+ { X86::UNPCKLPSrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_unpcklps, MCK_Mem, MCK_FR32 } },
+ { X86::VMREAD32rr, Convert__Reg1_2__Reg1_1, { MCK_vmreadl, MCK_GR32, MCK_GR32 } },
+ { X86::VMREAD32rm, Convert__Mem5_2__Reg1_1, { MCK_vmreadl, MCK_GR32, MCK_Mem } },
+ { X86::VMREAD64rr, Convert__Reg1_2__Reg1_1, { MCK_vmreadq, MCK_GR64, MCK_GR64 } },
+ { X86::VMREAD64rm, Convert__Mem5_2__Reg1_1, { MCK_vmreadq, MCK_GR64, MCK_Mem } },
+ { X86::VMWRITE32rr, Convert__Reg1_2__Reg1_1, { MCK_vmwritel, MCK_GR32, MCK_GR32 } },
+ { X86::VMWRITE32rm, Convert__Reg1_2__Mem5_1, { MCK_vmwritel, MCK_Mem, MCK_GR32 } },
+ { X86::VMWRITE64rr, Convert__Reg1_2__Reg1_1, { MCK_vmwriteq, MCK_GR64, MCK_GR64 } },
+ { X86::VMWRITE64rm, Convert__Reg1_2__Mem5_1, { MCK_vmwriteq, MCK_Mem, MCK_GR64 } },
+ { X86::XADD8rr, Convert__Reg1_2__Reg1_1, { MCK_xaddb, MCK_GR8, MCK_GR8 } },
+ { X86::XADD8rm, Convert__Mem5_2__Reg1_1, { MCK_xaddb, MCK_GR8, MCK_Mem } },
+ { X86::XADD32rr, Convert__Reg1_2__Reg1_1, { MCK_xaddl, MCK_GR32, MCK_GR32 } },
+ { X86::XADD32rm, Convert__Mem5_2__Reg1_1, { MCK_xaddl, MCK_GR32, MCK_Mem } },
+ { X86::XADD64rr, Convert__Reg1_2__Reg1_1, { MCK_xaddq, MCK_GR64, MCK_GR64 } },
+ { X86::XADD64rm, Convert__Mem5_2__Reg1_1, { MCK_xaddq, MCK_GR64, MCK_Mem } },
+ { X86::XADD16rr, Convert__Reg1_2__Reg1_1, { MCK_xaddw, MCK_GR16, MCK_GR16 } },
+ { X86::XADD16rm, Convert__Mem5_2__Reg1_1, { MCK_xaddw, MCK_GR16, MCK_Mem } },
+ { X86::XCHG8rr, Convert__Reg1_1__Tie0__Reg1_2, { MCK_xchgb, MCK_GR8, MCK_GR8 } },
+ { X86::XCHG8rm, Convert__Reg1_1__Tie0__Mem5_2, { MCK_xchgb, MCK_GR8, MCK_Mem } },
+ { X86::XCHG32ar, Convert__Reg1_1, { MCK_xchgl, MCK_GR32, MCK_EAX } },
+ { X86::XCHG32rr, Convert__Reg1_1__Tie0__Reg1_2, { MCK_xchgl, MCK_GR32, MCK_GR32 } },
+ { X86::XCHG32rm, Convert__Reg1_1__Tie0__Mem5_2, { MCK_xchgl, MCK_GR32, MCK_Mem } },
+ { X86::XCHG64ar, Convert__Reg1_1, { MCK_xchgq, MCK_GR64, MCK_RAX } },
+ { X86::XCHG64rr, Convert__Reg1_1__Tie0__Reg1_2, { MCK_xchgq, MCK_GR64, MCK_GR64 } },
+ { X86::XCHG64rm, Convert__Reg1_1__Tie0__Mem5_2, { MCK_xchgq, MCK_GR64, MCK_Mem } },
+ { X86::XCHG16ar, Convert__Reg1_1, { MCK_xchgw, MCK_GR16, MCK_AX } },
+ { X86::XCHG16rr, Convert__Reg1_1__Tie0__Reg1_2, { MCK_xchgw, MCK_GR16, MCK_GR16 } },
+ { X86::XCHG16rm, Convert__Reg1_1__Tie0__Mem5_2, { MCK_xchgw, MCK_GR16, MCK_Mem } },
+ { X86::XOR8rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_xorb, MCK_GR8, MCK_GR8 } },
+ { X86::XOR8rr_REV, Convert__Reg1_2__Tie0__Reg1_1, { MCK_xorb, MCK_GR8, MCK_GR8 } },
+ { X86::XOR8mr, Convert__Mem5_2__Reg1_1, { MCK_xorb, MCK_GR8, MCK_Mem } },
+ { X86::XOR8i8, Convert__Imm1_1, { MCK_xorb, MCK_Imm, MCK_AL } },
+ { X86::XOR8ri, Convert__Reg1_2__Tie0__Imm1_1, { MCK_xorb, MCK_Imm, MCK_GR8 } },
+ { X86::XOR8mi, Convert__Mem5_2__Imm1_1, { MCK_xorb, MCK_Imm, MCK_Mem } },
+ { X86::XOR8rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_xorb, MCK_Mem, MCK_GR8 } },
+ { X86::XOR32rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_xorl, MCK_GR32, MCK_GR32 } },
+ { X86::XOR32rr_REV, Convert__Reg1_2__Tie0__Reg1_1, { MCK_xorl, MCK_GR32, MCK_GR32 } },
+ { X86::XOR32mr, Convert__Mem5_2__Reg1_1, { MCK_xorl, MCK_GR32, MCK_Mem } },
+ { X86::XOR32ri8, Convert__Reg1_2__Tie0__ImmSExt81_1, { MCK_xorl, MCK_ImmSExt8, MCK_GR32 } },
+ { X86::XOR32mi8, Convert__Mem5_2__ImmSExt81_1, { MCK_xorl, MCK_ImmSExt8, MCK_Mem } },
+ { X86::XOR32i32, Convert__Imm1_1, { MCK_xorl, MCK_Imm, MCK_EAX } },
+ { X86::XOR32ri, Convert__Reg1_2__Tie0__Imm1_1, { MCK_xorl, MCK_Imm, MCK_GR32 } },
+ { X86::XOR32mi, Convert__Mem5_2__Imm1_1, { MCK_xorl, MCK_Imm, MCK_Mem } },
+ { X86::XOR32rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_xorl, MCK_Mem, MCK_GR32 } },
+ { X86::FsXORPDrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_xorpd, MCK_FR32, MCK_FR32 } },
+ { X86::XORPDrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_xorpd, MCK_FR32, MCK_FR32 } },
+ { X86::FsXORPDrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_xorpd, MCK_Mem, MCK_FR32 } },
+ { X86::XORPDrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_xorpd, MCK_Mem, MCK_FR32 } },
+ { X86::FsXORPSrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_xorps, MCK_FR32, MCK_FR32 } },
+ { X86::XORPSrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_xorps, MCK_FR32, MCK_FR32 } },
+ { X86::FsXORPSrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_xorps, MCK_Mem, MCK_FR32 } },
+ { X86::XORPSrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_xorps, MCK_Mem, MCK_FR32 } },
+ { X86::XOR64rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_xorq, MCK_GR64, MCK_GR64 } },
+ { X86::XOR64rr_REV, Convert__Reg1_2__Tie0__Reg1_1, { MCK_xorq, MCK_GR64, MCK_GR64 } },
+ { X86::XOR64mr, Convert__Mem5_2__Reg1_1, { MCK_xorq, MCK_GR64, MCK_Mem } },
+ { X86::XOR64ri8, Convert__Reg1_2__Tie0__ImmSExt81_1, { MCK_xorq, MCK_ImmSExt8, MCK_GR64 } },
+ { X86::XOR64mi8, Convert__Mem5_2__ImmSExt81_1, { MCK_xorq, MCK_ImmSExt8, MCK_Mem } },
+ { X86::XOR64i32, Convert__Imm1_1, { MCK_xorq, MCK_Imm, MCK_RAX } },
+ { X86::XOR64ri32, Convert__Reg1_2__Tie0__Imm1_1, { MCK_xorq, MCK_Imm, MCK_GR64 } },
+ { X86::XOR64mi32, Convert__Mem5_2__Imm1_1, { MCK_xorq, MCK_Imm, MCK_Mem } },
+ { X86::XOR64rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_xorq, MCK_Mem, MCK_GR64 } },
+ { X86::XOR16rr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_xorw, MCK_GR16, MCK_GR16 } },
+ { X86::XOR16rr_REV, Convert__Reg1_2__Tie0__Reg1_1, { MCK_xorw, MCK_GR16, MCK_GR16 } },
+ { X86::XOR16mr, Convert__Mem5_2__Reg1_1, { MCK_xorw, MCK_GR16, MCK_Mem } },
+ { X86::XOR16ri8, Convert__Reg1_2__Tie0__ImmSExt81_1, { MCK_xorw, MCK_ImmSExt8, MCK_GR16 } },
+ { X86::XOR16mi8, Convert__Mem5_2__ImmSExt81_1, { MCK_xorw, MCK_ImmSExt8, MCK_Mem } },
+ { X86::XOR16i16, Convert__Imm1_1, { MCK_xorw, MCK_Imm, MCK_AX } },
+ { X86::XOR16ri, Convert__Reg1_2__Tie0__Imm1_1, { MCK_xorw, MCK_Imm, MCK_GR16 } },
+ { X86::XOR16mi, Convert__Mem5_2__Imm1_1, { MCK_xorw, MCK_Imm, MCK_Mem } },
+ { X86::XOR16rm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_xorw, MCK_Mem, MCK_GR16 } },
+ { X86::BLENDPDrri, Convert__Reg1_3__Tie0__Reg1_2__ImmSExt81_1, { MCK_blendpd, MCK_ImmSExt8, MCK_FR32, MCK_FR32 } },
+ { X86::BLENDPDrmi, Convert__Reg1_3__Tie0__Mem5_2__ImmSExt81_1, { MCK_blendpd, MCK_ImmSExt8, MCK_Mem, MCK_FR32 } },
+ { X86::BLENDPSrri, Convert__Reg1_3__Tie0__Reg1_2__ImmSExt81_1, { MCK_blendps, MCK_ImmSExt8, MCK_FR32, MCK_FR32 } },
+ { X86::BLENDPSrmi, Convert__Reg1_3__Tie0__Mem5_2__ImmSExt81_1, { MCK_blendps, MCK_ImmSExt8, MCK_Mem, MCK_FR32 } },
+ { X86::BLENDVPDrr0, Convert__Reg1_3__Tie0__Reg1_2, { MCK_blendvpd, MCK_XMM0, MCK_FR32, MCK_FR32 } },
+ { X86::BLENDVPDrm0, Convert__Reg1_3__Tie0__Mem5_2, { MCK_blendvpd, MCK_XMM0, MCK_Mem, MCK_FR32 } },
+ { X86::BLENDVPSrr0, Convert__Reg1_3__Tie0__Reg1_2, { MCK_blendvps, MCK_XMM0, MCK_FR32, MCK_FR32 } },
+ { X86::BLENDVPSrm0, Convert__Reg1_3__Tie0__Mem5_2, { MCK_blendvps, MCK_XMM0, MCK_Mem, MCK_FR32 } },
+ { X86::DPPDrri, Convert__Reg1_3__Tie0__Reg1_2__ImmSExt81_1, { MCK_dppd, MCK_ImmSExt8, MCK_FR32, MCK_FR32 } },
+ { X86::DPPDrmi, Convert__Reg1_3__Tie0__Mem5_2__ImmSExt81_1, { MCK_dppd, MCK_ImmSExt8, MCK_Mem, MCK_FR32 } },
+ { X86::DPPSrri, Convert__Reg1_3__Tie0__Reg1_2__ImmSExt81_1, { MCK_dpps, MCK_ImmSExt8, MCK_FR32, MCK_FR32 } },
+ { X86::DPPSrmi, Convert__Reg1_3__Tie0__Mem5_2__ImmSExt81_1, { MCK_dpps, MCK_ImmSExt8, MCK_Mem, MCK_FR32 } },
+ { X86::EXTRACTPSrr, Convert__Reg1_3__Reg1_2__ImmSExt81_1, { MCK_extractps, MCK_ImmSExt8, MCK_FR32, MCK_GR32 } },
+ { X86::EXTRACTPSmr, Convert__Mem5_3__Reg1_2__ImmSExt81_1, { MCK_extractps, MCK_ImmSExt8, MCK_FR32, MCK_Mem } },
+ { X86::IMUL32rri8, Convert__Reg1_3__Reg1_2__ImmSExt81_1, { MCK_imull, MCK_ImmSExt8, MCK_GR32, MCK_GR32 } },
+ { X86::IMUL32rmi8, Convert__Reg1_3__Mem5_2__ImmSExt81_1, { MCK_imull, MCK_ImmSExt8, MCK_Mem, MCK_GR32 } },
+ { X86::IMUL32rri, Convert__Reg1_3__Reg1_2__Imm1_1, { MCK_imull, MCK_Imm, MCK_GR32, MCK_GR32 } },
+ { X86::IMUL32rmi, Convert__Reg1_3__Mem5_2__Imm1_1, { MCK_imull, MCK_Imm, MCK_Mem, MCK_GR32 } },
+ { X86::IMUL64rri8, Convert__Reg1_3__Reg1_2__ImmSExt81_1, { MCK_imulq, MCK_ImmSExt8, MCK_GR64, MCK_GR64 } },
+ { X86::IMUL64rmi8, Convert__Reg1_3__Mem5_2__ImmSExt81_1, { MCK_imulq, MCK_ImmSExt8, MCK_Mem, MCK_GR64 } },
+ { X86::IMUL64rri32, Convert__Reg1_3__Reg1_2__Imm1_1, { MCK_imulq, MCK_Imm, MCK_GR64, MCK_GR64 } },
+ { X86::IMUL64rmi32, Convert__Reg1_3__Mem5_2__Imm1_1, { MCK_imulq, MCK_Imm, MCK_Mem, MCK_GR64 } },
+ { X86::IMUL16rri8, Convert__Reg1_3__Reg1_2__ImmSExt81_1, { MCK_imulw, MCK_ImmSExt8, MCK_GR16, MCK_GR16 } },
+ { X86::IMUL16rmi8, Convert__Reg1_3__Mem5_2__ImmSExt81_1, { MCK_imulw, MCK_ImmSExt8, MCK_Mem, MCK_GR16 } },
+ { X86::IMUL16rri, Convert__Reg1_3__Reg1_2__Imm1_1, { MCK_imulw, MCK_Imm, MCK_GR16, MCK_GR16 } },
+ { X86::IMUL16rmi, Convert__Reg1_3__Mem5_2__Imm1_1, { MCK_imulw, MCK_Imm, MCK_Mem, MCK_GR16 } },
+ { X86::INSERTPSrr, Convert__Reg1_3__Tie0__Reg1_2__ImmSExt81_1, { MCK_insertps, MCK_ImmSExt8, MCK_FR32, MCK_FR32 } },
+ { X86::INSERTPSrm, Convert__Reg1_3__Tie0__Mem5_2__ImmSExt81_1, { MCK_insertps, MCK_ImmSExt8, MCK_Mem, MCK_FR32 } },
+ { X86::MPSADBWrri, Convert__Reg1_3__Tie0__Reg1_2__ImmSExt81_1, { MCK_mpsadbw, MCK_ImmSExt8, MCK_FR32, MCK_FR32 } },
+ { X86::MPSADBWrmi, Convert__Reg1_3__Tie0__Mem5_2__ImmSExt81_1, { MCK_mpsadbw, MCK_ImmSExt8, MCK_Mem, MCK_FR32 } },
+ { X86::PALIGNR64rr, Convert__Reg1_3__Tie0__Reg1_2__Imm1_1, { MCK_palignr, MCK_Imm, MCK_VR64, MCK_VR64 } },
+ { X86::PALIGNR128rr, Convert__Reg1_3__Tie0__Reg1_2__Imm1_1, { MCK_palignr, MCK_Imm, MCK_FR32, MCK_FR32 } },
+ { X86::PALIGNR64rm, Convert__Reg1_3__Tie0__Mem5_2__Imm1_1, { MCK_palignr, MCK_Imm, MCK_Mem, MCK_VR64 } },
+ { X86::PALIGNR128rm, Convert__Reg1_3__Tie0__Mem5_2__Imm1_1, { MCK_palignr, MCK_Imm, MCK_Mem, MCK_FR32 } },
+ { X86::PBLENDVBrr0, Convert__Reg1_3__Tie0__Reg1_2, { MCK_pblendvb, MCK_XMM0, MCK_FR32, MCK_FR32 } },
+ { X86::PBLENDVBrm0, Convert__Reg1_3__Tie0__Mem5_2, { MCK_pblendvb, MCK_XMM0, MCK_Mem, MCK_FR32 } },
+ { X86::PBLENDWrri, Convert__Reg1_3__Tie0__Reg1_2__ImmSExt81_1, { MCK_pblendw, MCK_ImmSExt8, MCK_FR32, MCK_FR32 } },
+ { X86::PBLENDWrmi, Convert__Reg1_3__Tie0__Mem5_2__ImmSExt81_1, { MCK_pblendw, MCK_ImmSExt8, MCK_Mem, MCK_FR32 } },
+ { X86::PCMPESTRIArr, Convert__Reg1_3__Reg1_2__Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_FR32, MCK_FR32 } },
+ { X86::PCMPESTRICrr, Convert__Reg1_3__Reg1_2__Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_FR32, MCK_FR32 } },
+ { X86::PCMPESTRIOrr, Convert__Reg1_3__Reg1_2__Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_FR32, MCK_FR32 } },
+ { X86::PCMPESTRISrr, Convert__Reg1_3__Reg1_2__Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_FR32, MCK_FR32 } },
+ { X86::PCMPESTRIZrr, Convert__Reg1_3__Reg1_2__Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_FR32, MCK_FR32 } },
+ { X86::PCMPESTRIrr, Convert__Reg1_3__Reg1_2__Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_FR32, MCK_FR32 } },
+ { X86::PCMPESTRIArm, Convert__Reg1_3__Mem5_2__Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_Mem, MCK_FR32 } },
+ { X86::PCMPESTRICrm, Convert__Reg1_3__Mem5_2__Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_Mem, MCK_FR32 } },
+ { X86::PCMPESTRIOrm, Convert__Reg1_3__Mem5_2__Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_Mem, MCK_FR32 } },
+ { X86::PCMPESTRISrm, Convert__Reg1_3__Mem5_2__Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_Mem, MCK_FR32 } },
+ { X86::PCMPESTRIZrm, Convert__Reg1_3__Mem5_2__Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_Mem, MCK_FR32 } },
+ { X86::PCMPESTRIrm, Convert__Reg1_3__Mem5_2__Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_Mem, MCK_FR32 } },
+ { X86::PCMPESTRM128rr, Convert__Reg1_3__Reg1_2__Imm1_1, { MCK_pcmpestrm, MCK_Imm, MCK_FR32, MCK_FR32 } },
+ { X86::PCMPESTRM128rm, Convert__Reg1_3__Mem5_2__Imm1_1, { MCK_pcmpestrm, MCK_Imm, MCK_Mem, MCK_FR32 } },
+ { X86::PCMPISTRIArr, Convert__Reg1_3__Reg1_2__Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_FR32, MCK_FR32 } },
+ { X86::PCMPISTRICrr, Convert__Reg1_3__Reg1_2__Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_FR32, MCK_FR32 } },
+ { X86::PCMPISTRIOrr, Convert__Reg1_3__Reg1_2__Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_FR32, MCK_FR32 } },
+ { X86::PCMPISTRISrr, Convert__Reg1_3__Reg1_2__Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_FR32, MCK_FR32 } },
+ { X86::PCMPISTRIZrr, Convert__Reg1_3__Reg1_2__Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_FR32, MCK_FR32 } },
+ { X86::PCMPISTRIrr, Convert__Reg1_3__Reg1_2__Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_FR32, MCK_FR32 } },
+ { X86::PCMPISTRIArm, Convert__Reg1_3__Mem5_2__Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_Mem, MCK_FR32 } },
+ { X86::PCMPISTRICrm, Convert__Reg1_3__Mem5_2__Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_Mem, MCK_FR32 } },
+ { X86::PCMPISTRIOrm, Convert__Reg1_3__Mem5_2__Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_Mem, MCK_FR32 } },
+ { X86::PCMPISTRISrm, Convert__Reg1_3__Mem5_2__Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_Mem, MCK_FR32 } },
+ { X86::PCMPISTRIZrm, Convert__Reg1_3__Mem5_2__Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_Mem, MCK_FR32 } },
+ { X86::PCMPISTRIrm, Convert__Reg1_3__Mem5_2__Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_Mem, MCK_FR32 } },
+ { X86::PCMPISTRM128rr, Convert__Reg1_3__Reg1_2__Imm1_1, { MCK_pcmpistrm, MCK_Imm, MCK_FR32, MCK_FR32 } },
+ { X86::PCMPISTRM128rm, Convert__Reg1_3__Mem5_2__Imm1_1, { MCK_pcmpistrm, MCK_Imm, MCK_Mem, MCK_FR32 } },
+ { X86::PEXTRBrr, Convert__Reg1_3__Reg1_2__ImmSExt81_1, { MCK_pextrb, MCK_ImmSExt8, MCK_FR32, MCK_GR32 } },
+ { X86::PEXTRBmr, Convert__Mem5_3__Reg1_2__ImmSExt81_1, { MCK_pextrb, MCK_ImmSExt8, MCK_FR32, MCK_Mem } },
+ { X86::PEXTRDrr, Convert__Reg1_3__Reg1_2__ImmSExt81_1, { MCK_pextrd, MCK_ImmSExt8, MCK_FR32, MCK_GR32 } },
+ { X86::PEXTRDmr, Convert__Mem5_3__Reg1_2__ImmSExt81_1, { MCK_pextrd, MCK_ImmSExt8, MCK_FR32, MCK_Mem } },
+ { X86::PEXTRQrr, Convert__Reg1_3__Reg1_2__ImmSExt81_1, { MCK_pextrq, MCK_ImmSExt8, MCK_FR32, MCK_GR64 } },
+ { X86::PEXTRQmr, Convert__Mem5_3__Reg1_2__ImmSExt81_1, { MCK_pextrq, MCK_ImmSExt8, MCK_FR32, MCK_Mem } },
+ { X86::MMX_PEXTRWri, Convert__Reg1_3__Reg1_2__ImmSExt81_1, { MCK_pextrw, MCK_ImmSExt8, MCK_VR64, MCK_GR32 } },
+ { X86::PEXTRWri, Convert__Reg1_3__Reg1_2__ImmSExt81_1, { MCK_pextrw, MCK_ImmSExt8, MCK_FR32, MCK_GR32 } },
+ { X86::PEXTRWmr, Convert__Mem5_3__Reg1_2__ImmSExt81_1, { MCK_pextrw, MCK_ImmSExt8, MCK_FR32, MCK_Mem } },
+ { X86::PINSRBrr, Convert__Reg1_3__Tie0__Reg1_2__ImmSExt81_1, { MCK_pinsrb, MCK_ImmSExt8, MCK_GR32, MCK_FR32 } },
+ { X86::PINSRBrm, Convert__Reg1_3__Tie0__Mem5_2__ImmSExt81_1, { MCK_pinsrb, MCK_ImmSExt8, MCK_Mem, MCK_FR32 } },
+ { X86::PINSRDrr, Convert__Reg1_3__Tie0__Reg1_2__ImmSExt81_1, { MCK_pinsrd, MCK_ImmSExt8, MCK_GR32, MCK_FR32 } },
+ { X86::PINSRDrm, Convert__Reg1_3__Tie0__Mem5_2__ImmSExt81_1, { MCK_pinsrd, MCK_ImmSExt8, MCK_Mem, MCK_FR32 } },
+ { X86::PINSRQrr, Convert__Reg1_3__Tie0__Reg1_2__ImmSExt81_1, { MCK_pinsrq, MCK_ImmSExt8, MCK_GR64, MCK_FR32 } },
+ { X86::PINSRQrm, Convert__Reg1_3__Tie0__Mem5_2__ImmSExt81_1, { MCK_pinsrq, MCK_ImmSExt8, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PINSRWrri, Convert__Reg1_3__Tie0__Reg1_2__ImmSExt81_1, { MCK_pinsrw, MCK_ImmSExt8, MCK_GR32, MCK_VR64 } },
+ { X86::PINSRWrri, Convert__Reg1_3__Tie0__Reg1_2__ImmSExt81_1, { MCK_pinsrw, MCK_ImmSExt8, MCK_GR32, MCK_FR32 } },
+ { X86::MMX_PINSRWrmi, Convert__Reg1_3__Tie0__Mem5_2__ImmSExt81_1, { MCK_pinsrw, MCK_ImmSExt8, MCK_Mem, MCK_VR64 } },
+ { X86::PINSRWrmi, Convert__Reg1_3__Tie0__Mem5_2__ImmSExt81_1, { MCK_pinsrw, MCK_ImmSExt8, MCK_Mem, MCK_FR32 } },
+ { X86::PSHUFDri, Convert__Reg1_3__Reg1_2__Imm1_1, { MCK_pshufd, MCK_Imm, MCK_FR32, MCK_FR32 } },
+ { X86::PSHUFDmi, Convert__Reg1_3__Mem5_2__Imm1_1, { MCK_pshufd, MCK_Imm, MCK_Mem, MCK_FR32 } },
+ { X86::PSHUFHWri, Convert__Reg1_3__Reg1_2__Imm1_1, { MCK_pshufhw, MCK_Imm, MCK_FR32, MCK_FR32 } },
+ { X86::PSHUFHWmi, Convert__Reg1_3__Mem5_2__Imm1_1, { MCK_pshufhw, MCK_Imm, MCK_Mem, MCK_FR32 } },
+ { X86::PSHUFLWri, Convert__Reg1_3__Reg1_2__Imm1_1, { MCK_pshuflw, MCK_Imm, MCK_FR32, MCK_FR32 } },
+ { X86::PSHUFLWmi, Convert__Reg1_3__Mem5_2__Imm1_1, { MCK_pshuflw, MCK_Imm, MCK_Mem, MCK_FR32 } },
+ { X86::MMX_PSHUFWri, Convert__Reg1_3__Reg1_2__Imm1_1, { MCK_pshufw, MCK_Imm, MCK_VR64, MCK_VR64 } },
+ { X86::MMX_PSHUFWmi, Convert__Reg1_3__Mem5_2__Imm1_1, { MCK_pshufw, MCK_Imm, MCK_Mem, MCK_VR64 } },
+ { X86::SHLD32rrCL, Convert__Reg1_3__Tie0__Reg1_2, { MCK_shldl, MCK_CL, MCK_GR32, MCK_GR32 } },
+ { X86::SHLD32mrCL, Convert__Mem5_3__Reg1_2, { MCK_shldl, MCK_CL, MCK_GR32, MCK_Mem } },
+ { X86::SHLD32rri8, Convert__Reg1_3__Tie0__Reg1_2__Imm1_1, { MCK_shldl, MCK_Imm, MCK_GR32, MCK_GR32 } },
+ { X86::SHLD32mri8, Convert__Mem5_3__Reg1_2__Imm1_1, { MCK_shldl, MCK_Imm, MCK_GR32, MCK_Mem } },
+ { X86::SHLD64rrCL, Convert__Reg1_3__Tie0__Reg1_2, { MCK_shldq, MCK_CL, MCK_GR64, MCK_GR64 } },
+ { X86::SHLD64mrCL, Convert__Mem5_3__Reg1_2, { MCK_shldq, MCK_CL, MCK_GR64, MCK_Mem } },
+ { X86::SHLD64rri8, Convert__Reg1_3__Tie0__Reg1_2__Imm1_1, { MCK_shldq, MCK_Imm, MCK_GR64, MCK_GR64 } },
+ { X86::SHLD64mri8, Convert__Mem5_3__Reg1_2__Imm1_1, { MCK_shldq, MCK_Imm, MCK_GR64, MCK_Mem } },
+ { X86::SHLD16rrCL, Convert__Reg1_3__Tie0__Reg1_2, { MCK_shldw, MCK_CL, MCK_GR16, MCK_GR16 } },
+ { X86::SHLD16mrCL, Convert__Mem5_3__Reg1_2, { MCK_shldw, MCK_CL, MCK_GR16, MCK_Mem } },
+ { X86::SHLD16rri8, Convert__Reg1_3__Tie0__Reg1_2__Imm1_1, { MCK_shldw, MCK_Imm, MCK_GR16, MCK_GR16 } },
+ { X86::SHLD16mri8, Convert__Mem5_3__Reg1_2__Imm1_1, { MCK_shldw, MCK_Imm, MCK_GR16, MCK_Mem } },
+ { X86::SHRD32rrCL, Convert__Reg1_3__Tie0__Reg1_2, { MCK_shrdl, MCK_CL, MCK_GR32, MCK_GR32 } },
+ { X86::SHRD32mrCL, Convert__Mem5_3__Reg1_2, { MCK_shrdl, MCK_CL, MCK_GR32, MCK_Mem } },
+ { X86::SHRD32rri8, Convert__Reg1_3__Tie0__Reg1_2__Imm1_1, { MCK_shrdl, MCK_Imm, MCK_GR32, MCK_GR32 } },
+ { X86::SHRD32mri8, Convert__Mem5_3__Reg1_2__Imm1_1, { MCK_shrdl, MCK_Imm, MCK_GR32, MCK_Mem } },
+ { X86::SHRD64rrCL, Convert__Reg1_3__Tie0__Reg1_2, { MCK_shrdq, MCK_CL, MCK_GR64, MCK_GR64 } },
+ { X86::SHRD64mrCL, Convert__Mem5_3__Reg1_2, { MCK_shrdq, MCK_CL, MCK_GR64, MCK_Mem } },
+ { X86::SHRD64rri8, Convert__Reg1_3__Tie0__Reg1_2__Imm1_1, { MCK_shrdq, MCK_Imm, MCK_GR64, MCK_GR64 } },
+ { X86::SHRD64mri8, Convert__Mem5_3__Reg1_2__Imm1_1, { MCK_shrdq, MCK_Imm, MCK_GR64, MCK_Mem } },
+ { X86::SHRD16rrCL, Convert__Reg1_3__Tie0__Reg1_2, { MCK_shrdw, MCK_CL, MCK_GR16, MCK_GR16 } },
+ { X86::SHRD16mrCL, Convert__Mem5_3__Reg1_2, { MCK_shrdw, MCK_CL, MCK_GR16, MCK_Mem } },
+ { X86::SHRD16rri8, Convert__Reg1_3__Tie0__Reg1_2__Imm1_1, { MCK_shrdw, MCK_Imm, MCK_GR16, MCK_GR16 } },
+ { X86::SHRD16mri8, Convert__Mem5_3__Reg1_2__Imm1_1, { MCK_shrdw, MCK_Imm, MCK_GR16, MCK_Mem } },
+ { X86::SHUFPDrri, Convert__Reg1_3__Tie0__Reg1_2__Imm1_1, { MCK_shufpd, MCK_Imm, MCK_FR32, MCK_FR32 } },
+ { X86::SHUFPDrmi, Convert__Reg1_3__Tie0__Mem5_2__Imm1_1, { MCK_shufpd, MCK_Imm, MCK_Mem, MCK_FR32 } },
+ { X86::SHUFPSrri, Convert__Reg1_3__Tie0__Reg1_2__Imm1_1, { MCK_shufps, MCK_Imm, MCK_FR32, MCK_FR32 } },
+ { X86::SHUFPSrmi, Convert__Reg1_3__Tie0__Mem5_2__Imm1_1, { MCK_shufps, MCK_Imm, MCK_Mem, MCK_FR32 } },
+ { X86::CMPPDrri, Convert__Reg1_4__Tie0__Reg1_3__Imm1_1, { MCK_cmp, MCK_Imm, MCK_pd, MCK_FR32, MCK_FR32 } },
+ { X86::CMPPDrmi, Convert__Reg1_4__Tie0__Mem5_3__Imm1_1, { MCK_cmp, MCK_Imm, MCK_pd, MCK_Mem, MCK_FR32 } },
+ { X86::CMPPSrri, Convert__Reg1_4__Tie0__Reg1_3__Imm1_1, { MCK_cmp, MCK_Imm, MCK_ps, MCK_FR32, MCK_FR32 } },
+ { X86::CMPPSrmi, Convert__Reg1_4__Tie0__Mem5_3__Imm1_1, { MCK_cmp, MCK_Imm, MCK_ps, MCK_Mem, MCK_FR32 } },
+ { X86::CMPSDrr, Convert__Reg1_4__Tie0__Reg1_3__Imm1_1, { MCK_cmp, MCK_Imm, MCK_sd, MCK_FR32, MCK_FR32 } },
+ { X86::CMPSDrm, Convert__Reg1_4__Tie0__Mem5_3__Imm1_1, { MCK_cmp, MCK_Imm, MCK_sd, MCK_Mem, MCK_FR32 } },
+ { X86::CMPSSrr, Convert__Reg1_4__Tie0__Reg1_3__Imm1_1, { MCK_cmp, MCK_Imm, MCK_ss, MCK_FR32, MCK_FR32 } },
+ { X86::CMPSSrm, Convert__Reg1_4__Tie0__Mem5_3__Imm1_1, { MCK_cmp, MCK_Imm, MCK_ss, MCK_Mem, MCK_FR32 } },
};
// Eliminate obvious mismatches.
@@ -8309,7 +8364,7 @@ MatchInstruction(const SmallVectorImpl<MCParsedAsmOperand*> &Operands,
Classes[i] = InvalidMatchClass;
// Search the table.
- for (const MatchEntry *it = MatchTable, *ie = MatchTable + 2040; it != ie; ++it) {
+ for (const MatchEntry *it = MatchTable, *ie = MatchTable + 2049; it != ie; ++it) {
if (!IsSubclass(Classes[0], it->Classes[0]))
continue;
if (!IsSubclass(Classes[1], it->Classes[1]))
diff --git a/libclamav/c++/X86GenAsmWriter.inc b/libclamav/c++/X86GenAsmWriter.inc
index 38d2786..bf99ac6 100644
--- a/libclamav/c++/X86GenAsmWriter.inc
+++ b/libclamav/c++/X86GenAsmWriter.inc
@@ -21,101 +21,101 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // IMPLICIT_DEF
0U, // SUBREG_TO_REG
0U, // COPY_TO_REGCLASS
- 1U, // DEBUG_VALUE
- 13U, // ABS_F
+ 1U, // DBG_VALUE
+ 11U, // ABS_F
0U, // ABS_Fp32
0U, // ABS_Fp64
0U, // ABS_Fp80
- 67108882U, // ADC16i16
- 135266322U, // ADC16mi
- 135266322U, // ADC16mi8
- 135266322U, // ADC16mr
- 203456530U, // ADC16ri
- 203456530U, // ADC16ri8
- 270565394U, // ADC16rm
- 203456530U, // ADC16rr
- 203456530U, // ADC16rr_REV
- 70254616U, // ADC32i32
- 135331864U, // ADC32mi
- 135331864U, // ADC32mi8
- 135331864U, // ADC32mr
- 203456536U, // ADC32ri
- 203456536U, // ADC32ri8
- 337674264U, // ADC32rm
- 203456536U, // ADC32rr
- 203456536U, // ADC32rr_REV
- 71303198U, // ADC64i32
- 135364638U, // ADC64mi32
- 135364638U, // ADC64mi8
- 135364638U, // ADC64mr
- 203456542U, // ADC64ri32
- 203456542U, // ADC64ri8
- 404783134U, // ADC64rm
- 203456542U, // ADC64rr
- 203456542U, // ADC64rr_REV
- 72351780U, // ADC8i8
- 135397412U, // ADC8mi
- 135397412U, // ADC8mr
- 203456548U, // ADC8ri
- 471892004U, // ADC8rm
- 203456548U, // ADC8rr
- 203456548U, // ADC8rr_REV
- 67108906U, // ADD16i16
- 135266346U, // ADD16mi
- 135266346U, // ADD16mi8
- 135266346U, // ADD16mr
- 203456554U, // ADD16mrmrr
- 203456554U, // ADD16ri
- 203456554U, // ADD16ri8
- 270565418U, // ADD16rm
- 203456554U, // ADD16rr
- 70254640U, // ADD32i32
- 135331888U, // ADD32mi
- 135331888U, // ADD32mi8
- 135331888U, // ADD32mr
- 203456560U, // ADD32mrmrr
- 203456560U, // ADD32ri
- 203456560U, // ADD32ri8
- 337674288U, // ADD32rm
- 203456560U, // ADD32rr
- 71303222U, // ADD64i32
- 135364662U, // ADD64mi32
- 135364662U, // ADD64mi8
- 135364662U, // ADD64mr
- 203456560U, // ADD64mrmrr
- 203456566U, // ADD64ri32
- 203456566U, // ADD64ri8
- 404783158U, // ADD64rm
- 203456566U, // ADD64rr
- 72351804U, // ADD8i8
- 135397436U, // ADD8mi
- 135397436U, // ADD8mr
- 203456572U, // ADD8mrmrr
- 203456572U, // ADD8ri
- 471892028U, // ADD8rm
- 203456572U, // ADD8rr
- 536870978U, // ADDPDrm
- 203456578U, // ADDPDrr
- 536870985U, // ADDPSrm
- 203456585U, // ADDPSrr
- 603979856U, // ADDSDrm
- 603979856U, // ADDSDrm_Int
- 203456592U, // ADDSDrr
- 203456592U, // ADDSDrr_Int
- 671088727U, // ADDSSrm
- 671088727U, // ADDSSrm_Int
- 203456599U, // ADDSSrr
- 203456599U, // ADDSSrr_Int
- 536871006U, // ADDSUBPDrm
- 203456606U, // ADDSUBPDrr
- 536871016U, // ADDSUBPSrm
- 203456616U, // ADDSUBPSrr
- 738197618U, // ADD_F32m
- 805306489U, // ADD_F64m
- 872415360U, // ADD_FI16m
- 945815688U, // ADD_FI32m
- 73400464U, // ADD_FPrST0
- 73400471U, // ADD_FST0r
+ 67108880U, // ADC16i16
+ 136314896U, // ADC16mi
+ 136314896U, // ADC16mi8
+ 136314896U, // ADC16mr
+ 205651984U, // ADC16ri
+ 205651984U, // ADC16ri8
+ 272760848U, // ADC16rm
+ 205651984U, // ADC16rr
+ 205651984U, // ADC16rr_REV
+ 73400342U, // ADC32i32
+ 136577046U, // ADC32mi
+ 136577046U, // ADC32mi8
+ 136577046U, // ADC32mr
+ 205651990U, // ADC32ri
+ 205651990U, // ADC32ri8
+ 339869718U, // ADC32rm
+ 205651990U, // ADC32rr
+ 205651990U, // ADC32rr_REV
+ 75497500U, // ADC64i32
+ 136708124U, // ADC64mi32
+ 136708124U, // ADC64mi8
+ 136708124U, // ADC64mr
+ 205651996U, // ADC64ri32
+ 205651996U, // ADC64ri8
+ 406978588U, // ADC64rm
+ 205651996U, // ADC64rr
+ 205651996U, // ADC64rr_REV
+ 77594658U, // ADC8i8
+ 136839202U, // ADC8mi
+ 136839202U, // ADC8mr
+ 205652002U, // ADC8ri
+ 474087458U, // ADC8rm
+ 205652002U, // ADC8rr
+ 205652002U, // ADC8rr_REV
+ 67108904U, // ADD16i16
+ 136314920U, // ADD16mi
+ 136314920U, // ADD16mi8
+ 136314920U, // ADD16mr
+ 205652008U, // ADD16mrmrr
+ 205652008U, // ADD16ri
+ 205652008U, // ADD16ri8
+ 272760872U, // ADD16rm
+ 205652008U, // ADD16rr
+ 73400366U, // ADD32i32
+ 136577070U, // ADD32mi
+ 136577070U, // ADD32mi8
+ 136577070U, // ADD32mr
+ 205652014U, // ADD32mrmrr
+ 205652014U, // ADD32ri
+ 205652014U, // ADD32ri8
+ 339869742U, // ADD32rm
+ 205652014U, // ADD32rr
+ 75497524U, // ADD64i32
+ 136708148U, // ADD64mi32
+ 136708148U, // ADD64mi8
+ 136708148U, // ADD64mr
+ 205652014U, // ADD64mrmrr
+ 205652020U, // ADD64ri32
+ 205652020U, // ADD64ri8
+ 406978612U, // ADD64rm
+ 205652020U, // ADD64rr
+ 77594682U, // ADD8i8
+ 136839226U, // ADD8mi
+ 136839226U, // ADD8mr
+ 205652026U, // ADD8mrmrr
+ 205652026U, // ADD8ri
+ 474087482U, // ADD8rm
+ 205652026U, // ADD8rr
+ 536870976U, // ADDPDrm
+ 205652032U, // ADDPDrr
+ 536870983U, // ADDPSrm
+ 205652039U, // ADDPSrr
+ 603979854U, // ADDSDrm
+ 603979854U, // ADDSDrm_Int
+ 205652046U, // ADDSDrr
+ 205652046U, // ADDSDrr_Int
+ 671088725U, // ADDSSrm
+ 671088725U, // ADDSSrm_Int
+ 205652053U, // ADDSSrr
+ 205652053U, // ADDSSrr_Int
+ 536871004U, // ADDSUBPDrm
+ 205652060U, // ADDSUBPDrr
+ 536871014U, // ADDSUBPSrm
+ 205652070U, // ADDSUBPSrr
+ 738197616U, // ADD_F32m
+ 805306487U, // ADD_F64m
+ 872415358U, // ADD_FI16m
+ 952107142U, // ADD_FI32m
+ 79691918U, // ADD_FPrST0
+ 79691925U, // ADD_FST0r
0U, // ADD_Fp32
0U, // ADD_Fp32m
0U, // ADD_Fp64
@@ -130,462 +130,463 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // ADD_FpI32m32
0U, // ADD_FpI32m64
0U, // ADD_FpI32m80
- 73400477U, // ADD_FrST0
- 171U, // ADJCALLSTACKDOWN32
- 171U, // ADJCALLSTACKDOWN64
- 189U, // ADJCALLSTACKUP32
- 189U, // ADJCALLSTACKUP64
- 67109069U, // AND16i16
- 135266509U, // AND16mi
- 135266509U, // AND16mi8
- 135266509U, // AND16mr
- 203456717U, // AND16ri
- 203456717U, // AND16ri8
- 270565581U, // AND16rm
- 203456717U, // AND16rr
- 203456717U, // AND16rr_REV
- 70254803U, // AND32i32
- 135332051U, // AND32mi
- 135332051U, // AND32mi8
- 135332051U, // AND32mr
- 203456723U, // AND32ri
- 203456723U, // AND32ri8
- 337674451U, // AND32rm
- 203456723U, // AND32rr
- 203456723U, // AND32rr_REV
- 71303385U, // AND64i32
- 135364825U, // AND64mi32
- 135364825U, // AND64mi8
- 135364825U, // AND64mr
- 203456729U, // AND64ri32
- 203456729U, // AND64ri8
- 404783321U, // AND64rm
- 203456729U, // AND64rr
- 203456729U, // AND64rr_REV
- 72351967U, // AND8i8
- 135397599U, // AND8mi
- 135397599U, // AND8mr
- 203456735U, // AND8ri
- 471892191U, // AND8rm
- 203456735U, // AND8rr
- 203456735U, // AND8rr_REV
- 536871141U, // ANDNPDrm
- 203456741U, // ANDNPDrr
- 536871149U, // ANDNPSrm
- 203456749U, // ANDNPSrr
- 536871157U, // ANDPDrm
- 203456757U, // ANDPDrr
- 536871164U, // ANDPSrm
- 203456764U, // ANDPSrr
- 259U, // ATOMADD6432
- 280U, // ATOMAND16
- 299U, // ATOMAND32
- 318U, // ATOMAND64
- 337U, // ATOMAND6432
- 358U, // ATOMAND8
- 376U, // ATOMMAX16
- 395U, // ATOMMAX32
- 414U, // ATOMMAX64
- 433U, // ATOMMIN16
- 452U, // ATOMMIN32
- 471U, // ATOMMIN64
- 490U, // ATOMNAND16
- 510U, // ATOMNAND32
- 530U, // ATOMNAND64
- 550U, // ATOMNAND6432
- 572U, // ATOMNAND8
- 591U, // ATOMOR16
- 609U, // ATOMOR32
- 627U, // ATOMOR64
- 645U, // ATOMOR6432
- 665U, // ATOMOR8
- 682U, // ATOMSUB6432
- 703U, // ATOMSWAP6432
- 725U, // ATOMUMAX16
- 745U, // ATOMUMAX32
- 765U, // ATOMUMAX64
- 785U, // ATOMUMIN16
- 805U, // ATOMUMIN32
- 825U, // ATOMUMIN64
- 845U, // ATOMXOR16
- 864U, // ATOMXOR32
- 883U, // ATOMXOR64
- 902U, // ATOMXOR6432
- 923U, // ATOMXOR8
- 1013973933U, // BLENDPDrmi
- 1073742765U, // BLENDPDrri
- 1013973942U, // BLENDPSrmi
- 1073742774U, // BLENDPSrri
- 1140851647U, // BLENDVPDrm0
- 203457471U, // BLENDVPDrr0
- 1140851664U, // BLENDVPSrm0
- 203457488U, // BLENDVPSrr0
- 1207960545U, // BSF16rm
- 1277199329U, // BSF16rr
- 1342178279U, // BSF32rm
- 1277199335U, // BSF32rr
- 1409287149U, // BSF64rm
- 1277199341U, // BSF64rr
- 1207960563U, // BSR16rm
- 1277199347U, // BSR16rr
- 1342178297U, // BSR32rm
- 1277199353U, // BSR32rr
- 1409287167U, // BSR64rm
- 1277199359U, // BSR64rr
- 73401349U, // BSWAP32r
- 73401357U, // BSWAP64r
- 135267349U, // BT16mi8
- 135267349U, // BT16mr
- 1277199381U, // BT16ri8
- 1277199381U, // BT16rr
- 135332890U, // BT32mi8
- 135332890U, // BT32mr
- 1277199386U, // BT32ri8
- 1277199386U, // BT32rr
- 135365663U, // BT64mi8
- 135365663U, // BT64mr
- 1277199391U, // BT64ri8
- 1277199391U, // BT64rr
- 135267364U, // BTC16mi8
- 135267364U, // BTC16mr
- 1277199396U, // BTC16ri8
- 1277199396U, // BTC16rr
- 135332906U, // BTC32mi8
- 135332906U, // BTC32mr
- 1277199402U, // BTC32ri8
- 1277199402U, // BTC32rr
- 135365680U, // BTC64mi8
- 135365680U, // BTC64mr
- 1277199408U, // BTC64ri8
- 1277199408U, // BTC64rr
- 135267382U, // BTR16mi8
- 135267382U, // BTR16mr
- 1277199414U, // BTR16ri8
- 1277199414U, // BTR16rr
- 135332924U, // BTR32mi8
- 135332924U, // BTR32mr
- 1277199420U, // BTR32ri8
- 1277199420U, // BTR32rr
- 135365698U, // BTR64mi8
- 135365698U, // BTR64mr
- 1277199426U, // BTR64ri8
- 1277199426U, // BTR64rr
- 135267400U, // BTS16mi8
- 135267400U, // BTS16mr
- 1277199432U, // BTS16ri8
- 1277199432U, // BTS16rr
- 135332942U, // BTS32mi8
- 135332942U, // BTS32mr
- 1277199438U, // BTS32ri8
- 1277199438U, // BTS32rr
- 135365716U, // BTS64mi8
- 135365716U, // BTS64mr
- 1277199444U, // BTS64ri8
- 1277199444U, // BTS64rr
- 945816666U, // CALL32m
- 73401434U, // CALL32r
- 1476396129U, // CALL64m
- 1549796457U, // CALL64pcrel32
- 73401441U, // CALL64r
- 1549796464U, // CALLpcrel32
- 1142U, // CBW
- 1147U, // CDQ
- 1152U, // CDQE
- 1157U, // CHS_F
+ 79691931U, // ADD_FrST0
+ 169U, // ADJCALLSTACKDOWN32
+ 169U, // ADJCALLSTACKDOWN64
+ 187U, // ADJCALLSTACKUP32
+ 187U, // ADJCALLSTACKUP64
+ 67109067U, // AND16i16
+ 136315083U, // AND16mi
+ 136315083U, // AND16mi8
+ 136315083U, // AND16mr
+ 205652171U, // AND16ri
+ 205652171U, // AND16ri8
+ 272761035U, // AND16rm
+ 205652171U, // AND16rr
+ 205652171U, // AND16rr_REV
+ 73400529U, // AND32i32
+ 136577233U, // AND32mi
+ 136577233U, // AND32mi8
+ 136577233U, // AND32mr
+ 205652177U, // AND32ri
+ 205652177U, // AND32ri8
+ 339869905U, // AND32rm
+ 205652177U, // AND32rr
+ 205652177U, // AND32rr_REV
+ 75497687U, // AND64i32
+ 136708311U, // AND64mi32
+ 136708311U, // AND64mi8
+ 136708311U, // AND64mr
+ 205652183U, // AND64ri32
+ 205652183U, // AND64ri8
+ 406978775U, // AND64rm
+ 205652183U, // AND64rr
+ 205652183U, // AND64rr_REV
+ 77594845U, // AND8i8
+ 136839389U, // AND8mi
+ 136839389U, // AND8mr
+ 205652189U, // AND8ri
+ 474087645U, // AND8rm
+ 205652189U, // AND8rr
+ 205652189U, // AND8rr_REV
+ 536871139U, // ANDNPDrm
+ 205652195U, // ANDNPDrr
+ 536871147U, // ANDNPSrm
+ 205652203U, // ANDNPSrr
+ 536871155U, // ANDPDrm
+ 205652211U, // ANDPDrr
+ 536871162U, // ANDPSrm
+ 205652218U, // ANDPSrr
+ 257U, // ATOMADD6432
+ 278U, // ATOMAND16
+ 297U, // ATOMAND32
+ 316U, // ATOMAND64
+ 335U, // ATOMAND6432
+ 356U, // ATOMAND8
+ 374U, // ATOMMAX16
+ 393U, // ATOMMAX32
+ 412U, // ATOMMAX64
+ 431U, // ATOMMIN16
+ 450U, // ATOMMIN32
+ 469U, // ATOMMIN64
+ 488U, // ATOMNAND16
+ 508U, // ATOMNAND32
+ 528U, // ATOMNAND64
+ 548U, // ATOMNAND6432
+ 570U, // ATOMNAND8
+ 589U, // ATOMOR16
+ 607U, // ATOMOR32
+ 625U, // ATOMOR64
+ 643U, // ATOMOR6432
+ 663U, // ATOMOR8
+ 680U, // ATOMSUB6432
+ 701U, // ATOMSWAP6432
+ 723U, // ATOMUMAX16
+ 743U, // ATOMUMAX32
+ 763U, // ATOMUMAX64
+ 783U, // ATOMUMIN16
+ 803U, // ATOMUMIN32
+ 823U, // ATOMUMIN64
+ 843U, // ATOMXOR16
+ 862U, // ATOMXOR32
+ 881U, // ATOMXOR64
+ 900U, // ATOMXOR6432
+ 921U, // ATOMXOR8
+ 1021313963U, // BLENDPDrmi
+ 1073742763U, // BLENDPDrri
+ 1021313972U, // BLENDPSrmi
+ 1073742772U, // BLENDPSrri
+ 1140851645U, // BLENDVPDrm0
+ 205652925U, // BLENDVPDrr0
+ 1140851662U, // BLENDVPSrm0
+ 205652942U, // BLENDVPSrr0
+ 1207960543U, // BSF16rm
+ 1279394783U, // BSF16rr
+ 1342178277U, // BSF32rm
+ 1279394789U, // BSF32rr
+ 1409287147U, // BSF64rm
+ 1279394795U, // BSF64rr
+ 1207960561U, // BSR16rm
+ 1279394801U, // BSR16rr
+ 1342178295U, // BSR32rm
+ 1279394807U, // BSR32rr
+ 1409287165U, // BSR64rm
+ 1279394813U, // BSR64rr
+ 79692803U, // BSWAP32r
+ 79692811U, // BSWAP64r
+ 136315923U, // BT16mi8
+ 136315923U, // BT16mr
+ 1279394835U, // BT16ri8
+ 1279394835U, // BT16rr
+ 136578072U, // BT32mi8
+ 136578072U, // BT32mr
+ 1279394840U, // BT32ri8
+ 1279394840U, // BT32rr
+ 136709149U, // BT64mi8
+ 136709149U, // BT64mr
+ 1279394845U, // BT64ri8
+ 1279394845U, // BT64rr
+ 136315938U, // BTC16mi8
+ 136315938U, // BTC16mr
+ 1279394850U, // BTC16ri8
+ 1279394850U, // BTC16rr
+ 136578088U, // BTC32mi8
+ 136578088U, // BTC32mr
+ 1279394856U, // BTC32ri8
+ 1279394856U, // BTC32rr
+ 136709166U, // BTC64mi8
+ 136709166U, // BTC64mr
+ 1279394862U, // BTC64ri8
+ 1279394862U, // BTC64rr
+ 136315956U, // BTR16mi8
+ 136315956U, // BTR16mr
+ 1279394868U, // BTR16ri8
+ 1279394868U, // BTR16rr
+ 136578106U, // BTR32mi8
+ 136578106U, // BTR32mr
+ 1279394874U, // BTR32ri8
+ 1279394874U, // BTR32rr
+ 136709184U, // BTR64mi8
+ 136709184U, // BTR64mr
+ 1279394880U, // BTR64ri8
+ 1279394880U, // BTR64rr
+ 136315974U, // BTS16mi8
+ 136315974U, // BTS16mr
+ 1279394886U, // BTS16ri8
+ 1279394886U, // BTS16rr
+ 136578124U, // BTS32mi8
+ 136578124U, // BTS32mr
+ 1279394892U, // BTS32ri8
+ 1279394892U, // BTS32rr
+ 136709202U, // BTS64mi8
+ 136709202U, // BTS64mr
+ 1279394898U, // BTS64ri8
+ 1279394898U, // BTS64rr
+ 952108120U, // CALL32m
+ 79692888U, // CALL32r
+ 1476396127U, // CALL64m
+ 1556087911U, // CALL64pcrel32
+ 79692895U, // CALL64r
+ 1556087918U, // CALLpcrel32
+ 1140U, // CBW
+ 1145U, // CDQ
+ 1150U, // CDQE
+ 1155U, // CHS_F
0U, // CHS_Fp32
0U, // CHS_Fp64
0U, // CHS_Fp80
- 1162U, // CLC
- 1166U, // CLD
- 1610613906U, // CLFLUSH
- 1179U, // CLI
- 1183U, // CLTS
- 1188U, // CMC
- 270566568U, // CMOVA16rm
- 203457704U, // CMOVA16rr
- 337675440U, // CMOVA32rm
- 203457712U, // CMOVA32rr
- 404784312U, // CMOVA64rm
- 203457720U, // CMOVA64rr
- 270566592U, // CMOVAE16rm
- 203457728U, // CMOVAE16rr
- 337675465U, // CMOVAE32rm
- 203457737U, // CMOVAE32rr
- 404784338U, // CMOVAE64rm
- 203457746U, // CMOVAE64rr
- 270566619U, // CMOVB16rm
- 203457755U, // CMOVB16rr
- 337675491U, // CMOVB32rm
- 203457763U, // CMOVB32rr
- 404784363U, // CMOVB64rm
- 203457771U, // CMOVB64rr
- 270566643U, // CMOVBE16rm
- 203457779U, // CMOVBE16rr
- 337675516U, // CMOVBE32rm
- 203457788U, // CMOVBE32rr
- 404784389U, // CMOVBE64rm
- 203457797U, // CMOVBE64rr
- 75498766U, // CMOVBE_F
+ 1160U, // CLC
+ 1164U, // CLD
+ 1610613904U, // CLFLUSH
+ 1177U, // CLI
+ 1181U, // CLTS
+ 1186U, // CMC
+ 272762022U, // CMOVA16rm
+ 205653158U, // CMOVA16rr
+ 339870894U, // CMOVA32rm
+ 205653166U, // CMOVA32rr
+ 406979766U, // CMOVA64rm
+ 205653174U, // CMOVA64rr
+ 272762046U, // CMOVAE16rm
+ 205653182U, // CMOVAE16rr
+ 339870919U, // CMOVAE32rm
+ 205653191U, // CMOVAE32rr
+ 406979792U, // CMOVAE64rm
+ 205653200U, // CMOVAE64rr
+ 272762073U, // CMOVB16rm
+ 205653209U, // CMOVB16rr
+ 339870945U, // CMOVB32rm
+ 205653217U, // CMOVB32rr
+ 406979817U, // CMOVB64rm
+ 205653225U, // CMOVB64rr
+ 272762097U, // CMOVBE16rm
+ 205653233U, // CMOVBE16rr
+ 339870970U, // CMOVBE32rm
+ 205653242U, // CMOVBE32rr
+ 406979843U, // CMOVBE64rm
+ 205653251U, // CMOVBE64rr
+ 83887372U, // CMOVBE_F
0U, // CMOVBE_Fp32
0U, // CMOVBE_Fp64
0U, // CMOVBE_Fp80
- 75498775U, // CMOVB_F
+ 83887381U, // CMOVB_F
0U, // CMOVB_Fp32
0U, // CMOVB_Fp64
0U, // CMOVB_Fp80
- 270566687U, // CMOVE16rm
- 203457823U, // CMOVE16rr
- 337675559U, // CMOVE32rm
- 203457831U, // CMOVE32rr
- 404784431U, // CMOVE64rm
- 203457839U, // CMOVE64rr
- 75498807U, // CMOVE_F
+ 272762141U, // CMOVE16rm
+ 205653277U, // CMOVE16rr
+ 339871013U, // CMOVE32rm
+ 205653285U, // CMOVE32rr
+ 406979885U, // CMOVE64rm
+ 205653293U, // CMOVE64rr
+ 83887413U, // CMOVE_F
0U, // CMOVE_Fp32
0U, // CMOVE_Fp64
0U, // CMOVE_Fp80
- 270566719U, // CMOVG16rm
- 203457855U, // CMOVG16rr
- 337675591U, // CMOVG32rm
- 203457863U, // CMOVG32rr
- 404784463U, // CMOVG64rm
- 203457871U, // CMOVG64rr
- 270566743U, // CMOVGE16rm
- 203457879U, // CMOVGE16rr
- 337675616U, // CMOVGE32rm
- 203457888U, // CMOVGE32rr
- 404784489U, // CMOVGE64rm
- 203457897U, // CMOVGE64rr
- 270566770U, // CMOVL16rm
- 203457906U, // CMOVL16rr
- 337675642U, // CMOVL32rm
- 203457914U, // CMOVL32rr
- 404784514U, // CMOVL64rm
- 203457922U, // CMOVL64rr
- 270566794U, // CMOVLE16rm
- 203457930U, // CMOVLE16rr
- 337675667U, // CMOVLE32rm
- 203457939U, // CMOVLE32rr
- 404784540U, // CMOVLE64rm
- 203457948U, // CMOVLE64rr
- 75498917U, // CMOVNBE_F
+ 272762173U, // CMOVG16rm
+ 205653309U, // CMOVG16rr
+ 339871045U, // CMOVG32rm
+ 205653317U, // CMOVG32rr
+ 406979917U, // CMOVG64rm
+ 205653325U, // CMOVG64rr
+ 272762197U, // CMOVGE16rm
+ 205653333U, // CMOVGE16rr
+ 339871070U, // CMOVGE32rm
+ 205653342U, // CMOVGE32rr
+ 406979943U, // CMOVGE64rm
+ 205653351U, // CMOVGE64rr
+ 272762224U, // CMOVL16rm
+ 205653360U, // CMOVL16rr
+ 339871096U, // CMOVL32rm
+ 205653368U, // CMOVL32rr
+ 406979968U, // CMOVL64rm
+ 205653376U, // CMOVL64rr
+ 272762248U, // CMOVLE16rm
+ 205653384U, // CMOVLE16rr
+ 339871121U, // CMOVLE32rm
+ 205653393U, // CMOVLE32rr
+ 406979994U, // CMOVLE64rm
+ 205653402U, // CMOVLE64rr
+ 83887523U, // CMOVNBE_F
0U, // CMOVNBE_Fp32
0U, // CMOVNBE_Fp64
0U, // CMOVNBE_Fp80
- 75498927U, // CMOVNB_F
+ 83887533U, // CMOVNB_F
0U, // CMOVNB_Fp32
0U, // CMOVNB_Fp64
0U, // CMOVNB_Fp80
- 270566840U, // CMOVNE16rm
- 203457976U, // CMOVNE16rr
- 337675713U, // CMOVNE32rm
- 203457985U, // CMOVNE32rr
- 404784586U, // CMOVNE64rm
- 203457994U, // CMOVNE64rr
- 75498963U, // CMOVNE_F
+ 272762294U, // CMOVNE16rm
+ 205653430U, // CMOVNE16rr
+ 339871167U, // CMOVNE32rm
+ 205653439U, // CMOVNE32rr
+ 406980040U, // CMOVNE64rm
+ 205653448U, // CMOVNE64rr
+ 83887569U, // CMOVNE_F
0U, // CMOVNE_Fp32
0U, // CMOVNE_Fp64
0U, // CMOVNE_Fp80
- 270566876U, // CMOVNO16rm
- 203458012U, // CMOVNO16rr
- 337675749U, // CMOVNO32rm
- 203458021U, // CMOVNO32rr
- 404784622U, // CMOVNO64rm
- 203458030U, // CMOVNO64rr
- 270566903U, // CMOVNP16rm
- 203458039U, // CMOVNP16rr
- 337675776U, // CMOVNP32rm
- 203458048U, // CMOVNP32rr
- 404784649U, // CMOVNP64rm
- 203458057U, // CMOVNP64rr
- 75499026U, // CMOVNP_F
+ 272762330U, // CMOVNO16rm
+ 205653466U, // CMOVNO16rr
+ 339871203U, // CMOVNO32rm
+ 205653475U, // CMOVNO32rr
+ 406980076U, // CMOVNO64rm
+ 205653484U, // CMOVNO64rr
+ 272762357U, // CMOVNP16rm
+ 205653493U, // CMOVNP16rr
+ 339871230U, // CMOVNP32rm
+ 205653502U, // CMOVNP32rr
+ 406980103U, // CMOVNP64rm
+ 205653511U, // CMOVNP64rr
+ 83887632U, // CMOVNP_F
0U, // CMOVNP_Fp32
0U, // CMOVNP_Fp64
0U, // CMOVNP_Fp80
- 270566939U, // CMOVNS16rm
- 203458075U, // CMOVNS16rr
- 337675812U, // CMOVNS32rm
- 203458084U, // CMOVNS32rr
- 404784685U, // CMOVNS64rm
- 203458093U, // CMOVNS64rr
- 270566966U, // CMOVO16rm
- 203458102U, // CMOVO16rr
- 337675838U, // CMOVO32rm
- 203458110U, // CMOVO32rr
- 404784710U, // CMOVO64rm
- 203458118U, // CMOVO64rr
- 270566990U, // CMOVP16rm
- 203458126U, // CMOVP16rr
- 337675862U, // CMOVP32rm
- 203458134U, // CMOVP32rr
- 404784734U, // CMOVP64rm
- 203458142U, // CMOVP64rr
- 75499110U, // CMOVP_F
+ 272762393U, // CMOVNS16rm
+ 205653529U, // CMOVNS16rr
+ 339871266U, // CMOVNS32rm
+ 205653538U, // CMOVNS32rr
+ 406980139U, // CMOVNS64rm
+ 205653547U, // CMOVNS64rr
+ 272762420U, // CMOVO16rm
+ 205653556U, // CMOVO16rr
+ 339871292U, // CMOVO32rm
+ 205653564U, // CMOVO32rr
+ 406980164U, // CMOVO64rm
+ 205653572U, // CMOVO64rr
+ 272762444U, // CMOVP16rm
+ 205653580U, // CMOVP16rr
+ 339871316U, // CMOVP32rm
+ 205653588U, // CMOVP32rr
+ 406980188U, // CMOVP64rm
+ 205653596U, // CMOVP64rr
+ 83887716U, // CMOVP_F
0U, // CMOVP_Fp32
0U, // CMOVP_Fp64
0U, // CMOVP_Fp80
- 270567023U, // CMOVS16rm
- 203458159U, // CMOVS16rr
- 337675895U, // CMOVS32rm
- 203458167U, // CMOVS32rr
- 404784767U, // CMOVS64rm
- 203458175U, // CMOVS64rr
- 1671U, // CMOV_FR32
- 1690U, // CMOV_FR64
- 1709U, // CMOV_GR8
- 1727U, // CMOV_V1I64
- 1747U, // CMOV_V2F64
- 1767U, // CMOV_V2I64
- 1787U, // CMOV_V4F32
- 67110671U, // CMP16i16
- 135268111U, // CMP16mi
- 135268111U, // CMP16mi8
- 135268111U, // CMP16mr
- 1277200143U, // CMP16mrmrr
- 1277200143U, // CMP16ri
- 1277200143U, // CMP16ri8
- 1207961359U, // CMP16rm
- 1277200143U, // CMP16rr
- 70256405U, // CMP32i32
- 135333653U, // CMP32mi
- 135333653U, // CMP32mi8
- 135333653U, // CMP32mr
- 1277200149U, // CMP32mrmrr
- 1277200149U, // CMP32ri
- 1277200149U, // CMP32ri8
- 1342179093U, // CMP32rm
- 1277200149U, // CMP32rr
- 71304987U, // CMP64i32
- 135366427U, // CMP64mi32
- 135366427U, // CMP64mi8
- 135366427U, // CMP64mr
- 1277200155U, // CMP64mrmrr
- 1277200155U, // CMP64ri32
- 1277200155U, // CMP64ri8
- 1409287963U, // CMP64rm
- 1277200155U, // CMP64rr
- 72353569U, // CMP8i8
- 135399201U, // CMP8mi
- 135399201U, // CMP8mr
- 1277200161U, // CMP8mrmrr
- 1277200161U, // CMP8ri
- 1684014881U, // CMP8rm
- 1277200161U, // CMP8rr
- 1754433319U, // CMPPDrmi
- 1821574951U, // CMPPDrri
- 1755481895U, // CMPPSrmi
- 1822623527U, // CMPPSrri
- 1835U, // CMPS16
- 1841U, // CMPS32
- 1847U, // CMPS64
- 1853U, // CMPS8
- 1756596007U, // CMPSDrm
- 1823672103U, // CMPSDrr
- 1757677351U, // CMPSSrm
- 1824720679U, // CMPSSrr
- 1879050051U, // CMPXCHG16B
- 135268175U, // CMPXCHG16rm
- 1277200207U, // CMPXCHG16rr
- 135333721U, // CMPXCHG32rm
- 1277200217U, // CMPXCHG32rr
- 135366499U, // CMPXCHG64rm
- 1277200227U, // CMPXCHG64rr
- 1476396909U, // CMPXCHG8B
- 135399288U, // CMPXCHG8rm
- 1277200248U, // CMPXCHG8rr
- 1946158978U, // COMISDrm
- 1277200258U, // COMISDrr
- 1946158986U, // COMISSrm
- 1277200266U, // COMISSrr
- 73402258U, // COMP_FST0r
- 75499417U, // COM_FIPr
- 75499425U, // COM_FIr
- 73402280U, // COM_FST0r
- 1966U, // COS_F
+ 272762477U, // CMOVS16rm
+ 205653613U, // CMOVS16rr
+ 339871349U, // CMOVS32rm
+ 205653621U, // CMOVS32rr
+ 406980221U, // CMOVS64rm
+ 205653629U, // CMOVS64rr
+ 1669U, // CMOV_FR32
+ 1688U, // CMOV_FR64
+ 1707U, // CMOV_GR8
+ 1725U, // CMOV_V1I64
+ 1745U, // CMOV_V2F64
+ 1765U, // CMOV_V2I64
+ 1785U, // CMOV_V4F32
+ 67110669U, // CMP16i16
+ 136316685U, // CMP16mi
+ 136316685U, // CMP16mi8
+ 136316685U, // CMP16mr
+ 1279395597U, // CMP16mrmrr
+ 1279395597U, // CMP16ri
+ 1279395597U, // CMP16ri8
+ 1207961357U, // CMP16rm
+ 1279395597U, // CMP16rr
+ 73402131U, // CMP32i32
+ 136578835U, // CMP32mi
+ 136578835U, // CMP32mi8
+ 136578835U, // CMP32mr
+ 1279395603U, // CMP32mrmrr
+ 1279395603U, // CMP32ri
+ 1279395603U, // CMP32ri8
+ 1342179091U, // CMP32rm
+ 1279395603U, // CMP32rr
+ 75499289U, // CMP64i32
+ 136709913U, // CMP64mi32
+ 136709913U, // CMP64mi8
+ 136709913U, // CMP64mr
+ 1279395609U, // CMP64mrmrr
+ 1279395609U, // CMP64ri32
+ 1279395609U, // CMP64ri8
+ 1409287961U, // CMP64rm
+ 1279395609U, // CMP64rr
+ 77596447U, // CMP8i8
+ 136840991U, // CMP8mi
+ 136840991U, // CMP8mr
+ 1279395615U, // CMP8mrmrr
+ 1279395615U, // CMP8ri
+ 1690306335U, // CMP8rm
+ 1279395615U, // CMP8rr
+ 1764362021U, // CMPPDrmi
+ 1831601957U, // CMPPDrri
+ 1766459173U, // CMPPSrmi
+ 1833699109U, // CMPPSrri
+ 1833U, // CMPS16
+ 1839U, // CMPS32
+ 1845U, // CMPS64
+ 1851U, // CMPS8
+ 1768818469U, // CMPSDrm
+ 1835796261U, // CMPSDrr
+ 1771046693U, // CMPSSrm
+ 1837893413U, // CMPSSrr
+ 1879050049U, // CMPXCHG16B
+ 136316749U, // CMPXCHG16rm
+ 1279395661U, // CMPXCHG16rr
+ 136578903U, // CMPXCHG32rm
+ 1279395671U, // CMPXCHG32rr
+ 136709985U, // CMPXCHG64rm
+ 1279395681U, // CMPXCHG64rr
+ 1476396907U, // CMPXCHG8B
+ 136841078U, // CMPXCHG8rm
+ 1279395702U, // CMPXCHG8rr
+ 1946158976U, // COMISDrm
+ 1279395712U, // COMISDrr
+ 1946158984U, // COMISSrm
+ 1279395720U, // COMISSrr
+ 79693712U, // COMP_FST0r
+ 83888023U, // COM_FIPr
+ 83888031U, // COM_FIr
+ 79693734U, // COM_FST0r
+ 1964U, // COS_F
0U, // COS_Fp32
0U, // COS_Fp64
0U, // COS_Fp80
- 1971U, // CPUID
- 1977U, // CQO
- 282101694U, // CRC32m16
- 349210558U, // CRC32m32
- 483428286U, // CRC32m8
- 214992830U, // CRC32r16
- 214992830U, // CRC32r32
- 214992830U, // CRC32r8
- 416319422U, // CRC64m64
- 214992830U, // CRC64r64
- 1946159046U, // CVTDQ2PDrm
- 1277200326U, // CVTDQ2PDrr
- 1946159056U, // CVTDQ2PSrm
- 1277200336U, // CVTDQ2PSrr
- 1946159066U, // CVTPD2DQrm
- 1277200346U, // CVTPD2DQrr
- 1946159076U, // CVTPD2PSrm
- 1277200356U, // CVTPD2PSrr
- 1946159086U, // CVTPS2DQrm
- 1277200366U, // CVTPS2DQrr
- 2013267960U, // CVTPS2PDrm
- 1277200376U, // CVTPS2PDrr
- 2013267970U, // CVTSD2SI64rm
- 1277200386U, // CVTSD2SI64rr
- 2013267981U, // CVTSD2SSrm
- 1277200397U, // CVTSD2SSrr
- 1409288215U, // CVTSI2SD64rm
- 1277200407U, // CVTSI2SD64rr
- 1342179362U, // CVTSI2SDrm
- 1277200418U, // CVTSI2SDrr
- 1409288236U, // CVTSI2SS64rm
- 1277200428U, // CVTSI2SS64rr
- 1342179383U, // CVTSI2SSrm
- 1277200439U, // CVTSI2SSrr
- 2080376897U, // CVTSS2SDrm
- 1277200449U, // CVTSS2SDrr
- 2080376907U, // CVTSS2SI64rm
- 1277200459U, // CVTSS2SI64rr
- 2080376918U, // CVTSS2SIrm
- 1277200470U, // CVTSS2SIrr
- 1946159201U, // CVTTPS2DQrm
- 1277200481U, // CVTTPS2DQrr
- 2013268076U, // CVTTSD2SI64rm
- 1277200492U, // CVTTSD2SI64rr
- 2013268088U, // CVTTSD2SIrm
- 1277200504U, // CVTTSD2SIrr
- 2080376963U, // CVTTSS2SI64rm
- 1277200515U, // CVTTSS2SI64rr
- 2080376975U, // CVTTSS2SIrm
- 1277200527U, // CVTTSS2SIrr
- 2202U, // CWD
- 2207U, // CWDE
- 872417444U, // DEC16m
- 73402532U, // DEC16r
- 945817770U, // DEC32m
- 73402538U, // DEC32r
- 872417444U, // DEC64_16m
- 73402532U, // DEC64_16r
- 945817770U, // DEC64_32m
- 73402538U, // DEC64_32r
- 1476397232U, // DEC64m
- 73402544U, // DEC64r
- 1610614966U, // DEC8m
- 73402550U, // DEC8r
- 872417468U, // DIV16m
- 73402556U, // DIV16r
- 945817794U, // DIV32m
- 73402562U, // DIV32r
- 1476397256U, // DIV64m
- 73402568U, // DIV64r
- 1610614990U, // DIV8m
- 73402574U, // DIV8r
- 536873172U, // DIVPDrm
- 203458772U, // DIVPDrr
- 536873179U, // DIVPSrm
- 203458779U, // DIVPSrr
- 738199778U, // DIVR_F32m
- 805308650U, // DIVR_F64m
- 872417522U, // DIVR_FI16m
- 945817851U, // DIVR_FI32m
- 73402628U, // DIVR_FPrST0
- 73402635U, // DIVR_FST0r
+ 1969U, // CPUID
+ 1975U, // CQO
+ 295831484U, // CRC32m16
+ 362940348U, // CRC32m32
+ 497158076U, // CRC32m8
+ 228722620U, // CRC32r16
+ 228722620U, // CRC32r32
+ 228722620U, // CRC32r8
+ 430049212U, // CRC64m64
+ 228722620U, // CRC64r64
+ 1988U, // CS_PREFIX
+ 1946159047U, // CVTDQ2PDrm
+ 1279395783U, // CVTDQ2PDrr
+ 1946159057U, // CVTDQ2PSrm
+ 1279395793U, // CVTDQ2PSrr
+ 1946159067U, // CVTPD2DQrm
+ 1279395803U, // CVTPD2DQrr
+ 1946159077U, // CVTPD2PSrm
+ 1279395813U, // CVTPD2PSrr
+ 1946159087U, // CVTPS2DQrm
+ 1279395823U, // CVTPS2DQrr
+ 2013267961U, // CVTPS2PDrm
+ 1279395833U, // CVTPS2PDrr
+ 2013267971U, // CVTSD2SI64rm
+ 1279395843U, // CVTSD2SI64rr
+ 2013267982U, // CVTSD2SSrm
+ 1279395854U, // CVTSD2SSrr
+ 1409288216U, // CVTSI2SD64rm
+ 1279395864U, // CVTSI2SD64rr
+ 1342179363U, // CVTSI2SDrm
+ 1279395875U, // CVTSI2SDrr
+ 1409288237U, // CVTSI2SS64rm
+ 1279395885U, // CVTSI2SS64rr
+ 1342179384U, // CVTSI2SSrm
+ 1279395896U, // CVTSI2SSrr
+ 2080376898U, // CVTSS2SDrm
+ 1279395906U, // CVTSS2SDrr
+ 2080376908U, // CVTSS2SI64rm
+ 1279395916U, // CVTSS2SI64rr
+ 2080376919U, // CVTSS2SIrm
+ 1279395927U, // CVTSS2SIrr
+ 1946159202U, // CVTTPS2DQrm
+ 1279395938U, // CVTTPS2DQrr
+ 2013268077U, // CVTTSD2SI64rm
+ 1279395949U, // CVTTSD2SI64rr
+ 2013268089U, // CVTTSD2SIrm
+ 1279395961U, // CVTTSD2SIrr
+ 2080376964U, // CVTTSS2SI64rm
+ 1279395972U, // CVTTSS2SI64rr
+ 2080376976U, // CVTTSS2SIrm
+ 1279395984U, // CVTTSS2SIrr
+ 2203U, // CWD
+ 2208U, // CWDE
+ 872417445U, // DEC16m
+ 79693989U, // DEC16r
+ 952109227U, // DEC32m
+ 79693995U, // DEC32r
+ 872417445U, // DEC64_16m
+ 79693989U, // DEC64_16r
+ 952109227U, // DEC64_32m
+ 79693995U, // DEC64_32r
+ 1476397233U, // DEC64m
+ 79694001U, // DEC64r
+ 1610614967U, // DEC8m
+ 79694007U, // DEC8r
+ 872417469U, // DIV16m
+ 79694013U, // DIV16r
+ 952109251U, // DIV32m
+ 79694019U, // DIV32r
+ 1476397257U, // DIV64m
+ 79694025U, // DIV64r
+ 1610614991U, // DIV8m
+ 79694031U, // DIV8r
+ 536873173U, // DIVPDrm
+ 205654229U, // DIVPDrr
+ 536873180U, // DIVPSrm
+ 205654236U, // DIVPSrr
+ 738199779U, // DIVR_F32m
+ 805308651U, // DIVR_F64m
+ 872417523U, // DIVR_FI16m
+ 952109308U, // DIVR_FI32m
+ 79694085U, // DIVR_FPrST0
+ 79694092U, // DIVR_FST0r
0U, // DIVR_Fp32m
0U, // DIVR_Fp64m
0U, // DIVR_Fp64m32
@@ -597,21 +598,21 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // DIVR_FpI32m32
0U, // DIVR_FpI32m64
0U, // DIVR_FpI32m80
- 73402642U, // DIVR_FrST0
- 603982112U, // DIVSDrm
- 603982112U, // DIVSDrm_Int
- 203458848U, // DIVSDrr
- 203458848U, // DIVSDrr_Int
- 671090983U, // DIVSSrm
- 671090983U, // DIVSSrm_Int
- 203458855U, // DIVSSrr
- 203458855U, // DIVSSrr_Int
- 738199854U, // DIV_F32m
- 805308725U, // DIV_F64m
- 872417596U, // DIV_FI16m
- 945817924U, // DIV_FI32m
- 73402700U, // DIV_FPrST0
- 73402708U, // DIV_FST0r
+ 79694099U, // DIVR_FrST0
+ 603982113U, // DIVSDrm
+ 603982113U, // DIVSDrm_Int
+ 205654305U, // DIVSDrr
+ 205654305U, // DIVSDrr_Int
+ 671090984U, // DIVSSrm
+ 671090984U, // DIVSSrm_Int
+ 205654312U, // DIVSSrr
+ 205654312U, // DIVSSrr_Int
+ 738199855U, // DIV_F32m
+ 805308726U, // DIV_F64m
+ 872417597U, // DIV_FI16m
+ 952109381U, // DIV_FI32m
+ 79694157U, // DIV_FPrST0
+ 79694165U, // DIV_FST0r
0U, // DIV_Fp32
0U, // DIV_Fp32m
0U, // DIV_Fp64
@@ -626,82 +627,84 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // DIV_FpI32m32
0U, // DIV_FpI32m64
0U, // DIV_FpI32m80
- 73402714U, // DIV_FrST0
- 1013975401U, // DPPDrmi
- 1073744233U, // DPPDrri
- 1013975407U, // DPPSrmi
- 1073744239U, // DPPSrri
- 73402741U, // EH_RETURN
- 73402741U, // EH_RETURN64
- 68454796U, // ENTER
- 2162493843U, // EXTRACTPSmr
- 215320979U, // EXTRACTPSrr
- 2462U, // F2XM1
- 68454820U, // FARCALL16i
- 2214594988U, // FARCALL16m
- 68454837U, // FARCALL32i
- 2214595005U, // FARCALL32m
- 2214595014U, // FARCALL64
- 68454863U, // FARJMP16i
- 2214595030U, // FARJMP16m
- 68454878U, // FARJMP32i
- 2214595045U, // FARJMP32m
- 2214595053U, // FARJMP64
- 738200053U, // FBLDm
- 738200059U, // FBSTPm
- 738200066U, // FCOM32m
- 805308937U, // FCOM64m
- 738200081U, // FCOMP32m
- 805308953U, // FCOMP64m
- 2594U, // FCOMPP
- 2601U, // FDECSTP
- 73402929U, // FFREE
- 872417848U, // FICOM16m
- 945818176U, // FICOM32m
- 872417864U, // FICOMP16m
- 945818193U, // FICOMP32m
- 2650U, // FINCSTP
- 945818210U, // FISTTP32m
- 872417899U, // FLDCW16m
- 738200178U, // FLDENVm
- 2682U, // FLDL2E
- 2689U, // FLDL2T
- 2696U, // FLDLG2
- 2703U, // FLDLN2
- 2710U, // FLDPI
- 2716U, // FNCLEX
- 2723U, // FNINIT
- 2730U, // FNOP
- 872417967U, // FNSTCW16m
- 2743U, // FNSTSW8r
- 738200258U, // FNSTSWm
- 2762U, // FP32_TO_INT16_IN_MEM
- 2793U, // FP32_TO_INT32_IN_MEM
- 2824U, // FP32_TO_INT64_IN_MEM
- 2855U, // FP64_TO_INT16_IN_MEM
- 2886U, // FP64_TO_INT32_IN_MEM
- 2917U, // FP64_TO_INT64_IN_MEM
- 2948U, // FP80_TO_INT16_IN_MEM
- 2979U, // FP80_TO_INT32_IN_MEM
- 3010U, // FP80_TO_INT64_IN_MEM
- 3041U, // FPATAN
- 3048U, // FPREM
- 3054U, // FPREM1
- 3061U, // FPTAN
- 3067U, // FP_REG_KILL
- 3081U, // FRNDINT
- 738200593U, // FRSTORm
- 738200601U, // FSAVEm
- 3105U, // FSCALE
- 3112U, // FSINCOS
- 738200624U, // FSTENVm
- 1342180409U, // FS_MOV32rm
- 3139U, // FXAM
- 2214595656U, // FXRSTOR
- 2214595665U, // FXSAVE
- 3161U, // FXTRACT
- 3169U, // FYL2X
- 3175U, // FYL2XP1
+ 79694171U, // DIV_FrST0
+ 1021315434U, // DPPDrmi
+ 1073744234U, // DPPDrri
+ 1021315440U, // DPPSrmi
+ 1073744240U, // DPPSrri
+ 2422U, // DS_PREFIX
+ 79694201U, // EH_RETURN
+ 79694201U, // EH_RETURN64
+ 70388112U, // ENTER
+ 2455U, // ES_PREFIX
+ 2178156954U, // EXTRACTPSmr
+ 230033818U, // EXTRACTPSrr
+ 2469U, // F2XM1
+ 70388139U, // FARCALL16i
+ 2214594995U, // FARCALL16m
+ 70388156U, // FARCALL32i
+ 2214595012U, // FARCALL32m
+ 2214595021U, // FARCALL64
+ 70388182U, // FARJMP16i
+ 2214595037U, // FARJMP16m
+ 70388197U, // FARJMP32i
+ 2214595052U, // FARJMP32m
+ 2214595060U, // FARJMP64
+ 738200060U, // FBLDm
+ 738200066U, // FBSTPm
+ 738200073U, // FCOM32m
+ 805308944U, // FCOM64m
+ 738200088U, // FCOMP32m
+ 805308960U, // FCOMP64m
+ 2601U, // FCOMPP
+ 2608U, // FDECSTP
+ 79694392U, // FFREE
+ 872417855U, // FICOM16m
+ 952109639U, // FICOM32m
+ 872417871U, // FICOMP16m
+ 952109656U, // FICOMP32m
+ 2657U, // FINCSTP
+ 872417897U, // FLDCW16m
+ 738200176U, // FLDENVm
+ 2680U, // FLDL2E
+ 2687U, // FLDL2T
+ 2694U, // FLDLG2
+ 2701U, // FLDLN2
+ 2708U, // FLDPI
+ 2714U, // FNCLEX
+ 2721U, // FNINIT
+ 2728U, // FNOP
+ 872417965U, // FNSTCW16m
+ 2741U, // FNSTSW8r
+ 738200256U, // FNSTSWm
+ 2760U, // FP32_TO_INT16_IN_MEM
+ 2791U, // FP32_TO_INT32_IN_MEM
+ 2822U, // FP32_TO_INT64_IN_MEM
+ 2853U, // FP64_TO_INT16_IN_MEM
+ 2884U, // FP64_TO_INT32_IN_MEM
+ 2915U, // FP64_TO_INT64_IN_MEM
+ 2946U, // FP80_TO_INT16_IN_MEM
+ 2977U, // FP80_TO_INT32_IN_MEM
+ 3008U, // FP80_TO_INT64_IN_MEM
+ 3039U, // FPATAN
+ 3046U, // FPREM
+ 3052U, // FPREM1
+ 3059U, // FPTAN
+ 3065U, // FP_REG_KILL
+ 3079U, // FRNDINT
+ 738200591U, // FRSTORm
+ 738200599U, // FSAVEm
+ 3103U, // FSCALE
+ 3110U, // FSINCOS
+ 738200622U, // FSTENVm
+ 1342180407U, // FS_MOV32rm
+ 3137U, // FS_PREFIX
+ 3140U, // FXAM
+ 2214595657U, // FXRSTOR
+ 2214595666U, // FXSAVE
+ 3162U, // FXTRACT
+ 3170U, // FYL2X
+ 3176U, // FYL2XP1
0U, // FpGET_ST0_32
0U, // FpGET_ST0_64
0U, // FpGET_ST0_80
@@ -714,49 +717,50 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // FpSET_ST1_32
0U, // FpSET_ST1_64
0U, // FpSET_ST1_80
- 536871141U, // FsANDNPDrm
- 203456741U, // FsANDNPDrr
- 536871149U, // FsANDNPSrm
- 203456749U, // FsANDNPSrr
- 536871157U, // FsANDPDrm
- 203456757U, // FsANDPDrr
- 536871164U, // FsANDPSrm
- 203456764U, // FsANDPSrr
- 68553839U, // FsFLD0SD
- 68553839U, // FsFLD0SS
- 1946160245U, // FsMOVAPDrm
- 1277201525U, // FsMOVAPDrr
- 1946160253U, // FsMOVAPSrm
- 1277201533U, // FsMOVAPSrr
- 536874117U, // FsORPDrm
- 203459717U, // FsORPDrr
- 536874123U, // FsORPSrm
- 203459723U, // FsORPSrr
- 536874129U, // FsXORPDrm
- 203459729U, // FsXORPDrr
- 536874136U, // FsXORPSrm
- 203459736U, // FsXORPSrr
- 1342180511U, // GS_MOV32rm
- 536874153U, // HADDPDrm
- 203459753U, // HADDPDrr
- 536874161U, // HADDPSrm
- 203459761U, // HADDPSrr
- 3257U, // HLT
- 536874173U, // HSUBPDrm
- 203459773U, // HSUBPDrr
- 536874181U, // HSUBPSrm
- 203459781U, // HSUBPSrr
- 872418509U, // IDIV16m
- 73403597U, // IDIV16r
- 945818836U, // IDIV32m
- 73403604U, // IDIV32r
- 1476398299U, // IDIV64m
- 73403611U, // IDIV64r
- 1610616034U, // IDIV8m
- 73403618U, // IDIV8r
- 872418537U, // ILD_F16m
- 945818864U, // ILD_F32m
- 1476398327U, // ILD_F64m
+ 536871139U, // FsANDNPDrm
+ 205652195U, // FsANDNPDrr
+ 536871147U, // FsANDNPSrm
+ 205652203U, // FsANDNPSrr
+ 536871155U, // FsANDPDrm
+ 205652211U, // FsANDPDrr
+ 536871162U, // FsANDPSrm
+ 205652218U, // FsANDPSrr
+ 0U, // FsFLD0SD
+ 0U, // FsFLD0SS
+ 1946160240U, // FsMOVAPDrm
+ 1279396976U, // FsMOVAPDrr
+ 1946160248U, // FsMOVAPSrm
+ 1279396984U, // FsMOVAPSrr
+ 536874112U, // FsORPDrm
+ 205655168U, // FsORPDrr
+ 536874118U, // FsORPSrm
+ 205655174U, // FsORPSrr
+ 536874124U, // FsXORPDrm
+ 205655180U, // FsXORPDrr
+ 536874131U, // FsXORPSrm
+ 205655187U, // FsXORPSrr
+ 1342180506U, // GS_MOV32rm
+ 3236U, // GS_PREFIX
+ 536874151U, // HADDPDrm
+ 205655207U, // HADDPDrr
+ 536874159U, // HADDPSrm
+ 205655215U, // HADDPSrr
+ 3255U, // HLT
+ 536874171U, // HSUBPDrm
+ 205655227U, // HSUBPDrr
+ 536874179U, // HSUBPSrm
+ 205655235U, // HSUBPSrr
+ 872418507U, // IDIV16m
+ 79695051U, // IDIV16r
+ 952110290U, // IDIV32m
+ 79695058U, // IDIV32r
+ 1476398297U, // IDIV64m
+ 79695065U, // IDIV64r
+ 1610616032U, // IDIV8m
+ 79695072U, // IDIV8r
+ 872418535U, // ILD_F16m
+ 952110318U, // ILD_F32m
+ 1476398325U, // ILD_F64m
0U, // ILD_Fp16m32
0U, // ILD_Fp16m64
0U, // ILD_Fp16m80
@@ -766,67 +770,67 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // ILD_Fp64m32
0U, // ILD_Fp64m64
0U, // ILD_Fp64m80
- 872418559U, // IMUL16m
- 73403647U, // IMUL16r
- 270568703U, // IMUL16rm
- 2163215615U, // IMUL16rmi
- 2163215615U, // IMUL16rmi8
- 203459839U, // IMUL16rr
- 215321855U, // IMUL16rri
- 215321855U, // IMUL16rri8
- 945818886U, // IMUL32m
- 73403654U, // IMUL32r
- 337677574U, // IMUL32rm
- 2164264198U, // IMUL32rmi
- 2164264198U, // IMUL32rmi8
- 203459846U, // IMUL32rr
- 215321862U, // IMUL32rri
- 215321862U, // IMUL32rri8
- 1476398349U, // IMUL64m
- 73403661U, // IMUL64r
- 404786445U, // IMUL64rm
- 2165312781U, // IMUL64rmi32
- 2165312781U, // IMUL64rmi8
- 203459853U, // IMUL64rr
- 215321869U, // IMUL64rri32
- 215321869U, // IMUL64rri8
- 1610616084U, // IMUL8m
- 73403668U, // IMUL8r
- 3355U, // IN16
- 67112224U, // IN16ri
- 3365U, // IN16rr
- 3378U, // IN32
- 70257975U, // IN32ri
- 3388U, // IN32rr
- 3402U, // IN8
- 72355151U, // IN8ri
- 3412U, // IN8rr
- 872418657U, // INC16m
- 73403745U, // INC16r
- 945818983U, // INC32m
- 73403751U, // INC32r
- 872418657U, // INC64_16m
- 73403745U, // INC64_16r
- 945818983U, // INC64_32m
- 73403751U, // INC64_32r
- 1476398445U, // INC64m
- 73403757U, // INC64r
- 1610616179U, // INC8m
- 73403763U, // INC8r
- 1025510777U, // INSERTPSrm
- 1073745273U, // INSERTPSrr
- 73403779U, // INT
- 3464U, // INT3
- 3470U, // INVD
- 3475U, // INVEPT
- 3482U, // INVLPG
- 3489U, // INVVPID
- 3497U, // IRET16
- 3503U, // IRET32
- 3509U, // IRET64
- 872418747U, // ISTT_FP16m
- 945818210U, // ISTT_FP32m
- 1476398532U, // ISTT_FP64m
+ 872418557U, // IMUL16m
+ 79695101U, // IMUL16r
+ 272764157U, // IMUL16rm
+ 2178944253U, // IMUL16rmi
+ 2178944253U, // IMUL16rmi8
+ 205655293U, // IMUL16rr
+ 230034685U, // IMUL16rri
+ 230034685U, // IMUL16rri8
+ 952110340U, // IMUL32m
+ 79695108U, // IMUL32r
+ 339873028U, // IMUL32rm
+ 2181041412U, // IMUL32rmi
+ 2181041412U, // IMUL32rmi8
+ 205655300U, // IMUL32rr
+ 230034692U, // IMUL32rri
+ 230034692U, // IMUL32rri8
+ 1476398347U, // IMUL64m
+ 79695115U, // IMUL64r
+ 406981899U, // IMUL64rm
+ 2183138571U, // IMUL64rmi32
+ 2183138571U, // IMUL64rmi8
+ 205655307U, // IMUL64rr
+ 230034699U, // IMUL64rri32
+ 230034699U, // IMUL64rri8
+ 1610616082U, // IMUL8m
+ 79695122U, // IMUL8r
+ 3353U, // IN16
+ 67112222U, // IN16ri
+ 3363U, // IN16rr
+ 3376U, // IN32
+ 73403701U, // IN32ri
+ 3386U, // IN32rr
+ 3400U, // IN8
+ 77598029U, // IN8ri
+ 3410U, // IN8rr
+ 872418655U, // INC16m
+ 79695199U, // INC16r
+ 952110437U, // INC32m
+ 79695205U, // INC32r
+ 872418655U, // INC64_16m
+ 79695199U, // INC64_16r
+ 952110437U, // INC64_32m
+ 79695205U, // INC64_32r
+ 1476398443U, // INC64m
+ 79695211U, // INC64r
+ 1610616177U, // INC8m
+ 79695217U, // INC8r
+ 1044385143U, // INSERTPSrm
+ 1073745271U, // INSERTPSrr
+ 79695233U, // INT
+ 3462U, // INT3
+ 3468U, // INVD
+ 3473U, // INVEPT
+ 1610616216U, // INVLPG
+ 3488U, // INVVPID
+ 3496U, // IRET16
+ 3502U, // IRET32
+ 3508U, // IRET64
+ 872418746U, // ISTT_FP16m
+ 952110531U, // ISTT_FP32m
+ 1476398540U, // ISTT_FP64m
0U, // ISTT_Fp16m32
0U, // ISTT_Fp16m64
0U, // ISTT_Fp16m80
@@ -836,11 +840,11 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // ISTT_Fp64m32
0U, // ISTT_Fp64m64
0U, // ISTT_Fp64m80
- 872418766U, // IST_F16m
- 945819093U, // IST_F32m
- 872418780U, // IST_FP16m
- 945819108U, // IST_FP32m
- 1476398572U, // IST_FP64m
+ 872418774U, // IST_F16m
+ 952110557U, // IST_F32m
+ 872418788U, // IST_FP16m
+ 952110572U, // IST_FP32m
+ 1476398580U, // IST_FP64m
0U, // IST_Fp16m32
0U, // IST_Fp16m64
0U, // IST_Fp16m80
@@ -850,135 +854,135 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // IST_Fp64m32
0U, // IST_Fp64m64
0U, // IST_Fp64m80
- 1756596007U, // Int_CMPSDrm
- 1823672103U, // Int_CMPSDrr
- 1757677351U, // Int_CMPSSrm
- 1824720679U, // Int_CMPSSrr
- 1946158978U, // Int_COMISDrm
- 1277200258U, // Int_COMISDrr
- 1946158986U, // Int_COMISSrm
- 1277200266U, // Int_COMISSrr
- 1409288134U, // Int_CVTDQ2PDrm
- 1277200326U, // Int_CVTDQ2PDrr
- 2281703376U, // Int_CVTDQ2PSrm
- 1277200336U, // Int_CVTDQ2PSrr
- 1946159066U, // Int_CVTPD2DQrm
- 1277200346U, // Int_CVTPD2DQrr
- 1946160629U, // Int_CVTPD2PIrm
- 1277201909U, // Int_CVTPD2PIrr
- 1946159076U, // Int_CVTPD2PSrm
- 1277200356U, // Int_CVTPD2PSrr
- 1409289727U, // Int_CVTPI2PDrm
- 1277201919U, // Int_CVTPI2PDrr
- 404786697U, // Int_CVTPI2PSrm
- 203460105U, // Int_CVTPI2PSrr
- 1946159086U, // Int_CVTPS2DQrm
- 1277200366U, // Int_CVTPS2DQrr
- 2013267960U, // Int_CVTPS2PDrm
- 1277200376U, // Int_CVTPS2PDrr
- 2013269523U, // Int_CVTPS2PIrm
- 1277201939U, // Int_CVTPS2PIrr
- 1946159106U, // Int_CVTSD2SI64rm
- 1277200386U, // Int_CVTSD2SI64rr
- 1946160669U, // Int_CVTSD2SIrm
- 1277201949U, // Int_CVTSD2SIrr
- 603981837U, // Int_CVTSD2SSrm
- 203458573U, // Int_CVTSD2SSrr
- 404785175U, // Int_CVTSI2SD64rm
- 203458583U, // Int_CVTSI2SD64rr
- 337676322U, // Int_CVTSI2SDrm
- 203458594U, // Int_CVTSI2SDrr
- 404785196U, // Int_CVTSI2SS64rm
- 203458604U, // Int_CVTSI2SS64rr
- 337676343U, // Int_CVTSI2SSrm
- 203458615U, // Int_CVTSI2SSrr
- 671090753U, // Int_CVTSS2SDrm
- 203458625U, // Int_CVTSS2SDrr
- 2080376907U, // Int_CVTSS2SI64rm
- 1277200459U, // Int_CVTSS2SI64rr
- 2080378407U, // Int_CVTSS2SIrm
- 1277201959U, // Int_CVTSS2SIrr
- 1946160689U, // Int_CVTTPD2DQrm
- 1277201969U, // Int_CVTTPD2DQrr
- 1946160700U, // Int_CVTTPD2PIrm
- 1277201980U, // Int_CVTTPD2PIrr
- 1946159201U, // Int_CVTTPS2DQrm
- 1277200481U, // Int_CVTTPS2DQrr
- 2013269575U, // Int_CVTTPS2PIrm
- 1277201991U, // Int_CVTTPS2PIrr
- 1946159212U, // Int_CVTTSD2SI64rm
- 1277200492U, // Int_CVTTSD2SI64rr
- 1946159224U, // Int_CVTTSD2SIrm
- 1277200504U, // Int_CVTTSD2SIrr
- 2080376963U, // Int_CVTTSS2SI64rm
- 1277200515U, // Int_CVTTSS2SI64rr
- 2080376975U, // Int_CVTTSS2SIrm
- 1277200527U, // Int_CVTTSS2SIrr
- 1946160722U, // Int_UCOMISDrm
- 1277202002U, // Int_UCOMISDrr
- 1946160731U, // Int_UCOMISSrm
- 1277202011U, // Int_UCOMISSrr
- 1549799012U, // JA
- 1549799012U, // JA8
- 1549799016U, // JAE
- 1549799016U, // JAE8
- 1549799021U, // JB
- 1549799021U, // JB8
- 1549799025U, // JBE
- 1549799025U, // JBE8
- 1549799030U, // JCXZ8
- 1549799036U, // JE
- 1549799036U, // JE8
- 1549799040U, // JG
- 1549799040U, // JG8
- 1549799044U, // JGE
- 1549799044U, // JGE8
- 1549799049U, // JL
- 1549799049U, // JL8
- 1549799053U, // JLE
- 1549799053U, // JLE8
- 1549799058U, // JMP
- 945819287U, // JMP32m
- 73404055U, // JMP32r
- 1476398750U, // JMP64m
- 1549799077U, // JMP64pcrel32
- 73404062U, // JMP64r
- 1549799058U, // JMP8
- 1549799083U, // JNE
- 1549799083U, // JNE8
- 1549799088U, // JNO
- 1549799088U, // JNO8
- 1549799093U, // JNP
- 1549799093U, // JNP8
- 1549799098U, // JNS
- 1549799098U, // JNS8
- 1549799103U, // JO
- 1549799103U, // JO8
- 1549799107U, // JP
- 1549799107U, // JP8
- 1549799111U, // JS
- 1549799111U, // JS8
- 3787U, // LAHF
- 1207963344U, // LAR16rm
- 1277202128U, // LAR16rr
- 1207963350U, // LAR32rm
- 1277202134U, // LAR32rr
- 1207963356U, // LAR64rm
- 1277202140U, // LAR64rr
- 135270114U, // LCMPXCHG16
- 135335666U, // LCMPXCHG32
- 154144514U, // LCMPXCHG64
- 135401234U, // LCMPXCHG8
- 1476398882U, // LCMPXCHG8B
- 2281705267U, // LDDQUrm
- 945819450U, // LDMXCSR
- 2348814147U, // LDS16rm
- 2348814153U, // LDS32rm
- 3919U, // LD_F0
- 3924U, // LD_F1
- 738201433U, // LD_F32m
- 805310303U, // LD_F64m
- 2415923045U, // LD_F80m
+ 1768818469U, // Int_CMPSDrm
+ 1835796261U, // Int_CMPSDrr
+ 1771046693U, // Int_CMPSSrm
+ 1837893413U, // Int_CMPSSrr
+ 1946158976U, // Int_COMISDrm
+ 1279395712U, // Int_COMISDrr
+ 1946158984U, // Int_COMISSrm
+ 1279395720U, // Int_COMISSrr
+ 1409288135U, // Int_CVTDQ2PDrm
+ 1279395783U, // Int_CVTDQ2PDrr
+ 2281703377U, // Int_CVTDQ2PSrm
+ 1279395793U, // Int_CVTDQ2PSrr
+ 1946159067U, // Int_CVTPD2DQrm
+ 1279395803U, // Int_CVTPD2DQrr
+ 1946160637U, // Int_CVTPD2PIrm
+ 1279397373U, // Int_CVTPD2PIrr
+ 1946159077U, // Int_CVTPD2PSrm
+ 1279395813U, // Int_CVTPD2PSrr
+ 1409289735U, // Int_CVTPI2PDrm
+ 1279397383U, // Int_CVTPI2PDrr
+ 406982161U, // Int_CVTPI2PSrm
+ 205655569U, // Int_CVTPI2PSrr
+ 1946159087U, // Int_CVTPS2DQrm
+ 1279395823U, // Int_CVTPS2DQrr
+ 2013267961U, // Int_CVTPS2PDrm
+ 1279395833U, // Int_CVTPS2PDrr
+ 2013269531U, // Int_CVTPS2PIrm
+ 1279397403U, // Int_CVTPS2PIrr
+ 1946159107U, // Int_CVTSD2SI64rm
+ 1279395843U, // Int_CVTSD2SI64rr
+ 1946160677U, // Int_CVTSD2SIrm
+ 1279397413U, // Int_CVTSD2SIrr
+ 603981838U, // Int_CVTSD2SSrm
+ 205654030U, // Int_CVTSD2SSrr
+ 406980632U, // Int_CVTSI2SD64rm
+ 205654040U, // Int_CVTSI2SD64rr
+ 339871779U, // Int_CVTSI2SDrm
+ 205654051U, // Int_CVTSI2SDrr
+ 406980653U, // Int_CVTSI2SS64rm
+ 205654061U, // Int_CVTSI2SS64rr
+ 339871800U, // Int_CVTSI2SSrm
+ 205654072U, // Int_CVTSI2SSrr
+ 671090754U, // Int_CVTSS2SDrm
+ 205654082U, // Int_CVTSS2SDrr
+ 2080376908U, // Int_CVTSS2SI64rm
+ 1279395916U, // Int_CVTSS2SI64rr
+ 2080378415U, // Int_CVTSS2SIrm
+ 1279397423U, // Int_CVTSS2SIrr
+ 1946160697U, // Int_CVTTPD2DQrm
+ 1279397433U, // Int_CVTTPD2DQrr
+ 1946160708U, // Int_CVTTPD2PIrm
+ 1279397444U, // Int_CVTTPD2PIrr
+ 1946159202U, // Int_CVTTPS2DQrm
+ 1279395938U, // Int_CVTTPS2DQrr
+ 2013269583U, // Int_CVTTPS2PIrm
+ 1279397455U, // Int_CVTTPS2PIrr
+ 1946159213U, // Int_CVTTSD2SI64rm
+ 1279395949U, // Int_CVTTSD2SI64rr
+ 1946159225U, // Int_CVTTSD2SIrm
+ 1279395961U, // Int_CVTTSD2SIrr
+ 2080376964U, // Int_CVTTSS2SI64rm
+ 1279395972U, // Int_CVTTSS2SI64rr
+ 2080376976U, // Int_CVTTSS2SIrm
+ 1279395984U, // Int_CVTTSS2SIrr
+ 1946160730U, // Int_UCOMISDrm
+ 1279397466U, // Int_UCOMISDrr
+ 1946160739U, // Int_UCOMISSrm
+ 1279397475U, // Int_UCOMISSrr
+ 1556090476U, // JAE_1
+ 1556090476U, // JAE_4
+ 1556090481U, // JA_1
+ 1556090481U, // JA_4
+ 1556090485U, // JBE_1
+ 1556090485U, // JBE_4
+ 1556090490U, // JB_1
+ 1556090490U, // JB_4
+ 1556090494U, // JCXZ8
+ 1556090500U, // JE_1
+ 1556090500U, // JE_4
+ 1556090504U, // JGE_1
+ 1556090504U, // JGE_4
+ 1556090509U, // JG_1
+ 1556090509U, // JG_4
+ 1556090513U, // JLE_1
+ 1556090513U, // JLE_4
+ 1556090518U, // JL_1
+ 1556090518U, // JL_4
+ 952110746U, // JMP32m
+ 79695514U, // JMP32r
+ 1476398753U, // JMP64m
+ 1556090536U, // JMP64pcrel32
+ 79695521U, // JMP64r
+ 1556090542U, // JMP_1
+ 1556090542U, // JMP_4
+ 1556090547U, // JNE_1
+ 1556090547U, // JNE_4
+ 1556090552U, // JNO_1
+ 1556090552U, // JNO_4
+ 1556090557U, // JNP_1
+ 1556090557U, // JNP_4
+ 1556090562U, // JNS_1
+ 1556090562U, // JNS_4
+ 1556090567U, // JO_1
+ 1556090567U, // JO_4
+ 1556090571U, // JP_1
+ 1556090571U, // JP_4
+ 1556090575U, // JS_1
+ 1556090575U, // JS_4
+ 3795U, // LAHF
+ 1207963352U, // LAR16rm
+ 1279397592U, // LAR16rr
+ 1207963358U, // LAR32rm
+ 1279397598U, // LAR32rr
+ 1207963364U, // LAR64rm
+ 1279397604U, // LAR64rr
+ 136318698U, // LCMPXCHG16
+ 136580858U, // LCMPXCHG32
+ 174067466U, // LCMPXCHG64
+ 136843034U, // LCMPXCHG8
+ 1476398890U, // LCMPXCHG8B
+ 2281705275U, // LDDQUrm
+ 952110914U, // LDMXCSR
+ 2348814155U, // LDS16rm
+ 2348814161U, // LDS32rm
+ 3927U, // LD_F0
+ 3932U, // LD_F1
+ 738201441U, // LD_F32m
+ 805310311U, // LD_F64m
+ 2415923053U, // LD_F80m
0U, // LD_Fp032
0U, // LD_Fp064
0U, // LD_Fp080
@@ -991,463 +995,467 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // LD_Fp64m
0U, // LD_Fp64m80
0U, // LD_Fp80m
- 73404267U, // LD_Frr
- 2483031920U, // LEA16r
- 2483031926U, // LEA32r
- 2550140790U, // LEA64_32r
- 2617249660U, // LEA64r
- 3970U, // LEAVE
- 3970U, // LEAVE64
- 2348814216U, // LES16rm
- 2348814222U, // LES32rm
- 3988U, // LFENCE
- 2348814235U, // LFS16rm
- 2348814241U, // LFS32rm
- 2348814247U, // LFS64rm
- 2214596525U, // LGDTm
- 2348814259U, // LGS16rm
- 2348814265U, // LGS32rm
- 2348814271U, // LGS64rm
- 2214596549U, // LIDTm
- 872419275U, // LLDT16m
- 73404363U, // LLDT16r
- 872419282U, // LMSW16m
- 73404370U, // LMSW16r
- 135270361U, // LOCK_ADD16mi
- 135270361U, // LOCK_ADD16mi8
- 135270361U, // LOCK_ADD16mr
- 135335909U, // LOCK_ADD32mi
- 135335909U, // LOCK_ADD32mi8
- 135335909U, // LOCK_ADD32mr
- 135368689U, // LOCK_ADD64mi32
- 135368689U, // LOCK_ADD64mi8
- 135368689U, // LOCK_ADD64mr
- 135401469U, // LOCK_ADD8mi
- 135401469U, // LOCK_ADD8mr
- 872419337U, // LOCK_DEC16m
- 945819669U, // LOCK_DEC32m
- 1476399137U, // LOCK_DEC64m
- 1610616877U, // LOCK_DEC8m
- 872419385U, // LOCK_INC16m
- 945819717U, // LOCK_INC32m
- 1476399185U, // LOCK_INC64m
- 1610616925U, // LOCK_INC8m
- 135270505U, // LOCK_SUB16mi
- 135270505U, // LOCK_SUB16mi8
- 135270505U, // LOCK_SUB16mr
- 135336053U, // LOCK_SUB32mi
- 135336053U, // LOCK_SUB32mi8
- 135336053U, // LOCK_SUB32mr
- 135368833U, // LOCK_SUB64mi32
- 135368833U, // LOCK_SUB64mi8
- 135368833U, // LOCK_SUB64mr
- 135401613U, // LOCK_SUB8mi
- 135401613U, // LOCK_SUB8mr
- 4249U, // LODSB
- 4255U, // LODSD
- 4261U, // LODSQ
- 4267U, // LODSW
- 1549799601U, // LOOP
- 1549799607U, // LOOPE
- 1549799614U, // LOOPNE
- 4294U, // LRET
- 73404619U, // LRETI
- 1207963857U, // LSL16rm
- 1277202641U, // LSL16rr
- 1342181591U, // LSL32rm
- 1277202647U, // LSL32rr
- 1409290461U, // LSL64rm
- 1277202653U, // LSL64rr
- 2348814563U, // LSS16rm
- 2348814569U, // LSS32rm
- 2348814575U, // LSS64rm
- 872419573U, // LTRm
- 73404661U, // LTRr
- 1296077051U, // LXADD16
- 1297125640U, // LXADD32
- 1298174229U, // LXADD64
- 1299222817U, // LXADD8
- 1277202734U, // MASKMOVDQU
- 1277202734U, // MASKMOVDQU64
- 536875322U, // MAXPDrm
- 536875322U, // MAXPDrm_Int
- 203460922U, // MAXPDrr
- 203460922U, // MAXPDrr_Int
- 536875329U, // MAXPSrm
- 536875329U, // MAXPSrm_Int
- 203460929U, // MAXPSrr
- 203460929U, // MAXPSrr_Int
- 603984200U, // MAXSDrm
- 603984200U, // MAXSDrm_Int
- 203460936U, // MAXSDrr
- 203460936U, // MAXSDrr_Int
- 671093071U, // MAXSSrm
- 671093071U, // MAXSSrm_Int
- 203460943U, // MAXSSrr
- 203460943U, // MAXSSrr_Int
- 4438U, // MFENCE
- 536875357U, // MINPDrm
- 536875357U, // MINPDrm_Int
- 203460957U, // MINPDrr
- 203460957U, // MINPDrr_Int
- 536875364U, // MINPSrm
- 536875364U, // MINPSrm_Int
- 203460964U, // MINPSrr
- 203460964U, // MINPSrr_Int
- 603984235U, // MINSDrm
- 603984235U, // MINSDrm_Int
- 203460971U, // MINSDrr
- 203460971U, // MINSDrr_Int
- 671093106U, // MINSSrm
- 671093106U, // MINSSrm_Int
- 203460978U, // MINSSrr
- 203460978U, // MINSSrr_Int
- 1946160629U, // MMX_CVTPD2PIrm
- 1277201909U, // MMX_CVTPD2PIrr
- 1409289727U, // MMX_CVTPI2PDrm
- 1277201919U, // MMX_CVTPI2PDrr
- 1409289737U, // MMX_CVTPI2PSrm
- 1277201929U, // MMX_CVTPI2PSrr
- 2013269523U, // MMX_CVTPS2PIrm
- 1277201939U, // MMX_CVTPS2PIrr
- 1946160700U, // MMX_CVTTPD2PIrm
- 1277201980U, // MMX_CVTTPD2PIrr
- 2013269575U, // MMX_CVTTPS2PIrm
- 1277201991U, // MMX_CVTTPS2PIrr
- 4473U, // MMX_EMMS
- 4478U, // MMX_FEMMS
- 1277202820U, // MMX_MASKMOVQ
- 1277202820U, // MMX_MASKMOVQ64
- 1277202830U, // MMX_MOVD64from64rr
- 1277202830U, // MMX_MOVD64grr
- 135336334U, // MMX_MOVD64mr
- 1342181774U, // MMX_MOVD64rm
- 1277202830U, // MMX_MOVD64rr
- 1277202830U, // MMX_MOVD64rrv164
- 1277202830U, // MMX_MOVD64to64rr
- 1277202836U, // MMX_MOVDQ2Qrr
- 135369117U, // MMX_MOVNTQmr
- 1277202853U, // MMX_MOVQ2DQrr
- 1277202853U, // MMX_MOVQ2FR64rr
- 135369134U, // MMX_MOVQ64gmr
- 135369134U, // MMX_MOVQ64mr
- 1409290670U, // MMX_MOVQ64rm
- 1277202862U, // MMX_MOVQ64rr
- 1342181774U, // MMX_MOVZDI2PDIrm
- 1277202830U, // MMX_MOVZDI2PDIrr
- 404787636U, // MMX_PACKSSDWrm
- 203461044U, // MMX_PACKSSDWrr
- 404787646U, // MMX_PACKSSWBrm
- 203461054U, // MMX_PACKSSWBrr
- 404787656U, // MMX_PACKUSWBrm
- 203461064U, // MMX_PACKUSWBrr
- 404787666U, // MMX_PADDBrm
- 203461074U, // MMX_PADDBrr
- 404787673U, // MMX_PADDDrm
- 203461081U, // MMX_PADDDrr
- 404787680U, // MMX_PADDQrm
- 203461088U, // MMX_PADDQrr
- 404787687U, // MMX_PADDSBrm
- 203461095U, // MMX_PADDSBrr
- 404787695U, // MMX_PADDSWrm
- 203461103U, // MMX_PADDSWrr
- 404787703U, // MMX_PADDUSBrm
- 203461111U, // MMX_PADDUSBrr
- 404787712U, // MMX_PADDUSWrm
- 203461120U, // MMX_PADDUSWrr
- 404787721U, // MMX_PADDWrm
- 203461129U, // MMX_PADDWrr
- 404787728U, // MMX_PANDNrm
- 203461136U, // MMX_PANDNrr
- 404787735U, // MMX_PANDrm
- 203461143U, // MMX_PANDrr
- 404787741U, // MMX_PAVGBrm
- 203461149U, // MMX_PAVGBrr
- 404787748U, // MMX_PAVGWrm
- 203461156U, // MMX_PAVGWrr
- 404787755U, // MMX_PCMPEQBrm
- 203461163U, // MMX_PCMPEQBrr
- 404787764U, // MMX_PCMPEQDrm
- 203461172U, // MMX_PCMPEQDrr
- 404787773U, // MMX_PCMPEQWrm
- 203461181U, // MMX_PCMPEQWrr
- 404787782U, // MMX_PCMPGTBrm
- 203461190U, // MMX_PCMPGTBrr
- 404787791U, // MMX_PCMPGTDrm
- 203461199U, // MMX_PCMPGTDrr
- 404787800U, // MMX_PCMPGTWrm
- 203461208U, // MMX_PCMPGTWrr
- 215323233U, // MMX_PEXTRWri
- 1027969641U, // MMX_PINSRWrmi
- 1073746537U, // MMX_PINSRWrri
- 404787825U, // MMX_PMADDWDrm
- 203461233U, // MMX_PMADDWDrr
- 404787834U, // MMX_PMAXSWrm
- 203461242U, // MMX_PMAXSWrr
- 404787842U, // MMX_PMAXUBrm
- 203461250U, // MMX_PMAXUBrr
- 404787850U, // MMX_PMINSWrm
- 203461258U, // MMX_PMINSWrr
- 404787858U, // MMX_PMINUBrm
- 203461266U, // MMX_PMINUBrr
- 1277203098U, // MMX_PMOVMSKBrr
- 404787876U, // MMX_PMULHUWrm
- 203461284U, // MMX_PMULHUWrr
- 404787885U, // MMX_PMULHWrm
- 203461293U, // MMX_PMULHWrr
- 404787893U, // MMX_PMULLWrm
- 203461301U, // MMX_PMULLWrr
- 404787901U, // MMX_PMULUDQrm
- 203461309U, // MMX_PMULUDQrr
- 404787910U, // MMX_PORrm
- 203461318U, // MMX_PORrr
- 404787915U, // MMX_PSADBWrm
- 203461323U, // MMX_PSADBWrr
- 2165314259U, // MMX_PSHUFWmi
- 215323347U, // MMX_PSHUFWri
- 203461339U, // MMX_PSLLDri
- 404787931U, // MMX_PSLLDrm
- 203461339U, // MMX_PSLLDrr
- 203461346U, // MMX_PSLLQri
- 404787938U, // MMX_PSLLQrm
- 203461346U, // MMX_PSLLQrr
- 203461353U, // MMX_PSLLWri
- 404787945U, // MMX_PSLLWrm
- 203461353U, // MMX_PSLLWrr
- 203461360U, // MMX_PSRADri
- 404787952U, // MMX_PSRADrm
- 203461360U, // MMX_PSRADrr
- 203461367U, // MMX_PSRAWri
- 404787959U, // MMX_PSRAWrm
- 203461367U, // MMX_PSRAWrr
- 203461374U, // MMX_PSRLDri
- 404787966U, // MMX_PSRLDrm
- 203461374U, // MMX_PSRLDrr
- 203461381U, // MMX_PSRLQri
- 404787973U, // MMX_PSRLQrm
- 203461381U, // MMX_PSRLQrr
- 203461388U, // MMX_PSRLWri
- 404787980U, // MMX_PSRLWrm
- 203461388U, // MMX_PSRLWrr
- 404787987U, // MMX_PSUBBrm
- 203461395U, // MMX_PSUBBrr
- 404787994U, // MMX_PSUBDrm
- 203461402U, // MMX_PSUBDrr
- 404788001U, // MMX_PSUBQrm
- 203461409U, // MMX_PSUBQrr
- 404788008U, // MMX_PSUBSBrm
- 203461416U, // MMX_PSUBSBrr
- 404788016U, // MMX_PSUBSWrm
- 203461424U, // MMX_PSUBSWrr
- 404788024U, // MMX_PSUBUSBrm
- 203461432U, // MMX_PSUBUSBrr
- 404788033U, // MMX_PSUBUSWrm
- 203461441U, // MMX_PSUBUSWrr
- 404788042U, // MMX_PSUBWrm
- 203461450U, // MMX_PSUBWrr
- 404788049U, // MMX_PUNPCKHBWrm
- 203461457U, // MMX_PUNPCKHBWrr
- 404788060U, // MMX_PUNPCKHDQrm
- 203461468U, // MMX_PUNPCKHDQrr
- 404788071U, // MMX_PUNPCKHWDrm
- 203461479U, // MMX_PUNPCKHWDrr
- 404788082U, // MMX_PUNPCKLBWrm
- 203461490U, // MMX_PUNPCKLBWrr
- 404788093U, // MMX_PUNPCKLDQrm
- 203461501U, // MMX_PUNPCKLDQrr
- 404788104U, // MMX_PUNPCKLWDrm
- 203461512U, // MMX_PUNPCKLWDrr
- 404786287U, // MMX_PXORrm
- 203459695U, // MMX_PXORrr
- 68553839U, // MMX_V_SET0
- 68555316U, // MMX_V_SETALLONES
- 5011U, // MONITOR
- 1549800347U, // MOV16ao16
- 135271334U, // MOV16mi
- 135271334U, // MOV16mr
- 135271334U, // MOV16ms
- 1543508902U, // MOV16o16a
+ 79695731U, // LD_Frr
+ 2483031928U, // LEA16r
+ 2483031934U, // LEA32r
+ 2550140798U, // LEA64_32r
+ 2617249668U, // LEA64r
+ 3978U, // LEAVE
+ 3978U, // LEAVE64
+ 2348814224U, // LES16rm
+ 2348814230U, // LES32rm
+ 3996U, // LFENCE
+ 2348814243U, // LFS16rm
+ 2348814249U, // LFS32rm
+ 2348814255U, // LFS64rm
+ 2214596533U, // LGDTm
+ 2348814267U, // LGS16rm
+ 2348814273U, // LGS32rm
+ 2348814279U, // LGS64rm
+ 2214596557U, // LIDTm
+ 872419283U, // LLDT16m
+ 79695827U, // LLDT16r
+ 872419290U, // LMSW16m
+ 79695834U, // LMSW16r
+ 136318945U, // LOCK_ADD16mi
+ 136318945U, // LOCK_ADD16mi8
+ 136318945U, // LOCK_ADD16mr
+ 136581101U, // LOCK_ADD32mi
+ 136581101U, // LOCK_ADD32mi8
+ 136581101U, // LOCK_ADD32mr
+ 136712185U, // LOCK_ADD64mi32
+ 136712185U, // LOCK_ADD64mi8
+ 136712185U, // LOCK_ADD64mr
+ 136843269U, // LOCK_ADD8mi
+ 136843269U, // LOCK_ADD8mr
+ 872419345U, // LOCK_DEC16m
+ 952111133U, // LOCK_DEC32m
+ 1476399145U, // LOCK_DEC64m
+ 1610616885U, // LOCK_DEC8m
+ 872419393U, // LOCK_INC16m
+ 952111181U, // LOCK_INC32m
+ 1476399193U, // LOCK_INC64m
+ 1610616933U, // LOCK_INC8m
+ 4209U, // LOCK_PREFIX
+ 136319094U, // LOCK_SUB16mi
+ 136319094U, // LOCK_SUB16mi8
+ 136319094U, // LOCK_SUB16mr
+ 136581250U, // LOCK_SUB32mi
+ 136581250U, // LOCK_SUB32mi8
+ 136581250U, // LOCK_SUB32mr
+ 136712334U, // LOCK_SUB64mi32
+ 136712334U, // LOCK_SUB64mi8
+ 136712334U, // LOCK_SUB64mr
+ 136843418U, // LOCK_SUB8mi
+ 136843418U, // LOCK_SUB8mr
+ 4262U, // LODSB
+ 4268U, // LODSD
+ 4274U, // LODSQ
+ 4280U, // LODSW
+ 1556091070U, // LOOP
+ 1556091076U, // LOOPE
+ 1556091083U, // LOOPNE
+ 4307U, // LRET
+ 79696088U, // LRETI
+ 1207963870U, // LSL16rm
+ 1279398110U, // LSL16rr
+ 1342181604U, // LSL32rm
+ 1279398116U, // LSL32rr
+ 1409290474U, // LSL64rm
+ 1279398122U, // LSL64rr
+ 2348814576U, // LSS16rm
+ 2348814582U, // LSS32rm
+ 2348814588U, // LSS64rm
+ 872419586U, // LTRm
+ 79696130U, // LTRr
+ 1317146888U, // LXADD16
+ 1319244053U, // LXADD32
+ 1321341218U, // LXADD64
+ 1323438382U, // LXADD8
+ 1279398203U, // MASKMOVDQU
+ 1279398203U, // MASKMOVDQU64
+ 536875335U, // MAXPDrm
+ 536875335U, // MAXPDrm_Int
+ 205656391U, // MAXPDrr
+ 205656391U, // MAXPDrr_Int
+ 536875342U, // MAXPSrm
+ 536875342U, // MAXPSrm_Int
+ 205656398U, // MAXPSrr
+ 205656398U, // MAXPSrr_Int
+ 603984213U, // MAXSDrm
+ 603984213U, // MAXSDrm_Int
+ 205656405U, // MAXSDrr
+ 205656405U, // MAXSDrr_Int
+ 671093084U, // MAXSSrm
+ 671093084U, // MAXSSrm_Int
+ 205656412U, // MAXSSrr
+ 205656412U, // MAXSSrr_Int
+ 4451U, // MFENCE
+ 536875370U, // MINPDrm
+ 536875370U, // MINPDrm_Int
+ 205656426U, // MINPDrr
+ 205656426U, // MINPDrr_Int
+ 536875377U, // MINPSrm
+ 536875377U, // MINPSrm_Int
+ 205656433U, // MINPSrr
+ 205656433U, // MINPSrr_Int
+ 603984248U, // MINSDrm
+ 603984248U, // MINSDrm_Int
+ 205656440U, // MINSDrr
+ 205656440U, // MINSDrr_Int
+ 671093119U, // MINSSrm
+ 671093119U, // MINSSrm_Int
+ 205656447U, // MINSSrr
+ 205656447U, // MINSSrr_Int
+ 1946160637U, // MMX_CVTPD2PIrm
+ 1279397373U, // MMX_CVTPD2PIrr
+ 1409289735U, // MMX_CVTPI2PDrm
+ 1279397383U, // MMX_CVTPI2PDrr
+ 1409289745U, // MMX_CVTPI2PSrm
+ 1279397393U, // MMX_CVTPI2PSrr
+ 2013269531U, // MMX_CVTPS2PIrm
+ 1279397403U, // MMX_CVTPS2PIrr
+ 1946160708U, // MMX_CVTTPD2PIrm
+ 1279397444U, // MMX_CVTTPD2PIrr
+ 2013269583U, // MMX_CVTTPS2PIrm
+ 1279397455U, // MMX_CVTTPS2PIrr
+ 4486U, // MMX_EMMS
+ 4491U, // MMX_FEMMS
+ 1279398289U, // MMX_MASKMOVQ
+ 1279398289U, // MMX_MASKMOVQ64
+ 1279398299U, // MMX_MOVD64from64rr
+ 1279398299U, // MMX_MOVD64grr
+ 136581531U, // MMX_MOVD64mr
+ 1342181787U, // MMX_MOVD64rm
+ 1279398299U, // MMX_MOVD64rr
+ 1279398299U, // MMX_MOVD64rrv164
+ 1279398299U, // MMX_MOVD64to64rr
+ 1279398305U, // MMX_MOVDQ2Qrr
+ 136712618U, // MMX_MOVNTQmr
+ 1279398322U, // MMX_MOVQ2DQrr
+ 1279398322U, // MMX_MOVQ2FR64rr
+ 136712635U, // MMX_MOVQ64gmr
+ 136712635U, // MMX_MOVQ64mr
+ 1409290683U, // MMX_MOVQ64rm
+ 1279398331U, // MMX_MOVQ64rr
+ 1342181787U, // MMX_MOVZDI2PDIrm
+ 1279398299U, // MMX_MOVZDI2PDIrr
+ 406983105U, // MMX_PACKSSDWrm
+ 205656513U, // MMX_PACKSSDWrr
+ 406983115U, // MMX_PACKSSWBrm
+ 205656523U, // MMX_PACKSSWBrr
+ 406983125U, // MMX_PACKUSWBrm
+ 205656533U, // MMX_PACKUSWBrr
+ 406983135U, // MMX_PADDBrm
+ 205656543U, // MMX_PADDBrr
+ 406983142U, // MMX_PADDDrm
+ 205656550U, // MMX_PADDDrr
+ 406983149U, // MMX_PADDQrm
+ 205656557U, // MMX_PADDQrr
+ 406983156U, // MMX_PADDSBrm
+ 205656564U, // MMX_PADDSBrr
+ 406983164U, // MMX_PADDSWrm
+ 205656572U, // MMX_PADDSWrr
+ 406983172U, // MMX_PADDUSBrm
+ 205656580U, // MMX_PADDUSBrr
+ 406983181U, // MMX_PADDUSWrm
+ 205656589U, // MMX_PADDUSWrr
+ 406983190U, // MMX_PADDWrm
+ 205656598U, // MMX_PADDWrr
+ 406983197U, // MMX_PANDNrm
+ 205656605U, // MMX_PANDNrr
+ 406983204U, // MMX_PANDrm
+ 205656612U, // MMX_PANDrr
+ 406983210U, // MMX_PAVGBrm
+ 205656618U, // MMX_PAVGBrr
+ 406983217U, // MMX_PAVGWrm
+ 205656625U, // MMX_PAVGWrr
+ 406983224U, // MMX_PCMPEQBrm
+ 205656632U, // MMX_PCMPEQBrr
+ 406983233U, // MMX_PCMPEQDrm
+ 205656641U, // MMX_PCMPEQDrr
+ 406983242U, // MMX_PCMPEQWrm
+ 205656650U, // MMX_PCMPEQWrr
+ 406983251U, // MMX_PCMPGTBrm
+ 205656659U, // MMX_PCMPGTBrr
+ 406983260U, // MMX_PCMPGTDrm
+ 205656668U, // MMX_PCMPGTDrr
+ 406983269U, // MMX_PCMPGTWrm
+ 205656677U, // MMX_PCMPGTWrr
+ 230036078U, // MMX_PEXTRWri
+ 1050022518U, // MMX_PINSRWrmi
+ 1073746550U, // MMX_PINSRWrri
+ 406983294U, // MMX_PMADDWDrm
+ 205656702U, // MMX_PMADDWDrr
+ 406983303U, // MMX_PMAXSWrm
+ 205656711U, // MMX_PMAXSWrr
+ 406983311U, // MMX_PMAXUBrm
+ 205656719U, // MMX_PMAXUBrr
+ 406983319U, // MMX_PMINSWrm
+ 205656727U, // MMX_PMINSWrr
+ 406983327U, // MMX_PMINUBrm
+ 205656735U, // MMX_PMINUBrr
+ 1279398567U, // MMX_PMOVMSKBrr
+ 406983345U, // MMX_PMULHUWrm
+ 205656753U, // MMX_PMULHUWrr
+ 406983354U, // MMX_PMULHWrm
+ 205656762U, // MMX_PMULHWrr
+ 406983362U, // MMX_PMULLWrm
+ 205656770U, // MMX_PMULLWrr
+ 406983370U, // MMX_PMULUDQrm
+ 205656778U, // MMX_PMULUDQrr
+ 406983379U, // MMX_PORrm
+ 205656787U, // MMX_PORrr
+ 406983384U, // MMX_PSADBWrm
+ 205656792U, // MMX_PSADBWrr
+ 2183140064U, // MMX_PSHUFWmi
+ 230036192U, // MMX_PSHUFWri
+ 205656808U, // MMX_PSLLDri
+ 406983400U, // MMX_PSLLDrm
+ 205656808U, // MMX_PSLLDrr
+ 205656815U, // MMX_PSLLQri
+ 406983407U, // MMX_PSLLQrm
+ 205656815U, // MMX_PSLLQrr
+ 205656822U, // MMX_PSLLWri
+ 406983414U, // MMX_PSLLWrm
+ 205656822U, // MMX_PSLLWrr
+ 205656829U, // MMX_PSRADri
+ 406983421U, // MMX_PSRADrm
+ 205656829U, // MMX_PSRADrr
+ 205656836U, // MMX_PSRAWri
+ 406983428U, // MMX_PSRAWrm
+ 205656836U, // MMX_PSRAWrr
+ 205656843U, // MMX_PSRLDri
+ 406983435U, // MMX_PSRLDrm
+ 205656843U, // MMX_PSRLDrr
+ 205656850U, // MMX_PSRLQri
+ 406983442U, // MMX_PSRLQrm
+ 205656850U, // MMX_PSRLQrr
+ 205656857U, // MMX_PSRLWri
+ 406983449U, // MMX_PSRLWrm
+ 205656857U, // MMX_PSRLWrr
+ 406983456U, // MMX_PSUBBrm
+ 205656864U, // MMX_PSUBBrr
+ 406983463U, // MMX_PSUBDrm
+ 205656871U, // MMX_PSUBDrr
+ 406983470U, // MMX_PSUBQrm
+ 205656878U, // MMX_PSUBQrr
+ 406983477U, // MMX_PSUBSBrm
+ 205656885U, // MMX_PSUBSBrr
+ 406983485U, // MMX_PSUBSWrm
+ 205656893U, // MMX_PSUBSWrr
+ 406983493U, // MMX_PSUBUSBrm
+ 205656901U, // MMX_PSUBUSBrr
+ 406983502U, // MMX_PSUBUSWrm
+ 205656910U, // MMX_PSUBUSWrr
+ 406983511U, // MMX_PSUBWrm
+ 205656919U, // MMX_PSUBWrr
+ 406983518U, // MMX_PUNPCKHBWrm
+ 205656926U, // MMX_PUNPCKHBWrr
+ 406983529U, // MMX_PUNPCKHDQrm
+ 205656937U, // MMX_PUNPCKHDQrr
+ 406983540U, // MMX_PUNPCKHWDrm
+ 205656948U, // MMX_PUNPCKHWDrr
+ 406983551U, // MMX_PUNPCKLBWrm
+ 205656959U, // MMX_PUNPCKLBWrr
+ 406983562U, // MMX_PUNPCKLDQrm
+ 205656970U, // MMX_PUNPCKLDQrr
+ 406983573U, // MMX_PUNPCKLWDrm
+ 205656981U, // MMX_PUNPCKLWDrr
+ 406983584U, // MMX_PXORrm
+ 205656992U, // MMX_PXORrr
+ 0U, // MMX_V_SET0
+ 0U, // MMX_V_SETALLONES
+ 5030U, // MONITOR
+ 1556091822U, // MOV16ao16
+ 136319929U, // MOV16mi
+ 136319929U, // MOV16mr
+ 136319929U, // MOV16ms
+ 1543508921U, // MOV16o16a
0U, // MOV16r0
- 1277203366U, // MOV16ri
- 1207964582U, // MOV16rm
- 1277203366U, // MOV16rr
- 1277203366U, // MOV16rr_REV
- 1277203366U, // MOV16rs
- 1207964582U, // MOV16sm
- 1277203366U, // MOV16sr
- 1549800364U, // MOV32ao32
- 1277202862U, // MOV32cr
- 1277203384U, // MOV32dr
- 135336888U, // MOV32mi
- 135336888U, // MOV32mr
- 1546654648U, // MOV32o32a
- 68555710U, // MOV32r0
- 1277202862U, // MOV32rc
- 1277203384U, // MOV32rd
- 1277203384U, // MOV32ri
- 1342182328U, // MOV32rm
- 1277203384U, // MOV32rr
- 1277203384U, // MOV32rr_REV
- 1409291204U, // MOV64FSrm
- 1409291214U, // MOV64GSrm
- 1549800408U, // MOV64ao64
- 1549800408U, // MOV64ao8
- 1277202862U, // MOV64cr
- 1277202862U, // MOV64dr
- 135369134U, // MOV64mi32
- 135369134U, // MOV64mr
- 135369134U, // MOV64ms
- 1547702702U, // MOV64o64a
- 1547702702U, // MOV64o8a
+ 1279398841U, // MOV16ri
+ 1207964601U, // MOV16rm
+ 1279398841U, // MOV16rr
+ 1279398841U, // MOV16rr_REV
+ 1279398841U, // MOV16rs
+ 1207964601U, // MOV16sm
+ 1279398841U, // MOV16sr
+ 1556091839U, // MOV32ao32
+ 1279398331U, // MOV32cr
+ 1279398859U, // MOV32dr
+ 136582091U, // MOV32mi
+ 136582091U, // MOV32mr
+ 1549800395U, // MOV32o32a
+ 0U, // MOV32r0
+ 1279398331U, // MOV32rc
+ 1279398859U, // MOV32rd
+ 1279398859U, // MOV32ri
+ 1342182347U, // MOV32rm
+ 1279398859U, // MOV32rr
+ 1279398859U, // MOV32rr_REV
+ 1409291217U, // MOV64FSrm
+ 1409291227U, // MOV64GSrm
+ 1556091877U, // MOV64ao64
+ 1556091877U, // MOV64ao8
+ 1279398331U, // MOV64cr
+ 1279398331U, // MOV64dr
+ 136712635U, // MOV64mi32
+ 136712635U, // MOV64mr
+ 136712635U, // MOV64ms
+ 1551897019U, // MOV64o64a
+ 1551897019U, // MOV64o8a
0U, // MOV64r0
- 1277202862U, // MOV64rc
- 1277202862U, // MOV64rd
- 1277203428U, // MOV64ri
- 1277202862U, // MOV64ri32
+ 1279398331U, // MOV64rc
+ 1279398331U, // MOV64rd
+ 1279398897U, // MOV64ri
+ 1279398331U, // MOV64ri32
0U, // MOV64ri64i32
- 1409290670U, // MOV64rm
- 1277202862U, // MOV64rr
- 1277202862U, // MOV64rr_REV
- 1277202862U, // MOV64rs
- 1409290670U, // MOV64sm
- 1277202862U, // MOV64sr
- 1277202830U, // MOV64toPQIrr
- 1409290670U, // MOV64toSDrm
- 1277202830U, // MOV64toSDrr
- 1549800429U, // MOV8ao8
- 135402488U, // MOV8mi
- 135402488U, // MOV8mr
- 135402488U, // MOV8mr_NOREX
- 1548751864U, // MOV8o8a
- 68555774U, // MOV8r0
- 1277203448U, // MOV8ri
- 1684018168U, // MOV8rm
- 1702892536U, // MOV8rm_NOREX
- 1277203448U, // MOV8rr
- 1277596664U, // MOV8rr_NOREX
- 1277203448U, // MOV8rr_REV
- 135728245U, // MOVAPDmr
- 1946160245U, // MOVAPDrm
- 1277201525U, // MOVAPDrr
- 135728253U, // MOVAPSmr
- 1946160253U, // MOVAPSrm
- 1277201533U, // MOVAPSrr
- 2013271044U, // MOVDDUPrm
- 1277203460U, // MOVDDUPrr
- 1342181774U, // MOVDI2PDIrm
- 1277202830U, // MOVDI2PDIrr
- 1342181774U, // MOVDI2SSrm
- 1277202830U, // MOVDI2SSrr
- 135762957U, // MOVDQAmr
- 2281706509U, // MOVDQArm
- 1277203469U, // MOVDQArr
- 135762965U, // MOVDQUmr
- 135762965U, // MOVDQUmr_Int
- 2281706517U, // MOVDQUrm
- 2281706517U, // MOVDQUrm_Int
- 203461661U, // MOVHLPSrr
- 135795750U, // MOVHPDmr
- 603984934U, // MOVHPDrm
- 135795758U, // MOVHPSmr
- 603984942U, // MOVHPSrm
- 203461686U, // MOVLHPSrr
- 135795775U, // MOVLPDmr
- 603984959U, // MOVLPDrm
- 203461703U, // MOVLPDrr
- 135795790U, // MOVLPSmr
- 603984974U, // MOVLPSrm
- 203461718U, // MOVLPSrr
- 135369134U, // MOVLQ128mr
- 203461703U, // MOVLSD2PDrr
- 203461718U, // MOVLSS2PSrr
- 1277203549U, // MOVMSKPDrr
- 1277203559U, // MOVMSKPSrr
- 2281706609U, // MOVNTDQArm
- 135730299U, // MOVNTDQmr
- 135337092U, // MOVNTImr
- 135763084U, // MOVNTPDmr
- 135763093U, // MOVNTPSmr
+ 1409290683U, // MOV64rm
+ 1279398331U, // MOV64rr
+ 1279398331U, // MOV64rr_REV
+ 1279398331U, // MOV64rs
+ 1409290683U, // MOV64sm
+ 1279398331U, // MOV64sr
+ 1279398299U, // MOV64toPQIrr
+ 1409290683U, // MOV64toSDrm
+ 1279398299U, // MOV64toSDrr
+ 1556091898U, // MOV8ao8
+ 136844293U, // MOV8mi
+ 136844293U, // MOV8mr
+ 136877061U, // MOV8mr_NOREX
+ 1553994757U, // MOV8o8a
+ 0U, // MOV8r0
+ 1279398917U, // MOV8ri
+ 1690309637U, // MOV8rm
+ 1728058373U, // MOV8rm_NOREX
+ 1279398917U, // MOV8rr
+ 1280840709U, // MOV8rr_NOREX
+ 1279398917U, // MOV8rr_REV
+ 138022000U, // MOVAPDmr
+ 1946160240U, // MOVAPDrm
+ 1279396976U, // MOVAPDrr
+ 138022008U, // MOVAPSmr
+ 1946160248U, // MOVAPSrm
+ 1279396984U, // MOVAPSrr
+ 2013271051U, // MOVDDUPrm
+ 1279398923U, // MOVDDUPrr
+ 1342181787U, // MOVDI2PDIrm
+ 1279398299U, // MOVDI2PDIrr
+ 1342181787U, // MOVDI2SSrm
+ 1279398299U, // MOVDI2SSrr
+ 138155028U, // MOVDQAmr
+ 2281706516U, // MOVDQArm
+ 1279398932U, // MOVDQArr
+ 138155036U, // MOVDQUmr
+ 138155036U, // MOVDQUmr_Int
+ 2281706524U, // MOVDQUrm
+ 2281706524U, // MOVDQUrm_Int
+ 205657124U, // MOVHLPSrr
+ 138286125U, // MOVHPDmr
+ 603984941U, // MOVHPDrm
+ 138286133U, // MOVHPSmr
+ 603984949U, // MOVHPSrm
+ 205657149U, // MOVLHPSrr
+ 138286150U, // MOVLPDmr
+ 603984966U, // MOVLPDrm
+ 205657166U, // MOVLPDrr
+ 138286165U, // MOVLPSmr
+ 603984981U, // MOVLPSrm
+ 205657181U, // MOVLPSrr
+ 136712635U, // MOVLQ128mr
+ 205657166U, // MOVLSD2PDrr
+ 205657181U, // MOVLSS2PSrr
+ 1279399012U, // MOVMSKPDrr
+ 1279399022U, // MOVMSKPSrr
+ 2281706616U, // MOVNTDQArm
+ 138024066U, // MOVNTDQmr
+ 136582283U, // MOVNTImr
+ 138155155U, // MOVNTPDmr
+ 138155164U, // MOVNTPSmr
0U, // MOVPC32r
- 135795783U, // MOVPD2SDmr
- 1277203527U, // MOVPD2SDrr
- 135336334U, // MOVPDI2DImr
- 1277202830U, // MOVPDI2DIrr
- 135369134U, // MOVPQI2QImr
- 1277202830U, // MOVPQIto64rr
- 135599190U, // MOVPS2SSmr
- 1277203542U, // MOVPS2SSrr
- 1409290670U, // MOVQI2PQIrm
- 1277202862U, // MOVQxrxr
- 2013271111U, // MOVSD2PDrm
- 1277203527U, // MOVSD2PDrr
- 135795783U, // MOVSDmr
- 2013271111U, // MOVSDrm
- 1277203527U, // MOVSDrr
- 135369134U, // MOVSDto64mr
- 1277202830U, // MOVSDto64rr
- 1946162334U, // MOVSHDUPrm
- 1277203614U, // MOVSHDUPrr
- 1946162344U, // MOVSLDUPrm
- 1277203624U, // MOVSLDUPrr
- 135336334U, // MOVSS2DImr
- 1277202830U, // MOVSS2DIrr
- 2080379990U, // MOVSS2PSrm
- 1277203542U, // MOVSS2PSrr
- 135599190U, // MOVSSmr
- 2080379990U, // MOVSSrm
- 1277203542U, // MOVSSrr
+ 138286158U, // MOVPD2SDmr
+ 1279398990U, // MOVPD2SDrr
+ 136581531U, // MOVPDI2DImr
+ 1279398299U, // MOVPDI2DIrr
+ 136712635U, // MOVPQI2QImr
+ 1279398299U, // MOVPQIto64rr
+ 137630813U, // MOVPS2SSmr
+ 1279399005U, // MOVPS2SSrr
+ 1409290683U, // MOVQI2PQIrm
+ 1279398331U, // MOVQxrxr
+ 5285U, // MOVSB
+ 5291U, // MOVSD
+ 2013271118U, // MOVSD2PDrm
+ 1279398990U, // MOVSD2PDrr
+ 138286158U, // MOVSDmr
+ 2013271118U, // MOVSDrm
+ 1279398990U, // MOVSDrr
+ 136712635U, // MOVSDto64mr
+ 1279398299U, // MOVSDto64rr
+ 1946162353U, // MOVSHDUPrm
+ 1279399089U, // MOVSHDUPrr
+ 1946162363U, // MOVSLDUPrm
+ 1279399099U, // MOVSLDUPrr
+ 136581531U, // MOVSS2DImr
+ 1279398299U, // MOVSS2DIrr
+ 2080379997U, // MOVSS2PSrm
+ 1279399005U, // MOVSS2PSrr
+ 137630813U, // MOVSSmr
+ 2080379997U, // MOVSSrm
+ 1279399005U, // MOVSSrr
+ 5317U, // MOVSW
0U, // MOVSX16rm8
- 1684018354U, // MOVSX16rm8W
+ 1690309835U, // MOVSX16rm8W
0U, // MOVSX16rr8
- 1277203634U, // MOVSX16rr8W
- 1207964858U, // MOVSX32rm16
- 1684018370U, // MOVSX32rm8
- 1277203642U, // MOVSX32rr16
- 1277203650U, // MOVSX32rr8
- 1207964874U, // MOVSX64rm16
- 1342182610U, // MOVSX64rm32
- 1684018394U, // MOVSX64rm8
- 1277203658U, // MOVSX64rr16
- 1277203666U, // MOVSX64rr32
- 1277203674U, // MOVSX64rr8
- 135730402U, // MOVUPDmr
- 135730402U, // MOVUPDmr_Int
- 1946162402U, // MOVUPDrm
- 1946162402U, // MOVUPDrm_Int
- 1277203682U, // MOVUPDrr
- 135730410U, // MOVUPSmr
- 135730410U, // MOVUPSmr_Int
- 1946162410U, // MOVUPSrm
- 1946162410U, // MOVUPSrm_Int
- 1277203690U, // MOVUPSrr
- 1342181774U, // MOVZDI2PDIrm
- 1277202830U, // MOVZDI2PDIrr
- 2281705902U, // MOVZPQILo2PQIrm
- 1277202862U, // MOVZPQILo2PQIrr
- 1409290670U, // MOVZQI2PQIrm
- 1277202830U, // MOVZQI2PQIrr
- 2013271111U, // MOVZSD2PDrm
- 2080379990U, // MOVZSS2PSrm
+ 1279399115U, // MOVSX16rr8W
+ 1207964883U, // MOVSX32rm16
+ 1690309851U, // MOVSX32rm8
+ 1279399123U, // MOVSX32rr16
+ 1279399131U, // MOVSX32rr8
+ 1207964899U, // MOVSX64rm16
+ 1342182635U, // MOVSX64rm32
+ 1690309875U, // MOVSX64rm8
+ 1279399139U, // MOVSX64rr16
+ 1279399147U, // MOVSX64rr32
+ 1279399155U, // MOVSX64rr8
+ 138024187U, // MOVUPDmr
+ 138024187U, // MOVUPDmr_Int
+ 1946162427U, // MOVUPDrm
+ 1946162427U, // MOVUPDrm_Int
+ 1279399163U, // MOVUPDrr
+ 138024195U, // MOVUPSmr
+ 138024195U, // MOVUPSmr_Int
+ 1946162435U, // MOVUPSrm
+ 1946162435U, // MOVUPSrm_Int
+ 1279399171U, // MOVUPSrr
+ 1342181787U, // MOVZDI2PDIrm
+ 1279398299U, // MOVZDI2PDIrr
+ 2281705915U, // MOVZPQILo2PQIrm
+ 1279398331U, // MOVZPQILo2PQIrr
+ 1409290683U, // MOVZQI2PQIrm
+ 1279398299U, // MOVZQI2PQIrr
+ 2013271118U, // MOVZSD2PDrm
+ 2080379997U, // MOVZSS2PSrm
0U, // MOVZX16rm8
- 1684018418U, // MOVZX16rm8W
+ 1690309899U, // MOVZX16rm8W
0U, // MOVZX16rr8
- 1277203698U, // MOVZX16rr8W
- 1702892794U, // MOVZX32_NOREXrm8
- 1277596922U, // MOVZX32_NOREXrr8
- 1207964930U, // MOVZX32rm16
- 1684018426U, // MOVZX32rm8
- 1277203714U, // MOVZX32rr16
- 1277203706U, // MOVZX32rr8
+ 1279399179U, // MOVZX16rr8W
+ 1728058643U, // MOVZX32_NOREXrm8
+ 1280840979U, // MOVZX32_NOREXrr8
+ 1207964955U, // MOVZX32rm16
+ 1690309907U, // MOVZX32rm8
+ 1279399195U, // MOVZX32rr16
+ 1279399187U, // MOVZX32rr8
0U, // MOVZX64rm16
- 1207964938U, // MOVZX64rm16_Q
+ 1207964963U, // MOVZX64rm16_Q
0U, // MOVZX64rm32
0U, // MOVZX64rm8
- 1684018450U, // MOVZX64rm8_Q
+ 1690309931U, // MOVZX64rm8_Q
0U, // MOVZX64rr16
- 1277203722U, // MOVZX64rr16_Q
+ 1279399203U, // MOVZX64rr16_Q
0U, // MOVZX64rr32
0U, // MOVZX64rr8
- 1277203730U, // MOVZX64rr8_Q
+ 1279399211U, // MOVZX64rr8_Q
0U, // MOV_Fp3232
0U, // MOV_Fp3264
0U, // MOV_Fp3280
@@ -1457,34 +1465,34 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // MOV_Fp8032
0U, // MOV_Fp8064
0U, // MOV_Fp8080
- 1013978394U, // MPSADBWrmi
- 1073747226U, // MPSADBWrri
- 872420643U, // MUL16m
- 73405731U, // MUL16r
- 945820969U, // MUL32m
- 73405737U, // MUL32r
- 1476400431U, // MUL64m
- 73405743U, // MUL64r
- 1610618165U, // MUL8m
- 73405749U, // MUL8r
- 536876347U, // MULPDrm
- 203461947U, // MULPDrr
- 536876354U, // MULPSrm
- 203461954U, // MULPSrr
- 603985225U, // MULSDrm
- 603985225U, // MULSDrm_Int
- 203461961U, // MULSDrr
- 203461961U, // MULSDrr_Int
- 671094096U, // MULSSrm
- 671094096U, // MULSSrm_Int
- 203461968U, // MULSSrr
- 203461968U, // MULSSrr_Int
- 738202967U, // MUL_F32m
- 805311838U, // MUL_F64m
- 872420709U, // MUL_FI16m
- 945821037U, // MUL_FI32m
- 73405813U, // MUL_FPrST0
- 73405820U, // MUL_FST0r
+ 1021318451U, // MPSADBWrmi
+ 1073747251U, // MPSADBWrri
+ 872420668U, // MUL16m
+ 79697212U, // MUL16r
+ 952112450U, // MUL32m
+ 79697218U, // MUL32r
+ 1476400456U, // MUL64m
+ 79697224U, // MUL64r
+ 1610618190U, // MUL8m
+ 79697230U, // MUL8r
+ 536876372U, // MULPDrm
+ 205657428U, // MULPDrr
+ 536876379U, // MULPSrm
+ 205657435U, // MULPSrr
+ 603985250U, // MULSDrm
+ 603985250U, // MULSDrm_Int
+ 205657442U, // MULSDrr
+ 205657442U, // MULSDrr_Int
+ 671094121U, // MULSSrm
+ 671094121U, // MULSSrm_Int
+ 205657449U, // MULSSrr
+ 205657449U, // MULSSrr_Int
+ 738202992U, // MUL_F32m
+ 805311863U, // MUL_F64m
+ 872420734U, // MUL_FI16m
+ 952112518U, // MUL_FI32m
+ 79697294U, // MUL_FPrST0
+ 79697301U, // MUL_FST0r
0U, // MUL_Fp32
0U, // MUL_Fp32m
0U, // MUL_Fp64
@@ -1499,785 +1507,792 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // MUL_FpI32m32
0U, // MUL_FpI32m64
0U, // MUL_FpI32m80
- 73405826U, // MUL_FrST0
- 5520U, // MWAIT
- 872420758U, // NEG16m
- 73405846U, // NEG16r
- 945821084U, // NEG32m
- 73405852U, // NEG32r
- 1476400546U, // NEG64m
- 73405858U, // NEG64r
- 1610618280U, // NEG8m
- 73405864U, // NEG8r
- 5550U, // NOOP
- 945821106U, // NOOPL
- 872420792U, // NOOPW
- 872420798U, // NOT16m
- 73405886U, // NOT16r
- 945821124U, // NOT32m
- 73405892U, // NOT32r
- 1476400586U, // NOT64m
- 73405898U, // NOT64r
- 1610618320U, // NOT8m
- 73405904U, // NOT8r
- 67114454U, // OR16i16
- 135271894U, // OR16mi
- 135271894U, // OR16mi8
- 135271894U, // OR16mr
- 203462102U, // OR16ri
- 203462102U, // OR16ri8
- 270570966U, // OR16rm
- 203462102U, // OR16rr
- 203462102U, // OR16rr_REV
- 70260187U, // OR32i32
- 135337435U, // OR32mi
- 135337435U, // OR32mi8
- 135337435U, // OR32mr
- 203462107U, // OR32ri
- 203462107U, // OR32ri8
- 337679835U, // OR32rm
- 203462107U, // OR32rr
- 203462107U, // OR32rr_REV
- 71308768U, // OR64i32
- 135370208U, // OR64mi32
- 135370208U, // OR64mi8
- 135370208U, // OR64mr
- 203462112U, // OR64ri32
- 203462112U, // OR64ri8
- 404788704U, // OR64rm
- 203462112U, // OR64rr
- 203462112U, // OR64rr_REV
- 72357349U, // OR8i8
- 135402981U, // OR8mi
- 135402981U, // OR8mr
- 203462117U, // OR8ri
- 471897573U, // OR8rm
- 203462117U, // OR8rr
- 203462117U, // OR8rr_REV
- 536874117U, // ORPDrm
- 203459717U, // ORPDrr
- 536874123U, // ORPSrm
- 203459723U, // ORPSrr
- 73405930U, // OUT16ir
- 5621U, // OUT16rr
- 73405955U, // OUT32ir
- 5647U, // OUT32rr
- 73405982U, // OUT8ir
- 5673U, // OUT8rr
- 5687U, // OUTSB
- 5693U, // OUTSD
- 5699U, // OUTSW
- 2281707081U, // PABSBrm128
- 1409291849U, // PABSBrm64
- 1277204041U, // PABSBrr128
- 1277204041U, // PABSBrr64
- 2281707088U, // PABSDrm128
- 1409291856U, // PABSDrm64
- 1277204048U, // PABSDrr128
- 1277204048U, // PABSDrr64
- 2281707095U, // PABSWrm128
- 1409291863U, // PABSWrm64
- 1277204055U, // PABSWrr128
- 1277204055U, // PABSWrr64
- 1140855220U, // PACKSSDWrm
- 203461044U, // PACKSSDWrr
- 1140855230U, // PACKSSWBrm
- 203461054U, // PACKSSWBrr
- 1140856414U, // PACKUSDWrm
- 203462238U, // PACKUSDWrr
- 1140855240U, // PACKUSWBrm
- 203461064U, // PACKUSWBrr
- 1140855250U, // PADDBrm
- 203461074U, // PADDBrr
- 1140855257U, // PADDDrm
- 203461081U, // PADDDrr
- 1140855264U, // PADDQrm
- 203461088U, // PADDQrr
- 1140855271U, // PADDSBrm
- 203461095U, // PADDSBrr
- 1140855279U, // PADDSWrm
- 203461103U, // PADDSWrr
- 1140855287U, // PADDUSBrm
- 203461111U, // PADDUSBrr
- 1140855296U, // PADDUSWrm
- 203461120U, // PADDUSWrr
- 1140855305U, // PADDWrm
- 203461129U, // PADDWrr
- 1013978728U, // PALIGNR128rm
- 1073747560U, // PALIGNR128rr
- 1030067816U, // PALIGNR64rm
- 1073747560U, // PALIGNR64rr
- 1140855312U, // PANDNrm
- 203461136U, // PANDNrr
- 1140855319U, // PANDrm
- 203461143U, // PANDrr
- 1140855325U, // PAVGBrm
- 203461149U, // PAVGBrr
- 1140855332U, // PAVGWrm
- 203461156U, // PAVGWrr
- 1140856433U, // PBLENDVBrm0
- 203462257U, // PBLENDVBrr0
- 1013978754U, // PBLENDWrmi
- 1073747586U, // PBLENDWrri
- 1140855339U, // PCMPEQBrm
- 203461163U, // PCMPEQBrr
- 1140855348U, // PCMPEQDrm
- 203461172U, // PCMPEQDrr
- 1140856459U, // PCMPEQQrm
- 203462283U, // PCMPEQQrr
- 1140855357U, // PCMPEQWrm
- 203461181U, // PCMPEQWrr
- 2173703828U, // PCMPESTRIArm
- 215324308U, // PCMPESTRIArr
- 2173703828U, // PCMPESTRICrm
- 215324308U, // PCMPESTRICrr
- 2173703828U, // PCMPESTRIOrm
- 215324308U, // PCMPESTRIOrr
- 2173703828U, // PCMPESTRISrm
- 215324308U, // PCMPESTRISrr
- 2173703828U, // PCMPESTRIZrm
- 215324308U, // PCMPESTRIZrr
- 2173703828U, // PCMPESTRIrm
- 215324308U, // PCMPESTRIrr
- 5791U, // PCMPESTRM128MEM
- 5815U, // PCMPESTRM128REG
- 2173703887U, // PCMPESTRM128rm
- 215324367U, // PCMPESTRM128rr
- 1140855366U, // PCMPGTBrm
- 203461190U, // PCMPGTBrr
- 1140855375U, // PCMPGTDrm
- 203461199U, // PCMPGTDrr
- 1140856538U, // PCMPGTQrm
- 203462362U, // PCMPGTQrr
- 1140855384U, // PCMPGTWrm
- 203461208U, // PCMPGTWrr
- 2173703907U, // PCMPISTRIArm
- 215324387U, // PCMPISTRIArr
- 2173703907U, // PCMPISTRICrm
- 215324387U, // PCMPISTRICrr
- 2173703907U, // PCMPISTRIOrm
- 215324387U, // PCMPISTRIOrr
- 2173703907U, // PCMPISTRISrm
- 215324387U, // PCMPISTRISrr
- 2173703907U, // PCMPISTRIZrm
- 215324387U, // PCMPISTRIZrr
- 2173703907U, // PCMPISTRIrm
- 215324387U, // PCMPISTRIrr
- 5870U, // PCMPISTRM128MEM
- 5894U, // PCMPISTRM128REG
- 2173703966U, // PCMPISTRM128rm
- 215324446U, // PCMPISTRM128rr
- 2162300713U, // PEXTRBmr
- 215324457U, // PEXTRBrr
- 2162235185U, // PEXTRDmr
- 215324465U, // PEXTRDrr
- 2162267961U, // PEXTRQmr
- 215324473U, // PEXTRQrr
- 2162168417U, // PEXTRWmr
- 215323233U, // PEXTRWri
- 1140856641U, // PHADDDrm128
- 404789057U, // PHADDDrm64
- 203462465U, // PHADDDrr128
- 203462465U, // PHADDDrr64
- 1140856649U, // PHADDSWrm128
- 404789065U, // PHADDSWrm64
- 203462473U, // PHADDSWrr128
- 203462473U, // PHADDSWrr64
- 1140856658U, // PHADDWrm128
- 404789074U, // PHADDWrm64
- 203462482U, // PHADDWrr128
- 203462482U, // PHADDWrr64
- 2281707354U, // PHMINPOSUWrm128
- 1277204314U, // PHMINPOSUWrr128
- 1140856678U, // PHSUBDrm128
- 404789094U, // PHSUBDrm64
- 203462502U, // PHSUBDrr128
- 203462502U, // PHSUBDrr64
- 1140856686U, // PHSUBSWrm128
- 404789102U, // PHSUBSWrm64
- 203462510U, // PHSUBSWrr128
- 203462510U, // PHSUBSWrr64
- 1140856695U, // PHSUBWrm128
- 404789111U, // PHSUBWrm64
- 203462519U, // PHSUBWrr128
- 203462519U, // PHSUBWrr64
- 1031116671U, // PINSRBrm
- 1073747839U, // PINSRBrr
- 1029019527U, // PINSRDrm
- 1073747847U, // PINSRDrr
- 1030068111U, // PINSRQrm
- 1073747855U, // PINSRQrr
- 1027969641U, // PINSRWrmi
- 1073746537U, // PINSRWrri
- 1140856727U, // PMADDUBSWrm128
- 404789143U, // PMADDUBSWrm64
- 203462551U, // PMADDUBSWrr128
- 203462551U, // PMADDUBSWrr64
- 1140855409U, // PMADDWDrm
- 203461233U, // PMADDWDrr
- 1140856738U, // PMAXSBrm
- 203462562U, // PMAXSBrr
- 1140856746U, // PMAXSDrm
- 203462570U, // PMAXSDrr
- 1140855418U, // PMAXSWrm
- 203461242U, // PMAXSWrr
- 1140855426U, // PMAXUBrm
- 203461250U, // PMAXUBrr
- 1140856754U, // PMAXUDrm
- 203462578U, // PMAXUDrr
- 1140856762U, // PMAXUWrm
- 203462586U, // PMAXUWrr
- 1140856770U, // PMINSBrm
- 203462594U, // PMINSBrr
- 1140856778U, // PMINSDrm
- 203462602U, // PMINSDrr
- 1140855434U, // PMINSWrm
- 203461258U, // PMINSWrr
- 1140855442U, // PMINUBrm
- 203461266U, // PMINUBrr
- 1140856786U, // PMINUDrm
- 203462610U, // PMINUDrr
- 1140856794U, // PMINUWrm
- 203462618U, // PMINUWrr
- 1277203098U, // PMOVMSKBrr
- 1342183394U, // PMOVSXBDrm
- 1277204450U, // PMOVSXBDrr
- 1207965676U, // PMOVSXBQrm
- 1277204460U, // PMOVSXBQrr
- 1409292278U, // PMOVSXBWrm
- 1277204470U, // PMOVSXBWrr
- 1409292288U, // PMOVSXDQrm
- 1277204480U, // PMOVSXDQrr
- 1409292298U, // PMOVSXWDrm
- 1277204490U, // PMOVSXWDrr
- 1342183444U, // PMOVSXWQrm
- 1277204500U, // PMOVSXWQrr
- 1342183454U, // PMOVZXBDrm
- 1277204510U, // PMOVZXBDrr
- 1207965736U, // PMOVZXBQrm
- 1277204520U, // PMOVZXBQrr
- 1409292338U, // PMOVZXBWrm
- 1277204530U, // PMOVZXBWrr
- 1409292348U, // PMOVZXDQrm
- 1277204540U, // PMOVZXDQrr
- 1409292358U, // PMOVZXWDrm
- 1277204550U, // PMOVZXWDrr
- 1342183504U, // PMOVZXWQrm
- 1277204560U, // PMOVZXWQrr
- 1140856922U, // PMULDQrm
- 203462746U, // PMULDQrr
- 1140856930U, // PMULHRSWrm128
- 404789346U, // PMULHRSWrm64
- 203462754U, // PMULHRSWrr128
- 203462754U, // PMULHRSWrr64
- 1140855460U, // PMULHUWrm
- 203461284U, // PMULHUWrr
- 1140855469U, // PMULHWrm
- 203461293U, // PMULHWrr
- 1140856940U, // PMULLDrm
- 1140856940U, // PMULLDrm_int
- 203462764U, // PMULLDrr
- 203462764U, // PMULLDrr_int
- 1140855477U, // PMULLWrm
- 203461301U, // PMULLWrr
- 1140855485U, // PMULUDQrm
- 203461309U, // PMULUDQrr
- 73406580U, // POP16r
- 872421492U, // POP16rmm
- 73406580U, // POP16rmr
- 73406586U, // POP32r
- 945821818U, // POP32rmm
- 73406586U, // POP32rmr
- 73406592U, // POP64r
- 1476401280U, // POP64rmm
- 73406592U, // POP64rmr
- 1207965830U, // POPCNT16rm
- 1277204614U, // POPCNT16rr
- 1342183567U, // POPCNT32rm
- 1277204623U, // POPCNT32rr
- 1409292440U, // POPCNT64rm
- 1277204632U, // POPCNT64rr
- 6305U, // POPF
- 6311U, // POPFD
- 6317U, // POPFQ
- 6323U, // POPFS16
- 6332U, // POPFS32
- 6341U, // POPFS64
- 6350U, // POPGS16
- 6359U, // POPGS32
- 6368U, // POPGS64
- 1140855494U, // PORrm
- 203461318U, // PORrr
- 1610619113U, // PREFETCHNTA
- 1610619126U, // PREFETCHT0
- 1610619138U, // PREFETCHT1
- 1610619150U, // PREFETCHT2
- 1140855499U, // PSADBWrm
- 203461323U, // PSADBWrr
- 1140857114U, // PSHUFBrm128
- 404789530U, // PSHUFBrm64
- 203462938U, // PSHUFBrr128
- 203462938U, // PSHUFBrr64
- 2173704482U, // PSHUFDmi
- 215324962U, // PSHUFDri
- 2173704490U, // PSHUFHWmi
- 215324970U, // PSHUFHWri
- 2173704499U, // PSHUFLWmi
- 215324979U, // PSHUFLWri
- 1140857148U, // PSIGNBrm128
- 404789564U, // PSIGNBrm64
- 203462972U, // PSIGNBrr128
- 203462972U, // PSIGNBrr64
- 1140857156U, // PSIGNDrm128
- 404789572U, // PSIGNDrm64
- 203462980U, // PSIGNDrr128
- 203462980U, // PSIGNDrr64
- 1140857164U, // PSIGNWrm128
- 404789580U, // PSIGNWrm64
- 203462988U, // PSIGNWrr128
- 203462988U, // PSIGNWrr64
- 203462996U, // PSLLDQri
- 203461339U, // PSLLDri
- 1140855515U, // PSLLDrm
- 203461339U, // PSLLDrr
- 203461346U, // PSLLQri
- 1140855522U, // PSLLQrm
- 203461346U, // PSLLQrr
- 203461353U, // PSLLWri
- 1140855529U, // PSLLWrm
- 203461353U, // PSLLWrr
- 203461360U, // PSRADri
- 1140855536U, // PSRADrm
- 203461360U, // PSRADrr
- 203461367U, // PSRAWri
- 1140855543U, // PSRAWrm
- 203461367U, // PSRAWrr
- 203463004U, // PSRLDQri
- 203461374U, // PSRLDri
- 1140855550U, // PSRLDrm
- 203461374U, // PSRLDrr
- 203461381U, // PSRLQri
- 1140855557U, // PSRLQrm
- 203461381U, // PSRLQrr
- 203461388U, // PSRLWri
- 1140855564U, // PSRLWrm
- 203461388U, // PSRLWrr
- 1140855571U, // PSUBBrm
- 203461395U, // PSUBBrr
- 1140855578U, // PSUBDrm
- 203461402U, // PSUBDrr
- 1140855585U, // PSUBQrm
- 203461409U, // PSUBQrr
- 1140855592U, // PSUBSBrm
- 203461416U, // PSUBSBrr
- 1140855600U, // PSUBSWrm
- 203461424U, // PSUBSWrr
- 1140855608U, // PSUBUSBrm
- 203461432U, // PSUBUSBrr
- 1140855617U, // PSUBUSWrm
- 203461441U, // PSUBUSWrr
- 1140855626U, // PSUBWrm
- 203461450U, // PSUBWrr
- 2281707876U, // PTESTrm
- 1277204836U, // PTESTrr
- 1140855633U, // PUNPCKHBWrm
- 203461457U, // PUNPCKHBWrr
- 1140855644U, // PUNPCKHDQrm
- 203461468U, // PUNPCKHDQrr
- 1140857196U, // PUNPCKHQDQrm
- 203463020U, // PUNPCKHQDQrr
- 1140855655U, // PUNPCKHWDrm
- 203461479U, // PUNPCKHWDrr
- 1140855666U, // PUNPCKLBWrm
- 203461490U, // PUNPCKLBWrr
- 1140855677U, // PUNPCKLDQrm
- 203461501U, // PUNPCKLDQrr
- 1140857208U, // PUNPCKLQDQrm
- 203463032U, // PUNPCKLQDQrr
- 1140855688U, // PUNPCKLWDrm
- 203461512U, // PUNPCKLWDrr
- 73406852U, // PUSH16r
- 872421764U, // PUSH16rmm
- 73406852U, // PUSH16rmr
- 73406859U, // PUSH32i16
- 73406859U, // PUSH32i32
- 73406859U, // PUSH32i8
- 73406859U, // PUSH32r
- 945822091U, // PUSH32rmm
- 73406859U, // PUSH32rmr
- 73406866U, // PUSH64i16
- 73406866U, // PUSH64i32
- 73406866U, // PUSH64i8
- 73406866U, // PUSH64r
- 1476401554U, // PUSH64rmm
- 73406866U, // PUSH64rmr
- 6553U, // PUSHF
- 6560U, // PUSHFD
- 6567U, // PUSHFQ64
- 6574U, // PUSHFS16
- 6584U, // PUSHFS32
- 6594U, // PUSHFS64
- 6604U, // PUSHGS16
- 6614U, // PUSHGS32
- 6624U, // PUSHGS64
- 1140853871U, // PXORrm
- 203459695U, // PXORrr
- 872421866U, // RCL16m1
- 872421875U, // RCL16mCL
- 2711624190U, // RCL16mi
- 73406954U, // RCL16r1
- 73406963U, // RCL16rCL
- 203463166U, // RCL16ri
- 945822212U, // RCL32m1
- 945822221U, // RCL32mCL
- 2712672792U, // RCL32mi
- 73406980U, // RCL32r1
- 73406989U, // RCL32rCL
- 203463192U, // RCL32ri
- 1476401694U, // RCL64m1
- 1476401703U, // RCL64mCL
- 2713721394U, // RCL64mi
- 73407006U, // RCL64r1
- 73407015U, // RCL64rCL
- 203463218U, // RCL64ri
- 1610619448U, // RCL8m1
- 1610619457U, // RCL8mCL
- 2714769996U, // RCL8mi
- 73407032U, // RCL8r1
- 73407041U, // RCL8rCL
- 203463244U, // RCL8ri
- 1946163794U, // RCPPSm
- 1946163794U, // RCPPSm_Int
- 1277205074U, // RCPPSr
- 1277205074U, // RCPPSr_Int
- 2080381529U, // RCPSSm
- 2080381529U, // RCPSSm_Int
- 1277205081U, // RCPSSr
- 1277205081U, // RCPSSr_Int
- 872421984U, // RCR16m1
- 872421993U, // RCR16mCL
- 2711624308U, // RCR16mi
- 73407072U, // RCR16r1
- 73407081U, // RCR16rCL
- 203463284U, // RCR16ri
- 945822330U, // RCR32m1
- 945822339U, // RCR32mCL
- 2712672910U, // RCR32mi
- 73407098U, // RCR32r1
- 73407107U, // RCR32rCL
- 203463310U, // RCR32ri
- 1476401812U, // RCR64m1
- 1476401821U, // RCR64mCL
- 2713721512U, // RCR64mi
- 73407124U, // RCR64r1
- 73407133U, // RCR64rCL
- 203463336U, // RCR64ri
- 1610619566U, // RCR8m1
- 1610619575U, // RCR8mCL
- 2714770114U, // RCR8mi
- 73407150U, // RCR8r1
- 73407159U, // RCR8rCL
- 203463362U, // RCR8ri
- 6856U, // RDMSR
- 6862U, // RDPMC
- 6868U, // RDTSC
- 6874U, // REP_MOVSB
- 6884U, // REP_MOVSD
- 6894U, // REP_MOVSQ
- 6904U, // REP_MOVSW
- 6914U, // REP_STOSB
- 6924U, // REP_STOSD
- 6934U, // REP_STOSQ
- 6944U, // REP_STOSW
- 6954U, // RET
- 73407278U, // RETI
- 872422195U, // ROL16m1
- 872422201U, // ROL16mCL
- 135273267U, // ROL16mi
- 73407283U, // ROL16r1
- 73407289U, // ROL16rCL
- 203463475U, // ROL16ri
- 945822532U, // ROL32m1
- 945822538U, // ROL32mCL
- 135338820U, // ROL32mi
- 73407300U, // ROL32r1
- 73407306U, // ROL32rCL
- 203463492U, // ROL32ri
- 1476402005U, // ROL64m1
- 1476402011U, // ROL64mCL
- 135371605U, // ROL64mi
- 73407317U, // ROL64r1
- 73407323U, // ROL64rCL
- 203463509U, // ROL64ri
- 1610619750U, // ROL8m1
- 1610619756U, // ROL8mCL
- 135404390U, // ROL8mi
- 73407334U, // ROL8r1
- 73407340U, // ROL8rCL
- 203463526U, // ROL8ri
- 872422263U, // ROR16m1
- 872422269U, // ROR16mCL
- 135273335U, // ROR16mi
- 73407351U, // ROR16r1
- 73407357U, // ROR16rCL
- 203463543U, // ROR16ri
- 945822600U, // ROR32m1
- 945822606U, // ROR32mCL
- 135338888U, // ROR32mi
- 73407368U, // ROR32r1
- 73407374U, // ROR32rCL
- 203463560U, // ROR32ri
- 1476402073U, // ROR64m1
- 1476402079U, // ROR64mCL
- 135371673U, // ROR64mi
- 73407385U, // ROR64r1
- 73407391U, // ROR64rCL
- 203463577U, // ROR64ri
- 1610619818U, // ROR8m1
- 1610619824U, // ROR8mCL
- 135404458U, // ROR8mi
- 73407402U, // ROR8r1
- 73407408U, // ROR8rCL
- 203463594U, // ROR8ri
- 2178948027U, // ROUNDPDm_Int
- 215325627U, // ROUNDPDr_Int
- 2178948036U, // ROUNDPSm_Int
- 215325636U, // ROUNDPSr_Int
- 1039145933U, // ROUNDSDm_Int
- 1073748941U, // ROUNDSDr_Int
- 1025514454U, // ROUNDSSm_Int
- 1073748950U, // ROUNDSSr_Int
- 7135U, // RSM
- 1946164195U, // RSQRTPSm
- 1946164195U, // RSQRTPSm_Int
- 1277205475U, // RSQRTPSr
- 1277205475U, // RSQRTPSr_Int
- 2080381932U, // RSQRTSSm
- 2080381932U, // RSQRTSSm_Int
- 1277205484U, // RSQRTSSr
- 1277205484U, // RSQRTSSr_Int
- 7157U, // SAHF
- 872422394U, // SAR16m1
- 872422400U, // SAR16mCL
- 135273466U, // SAR16mi
- 73407482U, // SAR16r1
- 73407488U, // SAR16rCL
- 203463674U, // SAR16ri
- 945822731U, // SAR32m1
- 945822737U, // SAR32mCL
- 135339019U, // SAR32mi
- 73407499U, // SAR32r1
- 73407505U, // SAR32rCL
- 203463691U, // SAR32ri
- 1476402204U, // SAR64m1
- 1476402210U, // SAR64mCL
- 135371804U, // SAR64mi
- 73407516U, // SAR64r1
- 73407522U, // SAR64rCL
- 203463708U, // SAR64ri
- 1610619949U, // SAR8m1
- 1610619955U, // SAR8mCL
- 135404589U, // SAR8mi
- 73407533U, // SAR8r1
- 73407539U, // SAR8rCL
- 203463725U, // SAR8ri
- 67116094U, // SBB16i16
- 135273534U, // SBB16mi
- 135273534U, // SBB16mi8
- 135273534U, // SBB16mr
- 203463742U, // SBB16ri
- 203463742U, // SBB16ri8
- 270572606U, // SBB16rm
- 203463742U, // SBB16rr
- 203463742U, // SBB16rr_REV
- 70261828U, // SBB32i32
- 135339076U, // SBB32mi
- 135339076U, // SBB32mi8
- 135339076U, // SBB32mr
- 203463748U, // SBB32ri
- 203463748U, // SBB32ri8
- 337681476U, // SBB32rm
- 203463748U, // SBB32rr
- 203463748U, // SBB32rr_REV
- 71310410U, // SBB64i32
- 135371850U, // SBB64mi32
- 135371850U, // SBB64mi8
- 135371850U, // SBB64mr
- 203463754U, // SBB64ri32
- 203463754U, // SBB64ri8
- 404790346U, // SBB64rm
- 203463754U, // SBB64rr
- 203463754U, // SBB64rr_REV
- 72358992U, // SBB8i8
- 135404624U, // SBB8mi
- 135404624U, // SBB8mr
- 203463760U, // SBB8ri
- 471899216U, // SBB8rm
- 203463760U, // SBB8rr
- 203463760U, // SBB8rr_REV
- 7254U, // SCAS16
- 7260U, // SCAS32
- 7266U, // SCAS64
- 7272U, // SCAS8
- 1610620014U, // SETAEm
- 73407598U, // SETAEr
- 1610620021U, // SETAm
- 73407605U, // SETAr
- 1610620027U, // SETBEm
- 73407611U, // SETBEr
- 68557886U, // SETB_C16r
- 68557892U, // SETB_C32r
- 68557898U, // SETB_C64r
- 68557904U, // SETB_C8r
- 1610620034U, // SETBm
- 73407618U, // SETBr
- 1610620040U, // SETEm
- 73407624U, // SETEr
- 1610620046U, // SETGEm
- 73407630U, // SETGEr
- 1610620053U, // SETGm
- 73407637U, // SETGr
- 1610620059U, // SETLEm
- 73407643U, // SETLEr
- 1610620066U, // SETLm
- 73407650U, // SETLr
- 1610620072U, // SETNEm
- 73407656U, // SETNEr
- 1610620079U, // SETNOm
- 73407663U, // SETNOr
- 1610620086U, // SETNPm
- 73407670U, // SETNPr
- 1610620093U, // SETNSm
- 73407677U, // SETNSr
- 1610620100U, // SETOm
- 73407684U, // SETOr
- 1610620106U, // SETPm
- 73407690U, // SETPr
- 1610620112U, // SETSm
- 73407696U, // SETSr
- 7382U, // SFENCE
- 2214599901U, // SGDTm
- 872422627U, // SHL16m1
- 872422633U, // SHL16mCL
- 135273699U, // SHL16mi
- 73407715U, // SHL16r1
- 73407721U, // SHL16rCL
- 203463907U, // SHL16ri
- 945822964U, // SHL32m1
- 945822970U, // SHL32mCL
- 135339252U, // SHL32mi
- 73407732U, // SHL32r1
- 73407738U, // SHL32rCL
- 203463924U, // SHL32ri
- 1476402437U, // SHL64m1
- 1476402443U, // SHL64mCL
- 135372037U, // SHL64mi
- 73407749U, // SHL64r1
- 73407755U, // SHL64rCL
- 203463941U, // SHL64ri
- 1610620182U, // SHL8m1
- 1610620188U, // SHL8mCL
- 135404822U, // SHL8mi
- 73407766U, // SHL8r1
- 73407772U, // SHL8rCL
- 203463958U, // SHL8ri
- 135273767U, // SHLD16mrCL
- 2162171187U, // SHLD16mri8
- 203463975U, // SHLD16rrCL
- 1073749299U, // SHLD16rri8
- 135339322U, // SHLD32mrCL
- 2162236742U, // SHLD32mri8
- 203463994U, // SHLD32rrCL
- 1073749318U, // SHLD32rri8
- 135372109U, // SHLD64mrCL
- 2162269529U, // SHLD64mri8
- 203464013U, // SHLD64rrCL
- 1073749337U, // SHLD64rri8
- 872422752U, // SHR16m1
- 872422758U, // SHR16mCL
- 135273824U, // SHR16mi
- 73407840U, // SHR16r1
- 73407846U, // SHR16rCL
- 203464032U, // SHR16ri
- 945823089U, // SHR32m1
- 945823095U, // SHR32mCL
- 135339377U, // SHR32mi
- 73407857U, // SHR32r1
- 73407863U, // SHR32rCL
- 203464049U, // SHR32ri
- 1476402562U, // SHR64m1
- 1476402568U, // SHR64mCL
- 135372162U, // SHR64mi
- 73407874U, // SHR64r1
- 73407880U, // SHR64rCL
- 203464066U, // SHR64ri
- 1610620307U, // SHR8m1
- 1610620313U, // SHR8mCL
- 135404947U, // SHR8mi
- 73407891U, // SHR8r1
- 73407897U, // SHR8rCL
- 203464083U, // SHR8ri
- 135273892U, // SHRD16mrCL
- 2162171312U, // SHRD16mri8
- 203464100U, // SHRD16rrCL
- 1073749424U, // SHRD16rri8
- 135339447U, // SHRD32mrCL
- 2162236867U, // SHRD32mri8
- 203464119U, // SHRD32rrCL
- 1073749443U, // SHRD32rri8
- 135372234U, // SHRD64mrCL
- 2162269654U, // SHRD64mri8
- 203464138U, // SHRD64rrCL
- 1073749462U, // SHRD64rri8
- 1040195037U, // SHUFPDrmi
- 1073749469U, // SHUFPDrri
- 1040195045U, // SHUFPSrmi
- 1073749477U, // SHUFPSrri
- 2214600173U, // SIDTm
- 7667U, // SIN_F
+ 79697307U, // MUL_FrST0
+ 5545U, // MWAIT
+ 872420783U, // NEG16m
+ 79697327U, // NEG16r
+ 952112565U, // NEG32m
+ 79697333U, // NEG32r
+ 1476400571U, // NEG64m
+ 79697339U, // NEG64r
+ 1610618305U, // NEG8m
+ 79697345U, // NEG8r
+ 5575U, // NOOP
+ 952112587U, // NOOPL
+ 872420817U, // NOOPW
+ 872420823U, // NOT16m
+ 79697367U, // NOT16r
+ 952112605U, // NOT32m
+ 79697373U, // NOT32r
+ 1476400611U, // NOT64m
+ 79697379U, // NOT64r
+ 1610618345U, // NOT8m
+ 79697385U, // NOT8r
+ 67114479U, // OR16i16
+ 136320495U, // OR16mi
+ 136320495U, // OR16mi8
+ 136320495U, // OR16mr
+ 205657583U, // OR16ri
+ 205657583U, // OR16ri8
+ 272766447U, // OR16rm
+ 205657583U, // OR16rr
+ 205657583U, // OR16rr_REV
+ 73405940U, // OR32i32
+ 136582644U, // OR32mi
+ 136582644U, // OR32mi8
+ 136582644U, // OR32mr
+ 205657588U, // OR32ri
+ 205657588U, // OR32ri8
+ 339875316U, // OR32rm
+ 205657588U, // OR32rr
+ 205657588U, // OR32rr_REV
+ 75503097U, // OR64i32
+ 136713721U, // OR64mi32
+ 136713721U, // OR64mi8
+ 136713721U, // OR64mr
+ 205657593U, // OR64ri32
+ 205657593U, // OR64ri8
+ 406984185U, // OR64rm
+ 205657593U, // OR64rr
+ 205657593U, // OR64rr_REV
+ 77600254U, // OR8i8
+ 136844798U, // OR8mi
+ 136844798U, // OR8mr
+ 205657598U, // OR8ri
+ 474093054U, // OR8rm
+ 205657598U, // OR8rr
+ 205657598U, // OR8rr_REV
+ 536874112U, // ORPDrm
+ 205655168U, // ORPDrr
+ 536874118U, // ORPSrm
+ 205655174U, // ORPSrr
+ 79697411U, // OUT16ir
+ 5646U, // OUT16rr
+ 79697436U, // OUT32ir
+ 5672U, // OUT32rr
+ 79697463U, // OUT8ir
+ 5698U, // OUT8rr
+ 5712U, // OUTSB
+ 5718U, // OUTSD
+ 5724U, // OUTSW
+ 2281707106U, // PABSBrm128
+ 1409291874U, // PABSBrm64
+ 1279399522U, // PABSBrr128
+ 1279399522U, // PABSBrr64
+ 2281707113U, // PABSDrm128
+ 1409291881U, // PABSDrm64
+ 1279399529U, // PABSDrr128
+ 1279399529U, // PABSDrr64
+ 2281707120U, // PABSWrm128
+ 1409291888U, // PABSWrm64
+ 1279399536U, // PABSWrr128
+ 1279399536U, // PABSWrr64
+ 1140855233U, // PACKSSDWrm
+ 205656513U, // PACKSSDWrr
+ 1140855243U, // PACKSSWBrm
+ 205656523U, // PACKSSWBrr
+ 1140856439U, // PACKUSDWrm
+ 205657719U, // PACKUSDWrr
+ 1140855253U, // PACKUSWBrm
+ 205656533U, // PACKUSWBrr
+ 1140855263U, // PADDBrm
+ 205656543U, // PADDBrr
+ 1140855270U, // PADDDrm
+ 205656550U, // PADDDrr
+ 1140855277U, // PADDQrm
+ 205656557U, // PADDQrr
+ 1140855284U, // PADDSBrm
+ 205656564U, // PADDSBrr
+ 1140855292U, // PADDSWrm
+ 205656572U, // PADDSWrr
+ 1140855300U, // PADDUSBrm
+ 205656580U, // PADDUSBrr
+ 1140855309U, // PADDUSWrm
+ 205656589U, // PADDUSWrr
+ 1140855318U, // PADDWrm
+ 205656598U, // PADDWrr
+ 1021318785U, // PALIGNR128rm
+ 1073747585U, // PALIGNR128rr
+ 1054217857U, // PALIGNR64rm
+ 1073747585U, // PALIGNR64rr
+ 1140855325U, // PANDNrm
+ 205656605U, // PANDNrr
+ 1140855332U, // PANDrm
+ 205656612U, // PANDrr
+ 1140855338U, // PAVGBrm
+ 205656618U, // PAVGBrr
+ 1140855345U, // PAVGWrm
+ 205656625U, // PAVGWrr
+ 1140856458U, // PBLENDVBrm0
+ 205657738U, // PBLENDVBrr0
+ 1021318811U, // PBLENDWrmi
+ 1073747611U, // PBLENDWrri
+ 1140855352U, // PCMPEQBrm
+ 205656632U, // PCMPEQBrr
+ 1140855361U, // PCMPEQDrm
+ 205656641U, // PCMPEQDrr
+ 1140856484U, // PCMPEQQrm
+ 205657764U, // PCMPEQQrr
+ 1140855370U, // PCMPEQWrm
+ 205656650U, // PCMPEQWrr
+ 2199918253U, // PCMPESTRIArm
+ 230037165U, // PCMPESTRIArr
+ 2199918253U, // PCMPESTRICrm
+ 230037165U, // PCMPESTRICrr
+ 2199918253U, // PCMPESTRIOrm
+ 230037165U, // PCMPESTRIOrr
+ 2199918253U, // PCMPESTRISrm
+ 230037165U, // PCMPESTRISrr
+ 2199918253U, // PCMPESTRIZrm
+ 230037165U, // PCMPESTRIZrr
+ 2199918253U, // PCMPESTRIrm
+ 230037165U, // PCMPESTRIrr
+ 5816U, // PCMPESTRM128MEM
+ 5840U, // PCMPESTRM128REG
+ 2199918312U, // PCMPESTRM128rm
+ 230037224U, // PCMPESTRM128rr
+ 1140855379U, // PCMPGTBrm
+ 205656659U, // PCMPGTBrr
+ 1140855388U, // PCMPGTDrm
+ 205656668U, // PCMPGTDrr
+ 1140856563U, // PCMPGTQrm
+ 205657843U, // PCMPGTQrr
+ 1140855397U, // PCMPGTWrm
+ 205656677U, // PCMPGTWrr
+ 2199918332U, // PCMPISTRIArm
+ 230037244U, // PCMPISTRIArr
+ 2199918332U, // PCMPISTRICrm
+ 230037244U, // PCMPISTRICrr
+ 2199918332U, // PCMPISTRIOrm
+ 230037244U, // PCMPISTRIOrr
+ 2199918332U, // PCMPISTRISrm
+ 230037244U, // PCMPISTRISrr
+ 2199918332U, // PCMPISTRIZrm
+ 230037244U, // PCMPISTRIZrr
+ 2199918332U, // PCMPISTRIrm
+ 230037244U, // PCMPISTRIrr
+ 5895U, // PCMPISTRM128MEM
+ 5919U, // PCMPISTRM128REG
+ 2199918391U, // PCMPISTRM128rm
+ 230037303U, // PCMPISTRM128rr
+ 2177374018U, // PEXTRBmr
+ 230037314U, // PEXTRBrr
+ 2177111882U, // PEXTRDmr
+ 230037322U, // PEXTRDrr
+ 2177242962U, // PEXTRQmr
+ 230037330U, // PEXTRQrr
+ 2176848494U, // PEXTRWmr
+ 230036078U, // PEXTRWri
+ 1140856666U, // PHADDDrm128
+ 406984538U, // PHADDDrm64
+ 205657946U, // PHADDDrr128
+ 205657946U, // PHADDDrr64
+ 1140856674U, // PHADDSWrm128
+ 406984546U, // PHADDSWrm64
+ 205657954U, // PHADDSWrr128
+ 205657954U, // PHADDSWrr64
+ 1140856683U, // PHADDWrm128
+ 406984555U, // PHADDWrm64
+ 205657963U, // PHADDWrr128
+ 205657963U, // PHADDWrr64
+ 2281707379U, // PHMINPOSUWrm128
+ 1279399795U, // PHMINPOSUWrr128
+ 1140856703U, // PHSUBDrm128
+ 406984575U, // PHSUBDrm64
+ 205657983U, // PHSUBDrr128
+ 205657983U, // PHSUBDrr64
+ 1140856711U, // PHSUBSWrm128
+ 406984583U, // PHSUBSWrm64
+ 205657991U, // PHSUBSWrr128
+ 205657991U, // PHSUBSWrr64
+ 1140856720U, // PHSUBWrm128
+ 406984592U, // PHSUBWrm64
+ 205658000U, // PHSUBWrr128
+ 205658000U, // PHSUBWrr64
+ 1056315288U, // PINSRBrm
+ 1073747864U, // PINSRBrr
+ 1052120992U, // PINSRDrm
+ 1073747872U, // PINSRDrr
+ 1054218152U, // PINSRQrm
+ 1073747880U, // PINSRQrr
+ 1050022518U, // PINSRWrmi
+ 1073746550U, // PINSRWrri
+ 1140856752U, // PMADDUBSWrm128
+ 406984624U, // PMADDUBSWrm64
+ 205658032U, // PMADDUBSWrr128
+ 205658032U, // PMADDUBSWrr64
+ 1140855422U, // PMADDWDrm
+ 205656702U, // PMADDWDrr
+ 1140856763U, // PMAXSBrm
+ 205658043U, // PMAXSBrr
+ 1140856771U, // PMAXSDrm
+ 205658051U, // PMAXSDrr
+ 1140855431U, // PMAXSWrm
+ 205656711U, // PMAXSWrr
+ 1140855439U, // PMAXUBrm
+ 205656719U, // PMAXUBrr
+ 1140856779U, // PMAXUDrm
+ 205658059U, // PMAXUDrr
+ 1140856787U, // PMAXUWrm
+ 205658067U, // PMAXUWrr
+ 1140856795U, // PMINSBrm
+ 205658075U, // PMINSBrr
+ 1140856803U, // PMINSDrm
+ 205658083U, // PMINSDrr
+ 1140855447U, // PMINSWrm
+ 205656727U, // PMINSWrr
+ 1140855455U, // PMINUBrm
+ 205656735U, // PMINUBrr
+ 1140856811U, // PMINUDrm
+ 205658091U, // PMINUDrr
+ 1140856819U, // PMINUWrm
+ 205658099U, // PMINUWrr
+ 1279398567U, // PMOVMSKBrr
+ 1342183419U, // PMOVSXBDrm
+ 1279399931U, // PMOVSXBDrr
+ 1207965701U, // PMOVSXBQrm
+ 1279399941U, // PMOVSXBQrr
+ 1409292303U, // PMOVSXBWrm
+ 1279399951U, // PMOVSXBWrr
+ 1409292313U, // PMOVSXDQrm
+ 1279399961U, // PMOVSXDQrr
+ 1409292323U, // PMOVSXWDrm
+ 1279399971U, // PMOVSXWDrr
+ 1342183469U, // PMOVSXWQrm
+ 1279399981U, // PMOVSXWQrr
+ 1342183479U, // PMOVZXBDrm
+ 1279399991U, // PMOVZXBDrr
+ 1207965761U, // PMOVZXBQrm
+ 1279400001U, // PMOVZXBQrr
+ 1409292363U, // PMOVZXBWrm
+ 1279400011U, // PMOVZXBWrr
+ 1409292373U, // PMOVZXDQrm
+ 1279400021U, // PMOVZXDQrr
+ 1409292383U, // PMOVZXWDrm
+ 1279400031U, // PMOVZXWDrr
+ 1342183529U, // PMOVZXWQrm
+ 1279400041U, // PMOVZXWQrr
+ 1140856947U, // PMULDQrm
+ 205658227U, // PMULDQrr
+ 1140856955U, // PMULHRSWrm128
+ 406984827U, // PMULHRSWrm64
+ 205658235U, // PMULHRSWrr128
+ 205658235U, // PMULHRSWrr64
+ 1140855473U, // PMULHUWrm
+ 205656753U, // PMULHUWrr
+ 1140855482U, // PMULHWrm
+ 205656762U, // PMULHWrr
+ 1140856965U, // PMULLDrm
+ 1140856965U, // PMULLDrm_int
+ 205658245U, // PMULLDrr
+ 205658245U, // PMULLDrr_int
+ 1140855490U, // PMULLWrm
+ 205656770U, // PMULLWrr
+ 1140855498U, // PMULUDQrm
+ 205656778U, // PMULUDQrr
+ 79698061U, // POP16r
+ 872421517U, // POP16rmm
+ 79698061U, // POP16rmr
+ 79698067U, // POP32r
+ 952113299U, // POP32rmm
+ 79698067U, // POP32rmr
+ 79698073U, // POP64r
+ 1476401305U, // POP64rmm
+ 79698073U, // POP64rmr
+ 1207965855U, // POPCNT16rm
+ 1279400095U, // POPCNT16rr
+ 1342183592U, // POPCNT32rm
+ 1279400104U, // POPCNT32rr
+ 1409292465U, // POPCNT64rm
+ 1279400113U, // POPCNT64rr
+ 6330U, // POPF
+ 6336U, // POPFD
+ 6342U, // POPFQ
+ 6348U, // POPFS16
+ 6357U, // POPFS32
+ 6366U, // POPFS64
+ 6375U, // POPGS16
+ 6384U, // POPGS32
+ 6393U, // POPGS64
+ 1140855507U, // PORrm
+ 205656787U, // PORrr
+ 1610619138U, // PREFETCHNTA
+ 1610619151U, // PREFETCHT0
+ 1610619163U, // PREFETCHT1
+ 1610619175U, // PREFETCHT2
+ 1140855512U, // PSADBWrm
+ 205656792U, // PSADBWrr
+ 1140857139U, // PSHUFBrm128
+ 406985011U, // PSHUFBrm64
+ 205658419U, // PSHUFBrr128
+ 205658419U, // PSHUFBrr64
+ 2199918907U, // PSHUFDmi
+ 230037819U, // PSHUFDri
+ 2199918915U, // PSHUFHWmi
+ 230037827U, // PSHUFHWri
+ 2199918924U, // PSHUFLWmi
+ 230037836U, // PSHUFLWri
+ 1140857173U, // PSIGNBrm128
+ 406985045U, // PSIGNBrm64
+ 205658453U, // PSIGNBrr128
+ 205658453U, // PSIGNBrr64
+ 1140857181U, // PSIGNDrm128
+ 406985053U, // PSIGNDrm64
+ 205658461U, // PSIGNDrr128
+ 205658461U, // PSIGNDrr64
+ 1140857189U, // PSIGNWrm128
+ 406985061U, // PSIGNWrm64
+ 205658469U, // PSIGNWrr128
+ 205658469U, // PSIGNWrr64
+ 205658477U, // PSLLDQri
+ 205656808U, // PSLLDri
+ 1140855528U, // PSLLDrm
+ 205656808U, // PSLLDrr
+ 205656815U, // PSLLQri
+ 1140855535U, // PSLLQrm
+ 205656815U, // PSLLQrr
+ 205656822U, // PSLLWri
+ 1140855542U, // PSLLWrm
+ 205656822U, // PSLLWrr
+ 205656829U, // PSRADri
+ 1140855549U, // PSRADrm
+ 205656829U, // PSRADrr
+ 205656836U, // PSRAWri
+ 1140855556U, // PSRAWrm
+ 205656836U, // PSRAWrr
+ 205658485U, // PSRLDQri
+ 205656843U, // PSRLDri
+ 1140855563U, // PSRLDrm
+ 205656843U, // PSRLDrr
+ 205656850U, // PSRLQri
+ 1140855570U, // PSRLQrm
+ 205656850U, // PSRLQrr
+ 205656857U, // PSRLWri
+ 1140855577U, // PSRLWrm
+ 205656857U, // PSRLWrr
+ 1140855584U, // PSUBBrm
+ 205656864U, // PSUBBrr
+ 1140855591U, // PSUBDrm
+ 205656871U, // PSUBDrr
+ 1140855598U, // PSUBQrm
+ 205656878U, // PSUBQrr
+ 1140855605U, // PSUBSBrm
+ 205656885U, // PSUBSBrr
+ 1140855613U, // PSUBSWrm
+ 205656893U, // PSUBSWrr
+ 1140855621U, // PSUBUSBrm
+ 205656901U, // PSUBUSBrr
+ 1140855630U, // PSUBUSWrm
+ 205656910U, // PSUBUSWrr
+ 1140855639U, // PSUBWrm
+ 205656919U, // PSUBWrr
+ 2281707901U, // PTESTrm
+ 1279400317U, // PTESTrr
+ 1140855646U, // PUNPCKHBWrm
+ 205656926U, // PUNPCKHBWrr
+ 1140855657U, // PUNPCKHDQrm
+ 205656937U, // PUNPCKHDQrr
+ 1140857221U, // PUNPCKHQDQrm
+ 205658501U, // PUNPCKHQDQrr
+ 1140855668U, // PUNPCKHWDrm
+ 205656948U, // PUNPCKHWDrr
+ 1140855679U, // PUNPCKLBWrm
+ 205656959U, // PUNPCKLBWrr
+ 1140855690U, // PUNPCKLDQrm
+ 205656970U, // PUNPCKLDQrr
+ 1140857233U, // PUNPCKLQDQrm
+ 205658513U, // PUNPCKLQDQrr
+ 1140855701U, // PUNPCKLWDrm
+ 205656981U, // PUNPCKLWDrr
+ 79698333U, // PUSH16r
+ 872421789U, // PUSH16rmm
+ 79698333U, // PUSH16rmr
+ 79698340U, // PUSH32i16
+ 79698340U, // PUSH32i32
+ 79698340U, // PUSH32i8
+ 79698340U, // PUSH32r
+ 952113572U, // PUSH32rmm
+ 79698340U, // PUSH32rmr
+ 79698347U, // PUSH64i16
+ 79698347U, // PUSH64i32
+ 79698347U, // PUSH64i8
+ 79698347U, // PUSH64r
+ 1476401579U, // PUSH64rmm
+ 79698347U, // PUSH64rmr
+ 6578U, // PUSHF
+ 6585U, // PUSHFD
+ 6592U, // PUSHFQ64
+ 6599U, // PUSHFS16
+ 6609U, // PUSHFS32
+ 6619U, // PUSHFS64
+ 6629U, // PUSHGS16
+ 6639U, // PUSHGS32
+ 6649U, // PUSHGS64
+ 1140855712U, // PXORrm
+ 205656992U, // PXORrr
+ 872421891U, // RCL16m1
+ 872421900U, // RCL16mCL
+ 136321559U, // RCL16mi
+ 79698435U, // RCL16r1
+ 79698444U, // RCL16rCL
+ 205658647U, // RCL16ri
+ 952113693U, // RCL32m1
+ 952113702U, // RCL32mCL
+ 136583729U, // RCL32mi
+ 79698461U, // RCL32r1
+ 79698470U, // RCL32rCL
+ 205658673U, // RCL32ri
+ 1476401719U, // RCL64m1
+ 1476401728U, // RCL64mCL
+ 136714827U, // RCL64mi
+ 79698487U, // RCL64r1
+ 79698496U, // RCL64rCL
+ 205658699U, // RCL64ri
+ 1610619473U, // RCL8m1
+ 1610619482U, // RCL8mCL
+ 136845925U, // RCL8mi
+ 79698513U, // RCL8r1
+ 79698522U, // RCL8rCL
+ 205658725U, // RCL8ri
+ 1946163819U, // RCPPSm
+ 1946163819U, // RCPPSm_Int
+ 1279400555U, // RCPPSr
+ 1279400555U, // RCPPSr_Int
+ 2080381554U, // RCPSSm
+ 2080381554U, // RCPSSm_Int
+ 1279400562U, // RCPSSr
+ 1279400562U, // RCPSSr_Int
+ 872422009U, // RCR16m1
+ 872422018U, // RCR16mCL
+ 136321677U, // RCR16mi
+ 79698553U, // RCR16r1
+ 79698562U, // RCR16rCL
+ 205658765U, // RCR16ri
+ 952113811U, // RCR32m1
+ 952113820U, // RCR32mCL
+ 136583847U, // RCR32mi
+ 79698579U, // RCR32r1
+ 79698588U, // RCR32rCL
+ 205658791U, // RCR32ri
+ 1476401837U, // RCR64m1
+ 1476401846U, // RCR64mCL
+ 136714945U, // RCR64mi
+ 79698605U, // RCR64r1
+ 79698614U, // RCR64rCL
+ 205658817U, // RCR64ri
+ 1610619591U, // RCR8m1
+ 1610619600U, // RCR8mCL
+ 136846043U, // RCR8mi
+ 79698631U, // RCR8r1
+ 79698640U, // RCR8rCL
+ 205658843U, // RCR8ri
+ 6881U, // RDMSR
+ 6887U, // RDPMC
+ 6893U, // RDTSC
+ 6899U, // RDTSCP
+ 6906U, // REPNE_PREFIX
+ 6912U, // REP_MOVSB
+ 6922U, // REP_MOVSD
+ 6932U, // REP_MOVSQ
+ 6942U, // REP_MOVSW
+ 6952U, // REP_PREFIX
+ 6956U, // REP_STOSB
+ 6966U, // REP_STOSD
+ 6976U, // REP_STOSQ
+ 6986U, // REP_STOSW
+ 6996U, // RET
+ 79698776U, // RETI
+ 872422237U, // ROL16m1
+ 872422243U, // ROL16mCL
+ 136321885U, // ROL16mi
+ 79698781U, // ROL16r1
+ 79698787U, // ROL16rCL
+ 205658973U, // ROL16ri
+ 952114030U, // ROL32m1
+ 952114036U, // ROL32mCL
+ 136584046U, // ROL32mi
+ 79698798U, // ROL32r1
+ 79698804U, // ROL32rCL
+ 205658990U, // ROL32ri
+ 1476402047U, // ROL64m1
+ 1476402053U, // ROL64mCL
+ 136715135U, // ROL64mi
+ 79698815U, // ROL64r1
+ 79698821U, // ROL64rCL
+ 205659007U, // ROL64ri
+ 1610619792U, // ROL8m1
+ 1610619798U, // ROL8mCL
+ 136846224U, // ROL8mi
+ 79698832U, // ROL8r1
+ 79698838U, // ROL8rCL
+ 205659024U, // ROL8ri
+ 872422305U, // ROR16m1
+ 872422311U, // ROR16mCL
+ 136321953U, // ROR16mi
+ 79698849U, // ROR16r1
+ 79698855U, // ROR16rCL
+ 205659041U, // ROR16ri
+ 952114098U, // ROR32m1
+ 952114104U, // ROR32mCL
+ 136584114U, // ROR32mi
+ 79698866U, // ROR32r1
+ 79698872U, // ROR32rCL
+ 205659058U, // ROR32ri
+ 1476402115U, // ROR64m1
+ 1476402121U, // ROR64mCL
+ 136715203U, // ROR64mi
+ 79698883U, // ROR64r1
+ 79698889U, // ROR64rCL
+ 205659075U, // ROR64ri
+ 1610619860U, // ROR8m1
+ 1610619866U, // ROR8mCL
+ 136846292U, // ROR8mi
+ 79698900U, // ROR8r1
+ 79698906U, // ROR8rCL
+ 205659092U, // ROR8ri
+ 2202016741U, // ROUNDPDm_Int
+ 230038501U, // ROUNDPDr_Int
+ 2202016750U, // ROUNDPSm_Int
+ 230038510U, // ROUNDPSr_Int
+ 1063263223U, // ROUNDSDm_Int
+ 1073748983U, // ROUNDSDr_Int
+ 1044388864U, // ROUNDSSm_Int
+ 1073748992U, // ROUNDSSr_Int
+ 7177U, // RSM
+ 1946164237U, // RSQRTPSm
+ 1946164237U, // RSQRTPSm_Int
+ 1279400973U, // RSQRTPSr
+ 1279400973U, // RSQRTPSr_Int
+ 2080381974U, // RSQRTSSm
+ 2080381974U, // RSQRTSSm_Int
+ 1279400982U, // RSQRTSSr
+ 1279400982U, // RSQRTSSr_Int
+ 7199U, // SAHF
+ 872422436U, // SAR16m1
+ 872422442U, // SAR16mCL
+ 136322084U, // SAR16mi
+ 79698980U, // SAR16r1
+ 79698986U, // SAR16rCL
+ 205659172U, // SAR16ri
+ 952114229U, // SAR32m1
+ 952114235U, // SAR32mCL
+ 136584245U, // SAR32mi
+ 79698997U, // SAR32r1
+ 79699003U, // SAR32rCL
+ 205659189U, // SAR32ri
+ 1476402246U, // SAR64m1
+ 1476402252U, // SAR64mCL
+ 136715334U, // SAR64mi
+ 79699014U, // SAR64r1
+ 79699020U, // SAR64rCL
+ 205659206U, // SAR64ri
+ 1610619991U, // SAR8m1
+ 1610619997U, // SAR8mCL
+ 136846423U, // SAR8mi
+ 79699031U, // SAR8r1
+ 79699037U, // SAR8rCL
+ 205659223U, // SAR8ri
+ 67116136U, // SBB16i16
+ 136322152U, // SBB16mi
+ 136322152U, // SBB16mi8
+ 136322152U, // SBB16mr
+ 205659240U, // SBB16ri
+ 205659240U, // SBB16ri8
+ 272768104U, // SBB16rm
+ 205659240U, // SBB16rr
+ 205659240U, // SBB16rr_REV
+ 73407598U, // SBB32i32
+ 136584302U, // SBB32mi
+ 136584302U, // SBB32mi8
+ 136584302U, // SBB32mr
+ 205659246U, // SBB32ri
+ 205659246U, // SBB32ri8
+ 339876974U, // SBB32rm
+ 205659246U, // SBB32rr
+ 205659246U, // SBB32rr_REV
+ 75504756U, // SBB64i32
+ 136715380U, // SBB64mi32
+ 136715380U, // SBB64mi8
+ 136715380U, // SBB64mr
+ 205659252U, // SBB64ri32
+ 205659252U, // SBB64ri8
+ 406985844U, // SBB64rm
+ 205659252U, // SBB64rr
+ 205659252U, // SBB64rr_REV
+ 77601914U, // SBB8i8
+ 136846458U, // SBB8mi
+ 136846458U, // SBB8mr
+ 205659258U, // SBB8ri
+ 474094714U, // SBB8rm
+ 205659258U, // SBB8rr
+ 205659258U, // SBB8rr_REV
+ 7296U, // SCAS16
+ 7302U, // SCAS32
+ 7308U, // SCAS64
+ 7314U, // SCAS8
+ 1610620056U, // SETAEm
+ 79699096U, // SETAEr
+ 1610620063U, // SETAm
+ 79699103U, // SETAr
+ 1610620069U, // SETBEm
+ 79699109U, // SETBEr
+ 0U, // SETB_C16r
+ 0U, // SETB_C32r
+ 0U, // SETB_C64r
+ 0U, // SETB_C8r
+ 1610620076U, // SETBm
+ 79699116U, // SETBr
+ 1610620082U, // SETEm
+ 79699122U, // SETEr
+ 1610620088U, // SETGEm
+ 79699128U, // SETGEr
+ 1610620095U, // SETGm
+ 79699135U, // SETGr
+ 1610620101U, // SETLEm
+ 79699141U, // SETLEr
+ 1610620108U, // SETLm
+ 79699148U, // SETLr
+ 1610620114U, // SETNEm
+ 79699154U, // SETNEr
+ 1610620121U, // SETNOm
+ 79699161U, // SETNOr
+ 1610620128U, // SETNPm
+ 79699168U, // SETNPr
+ 1610620135U, // SETNSm
+ 79699175U, // SETNSr
+ 1610620142U, // SETOm
+ 79699182U, // SETOr
+ 1610620148U, // SETPm
+ 79699188U, // SETPr
+ 1610620154U, // SETSm
+ 79699194U, // SETSr
+ 7424U, // SFENCE
+ 2214599943U, // SGDTm
+ 872422669U, // SHL16m1
+ 872422675U, // SHL16mCL
+ 136322317U, // SHL16mi
+ 79699213U, // SHL16r1
+ 79699219U, // SHL16rCL
+ 205659405U, // SHL16ri
+ 952114462U, // SHL32m1
+ 952114468U, // SHL32mCL
+ 136584478U, // SHL32mi
+ 79699230U, // SHL32r1
+ 79699236U, // SHL32rCL
+ 205659422U, // SHL32ri
+ 1476402479U, // SHL64m1
+ 1476402485U, // SHL64mCL
+ 136715567U, // SHL64mi
+ 79699247U, // SHL64r1
+ 79699253U, // SHL64rCL
+ 205659439U, // SHL64ri
+ 1610620224U, // SHL8m1
+ 1610620230U, // SHL8mCL
+ 136846656U, // SHL8mi
+ 79699264U, // SHL8r1
+ 79699270U, // SHL8rCL
+ 205659456U, // SHL8ri
+ 136322385U, // SHLD16mrCL
+ 2176851293U, // SHLD16mri8
+ 205659473U, // SHLD16rrCL
+ 1073749341U, // SHLD16rri8
+ 136584548U, // SHLD32mrCL
+ 2177113456U, // SHLD32mri8
+ 205659492U, // SHLD32rrCL
+ 1073749360U, // SHLD32rri8
+ 136715639U, // SHLD64mrCL
+ 2177244547U, // SHLD64mri8
+ 205659511U, // SHLD64rrCL
+ 1073749379U, // SHLD64rri8
+ 872422794U, // SHR16m1
+ 872422800U, // SHR16mCL
+ 136322442U, // SHR16mi
+ 79699338U, // SHR16r1
+ 79699344U, // SHR16rCL
+ 205659530U, // SHR16ri
+ 952114587U, // SHR32m1
+ 952114593U, // SHR32mCL
+ 136584603U, // SHR32mi
+ 79699355U, // SHR32r1
+ 79699361U, // SHR32rCL
+ 205659547U, // SHR32ri
+ 1476402604U, // SHR64m1
+ 1476402610U, // SHR64mCL
+ 136715692U, // SHR64mi
+ 79699372U, // SHR64r1
+ 79699378U, // SHR64rCL
+ 205659564U, // SHR64ri
+ 1610620349U, // SHR8m1
+ 1610620355U, // SHR8mCL
+ 136846781U, // SHR8mi
+ 79699389U, // SHR8r1
+ 79699395U, // SHR8rCL
+ 205659581U, // SHR8ri
+ 136322510U, // SHRD16mrCL
+ 2176851418U, // SHRD16mri8
+ 205659598U, // SHRD16rrCL
+ 1073749466U, // SHRD16rri8
+ 136584673U, // SHRD32mrCL
+ 2177113581U, // SHRD32mri8
+ 205659617U, // SHRD32rrCL
+ 1073749485U, // SHRD32rri8
+ 136715764U, // SHRD64mrCL
+ 2177244672U, // SHRD64mri8
+ 205659636U, // SHRD64rrCL
+ 1073749504U, // SHRD64rri8
+ 1065360903U, // SHUFPDrmi
+ 1073749511U, // SHUFPDrri
+ 1065360911U, // SHUFPSrmi
+ 1073749519U, // SHUFPSrri
+ 2214600215U, // SIDTm
+ 7709U, // SIN_F
0U, // SIN_Fp32
0U, // SIN_Fp64
0U, // SIN_Fp80
- 872422904U, // SLDT16m
- 73407992U, // SLDT16r
- 872422911U, // SLDT64m
- 73407999U, // SLDT64r
- 872422918U, // SMSW16m
- 73408006U, // SMSW16r
- 73408013U, // SMSW32r
- 73408020U, // SMSW64r
- 1946164763U, // SQRTPDm
- 1946164763U, // SQRTPDm_Int
- 1277206043U, // SQRTPDr
- 1277206043U, // SQRTPDr_Int
- 1946164771U, // SQRTPSm
- 1946164771U, // SQRTPSm_Int
- 1277206051U, // SQRTPSr
- 1277206051U, // SQRTPSr_Int
- 2013273643U, // SQRTSDm
- 2013273643U, // SQRTSDm_Int
- 1277206059U, // SQRTSDr
- 1277206059U, // SQRTSDr_Int
- 2080382515U, // SQRTSSm
- 2080382515U, // SQRTSSm_Int
- 1277206067U, // SQRTSSr
- 1277206067U, // SQRTSSr_Int
- 7739U, // SQRT_F
+ 872422946U, // SLDT16m
+ 79699490U, // SLDT16r
+ 872422953U, // SLDT64m
+ 79699497U, // SLDT64r
+ 872422960U, // SMSW16m
+ 79699504U, // SMSW16r
+ 79699511U, // SMSW32r
+ 79699518U, // SMSW64r
+ 1946164805U, // SQRTPDm
+ 1946164805U, // SQRTPDm_Int
+ 1279401541U, // SQRTPDr
+ 1279401541U, // SQRTPDr_Int
+ 1946164813U, // SQRTPSm
+ 1946164813U, // SQRTPSm_Int
+ 1279401549U, // SQRTPSr
+ 1279401549U, // SQRTPSr_Int
+ 2013273685U, // SQRTSDm
+ 2013273685U, // SQRTSDm_Int
+ 1279401557U, // SQRTSDr
+ 1279401557U, // SQRTSDr_Int
+ 2080382557U, // SQRTSSm
+ 2080382557U, // SQRTSSm_Int
+ 1279401565U, // SQRTSSr
+ 1279401565U, // SQRTSSr_Int
+ 7781U, // SQRT_F
0U, // SQRT_Fp32
0U, // SQRT_Fp64
0U, // SQRT_Fp80
- 7745U, // STC
- 7749U, // STD
- 7753U, // STI
- 945823309U, // STMXCSR
- 872422998U, // STRm
- 73408086U, // STRr
- 738205276U, // ST_F32m
- 805314146U, // ST_F64m
- 738205288U, // ST_FP32m
- 805314159U, // ST_FP64m
- 2415926902U, // ST_FP80m
- 73408125U, // ST_FPrr
+ 7787U, // SS_PREFIX
+ 7790U, // STC
+ 7794U, // STD
+ 7798U, // STI
+ 952114810U, // STMXCSR
+ 7811U, // STOSB
+ 7817U, // STOSD
+ 7823U, // STOSW
+ 872423061U, // STRm
+ 79699605U, // STRr
+ 738205339U, // ST_F32m
+ 805314209U, // ST_F64m
+ 738205351U, // ST_FP32m
+ 805314222U, // ST_FP64m
+ 2415926965U, // ST_FP80m
+ 79699644U, // ST_FPrr
0U, // ST_Fp32m
0U, // ST_Fp64m
0U, // ST_Fp64m32
@@ -2289,51 +2304,51 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // ST_FpP80m
0U, // ST_FpP80m32
0U, // ST_FpP80m64
- 73408131U, // ST_Frr
- 67116680U, // SUB16i16
- 135274120U, // SUB16mi
- 135274120U, // SUB16mi8
- 135274120U, // SUB16mr
- 203464328U, // SUB16ri
- 203464328U, // SUB16ri8
- 270573192U, // SUB16rm
- 203464328U, // SUB16rr
- 203464328U, // SUB16rr_REV
- 70262414U, // SUB32i32
- 135339662U, // SUB32mi
- 135339662U, // SUB32mi8
- 135339662U, // SUB32mr
- 203464334U, // SUB32ri
- 203464334U, // SUB32ri8
- 337682062U, // SUB32rm
- 203464334U, // SUB32rr
- 203464334U, // SUB32rr_REV
- 71310996U, // SUB64i32
- 135372436U, // SUB64mi32
- 135372436U, // SUB64mi8
- 135372436U, // SUB64mr
- 203464340U, // SUB64ri32
- 203464340U, // SUB64ri8
- 404790932U, // SUB64rm
- 203464340U, // SUB64rr
- 203464340U, // SUB64rr_REV
- 72359578U, // SUB8i8
- 135405210U, // SUB8mi
- 135405210U, // SUB8mr
- 203464346U, // SUB8ri
- 471899802U, // SUB8rm
- 203464346U, // SUB8rr
- 203464346U, // SUB8rr_REV
- 536878752U, // SUBPDrm
- 203464352U, // SUBPDrr
- 536878759U, // SUBPSrm
- 203464359U, // SUBPSrr
- 738205358U, // SUBR_F32m
- 805314230U, // SUBR_F64m
- 872423102U, // SUBR_FI16m
- 945823431U, // SUBR_FI32m
- 73408208U, // SUBR_FPrST0
- 73408215U, // SUBR_FST0r
+ 79699650U, // ST_Frr
+ 67116743U, // SUB16i16
+ 136322759U, // SUB16mi
+ 136322759U, // SUB16mi8
+ 136322759U, // SUB16mr
+ 205659847U, // SUB16ri
+ 205659847U, // SUB16ri8
+ 272768711U, // SUB16rm
+ 205659847U, // SUB16rr
+ 205659847U, // SUB16rr_REV
+ 73408205U, // SUB32i32
+ 136584909U, // SUB32mi
+ 136584909U, // SUB32mi8
+ 136584909U, // SUB32mr
+ 205659853U, // SUB32ri
+ 205659853U, // SUB32ri8
+ 339877581U, // SUB32rm
+ 205659853U, // SUB32rr
+ 205659853U, // SUB32rr_REV
+ 75505363U, // SUB64i32
+ 136715987U, // SUB64mi32
+ 136715987U, // SUB64mi8
+ 136715987U, // SUB64mr
+ 205659859U, // SUB64ri32
+ 205659859U, // SUB64ri8
+ 406986451U, // SUB64rm
+ 205659859U, // SUB64rr
+ 205659859U, // SUB64rr_REV
+ 77602521U, // SUB8i8
+ 136847065U, // SUB8mi
+ 136847065U, // SUB8mr
+ 205659865U, // SUB8ri
+ 474095321U, // SUB8rm
+ 205659865U, // SUB8rr
+ 205659865U, // SUB8rr_REV
+ 536878815U, // SUBPDrm
+ 205659871U, // SUBPDrr
+ 536878822U, // SUBPSrm
+ 205659878U, // SUBPSrr
+ 738205421U, // SUBR_F32m
+ 805314293U, // SUBR_F64m
+ 872423165U, // SUBR_FI16m
+ 952114950U, // SUBR_FI32m
+ 79699727U, // SUBR_FPrST0
+ 79699734U, // SUBR_FST0r
0U, // SUBR_Fp32m
0U, // SUBR_Fp64m
0U, // SUBR_Fp64m32
@@ -2345,21 +2360,21 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // SUBR_FpI32m32
0U, // SUBR_FpI32m64
0U, // SUBR_FpI32m80
- 73408222U, // SUBR_FrST0
- 603987692U, // SUBSDrm
- 603987692U, // SUBSDrm_Int
- 203464428U, // SUBSDrr
- 203464428U, // SUBSDrr_Int
- 671096563U, // SUBSSrm
- 671096563U, // SUBSSrm_Int
- 203464435U, // SUBSSrr
- 203464435U, // SUBSSrr_Int
- 738205434U, // SUB_F32m
- 805314305U, // SUB_F64m
- 872423176U, // SUB_FI16m
- 945823504U, // SUB_FI32m
- 73408280U, // SUB_FPrST0
- 73408288U, // SUB_FST0r
+ 79699741U, // SUBR_FrST0
+ 603987755U, // SUBSDrm
+ 603987755U, // SUBSDrm_Int
+ 205659947U, // SUBSDrr
+ 205659947U, // SUBSDrr_Int
+ 671096626U, // SUBSSrm
+ 671096626U, // SUBSSrm_Int
+ 205659954U, // SUBSSrr
+ 205659954U, // SUBSSrr_Int
+ 738205497U, // SUB_F32m
+ 805314368U, // SUB_F64m
+ 872423239U, // SUB_FI16m
+ 952115023U, // SUB_FI32m
+ 79699799U, // SUB_FPrST0
+ 79699807U, // SUB_FST0r
0U, // SUB_Fp32
0U, // SUB_Fp32m
0U, // SUB_Fp64
@@ -2374,164 +2389,164 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // SUB_FpI32m32
0U, // SUB_FpI32m64
0U, // SUB_FpI32m80
- 73408294U, // SUB_FrST0
- 7989U, // SWPGS
- 7995U, // SYSCALL
- 8003U, // SYSENTER
- 8012U, // SYSEXIT
- 8012U, // SYSEXIT64
- 8020U, // SYSRET
- 1578110610U, // TAILJMPd
- 974135131U, // TAILJMPm
- 101715607U, // TAILJMPr
- 101715614U, // TAILJMPr64
- 102768481U, // TCRETURNdi
- 102768481U, // TCRETURNdi64
- 102768481U, // TCRETURNri
- 102768481U, // TCRETURNri64
- 67116909U, // TEST16i16
- 135274349U, // TEST16mi
- 1277206381U, // TEST16ri
- 1207967597U, // TEST16rm
- 1277206381U, // TEST16rr
- 70262644U, // TEST32i32
- 135339892U, // TEST32mi
- 1277206388U, // TEST32ri
- 1342185332U, // TEST32rm
- 1277206388U, // TEST32rr
- 71311227U, // TEST64i32
- 135372667U, // TEST64mi32
- 1277206395U, // TEST64ri32
- 1409294203U, // TEST64rm
- 1277206395U, // TEST64rr
- 72359810U, // TEST8i8
- 135405442U, // TEST8mi
- 1277206402U, // TEST8ri
- 1684021122U, // TEST8rm
- 1277206402U, // TEST8rr
- 2751467382U, // TLS_addr32
- 2818580361U, // TLS_addr64
- 8091U, // TRAP
- 8095U, // TST_F
+ 79699813U, // SUB_FrST0
+ 8052U, // SWAPGS
+ 8059U, // SYSCALL
+ 8067U, // SYSENTER
+ 8076U, // SYSEXIT
+ 8076U, // SYSEXIT64
+ 8084U, // SYSRET
+ 1604325038U, // TAILJMPd
+ 1000349595U, // TAILJMPm
+ 127930010U, // TAILJMPr
+ 127930017U, // TAILJMPr64
+ 130031521U, // TCRETURNdi
+ 130031521U, // TCRETURNdi64
+ 130031521U, // TCRETURNri
+ 130031521U, // TCRETURNri64
+ 67116973U, // TEST16i16
+ 136322989U, // TEST16mi
+ 1279401901U, // TEST16ri
+ 1207967661U, // TEST16rm
+ 1279401901U, // TEST16rr
+ 73408436U, // TEST32i32
+ 136585140U, // TEST32mi
+ 1279401908U, // TEST32ri
+ 1342185396U, // TEST32rm
+ 1279401908U, // TEST32rr
+ 75505595U, // TEST64i32
+ 136716219U, // TEST64mi32
+ 1279401915U, // TEST64ri32
+ 1409294267U, // TEST64rm
+ 1279401915U, // TEST64rr
+ 77602754U, // TEST8i8
+ 136847298U, // TEST8mi
+ 1279401922U, // TEST8ri
+ 1690312642U, // TEST8rm
+ 1279401922U, // TEST8rr
+ 2684358526U, // TLS_addr32
+ 2751471561U, // TLS_addr64
+ 8155U, // TRAP
+ 8159U, // TST_F
0U, // TST_Fp32
0U, // TST_Fp64
0U, // TST_Fp80
- 2013269586U, // UCOMISDrm
- 1277202002U, // UCOMISDrr
- 2080378459U, // UCOMISSrm
- 1277202011U, // UCOMISSrr
- 75505572U, // UCOM_FIPr
- 75505581U, // UCOM_FIr
- 8117U, // UCOM_FPPr
- 73408445U, // UCOM_FPr
+ 2013269594U, // UCOMISDrm
+ 1279397466U, // UCOMISDrr
+ 2080378467U, // UCOMISSrm
+ 1279397475U, // UCOMISSrr
+ 83894244U, // UCOM_FIPr
+ 83894253U, // UCOM_FIr
+ 8181U, // UCOM_FPPr
+ 79699965U, // UCOM_FPr
0U, // UCOM_FpIr32
0U, // UCOM_FpIr64
0U, // UCOM_FpIr80
0U, // UCOM_Fpr32
0U, // UCOM_Fpr64
0U, // UCOM_Fpr80
- 73408453U, // UCOM_Fr
- 536879052U, // UNPCKHPDrm
- 203464652U, // UNPCKHPDrr
- 536879062U, // UNPCKHPSrm
- 203464662U, // UNPCKHPSrr
- 536879072U, // UNPCKLPDrm
- 203464672U, // UNPCKLPDrr
- 536879082U, // UNPCKLPSrm
- 203464682U, // UNPCKLPSrr
- 68460532U, // VASTART_SAVE_XMM_REGS
- 872423436U, // VERRm
- 73408524U, // VERRr
- 872423442U, // VERWm
- 73408530U, // VERWr
- 8216U, // VMCALL
- 1476403231U, // VMCLEARm
- 8232U, // VMLAUNCH
- 1476403249U, // VMPTRLDm
- 1476403258U, // VMPTRSTm
- 135340099U, // VMREAD32rm
- 1277206595U, // VMREAD32rr
- 135372876U, // VMREAD64rm
- 1277206604U, // VMREAD64rr
- 8277U, // VMRESUME
- 1342185566U, // VMWRITE32rm
- 1277206622U, // VMWRITE32rr
- 1409294440U, // VMWRITE64rm
- 1277206632U, // VMWRITE64rr
- 8306U, // VMXOFF
- 1476403321U, // VMXON
- 68553880U, // V_SET0
- 68555316U, // V_SETALLONES
- 8320U, // WAIT
- 8325U, // WBINVD
- 1476396122U, // WINCALL64m
- 1549796464U, // WINCALL64pcrel32
- 73401434U, // WINCALL64r
- 8332U, // WRMSR
- 135274642U, // XADD16rm
- 1277206674U, // XADD16rr
- 135340185U, // XADD32rm
- 1277206681U, // XADD32rr
- 135372960U, // XADD64rm
- 1277206688U, // XADD64rr
- 135405735U, // XADD8rm
- 1277206695U, // XADD8rr
- 67117230U, // XCHG16ar
- 1296081070U, // XCHG16rm
- 1311776942U, // XCHG16rr
- 70262965U, // XCHG32ar
- 1297129653U, // XCHG32rm
- 1311776949U, // XCHG32rr
- 71311548U, // XCHG64ar
- 1298178236U, // XCHG64rm
- 1311776956U, // XCHG64rr
- 1299226819U, // XCHG8rm
- 1311776963U, // XCHG8rr
- 73408714U, // XCH_F
- 8400U, // XLAT
- 67117270U, // XOR16i16
- 135274710U, // XOR16mi
- 135274710U, // XOR16mi8
- 135274710U, // XOR16mr
- 203464918U, // XOR16ri
- 203464918U, // XOR16ri8
- 270573782U, // XOR16rm
- 203464918U, // XOR16rr
- 203464918U, // XOR16rr_REV
- 70259646U, // XOR32i32
- 135336894U, // XOR32mi
- 135336894U, // XOR32mi8
- 135336894U, // XOR32mr
- 203461566U, // XOR32ri
- 203461566U, // XOR32ri8
- 337679294U, // XOR32rm
- 203461566U, // XOR32rr
- 203461566U, // XOR32rr_REV
- 71311580U, // XOR64i32
- 135373020U, // XOR64mi32
- 135373020U, // XOR64mi8
- 135373020U, // XOR64mr
- 203464924U, // XOR64ri32
- 203464924U, // XOR64ri8
- 404791516U, // XOR64rm
- 203464924U, // XOR64rr
- 203464924U, // XOR64rr_REV
- 72356862U, // XOR8i8
- 135402494U, // XOR8mi
- 135402494U, // XOR8mr
- 203461630U, // XOR8ri
- 471897086U, // XOR8rm
- 203461630U, // XOR8rr
- 203461630U, // XOR8rr_REV
- 536874129U, // XORPDrm
- 203459729U, // XORPDrr
- 536874136U, // XORPSrm
- 203459736U, // XORPSrr
+ 79699973U, // UCOM_Fr
+ 536879116U, // UNPCKHPDrm
+ 205660172U, // UNPCKHPDrr
+ 536879126U, // UNPCKHPSrm
+ 205660182U, // UNPCKHPSrr
+ 536879136U, // UNPCKLPDrm
+ 205660192U, // UNPCKLPDrr
+ 536879146U, // UNPCKLPSrm
+ 205660202U, // UNPCKLPSrr
+ 70459444U, // VASTART_SAVE_XMM_REGS
+ 872423500U, // VERRm
+ 79700044U, // VERRr
+ 872423506U, // VERWm
+ 79700050U, // VERWr
+ 8280U, // VMCALL
+ 1476403295U, // VMCLEARm
+ 8296U, // VMLAUNCH
+ 1476403313U, // VMPTRLDm
+ 1476403322U, // VMPTRSTm
+ 136585347U, // VMREAD32rm
+ 1279402115U, // VMREAD32rr
+ 136716428U, // VMREAD64rm
+ 1279402124U, // VMREAD64rr
+ 8341U, // VMRESUME
+ 1342185630U, // VMWRITE32rm
+ 1279402142U, // VMWRITE32rr
+ 1409294504U, // VMWRITE64rm
+ 1279402152U, // VMWRITE64rr
+ 8370U, // VMXOFF
+ 1476403385U, // VMXON
+ 0U, // V_SET0
+ 0U, // V_SETALLONES
+ 8384U, // WAIT
+ 8389U, // WBINVD
+ 1476396120U, // WINCALL64m
+ 1556087918U, // WINCALL64pcrel32
+ 79692888U, // WINCALL64r
+ 8396U, // WRMSR
+ 136323282U, // XADD16rm
+ 1279402194U, // XADD16rr
+ 136585433U, // XADD32rm
+ 1279402201U, // XADD32rr
+ 136716512U, // XADD64rm
+ 1279402208U, // XADD64rr
+ 136847591U, // XADD8rm
+ 1279402215U, // XADD8rr
+ 67117294U, // XCHG16ar
+ 1317150958U, // XCHG16rm
+ 1340088558U, // XCHG16rr
+ 73408757U, // XCHG32ar
+ 1319248117U, // XCHG32rm
+ 1340088565U, // XCHG32rr
+ 75505916U, // XCHG64ar
+ 1321345276U, // XCHG64rm
+ 1340088572U, // XCHG64rr
+ 1323442435U, // XCHG8rm
+ 1340088579U, // XCHG8rr
+ 79700234U, // XCH_F
+ 8464U, // XLAT
+ 67117334U, // XOR16i16
+ 136323350U, // XOR16mi
+ 136323350U, // XOR16mi8
+ 136323350U, // XOR16mr
+ 205660438U, // XOR16ri
+ 205660438U, // XOR16ri8
+ 272769302U, // XOR16rm
+ 205660438U, // XOR16rr
+ 205660438U, // XOR16rr_REV
+ 73408796U, // XOR32i32
+ 136585500U, // XOR32mi
+ 136585500U, // XOR32mi8
+ 136585500U, // XOR32mr
+ 205660444U, // XOR32ri
+ 205660444U, // XOR32ri8
+ 339878172U, // XOR32rm
+ 205660444U, // XOR32rr
+ 205660444U, // XOR32rr_REV
+ 75505954U, // XOR64i32
+ 136716578U, // XOR64mi32
+ 136716578U, // XOR64mi8
+ 136716578U, // XOR64mr
+ 205660450U, // XOR64ri32
+ 205660450U, // XOR64ri8
+ 406987042U, // XOR64rm
+ 205660450U, // XOR64rr
+ 205660450U, // XOR64rr_REV
+ 77603112U, // XOR8i8
+ 136847656U, // XOR8mi
+ 136847656U, // XOR8mr
+ 205660456U, // XOR8ri
+ 474095912U, // XOR8rm
+ 205660456U, // XOR8rr
+ 205660456U, // XOR8rr_REV
+ 536874124U, // XORPDrm
+ 205655180U, // XORPDrr
+ 536874131U, // XORPSrm
+ 205655187U, // XORPSrr
0U
};
const char *AsmStrs =
- "DEBUG_VALUE\000fabs\000adcw\t\000adcl\t\000adcq\t\000adcb\t\000addw\t\000"
+ "DBG_VALUE\000fabs\000adcw\t\000adcl\t\000adcq\t\000adcb\t\000addw\t\000"
"addl\t\000addq\t\000addb\t\000addpd\t\000addps\t\000addsd\t\000addss\t\000"
"addsubpd\t\000addsubps\t\000fadds\t\000faddl\t\000fiadds\t\000fiaddl\t\000"
"faddp\t\000fadd\t\000fadd\t%st(0), \000#ADJCALLSTACKDOWN\000#ADJCALLSTA"
@@ -2568,158 +2583,142 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
"cmpl\t\000cmpq\t\000cmpb\t\000cmp\000cmpsw\000cmpsl\000cmpsq\000cmpsb\000"
"cmpxchg16b\t\000cmpxchgw\t\000cmpxchgl\t\000cmpxchgq\t\000cmpxchg8b\t\000"
"cmpxchgb\t\000comisd\t\000comiss\t\000fcomp\t\000fcomip\t\000fcomi\t\000"
- "fcom\t\000fcos\000cpuid\000cqto\000crc32 \t\000cvtdq2pd\t\000cvtdq2ps\t"
- "\000cvtpd2dq\t\000cvtpd2ps\t\000cvtps2dq\t\000cvtps2pd\t\000cvtsd2siq\t"
- "\000cvtsd2ss\t\000cvtsi2sdq\t\000cvtsi2sd\t\000cvtsi2ssq\t\000cvtsi2ss\t"
- "\000cvtss2sd\t\000cvtss2siq\t\000cvtss2sil\t\000cvttps2dq\t\000cvttsd2s"
- "iq\t\000cvttsd2si\t\000cvttss2siq\t\000cvttss2si\t\000cwtd\000cwtl\000d"
- "ecw\t\000decl\t\000decq\t\000decb\t\000divw\t\000divl\t\000divq\t\000di"
- "vb\t\000divpd\t\000divps\t\000fdivrs\t\000fdivrl\t\000fidivrs\t\000fidi"
- "vrl\t\000fdivp\t\000fdivr\t\000fdiv\t%st(0), \000divsd\t\000divss\t\000"
- "fdivs\t\000fdivl\t\000fidivs\t\000fidivl\t\000fdivrp\t\000fdiv\t\000fdi"
- "vr\t%st(0), \000dppd\t\000dpps\t\000ret\t#eh_return, addr: \000enter\t\000"
- "extractps\t\000f2xm1\000lcallw\t\000lcallw\t*\000lcalll\t\000lcalll\t*\000"
- "lcallq\t*\000ljmpw\t\000ljmpw\t*\000ljmpl\t\000ljmpl\t*\000ljmpq\t*\000"
- "fbld\t\000fbstp\t\000fcoml\t\000fcomll\t\000fcompl\t\000fcompll\t\000fc"
- "ompp\000fdecstp\000ffree\t\000ficomw\t\000ficoml\t\000ficompw\t\000fico"
- "mpl\t\000fincstp\000fisttpl\t\000fldcw\t\000fldenv\t\000fldl2e\000fldl2"
- "t\000fldlg2\000fldln2\000fldpi\000fnclex\000fninit\000fnop\000fnstcw\t\000"
- "fnstsw %ax\000fnstsw\t\000##FP32_TO_INT16_IN_MEM PSEUDO!\000##FP32_TO_I"
- "NT32_IN_MEM PSEUDO!\000##FP32_TO_INT64_IN_MEM PSEUDO!\000##FP64_TO_INT1"
- "6_IN_MEM PSEUDO!\000##FP64_TO_INT32_IN_MEM PSEUDO!\000##FP64_TO_INT64_I"
- "N_MEM PSEUDO!\000##FP80_TO_INT16_IN_MEM PSEUDO!\000##FP80_TO_INT32_IN_M"
- "EM PSEUDO!\000##FP80_TO_INT64_IN_MEM PSEUDO!\000fpatan\000fprem\000fpre"
- "m1\000fptan\000##FP_REG_KILL\000frndint\000frstor\t\000fnsave\t\000fsca"
- "le\000fsincos\000fnstenv\t\000movl\t%fs:\000fxam\000fxrstor\t\000fxsave"
- "\t\000fxtract\000fyl2x\000fyl2xp1\000pxor\t\000movapd\t\000movaps\t\000"
- "orpd\t\000orps\t\000xorpd\t\000xorps\t\000movl\t%gs:\000haddpd\t\000had"
- "dps\t\000hlt\000hsubpd\t\000hsubps\t\000idivw\t\000idivl\t\000idivq\t\000"
- "idivb\t\000filds\t\000fildl\t\000fildll\t\000imulw\t\000imull\t\000imul"
- "q\t\000imulb\t\000insw\000inw\t\000inw\t%dx, %ax\000insl\000inl\t\000in"
- "l\t%dx, %eax\000insb\000inb\t\000inb\t%dx, %al\000incw\t\000incl\t\000i"
- "ncq\t\000incb\t\000insertps\t\000int\t\000int\t3\000invd\000invept\000i"
- "nvlpg\000invvpid\000iretw\000iretl\000iretq\000fisttps\t\000fisttpll\t\000"
- "fists\t\000fistl\t\000fistps\t\000fistpl\t\000fistpll\t\000cvtpd2pi\t\000"
- "cvtpi2pd\t\000cvtpi2ps\t\000cvtps2pi\t\000cvtsd2si\t\000cvtss2si\t\000c"
- "vttpd2dq\t\000cvttpd2pi\t\000cvttps2pi\t\000ucomisd\t\000ucomiss\t\000j"
- "a\t\000jae\t\000jb\t\000jbe\t\000jcxz\t\000je\t\000jg\t\000jge\t\000jl\t"
- "\000jle\t\000jmp\t\000jmpl\t*\000jmpq\t*\000jmpq\t\000jne\t\000jno\t\000"
- "jnp\t\000jns\t\000jo\t\000jp\t\000js\t\000lahf\000larw\t\000larl\t\000l"
- "arq\t\000lock\n\tcmpxchgw\t\000lock\n\tcmpxchgl\t\000lock\n\tcmpxchgq\t"
- "\000lock\n\tcmpxchgb\t\000lock\n\tcmpxchg8b\t\000lddqu\t\000ldmxcsr\t\000"
- "ldsw\t\000ldsl\t\000fldz\000fld1\000flds\t\000fldl\t\000fldt\t\000fld\t"
- "\000leaw\t\000leal\t\000leaq\t\000leave\000lesw\t\000lesl\t\000lfence\000"
- "lfsw\t\000lfsl\t\000lfsq\t\000lgdt\t\000lgsw\t\000lgsl\t\000lgsq\t\000l"
- "idt\t\000lldtw\t\000lmsww\t\000lock\n\taddw\t\000lock\n\taddl\t\000lock"
- "\n\taddq\t\000lock\n\taddb\t\000lock\n\tdecw\t\000lock\n\tdecl\t\000loc"
- "k\n\tdecq\t\000lock\n\tdecb\t\000lock\n\tincw\t\000lock\n\tincl\t\000lo"
- "ck\n\tincq\t\000lock\n\tincb\t\000lock\n\tsubw\t\000lock\n\tsubl\t\000l"
- "ock\n\tsubq\t\000lock\n\tsubb\t\000lodsb\000lodsl\000lodsq\000lodsw\000"
- "loop\t\000loope\t\000loopne\t\000lret\000lret\t\000lslw\t\000lsll\t\000"
- "lslq\t\000lssw\t\000lssl\t\000lssq\t\000ltrw\t\000lock\n\txaddw\t\000lo"
- "ck\n\txaddl\t\000lock\n\txadd\t\000lock\n\txaddb\t\000maskmovdqu\t\000m"
- "axpd\t\000maxps\t\000maxsd\t\000maxss\t\000mfence\000minpd\t\000minps\t"
- "\000minsd\t\000minss\t\000emms\000femms\000maskmovq\t\000movd\t\000movd"
- "q2q\t\000movntq\t\000movq2dq\t\000movq\t\000packssdw\t\000packsswb\t\000"
- "packuswb\t\000paddb\t\000paddd\t\000paddq\t\000paddsb\t\000paddsw\t\000"
- "paddusb\t\000paddusw\t\000paddw\t\000pandn\t\000pand\t\000pavgb\t\000pa"
- "vgw\t\000pcmpeqb\t\000pcmpeqd\t\000pcmpeqw\t\000pcmpgtb\t\000pcmpgtd\t\000"
- "pcmpgtw\t\000pextrw\t\000pinsrw\t\000pmaddwd\t\000pmaxsw\t\000pmaxub\t\000"
- "pminsw\t\000pminub\t\000pmovmskb\t\000pmulhuw\t\000pmulhw\t\000pmullw\t"
- "\000pmuludq\t\000por\t\000psadbw\t\000pshufw\t\000pslld\t\000psllq\t\000"
- "psllw\t\000psrad\t\000psraw\t\000psrld\t\000psrlq\t\000psrlw\t\000psubb"
- "\t\000psubd\t\000psubq\t\000psubsb\t\000psubsw\t\000psubusb\t\000psubus"
- "w\t\000psubw\t\000punpckhbw\t\000punpckhdq\t\000punpckhwd\t\000punpcklb"
- "w\t\000punpckldq\t\000punpcklwd\t\000monitor\000movw\t%ax, \000movw\t\000"
- "movl\t%eax, \000movl\t\000xorl\t\000movq\t%fs:\000movq\t%gs:\000movq\t%"
- "rax, \000movabsq\t\000movb\t%al, \000movb\t\000xorb\t\000movddup\t\000m"
- "ovdqa\t\000movdqu\t\000movhlps\t\000movhpd\t\000movhps\t\000movlhps\t\000"
- "movlpd\t\000movsd\t\000movlps\t\000movss\t\000movmskpd\t\000movmskps\t\000"
- "movntdqa\t\000movntdq\t\000movnti\t\000movntpd\t\000movntps\t\000movshd"
- "up\t\000movsldup\t\000movsbw\t\000movswl\t\000movsbl\t\000movswq\t\000m"
- "ovslq\t\000movsbq\t\000movupd\t\000movups\t\000movzbw\t\000movzbl\t\000"
- "movzwl\t\000movzwq\t\000movzbq\t\000mpsadbw\t\000mulw\t\000mull\t\000mu"
- "lq\t\000mulb\t\000mulpd\t\000mulps\t\000mulsd\t\000mulss\t\000fmuls\t\000"
- "fmull\t\000fimuls\t\000fimull\t\000fmulp\t\000fmul\t\000fmul\t%st(0), \000"
- "mwait\000negw\t\000negl\t\000negq\t\000negb\t\000nop\000nopl\t\000nopw\t"
- "\000notw\t\000notl\t\000notq\t\000notb\t\000orw\t\000orl\t\000orq\t\000"
- "orb\t\000outw\t%ax, \000outw\t%ax, %dx\000outl\t%eax, \000outl\t%eax, %"
- "dx\000outb\t%al, \000outb\t%al, %dx\000outsb\000outsl\000outsw\000pabsb"
- "\t\000pabsd\t\000pabsw\t\000packusdw\t\000palignr\t\000pblendvb\t%xmm0,"
- " \000pblendw\t\000pcmpeqq\t\000pcmpestri\t\000#PCMPESTRM128rm PSEUDO!\000"
- "#PCMPESTRM128rr PSEUDO!\000pcmpestrm\t\000pcmpgtq\t\000pcmpistri\t\000#"
- "PCMPISTRM128rm PSEUDO!\000#PCMPISTRM128rr PSEUDO!\000pcmpistrm\t\000pex"
- "trb\t\000pextrd\t\000pextrq\t\000phaddd\t\000phaddsw\t\000phaddw\t\000p"
- "hminposuw\t\000phsubd\t\000phsubsw\t\000phsubw\t\000pinsrb\t\000pinsrd\t"
- "\000pinsrq\t\000pmaddubsw\t\000pmaxsb\t\000pmaxsd\t\000pmaxud\t\000pmax"
- "uw\t\000pminsb\t\000pminsd\t\000pminud\t\000pminuw\t\000pmovsxbd\t\000p"
- "movsxbq\t\000pmovsxbw\t\000pmovsxdq\t\000pmovsxwd\t\000pmovsxwq\t\000pm"
- "ovzxbd\t\000pmovzxbq\t\000pmovzxbw\t\000pmovzxdq\t\000pmovzxwd\t\000pmo"
- "vzxwq\t\000pmuldq\t\000pmulhrsw\t\000pmulld\t\000popw\t\000popl\t\000po"
- "pq\t\000popcntw\t\000popcntl\t\000popcntq\t\000popfw\000popfl\000popfq\000"
- "popw\t%fs\000popl\t%fs\000popq\t%fs\000popw\t%gs\000popl\t%gs\000popq\t"
- "%gs\000prefetchnta\t\000prefetcht0\t\000prefetcht1\t\000prefetcht2\t\000"
- "pshufb\t\000pshufd\t\000pshufhw\t\000pshuflw\t\000psignb\t\000psignd\t\000"
- "psignw\t\000pslldq\t\000psrldq\t\000ptest \t\000punpckhqdq\t\000punpckl"
- "qdq\t\000pushw\t\000pushl\t\000pushq\t\000pushfw\000pushfl\000pushfq\000"
- "pushw\t%fs\000pushl\t%fs\000pushq\t%fs\000pushw\t%gs\000pushl\t%gs\000p"
- "ushq\t%gs\000rclw\t1, \000rclw\t%cl, \000rclw\t\000rcll\t1, \000rcll\t%"
- "cl, \000rcll\t\000rclq\t1, \000rclq\t%cl, \000rclq\t\000rclb\t1, \000rc"
- "lb\t%cl, \000rclb\t\000rcpps\t\000rcpss\t\000rcrw\t1, \000rcrw\t%cl, \000"
- "rcrw\t\000rcrl\t1, \000rcrl\t%cl, \000rcrl\t\000rcrq\t1, \000rcrq\t%cl,"
- " \000rcrq\t\000rcrb\t1, \000rcrb\t%cl, \000rcrb\t\000rdmsr\000rdpmc\000"
- "rdtsc\000rep;movsb\000rep;movsl\000rep;movsq\000rep;movsw\000rep;stosb\000"
- "rep;stosl\000rep;stosq\000rep;stosw\000ret\000ret\t\000rolw\t\000rolw\t"
- "%cl, \000roll\t\000roll\t%cl, \000rolq\t\000rolq\t%cl, \000rolb\t\000ro"
- "lb\t%cl, \000rorw\t\000rorw\t%cl, \000rorl\t\000rorl\t%cl, \000rorq\t\000"
- "rorq\t%cl, \000rorb\t\000rorb\t%cl, \000roundpd\t\000roundps\t\000round"
- "sd\t\000roundss\t\000rsm\000rsqrtps\t\000rsqrtss\t\000sahf\000sarw\t\000"
- "sarw\t%cl, \000sarl\t\000sarl\t%cl, \000sarq\t\000sarq\t%cl, \000sarb\t"
- "\000sarb\t%cl, \000sbbw\t\000sbbl\t\000sbbq\t\000sbbb\t\000scasw\000sca"
- "sl\000scasq\000scasb\000setae\t\000seta\t\000setbe\t\000setb\t\000sete\t"
- "\000setge\t\000setg\t\000setle\t\000setl\t\000setne\t\000setno\t\000set"
- "np\t\000setns\t\000seto\t\000setp\t\000sets\t\000sfence\000sgdt\t\000sh"
- "lw\t\000shlw\t%cl, \000shll\t\000shll\t%cl, \000shlq\t\000shlq\t%cl, \000"
- "shlb\t\000shlb\t%cl, \000shldw\t%cl, \000shldw\t\000shldl\t%cl, \000shl"
- "dl\t\000shldq\t%cl, \000shldq\t\000shrw\t\000shrw\t%cl, \000shrl\t\000s"
- "hrl\t%cl, \000shrq\t\000shrq\t%cl, \000shrb\t\000shrb\t%cl, \000shrdw\t"
- "%cl, \000shrdw\t\000shrdl\t%cl, \000shrdl\t\000shrdq\t%cl, \000shrdq\t\000"
- "shufpd\t\000shufps\t\000sidt\t\000fsin\000sldtw\t\000sldtq\t\000smsww\t"
- "\000smswl\t\000smswq\t\000sqrtpd\t\000sqrtps\t\000sqrtsd\t\000sqrtss\t\000"
- "fsqrt\000stc\000std\000sti\000stmxcsr\t\000strw\t\000fsts\t\000fstl\t\000"
- "fstps\t\000fstpl\t\000fstpt\t\000fstp\t\000fst\t\000subw\t\000subl\t\000"
- "subq\t\000subb\t\000subpd\t\000subps\t\000fsubrs\t\000fsubrl\t\000fisub"
- "rs\t\000fisubrl\t\000fsubp\t\000fsubr\t\000fsub\t%st(0), \000subsd\t\000"
- "subss\t\000fsubs\t\000fsubl\t\000fisubs\t\000fisubl\t\000fsubrp\t\000fs"
- "ub\t\000fsubr\t%st(0), \000swpgs\000syscall\000sysenter\000sysexit\000s"
- "ysret\000jmp\t*\000#TC_RETURN \000testw\t\000testl\t\000testq\t\000test"
- "b\t\000.byte\t0x66; leaq\t\000ud2\000ftst\000fucomip\t\000fucomi\t\000f"
- "ucompp\000fucomp\t\000fucom\t\000unpckhpd\t\000unpckhps\t\000unpcklpd\t"
- "\000unpcklps\t\000#VASTART_SAVE_XMM_REGS \000verr\t\000verw\t\000vmcall"
- "\000vmclear\t\000vmlaunch\000vmptrld\t\000vmptrst\t\000vmreadl\t\000vmr"
- "eadq\t\000vmresume\000vmwritel\t\000vmwriteq\t\000vmxoff\000vmxon\t\000"
- "wait\000wbinvd\000wrmsr\000xaddw\t\000xaddl\t\000xaddq\t\000xaddb\t\000"
- "xchgw\t\000xchgl\t\000xchgq\t\000xchgb\t\000fxch\t\000xlatb\000xorw\t\000"
- "xorq\t\000";
+ "fcom\t\000fcos\000cpuid\000cqto\000crc32 \t\000cs\000cvtdq2pd\t\000cvtd"
+ "q2ps\t\000cvtpd2dq\t\000cvtpd2ps\t\000cvtps2dq\t\000cvtps2pd\t\000cvtsd"
+ "2siq\t\000cvtsd2ss\t\000cvtsi2sdq\t\000cvtsi2sd\t\000cvtsi2ssq\t\000cvt"
+ "si2ss\t\000cvtss2sd\t\000cvtss2siq\t\000cvtss2sil\t\000cvttps2dq\t\000c"
+ "vttsd2siq\t\000cvttsd2si\t\000cvttss2siq\t\000cvttss2si\t\000cwtd\000cw"
+ "tl\000decw\t\000decl\t\000decq\t\000decb\t\000divw\t\000divl\t\000divq\t"
+ "\000divb\t\000divpd\t\000divps\t\000fdivrs\t\000fdivrl\t\000fidivrs\t\000"
+ "fidivrl\t\000fdivp\t\000fdivr\t\000fdiv\t%st(0), \000divsd\t\000divss\t"
+ "\000fdivs\t\000fdivl\t\000fidivs\t\000fidivl\t\000fdivrp\t\000fdiv\t\000"
+ "fdivr\t%st(0), \000dppd\t\000dpps\t\000ds\000ret\t#eh_return, addr: \000"
+ "enter\t\000es\000extractps\t\000f2xm1\000lcallw\t\000lcallw\t*\000lcall"
+ "l\t\000lcalll\t*\000lcallq\t*\000ljmpw\t\000ljmpw\t*\000ljmpl\t\000ljmp"
+ "l\t*\000ljmpq\t*\000fbld\t\000fbstp\t\000fcoml\t\000fcomll\t\000fcompl\t"
+ "\000fcompll\t\000fcompp\000fdecstp\000ffree\t\000ficomw\t\000ficoml\t\000"
+ "ficompw\t\000ficompl\t\000fincstp\000fldcw\t\000fldenv\t\000fldl2e\000f"
+ "ldl2t\000fldlg2\000fldln2\000fldpi\000fnclex\000fninit\000fnop\000fnstc"
+ "w\t\000fnstsw %ax\000fnstsw\t\000##FP32_TO_INT16_IN_MEM PSEUDO!\000##FP"
+ "32_TO_INT32_IN_MEM PSEUDO!\000##FP32_TO_INT64_IN_MEM PSEUDO!\000##FP64_"
+ "TO_INT16_IN_MEM PSEUDO!\000##FP64_TO_INT32_IN_MEM PSEUDO!\000##FP64_TO_"
+ "INT64_IN_MEM PSEUDO!\000##FP80_TO_INT16_IN_MEM PSEUDO!\000##FP80_TO_INT"
+ "32_IN_MEM PSEUDO!\000##FP80_TO_INT64_IN_MEM PSEUDO!\000fpatan\000fprem\000"
+ "fprem1\000fptan\000##FP_REG_KILL\000frndint\000frstor\t\000fnsave\t\000"
+ "fscale\000fsincos\000fnstenv\t\000movl\t%fs:\000fs\000fxam\000fxrstor\t"
+ "\000fxsave\t\000fxtract\000fyl2x\000fyl2xp1\000movapd\t\000movaps\t\000"
+ "orpd\t\000orps\t\000xorpd\t\000xorps\t\000movl\t%gs:\000gs\000haddpd\t\000"
+ "haddps\t\000hlt\000hsubpd\t\000hsubps\t\000idivw\t\000idivl\t\000idivq\t"
+ "\000idivb\t\000filds\t\000fildl\t\000fildll\t\000imulw\t\000imull\t\000"
+ "imulq\t\000imulb\t\000insw\000inw\t\000inw\t%dx, %ax\000insl\000inl\t\000"
+ "inl\t%dx, %eax\000insb\000inb\t\000inb\t%dx, %al\000incw\t\000incl\t\000"
+ "incq\t\000incb\t\000insertps\t\000int\t\000int\t3\000invd\000invept\000"
+ "invlpg\t\000invvpid\000iretw\000iretl\000iretq\000fisttps\t\000fisttpl\t"
+ "\000fisttpll\t\000fists\t\000fistl\t\000fistps\t\000fistpl\t\000fistpll"
+ "\t\000cvtpd2pi\t\000cvtpi2pd\t\000cvtpi2ps\t\000cvtps2pi\t\000cvtsd2si\t"
+ "\000cvtss2si\t\000cvttpd2dq\t\000cvttpd2pi\t\000cvttps2pi\t\000ucomisd\t"
+ "\000ucomiss\t\000jae\t\000ja\t\000jbe\t\000jb\t\000jcxz\t\000je\t\000jg"
+ "e\t\000jg\t\000jle\t\000jl\t\000jmpl\t*\000jmpq\t*\000jmpq\t\000jmp\t\000"
+ "jne\t\000jno\t\000jnp\t\000jns\t\000jo\t\000jp\t\000js\t\000lahf\000lar"
+ "w\t\000larl\t\000larq\t\000lock\n\tcmpxchgw\t\000lock\n\tcmpxchgl\t\000"
+ "lock\n\tcmpxchgq\t\000lock\n\tcmpxchgb\t\000lock\n\tcmpxchg8b\t\000lddq"
+ "u\t\000ldmxcsr\t\000ldsw\t\000ldsl\t\000fldz\000fld1\000flds\t\000fldl\t"
+ "\000fldt\t\000fld\t\000leaw\t\000leal\t\000leaq\t\000leave\000lesw\t\000"
+ "lesl\t\000lfence\000lfsw\t\000lfsl\t\000lfsq\t\000lgdt\t\000lgsw\t\000l"
+ "gsl\t\000lgsq\t\000lidt\t\000lldtw\t\000lmsww\t\000lock\n\taddw\t\000lo"
+ "ck\n\taddl\t\000lock\n\taddq\t\000lock\n\taddb\t\000lock\n\tdecw\t\000l"
+ "ock\n\tdecl\t\000lock\n\tdecq\t\000lock\n\tdecb\t\000lock\n\tincw\t\000"
+ "lock\n\tincl\t\000lock\n\tincq\t\000lock\n\tincb\t\000lock\000lock\n\ts"
+ "ubw\t\000lock\n\tsubl\t\000lock\n\tsubq\t\000lock\n\tsubb\t\000lodsb\000"
+ "lodsl\000lodsq\000lodsw\000loop\t\000loope\t\000loopne\t\000lret\000lre"
+ "t\t\000lslw\t\000lsll\t\000lslq\t\000lssw\t\000lssl\t\000lssq\t\000ltrw"
+ "\t\000lock\n\txaddw\t\000lock\n\txaddl\t\000lock\n\txadd\t\000lock\n\tx"
+ "addb\t\000maskmovdqu\t\000maxpd\t\000maxps\t\000maxsd\t\000maxss\t\000m"
+ "fence\000minpd\t\000minps\t\000minsd\t\000minss\t\000emms\000femms\000m"
+ "askmovq\t\000movd\t\000movdq2q\t\000movntq\t\000movq2dq\t\000movq\t\000"
+ "packssdw\t\000packsswb\t\000packuswb\t\000paddb\t\000paddd\t\000paddq\t"
+ "\000paddsb\t\000paddsw\t\000paddusb\t\000paddusw\t\000paddw\t\000pandn\t"
+ "\000pand\t\000pavgb\t\000pavgw\t\000pcmpeqb\t\000pcmpeqd\t\000pcmpeqw\t"
+ "\000pcmpgtb\t\000pcmpgtd\t\000pcmpgtw\t\000pextrw\t\000pinsrw\t\000pmad"
+ "dwd\t\000pmaxsw\t\000pmaxub\t\000pminsw\t\000pminub\t\000pmovmskb\t\000"
+ "pmulhuw\t\000pmulhw\t\000pmullw\t\000pmuludq\t\000por\t\000psadbw\t\000"
+ "pshufw\t\000pslld\t\000psllq\t\000psllw\t\000psrad\t\000psraw\t\000psrl"
+ "d\t\000psrlq\t\000psrlw\t\000psubb\t\000psubd\t\000psubq\t\000psubsb\t\000"
+ "psubsw\t\000psubusb\t\000psubusw\t\000psubw\t\000punpckhbw\t\000punpckh"
+ "dq\t\000punpckhwd\t\000punpcklbw\t\000punpckldq\t\000punpcklwd\t\000pxo"
+ "r\t\000monitor\000movw\t%ax, \000movw\t\000movl\t%eax, \000movl\t\000mo"
+ "vq\t%fs:\000movq\t%gs:\000movq\t%rax, \000movabsq\t\000movb\t%al, \000m"
+ "ovb\t\000movddup\t\000movdqa\t\000movdqu\t\000movhlps\t\000movhpd\t\000"
+ "movhps\t\000movlhps\t\000movlpd\t\000movsd\t\000movlps\t\000movss\t\000"
+ "movmskpd\t\000movmskps\t\000movntdqa\t\000movntdq\t\000movnti\t\000movn"
+ "tpd\t\000movntps\t\000movsb\000movsl\000movshdup\t\000movsldup\t\000mov"
+ "sw\000movsbw\t\000movswl\t\000movsbl\t\000movswq\t\000movslq\t\000movsb"
+ "q\t\000movupd\t\000movups\t\000movzbw\t\000movzbl\t\000movzwl\t\000movz"
+ "wq\t\000movzbq\t\000mpsadbw\t\000mulw\t\000mull\t\000mulq\t\000mulb\t\000"
+ "mulpd\t\000mulps\t\000mulsd\t\000mulss\t\000fmuls\t\000fmull\t\000fimul"
+ "s\t\000fimull\t\000fmulp\t\000fmul\t\000fmul\t%st(0), \000mwait\000negw"
+ "\t\000negl\t\000negq\t\000negb\t\000nop\000nopl\t\000nopw\t\000notw\t\000"
+ "notl\t\000notq\t\000notb\t\000orw\t\000orl\t\000orq\t\000orb\t\000outw\t"
+ "%ax, \000outw\t%ax, %dx\000outl\t%eax, \000outl\t%eax, %dx\000outb\t%al"
+ ", \000outb\t%al, %dx\000outsb\000outsl\000outsw\000pabsb\t\000pabsd\t\000"
+ "pabsw\t\000packusdw\t\000palignr\t\000pblendvb\t%xmm0, \000pblendw\t\000"
+ "pcmpeqq\t\000pcmpestri\t\000#PCMPESTRM128rm PSEUDO!\000#PCMPESTRM128rr "
+ "PSEUDO!\000pcmpestrm\t\000pcmpgtq\t\000pcmpistri\t\000#PCMPISTRM128rm P"
+ "SEUDO!\000#PCMPISTRM128rr PSEUDO!\000pcmpistrm\t\000pextrb\t\000pextrd\t"
+ "\000pextrq\t\000phaddd\t\000phaddsw\t\000phaddw\t\000phminposuw\t\000ph"
+ "subd\t\000phsubsw\t\000phsubw\t\000pinsrb\t\000pinsrd\t\000pinsrq\t\000"
+ "pmaddubsw\t\000pmaxsb\t\000pmaxsd\t\000pmaxud\t\000pmaxuw\t\000pminsb\t"
+ "\000pminsd\t\000pminud\t\000pminuw\t\000pmovsxbd\t\000pmovsxbq\t\000pmo"
+ "vsxbw\t\000pmovsxdq\t\000pmovsxwd\t\000pmovsxwq\t\000pmovzxbd\t\000pmov"
+ "zxbq\t\000pmovzxbw\t\000pmovzxdq\t\000pmovzxwd\t\000pmovzxwq\t\000pmuld"
+ "q\t\000pmulhrsw\t\000pmulld\t\000popw\t\000popl\t\000popq\t\000popcntw\t"
+ "\000popcntl\t\000popcntq\t\000popfw\000popfl\000popfq\000popw\t%fs\000p"
+ "opl\t%fs\000popq\t%fs\000popw\t%gs\000popl\t%gs\000popq\t%gs\000prefetc"
+ "hnta\t\000prefetcht0\t\000prefetcht1\t\000prefetcht2\t\000pshufb\t\000p"
+ "shufd\t\000pshufhw\t\000pshuflw\t\000psignb\t\000psignd\t\000psignw\t\000"
+ "pslldq\t\000psrldq\t\000ptest \t\000punpckhqdq\t\000punpcklqdq\t\000pus"
+ "hw\t\000pushl\t\000pushq\t\000pushfw\000pushfl\000pushfq\000pushw\t%fs\000"
+ "pushl\t%fs\000pushq\t%fs\000pushw\t%gs\000pushl\t%gs\000pushq\t%gs\000r"
+ "clw\t1, \000rclw\t%cl, \000rclw\t\000rcll\t1, \000rcll\t%cl, \000rcll\t"
+ "\000rclq\t1, \000rclq\t%cl, \000rclq\t\000rclb\t1, \000rclb\t%cl, \000r"
+ "clb\t\000rcpps\t\000rcpss\t\000rcrw\t1, \000rcrw\t%cl, \000rcrw\t\000rc"
+ "rl\t1, \000rcrl\t%cl, \000rcrl\t\000rcrq\t1, \000rcrq\t%cl, \000rcrq\t\000"
+ "rcrb\t1, \000rcrb\t%cl, \000rcrb\t\000rdmsr\000rdpmc\000rdtsc\000rdtscp"
+ "\000repne\000rep;movsb\000rep;movsl\000rep;movsq\000rep;movsw\000rep\000"
+ "rep;stosb\000rep;stosl\000rep;stosq\000rep;stosw\000ret\000ret\t\000rol"
+ "w\t\000rolw\t%cl, \000roll\t\000roll\t%cl, \000rolq\t\000rolq\t%cl, \000"
+ "rolb\t\000rolb\t%cl, \000rorw\t\000rorw\t%cl, \000rorl\t\000rorl\t%cl, "
+ "\000rorq\t\000rorq\t%cl, \000rorb\t\000rorb\t%cl, \000roundpd\t\000roun"
+ "dps\t\000roundsd\t\000roundss\t\000rsm\000rsqrtps\t\000rsqrtss\t\000sah"
+ "f\000sarw\t\000sarw\t%cl, \000sarl\t\000sarl\t%cl, \000sarq\t\000sarq\t"
+ "%cl, \000sarb\t\000sarb\t%cl, \000sbbw\t\000sbbl\t\000sbbq\t\000sbbb\t\000"
+ "scasw\000scasl\000scasq\000scasb\000setae\t\000seta\t\000setbe\t\000set"
+ "b\t\000sete\t\000setge\t\000setg\t\000setle\t\000setl\t\000setne\t\000s"
+ "etno\t\000setnp\t\000setns\t\000seto\t\000setp\t\000sets\t\000sfence\000"
+ "sgdt\t\000shlw\t\000shlw\t%cl, \000shll\t\000shll\t%cl, \000shlq\t\000s"
+ "hlq\t%cl, \000shlb\t\000shlb\t%cl, \000shldw\t%cl, \000shldw\t\000shldl"
+ "\t%cl, \000shldl\t\000shldq\t%cl, \000shldq\t\000shrw\t\000shrw\t%cl, \000"
+ "shrl\t\000shrl\t%cl, \000shrq\t\000shrq\t%cl, \000shrb\t\000shrb\t%cl, "
+ "\000shrdw\t%cl, \000shrdw\t\000shrdl\t%cl, \000shrdl\t\000shrdq\t%cl, \000"
+ "shrdq\t\000shufpd\t\000shufps\t\000sidt\t\000fsin\000sldtw\t\000sldtq\t"
+ "\000smsww\t\000smswl\t\000smswq\t\000sqrtpd\t\000sqrtps\t\000sqrtsd\t\000"
+ "sqrtss\t\000fsqrt\000ss\000stc\000std\000sti\000stmxcsr\t\000stosb\000s"
+ "tosl\000stosw\000strw\t\000fsts\t\000fstl\t\000fstps\t\000fstpl\t\000fs"
+ "tpt\t\000fstp\t\000fst\t\000subw\t\000subl\t\000subq\t\000subb\t\000sub"
+ "pd\t\000subps\t\000fsubrs\t\000fsubrl\t\000fisubrs\t\000fisubrl\t\000fs"
+ "ubp\t\000fsubr\t\000fsub\t%st(0), \000subsd\t\000subss\t\000fsubs\t\000"
+ "fsubl\t\000fisubs\t\000fisubl\t\000fsubrp\t\000fsub\t\000fsubr\t%st(0),"
+ " \000swapgs\000syscall\000sysenter\000sysexit\000sysret\000jmp\t*\000#T"
+ "C_RETURN \000testw\t\000testl\t\000testq\t\000testb\t\000.byte\t0x66; l"
+ "eaq\t\000ud2\000ftst\000fucomip\t\000fucomi\t\000fucompp\000fucomp\t\000"
+ "fucom\t\000unpckhpd\t\000unpckhps\t\000unpcklpd\t\000unpcklps\t\000#VAS"
+ "TART_SAVE_XMM_REGS \000verr\t\000verw\t\000vmcall\000vmclear\t\000vmlau"
+ "nch\000vmptrld\t\000vmptrst\t\000vmreadl\t\000vmreadq\t\000vmresume\000"
+ "vmwritel\t\000vmwriteq\t\000vmxoff\000vmxon\t\000wait\000wbinvd\000wrms"
+ "r\000xaddw\t\000xaddl\t\000xaddq\t\000xaddb\t\000xchgw\t\000xchgl\t\000"
+ "xchgq\t\000xchgb\t\000fxch\t\000xlatb\000xorw\t\000xorl\t\000xorq\t\000"
+ "xorb\t\000";
-
-#ifndef NO_ASM_WRITER_BOILERPLATE
- if (MI->getOpcode() == TargetInstrInfo::INLINEASM) {
- printInlineAsm(MI);
- return;
- } else if (MI->isLabel()) {
- printLabel(MI);
- return;
- } else if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
- printImplicitDef(MI);
- return;
- } else if (MI->getOpcode() == TargetInstrInfo::KILL) {
- printKill(MI);
- return;
- }
-
-
-#endif
O << "\t";
// Emit the opcode for the instruction.
@@ -2728,11 +2727,11 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
O << AsmStrs+(Bits & 16383)-1;
- // Fragment 0 encoded into 6 bits for 43 unique commands.
+ // Fragment 0 encoded into 6 bits for 42 unique commands.
switch ((Bits >> 26) & 63) {
default: // unreachable.
case 0:
- // DEBUG_VALUE, ABS_F, ADJCALLSTACKDOWN32, ADJCALLSTACKDOWN64, ADJCALLSTA...
+ // DBG_VALUE, ABS_F, ADJCALLSTACKDOWN32, ADJCALLSTACKDOWN64, ADJCALLSTACK...
return;
break;
case 1:
@@ -2861,11 +2860,11 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
return;
break;
case 23:
- // CALL64pcrel32, CALLpcrel32, JA, JA8, JAE, JAE8, JB, JB8, JBE, JBE8, JC...
+ // CALL64pcrel32, CALLpcrel32, JAE_1, JAE_4, JA_1, JA_4, JBE_1, JBE_4, JB...
print_pcrel_imm(MI, 0);
break;
case 24:
- // CLFLUSH, DEC8m, DIV8m, IDIV8m, IMUL8m, INC8m, LOCK_DEC8m, LOCK_INC8m, ...
+ // CLFLUSH, DEC8m, DIV8m, IDIV8m, IMUL8m, INC8m, INVLPG, LOCK_DEC8m, LOCK...
printi8mem(MI, 0);
return;
break;
@@ -2960,17 +2959,12 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
return;
break;
case 40:
- // RCL16mi, RCL32mi, RCL64mi, RCL8mi, RCR16mi, RCR32mi, RCR64mi, RCR8mi
- printOperand(MI, 10);
- O << ", ";
- break;
- case 41:
// TLS_addr32
printlea32mem(MI, 0);
O << ", %eax; call\t___tls_get_addr at PLT";
return;
break;
- case 42:
+ case 41:
// TLS_addr64
printlea64mem(MI, 0);
O << "(%rip), %rdi; .word\t0x6666; rex64; call\t__tls_get_addr at PLT";
@@ -2979,8 +2973,8 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
}
- // Fragment 1 encoded into 6 bits for 36 unique commands.
- switch ((Bits >> 20) & 63) {
+ // Fragment 1 encoded into 5 bits for 32 unique commands.
+ switch ((Bits >> 21) & 31) {
default: // unreachable.
case 0:
// ADC16i16, ADD16i16, AND16i16, CMP16i16, IN16ri, MOV16o16a, OR16i16, SB...
@@ -3114,58 +3108,38 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
return;
break;
case 26:
- // RCL16mi, RCR16mi
- printi16mem(MI, 0);
- return;
- break;
- case 27:
- // RCL32mi, RCR32mi
- printi32mem(MI, 0);
- return;
- break;
- case 28:
- // RCL64mi, RCR64mi
- printi64mem(MI, 0);
- return;
- break;
- case 29:
- // RCL8mi, RCR8mi
- printi8mem(MI, 0);
- return;
- break;
- case 30:
// ROUNDPDm_Int, ROUNDPSm_Int
printf128mem(MI, 1);
O << ", ";
printOperand(MI, 0);
return;
break;
- case 31:
+ case 27:
// ROUNDSDm_Int
printf64mem(MI, 2);
O << ", ";
printOperand(MI, 0);
return;
break;
- case 32:
+ case 28:
// SHUFPDrmi, SHUFPSrmi
printf128mem(MI, 2);
O << ", ";
printOperand(MI, 0);
return;
break;
- case 33:
+ case 29:
// TAILJMPd, TAILJMPm, TAILJMPr, TAILJMPr64
O << " # TAILCALL";
return;
break;
- case 34:
+ case 30:
// TCRETURNdi, TCRETURNdi64, TCRETURNri, TCRETURNri64
O << ' ';
printOperand(MI, 1);
return;
break;
- case 35:
+ case 31:
// XCHG16rr, XCHG32rr, XCHG64rr, XCHG8rr
printOperand(MI, 2);
return;
@@ -3173,8 +3147,8 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
}
- // Fragment 2 encoded into 5 bits for 17 unique commands.
- switch ((Bits >> 15) & 31) {
+ // Fragment 2 encoded into 4 bits for 16 unique commands.
+ switch ((Bits >> 17) & 15) {
default: // unreachable.
case 0:
// ADC16mi, ADC16mi8, ADC16mr, ADD16mi, ADD16mi8, ADD16mr, AND16mi, AND16...
@@ -3243,83 +3217,48 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
return;
break;
case 12:
- // FsFLD0SD, FsFLD0SS, MMX_V_SET0, MMX_V_SETALLONES, MOV32r0, MOV8r0, SET...
- printOperand(MI, 0);
- return;
- break;
- case 13:
// MOV8rr_NOREX, MOVZX32_NOREXrr8
O << " # NOREX";
return;
break;
- case 14:
+ case 13:
// MOVAPDmr, MOVAPSmr, MOVNTDQmr, MOVUPDmr, MOVUPDmr_Int, MOVUPSmr, MOVUP...
printf128mem(MI, 0);
return;
break;
- case 15:
+ case 14:
// MOVDQAmr, MOVDQUmr, MOVDQUmr_Int, MOVNTPDmr, MOVNTPSmr
printi128mem(MI, 0);
return;
break;
- case 16:
+ case 15:
// MOVHPDmr, MOVHPSmr, MOVLPDmr, MOVLPSmr, MOVPD2SDmr, MOVSDmr
printf64mem(MI, 0);
return;
break;
}
- switch (MI->getOpcode()) {
- case X86::ADC8mi:
- case X86::ADC8mr:
- case X86::ADD8mi:
- case X86::ADD8mr:
- case X86::AND8mi:
- case X86::AND8mr:
- case X86::CMP8mi:
- case X86::CMP8mr:
- case X86::CMPXCHG8rm:
- case X86::ENTER:
- case X86::FARCALL16i:
- case X86::FARCALL32i:
- case X86::FARJMP16i:
- case X86::FARJMP32i:
- case X86::LCMPXCHG8:
- case X86::LOCK_ADD8mi:
- case X86::LOCK_ADD8mr:
- case X86::LOCK_SUB8mi:
- case X86::LOCK_SUB8mr:
- case X86::MOV8mi:
- case X86::MOV8mr:
- case X86::OR8mi:
- case X86::OR8mr:
- case X86::PEXTRBmr:
- case X86::ROL8mi:
- case X86::ROR8mi:
- case X86::SAR8mi:
- case X86::SBB8mi:
- case X86::SBB8mr:
- case X86::SHL8mi:
- case X86::SHR8mi:
- case X86::SUB8mi:
- case X86::SUB8mr:
- case X86::TEST8mi:
- case X86::XADD8rm:
- case X86::XOR8mi:
- case X86::XOR8mr:
- return;
- break;
- case X86::MOV8mr_NOREX:
+
+ // Fragment 3 encoded into 2 bits for 3 unique commands.
+ switch ((Bits >> 15) & 3) {
+ default: // unreachable.
+ case 0:
+ // ADC8mi, ADC8mr, ADD8mi, ADD8mr, AND8mi, AND8mr, CMP8mi, CMP8mr, CMPXCH...
+ return;
+ break;
+ case 1:
+ // MOV8mr_NOREX
O << " # NOREX";
return;
break;
- case X86::VASTART_SAVE_XMM_REGS:
+ case 2:
+ // VASTART_SAVE_XMM_REGS
O << ", ";
printOperand(MI, 2);
return;
break;
}
- return;
+
}
@@ -3364,3 +3303,659 @@ const char *X86ATTInstPrinter::getRegisterName(unsigned RegNo) {
"\000ymm7\000ymm8\000ymm9\000";
return AsmStrs+RegAsmOffset[RegNo-1];
}
+
+
+#ifdef GET_INSTRUCTION_NAME
+#undef GET_INSTRUCTION_NAME
+
+/// getInstructionName: This method is automatically generated by tblgen
+/// from the instruction set description. This returns the enum name of the
+/// specified instruction.
+const char *X86ATTInstPrinter::getInstructionName(unsigned Opcode) {
+ assert(Opcode < 2532 && "Invalid instruction number!");
+
+ static const unsigned InstAsmOffset[] = {
+ 0, 4, 14, 24, 33, 42, 47, 62, 76, 89, 103, 120, 130, 136,
+ 145, 154, 163, 172, 180, 189, 197, 205, 214, 222, 230, 242, 251, 259,
+ 268, 276, 284, 293, 301, 309, 321, 330, 340, 349, 357, 367, 376, 384,
+ 392, 404, 411, 418, 425, 432, 439, 446, 457, 466, 474, 483, 491, 502,
+ 510, 519, 527, 535, 544, 552, 561, 569, 580, 588, 597, 605, 613, 622,
+ 632, 641, 649, 660, 670, 679, 687, 695, 702, 709, 716, 726, 733, 740,
+ 747, 755, 763, 771, 779, 787, 799, 807, 819, 827, 839, 847, 859, 870,
+ 881, 892, 903, 912, 921, 931, 941, 952, 962, 971, 981, 990, 1000, 1012,
+ 1021, 1033, 1045, 1058, 1071, 1084, 1097, 1110, 1123, 1133, 1152, 1171, 1188, 1205,
+ 1214, 1222, 1231, 1239, 1247, 1256, 1264, 1272, 1284, 1293, 1301, 1310, 1318, 1326,
+ 1335, 1343, 1351, 1363, 1372, 1382, 1391, 1399, 1409, 1418, 1426, 1434, 1446, 1453,
+ 1460, 1467, 1474, 1481, 1488, 1499, 1508, 1517, 1526, 1535, 1543, 1551, 1559, 1567,
+ 1579, 1589, 1599, 1609, 1621, 1630, 1640, 1650, 1660, 1670, 1680, 1690, 1701, 1712,
+ 1723, 1736, 1746, 1755, 1764, 1773, 1784, 1792, 1804, 1817, 1828, 1839, 1850, 1861,
+ 1872, 1883, 1893, 1903, 1913, 1925, 1934, 1945, 1956, 1967, 1978, 1990, 2002, 2014,
+ 2026, 2034, 2042, 2050, 2058, 2066, 2074, 2082, 2090, 2098, 2106, 2114, 2122, 2131,
+ 2140, 2148, 2155, 2163, 2170, 2178, 2185, 2193, 2200, 2208, 2215, 2223, 2230, 2239,
+ 2247, 2256, 2264, 2273, 2281, 2290, 2298, 2307, 2315, 2324, 2332, 2341, 2349, 2358,
+ 2366, 2375, 2383, 2392, 2400, 2409, 2417, 2426, 2434, 2443, 2451, 2460, 2468, 2477,
+ 2485, 2494, 2502, 2511, 2519, 2528, 2536, 2544, 2552, 2560, 2574, 2582, 2594, 2598,
+ 2602, 2607, 2613, 2622, 2631, 2640, 2644, 2648, 2656, 2660, 2665, 2669, 2679, 2689,
+ 2699, 2709, 2719, 2729, 2740, 2751, 2762, 2773, 2784, 2795, 2805, 2815, 2825, 2835,
+ 2845, 2855, 2866, 2877, 2888, 2899, 2910, 2921, 2930, 2942, 2954, 2966, 2974, 2985,
+ 2996, 3007, 3017, 3027, 3037, 3047, 3057, 3067, 3075, 3086, 3097, 3108, 3118, 3128,
+ 3138, 3148, 3158, 3168, 3179, 3190, 3201, 3212, 3223, 3234, 3244, 3254, 3264, 3274,
+ 3284, 3294, 3305, 3316, 3327, 3338, 3349, 3360, 3370, 3383, 3396, 3409, 3418, 3430,
+ 3442, 3454, 3465, 3476, 3487, 3498, 3509, 3520, 3529, 3541, 3553, 3565, 3576, 3587,
+ 3598, 3609, 3620, 3631, 3642, 3653, 3664, 3675, 3686, 3697, 3706, 3718, 3730, 3742,
+ 3753, 3764, 3775, 3786, 3797, 3808, 3818, 3828, 3838, 3848, 3858, 3868, 3878, 3888,
+ 3898, 3908, 3918, 3928, 3936, 3947, 3958, 3969, 3979, 3989, 3999, 4009, 4019, 4029,
+ 4039, 4049, 4058, 4069, 4080, 4091, 4102, 4111, 4119, 4128, 4136, 4147, 4155, 4164,
+ 4172, 4180, 4189, 4197, 4206, 4214, 4225, 4233, 4242, 4250, 4258, 4267, 4277, 4286,
+ 4294, 4305, 4315, 4324, 4332, 4340, 4347, 4354, 4361, 4371, 4378, 4385, 4392, 4401,
+ 4410, 4419, 4428, 4435, 4442, 4449, 4455, 4463, 4471, 4479, 4487, 4498, 4510, 4522,
+ 4534, 4546, 4558, 4570, 4580, 4591, 4602, 4611, 4620, 4629, 4638, 4649, 4658, 4666,
+ 4676, 4682, 4691, 4700, 4709, 4715, 4719, 4728, 4737, 4745, 4754, 4763, 4771, 4780,
+ 4789, 4799, 4810, 4821, 4832, 4843, 4854, 4865, 4876, 4887, 4898, 4909, 4920, 4931,
+ 4944, 4957, 4968, 4979, 4992, 5005, 5016, 5027, 5040, 5053, 5064, 5075, 5086, 5097,
+ 5110, 5123, 5134, 5145, 5157, 5169, 5183, 5197, 5209, 5221, 5235, 5249, 5261, 5273,
+ 5277, 5282, 5289, 5296, 5303, 5310, 5320, 5330, 5340, 5350, 5357, 5364, 5370, 5376,
+ 5383, 5390, 5397, 5404, 5411, 5418, 5424, 5430, 5438, 5446, 5454, 5462, 5472, 5482,
+ 5493, 5504, 5516, 5527, 5538, 5549, 5562, 5575, 5588, 5602, 5616, 5630, 5644, 5658,
+ 5672, 5683, 5691, 5703, 5711, 5723, 5731, 5743, 5751, 5763, 5772, 5781, 5791, 5801,
+ 5812, 5822, 5831, 5841, 5850, 5860, 5872, 5881, 5893, 5905, 5918, 5931, 5944, 5957,
+ 5970, 5983, 5993, 6001, 6009, 6017, 6025, 6035, 6045, 6057, 6063, 6073, 6085, 6097,
+ 6103, 6114, 6125, 6136, 6147, 6157, 6167, 6177, 6187, 6197, 6206, 6212, 6219, 6227,
+ 6235, 6244, 6253, 6260, 6268, 6274, 6283, 6292, 6302, 6312, 6320, 6329, 6337, 6344,
+ 6351, 6358, 6365, 6371, 6378, 6385, 6390, 6400, 6409, 6417, 6438, 6459, 6480, 6501,
+ 6522, 6543, 6564, 6585, 6606, 6613, 6619, 6626, 6632, 6644, 6652, 6660, 6667, 6674,
+ 6682, 6690, 6701, 6711, 6716, 6724, 6731, 6739, 6745, 6753, 6766, 6779, 6792, 6805,
+ 6818, 6831, 6844, 6857, 6870, 6883, 6896, 6909, 6920, 6931, 6942, 6953, 6963, 6973,
+ 6983, 6993, 7002, 7011, 7022, 7033, 7044, 7055, 7064, 7073, 7082, 7091, 7101, 7111,
+ 7121, 7131, 7142, 7152, 7161, 7170, 7179, 7188, 7192, 7201, 7210, 7219, 7228, 7236,
+ 7244, 7252, 7260, 7268, 7276, 7283, 7290, 7299, 7308, 7317, 7329, 7341, 7353, 7365,
+ 7377, 7389, 7401, 7413, 7425, 7433, 7441, 7450, 7460, 7471, 7480, 7490, 7501, 7509,
+ 7517, 7526, 7536, 7547, 7556, 7566, 7577, 7585, 7593, 7602, 7614, 7625, 7634, 7646,
+ 7657, 7664, 7671, 7676, 7683, 7690, 7695, 7702, 7709, 7713, 7719, 7725, 7732, 7739,
+ 7746, 7753, 7763, 7773, 7783, 7793, 7800, 7807, 7813, 7819, 7830, 7841, 7845, 7850,
+ 7855, 7862, 7869, 7877, 7884, 7891, 7898, 7909, 7920, 7931, 7944, 7957, 7970, 7983,
+ 7996, 8009, 8022, 8035, 8048, 8057, 8066, 8076, 8086, 8096, 8108, 8120, 8132, 8144,
+ 8156, 8168, 8180, 8192, 8204, 8216, 8228, 8240, 8252, 8265, 8278, 8291, 8304, 8319,
+ 8334, 8349, 8364, 8379, 8394, 8409, 8424, 8439, 8454, 8469, 8484, 8499, 8514, 8529,
+ 8544, 8559, 8574, 8589, 8604, 8621, 8638, 8653, 8668, 8683, 8698, 8715, 8732, 8747,
+ 8762, 8779, 8796, 8811, 8826, 8841, 8856, 8873, 8890, 8905, 8920, 8936, 8952, 8968,
+ 8984, 9000, 9016, 9032, 9048, 9066, 9084, 9100, 9116, 9134, 9152, 9168, 9184, 9198,
+ 9212, 9226, 9240, 9246, 9252, 9257, 9262, 9268, 9274, 9279, 9284, 9290, 9295, 9300,
+ 9306, 9312, 9317, 9322, 9328, 9334, 9339, 9344, 9351, 9358, 9365, 9378, 9385, 9391,
+ 9397, 9403, 9409, 9415, 9421, 9427, 9433, 9439, 9445, 9450, 9455, 9460, 9465, 9470,
+ 9475, 9480, 9488, 9496, 9504, 9512, 9520, 9528, 9539, 9550, 9561, 9571, 9582, 9590,
+ 9598, 9606, 9614, 9620, 9626, 9634, 9642, 9650, 9659, 9668, 9677, 9686, 9695, 9704,
+ 9713, 9724, 9735, 9744, 9755, 9764, 9771, 9778, 9785, 9795, 9802, 9808, 9816, 9824,
+ 9832, 9839, 9847, 9855, 9863, 9869, 9877, 9885, 9893, 9899, 9907, 9915, 9923, 9931,
+ 9944, 9958, 9971, 9984, 9998, 10011, 10026, 10040, 10053, 10065, 10077, 10089, 10101, 10113,
+ 10124, 10136, 10148, 10160, 10171, 10183, 10196, 10210, 10223, 10236, 10250, 10263, 10278, 10292,
+ 10305, 10317, 10329, 10335, 10341, 10347, 10353, 10358, 10364, 10371, 10376, 10382, 10390, 10398,
+ 10406, 10414, 10422, 10430, 10438, 10446, 10454, 10459, 10464, 10472, 10480, 10488, 10495, 10506,
+ 10519, 10527, 10539, 10547, 10559, 10567, 10579, 10587, 10599, 10607, 10619, 10627, 10639, 10647,
+ 10659, 10667, 10679, 10686, 10694, 10706, 10714, 10726, 10734, 10746, 10754, 10766, 10774, 10786,
+ 10794, 10806, 10814, 10826, 10834, 10846, 10861, 10876, 10891, 10906, 10921, 10936, 10951, 10966,
+ 10982, 10998, 11014, 11030, 11039, 11049, 11062, 11077, 11096, 11110, 11123, 11136, 11149, 11166,
+ 11183, 11197, 11210, 11224, 11240, 11254, 11267, 11280, 11293, 11310, 11327, 11342, 11357, 11372,
+ 11387, 11402, 11417, 11429, 11441, 11453, 11465, 11477, 11489, 11502, 11515, 11528, 11541, 11555,
+ 11569, 11583, 11597, 11609, 11621, 11633, 11645, 11656, 11667, 11679, 11691, 11703, 11715, 11729,
+ 11743, 11757, 11771, 11785, 11799, 11813, 11827, 11841, 11855, 11869, 11883, 11896, 11910, 11924,
+ 11938, 11952, 11965, 11978, 11991, 12004, 12017, 12030, 12043, 12056, 12071, 12085, 12099, 12112,
+ 12125, 12138, 12151, 12165, 12179, 12189, 12199, 12212, 12225, 12238, 12251, 12263, 12275, 12287,
+ 12299, 12311, 12323, 12335, 12347, 12359, 12371, 12383, 12395, 12407, 12419, 12431, 12443, 12455,
+ 12467, 12479, 12491, 12503, 12515, 12527, 12539, 12551, 12563, 12575, 12587, 12599, 12611, 12624,
+ 12637, 12650, 12663, 12677, 12691, 12705, 12719, 12731, 12743, 12759, 12775, 12791, 12807, 12823,
+ 12839, 12855, 12871, 12887, 12903, 12919, 12935, 12946, 12957, 12968, 12985, 12993, 13003, 13011,
+ 13019, 13027, 13037, 13045, 13053, 13061, 13069, 13081, 13089, 13097, 13105, 13115, 13123, 13131,
+ 13139, 13147, 13157, 13165, 13173, 13181, 13189, 13197, 13205, 13217, 13227, 13237, 13247, 13256,
+ 13264, 13272, 13282, 13290, 13298, 13308, 13317, 13325, 13333, 13341, 13349, 13359, 13372, 13380,
+ 13388, 13400, 13408, 13416, 13424, 13437, 13449, 13461, 13469, 13476, 13483, 13496, 13504, 13511,
+ 13518, 13525, 13538, 13545, 13558, 13569, 13578, 13587, 13596, 13605, 13614, 13623, 13633, 13643,
+ 13655, 13667, 13678, 13689, 13698, 13707, 13716, 13725, 13738, 13747, 13760, 13770, 13779, 13788,
+ 13797, 13806, 13816, 13825, 13834, 13843, 13852, 13861, 13870, 13881, 13893, 13905, 13916, 13927,
+ 13938, 13948, 13957, 13967, 13977, 13986, 13997, 14008, 14020, 14032, 14044, 14057, 14068, 14079,
+ 14091, 14100, 14106, 14112, 14123, 14134, 14142, 14150, 14158, 14170, 14182, 14193, 14204, 14215,
+ 14226, 14237, 14248, 14259, 14270, 14278, 14286, 14294, 14300, 14311, 14323, 14334, 14346, 14358,
+ 14369, 14381, 14392, 14404, 14416, 14427, 14439, 14451, 14462, 14471, 14484, 14493, 14506, 14515,
+ 14524, 14537, 14546, 14559, 14568, 14581, 14594, 14610, 14626, 14639, 14652, 14664, 14676, 14687,
+ 14699, 14710, 14722, 14739, 14756, 14768, 14779, 14791, 14802, 14814, 14828, 14840, 14851, 14864,
+ 14876, 14890, 14902, 14913, 14926, 14937, 14948, 14959, 14970, 14981, 14992, 15003, 15014, 15025,
+ 15036, 15047, 15054, 15061, 15068, 15075, 15082, 15089, 15095, 15101, 15109, 15117, 15125, 15133,
+ 15141, 15153, 15161, 15173, 15181, 15193, 15201, 15213, 15222, 15231, 15241, 15251, 15262, 15272,
+ 15281, 15291, 15300, 15310, 15322, 15331, 15343, 15355, 15368, 15381, 15394, 15407, 15420, 15433,
+ 15443, 15449, 15456, 15463, 15470, 15477, 15484, 15491, 15497, 15503, 15508, 15514, 15520, 15527,
+ 15534, 15541, 15548, 15555, 15562, 15568, 15574, 15582, 15589, 15597, 15604, 15611, 15619, 15626,
+ 15633, 15644, 15652, 15659, 15667, 15674, 15681, 15689, 15696, 15703, 15714, 15722, 15731, 15739,
+ 15746, 15755, 15763, 15770, 15777, 15788, 15794, 15800, 15806, 15812, 15818, 15824, 15834, 15841,
+ 15848, 15855, 15862, 15870, 15878, 15886, 15894, 15901, 15908, 15914, 15920, 15926, 15937, 15947,
+ 15958, 15968, 15979, 15989, 16000, 16010, 16021, 16031, 16042, 16052, 16063, 16074, 16085, 16096,
+ 16107, 16118, 16129, 16140, 16148, 16156, 16164, 16172, 16180, 16188, 16197, 16206, 16215, 16224,
+ 16234, 16244, 16254, 16264, 16272, 16280, 16293, 16306, 16318, 16330, 16338, 16346, 16353, 16360,
+ 16368, 16376, 16384, 16392, 16404, 16416, 16427, 16438, 16448, 16458, 16468, 16478, 16488, 16498,
+ 16508, 16518, 16531, 16544, 16557, 16570, 16583, 16596, 16609, 16622, 16635, 16648, 16660, 16672,
+ 16688, 16704, 16719, 16734, 16744, 16754, 16764, 16774, 16784, 16794, 16804, 16814, 16827, 16840,
+ 16853, 16866, 16879, 16892, 16905, 16918, 16931, 16944, 16956, 16968, 16984, 17000, 17015, 17030,
+ 17039, 17048, 17057, 17066, 17075, 17084, 17093, 17102, 17114, 17125, 17137, 17148, 17161, 17173,
+ 17186, 17198, 17210, 17221, 17233, 17244, 17260, 17276, 17288, 17299, 17311, 17322, 17335, 17347,
+ 17360, 17372, 17384, 17395, 17407, 17418, 17427, 17436, 17445, 17454, 17463, 17472, 17482, 17492,
+ 17507, 17521, 17536, 17550, 17560, 17570, 17579, 17588, 17597, 17606, 17615, 17624, 17633, 17642,
+ 17651, 17660, 17669, 17678, 17687, 17696, 17705, 17714, 17723, 17732, 17741, 17750, 17759, 17768,
+ 17777, 17786, 17797, 17808, 17819, 17830, 17841, 17852, 17863, 17874, 17885, 17896, 17907, 17918,
+ 17929, 17940, 17951, 17962, 17973, 17984, 17995, 18006, 18017, 18028, 18039, 18050, 18061, 18070,
+ 18079, 18093, 18106, 18120, 18133, 18143, 18153, 18162, 18171, 18180, 18193, 18202, 18215, 18224,
+ 18233, 18243, 18253, 18260, 18269, 18278, 18285, 18294, 18303, 18310, 18319, 18328, 18339, 18350,
+ 18361, 18372, 18383, 18394, 18399, 18405, 18411, 18419, 18427, 18435, 18443, 18451, 18459, 18465,
+ 18471, 18483, 18494, 18505, 18516, 18525, 18534, 18546, 18557, 18569, 18580, 18589, 18598, 18608,
+ 18618, 18628, 18638, 18650, 18661, 18673, 18684, 18696, 18707, 18719, 18730, 18742, 18753, 18765,
+ 18776, 18785, 18793, 18801, 18809, 18817, 18825, 18833, 18841, 18849, 18857, 18865, 18873, 18881,
+ 18889, 18897, 18905, 18914, 18922, 18930, 18938, 18946, 18954, 18962, 18970, 18978, 18986, 18994,
+ 19002, 19010, 19018, 19026, 19034, 19043, 19052, 19061, 19070, 19080, 19090, 19100, 19110, 19118,
+ 19126, 19134, 19142, 19154, 19166, 19178, 19190, 19203, 19216, 19228, 19240, 19252, 19264, 19276,
+ 19288, 19301, 19314, 19326, 19338, 19346, 19356, 19366, 19376, 19386, 19395, 19403, 19413, 19423,
+ 19433, 19443, 19452, 19460, 19470, 19480, 19486, 19493, 19502, 19511, 19520, 19529, 19538, 19547,
+ 19556, 19563, 19570, 19578, 19587, 19595, 19603, 19612, 19620, 19628, 19637, 19645, 19653, 19662,
+ 19670, 19678, 19687, 19695, 19703, 19712, 19720, 19727, 19735, 19742, 19749, 19757, 19764, 19771,
+ 19782, 19789, 19800, 19807, 19818, 19825, 19836, 19844, 19853, 19861, 19869, 19878, 19886, 19894,
+ 19903, 19911, 19919, 19928, 19936, 19944, 19953, 19961, 19969, 19978, 19986, 19993, 20001, 20008,
+ 20015, 20023, 20030, 20036, 20042, 20048, 20055, 20068, 20078, 20088, 20098, 20108, 20119, 20129,
+ 20139, 20149, 20159, 20163, 20168, 20176, 20185, 20193, 20201, 20210, 20218, 20226, 20235, 20243,
+ 20251, 20260, 20268, 20276, 20285, 20293, 20301, 20310, 20318, 20325, 20333, 20340, 20347, 20355,
+ 20362, 20370, 20379, 20387, 20395, 20404, 20412, 20420, 20429, 20437, 20445, 20454, 20462, 20470,
+ 20479, 20487, 20495, 20504, 20512, 20519, 20527, 20534, 20541, 20549, 20556, 20569, 20582, 20595,
+ 20608, 20621, 20634, 20647, 20660, 20664, 20673, 20686, 20695, 20708, 20717, 20730, 20739, 20752,
+ 20757, 20765, 20774, 20782, 20790, 20799, 20807, 20815, 20824, 20832, 20840, 20849, 20857, 20865,
+ 20874, 20882, 20890, 20899, 20907, 20914, 20922, 20929, 20936, 20944, 20951, 20960, 20968, 20977,
+ 20985, 20993, 21002, 21010, 21018, 21030, 21039, 21047, 21056, 21064, 21072, 21081, 21089, 21097,
+ 21109, 21118, 21128, 21137, 21145, 21155, 21164, 21172, 21180, 21192, 21199, 21206, 21213, 21220,
+ 21227, 21234, 21245, 21252, 21259, 21266, 21272, 21279, 21286, 21292, 21298, 21305, 21312, 21322,
+ 21332, 21342, 21351, 21357, 21363, 21369, 21375, 21382, 21389, 21395, 21401, 21408, 21415, 21421,
+ 21427, 21434, 21441, 21448, 21455, 21462, 21469, 21476, 21483, 21489, 21495, 21501, 21507, 21513,
+ 21519, 21526, 21532, 21540, 21549, 21557, 21565, 21574, 21582, 21590, 21599, 21607, 21615, 21624,
+ 21632, 21640, 21649, 21657, 21665, 21674, 21682, 21689, 21697, 21704, 21711, 21719, 21726, 21737,
+ 21748, 21759, 21770, 21781, 21792, 21803, 21814, 21825, 21836, 21847, 21858, 21866, 21875, 21883,
+ 21891, 21900, 21908, 21916, 21925, 21933, 21941, 21950, 21958, 21966, 21975, 21983, 21991, 22000,
+ 22008, 22015, 22023, 22030, 22037, 22045, 22052, 22063, 22074, 22085, 22096, 22107, 22118, 22129,
+ 22140, 22151, 22162, 22173, 22184, 22194, 22204, 22214, 22224, 22230, 22236, 22245, 22254, 22263,
+ 22271, 22279, 22287, 22295, 22303, 22311, 22319, 22327, 22335, 22347, 22355, 22367, 22375, 22387,
+ 22395, 22407, 22415, 22427, 22435, 22447, 22455, 22467, 22475, 22487, 22494, 22504, 22514, 22524,
+ 22534, 22538, 22542, 22546, 22554, 22560, 22566, 22572, 22577, 22582, 22590, 22598, 22607, 22616,
+ 22625, 22633, 22642, 22651, 22662, 22673, 22684, 22694, 22704, 22716, 22726, 22738, 22750, 22757,
+ 22766, 22774, 22783, 22791, 22799, 22808, 22816, 22824, 22836, 22845, 22853, 22862, 22870, 22878,
+ 22887, 22895, 22903, 22915, 22924, 22934, 22943, 22951, 22961, 22970, 22978, 22986, 22998, 23005,
+ 23012, 23019, 23026, 23033, 23040, 23051, 23059, 23067, 23075, 23083, 23093, 23103, 23114, 23125,
+ 23137, 23148, 23159, 23170, 23183, 23196, 23209, 23223, 23237, 23251, 23265, 23279, 23293, 23304,
+ 23312, 23324, 23332, 23344, 23352, 23364, 23372, 23384, 23393, 23402, 23412, 23422, 23433, 23443,
+ 23452, 23462, 23471, 23481, 23493, 23502, 23514, 23526, 23539, 23552, 23565, 23578, 23591, 23604,
+ 23614, 23621, 23629, 23638, 23646, 23656, 23663, 23672, 23681, 23690, 23701, 23712, 23725, 23736,
+ 23749, 23759, 23768, 23777, 23786, 23795, 23805, 23814, 23823, 23832, 23841, 23851, 23862, 23873,
+ 23882, 23891, 23899, 23907, 23915, 23923, 23931, 23942, 23953, 23958, 23964, 23973, 23982, 23991,
+ 24001, 24011, 24021, 24031, 24041, 24050, 24060, 24069, 24081, 24093, 24105, 24116, 24127, 24138,
+ 24146, 24157, 24168, 24179, 24190, 24201, 24212, 24223, 24234, 24256, 24262, 24268, 24274, 24280,
+ 24287, 24296, 24305, 24314, 24323, 24334, 24345, 24356, 24367, 24376, 24388, 24400, 24412, 24424,
+ 24431, 24437, 24444, 24457, 24462, 24469, 24480, 24497, 24508, 24514, 24523, 24532, 24541, 24550,
+ 24559, 24568, 24576, 24584, 24593, 24602, 24611, 24620, 24629, 24638, 24647, 24656, 24665, 24673,
+ 24681, 24687, 24692, 24701, 24709, 24718, 24726, 24734, 24743, 24751, 24759, 24771, 24780, 24788,
+ 24797, 24805, 24813, 24822, 24830, 24838, 24850, 24859, 24869, 24878, 24886, 24896, 24905, 24913,
+ 24921, 24933, 24940, 24947, 24954, 24961, 24968, 24975, 24986, 24994, 25002, 25010, 0
+ };
+
+ const char *Strs =
+ "PHI\000INLINEASM\000DBG_LABEL\000EH_LABEL\000GC_LABEL\000KILL\000EXTRAC"
+ "T_SUBREG\000INSERT_SUBREG\000IMPLICIT_DEF\000SUBREG_TO_REG\000COPY_TO_R"
+ "EGCLASS\000DBG_VALUE\000ABS_F\000ABS_Fp32\000ABS_Fp64\000ABS_Fp80\000AD"
+ "C16i16\000ADC16mi\000ADC16mi8\000ADC16mr\000ADC16ri\000ADC16ri8\000ADC1"
+ "6rm\000ADC16rr\000ADC16rr_REV\000ADC32i32\000ADC32mi\000ADC32mi8\000ADC"
+ "32mr\000ADC32ri\000ADC32ri8\000ADC32rm\000ADC32rr\000ADC32rr_REV\000ADC"
+ "64i32\000ADC64mi32\000ADC64mi8\000ADC64mr\000ADC64ri32\000ADC64ri8\000A"
+ "DC64rm\000ADC64rr\000ADC64rr_REV\000ADC8i8\000ADC8mi\000ADC8mr\000ADC8r"
+ "i\000ADC8rm\000ADC8rr\000ADC8rr_REV\000ADD16i16\000ADD16mi\000ADD16mi8\000"
+ "ADD16mr\000ADD16mrmrr\000ADD16ri\000ADD16ri8\000ADD16rm\000ADD16rr\000A"
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+ "DD32ri8\000ADD32rm\000ADD32rr\000ADD64i32\000ADD64mi32\000ADD64mi8\000A"
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+ "ADD8i8\000ADD8mi\000ADD8mr\000ADD8mrmrr\000ADD8ri\000ADD8rm\000ADD8rr\000"
+ "ADDPDrm\000ADDPDrr\000ADDPSrm\000ADDPSrr\000ADDSDrm\000ADDSDrm_Int\000A"
+ "DDSDrr\000ADDSDrr_Int\000ADDSSrm\000ADDSSrm_Int\000ADDSSrr\000ADDSSrr_I"
+ "nt\000ADDSUBPDrm\000ADDSUBPDrr\000ADDSUBPSrm\000ADDSUBPSrr\000ADD_F32m\000"
+ "ADD_F64m\000ADD_FI16m\000ADD_FI32m\000ADD_FPrST0\000ADD_FST0r\000ADD_Fp"
+ "32\000ADD_Fp32m\000ADD_Fp64\000ADD_Fp64m\000ADD_Fp64m32\000ADD_Fp80\000"
+ "ADD_Fp80m32\000ADD_Fp80m64\000ADD_FpI16m32\000ADD_FpI16m64\000ADD_FpI16"
+ "m80\000ADD_FpI32m32\000ADD_FpI32m64\000ADD_FpI32m80\000ADD_FrST0\000ADJ"
+ "CALLSTACKDOWN32\000ADJCALLSTACKDOWN64\000ADJCALLSTACKUP32\000ADJCALLSTA"
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+ "32mi8\000AND32mr\000AND32ri\000AND32ri8\000AND32rm\000AND32rr\000AND32r"
+ "r_REV\000AND64i32\000AND64mi32\000AND64mi8\000AND64mr\000AND64ri32\000A"
+ "ND64ri8\000AND64rm\000AND64rr\000AND64rr_REV\000AND8i8\000AND8mi\000AND"
+ "8mr\000AND8ri\000AND8rm\000AND8rr\000AND8rr_REV\000ANDNPDrm\000ANDNPDrr"
+ "\000ANDNPSrm\000ANDNPSrr\000ANDPDrm\000ANDPDrr\000ANDPSrm\000ANDPSrr\000"
+ "ATOMADD6432\000ATOMAND16\000ATOMAND32\000ATOMAND64\000ATOMAND6432\000AT"
+ "OMAND8\000ATOMMAX16\000ATOMMAX32\000ATOMMAX64\000ATOMMIN16\000ATOMMIN32"
+ "\000ATOMMIN64\000ATOMNAND16\000ATOMNAND32\000ATOMNAND64\000ATOMNAND6432"
+ "\000ATOMNAND8\000ATOMOR16\000ATOMOR32\000ATOMOR64\000ATOMOR6432\000ATOM"
+ "OR8\000ATOMSUB6432\000ATOMSWAP6432\000ATOMUMAX16\000ATOMUMAX32\000ATOMU"
+ "MAX64\000ATOMUMIN16\000ATOMUMIN32\000ATOMUMIN64\000ATOMXOR16\000ATOMXOR"
+ "32\000ATOMXOR64\000ATOMXOR6432\000ATOMXOR8\000BLENDPDrmi\000BLENDPDrri\000"
+ "BLENDPSrmi\000BLENDPSrri\000BLENDVPDrm0\000BLENDVPDrr0\000BLENDVPSrm0\000"
+ "BLENDVPSrr0\000BSF16rm\000BSF16rr\000BSF32rm\000BSF32rr\000BSF64rm\000B"
+ "SF64rr\000BSR16rm\000BSR16rr\000BSR32rm\000BSR32rr\000BSR64rm\000BSR64r"
+ "r\000BSWAP32r\000BSWAP64r\000BT16mi8\000BT16mr\000BT16ri8\000BT16rr\000"
+ "BT32mi8\000BT32mr\000BT32ri8\000BT32rr\000BT64mi8\000BT64mr\000BT64ri8\000"
+ "BT64rr\000BTC16mi8\000BTC16mr\000BTC16ri8\000BTC16rr\000BTC32mi8\000BTC"
+ "32mr\000BTC32ri8\000BTC32rr\000BTC64mi8\000BTC64mr\000BTC64ri8\000BTC64"
+ "rr\000BTR16mi8\000BTR16mr\000BTR16ri8\000BTR16rr\000BTR32mi8\000BTR32mr"
+ "\000BTR32ri8\000BTR32rr\000BTR64mi8\000BTR64mr\000BTR64ri8\000BTR64rr\000"
+ "BTS16mi8\000BTS16mr\000BTS16ri8\000BTS16rr\000BTS32mi8\000BTS32mr\000BT"
+ "S32ri8\000BTS32rr\000BTS64mi8\000BTS64mr\000BTS64ri8\000BTS64rr\000CALL"
+ "32m\000CALL32r\000CALL64m\000CALL64pcrel32\000CALL64r\000CALLpcrel32\000"
+ "CBW\000CDQ\000CDQE\000CHS_F\000CHS_Fp32\000CHS_Fp64\000CHS_Fp80\000CLC\000"
+ "CLD\000CLFLUSH\000CLI\000CLTS\000CMC\000CMOVA16rm\000CMOVA16rr\000CMOVA"
+ "32rm\000CMOVA32rr\000CMOVA64rm\000CMOVA64rr\000CMOVAE16rm\000CMOVAE16rr"
+ "\000CMOVAE32rm\000CMOVAE32rr\000CMOVAE64rm\000CMOVAE64rr\000CMOVB16rm\000"
+ "CMOVB16rr\000CMOVB32rm\000CMOVB32rr\000CMOVB64rm\000CMOVB64rr\000CMOVBE"
+ "16rm\000CMOVBE16rr\000CMOVBE32rm\000CMOVBE32rr\000CMOVBE64rm\000CMOVBE6"
+ "4rr\000CMOVBE_F\000CMOVBE_Fp32\000CMOVBE_Fp64\000CMOVBE_Fp80\000CMOVB_F"
+ "\000CMOVB_Fp32\000CMOVB_Fp64\000CMOVB_Fp80\000CMOVE16rm\000CMOVE16rr\000"
+ "CMOVE32rm\000CMOVE32rr\000CMOVE64rm\000CMOVE64rr\000CMOVE_F\000CMOVE_Fp"
+ "32\000CMOVE_Fp64\000CMOVE_Fp80\000CMOVG16rm\000CMOVG16rr\000CMOVG32rm\000"
+ "CMOVG32rr\000CMOVG64rm\000CMOVG64rr\000CMOVGE16rm\000CMOVGE16rr\000CMOV"
+ "GE32rm\000CMOVGE32rr\000CMOVGE64rm\000CMOVGE64rr\000CMOVL16rm\000CMOVL1"
+ "6rr\000CMOVL32rm\000CMOVL32rr\000CMOVL64rm\000CMOVL64rr\000CMOVLE16rm\000"
+ "CMOVLE16rr\000CMOVLE32rm\000CMOVLE32rr\000CMOVLE64rm\000CMOVLE64rr\000C"
+ "MOVNBE_F\000CMOVNBE_Fp32\000CMOVNBE_Fp64\000CMOVNBE_Fp80\000CMOVNB_F\000"
+ "CMOVNB_Fp32\000CMOVNB_Fp64\000CMOVNB_Fp80\000CMOVNE16rm\000CMOVNE16rr\000"
+ "CMOVNE32rm\000CMOVNE32rr\000CMOVNE64rm\000CMOVNE64rr\000CMOVNE_F\000CMO"
+ "VNE_Fp32\000CMOVNE_Fp64\000CMOVNE_Fp80\000CMOVNO16rm\000CMOVNO16rr\000C"
+ "MOVNO32rm\000CMOVNO32rr\000CMOVNO64rm\000CMOVNO64rr\000CMOVNP16rm\000CM"
+ "OVNP16rr\000CMOVNP32rm\000CMOVNP32rr\000CMOVNP64rm\000CMOVNP64rr\000CMO"
+ "VNP_F\000CMOVNP_Fp32\000CMOVNP_Fp64\000CMOVNP_Fp80\000CMOVNS16rm\000CMO"
+ "VNS16rr\000CMOVNS32rm\000CMOVNS32rr\000CMOVNS64rm\000CMOVNS64rr\000CMOV"
+ "O16rm\000CMOVO16rr\000CMOVO32rm\000CMOVO32rr\000CMOVO64rm\000CMOVO64rr\000"
+ "CMOVP16rm\000CMOVP16rr\000CMOVP32rm\000CMOVP32rr\000CMOVP64rm\000CMOVP6"
+ "4rr\000CMOVP_F\000CMOVP_Fp32\000CMOVP_Fp64\000CMOVP_Fp80\000CMOVS16rm\000"
+ "CMOVS16rr\000CMOVS32rm\000CMOVS32rr\000CMOVS64rm\000CMOVS64rr\000CMOV_F"
+ "R32\000CMOV_FR64\000CMOV_GR8\000CMOV_V1I64\000CMOV_V2F64\000CMOV_V2I64\000"
+ "CMOV_V4F32\000CMP16i16\000CMP16mi\000CMP16mi8\000CMP16mr\000CMP16mrmrr\000"
+ "CMP16ri\000CMP16ri8\000CMP16rm\000CMP16rr\000CMP32i32\000CMP32mi\000CMP"
+ "32mi8\000CMP32mr\000CMP32mrmrr\000CMP32ri\000CMP32ri8\000CMP32rm\000CMP"
+ "32rr\000CMP64i32\000CMP64mi32\000CMP64mi8\000CMP64mr\000CMP64mrmrr\000C"
+ "MP64ri32\000CMP64ri8\000CMP64rm\000CMP64rr\000CMP8i8\000CMP8mi\000CMP8m"
+ "r\000CMP8mrmrr\000CMP8ri\000CMP8rm\000CMP8rr\000CMPPDrmi\000CMPPDrri\000"
+ "CMPPSrmi\000CMPPSrri\000CMPS16\000CMPS32\000CMPS64\000CMPS8\000CMPSDrm\000"
+ "CMPSDrr\000CMPSSrm\000CMPSSrr\000CMPXCHG16B\000CMPXCHG16rm\000CMPXCHG16"
+ "rr\000CMPXCHG32rm\000CMPXCHG32rr\000CMPXCHG64rm\000CMPXCHG64rr\000CMPXC"
+ "HG8B\000CMPXCHG8rm\000CMPXCHG8rr\000COMISDrm\000COMISDrr\000COMISSrm\000"
+ "COMISSrr\000COMP_FST0r\000COM_FIPr\000COM_FIr\000COM_FST0r\000COS_F\000"
+ "COS_Fp32\000COS_Fp64\000COS_Fp80\000CPUID\000CQO\000CRC32m16\000CRC32m3"
+ "2\000CRC32m8\000CRC32r16\000CRC32r32\000CRC32r8\000CRC64m64\000CRC64r64"
+ "\000CS_PREFIX\000CVTDQ2PDrm\000CVTDQ2PDrr\000CVTDQ2PSrm\000CVTDQ2PSrr\000"
+ "CVTPD2DQrm\000CVTPD2DQrr\000CVTPD2PSrm\000CVTPD2PSrr\000CVTPS2DQrm\000C"
+ "VTPS2DQrr\000CVTPS2PDrm\000CVTPS2PDrr\000CVTSD2SI64rm\000CVTSD2SI64rr\000"
+ "CVTSD2SSrm\000CVTSD2SSrr\000CVTSI2SD64rm\000CVTSI2SD64rr\000CVTSI2SDrm\000"
+ "CVTSI2SDrr\000CVTSI2SS64rm\000CVTSI2SS64rr\000CVTSI2SSrm\000CVTSI2SSrr\000"
+ "CVTSS2SDrm\000CVTSS2SDrr\000CVTSS2SI64rm\000CVTSS2SI64rr\000CVTSS2SIrm\000"
+ "CVTSS2SIrr\000CVTTPS2DQrm\000CVTTPS2DQrr\000CVTTSD2SI64rm\000CVTTSD2SI6"
+ "4rr\000CVTTSD2SIrm\000CVTTSD2SIrr\000CVTTSS2SI64rm\000CVTTSS2SI64rr\000"
+ "CVTTSS2SIrm\000CVTTSS2SIrr\000CWD\000CWDE\000DEC16m\000DEC16r\000DEC32m"
+ "\000DEC32r\000DEC64_16m\000DEC64_16r\000DEC64_32m\000DEC64_32r\000DEC64"
+ "m\000DEC64r\000DEC8m\000DEC8r\000DIV16m\000DIV16r\000DIV32m\000DIV32r\000"
+ "DIV64m\000DIV64r\000DIV8m\000DIV8r\000DIVPDrm\000DIVPDrr\000DIVPSrm\000"
+ "DIVPSrr\000DIVR_F32m\000DIVR_F64m\000DIVR_FI16m\000DIVR_FI32m\000DIVR_F"
+ "PrST0\000DIVR_FST0r\000DIVR_Fp32m\000DIVR_Fp64m\000DIVR_Fp64m32\000DIVR"
+ "_Fp80m32\000DIVR_Fp80m64\000DIVR_FpI16m32\000DIVR_FpI16m64\000DIVR_FpI1"
+ "6m80\000DIVR_FpI32m32\000DIVR_FpI32m64\000DIVR_FpI32m80\000DIVR_FrST0\000"
+ "DIVSDrm\000DIVSDrm_Int\000DIVSDrr\000DIVSDrr_Int\000DIVSSrm\000DIVSSrm_"
+ "Int\000DIVSSrr\000DIVSSrr_Int\000DIV_F32m\000DIV_F64m\000DIV_FI16m\000D"
+ "IV_FI32m\000DIV_FPrST0\000DIV_FST0r\000DIV_Fp32\000DIV_Fp32m\000DIV_Fp6"
+ "4\000DIV_Fp64m\000DIV_Fp64m32\000DIV_Fp80\000DIV_Fp80m32\000DIV_Fp80m64"
+ "\000DIV_FpI16m32\000DIV_FpI16m64\000DIV_FpI16m80\000DIV_FpI32m32\000DIV"
+ "_FpI32m64\000DIV_FpI32m80\000DIV_FrST0\000DPPDrmi\000DPPDrri\000DPPSrmi"
+ "\000DPPSrri\000DS_PREFIX\000EH_RETURN\000EH_RETURN64\000ENTER\000ES_PRE"
+ "FIX\000EXTRACTPSmr\000EXTRACTPSrr\000F2XM1\000FARCALL16i\000FARCALL16m\000"
+ "FARCALL32i\000FARCALL32m\000FARCALL64\000FARJMP16i\000FARJMP16m\000FARJ"
+ "MP32i\000FARJMP32m\000FARJMP64\000FBLDm\000FBSTPm\000FCOM32m\000FCOM64m"
+ "\000FCOMP32m\000FCOMP64m\000FCOMPP\000FDECSTP\000FFREE\000FICOM16m\000F"
+ "ICOM32m\000FICOMP16m\000FICOMP32m\000FINCSTP\000FLDCW16m\000FLDENVm\000"
+ "FLDL2E\000FLDL2T\000FLDLG2\000FLDLN2\000FLDPI\000FNCLEX\000FNINIT\000FN"
+ "OP\000FNSTCW16m\000FNSTSW8r\000FNSTSWm\000FP32_TO_INT16_IN_MEM\000FP32_"
+ "TO_INT32_IN_MEM\000FP32_TO_INT64_IN_MEM\000FP64_TO_INT16_IN_MEM\000FP64"
+ "_TO_INT32_IN_MEM\000FP64_TO_INT64_IN_MEM\000FP80_TO_INT16_IN_MEM\000FP8"
+ "0_TO_INT32_IN_MEM\000FP80_TO_INT64_IN_MEM\000FPATAN\000FPREM\000FPREM1\000"
+ "FPTAN\000FP_REG_KILL\000FRNDINT\000FRSTORm\000FSAVEm\000FSCALE\000FSINC"
+ "OS\000FSTENVm\000FS_MOV32rm\000FS_PREFIX\000FXAM\000FXRSTOR\000FXSAVE\000"
+ "FXTRACT\000FYL2X\000FYL2XP1\000FpGET_ST0_32\000FpGET_ST0_64\000FpGET_ST"
+ "0_80\000FpGET_ST1_32\000FpGET_ST1_64\000FpGET_ST1_80\000FpSET_ST0_32\000"
+ "FpSET_ST0_64\000FpSET_ST0_80\000FpSET_ST1_32\000FpSET_ST1_64\000FpSET_S"
+ "T1_80\000FsANDNPDrm\000FsANDNPDrr\000FsANDNPSrm\000FsANDNPSrr\000FsANDP"
+ "Drm\000FsANDPDrr\000FsANDPSrm\000FsANDPSrr\000FsFLD0SD\000FsFLD0SS\000F"
+ "sMOVAPDrm\000FsMOVAPDrr\000FsMOVAPSrm\000FsMOVAPSrr\000FsORPDrm\000FsOR"
+ "PDrr\000FsORPSrm\000FsORPSrr\000FsXORPDrm\000FsXORPDrr\000FsXORPSrm\000"
+ "FsXORPSrr\000GS_MOV32rm\000GS_PREFIX\000HADDPDrm\000HADDPDrr\000HADDPSr"
+ "m\000HADDPSrr\000HLT\000HSUBPDrm\000HSUBPDrr\000HSUBPSrm\000HSUBPSrr\000"
+ "IDIV16m\000IDIV16r\000IDIV32m\000IDIV32r\000IDIV64m\000IDIV64r\000IDIV8"
+ "m\000IDIV8r\000ILD_F16m\000ILD_F32m\000ILD_F64m\000ILD_Fp16m32\000ILD_F"
+ "p16m64\000ILD_Fp16m80\000ILD_Fp32m32\000ILD_Fp32m64\000ILD_Fp32m80\000I"
+ "LD_Fp64m32\000ILD_Fp64m64\000ILD_Fp64m80\000IMUL16m\000IMUL16r\000IMUL1"
+ "6rm\000IMUL16rmi\000IMUL16rmi8\000IMUL16rr\000IMUL16rri\000IMUL16rri8\000"
+ "IMUL32m\000IMUL32r\000IMUL32rm\000IMUL32rmi\000IMUL32rmi8\000IMUL32rr\000"
+ "IMUL32rri\000IMUL32rri8\000IMUL64m\000IMUL64r\000IMUL64rm\000IMUL64rmi3"
+ "2\000IMUL64rmi8\000IMUL64rr\000IMUL64rri32\000IMUL64rri8\000IMUL8m\000I"
+ "MUL8r\000IN16\000IN16ri\000IN16rr\000IN32\000IN32ri\000IN32rr\000IN8\000"
+ "IN8ri\000IN8rr\000INC16m\000INC16r\000INC32m\000INC32r\000INC64_16m\000"
+ "INC64_16r\000INC64_32m\000INC64_32r\000INC64m\000INC64r\000INC8m\000INC"
+ "8r\000INSERTPSrm\000INSERTPSrr\000INT\000INT3\000INVD\000INVEPT\000INVL"
+ "PG\000INVVPID\000IRET16\000IRET32\000IRET64\000ISTT_FP16m\000ISTT_FP32m"
+ "\000ISTT_FP64m\000ISTT_Fp16m32\000ISTT_Fp16m64\000ISTT_Fp16m80\000ISTT_"
+ "Fp32m32\000ISTT_Fp32m64\000ISTT_Fp32m80\000ISTT_Fp64m32\000ISTT_Fp64m64"
+ "\000ISTT_Fp64m80\000IST_F16m\000IST_F32m\000IST_FP16m\000IST_FP32m\000I"
+ "ST_FP64m\000IST_Fp16m32\000IST_Fp16m64\000IST_Fp16m80\000IST_Fp32m32\000"
+ "IST_Fp32m64\000IST_Fp32m80\000IST_Fp64m32\000IST_Fp64m64\000IST_Fp64m80"
+ "\000Int_CMPSDrm\000Int_CMPSDrr\000Int_CMPSSrm\000Int_CMPSSrr\000Int_COM"
+ "ISDrm\000Int_COMISDrr\000Int_COMISSrm\000Int_COMISSrr\000Int_CVTDQ2PDrm"
+ "\000Int_CVTDQ2PDrr\000Int_CVTDQ2PSrm\000Int_CVTDQ2PSrr\000Int_CVTPD2DQr"
+ "m\000Int_CVTPD2DQrr\000Int_CVTPD2PIrm\000Int_CVTPD2PIrr\000Int_CVTPD2PS"
+ "rm\000Int_CVTPD2PSrr\000Int_CVTPI2PDrm\000Int_CVTPI2PDrr\000Int_CVTPI2P"
+ "Srm\000Int_CVTPI2PSrr\000Int_CVTPS2DQrm\000Int_CVTPS2DQrr\000Int_CVTPS2"
+ "PDrm\000Int_CVTPS2PDrr\000Int_CVTPS2PIrm\000Int_CVTPS2PIrr\000Int_CVTSD"
+ "2SI64rm\000Int_CVTSD2SI64rr\000Int_CVTSD2SIrm\000Int_CVTSD2SIrr\000Int_"
+ "CVTSD2SSrm\000Int_CVTSD2SSrr\000Int_CVTSI2SD64rm\000Int_CVTSI2SD64rr\000"
+ "Int_CVTSI2SDrm\000Int_CVTSI2SDrr\000Int_CVTSI2SS64rm\000Int_CVTSI2SS64r"
+ "r\000Int_CVTSI2SSrm\000Int_CVTSI2SSrr\000Int_CVTSS2SDrm\000Int_CVTSS2SD"
+ "rr\000Int_CVTSS2SI64rm\000Int_CVTSS2SI64rr\000Int_CVTSS2SIrm\000Int_CVT"
+ "SS2SIrr\000Int_CVTTPD2DQrm\000Int_CVTTPD2DQrr\000Int_CVTTPD2PIrm\000Int"
+ "_CVTTPD2PIrr\000Int_CVTTPS2DQrm\000Int_CVTTPS2DQrr\000Int_CVTTPS2PIrm\000"
+ "Int_CVTTPS2PIrr\000Int_CVTTSD2SI64rm\000Int_CVTTSD2SI64rr\000Int_CVTTSD"
+ "2SIrm\000Int_CVTTSD2SIrr\000Int_CVTTSS2SI64rm\000Int_CVTTSS2SI64rr\000I"
+ "nt_CVTTSS2SIrm\000Int_CVTTSS2SIrr\000Int_UCOMISDrm\000Int_UCOMISDrr\000"
+ "Int_UCOMISSrm\000Int_UCOMISSrr\000JAE_1\000JAE_4\000JA_1\000JA_4\000JBE"
+ "_1\000JBE_4\000JB_1\000JB_4\000JCXZ8\000JE_1\000JE_4\000JGE_1\000JGE_4\000"
+ "JG_1\000JG_4\000JLE_1\000JLE_4\000JL_1\000JL_4\000JMP32m\000JMP32r\000J"
+ "MP64m\000JMP64pcrel32\000JMP64r\000JMP_1\000JMP_4\000JNE_1\000JNE_4\000"
+ "JNO_1\000JNO_4\000JNP_1\000JNP_4\000JNS_1\000JNS_4\000JO_1\000JO_4\000J"
+ "P_1\000JP_4\000JS_1\000JS_4\000LAHF\000LAR16rm\000LAR16rr\000LAR32rm\000"
+ "LAR32rr\000LAR64rm\000LAR64rr\000LCMPXCHG16\000LCMPXCHG32\000LCMPXCHG64"
+ "\000LCMPXCHG8\000LCMPXCHG8B\000LDDQUrm\000LDMXCSR\000LDS16rm\000LDS32rm"
+ "\000LD_F0\000LD_F1\000LD_F32m\000LD_F64m\000LD_F80m\000LD_Fp032\000LD_F"
+ "p064\000LD_Fp080\000LD_Fp132\000LD_Fp164\000LD_Fp180\000LD_Fp32m\000LD_"
+ "Fp32m64\000LD_Fp32m80\000LD_Fp64m\000LD_Fp64m80\000LD_Fp80m\000LD_Frr\000"
+ "LEA16r\000LEA32r\000LEA64_32r\000LEA64r\000LEAVE\000LEAVE64\000LES16rm\000"
+ "LES32rm\000LFENCE\000LFS16rm\000LFS32rm\000LFS64rm\000LGDTm\000LGS16rm\000"
+ "LGS32rm\000LGS64rm\000LIDTm\000LLDT16m\000LLDT16r\000LMSW16m\000LMSW16r"
+ "\000LOCK_ADD16mi\000LOCK_ADD16mi8\000LOCK_ADD16mr\000LOCK_ADD32mi\000LO"
+ "CK_ADD32mi8\000LOCK_ADD32mr\000LOCK_ADD64mi32\000LOCK_ADD64mi8\000LOCK_"
+ "ADD64mr\000LOCK_ADD8mi\000LOCK_ADD8mr\000LOCK_DEC16m\000LOCK_DEC32m\000"
+ "LOCK_DEC64m\000LOCK_DEC8m\000LOCK_INC16m\000LOCK_INC32m\000LOCK_INC64m\000"
+ "LOCK_INC8m\000LOCK_PREFIX\000LOCK_SUB16mi\000LOCK_SUB16mi8\000LOCK_SUB1"
+ "6mr\000LOCK_SUB32mi\000LOCK_SUB32mi8\000LOCK_SUB32mr\000LOCK_SUB64mi32\000"
+ "LOCK_SUB64mi8\000LOCK_SUB64mr\000LOCK_SUB8mi\000LOCK_SUB8mr\000LODSB\000"
+ "LODSD\000LODSQ\000LODSW\000LOOP\000LOOPE\000LOOPNE\000LRET\000LRETI\000"
+ "LSL16rm\000LSL16rr\000LSL32rm\000LSL32rr\000LSL64rm\000LSL64rr\000LSS16"
+ "rm\000LSS32rm\000LSS64rm\000LTRm\000LTRr\000LXADD16\000LXADD32\000LXADD"
+ "64\000LXADD8\000MASKMOVDQU\000MASKMOVDQU64\000MAXPDrm\000MAXPDrm_Int\000"
+ "MAXPDrr\000MAXPDrr_Int\000MAXPSrm\000MAXPSrm_Int\000MAXPSrr\000MAXPSrr_"
+ "Int\000MAXSDrm\000MAXSDrm_Int\000MAXSDrr\000MAXSDrr_Int\000MAXSSrm\000M"
+ "AXSSrm_Int\000MAXSSrr\000MAXSSrr_Int\000MFENCE\000MINPDrm\000MINPDrm_In"
+ "t\000MINPDrr\000MINPDrr_Int\000MINPSrm\000MINPSrm_Int\000MINPSrr\000MIN"
+ "PSrr_Int\000MINSDrm\000MINSDrm_Int\000MINSDrr\000MINSDrr_Int\000MINSSrm"
+ "\000MINSSrm_Int\000MINSSrr\000MINSSrr_Int\000MMX_CVTPD2PIrm\000MMX_CVTP"
+ "D2PIrr\000MMX_CVTPI2PDrm\000MMX_CVTPI2PDrr\000MMX_CVTPI2PSrm\000MMX_CVT"
+ "PI2PSrr\000MMX_CVTPS2PIrm\000MMX_CVTPS2PIrr\000MMX_CVTTPD2PIrm\000MMX_C"
+ "VTTPD2PIrr\000MMX_CVTTPS2PIrm\000MMX_CVTTPS2PIrr\000MMX_EMMS\000MMX_FEM"
+ "MS\000MMX_MASKMOVQ\000MMX_MASKMOVQ64\000MMX_MOVD64from64rr\000MMX_MOVD6"
+ "4grr\000MMX_MOVD64mr\000MMX_MOVD64rm\000MMX_MOVD64rr\000MMX_MOVD64rrv16"
+ "4\000MMX_MOVD64to64rr\000MMX_MOVDQ2Qrr\000MMX_MOVNTQmr\000MMX_MOVQ2DQrr"
+ "\000MMX_MOVQ2FR64rr\000MMX_MOVQ64gmr\000MMX_MOVQ64mr\000MMX_MOVQ64rm\000"
+ "MMX_MOVQ64rr\000MMX_MOVZDI2PDIrm\000MMX_MOVZDI2PDIrr\000MMX_PACKSSDWrm\000"
+ "MMX_PACKSSDWrr\000MMX_PACKSSWBrm\000MMX_PACKSSWBrr\000MMX_PACKUSWBrm\000"
+ "MMX_PACKUSWBrr\000MMX_PADDBrm\000MMX_PADDBrr\000MMX_PADDDrm\000MMX_PADD"
+ "Drr\000MMX_PADDQrm\000MMX_PADDQrr\000MMX_PADDSBrm\000MMX_PADDSBrr\000MM"
+ "X_PADDSWrm\000MMX_PADDSWrr\000MMX_PADDUSBrm\000MMX_PADDUSBrr\000MMX_PAD"
+ "DUSWrm\000MMX_PADDUSWrr\000MMX_PADDWrm\000MMX_PADDWrr\000MMX_PANDNrm\000"
+ "MMX_PANDNrr\000MMX_PANDrm\000MMX_PANDrr\000MMX_PAVGBrm\000MMX_PAVGBrr\000"
+ "MMX_PAVGWrm\000MMX_PAVGWrr\000MMX_PCMPEQBrm\000MMX_PCMPEQBrr\000MMX_PCM"
+ "PEQDrm\000MMX_PCMPEQDrr\000MMX_PCMPEQWrm\000MMX_PCMPEQWrr\000MMX_PCMPGT"
+ "Brm\000MMX_PCMPGTBrr\000MMX_PCMPGTDrm\000MMX_PCMPGTDrr\000MMX_PCMPGTWrm"
+ "\000MMX_PCMPGTWrr\000MMX_PEXTRWri\000MMX_PINSRWrmi\000MMX_PINSRWrri\000"
+ "MMX_PMADDWDrm\000MMX_PMADDWDrr\000MMX_PMAXSWrm\000MMX_PMAXSWrr\000MMX_P"
+ "MAXUBrm\000MMX_PMAXUBrr\000MMX_PMINSWrm\000MMX_PMINSWrr\000MMX_PMINUBrm"
+ "\000MMX_PMINUBrr\000MMX_PMOVMSKBrr\000MMX_PMULHUWrm\000MMX_PMULHUWrr\000"
+ "MMX_PMULHWrm\000MMX_PMULHWrr\000MMX_PMULLWrm\000MMX_PMULLWrr\000MMX_PMU"
+ "LUDQrm\000MMX_PMULUDQrr\000MMX_PORrm\000MMX_PORrr\000MMX_PSADBWrm\000MM"
+ "X_PSADBWrr\000MMX_PSHUFWmi\000MMX_PSHUFWri\000MMX_PSLLDri\000MMX_PSLLDr"
+ "m\000MMX_PSLLDrr\000MMX_PSLLQri\000MMX_PSLLQrm\000MMX_PSLLQrr\000MMX_PS"
+ "LLWri\000MMX_PSLLWrm\000MMX_PSLLWrr\000MMX_PSRADri\000MMX_PSRADrm\000MM"
+ "X_PSRADrr\000MMX_PSRAWri\000MMX_PSRAWrm\000MMX_PSRAWrr\000MMX_PSRLDri\000"
+ "MMX_PSRLDrm\000MMX_PSRLDrr\000MMX_PSRLQri\000MMX_PSRLQrm\000MMX_PSRLQrr"
+ "\000MMX_PSRLWri\000MMX_PSRLWrm\000MMX_PSRLWrr\000MMX_PSUBBrm\000MMX_PSU"
+ "BBrr\000MMX_PSUBDrm\000MMX_PSUBDrr\000MMX_PSUBQrm\000MMX_PSUBQrr\000MMX"
+ "_PSUBSBrm\000MMX_PSUBSBrr\000MMX_PSUBSWrm\000MMX_PSUBSWrr\000MMX_PSUBUS"
+ "Brm\000MMX_PSUBUSBrr\000MMX_PSUBUSWrm\000MMX_PSUBUSWrr\000MMX_PSUBWrm\000"
+ "MMX_PSUBWrr\000MMX_PUNPCKHBWrm\000MMX_PUNPCKHBWrr\000MMX_PUNPCKHDQrm\000"
+ "MMX_PUNPCKHDQrr\000MMX_PUNPCKHWDrm\000MMX_PUNPCKHWDrr\000MMX_PUNPCKLBWr"
+ "m\000MMX_PUNPCKLBWrr\000MMX_PUNPCKLDQrm\000MMX_PUNPCKLDQrr\000MMX_PUNPC"
+ "KLWDrm\000MMX_PUNPCKLWDrr\000MMX_PXORrm\000MMX_PXORrr\000MMX_V_SET0\000"
+ "MMX_V_SETALLONES\000MONITOR\000MOV16ao16\000MOV16mi\000MOV16mr\000MOV16"
+ "ms\000MOV16o16a\000MOV16r0\000MOV16ri\000MOV16rm\000MOV16rr\000MOV16rr_"
+ "REV\000MOV16rs\000MOV16sm\000MOV16sr\000MOV32ao32\000MOV32cr\000MOV32dr"
+ "\000MOV32mi\000MOV32mr\000MOV32o32a\000MOV32r0\000MOV32rc\000MOV32rd\000"
+ "MOV32ri\000MOV32rm\000MOV32rr\000MOV32rr_REV\000MOV64FSrm\000MOV64GSrm\000"
+ "MOV64ao64\000MOV64ao8\000MOV64cr\000MOV64dr\000MOV64mi32\000MOV64mr\000"
+ "MOV64ms\000MOV64o64a\000MOV64o8a\000MOV64r0\000MOV64rc\000MOV64rd\000MO"
+ "V64ri\000MOV64ri32\000MOV64ri64i32\000MOV64rm\000MOV64rr\000MOV64rr_REV"
+ "\000MOV64rs\000MOV64sm\000MOV64sr\000MOV64toPQIrr\000MOV64toSDrm\000MOV"
+ "64toSDrr\000MOV8ao8\000MOV8mi\000MOV8mr\000MOV8mr_NOREX\000MOV8o8a\000M"
+ "OV8r0\000MOV8ri\000MOV8rm\000MOV8rm_NOREX\000MOV8rr\000MOV8rr_NOREX\000"
+ "MOV8rr_REV\000MOVAPDmr\000MOVAPDrm\000MOVAPDrr\000MOVAPSmr\000MOVAPSrm\000"
+ "MOVAPSrr\000MOVDDUPrm\000MOVDDUPrr\000MOVDI2PDIrm\000MOVDI2PDIrr\000MOV"
+ "DI2SSrm\000MOVDI2SSrr\000MOVDQAmr\000MOVDQArm\000MOVDQArr\000MOVDQUmr\000"
+ "MOVDQUmr_Int\000MOVDQUrm\000MOVDQUrm_Int\000MOVHLPSrr\000MOVHPDmr\000MO"
+ "VHPDrm\000MOVHPSmr\000MOVHPSrm\000MOVLHPSrr\000MOVLPDmr\000MOVLPDrm\000"
+ "MOVLPDrr\000MOVLPSmr\000MOVLPSrm\000MOVLPSrr\000MOVLQ128mr\000MOVLSD2PD"
+ "rr\000MOVLSS2PSrr\000MOVMSKPDrr\000MOVMSKPSrr\000MOVNTDQArm\000MOVNTDQm"
+ "r\000MOVNTImr\000MOVNTPDmr\000MOVNTPSmr\000MOVPC32r\000MOVPD2SDmr\000MO"
+ "VPD2SDrr\000MOVPDI2DImr\000MOVPDI2DIrr\000MOVPQI2QImr\000MOVPQIto64rr\000"
+ "MOVPS2SSmr\000MOVPS2SSrr\000MOVQI2PQIrm\000MOVQxrxr\000MOVSB\000MOVSD\000"
+ "MOVSD2PDrm\000MOVSD2PDrr\000MOVSDmr\000MOVSDrm\000MOVSDrr\000MOVSDto64m"
+ "r\000MOVSDto64rr\000MOVSHDUPrm\000MOVSHDUPrr\000MOVSLDUPrm\000MOVSLDUPr"
+ "r\000MOVSS2DImr\000MOVSS2DIrr\000MOVSS2PSrm\000MOVSS2PSrr\000MOVSSmr\000"
+ "MOVSSrm\000MOVSSrr\000MOVSW\000MOVSX16rm8\000MOVSX16rm8W\000MOVSX16rr8\000"
+ "MOVSX16rr8W\000MOVSX32rm16\000MOVSX32rm8\000MOVSX32rr16\000MOVSX32rr8\000"
+ "MOVSX64rm16\000MOVSX64rm32\000MOVSX64rm8\000MOVSX64rr16\000MOVSX64rr32\000"
+ "MOVSX64rr8\000MOVUPDmr\000MOVUPDmr_Int\000MOVUPDrm\000MOVUPDrm_Int\000M"
+ "OVUPDrr\000MOVUPSmr\000MOVUPSmr_Int\000MOVUPSrm\000MOVUPSrm_Int\000MOVU"
+ "PSrr\000MOVZDI2PDIrm\000MOVZDI2PDIrr\000MOVZPQILo2PQIrm\000MOVZPQILo2PQ"
+ "Irr\000MOVZQI2PQIrm\000MOVZQI2PQIrr\000MOVZSD2PDrm\000MOVZSS2PSrm\000MO"
+ "VZX16rm8\000MOVZX16rm8W\000MOVZX16rr8\000MOVZX16rr8W\000MOVZX32_NOREXrm"
+ "8\000MOVZX32_NOREXrr8\000MOVZX32rm16\000MOVZX32rm8\000MOVZX32rr16\000MO"
+ "VZX32rr8\000MOVZX64rm16\000MOVZX64rm16_Q\000MOVZX64rm32\000MOVZX64rm8\000"
+ "MOVZX64rm8_Q\000MOVZX64rr16\000MOVZX64rr16_Q\000MOVZX64rr32\000MOVZX64r"
+ "r8\000MOVZX64rr8_Q\000MOV_Fp3232\000MOV_Fp3264\000MOV_Fp3280\000MOV_Fp6"
+ "432\000MOV_Fp6464\000MOV_Fp6480\000MOV_Fp8032\000MOV_Fp8064\000MOV_Fp80"
+ "80\000MPSADBWrmi\000MPSADBWrri\000MUL16m\000MUL16r\000MUL32m\000MUL32r\000"
+ "MUL64m\000MUL64r\000MUL8m\000MUL8r\000MULPDrm\000MULPDrr\000MULPSrm\000"
+ "MULPSrr\000MULSDrm\000MULSDrm_Int\000MULSDrr\000MULSDrr_Int\000MULSSrm\000"
+ "MULSSrm_Int\000MULSSrr\000MULSSrr_Int\000MUL_F32m\000MUL_F64m\000MUL_FI"
+ "16m\000MUL_FI32m\000MUL_FPrST0\000MUL_FST0r\000MUL_Fp32\000MUL_Fp32m\000"
+ "MUL_Fp64\000MUL_Fp64m\000MUL_Fp64m32\000MUL_Fp80\000MUL_Fp80m32\000MUL_"
+ "Fp80m64\000MUL_FpI16m32\000MUL_FpI16m64\000MUL_FpI16m80\000MUL_FpI32m32"
+ "\000MUL_FpI32m64\000MUL_FpI32m80\000MUL_FrST0\000MWAIT\000NEG16m\000NEG"
+ "16r\000NEG32m\000NEG32r\000NEG64m\000NEG64r\000NEG8m\000NEG8r\000NOOP\000"
+ "NOOPL\000NOOPW\000NOT16m\000NOT16r\000NOT32m\000NOT32r\000NOT64m\000NOT"
+ "64r\000NOT8m\000NOT8r\000OR16i16\000OR16mi\000OR16mi8\000OR16mr\000OR16"
+ "ri\000OR16ri8\000OR16rm\000OR16rr\000OR16rr_REV\000OR32i32\000OR32mi\000"
+ "OR32mi8\000OR32mr\000OR32ri\000OR32ri8\000OR32rm\000OR32rr\000OR32rr_RE"
+ "V\000OR64i32\000OR64mi32\000OR64mi8\000OR64mr\000OR64ri32\000OR64ri8\000"
+ "OR64rm\000OR64rr\000OR64rr_REV\000OR8i8\000OR8mi\000OR8mr\000OR8ri\000O"
+ "R8rm\000OR8rr\000OR8rr_REV\000ORPDrm\000ORPDrr\000ORPSrm\000ORPSrr\000O"
+ "UT16ir\000OUT16rr\000OUT32ir\000OUT32rr\000OUT8ir\000OUT8rr\000OUTSB\000"
+ "OUTSD\000OUTSW\000PABSBrm128\000PABSBrm64\000PABSBrr128\000PABSBrr64\000"
+ "PABSDrm128\000PABSDrm64\000PABSDrr128\000PABSDrr64\000PABSWrm128\000PAB"
+ "SWrm64\000PABSWrr128\000PABSWrr64\000PACKSSDWrm\000PACKSSDWrr\000PACKSS"
+ "WBrm\000PACKSSWBrr\000PACKUSDWrm\000PACKUSDWrr\000PACKUSWBrm\000PACKUSW"
+ "Brr\000PADDBrm\000PADDBrr\000PADDDrm\000PADDDrr\000PADDQrm\000PADDQrr\000"
+ "PADDSBrm\000PADDSBrr\000PADDSWrm\000PADDSWrr\000PADDUSBrm\000PADDUSBrr\000"
+ "PADDUSWrm\000PADDUSWrr\000PADDWrm\000PADDWrr\000PALIGNR128rm\000PALIGNR"
+ "128rr\000PALIGNR64rm\000PALIGNR64rr\000PANDNrm\000PANDNrr\000PANDrm\000"
+ "PANDrr\000PAVGBrm\000PAVGBrr\000PAVGWrm\000PAVGWrr\000PBLENDVBrm0\000PB"
+ "LENDVBrr0\000PBLENDWrmi\000PBLENDWrri\000PCMPEQBrm\000PCMPEQBrr\000PCMP"
+ "EQDrm\000PCMPEQDrr\000PCMPEQQrm\000PCMPEQQrr\000PCMPEQWrm\000PCMPEQWrr\000"
+ "PCMPESTRIArm\000PCMPESTRIArr\000PCMPESTRICrm\000PCMPESTRICrr\000PCMPEST"
+ "RIOrm\000PCMPESTRIOrr\000PCMPESTRISrm\000PCMPESTRISrr\000PCMPESTRIZrm\000"
+ "PCMPESTRIZrr\000PCMPESTRIrm\000PCMPESTRIrr\000PCMPESTRM128MEM\000PCMPES"
+ "TRM128REG\000PCMPESTRM128rm\000PCMPESTRM128rr\000PCMPGTBrm\000PCMPGTBrr"
+ "\000PCMPGTDrm\000PCMPGTDrr\000PCMPGTQrm\000PCMPGTQrr\000PCMPGTWrm\000PC"
+ "MPGTWrr\000PCMPISTRIArm\000PCMPISTRIArr\000PCMPISTRICrm\000PCMPISTRICrr"
+ "\000PCMPISTRIOrm\000PCMPISTRIOrr\000PCMPISTRISrm\000PCMPISTRISrr\000PCM"
+ "PISTRIZrm\000PCMPISTRIZrr\000PCMPISTRIrm\000PCMPISTRIrr\000PCMPISTRM128"
+ "MEM\000PCMPISTRM128REG\000PCMPISTRM128rm\000PCMPISTRM128rr\000PEXTRBmr\000"
+ "PEXTRBrr\000PEXTRDmr\000PEXTRDrr\000PEXTRQmr\000PEXTRQrr\000PEXTRWmr\000"
+ "PEXTRWri\000PHADDDrm128\000PHADDDrm64\000PHADDDrr128\000PHADDDrr64\000P"
+ "HADDSWrm128\000PHADDSWrm64\000PHADDSWrr128\000PHADDSWrr64\000PHADDWrm12"
+ "8\000PHADDWrm64\000PHADDWrr128\000PHADDWrr64\000PHMINPOSUWrm128\000PHMI"
+ "NPOSUWrr128\000PHSUBDrm128\000PHSUBDrm64\000PHSUBDrr128\000PHSUBDrr64\000"
+ "PHSUBSWrm128\000PHSUBSWrm64\000PHSUBSWrr128\000PHSUBSWrr64\000PHSUBWrm1"
+ "28\000PHSUBWrm64\000PHSUBWrr128\000PHSUBWrr64\000PINSRBrm\000PINSRBrr\000"
+ "PINSRDrm\000PINSRDrr\000PINSRQrm\000PINSRQrr\000PINSRWrmi\000PINSRWrri\000"
+ "PMADDUBSWrm128\000PMADDUBSWrm64\000PMADDUBSWrr128\000PMADDUBSWrr64\000P"
+ "MADDWDrm\000PMADDWDrr\000PMAXSBrm\000PMAXSBrr\000PMAXSDrm\000PMAXSDrr\000"
+ "PMAXSWrm\000PMAXSWrr\000PMAXUBrm\000PMAXUBrr\000PMAXUDrm\000PMAXUDrr\000"
+ "PMAXUWrm\000PMAXUWrr\000PMINSBrm\000PMINSBrr\000PMINSDrm\000PMINSDrr\000"
+ "PMINSWrm\000PMINSWrr\000PMINUBrm\000PMINUBrr\000PMINUDrm\000PMINUDrr\000"
+ "PMINUWrm\000PMINUWrr\000PMOVMSKBrr\000PMOVSXBDrm\000PMOVSXBDrr\000PMOVS"
+ "XBQrm\000PMOVSXBQrr\000PMOVSXBWrm\000PMOVSXBWrr\000PMOVSXDQrm\000PMOVSX"
+ "DQrr\000PMOVSXWDrm\000PMOVSXWDrr\000PMOVSXWQrm\000PMOVSXWQrr\000PMOVZXB"
+ "Drm\000PMOVZXBDrr\000PMOVZXBQrm\000PMOVZXBQrr\000PMOVZXBWrm\000PMOVZXBW"
+ "rr\000PMOVZXDQrm\000PMOVZXDQrr\000PMOVZXWDrm\000PMOVZXWDrr\000PMOVZXWQr"
+ "m\000PMOVZXWQrr\000PMULDQrm\000PMULDQrr\000PMULHRSWrm128\000PMULHRSWrm6"
+ "4\000PMULHRSWrr128\000PMULHRSWrr64\000PMULHUWrm\000PMULHUWrr\000PMULHWr"
+ "m\000PMULHWrr\000PMULLDrm\000PMULLDrm_int\000PMULLDrr\000PMULLDrr_int\000"
+ "PMULLWrm\000PMULLWrr\000PMULUDQrm\000PMULUDQrr\000POP16r\000POP16rmm\000"
+ "POP16rmr\000POP32r\000POP32rmm\000POP32rmr\000POP64r\000POP64rmm\000POP"
+ "64rmr\000POPCNT16rm\000POPCNT16rr\000POPCNT32rm\000POPCNT32rr\000POPCNT"
+ "64rm\000POPCNT64rr\000POPF\000POPFD\000POPFQ\000POPFS16\000POPFS32\000P"
+ "OPFS64\000POPGS16\000POPGS32\000POPGS64\000PORrm\000PORrr\000PREFETCHNT"
+ "A\000PREFETCHT0\000PREFETCHT1\000PREFETCHT2\000PSADBWrm\000PSADBWrr\000"
+ "PSHUFBrm128\000PSHUFBrm64\000PSHUFBrr128\000PSHUFBrr64\000PSHUFDmi\000P"
+ "SHUFDri\000PSHUFHWmi\000PSHUFHWri\000PSHUFLWmi\000PSHUFLWri\000PSIGNBrm"
+ "128\000PSIGNBrm64\000PSIGNBrr128\000PSIGNBrr64\000PSIGNDrm128\000PSIGND"
+ "rm64\000PSIGNDrr128\000PSIGNDrr64\000PSIGNWrm128\000PSIGNWrm64\000PSIGN"
+ "Wrr128\000PSIGNWrr64\000PSLLDQri\000PSLLDri\000PSLLDrm\000PSLLDrr\000PS"
+ "LLQri\000PSLLQrm\000PSLLQrr\000PSLLWri\000PSLLWrm\000PSLLWrr\000PSRADri"
+ "\000PSRADrm\000PSRADrr\000PSRAWri\000PSRAWrm\000PSRAWrr\000PSRLDQri\000"
+ "PSRLDri\000PSRLDrm\000PSRLDrr\000PSRLQri\000PSRLQrm\000PSRLQrr\000PSRLW"
+ "ri\000PSRLWrm\000PSRLWrr\000PSUBBrm\000PSUBBrr\000PSUBDrm\000PSUBDrr\000"
+ "PSUBQrm\000PSUBQrr\000PSUBSBrm\000PSUBSBrr\000PSUBSWrm\000PSUBSWrr\000P"
+ "SUBUSBrm\000PSUBUSBrr\000PSUBUSWrm\000PSUBUSWrr\000PSUBWrm\000PSUBWrr\000"
+ "PTESTrm\000PTESTrr\000PUNPCKHBWrm\000PUNPCKHBWrr\000PUNPCKHDQrm\000PUNP"
+ "CKHDQrr\000PUNPCKHQDQrm\000PUNPCKHQDQrr\000PUNPCKHWDrm\000PUNPCKHWDrr\000"
+ "PUNPCKLBWrm\000PUNPCKLBWrr\000PUNPCKLDQrm\000PUNPCKLDQrr\000PUNPCKLQDQr"
+ "m\000PUNPCKLQDQrr\000PUNPCKLWDrm\000PUNPCKLWDrr\000PUSH16r\000PUSH16rmm"
+ "\000PUSH16rmr\000PUSH32i16\000PUSH32i32\000PUSH32i8\000PUSH32r\000PUSH3"
+ "2rmm\000PUSH32rmr\000PUSH64i16\000PUSH64i32\000PUSH64i8\000PUSH64r\000P"
+ "USH64rmm\000PUSH64rmr\000PUSHF\000PUSHFD\000PUSHFQ64\000PUSHFS16\000PUS"
+ "HFS32\000PUSHFS64\000PUSHGS16\000PUSHGS32\000PUSHGS64\000PXORrm\000PXOR"
+ "rr\000RCL16m1\000RCL16mCL\000RCL16mi\000RCL16r1\000RCL16rCL\000RCL16ri\000"
+ "RCL32m1\000RCL32mCL\000RCL32mi\000RCL32r1\000RCL32rCL\000RCL32ri\000RCL"
+ "64m1\000RCL64mCL\000RCL64mi\000RCL64r1\000RCL64rCL\000RCL64ri\000RCL8m1"
+ "\000RCL8mCL\000RCL8mi\000RCL8r1\000RCL8rCL\000RCL8ri\000RCPPSm\000RCPPS"
+ "m_Int\000RCPPSr\000RCPPSr_Int\000RCPSSm\000RCPSSm_Int\000RCPSSr\000RCPS"
+ "Sr_Int\000RCR16m1\000RCR16mCL\000RCR16mi\000RCR16r1\000RCR16rCL\000RCR1"
+ "6ri\000RCR32m1\000RCR32mCL\000RCR32mi\000RCR32r1\000RCR32rCL\000RCR32ri"
+ "\000RCR64m1\000RCR64mCL\000RCR64mi\000RCR64r1\000RCR64rCL\000RCR64ri\000"
+ "RCR8m1\000RCR8mCL\000RCR8mi\000RCR8r1\000RCR8rCL\000RCR8ri\000RDMSR\000"
+ "RDPMC\000RDTSC\000RDTSCP\000REPNE_PREFIX\000REP_MOVSB\000REP_MOVSD\000R"
+ "EP_MOVSQ\000REP_MOVSW\000REP_PREFIX\000REP_STOSB\000REP_STOSD\000REP_ST"
+ "OSQ\000REP_STOSW\000RET\000RETI\000ROL16m1\000ROL16mCL\000ROL16mi\000RO"
+ "L16r1\000ROL16rCL\000ROL16ri\000ROL32m1\000ROL32mCL\000ROL32mi\000ROL32"
+ "r1\000ROL32rCL\000ROL32ri\000ROL64m1\000ROL64mCL\000ROL64mi\000ROL64r1\000"
+ "ROL64rCL\000ROL64ri\000ROL8m1\000ROL8mCL\000ROL8mi\000ROL8r1\000ROL8rCL"
+ "\000ROL8ri\000ROR16m1\000ROR16mCL\000ROR16mi\000ROR16r1\000ROR16rCL\000"
+ "ROR16ri\000ROR32m1\000ROR32mCL\000ROR32mi\000ROR32r1\000ROR32rCL\000ROR"
+ "32ri\000ROR64m1\000ROR64mCL\000ROR64mi\000ROR64r1\000ROR64rCL\000ROR64r"
+ "i\000ROR8m1\000ROR8mCL\000ROR8mi\000ROR8r1\000ROR8rCL\000ROR8ri\000ROUN"
+ "DPDm_Int\000ROUNDPDr_Int\000ROUNDPSm_Int\000ROUNDPSr_Int\000ROUNDSDm_In"
+ "t\000ROUNDSDr_Int\000ROUNDSSm_Int\000ROUNDSSr_Int\000RSM\000RSQRTPSm\000"
+ "RSQRTPSm_Int\000RSQRTPSr\000RSQRTPSr_Int\000RSQRTSSm\000RSQRTSSm_Int\000"
+ "RSQRTSSr\000RSQRTSSr_Int\000SAHF\000SAR16m1\000SAR16mCL\000SAR16mi\000S"
+ "AR16r1\000SAR16rCL\000SAR16ri\000SAR32m1\000SAR32mCL\000SAR32mi\000SAR3"
+ "2r1\000SAR32rCL\000SAR32ri\000SAR64m1\000SAR64mCL\000SAR64mi\000SAR64r1"
+ "\000SAR64rCL\000SAR64ri\000SAR8m1\000SAR8mCL\000SAR8mi\000SAR8r1\000SAR"
+ "8rCL\000SAR8ri\000SBB16i16\000SBB16mi\000SBB16mi8\000SBB16mr\000SBB16ri"
+ "\000SBB16ri8\000SBB16rm\000SBB16rr\000SBB16rr_REV\000SBB32i32\000SBB32m"
+ "i\000SBB32mi8\000SBB32mr\000SBB32ri\000SBB32ri8\000SBB32rm\000SBB32rr\000"
+ "SBB32rr_REV\000SBB64i32\000SBB64mi32\000SBB64mi8\000SBB64mr\000SBB64ri3"
+ "2\000SBB64ri8\000SBB64rm\000SBB64rr\000SBB64rr_REV\000SBB8i8\000SBB8mi\000"
+ "SBB8mr\000SBB8ri\000SBB8rm\000SBB8rr\000SBB8rr_REV\000SCAS16\000SCAS32\000"
+ "SCAS64\000SCAS8\000SETAEm\000SETAEr\000SETAm\000SETAr\000SETBEm\000SETB"
+ "Er\000SETB_C16r\000SETB_C32r\000SETB_C64r\000SETB_C8r\000SETBm\000SETBr"
+ "\000SETEm\000SETEr\000SETGEm\000SETGEr\000SETGm\000SETGr\000SETLEm\000S"
+ "ETLEr\000SETLm\000SETLr\000SETNEm\000SETNEr\000SETNOm\000SETNOr\000SETN"
+ "Pm\000SETNPr\000SETNSm\000SETNSr\000SETOm\000SETOr\000SETPm\000SETPr\000"
+ "SETSm\000SETSr\000SFENCE\000SGDTm\000SHL16m1\000SHL16mCL\000SHL16mi\000"
+ "SHL16r1\000SHL16rCL\000SHL16ri\000SHL32m1\000SHL32mCL\000SHL32mi\000SHL"
+ "32r1\000SHL32rCL\000SHL32ri\000SHL64m1\000SHL64mCL\000SHL64mi\000SHL64r"
+ "1\000SHL64rCL\000SHL64ri\000SHL8m1\000SHL8mCL\000SHL8mi\000SHL8r1\000SH"
+ "L8rCL\000SHL8ri\000SHLD16mrCL\000SHLD16mri8\000SHLD16rrCL\000SHLD16rri8"
+ "\000SHLD32mrCL\000SHLD32mri8\000SHLD32rrCL\000SHLD32rri8\000SHLD64mrCL\000"
+ "SHLD64mri8\000SHLD64rrCL\000SHLD64rri8\000SHR16m1\000SHR16mCL\000SHR16m"
+ "i\000SHR16r1\000SHR16rCL\000SHR16ri\000SHR32m1\000SHR32mCL\000SHR32mi\000"
+ "SHR32r1\000SHR32rCL\000SHR32ri\000SHR64m1\000SHR64mCL\000SHR64mi\000SHR"
+ "64r1\000SHR64rCL\000SHR64ri\000SHR8m1\000SHR8mCL\000SHR8mi\000SHR8r1\000"
+ "SHR8rCL\000SHR8ri\000SHRD16mrCL\000SHRD16mri8\000SHRD16rrCL\000SHRD16rr"
+ "i8\000SHRD32mrCL\000SHRD32mri8\000SHRD32rrCL\000SHRD32rri8\000SHRD64mrC"
+ "L\000SHRD64mri8\000SHRD64rrCL\000SHRD64rri8\000SHUFPDrmi\000SHUFPDrri\000"
+ "SHUFPSrmi\000SHUFPSrri\000SIDTm\000SIN_F\000SIN_Fp32\000SIN_Fp64\000SIN"
+ "_Fp80\000SLDT16m\000SLDT16r\000SLDT64m\000SLDT64r\000SMSW16m\000SMSW16r"
+ "\000SMSW32r\000SMSW64r\000SQRTPDm\000SQRTPDm_Int\000SQRTPDr\000SQRTPDr_"
+ "Int\000SQRTPSm\000SQRTPSm_Int\000SQRTPSr\000SQRTPSr_Int\000SQRTSDm\000S"
+ "QRTSDm_Int\000SQRTSDr\000SQRTSDr_Int\000SQRTSSm\000SQRTSSm_Int\000SQRTS"
+ "Sr\000SQRTSSr_Int\000SQRT_F\000SQRT_Fp32\000SQRT_Fp64\000SQRT_Fp80\000S"
+ "S_PREFIX\000STC\000STD\000STI\000STMXCSR\000STOSB\000STOSD\000STOSW\000"
+ "STRm\000STRr\000ST_F32m\000ST_F64m\000ST_FP32m\000ST_FP64m\000ST_FP80m\000"
+ "ST_FPrr\000ST_Fp32m\000ST_Fp64m\000ST_Fp64m32\000ST_Fp80m32\000ST_Fp80m"
+ "64\000ST_FpP32m\000ST_FpP64m\000ST_FpP64m32\000ST_FpP80m\000ST_FpP80m32"
+ "\000ST_FpP80m64\000ST_Frr\000SUB16i16\000SUB16mi\000SUB16mi8\000SUB16mr"
+ "\000SUB16ri\000SUB16ri8\000SUB16rm\000SUB16rr\000SUB16rr_REV\000SUB32i3"
+ "2\000SUB32mi\000SUB32mi8\000SUB32mr\000SUB32ri\000SUB32ri8\000SUB32rm\000"
+ "SUB32rr\000SUB32rr_REV\000SUB64i32\000SUB64mi32\000SUB64mi8\000SUB64mr\000"
+ "SUB64ri32\000SUB64ri8\000SUB64rm\000SUB64rr\000SUB64rr_REV\000SUB8i8\000"
+ "SUB8mi\000SUB8mr\000SUB8ri\000SUB8rm\000SUB8rr\000SUB8rr_REV\000SUBPDrm"
+ "\000SUBPDrr\000SUBPSrm\000SUBPSrr\000SUBR_F32m\000SUBR_F64m\000SUBR_FI1"
+ "6m\000SUBR_FI32m\000SUBR_FPrST0\000SUBR_FST0r\000SUBR_Fp32m\000SUBR_Fp6"
+ "4m\000SUBR_Fp64m32\000SUBR_Fp80m32\000SUBR_Fp80m64\000SUBR_FpI16m32\000"
+ "SUBR_FpI16m64\000SUBR_FpI16m80\000SUBR_FpI32m32\000SUBR_FpI32m64\000SUB"
+ "R_FpI32m80\000SUBR_FrST0\000SUBSDrm\000SUBSDrm_Int\000SUBSDrr\000SUBSDr"
+ "r_Int\000SUBSSrm\000SUBSSrm_Int\000SUBSSrr\000SUBSSrr_Int\000SUB_F32m\000"
+ "SUB_F64m\000SUB_FI16m\000SUB_FI32m\000SUB_FPrST0\000SUB_FST0r\000SUB_Fp"
+ "32\000SUB_Fp32m\000SUB_Fp64\000SUB_Fp64m\000SUB_Fp64m32\000SUB_Fp80\000"
+ "SUB_Fp80m32\000SUB_Fp80m64\000SUB_FpI16m32\000SUB_FpI16m64\000SUB_FpI16"
+ "m80\000SUB_FpI32m32\000SUB_FpI32m64\000SUB_FpI32m80\000SUB_FrST0\000SWA"
+ "PGS\000SYSCALL\000SYSENTER\000SYSEXIT\000SYSEXIT64\000SYSRET\000TAILJMP"
+ "d\000TAILJMPm\000TAILJMPr\000TAILJMPr64\000TCRETURNdi\000TCRETURNdi64\000"
+ "TCRETURNri\000TCRETURNri64\000TEST16i16\000TEST16mi\000TEST16ri\000TEST"
+ "16rm\000TEST16rr\000TEST32i32\000TEST32mi\000TEST32ri\000TEST32rm\000TE"
+ "ST32rr\000TEST64i32\000TEST64mi32\000TEST64ri32\000TEST64rm\000TEST64rr"
+ "\000TEST8i8\000TEST8mi\000TEST8ri\000TEST8rm\000TEST8rr\000TLS_addr32\000"
+ "TLS_addr64\000TRAP\000TST_F\000TST_Fp32\000TST_Fp64\000TST_Fp80\000UCOM"
+ "ISDrm\000UCOMISDrr\000UCOMISSrm\000UCOMISSrr\000UCOM_FIPr\000UCOM_FIr\000"
+ "UCOM_FPPr\000UCOM_FPr\000UCOM_FpIr32\000UCOM_FpIr64\000UCOM_FpIr80\000U"
+ "COM_Fpr32\000UCOM_Fpr64\000UCOM_Fpr80\000UCOM_Fr\000UNPCKHPDrm\000UNPCK"
+ "HPDrr\000UNPCKHPSrm\000UNPCKHPSrr\000UNPCKLPDrm\000UNPCKLPDrr\000UNPCKL"
+ "PSrm\000UNPCKLPSrr\000VASTART_SAVE_XMM_REGS\000VERRm\000VERRr\000VERWm\000"
+ "VERWr\000VMCALL\000VMCLEARm\000VMLAUNCH\000VMPTRLDm\000VMPTRSTm\000VMRE"
+ "AD32rm\000VMREAD32rr\000VMREAD64rm\000VMREAD64rr\000VMRESUME\000VMWRITE"
+ "32rm\000VMWRITE32rr\000VMWRITE64rm\000VMWRITE64rr\000VMXOFF\000VMXON\000"
+ "V_SET0\000V_SETALLONES\000WAIT\000WBINVD\000WINCALL64m\000WINCALL64pcre"
+ "l32\000WINCALL64r\000WRMSR\000XADD16rm\000XADD16rr\000XADD32rm\000XADD3"
+ "2rr\000XADD64rm\000XADD64rr\000XADD8rm\000XADD8rr\000XCHG16ar\000XCHG16"
+ "rm\000XCHG16rr\000XCHG32ar\000XCHG32rm\000XCHG32rr\000XCHG64ar\000XCHG6"
+ "4rm\000XCHG64rr\000XCHG8rm\000XCHG8rr\000XCH_F\000XLAT\000XOR16i16\000X"
+ "OR16mi\000XOR16mi8\000XOR16mr\000XOR16ri\000XOR16ri8\000XOR16rm\000XOR1"
+ "6rr\000XOR16rr_REV\000XOR32i32\000XOR32mi\000XOR32mi8\000XOR32mr\000XOR"
+ "32ri\000XOR32ri8\000XOR32rm\000XOR32rr\000XOR32rr_REV\000XOR64i32\000XO"
+ "R64mi32\000XOR64mi8\000XOR64mr\000XOR64ri32\000XOR64ri8\000XOR64rm\000X"
+ "OR64rr\000XOR64rr_REV\000XOR8i8\000XOR8mi\000XOR8mr\000XOR8ri\000XOR8rm"
+ "\000XOR8rr\000XOR8rr_REV\000XORPDrm\000XORPDrr\000XORPSrm\000XORPSrr\000";
+ return Strs+InstAsmOffset[Opcode];
+}
+
+#endif
diff --git a/libclamav/c++/X86GenAsmWriter1.inc b/libclamav/c++/X86GenAsmWriter1.inc
index 56b4f90..f6b1d41 100644
--- a/libclamav/c++/X86GenAsmWriter1.inc
+++ b/libclamav/c++/X86GenAsmWriter1.inc
@@ -21,101 +21,101 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // IMPLICIT_DEF
0U, // SUBREG_TO_REG
0U, // COPY_TO_REGCLASS
- 1U, // DEBUG_VALUE
- 13U, // ABS_F
+ 1U, // DBG_VALUE
+ 11U, // ABS_F
0U, // ABS_Fp32
0U, // ABS_Fp64
0U, // ABS_Fp80
- 134217746U, // ADC16i16
- 272629788U, // ADC16mi
- 272629788U, // ADC16mi8
- 272629788U, // ADC16mr
- 138543132U, // ADC16ri
- 138543132U, // ADC16ri8
- 138674204U, // ADC16rm
- 138543132U, // ADC16rr
- 138543132U, // ADC16rr_REV
- 134217761U, // ADC32i32
- 406847516U, // ADC32mi
- 406847516U, // ADC32mi8
- 406847516U, // ADC32mr
- 138543132U, // ADC32ri
- 138543132U, // ADC32ri8
- 138805276U, // ADC32rm
- 138543132U, // ADC32rr
- 138543132U, // ADC32rr_REV
- 134217772U, // ADC64i32
- 541065244U, // ADC64mi32
- 541065244U, // ADC64mi8
- 541065244U, // ADC64mr
- 138543132U, // ADC64ri32
- 138543132U, // ADC64ri8
- 138936348U, // ADC64rm
- 138543132U, // ADC64rr
- 138543132U, // ADC64rr_REV
- 134217783U, // ADC8i8
- 675282972U, // ADC8mi
- 675282972U, // ADC8mr
- 138543132U, // ADC8ri
- 139067420U, // ADC8rm
- 138543132U, // ADC8rr
- 138543132U, // ADC8rr_REV
- 134217793U, // ADD16i16
- 272629835U, // ADD16mi
- 272629835U, // ADD16mi8
- 272629835U, // ADD16mr
- 138543179U, // ADD16mrmrr
- 138543179U, // ADD16ri
- 138543179U, // ADD16ri8
- 138674251U, // ADD16rm
- 138543179U, // ADD16rr
- 134217808U, // ADD32i32
- 406847563U, // ADD32mi
- 406847563U, // ADD32mi8
- 406847563U, // ADD32mr
- 138543179U, // ADD32mrmrr
- 138543179U, // ADD32ri
- 138543179U, // ADD32ri8
- 138805323U, // ADD32rm
- 138543179U, // ADD32rr
- 134217819U, // ADD64i32
- 541065291U, // ADD64mi32
- 541065291U, // ADD64mi8
- 541065291U, // ADD64mr
- 138543179U, // ADD64mrmrr
- 138543179U, // ADD64ri32
- 138543179U, // ADD64ri8
- 138936395U, // ADD64rm
- 138543179U, // ADD64rr
- 134217830U, // ADD8i8
- 675283019U, // ADD8mi
- 675283019U, // ADD8mr
- 138543179U, // ADD8mrmrr
- 138543179U, // ADD8ri
- 139067467U, // ADD8rm
- 138543179U, // ADD8rr
- 139198576U, // ADDPDrm
- 138543216U, // ADDPDrr
- 139198583U, // ADDPSrm
- 138543223U, // ADDPSrr
- 139329662U, // ADDSDrm
- 139329662U, // ADDSDrm_Int
- 138543230U, // ADDSDrr
- 138543230U, // ADDSDrr_Int
- 139460741U, // ADDSSrm
- 139460741U, // ADDSSrm_Int
- 138543237U, // ADDSSrr
- 138543237U, // ADDSSrr_Int
- 139198604U, // ADDSUBPDrm
- 138543244U, // ADDSUBPDrr
- 139198614U, // ADDSUBPSrm
- 138543254U, // ADDSUBPSrr
- 805306528U, // ADD_F32m
- 939524256U, // ADD_F64m
- 268435622U, // ADD_FI16m
- 402653350U, // ADD_FI32m
- 134217901U, // ADD_FPrST0
- 134217888U, // ADD_FST0r
+ 134217744U, // ADC16i16
+ 272629786U, // ADC16mi
+ 272629786U, // ADC16mi8
+ 272629786U, // ADC16mr
+ 138543130U, // ADC16ri
+ 138543130U, // ADC16ri8
+ 138674202U, // ADC16rm
+ 138543130U, // ADC16rr
+ 138543130U, // ADC16rr_REV
+ 134217759U, // ADC32i32
+ 406847514U, // ADC32mi
+ 406847514U, // ADC32mi8
+ 406847514U, // ADC32mr
+ 138543130U, // ADC32ri
+ 138543130U, // ADC32ri8
+ 138805274U, // ADC32rm
+ 138543130U, // ADC32rr
+ 138543130U, // ADC32rr_REV
+ 134217770U, // ADC64i32
+ 541065242U, // ADC64mi32
+ 541065242U, // ADC64mi8
+ 541065242U, // ADC64mr
+ 138543130U, // ADC64ri32
+ 138543130U, // ADC64ri8
+ 138936346U, // ADC64rm
+ 138543130U, // ADC64rr
+ 138543130U, // ADC64rr_REV
+ 134217781U, // ADC8i8
+ 675282970U, // ADC8mi
+ 675282970U, // ADC8mr
+ 138543130U, // ADC8ri
+ 139067418U, // ADC8rm
+ 138543130U, // ADC8rr
+ 138543130U, // ADC8rr_REV
+ 134217791U, // ADD16i16
+ 272629833U, // ADD16mi
+ 272629833U, // ADD16mi8
+ 272629833U, // ADD16mr
+ 138543177U, // ADD16mrmrr
+ 138543177U, // ADD16ri
+ 138543177U, // ADD16ri8
+ 138674249U, // ADD16rm
+ 138543177U, // ADD16rr
+ 134217806U, // ADD32i32
+ 406847561U, // ADD32mi
+ 406847561U, // ADD32mi8
+ 406847561U, // ADD32mr
+ 138543177U, // ADD32mrmrr
+ 138543177U, // ADD32ri
+ 138543177U, // ADD32ri8
+ 138805321U, // ADD32rm
+ 138543177U, // ADD32rr
+ 134217817U, // ADD64i32
+ 541065289U, // ADD64mi32
+ 541065289U, // ADD64mi8
+ 541065289U, // ADD64mr
+ 138543177U, // ADD64mrmrr
+ 138543177U, // ADD64ri32
+ 138543177U, // ADD64ri8
+ 138936393U, // ADD64rm
+ 138543177U, // ADD64rr
+ 134217828U, // ADD8i8
+ 675283017U, // ADD8mi
+ 675283017U, // ADD8mr
+ 138543177U, // ADD8mrmrr
+ 138543177U, // ADD8ri
+ 139067465U, // ADD8rm
+ 138543177U, // ADD8rr
+ 139198574U, // ADDPDrm
+ 138543214U, // ADDPDrr
+ 139198581U, // ADDPSrm
+ 138543221U, // ADDPSrr
+ 139329660U, // ADDSDrm
+ 139329660U, // ADDSDrm_Int
+ 138543228U, // ADDSDrr
+ 138543228U, // ADDSDrr_Int
+ 139460739U, // ADDSSrm
+ 139460739U, // ADDSSrm_Int
+ 138543235U, // ADDSSrr
+ 138543235U, // ADDSSrr_Int
+ 139198602U, // ADDSUBPDrm
+ 138543242U, // ADDSUBPDrr
+ 139198612U, // ADDSUBPSrm
+ 138543252U, // ADDSUBPSrr
+ 805306526U, // ADD_F32m
+ 939524254U, // ADD_F64m
+ 268435620U, // ADD_FI16m
+ 402653348U, // ADD_FI32m
+ 134217899U, // ADD_FPrST0
+ 134217886U, // ADD_FST0r
0U, // ADD_Fp32
0U, // ADD_Fp32m
0U, // ADD_Fp64
@@ -130,462 +130,463 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // ADD_FpI32m32
0U, // ADD_FpI32m64
0U, // ADD_FpI32m80
- 142606496U, // ADD_FrST0
- 180U, // ADJCALLSTACKDOWN32
- 180U, // ADJCALLSTACKDOWN64
- 198U, // ADJCALLSTACKUP32
- 198U, // ADJCALLSTACKUP64
- 134217942U, // AND16i16
- 272629984U, // AND16mi
- 272629984U, // AND16mi8
- 272629984U, // AND16mr
- 138543328U, // AND16ri
- 138543328U, // AND16ri8
- 138674400U, // AND16rm
- 138543328U, // AND16rr
- 138543328U, // AND16rr_REV
- 134217957U, // AND32i32
- 406847712U, // AND32mi
- 406847712U, // AND32mi8
- 406847712U, // AND32mr
- 138543328U, // AND32ri
- 138543328U, // AND32ri8
- 138805472U, // AND32rm
- 138543328U, // AND32rr
- 138543328U, // AND32rr_REV
- 134217968U, // AND64i32
- 541065440U, // AND64mi32
- 541065440U, // AND64mi8
- 541065440U, // AND64mr
- 138543328U, // AND64ri32
- 138543328U, // AND64ri8
- 138936544U, // AND64rm
- 138543328U, // AND64rr
- 138543328U, // AND64rr_REV
- 134217979U, // AND8i8
- 675283168U, // AND8mi
- 675283168U, // AND8mr
- 138543328U, // AND8ri
- 139067616U, // AND8rm
- 138543328U, // AND8rr
- 138543328U, // AND8rr_REV
- 139198725U, // ANDNPDrm
- 138543365U, // ANDNPDrr
- 139198733U, // ANDNPSrm
- 138543373U, // ANDNPSrr
- 139198741U, // ANDPDrm
- 138543381U, // ANDPDrr
- 139198748U, // ANDPSrm
- 138543388U, // ANDPSrr
- 291U, // ATOMADD6432
- 312U, // ATOMAND16
- 331U, // ATOMAND32
- 350U, // ATOMAND64
- 369U, // ATOMAND6432
- 390U, // ATOMAND8
- 408U, // ATOMMAX16
- 427U, // ATOMMAX32
- 446U, // ATOMMAX64
- 465U, // ATOMMIN16
- 484U, // ATOMMIN32
- 503U, // ATOMMIN64
- 522U, // ATOMNAND16
- 542U, // ATOMNAND32
- 562U, // ATOMNAND64
- 582U, // ATOMNAND6432
- 604U, // ATOMNAND8
- 623U, // ATOMOR16
- 641U, // ATOMOR32
- 659U, // ATOMOR64
- 677U, // ATOMOR6432
- 697U, // ATOMOR8
- 714U, // ATOMSUB6432
- 735U, // ATOMSWAP6432
- 757U, // ATOMUMAX16
- 777U, // ATOMUMAX32
- 797U, // ATOMUMAX64
- 817U, // ATOMUMIN16
- 837U, // ATOMUMIN32
- 857U, // ATOMUMIN64
- 877U, // ATOMXOR16
- 896U, // ATOMXOR32
- 915U, // ATOMXOR64
- 934U, // ATOMXOR6432
- 955U, // ATOMXOR8
- 139609037U, // BLENDPDrmi
- 138560461U, // BLENDPDrri
- 139609046U, // BLENDPSrmi
- 138560470U, // BLENDPSrri
- 139625439U, // BLENDVPDrm0
- 138576863U, // BLENDVPDrr0
- 139625449U, // BLENDVPSrm0
- 138576873U, // BLENDVPSrr0
- 139723763U, // BSF16rm
- 139854835U, // BSF16rr
- 139985907U, // BSF32rm
- 139854835U, // BSF32rr
- 140116979U, // BSF64rm
- 139854835U, // BSF64rr
- 139723768U, // BSR16rm
- 139854840U, // BSR16rr
- 139985912U, // BSR32rm
- 139854840U, // BSR32rr
- 140116984U, // BSR64rm
- 139854840U, // BSR64rr
- 134218749U, // BSWAP32r
- 134218749U, // BSWAP64r
- 272630788U, // BT16mi8
- 272630788U, // BT16mr
- 139854852U, // BT16ri8
- 139854852U, // BT16rr
- 406848516U, // BT32mi8
- 406848516U, // BT32mr
- 139854852U, // BT32ri8
- 139854852U, // BT32rr
- 541066244U, // BT64mi8
- 541066244U, // BT64mr
- 139854852U, // BT64ri8
- 139854852U, // BT64rr
- 272630792U, // BTC16mi8
- 272630792U, // BTC16mr
- 139854856U, // BTC16ri8
- 139854856U, // BTC16rr
- 406848520U, // BTC32mi8
- 406848520U, // BTC32mr
- 139854856U, // BTC32ri8
- 139854856U, // BTC32rr
- 541066248U, // BTC64mi8
- 541066248U, // BTC64mr
- 139854856U, // BTC64ri8
- 139854856U, // BTC64rr
- 272630797U, // BTR16mi8
- 272630797U, // BTR16mr
- 139854861U, // BTR16ri8
- 139854861U, // BTR16rr
- 406848525U, // BTR32mi8
- 406848525U, // BTR32mr
- 139854861U, // BTR32ri8
- 139854861U, // BTR32rr
- 541066253U, // BTR64mi8
- 541066253U, // BTR64mr
- 139854861U, // BTR64ri8
- 139854861U, // BTR64rr
- 272630802U, // BTS16mi8
- 272630802U, // BTS16mr
- 139854866U, // BTS16ri8
- 139854866U, // BTS16rr
- 406848530U, // BTS32mi8
- 406848530U, // BTS32mr
- 139854866U, // BTS32ri8
- 139854866U, // BTS32rr
- 541066258U, // BTS64mi8
- 541066258U, // BTS64mr
- 139854866U, // BTS64ri8
- 139854866U, // BTS64rr
- 402654231U, // CALL32m
- 134218775U, // CALL32r
- 536871959U, // CALL64m
- 1073742871U, // CALL64pcrel32
- 134218775U, // CALL64r
- 1073742871U, // CALLpcrel32
- 1053U, // CBW
- 1057U, // CDQ
- 1061U, // CDQE
- 1066U, // CHS_F
+ 142606494U, // ADD_FrST0
+ 178U, // ADJCALLSTACKDOWN32
+ 178U, // ADJCALLSTACKDOWN64
+ 196U, // ADJCALLSTACKUP32
+ 196U, // ADJCALLSTACKUP64
+ 134217940U, // AND16i16
+ 272629982U, // AND16mi
+ 272629982U, // AND16mi8
+ 272629982U, // AND16mr
+ 138543326U, // AND16ri
+ 138543326U, // AND16ri8
+ 138674398U, // AND16rm
+ 138543326U, // AND16rr
+ 138543326U, // AND16rr_REV
+ 134217955U, // AND32i32
+ 406847710U, // AND32mi
+ 406847710U, // AND32mi8
+ 406847710U, // AND32mr
+ 138543326U, // AND32ri
+ 138543326U, // AND32ri8
+ 138805470U, // AND32rm
+ 138543326U, // AND32rr
+ 138543326U, // AND32rr_REV
+ 134217966U, // AND64i32
+ 541065438U, // AND64mi32
+ 541065438U, // AND64mi8
+ 541065438U, // AND64mr
+ 138543326U, // AND64ri32
+ 138543326U, // AND64ri8
+ 138936542U, // AND64rm
+ 138543326U, // AND64rr
+ 138543326U, // AND64rr_REV
+ 134217977U, // AND8i8
+ 675283166U, // AND8mi
+ 675283166U, // AND8mr
+ 138543326U, // AND8ri
+ 139067614U, // AND8rm
+ 138543326U, // AND8rr
+ 138543326U, // AND8rr_REV
+ 139198723U, // ANDNPDrm
+ 138543363U, // ANDNPDrr
+ 139198731U, // ANDNPSrm
+ 138543371U, // ANDNPSrr
+ 139198739U, // ANDPDrm
+ 138543379U, // ANDPDrr
+ 139198746U, // ANDPSrm
+ 138543386U, // ANDPSrr
+ 289U, // ATOMADD6432
+ 310U, // ATOMAND16
+ 329U, // ATOMAND32
+ 348U, // ATOMAND64
+ 367U, // ATOMAND6432
+ 388U, // ATOMAND8
+ 406U, // ATOMMAX16
+ 425U, // ATOMMAX32
+ 444U, // ATOMMAX64
+ 463U, // ATOMMIN16
+ 482U, // ATOMMIN32
+ 501U, // ATOMMIN64
+ 520U, // ATOMNAND16
+ 540U, // ATOMNAND32
+ 560U, // ATOMNAND64
+ 580U, // ATOMNAND6432
+ 602U, // ATOMNAND8
+ 621U, // ATOMOR16
+ 639U, // ATOMOR32
+ 657U, // ATOMOR64
+ 675U, // ATOMOR6432
+ 695U, // ATOMOR8
+ 712U, // ATOMSUB6432
+ 733U, // ATOMSWAP6432
+ 755U, // ATOMUMAX16
+ 775U, // ATOMUMAX32
+ 795U, // ATOMUMAX64
+ 815U, // ATOMUMIN16
+ 835U, // ATOMUMIN32
+ 855U, // ATOMUMIN64
+ 875U, // ATOMXOR16
+ 894U, // ATOMXOR32
+ 913U, // ATOMXOR64
+ 932U, // ATOMXOR6432
+ 953U, // ATOMXOR8
+ 139609035U, // BLENDPDrmi
+ 138560459U, // BLENDPDrri
+ 139609044U, // BLENDPSrmi
+ 138560468U, // BLENDPSrri
+ 139625437U, // BLENDVPDrm0
+ 138576861U, // BLENDVPDrr0
+ 139625447U, // BLENDVPSrm0
+ 138576871U, // BLENDVPSrr0
+ 139723761U, // BSF16rm
+ 139854833U, // BSF16rr
+ 139985905U, // BSF32rm
+ 139854833U, // BSF32rr
+ 140116977U, // BSF64rm
+ 139854833U, // BSF64rr
+ 139723766U, // BSR16rm
+ 139854838U, // BSR16rr
+ 139985910U, // BSR32rm
+ 139854838U, // BSR32rr
+ 140116982U, // BSR64rm
+ 139854838U, // BSR64rr
+ 134218747U, // BSWAP32r
+ 134218747U, // BSWAP64r
+ 272630786U, // BT16mi8
+ 272630786U, // BT16mr
+ 139854850U, // BT16ri8
+ 139854850U, // BT16rr
+ 406848514U, // BT32mi8
+ 406848514U, // BT32mr
+ 139854850U, // BT32ri8
+ 139854850U, // BT32rr
+ 541066242U, // BT64mi8
+ 541066242U, // BT64mr
+ 139854850U, // BT64ri8
+ 139854850U, // BT64rr
+ 272630790U, // BTC16mi8
+ 272630790U, // BTC16mr
+ 139854854U, // BTC16ri8
+ 139854854U, // BTC16rr
+ 406848518U, // BTC32mi8
+ 406848518U, // BTC32mr
+ 139854854U, // BTC32ri8
+ 139854854U, // BTC32rr
+ 541066246U, // BTC64mi8
+ 541066246U, // BTC64mr
+ 139854854U, // BTC64ri8
+ 139854854U, // BTC64rr
+ 272630795U, // BTR16mi8
+ 272630795U, // BTR16mr
+ 139854859U, // BTR16ri8
+ 139854859U, // BTR16rr
+ 406848523U, // BTR32mi8
+ 406848523U, // BTR32mr
+ 139854859U, // BTR32ri8
+ 139854859U, // BTR32rr
+ 541066251U, // BTR64mi8
+ 541066251U, // BTR64mr
+ 139854859U, // BTR64ri8
+ 139854859U, // BTR64rr
+ 272630800U, // BTS16mi8
+ 272630800U, // BTS16mr
+ 139854864U, // BTS16ri8
+ 139854864U, // BTS16rr
+ 406848528U, // BTS32mi8
+ 406848528U, // BTS32mr
+ 139854864U, // BTS32ri8
+ 139854864U, // BTS32rr
+ 541066256U, // BTS64mi8
+ 541066256U, // BTS64mr
+ 139854864U, // BTS64ri8
+ 139854864U, // BTS64rr
+ 402654229U, // CALL32m
+ 134218773U, // CALL32r
+ 536871957U, // CALL64m
+ 1073742869U, // CALL64pcrel32
+ 134218773U, // CALL64r
+ 1073742869U, // CALLpcrel32
+ 1051U, // CBW
+ 1055U, // CDQ
+ 1059U, // CDQE
+ 1064U, // CHS_F
0U, // CHS_Fp32
0U, // CHS_Fp64
0U, // CHS_Fp80
- 1071U, // CLC
- 1075U, // CLD
- 671089719U, // CLFLUSH
- 1088U, // CLI
- 1092U, // CLTS
- 1097U, // CMC
- 138675277U, // CMOVA16rm
- 138544205U, // CMOVA16rr
- 138806349U, // CMOVA32rm
- 138544205U, // CMOVA32rr
- 138937421U, // CMOVA64rm
- 138544205U, // CMOVA64rr
- 138675284U, // CMOVAE16rm
- 138544212U, // CMOVAE16rr
- 138806356U, // CMOVAE32rm
- 138544212U, // CMOVAE32rr
- 138937428U, // CMOVAE64rm
- 138544212U, // CMOVAE64rr
- 138675292U, // CMOVB16rm
- 138544220U, // CMOVB16rr
- 138806364U, // CMOVB32rm
- 138544220U, // CMOVB32rr
- 138937436U, // CMOVB64rm
- 138544220U, // CMOVB64rr
- 138675299U, // CMOVBE16rm
- 138544227U, // CMOVBE16rr
- 138806371U, // CMOVBE32rm
- 138544227U, // CMOVBE32rr
- 138937443U, // CMOVBE64rm
- 138544227U, // CMOVBE64rr
- 134218859U, // CMOVBE_F
+ 1069U, // CLC
+ 1073U, // CLD
+ 671089717U, // CLFLUSH
+ 1086U, // CLI
+ 1090U, // CLTS
+ 1095U, // CMC
+ 138675275U, // CMOVA16rm
+ 138544203U, // CMOVA16rr
+ 138806347U, // CMOVA32rm
+ 138544203U, // CMOVA32rr
+ 138937419U, // CMOVA64rm
+ 138544203U, // CMOVA64rr
+ 138675282U, // CMOVAE16rm
+ 138544210U, // CMOVAE16rr
+ 138806354U, // CMOVAE32rm
+ 138544210U, // CMOVAE32rr
+ 138937426U, // CMOVAE64rm
+ 138544210U, // CMOVAE64rr
+ 138675290U, // CMOVB16rm
+ 138544218U, // CMOVB16rr
+ 138806362U, // CMOVB32rm
+ 138544218U, // CMOVB32rr
+ 138937434U, // CMOVB64rm
+ 138544218U, // CMOVB64rr
+ 138675297U, // CMOVBE16rm
+ 138544225U, // CMOVBE16rr
+ 138806369U, // CMOVBE32rm
+ 138544225U, // CMOVBE32rr
+ 138937441U, // CMOVBE64rm
+ 138544225U, // CMOVBE64rr
+ 134218857U, // CMOVBE_F
0U, // CMOVBE_Fp32
0U, // CMOVBE_Fp64
0U, // CMOVBE_Fp80
- 134218876U, // CMOVB_F
+ 134218874U, // CMOVB_F
0U, // CMOVB_Fp32
0U, // CMOVB_Fp64
0U, // CMOVB_Fp80
- 138675340U, // CMOVE16rm
- 138544268U, // CMOVE16rr
- 138806412U, // CMOVE32rm
- 138544268U, // CMOVE32rr
- 138937484U, // CMOVE64rm
- 138544268U, // CMOVE64rr
- 134218899U, // CMOVE_F
+ 138675338U, // CMOVE16rm
+ 138544266U, // CMOVE16rr
+ 138806410U, // CMOVE32rm
+ 138544266U, // CMOVE32rr
+ 138937482U, // CMOVE64rm
+ 138544266U, // CMOVE64rr
+ 134218897U, // CMOVE_F
0U, // CMOVE_Fp32
0U, // CMOVE_Fp64
0U, // CMOVE_Fp80
- 138675363U, // CMOVG16rm
- 138544291U, // CMOVG16rr
- 138806435U, // CMOVG32rm
- 138544291U, // CMOVG32rr
- 138937507U, // CMOVG64rm
- 138544291U, // CMOVG64rr
- 138675370U, // CMOVGE16rm
- 138544298U, // CMOVGE16rr
- 138806442U, // CMOVGE32rm
- 138544298U, // CMOVGE32rr
- 138937514U, // CMOVGE64rm
- 138544298U, // CMOVGE64rr
- 138675378U, // CMOVL16rm
- 138544306U, // CMOVL16rr
- 138806450U, // CMOVL32rm
- 138544306U, // CMOVL32rr
- 138937522U, // CMOVL64rm
- 138544306U, // CMOVL64rr
- 138675385U, // CMOVLE16rm
- 138544313U, // CMOVLE16rr
- 138806457U, // CMOVLE32rm
- 138544313U, // CMOVLE32rr
- 138937529U, // CMOVLE64rm
- 138544313U, // CMOVLE64rr
- 134218945U, // CMOVNBE_F
+ 138675361U, // CMOVG16rm
+ 138544289U, // CMOVG16rr
+ 138806433U, // CMOVG32rm
+ 138544289U, // CMOVG32rr
+ 138937505U, // CMOVG64rm
+ 138544289U, // CMOVG64rr
+ 138675368U, // CMOVGE16rm
+ 138544296U, // CMOVGE16rr
+ 138806440U, // CMOVGE32rm
+ 138544296U, // CMOVGE32rr
+ 138937512U, // CMOVGE64rm
+ 138544296U, // CMOVGE64rr
+ 138675376U, // CMOVL16rm
+ 138544304U, // CMOVL16rr
+ 138806448U, // CMOVL32rm
+ 138544304U, // CMOVL32rr
+ 138937520U, // CMOVL64rm
+ 138544304U, // CMOVL64rr
+ 138675383U, // CMOVLE16rm
+ 138544311U, // CMOVLE16rr
+ 138806455U, // CMOVLE32rm
+ 138544311U, // CMOVLE32rr
+ 138937527U, // CMOVLE64rm
+ 138544311U, // CMOVLE64rr
+ 134218943U, // CMOVNBE_F
0U, // CMOVNBE_Fp32
0U, // CMOVNBE_Fp64
0U, // CMOVNBE_Fp80
- 134218963U, // CMOVNB_F
+ 134218961U, // CMOVNB_F
0U, // CMOVNB_Fp32
0U, // CMOVNB_Fp64
0U, // CMOVNB_Fp80
- 138675428U, // CMOVNE16rm
- 138544356U, // CMOVNE16rr
- 138806500U, // CMOVNE32rm
- 138544356U, // CMOVNE32rr
- 138937572U, // CMOVNE64rm
- 138544356U, // CMOVNE64rr
- 134218988U, // CMOVNE_F
+ 138675426U, // CMOVNE16rm
+ 138544354U, // CMOVNE16rr
+ 138806498U, // CMOVNE32rm
+ 138544354U, // CMOVNE32rr
+ 138937570U, // CMOVNE64rm
+ 138544354U, // CMOVNE64rr
+ 134218986U, // CMOVNE_F
0U, // CMOVNE_Fp32
0U, // CMOVNE_Fp64
0U, // CMOVNE_Fp80
- 138675453U, // CMOVNO16rm
- 138544381U, // CMOVNO16rr
- 138806525U, // CMOVNO32rm
- 138544381U, // CMOVNO32rr
- 138937597U, // CMOVNO64rm
- 138544381U, // CMOVNO64rr
- 138675461U, // CMOVNP16rm
- 138544389U, // CMOVNP16rr
- 138806533U, // CMOVNP32rm
- 138544389U, // CMOVNP32rr
- 138937605U, // CMOVNP64rm
- 138544389U, // CMOVNP64rr
- 134219021U, // CMOVNP_F
+ 138675451U, // CMOVNO16rm
+ 138544379U, // CMOVNO16rr
+ 138806523U, // CMOVNO32rm
+ 138544379U, // CMOVNO32rr
+ 138937595U, // CMOVNO64rm
+ 138544379U, // CMOVNO64rr
+ 138675459U, // CMOVNP16rm
+ 138544387U, // CMOVNP16rr
+ 138806531U, // CMOVNP32rm
+ 138544387U, // CMOVNP32rr
+ 138937603U, // CMOVNP64rm
+ 138544387U, // CMOVNP64rr
+ 134219019U, // CMOVNP_F
0U, // CMOVNP_Fp32
0U, // CMOVNP_Fp64
0U, // CMOVNP_Fp80
- 138675486U, // CMOVNS16rm
- 138544414U, // CMOVNS16rr
- 138806558U, // CMOVNS32rm
- 138544414U, // CMOVNS32rr
- 138937630U, // CMOVNS64rm
- 138544414U, // CMOVNS64rr
- 138675494U, // CMOVO16rm
- 138544422U, // CMOVO16rr
- 138806566U, // CMOVO32rm
- 138544422U, // CMOVO32rr
- 138937638U, // CMOVO64rm
- 138544422U, // CMOVO64rr
- 138675501U, // CMOVP16rm
- 138544429U, // CMOVP16rr
- 138806573U, // CMOVP32rm
- 138544429U, // CMOVP32rr
- 138937645U, // CMOVP64rm
- 138544429U, // CMOVP64rr
- 134219060U, // CMOVP_F
+ 138675484U, // CMOVNS16rm
+ 138544412U, // CMOVNS16rr
+ 138806556U, // CMOVNS32rm
+ 138544412U, // CMOVNS32rr
+ 138937628U, // CMOVNS64rm
+ 138544412U, // CMOVNS64rr
+ 138675492U, // CMOVO16rm
+ 138544420U, // CMOVO16rr
+ 138806564U, // CMOVO32rm
+ 138544420U, // CMOVO32rr
+ 138937636U, // CMOVO64rm
+ 138544420U, // CMOVO64rr
+ 138675499U, // CMOVP16rm
+ 138544427U, // CMOVP16rr
+ 138806571U, // CMOVP32rm
+ 138544427U, // CMOVP32rr
+ 138937643U, // CMOVP64rm
+ 138544427U, // CMOVP64rr
+ 134219058U, // CMOVP_F
0U, // CMOVP_Fp32
0U, // CMOVP_Fp64
0U, // CMOVP_Fp80
- 138675525U, // CMOVS16rm
- 138544453U, // CMOVS16rr
- 138806597U, // CMOVS32rm
- 138544453U, // CMOVS32rr
- 138937669U, // CMOVS64rm
- 138544453U, // CMOVS64rr
- 1356U, // CMOV_FR32
- 1375U, // CMOV_FR64
- 1394U, // CMOV_GR8
- 1412U, // CMOV_V1I64
- 1432U, // CMOV_V2F64
- 1452U, // CMOV_V2I64
- 1472U, // CMOV_V4F32
- 134219220U, // CMP16i16
- 272631262U, // CMP16mi
- 272631262U, // CMP16mi8
- 272631262U, // CMP16mr
- 139855326U, // CMP16mrmrr
- 139855326U, // CMP16ri
- 139855326U, // CMP16ri8
- 139724254U, // CMP16rm
- 139855326U, // CMP16rr
- 134219235U, // CMP32i32
- 406848990U, // CMP32mi
- 406848990U, // CMP32mi8
- 406848990U, // CMP32mr
- 139855326U, // CMP32mrmrr
- 139855326U, // CMP32ri
- 139855326U, // CMP32ri8
- 139986398U, // CMP32rm
- 139855326U, // CMP32rr
- 134219246U, // CMP64i32
- 541066718U, // CMP64mi32
- 541066718U, // CMP64mi8
- 541066718U, // CMP64mr
- 139855326U, // CMP64mrmrr
- 139855326U, // CMP64ri32
- 139855326U, // CMP64ri8
- 140117470U, // CMP64rm
- 139855326U, // CMP64rr
- 134219257U, // CMP8i8
- 675284446U, // CMP8mi
- 675284446U, // CMP8mr
- 139855326U, // CMP8mrmrr
- 139855326U, // CMP8ri
- 140248542U, // CMP8rm
- 139855326U, // CMP8rr
- 1221330435U, // CMPPDrmi
- 1354892803U, // CMPPDrri
- 1225524739U, // CMPPSrmi
- 1359087107U, // CMPPSrri
- 1543U, // CMPS16
- 1543U, // CMPS32
- 1543U, // CMPS64
- 1543U, // CMPS8
- 1229850115U, // CMPSDrm
- 1363281411U, // CMPSDrr
- 1234175491U, // CMPSSrm
- 1367475715U, // CMPSSrr
- 1476396556U, // CMPXCHG16B
- 272631320U, // CMPXCHG16rm
- 139855384U, // CMPXCHG16rr
- 406849048U, // CMPXCHG32rm
- 139855384U, // CMPXCHG32rr
- 541066776U, // CMPXCHG64rm
- 139855384U, // CMPXCHG64rr
- 536872481U, // CMPXCHG8B
- 675284504U, // CMPXCHG8rm
- 139855384U, // CMPXCHG8rr
- 140379692U, // COMISDrm
- 139855404U, // COMISDrr
- 140379700U, // COMISSrm
- 139855412U, // COMISSrr
- 134219324U, // COMP_FST0r
- 134219331U, // COM_FIPr
- 134219347U, // COM_FIr
- 134219362U, // COM_FST0r
- 1640U, // COS_F
+ 138675523U, // CMOVS16rm
+ 138544451U, // CMOVS16rr
+ 138806595U, // CMOVS32rm
+ 138544451U, // CMOVS32rr
+ 138937667U, // CMOVS64rm
+ 138544451U, // CMOVS64rr
+ 1354U, // CMOV_FR32
+ 1373U, // CMOV_FR64
+ 1392U, // CMOV_GR8
+ 1410U, // CMOV_V1I64
+ 1430U, // CMOV_V2F64
+ 1450U, // CMOV_V2I64
+ 1470U, // CMOV_V4F32
+ 134219218U, // CMP16i16
+ 272631260U, // CMP16mi
+ 272631260U, // CMP16mi8
+ 272631260U, // CMP16mr
+ 139855324U, // CMP16mrmrr
+ 139855324U, // CMP16ri
+ 139855324U, // CMP16ri8
+ 139724252U, // CMP16rm
+ 139855324U, // CMP16rr
+ 134219233U, // CMP32i32
+ 406848988U, // CMP32mi
+ 406848988U, // CMP32mi8
+ 406848988U, // CMP32mr
+ 139855324U, // CMP32mrmrr
+ 139855324U, // CMP32ri
+ 139855324U, // CMP32ri8
+ 139986396U, // CMP32rm
+ 139855324U, // CMP32rr
+ 134219244U, // CMP64i32
+ 541066716U, // CMP64mi32
+ 541066716U, // CMP64mi8
+ 541066716U, // CMP64mr
+ 139855324U, // CMP64mrmrr
+ 139855324U, // CMP64ri32
+ 139855324U, // CMP64ri8
+ 140117468U, // CMP64rm
+ 139855324U, // CMP64rr
+ 134219255U, // CMP8i8
+ 675284444U, // CMP8mi
+ 675284444U, // CMP8mr
+ 139855324U, // CMP8mrmrr
+ 139855324U, // CMP8ri
+ 140248540U, // CMP8rm
+ 139855324U, // CMP8rr
+ 1221330433U, // CMPPDrmi
+ 1354892801U, // CMPPDrri
+ 1225524737U, // CMPPSrmi
+ 1359087105U, // CMPPSrri
+ 1541U, // CMPS16
+ 1541U, // CMPS32
+ 1541U, // CMPS64
+ 1541U, // CMPS8
+ 1229850113U, // CMPSDrm
+ 1363281409U, // CMPSDrr
+ 1234175489U, // CMPSSrm
+ 1367475713U, // CMPSSrr
+ 1476396554U, // CMPXCHG16B
+ 272631318U, // CMPXCHG16rm
+ 139855382U, // CMPXCHG16rr
+ 406849046U, // CMPXCHG32rm
+ 139855382U, // CMPXCHG32rr
+ 541066774U, // CMPXCHG64rm
+ 139855382U, // CMPXCHG64rr
+ 536872479U, // CMPXCHG8B
+ 675284502U, // CMPXCHG8rm
+ 139855382U, // CMPXCHG8rr
+ 140379690U, // COMISDrm
+ 139855402U, // COMISDrr
+ 140379698U, // COMISSrm
+ 139855410U, // COMISSrr
+ 134219322U, // COMP_FST0r
+ 134219329U, // COM_FIPr
+ 134219345U, // COM_FIr
+ 134219360U, // COM_FST0r
+ 1638U, // COS_F
0U, // COS_Fp32
0U, // COS_Fp64
0U, // COS_Fp80
- 1645U, // CPUID
- 1651U, // CQO
- 1639974519U, // CRC32m16
- 1644168823U, // CRC32m32
- 1648363127U, // CRC32m8
- 1652557431U, // CRC32r16
- 1652557431U, // CRC32r32
- 1652557431U, // CRC32r8
- 1656751735U, // CRC64m64
- 1652557431U, // CRC64r64
- 140379775U, // CVTDQ2PDrm
- 139855487U, // CVTDQ2PDrr
- 140379785U, // CVTDQ2PSrm
- 139855497U, // CVTDQ2PSrr
- 140379795U, // CVTPD2DQrm
- 139855507U, // CVTPD2DQrr
- 140379805U, // CVTPD2PSrm
- 139855517U, // CVTPD2PSrr
- 140379815U, // CVTPS2DQrm
- 139855527U, // CVTPS2DQrr
- 140510897U, // CVTPS2PDrm
- 139855537U, // CVTPS2PDrr
- 140510907U, // CVTSD2SI64rm
- 139855547U, // CVTSD2SI64rr
- 140510917U, // CVTSD2SSrm
- 139855557U, // CVTSD2SSrr
- 140117711U, // CVTSI2SD64rm
- 139855567U, // CVTSI2SD64rr
- 139986639U, // CVTSI2SDrm
- 139855567U, // CVTSI2SDrr
- 140117721U, // CVTSI2SS64rm
- 139855577U, // CVTSI2SS64rr
- 139986649U, // CVTSI2SSrm
- 139855577U, // CVTSI2SSrr
- 140642019U, // CVTSS2SDrm
- 139855587U, // CVTSS2SDrr
- 140642029U, // CVTSS2SI64rm
- 139855597U, // CVTSS2SI64rr
- 140642029U, // CVTSS2SIrm
- 139855597U, // CVTSS2SIrr
- 140379895U, // CVTTPS2DQrm
- 139855607U, // CVTTPS2DQrr
- 140510978U, // CVTTSD2SI64rm
- 139855618U, // CVTTSD2SI64rr
- 140510978U, // CVTTSD2SIrm
- 139855618U, // CVTTSD2SIrr
- 140642061U, // CVTTSS2SI64rm
- 139855629U, // CVTTSS2SI64rr
- 140642061U, // CVTTSS2SIrm
- 139855629U, // CVTTSS2SIrr
- 1816U, // CWD
- 1820U, // CWDE
- 268437281U, // DEC16m
- 134219553U, // DEC16r
- 402655009U, // DEC32m
- 134219553U, // DEC32r
- 268437281U, // DEC64_16m
- 134219553U, // DEC64_16r
- 402655009U, // DEC64_32m
- 134219553U, // DEC64_32r
- 536872737U, // DEC64m
- 134219553U, // DEC64r
- 671090465U, // DEC8m
- 134219553U, // DEC8r
- 268437286U, // DIV16m
- 134219558U, // DIV16r
- 402655014U, // DIV32m
- 134219558U, // DIV32r
- 536872742U, // DIV64m
- 134219558U, // DIV64r
- 671090470U, // DIV8m
- 134219558U, // DIV8r
- 139200299U, // DIVPDrm
- 138544939U, // DIVPDrr
- 139200306U, // DIVPSrm
- 138544946U, // DIVPSrr
- 805308217U, // DIVR_F32m
- 939525945U, // DIVR_F64m
- 268437312U, // DIVR_FI16m
- 402655040U, // DIVR_FI32m
- 134219592U, // DIVR_FPrST0
- 134219577U, // DIVR_FST0r
+ 1643U, // CPUID
+ 1649U, // CQO
+ 1639974517U, // CRC32m16
+ 1644168821U, // CRC32m32
+ 1648363125U, // CRC32m8
+ 1652557429U, // CRC32r16
+ 1652557429U, // CRC32r32
+ 1652557429U, // CRC32r8
+ 1656751733U, // CRC64m64
+ 1652557429U, // CRC64r64
+ 1661U, // CS_PREFIX
+ 140379776U, // CVTDQ2PDrm
+ 139855488U, // CVTDQ2PDrr
+ 140379786U, // CVTDQ2PSrm
+ 139855498U, // CVTDQ2PSrr
+ 140379796U, // CVTPD2DQrm
+ 139855508U, // CVTPD2DQrr
+ 140379806U, // CVTPD2PSrm
+ 139855518U, // CVTPD2PSrr
+ 140379816U, // CVTPS2DQrm
+ 139855528U, // CVTPS2DQrr
+ 140510898U, // CVTPS2PDrm
+ 139855538U, // CVTPS2PDrr
+ 140510908U, // CVTSD2SI64rm
+ 139855548U, // CVTSD2SI64rr
+ 140510918U, // CVTSD2SSrm
+ 139855558U, // CVTSD2SSrr
+ 140117712U, // CVTSI2SD64rm
+ 139855568U, // CVTSI2SD64rr
+ 139986640U, // CVTSI2SDrm
+ 139855568U, // CVTSI2SDrr
+ 140117722U, // CVTSI2SS64rm
+ 139855578U, // CVTSI2SS64rr
+ 139986650U, // CVTSI2SSrm
+ 139855578U, // CVTSI2SSrr
+ 140642020U, // CVTSS2SDrm
+ 139855588U, // CVTSS2SDrr
+ 140642030U, // CVTSS2SI64rm
+ 139855598U, // CVTSS2SI64rr
+ 140642030U, // CVTSS2SIrm
+ 139855598U, // CVTSS2SIrr
+ 140379896U, // CVTTPS2DQrm
+ 139855608U, // CVTTPS2DQrr
+ 140510979U, // CVTTSD2SI64rm
+ 139855619U, // CVTTSD2SI64rr
+ 140510979U, // CVTTSD2SIrm
+ 139855619U, // CVTTSD2SIrr
+ 140642062U, // CVTTSS2SI64rm
+ 139855630U, // CVTTSS2SI64rr
+ 140642062U, // CVTTSS2SIrm
+ 139855630U, // CVTTSS2SIrr
+ 1817U, // CWD
+ 1821U, // CWDE
+ 268437282U, // DEC16m
+ 134219554U, // DEC16r
+ 402655010U, // DEC32m
+ 134219554U, // DEC32r
+ 268437282U, // DEC64_16m
+ 134219554U, // DEC64_16r
+ 402655010U, // DEC64_32m
+ 134219554U, // DEC64_32r
+ 536872738U, // DEC64m
+ 134219554U, // DEC64r
+ 671090466U, // DEC8m
+ 134219554U, // DEC8r
+ 268437287U, // DIV16m
+ 134219559U, // DIV16r
+ 402655015U, // DIV32m
+ 134219559U, // DIV32r
+ 536872743U, // DIV64m
+ 134219559U, // DIV64r
+ 671090471U, // DIV8m
+ 134219559U, // DIV8r
+ 139200300U, // DIVPDrm
+ 138544940U, // DIVPDrr
+ 139200307U, // DIVPSrm
+ 138544947U, // DIVPSrr
+ 805308218U, // DIVR_F32m
+ 939525946U, // DIVR_F64m
+ 268437313U, // DIVR_FI16m
+ 402655041U, // DIVR_FI32m
+ 134219593U, // DIVR_FPrST0
+ 134219578U, // DIVR_FST0r
0U, // DIVR_Fp32m
0U, // DIVR_Fp64m
0U, // DIVR_Fp64m32
@@ -597,21 +598,21 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // DIVR_FpI32m32
0U, // DIVR_FpI32m64
0U, // DIVR_FpI32m80
- 142608185U, // DIVR_FrST0
- 139331408U, // DIVSDrm
- 139331408U, // DIVSDrm_Int
- 138544976U, // DIVSDrr
- 138544976U, // DIVSDrr_Int
- 139462487U, // DIVSSrm
- 139462487U, // DIVSSrm_Int
- 138544983U, // DIVSSrr
- 138544983U, // DIVSSrr_Int
- 805308254U, // DIV_F32m
- 939525982U, // DIV_F64m
- 268437348U, // DIV_FI16m
- 402655076U, // DIV_FI32m
- 134219627U, // DIV_FPrST0
- 134219614U, // DIV_FST0r
+ 142608186U, // DIVR_FrST0
+ 139331409U, // DIVSDrm
+ 139331409U, // DIVSDrm_Int
+ 138544977U, // DIVSDrr
+ 138544977U, // DIVSDrr_Int
+ 139462488U, // DIVSSrm
+ 139462488U, // DIVSSrm_Int
+ 138544984U, // DIVSSrr
+ 138544984U, // DIVSSrr_Int
+ 805308255U, // DIV_F32m
+ 939525983U, // DIV_F64m
+ 268437349U, // DIV_FI16m
+ 402655077U, // DIV_FI32m
+ 134219628U, // DIV_FPrST0
+ 134219615U, // DIV_FST0r
0U, // DIV_Fp32
0U, // DIV_Fp32m
0U, // DIV_Fp64
@@ -626,82 +627,84 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // DIV_FpI32m32
0U, // DIV_FpI32m64
0U, // DIV_FpI32m80
- 142608222U, // DIV_FrST0
- 139609970U, // DPPDrmi
- 138561394U, // DPPDrri
- 139609976U, // DPPSrmi
- 138561400U, // DPPSrri
- 134219646U, // EH_RETURN
- 134219646U, // EH_RETURN64
- 139855765U, // ENTER
- 809519004U, // EXTRACTPSmr
- 139872156U, // EXTRACTPSrr
- 1959U, // F2XM1
- 139855789U, // FARCALL16i
- 1744832429U, // FARCALL16m
- 139855789U, // FARCALL32i
- 1744832429U, // FARCALL32m
- 1744832429U, // FARCALL64
- 139855796U, // FARJMP16i
- 1744832436U, // FARJMP16m
- 139855796U, // FARJMP32i
- 1744832436U, // FARJMP32m
- 1744832436U, // FARJMP64
- 805308346U, // FBLDm
- 805308352U, // FBSTPm
- 805308002U, // FCOM32m
- 939525730U, // FCOM64m
- 805307964U, // FCOMP32m
- 939525692U, // FCOMP64m
- 1991U, // FCOMPP
- 1998U, // FDECSTP
- 134219734U, // FFREE
- 268437469U, // FICOM16m
- 402655197U, // FICOM32m
- 268437476U, // FICOMP16m
- 402655204U, // FICOMP32m
- 2028U, // FINCSTP
- 402655220U, // FISTTP32m
- 268437500U, // FLDCW16m
- 805308419U, // FLDENVm
- 2059U, // FLDL2E
- 2066U, // FLDL2T
- 2073U, // FLDLG2
- 2080U, // FLDLN2
- 2087U, // FLDPI
- 2093U, // FNCLEX
- 2100U, // FNINIT
- 2107U, // FNOP
- 268437568U, // FNSTCW16m
- 2120U, // FNSTSW8r
- 805308499U, // FNSTSWm
- 2139U, // FP32_TO_INT16_IN_MEM
- 2170U, // FP32_TO_INT32_IN_MEM
- 2201U, // FP32_TO_INT64_IN_MEM
- 2232U, // FP64_TO_INT16_IN_MEM
- 2263U, // FP64_TO_INT32_IN_MEM
- 2294U, // FP64_TO_INT64_IN_MEM
- 2325U, // FP80_TO_INT16_IN_MEM
- 2356U, // FP80_TO_INT32_IN_MEM
- 2387U, // FP80_TO_INT64_IN_MEM
- 2418U, // FPATAN
- 2425U, // FPREM
- 2431U, // FPREM1
- 2438U, // FPTAN
- 2444U, // FP_REG_KILL
- 2458U, // FRNDINT
- 805308834U, // FRSTORm
- 805308842U, // FSAVEm
- 2482U, // FSCALE
- 2489U, // FSINCOS
- 805308865U, // FSTENVm
- 1879050698U, // FS_MOV32rm
- 2516U, // FXAM
- 1744832985U, // FXRSTOR
- 1744832994U, // FXSAVE
- 2538U, // FXTRACT
- 2546U, // FYL2X
- 2552U, // FYL2XP1
+ 142608223U, // DIV_FrST0
+ 139609971U, // DPPDrmi
+ 138561395U, // DPPDrri
+ 139609977U, // DPPSrmi
+ 138561401U, // DPPSrri
+ 1919U, // DS_PREFIX
+ 134219650U, // EH_RETURN
+ 134219650U, // EH_RETURN64
+ 139855769U, // ENTER
+ 1952U, // ES_PREFIX
+ 809519011U, // EXTRACTPSmr
+ 139872163U, // EXTRACTPSrr
+ 1966U, // F2XM1
+ 139855796U, // FARCALL16i
+ 1744832436U, // FARCALL16m
+ 139855796U, // FARCALL32i
+ 1744832436U, // FARCALL32m
+ 1744832436U, // FARCALL64
+ 139855803U, // FARJMP16i
+ 1744832443U, // FARJMP16m
+ 139855803U, // FARJMP32i
+ 1744832443U, // FARJMP32m
+ 1744832443U, // FARJMP64
+ 805308353U, // FBLDm
+ 805308359U, // FBSTPm
+ 805308000U, // FCOM32m
+ 939525728U, // FCOM64m
+ 805307962U, // FCOMP32m
+ 939525690U, // FCOMP64m
+ 1998U, // FCOMPP
+ 2005U, // FDECSTP
+ 134219741U, // FFREE
+ 268437476U, // FICOM16m
+ 402655204U, // FICOM32m
+ 268437483U, // FICOMP16m
+ 402655211U, // FICOMP32m
+ 2035U, // FINCSTP
+ 268437499U, // FLDCW16m
+ 805308418U, // FLDENVm
+ 2058U, // FLDL2E
+ 2065U, // FLDL2T
+ 2072U, // FLDLG2
+ 2079U, // FLDLN2
+ 2086U, // FLDPI
+ 2092U, // FNCLEX
+ 2099U, // FNINIT
+ 2106U, // FNOP
+ 268437567U, // FNSTCW16m
+ 2119U, // FNSTSW8r
+ 805308498U, // FNSTSWm
+ 2138U, // FP32_TO_INT16_IN_MEM
+ 2169U, // FP32_TO_INT32_IN_MEM
+ 2200U, // FP32_TO_INT64_IN_MEM
+ 2231U, // FP64_TO_INT16_IN_MEM
+ 2262U, // FP64_TO_INT32_IN_MEM
+ 2293U, // FP64_TO_INT64_IN_MEM
+ 2324U, // FP80_TO_INT16_IN_MEM
+ 2355U, // FP80_TO_INT32_IN_MEM
+ 2386U, // FP80_TO_INT64_IN_MEM
+ 2417U, // FPATAN
+ 2424U, // FPREM
+ 2430U, // FPREM1
+ 2437U, // FPTAN
+ 2443U, // FP_REG_KILL
+ 2457U, // FRNDINT
+ 805308833U, // FRSTORm
+ 805308841U, // FSAVEm
+ 2481U, // FSCALE
+ 2488U, // FSINCOS
+ 805308864U, // FSTENVm
+ 1879050697U, // FS_MOV32rm
+ 2515U, // FS_PREFIX
+ 2518U, // FXAM
+ 1744832987U, // FXRSTOR
+ 1744832996U, // FXSAVE
+ 2540U, // FXTRACT
+ 2548U, // FYL2X
+ 2554U, // FYL2XP1
0U, // FpGET_ST0_32
0U, // FpGET_ST0_64
0U, // FpGET_ST0_80
@@ -714,49 +717,50 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // FpSET_ST1_32
0U, // FpSET_ST1_64
0U, // FpSET_ST1_80
- 139198725U, // FsANDNPDrm
- 138543365U, // FsANDNPDrr
- 139198733U, // FsANDNPSrm
- 138543373U, // FsANDNPSrr
- 139198741U, // FsANDPDrm
- 138543381U, // FsANDPDrr
- 139198748U, // FsANDPSrm
- 138543388U, // FsANDPSrr
- 140773888U, // FsFLD0SD
- 140773888U, // FsFLD0SS
- 140380678U, // FsMOVAPDrm
- 139856390U, // FsMOVAPDrr
- 140380686U, // FsMOVAPSrm
- 139856398U, // FsMOVAPSrr
- 139201046U, // FsORPDrm
- 138545686U, // FsORPDrr
- 139201052U, // FsORPSrm
- 138545692U, // FsORPSrr
- 139201058U, // FsXORPDrm
- 138545698U, // FsXORPDrr
- 139201065U, // FsXORPSrm
- 138545705U, // FsXORPSrr
- 1879050800U, // GS_MOV32rm
- 139201082U, // HADDPDrm
- 138545722U, // HADDPDrr
- 139201090U, // HADDPSrm
- 138545730U, // HADDPSrr
- 2634U, // HLT
- 139201102U, // HSUBPDrm
- 138545742U, // HSUBPDrr
- 139201110U, // HSUBPSrm
- 138545750U, // HSUBPSrr
- 268438110U, // IDIV16m
- 134220382U, // IDIV16r
- 402655838U, // IDIV32m
- 134220382U, // IDIV32r
- 536873566U, // IDIV64m
- 134220382U, // IDIV64r
- 671091294U, // IDIV8m
- 134220382U, // IDIV8r
- 268438116U, // ILD_F16m
- 402655844U, // ILD_F32m
- 536873572U, // ILD_F64m
+ 139198723U, // FsANDNPDrm
+ 138543363U, // FsANDNPDrr
+ 139198731U, // FsANDNPSrm
+ 138543371U, // FsANDNPSrr
+ 139198739U, // FsANDPDrm
+ 138543379U, // FsANDPDrr
+ 139198746U, // FsANDPSrm
+ 138543386U, // FsANDPSrr
+ 0U, // FsFLD0SD
+ 0U, // FsFLD0SS
+ 140380674U, // FsMOVAPDrm
+ 139856386U, // FsMOVAPDrr
+ 140380682U, // FsMOVAPSrm
+ 139856394U, // FsMOVAPSrr
+ 139201042U, // FsORPDrm
+ 138545682U, // FsORPDrr
+ 139201048U, // FsORPSrm
+ 138545688U, // FsORPSrr
+ 139201054U, // FsXORPDrm
+ 138545694U, // FsXORPDrr
+ 139201061U, // FsXORPSrm
+ 138545701U, // FsXORPSrr
+ 1879050796U, // GS_MOV32rm
+ 2614U, // GS_PREFIX
+ 139201081U, // HADDPDrm
+ 138545721U, // HADDPDrr
+ 139201089U, // HADDPSrm
+ 138545729U, // HADDPSrr
+ 2633U, // HLT
+ 139201101U, // HSUBPDrm
+ 138545741U, // HSUBPDrr
+ 139201109U, // HSUBPSrm
+ 138545749U, // HSUBPSrr
+ 268438109U, // IDIV16m
+ 134220381U, // IDIV16r
+ 402655837U, // IDIV32m
+ 134220381U, // IDIV32r
+ 536873565U, // IDIV64m
+ 134220381U, // IDIV64r
+ 671091293U, // IDIV8m
+ 134220381U, // IDIV8r
+ 268438115U, // ILD_F16m
+ 402655843U, // ILD_F32m
+ 536873571U, // ILD_F64m
0U, // ILD_Fp16m32
0U, // ILD_Fp16m64
0U, // ILD_Fp16m80
@@ -766,67 +770,67 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // ILD_Fp64m32
0U, // ILD_Fp64m64
0U, // ILD_Fp64m80
- 268438122U, // IMUL16m
- 134220394U, // IMUL16r
- 138676842U, // IMUL16rm
- 139741802U, // IMUL16rmi
- 139741802U, // IMUL16rmi8
- 138545770U, // IMUL16rr
- 139872874U, // IMUL16rri
- 139872874U, // IMUL16rri8
- 402655850U, // IMUL32m
- 134220394U, // IMUL32r
- 138807914U, // IMUL32rm
- 140003946U, // IMUL32rmi
- 140003946U, // IMUL32rmi8
- 138545770U, // IMUL32rr
- 139872874U, // IMUL32rri
- 139872874U, // IMUL32rri8
- 536873578U, // IMUL64m
- 134220394U, // IMUL64r
- 138938986U, // IMUL64rm
- 140135018U, // IMUL64rmi32
- 140135018U, // IMUL64rmi8
- 138545770U, // IMUL64rr
- 139872874U, // IMUL64rri32
- 139872874U, // IMUL64rri8
- 671091306U, // IMUL8m
- 134220394U, // IMUL8r
- 2672U, // IN16
- 134220404U, // IN16ri
- 2685U, // IN16rr
- 2672U, // IN32
- 134220425U, // IN32ri
- 2707U, // IN32rr
- 2672U, // IN8
- 134220448U, // IN8ri
- 2729U, // IN8rr
- 268438197U, // INC16m
- 134220469U, // INC16r
- 402655925U, // INC32m
- 134220469U, // INC32r
- 268438197U, // INC64_16m
- 134220469U, // INC64_16r
- 402655925U, // INC64_32m
- 134220469U, // INC64_32r
- 536873653U, // INC64m
- 134220469U, // INC64r
- 671091381U, // INC8m
- 134220469U, // INC8r
- 139479738U, // INSERTPSrm
- 138562234U, // INSERTPSrr
- 134220484U, // INT
- 2761U, // INT3
- 2767U, // INVD
- 2772U, // INVEPT
- 2779U, // INVLPG
+ 268438121U, // IMUL16m
+ 134220393U, // IMUL16r
+ 138676841U, // IMUL16rm
+ 139741801U, // IMUL16rmi
+ 139741801U, // IMUL16rmi8
+ 138545769U, // IMUL16rr
+ 139872873U, // IMUL16rri
+ 139872873U, // IMUL16rri8
+ 402655849U, // IMUL32m
+ 134220393U, // IMUL32r
+ 138807913U, // IMUL32rm
+ 140003945U, // IMUL32rmi
+ 140003945U, // IMUL32rmi8
+ 138545769U, // IMUL32rr
+ 139872873U, // IMUL32rri
+ 139872873U, // IMUL32rri8
+ 536873577U, // IMUL64m
+ 134220393U, // IMUL64r
+ 138938985U, // IMUL64rm
+ 140135017U, // IMUL64rmi32
+ 140135017U, // IMUL64rmi8
+ 138545769U, // IMUL64rr
+ 139872873U, // IMUL64rri32
+ 139872873U, // IMUL64rri8
+ 671091305U, // IMUL8m
+ 134220393U, // IMUL8r
+ 2671U, // IN16
+ 134220403U, // IN16ri
+ 2684U, // IN16rr
+ 2671U, // IN32
+ 134220424U, // IN32ri
+ 2706U, // IN32rr
+ 2671U, // IN8
+ 134220447U, // IN8ri
+ 2728U, // IN8rr
+ 268438196U, // INC16m
+ 134220468U, // INC16r
+ 402655924U, // INC32m
+ 134220468U, // INC32r
+ 268438196U, // INC64_16m
+ 134220468U, // INC64_16r
+ 402655924U, // INC64_32m
+ 134220468U, // INC64_32r
+ 536873652U, // INC64m
+ 134220468U, // INC64r
+ 671091380U, // INC8m
+ 134220468U, // INC8r
+ 139479737U, // INSERTPSrm
+ 138562233U, // INSERTPSrr
+ 134220483U, // INT
+ 2760U, // INT3
+ 2766U, // INVD
+ 2771U, // INVEPT
+ 671091418U, // INVLPG
2786U, // INVVPID
2794U, // IRET16
2794U, // IRET32
2794U, // IRET64
- 268437492U, // ISTT_FP16m
- 402655220U, // ISTT_FP32m
- 536872948U, // ISTT_FP64m
+ 268438255U, // ISTT_FP16m
+ 402655983U, // ISTT_FP32m
+ 536873711U, // ISTT_FP64m
0U, // ISTT_Fp16m32
0U, // ISTT_Fp16m64
0U, // ISTT_Fp16m80
@@ -836,11 +840,11 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // ISTT_Fp64m32
0U, // ISTT_Fp64m64
0U, // ISTT_Fp64m80
- 268438255U, // IST_F16m
- 402655983U, // IST_F32m
- 268438261U, // IST_FP16m
- 402655989U, // IST_FP32m
- 536873717U, // IST_FP64m
+ 268438263U, // IST_F16m
+ 402655991U, // IST_F32m
+ 268438269U, // IST_FP16m
+ 402655997U, // IST_FP32m
+ 536873725U, // IST_FP64m
0U, // IST_Fp16m32
0U, // IST_Fp16m64
0U, // IST_Fp16m80
@@ -850,135 +854,135 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // IST_Fp64m32
0U, // IST_Fp64m64
0U, // IST_Fp64m80
- 1229850115U, // Int_CMPSDrm
- 1363281411U, // Int_CMPSDrr
- 1234175491U, // Int_CMPSSrm
- 1367475715U, // Int_CMPSSrr
- 140379692U, // Int_COMISDrm
- 139855404U, // Int_COMISDrr
- 140379700U, // Int_COMISSrm
- 139855412U, // Int_COMISSrr
- 140117631U, // Int_CVTDQ2PDrm
- 139855487U, // Int_CVTDQ2PDrr
- 140904073U, // Int_CVTDQ2PSrm
- 139855497U, // Int_CVTDQ2PSrr
- 140379795U, // Int_CVTPD2DQrm
- 139855507U, // Int_CVTPD2DQrr
- 140380924U, // Int_CVTPD2PIrm
- 139856636U, // Int_CVTPD2PIrr
- 140379805U, // Int_CVTPD2PSrm
- 139855517U, // Int_CVTPD2PSrr
- 140118790U, // Int_CVTPI2PDrm
- 139856646U, // Int_CVTPI2PDrr
- 138939152U, // Int_CVTPI2PSrm
- 138545936U, // Int_CVTPI2PSrr
- 140379815U, // Int_CVTPS2DQrm
- 139855527U, // Int_CVTPS2DQrr
- 140510897U, // Int_CVTPS2PDrm
- 139855537U, // Int_CVTPS2PDrr
- 140512026U, // Int_CVTPS2PIrm
- 139856666U, // Int_CVTPS2PIrr
- 140379835U, // Int_CVTSD2SI64rm
- 139855547U, // Int_CVTSD2SI64rr
- 140379835U, // Int_CVTSD2SIrm
- 139855547U, // Int_CVTSD2SIrr
- 139331269U, // Int_CVTSD2SSrm
- 138544837U, // Int_CVTSD2SSrr
- 138938063U, // Int_CVTSI2SD64rm
- 138544847U, // Int_CVTSI2SD64rr
- 138806991U, // Int_CVTSI2SDrm
- 138544847U, // Int_CVTSI2SDrr
- 138938073U, // Int_CVTSI2SS64rm
- 138544857U, // Int_CVTSI2SS64rr
- 138807001U, // Int_CVTSI2SSrm
- 138544857U, // Int_CVTSI2SSrr
- 139462371U, // Int_CVTSS2SDrm
- 138544867U, // Int_CVTSS2SDrr
- 140642029U, // Int_CVTSS2SI64rm
- 139855597U, // Int_CVTSS2SI64rr
- 140642029U, // Int_CVTSS2SIrm
- 139855597U, // Int_CVTSS2SIrr
- 140380964U, // Int_CVTTPD2DQrm
- 139856676U, // Int_CVTTPD2DQrr
- 140380975U, // Int_CVTTPD2PIrm
- 139856687U, // Int_CVTTPD2PIrr
- 140379895U, // Int_CVTTPS2DQrm
- 139855607U, // Int_CVTTPS2DQrr
- 140512058U, // Int_CVTTPS2PIrm
- 139856698U, // Int_CVTTPS2PIrr
- 140379906U, // Int_CVTTSD2SI64rm
- 139855618U, // Int_CVTTSD2SI64rr
- 140379906U, // Int_CVTTSD2SIrm
- 139855618U, // Int_CVTTSD2SIrr
- 140642061U, // Int_CVTTSS2SI64rm
- 139855629U, // Int_CVTTSS2SI64rr
- 140642061U, // Int_CVTTSS2SIrm
- 139855629U, // Int_CVTTSS2SIrr
- 140380997U, // Int_UCOMISDrm
- 139856709U, // Int_UCOMISDrr
- 140381006U, // Int_UCOMISSrm
- 139856718U, // Int_UCOMISSrr
- 1073744727U, // JA
- 1073744727U, // JA8
- 1073744731U, // JAE
- 1073744731U, // JAE8
- 1073744736U, // JB
- 1073744736U, // JB8
- 1073744740U, // JBE
- 1073744740U, // JBE8
- 1073744745U, // JCXZ8
- 1073744751U, // JE
- 1073744751U, // JE8
- 1073744755U, // JG
- 1073744755U, // JG8
- 1073744759U, // JGE
- 1073744759U, // JGE8
- 1073744764U, // JL
- 1073744764U, // JL8
- 1073744768U, // JLE
- 1073744768U, // JLE8
- 1073744773U, // JMP
- 402656133U, // JMP32m
- 134220677U, // JMP32r
- 536873861U, // JMP64m
- 1073744773U, // JMP64pcrel32
- 134220677U, // JMP64r
- 1073744773U, // JMP8
- 1073744778U, // JNE
- 1073744778U, // JNE8
- 1073744783U, // JNO
- 1073744783U, // JNO8
- 1073744788U, // JNP
- 1073744788U, // JNP8
- 1073744793U, // JNS
- 1073744793U, // JNS8
- 1073744798U, // JO
- 1073744798U, // JO8
- 1073744802U, // JP
- 1073744802U, // JP8
- 1073744806U, // JS
- 1073744806U, // JS8
- 2986U, // LAHF
- 139725743U, // LAR16rm
- 139856815U, // LAR16rr
- 139725743U, // LAR32rm
- 139856815U, // LAR32rr
- 139725743U, // LAR64rm
- 139856815U, // LAR64rr
- 272632756U, // LCMPXCHG16
- 406850484U, // LCMPXCHG32
- 2013268931U, // LCMPXCHG64
- 675285940U, // LCMPXCHG8
- 536873939U, // LCMPXCHG8B
- 140905444U, // LDDQUrm
- 402656235U, // LDMXCSR
- 141036532U, // LDS16rm
- 141036532U, // LDS32rm
- 3065U, // LD_F0
- 3070U, // LD_F1
- 805309443U, // LD_F32m
- 939527171U, // LD_F64m
- 2147486723U, // LD_F80m
+ 1229850113U, // Int_CMPSDrm
+ 1363281409U, // Int_CMPSDrr
+ 1234175489U, // Int_CMPSSrm
+ 1367475713U, // Int_CMPSSrr
+ 140379690U, // Int_COMISDrm
+ 139855402U, // Int_COMISDrr
+ 140379698U, // Int_COMISSrm
+ 139855410U, // Int_COMISSrr
+ 140117632U, // Int_CVTDQ2PDrm
+ 139855488U, // Int_CVTDQ2PDrr
+ 140773002U, // Int_CVTDQ2PSrm
+ 139855498U, // Int_CVTDQ2PSrr
+ 140379796U, // Int_CVTPD2DQrm
+ 139855508U, // Int_CVTPD2DQrr
+ 140380932U, // Int_CVTPD2PIrm
+ 139856644U, // Int_CVTPD2PIrr
+ 140379806U, // Int_CVTPD2PSrm
+ 139855518U, // Int_CVTPD2PSrr
+ 140118798U, // Int_CVTPI2PDrm
+ 139856654U, // Int_CVTPI2PDrr
+ 138939160U, // Int_CVTPI2PSrm
+ 138545944U, // Int_CVTPI2PSrr
+ 140379816U, // Int_CVTPS2DQrm
+ 139855528U, // Int_CVTPS2DQrr
+ 140510898U, // Int_CVTPS2PDrm
+ 139855538U, // Int_CVTPS2PDrr
+ 140512034U, // Int_CVTPS2PIrm
+ 139856674U, // Int_CVTPS2PIrr
+ 140379836U, // Int_CVTSD2SI64rm
+ 139855548U, // Int_CVTSD2SI64rr
+ 140379836U, // Int_CVTSD2SIrm
+ 139855548U, // Int_CVTSD2SIrr
+ 139331270U, // Int_CVTSD2SSrm
+ 138544838U, // Int_CVTSD2SSrr
+ 138938064U, // Int_CVTSI2SD64rm
+ 138544848U, // Int_CVTSI2SD64rr
+ 138806992U, // Int_CVTSI2SDrm
+ 138544848U, // Int_CVTSI2SDrr
+ 138938074U, // Int_CVTSI2SS64rm
+ 138544858U, // Int_CVTSI2SS64rr
+ 138807002U, // Int_CVTSI2SSrm
+ 138544858U, // Int_CVTSI2SSrr
+ 139462372U, // Int_CVTSS2SDrm
+ 138544868U, // Int_CVTSS2SDrr
+ 140642030U, // Int_CVTSS2SI64rm
+ 139855598U, // Int_CVTSS2SI64rr
+ 140642030U, // Int_CVTSS2SIrm
+ 139855598U, // Int_CVTSS2SIrr
+ 140380972U, // Int_CVTTPD2DQrm
+ 139856684U, // Int_CVTTPD2DQrr
+ 140380983U, // Int_CVTTPD2PIrm
+ 139856695U, // Int_CVTTPD2PIrr
+ 140379896U, // Int_CVTTPS2DQrm
+ 139855608U, // Int_CVTTPS2DQrr
+ 140512066U, // Int_CVTTPS2PIrm
+ 139856706U, // Int_CVTTPS2PIrr
+ 140379907U, // Int_CVTTSD2SI64rm
+ 139855619U, // Int_CVTTSD2SI64rr
+ 140379907U, // Int_CVTTSD2SIrm
+ 139855619U, // Int_CVTTSD2SIrr
+ 140642062U, // Int_CVTTSS2SI64rm
+ 139855630U, // Int_CVTTSS2SI64rr
+ 140642062U, // Int_CVTTSS2SIrm
+ 139855630U, // Int_CVTTSS2SIrr
+ 140381005U, // Int_UCOMISDrm
+ 139856717U, // Int_UCOMISDrr
+ 140381014U, // Int_UCOMISSrm
+ 139856726U, // Int_UCOMISSrr
+ 1073744735U, // JAE_1
+ 1073744735U, // JAE_4
+ 1073744740U, // JA_1
+ 1073744740U, // JA_4
+ 1073744744U, // JBE_1
+ 1073744744U, // JBE_4
+ 1073744749U, // JB_1
+ 1073744749U, // JB_4
+ 1073744753U, // JCXZ8
+ 1073744759U, // JE_1
+ 1073744759U, // JE_4
+ 1073744763U, // JGE_1
+ 1073744763U, // JGE_4
+ 1073744768U, // JG_1
+ 1073744768U, // JG_4
+ 1073744772U, // JLE_1
+ 1073744772U, // JLE_4
+ 1073744777U, // JL_1
+ 1073744777U, // JL_4
+ 402656141U, // JMP32m
+ 134220685U, // JMP32r
+ 536873869U, // JMP64m
+ 1073744781U, // JMP64pcrel32
+ 134220685U, // JMP64r
+ 1073744781U, // JMP_1
+ 1073744781U, // JMP_4
+ 1073744786U, // JNE_1
+ 1073744786U, // JNE_4
+ 1073744791U, // JNO_1
+ 1073744791U, // JNO_4
+ 1073744796U, // JNP_1
+ 1073744796U, // JNP_4
+ 1073744801U, // JNS_1
+ 1073744801U, // JNS_4
+ 1073744806U, // JO_1
+ 1073744806U, // JO_4
+ 1073744810U, // JP_1
+ 1073744810U, // JP_4
+ 1073744814U, // JS_1
+ 1073744814U, // JS_4
+ 2994U, // LAHF
+ 139725751U, // LAR16rm
+ 139856823U, // LAR16rr
+ 139725751U, // LAR32rm
+ 139856823U, // LAR32rr
+ 139725751U, // LAR64rm
+ 139856823U, // LAR64rr
+ 272632764U, // LCMPXCHG16
+ 406850492U, // LCMPXCHG32
+ 2013268939U, // LCMPXCHG64
+ 675285948U, // LCMPXCHG8
+ 536873947U, // LCMPXCHG8B
+ 140774380U, // LDDQUrm
+ 402656243U, // LDMXCSR
+ 140905468U, // LDS16rm
+ 140905468U, // LDS32rm
+ 3073U, // LD_F0
+ 3078U, // LD_F1
+ 805309451U, // LD_F32m
+ 939527179U, // LD_F64m
+ 2147486731U, // LD_F80m
0U, // LD_Fp032
0U, // LD_Fp064
0U, // LD_Fp080
@@ -991,463 +995,467 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // LD_Fp64m
0U, // LD_Fp64m80
0U, // LD_Fp80m
- 134220803U, // LD_Frr
- 141167624U, // LEA16r
- 141167624U, // LEA32r
- 141298696U, // LEA64_32r
- 141429768U, // LEA64r
- 3085U, // LEAVE
- 3085U, // LEAVE64
- 141036563U, // LES16rm
- 141036563U, // LES32rm
- 3096U, // LFENCE
- 141036575U, // LFS16rm
- 141036575U, // LFS32rm
- 141036575U, // LFS64rm
- 1744833572U, // LGDTm
- 141036586U, // LGS16rm
- 141036586U, // LGS32rm
- 141036586U, // LGS64rm
- 1744833583U, // LIDTm
- 268438581U, // LLDT16m
- 134220853U, // LLDT16r
- 268438587U, // LMSW16m
- 134220859U, // LMSW16r
- 272632897U, // LOCK_ADD16mi
- 272632897U, // LOCK_ADD16mi8
- 272632897U, // LOCK_ADD16mr
- 406850625U, // LOCK_ADD32mi
- 406850625U, // LOCK_ADD32mi8
- 406850625U, // LOCK_ADD32mr
- 541068353U, // LOCK_ADD64mi32
- 541068353U, // LOCK_ADD64mi8
- 541068353U, // LOCK_ADD64mr
- 675286081U, // LOCK_ADD8mi
- 675286081U, // LOCK_ADD8mr
- 268438604U, // LOCK_DEC16m
- 402656332U, // LOCK_DEC32m
- 536874060U, // LOCK_DEC64m
- 671091788U, // LOCK_DEC8m
- 268438615U, // LOCK_INC16m
- 402656343U, // LOCK_INC32m
- 536874071U, // LOCK_INC64m
- 671091799U, // LOCK_INC8m
- 272632930U, // LOCK_SUB16mi
- 272632930U, // LOCK_SUB16mi8
- 272632930U, // LOCK_SUB16mr
- 406850658U, // LOCK_SUB32mi
- 406850658U, // LOCK_SUB32mi8
- 406850658U, // LOCK_SUB32mr
- 541068386U, // LOCK_SUB64mi32
- 541068386U, // LOCK_SUB64mi8
- 541068386U, // LOCK_SUB64mr
- 675286114U, // LOCK_SUB8mi
- 675286114U, // LOCK_SUB8mr
- 3181U, // LODSB
- 3187U, // LODSD
- 3193U, // LODSQ
- 3199U, // LODSW
- 1073745029U, // LOOP
- 1073745035U, // LOOPE
- 1073745042U, // LOOPNE
- 3226U, // LRET
- 134220959U, // LRETI
- 139725989U, // LSL16rm
- 139857061U, // LSL16rr
- 139988133U, // LSL32rm
- 139857061U, // LSL32rr
- 140119205U, // LSL64rm
- 139857061U, // LSL64rr
- 141036714U, // LSS16rm
- 141036714U, // LSS32rm
- 141036714U, // LSS64rm
- 3247U, // LTRm
- 3247U, // LTRr
- 2281704628U, // LXADD16
- 2415922356U, // LXADD32
- 1656753332U, // LXADD64
- 2550140084U, // LXADD8
- 139857088U, // MASKMOVDQU
- 139857088U, // MASKMOVDQU64
- 139201740U, // MAXPDrm
- 139201740U, // MAXPDrm_Int
- 138546380U, // MAXPDrr
- 138546380U, // MAXPDrr_Int
- 139201747U, // MAXPSrm
- 139201747U, // MAXPSrm_Int
- 138546387U, // MAXPSrr
- 138546387U, // MAXPSrr_Int
- 139332826U, // MAXSDrm
- 139332826U, // MAXSDrm_Int
- 138546394U, // MAXSDrr
- 138546394U, // MAXSDrr_Int
- 139463905U, // MAXSSrm
- 139463905U, // MAXSSrm_Int
- 138546401U, // MAXSSrr
- 138546401U, // MAXSSrr_Int
- 3304U, // MFENCE
- 139201775U, // MINPDrm
- 139201775U, // MINPDrm_Int
- 138546415U, // MINPDrr
- 138546415U, // MINPDrr_Int
- 139201782U, // MINPSrm
- 139201782U, // MINPSrm_Int
- 138546422U, // MINPSrr
- 138546422U, // MINPSrr_Int
- 139332861U, // MINSDrm
- 139332861U, // MINSDrm_Int
- 138546429U, // MINSDrr
- 138546429U, // MINSDrr_Int
- 139463940U, // MINSSrm
- 139463940U, // MINSSrm_Int
- 138546436U, // MINSSrr
- 138546436U, // MINSSrr_Int
- 140380924U, // MMX_CVTPD2PIrm
- 139856636U, // MMX_CVTPD2PIrr
- 140118790U, // MMX_CVTPI2PDrm
- 139856646U, // MMX_CVTPI2PDrr
- 140118800U, // MMX_CVTPI2PSrm
- 139856656U, // MMX_CVTPI2PSrr
- 140512026U, // MMX_CVTPS2PIrm
- 139856666U, // MMX_CVTPS2PIrr
- 140380975U, // MMX_CVTTPD2PIrm
- 139856687U, // MMX_CVTTPD2PIrr
- 140512058U, // MMX_CVTTPS2PIrm
- 139856698U, // MMX_CVTTPS2PIrr
- 3339U, // MMX_EMMS
- 3344U, // MMX_FEMMS
- 139857174U, // MMX_MASKMOVQ
- 139857174U, // MMX_MASKMOVQ64
- 139857184U, // MMX_MOVD64from64rr
- 139857184U, // MMX_MOVD64grr
- 406850848U, // MMX_MOVD64mr
- 139988256U, // MMX_MOVD64rm
- 139857184U, // MMX_MOVD64rr
- 139857184U, // MMX_MOVD64rrv164
- 139857184U, // MMX_MOVD64to64rr
- 139857190U, // MMX_MOVDQ2Qrr
- 541068591U, // MMX_MOVNTQmr
- 139857207U, // MMX_MOVQ2DQrr
- 139857207U, // MMX_MOVQ2FR64rr
- 541068608U, // MMX_MOVQ64gmr
- 541068608U, // MMX_MOVQ64mr
- 140119360U, // MMX_MOVQ64rm
- 139857216U, // MMX_MOVQ64rr
- 139988256U, // MMX_MOVZDI2PDIrm
- 139857184U, // MMX_MOVZDI2PDIrr
- 138939718U, // MMX_PACKSSDWrm
- 138546502U, // MMX_PACKSSDWrr
- 138939728U, // MMX_PACKSSWBrm
- 138546512U, // MMX_PACKSSWBrr
- 138939738U, // MMX_PACKUSWBrm
- 138546522U, // MMX_PACKUSWBrr
- 138939748U, // MMX_PADDBrm
- 138546532U, // MMX_PADDBrr
- 138939755U, // MMX_PADDDrm
- 138546539U, // MMX_PADDDrr
- 138939762U, // MMX_PADDQrm
- 138546546U, // MMX_PADDQrr
- 138939769U, // MMX_PADDSBrm
- 138546553U, // MMX_PADDSBrr
- 138939777U, // MMX_PADDSWrm
- 138546561U, // MMX_PADDSWrr
- 138939785U, // MMX_PADDUSBrm
- 138546569U, // MMX_PADDUSBrr
- 138939794U, // MMX_PADDUSWrm
- 138546578U, // MMX_PADDUSWrr
- 138939803U, // MMX_PADDWrm
- 138546587U, // MMX_PADDWrr
- 138939810U, // MMX_PANDNrm
- 138546594U, // MMX_PANDNrr
- 138939817U, // MMX_PANDrm
- 138546601U, // MMX_PANDrr
- 138939823U, // MMX_PAVGBrm
- 138546607U, // MMX_PAVGBrr
- 138939830U, // MMX_PAVGWrm
- 138546614U, // MMX_PAVGWrr
- 138939837U, // MMX_PCMPEQBrm
- 138546621U, // MMX_PCMPEQBrr
- 138939846U, // MMX_PCMPEQDrm
- 138546630U, // MMX_PCMPEQDrr
- 138939855U, // MMX_PCMPEQWrm
- 138546639U, // MMX_PCMPEQWrr
- 138939864U, // MMX_PCMPGTBrm
- 138546648U, // MMX_PCMPGTBrr
- 138939873U, // MMX_PCMPGTDrm
- 138546657U, // MMX_PCMPGTDrr
- 138939882U, // MMX_PCMPGTWrm
- 138546666U, // MMX_PCMPGTWrr
- 139873779U, // MMX_PEXTRWri
- 138694139U, // MMX_PINSRWrmi
- 138563067U, // MMX_PINSRWrri
- 138939907U, // MMX_PMADDWDrm
- 138546691U, // MMX_PMADDWDrr
- 138939916U, // MMX_PMAXSWrm
- 138546700U, // MMX_PMAXSWrr
- 138939924U, // MMX_PMAXUBrm
- 138546708U, // MMX_PMAXUBrr
- 138939932U, // MMX_PMINSWrm
- 138546716U, // MMX_PMINSWrr
- 138939940U, // MMX_PMINUBrm
- 138546724U, // MMX_PMINUBrr
- 139857452U, // MMX_PMOVMSKBrr
- 138939958U, // MMX_PMULHUWrm
- 138546742U, // MMX_PMULHUWrr
- 138939967U, // MMX_PMULHWrm
- 138546751U, // MMX_PMULHWrr
- 138939975U, // MMX_PMULLWrm
- 138546759U, // MMX_PMULLWrr
- 138939983U, // MMX_PMULUDQrm
- 138546767U, // MMX_PMULUDQrr
- 138939992U, // MMX_PORrm
- 138546776U, // MMX_PORrr
- 138939997U, // MMX_PSADBWrm
- 138546781U, // MMX_PSADBWrr
- 140136037U, // MMX_PSHUFWmi
- 139873893U, // MMX_PSHUFWri
- 138546797U, // MMX_PSLLDri
- 138940013U, // MMX_PSLLDrm
- 138546797U, // MMX_PSLLDrr
- 138546804U, // MMX_PSLLQri
- 138940020U, // MMX_PSLLQrm
- 138546804U, // MMX_PSLLQrr
- 138546811U, // MMX_PSLLWri
- 138940027U, // MMX_PSLLWrm
- 138546811U, // MMX_PSLLWrr
- 138546818U, // MMX_PSRADri
- 138940034U, // MMX_PSRADrm
- 138546818U, // MMX_PSRADrr
- 138546825U, // MMX_PSRAWri
- 138940041U, // MMX_PSRAWrm
- 138546825U, // MMX_PSRAWrr
- 138546832U, // MMX_PSRLDri
- 138940048U, // MMX_PSRLDrm
- 138546832U, // MMX_PSRLDrr
- 138546839U, // MMX_PSRLQri
- 138940055U, // MMX_PSRLQrm
- 138546839U, // MMX_PSRLQrr
- 138546846U, // MMX_PSRLWri
- 138940062U, // MMX_PSRLWrm
- 138546846U, // MMX_PSRLWrr
- 138940069U, // MMX_PSUBBrm
- 138546853U, // MMX_PSUBBrr
- 138940076U, // MMX_PSUBDrm
- 138546860U, // MMX_PSUBDrr
- 138940083U, // MMX_PSUBQrm
- 138546867U, // MMX_PSUBQrr
- 138940090U, // MMX_PSUBSBrm
- 138546874U, // MMX_PSUBSBrr
- 138940098U, // MMX_PSUBSWrm
- 138546882U, // MMX_PSUBSWrr
- 138940106U, // MMX_PSUBUSBrm
- 138546890U, // MMX_PSUBUSBrr
- 138940115U, // MMX_PSUBUSWrm
- 138546899U, // MMX_PSUBUSWrr
- 138940124U, // MMX_PSUBWrm
- 138546908U, // MMX_PSUBWrr
- 138940131U, // MMX_PUNPCKHBWrm
- 138546915U, // MMX_PUNPCKHBWrr
- 138940142U, // MMX_PUNPCKHDQrm
- 138546926U, // MMX_PUNPCKHDQrr
- 138940153U, // MMX_PUNPCKHWDrm
- 138546937U, // MMX_PUNPCKHWDrr
- 138940164U, // MMX_PUNPCKLBWrm
- 138546948U, // MMX_PUNPCKLBWrr
- 138940175U, // MMX_PUNPCKLDQrm
- 138546959U, // MMX_PUNPCKLDQrr
- 138940186U, // MMX_PUNPCKLWDrm
- 138546970U, // MMX_PUNPCKLWDrr
- 138938880U, // MMX_PXORrm
- 138545664U, // MMX_PXORrr
- 140773888U, // MMX_V_SET0
- 140774854U, // MMX_V_SETALLONES
- 3877U, // MONITOR
- 1124077357U, // MOV16ao16
- 272633645U, // MOV16mi
- 272633645U, // MOV16mr
- 272633645U, // MOV16ms
- 1073745714U, // MOV16o16a
+ 134220811U, // LD_Frr
+ 141036560U, // LEA16r
+ 141036560U, // LEA32r
+ 141167632U, // LEA64_32r
+ 141298704U, // LEA64r
+ 3093U, // LEAVE
+ 3093U, // LEAVE64
+ 140905499U, // LES16rm
+ 140905499U, // LES32rm
+ 3104U, // LFENCE
+ 140905511U, // LFS16rm
+ 140905511U, // LFS32rm
+ 140905511U, // LFS64rm
+ 1744833580U, // LGDTm
+ 140905522U, // LGS16rm
+ 140905522U, // LGS32rm
+ 140905522U, // LGS64rm
+ 1744833591U, // LIDTm
+ 268438589U, // LLDT16m
+ 134220861U, // LLDT16r
+ 268438595U, // LMSW16m
+ 134220867U, // LMSW16r
+ 272632905U, // LOCK_ADD16mi
+ 272632905U, // LOCK_ADD16mi8
+ 272632905U, // LOCK_ADD16mr
+ 406850633U, // LOCK_ADD32mi
+ 406850633U, // LOCK_ADD32mi8
+ 406850633U, // LOCK_ADD32mr
+ 541068361U, // LOCK_ADD64mi32
+ 541068361U, // LOCK_ADD64mi8
+ 541068361U, // LOCK_ADD64mr
+ 675286089U, // LOCK_ADD8mi
+ 675286089U, // LOCK_ADD8mr
+ 268438612U, // LOCK_DEC16m
+ 402656340U, // LOCK_DEC32m
+ 536874068U, // LOCK_DEC64m
+ 671091796U, // LOCK_DEC8m
+ 268438623U, // LOCK_INC16m
+ 402656351U, // LOCK_INC32m
+ 536874079U, // LOCK_INC64m
+ 671091807U, // LOCK_INC8m
+ 3178U, // LOCK_PREFIX
+ 272632943U, // LOCK_SUB16mi
+ 272632943U, // LOCK_SUB16mi8
+ 272632943U, // LOCK_SUB16mr
+ 406850671U, // LOCK_SUB32mi
+ 406850671U, // LOCK_SUB32mi8
+ 406850671U, // LOCK_SUB32mr
+ 541068399U, // LOCK_SUB64mi32
+ 541068399U, // LOCK_SUB64mi8
+ 541068399U, // LOCK_SUB64mr
+ 675286127U, // LOCK_SUB8mi
+ 675286127U, // LOCK_SUB8mr
+ 3194U, // LODSB
+ 3200U, // LODSD
+ 3206U, // LODSQ
+ 3212U, // LODSW
+ 1073745042U, // LOOP
+ 1073745048U, // LOOPE
+ 1073745055U, // LOOPNE
+ 3239U, // LRET
+ 134220972U, // LRETI
+ 139726002U, // LSL16rm
+ 139857074U, // LSL16rr
+ 139988146U, // LSL32rm
+ 139857074U, // LSL32rr
+ 140119218U, // LSL64rm
+ 139857074U, // LSL64rr
+ 140905655U, // LSS16rm
+ 140905655U, // LSS32rm
+ 140905655U, // LSS64rm
+ 3260U, // LTRm
+ 3260U, // LTRr
+ 2281704641U, // LXADD16
+ 2415922369U, // LXADD32
+ 1656753345U, // LXADD64
+ 2550140097U, // LXADD8
+ 139857101U, // MASKMOVDQU
+ 139857101U, // MASKMOVDQU64
+ 139201753U, // MAXPDrm
+ 139201753U, // MAXPDrm_Int
+ 138546393U, // MAXPDrr
+ 138546393U, // MAXPDrr_Int
+ 139201760U, // MAXPSrm
+ 139201760U, // MAXPSrm_Int
+ 138546400U, // MAXPSrr
+ 138546400U, // MAXPSrr_Int
+ 139332839U, // MAXSDrm
+ 139332839U, // MAXSDrm_Int
+ 138546407U, // MAXSDrr
+ 138546407U, // MAXSDrr_Int
+ 139463918U, // MAXSSrm
+ 139463918U, // MAXSSrm_Int
+ 138546414U, // MAXSSrr
+ 138546414U, // MAXSSrr_Int
+ 3317U, // MFENCE
+ 139201788U, // MINPDrm
+ 139201788U, // MINPDrm_Int
+ 138546428U, // MINPDrr
+ 138546428U, // MINPDrr_Int
+ 139201795U, // MINPSrm
+ 139201795U, // MINPSrm_Int
+ 138546435U, // MINPSrr
+ 138546435U, // MINPSrr_Int
+ 139332874U, // MINSDrm
+ 139332874U, // MINSDrm_Int
+ 138546442U, // MINSDrr
+ 138546442U, // MINSDrr_Int
+ 139463953U, // MINSSrm
+ 139463953U, // MINSSrm_Int
+ 138546449U, // MINSSrr
+ 138546449U, // MINSSrr_Int
+ 140380932U, // MMX_CVTPD2PIrm
+ 139856644U, // MMX_CVTPD2PIrr
+ 140118798U, // MMX_CVTPI2PDrm
+ 139856654U, // MMX_CVTPI2PDrr
+ 140118808U, // MMX_CVTPI2PSrm
+ 139856664U, // MMX_CVTPI2PSrr
+ 140512034U, // MMX_CVTPS2PIrm
+ 139856674U, // MMX_CVTPS2PIrr
+ 140380983U, // MMX_CVTTPD2PIrm
+ 139856695U, // MMX_CVTTPD2PIrr
+ 140512066U, // MMX_CVTTPS2PIrm
+ 139856706U, // MMX_CVTTPS2PIrr
+ 3352U, // MMX_EMMS
+ 3357U, // MMX_FEMMS
+ 139857187U, // MMX_MASKMOVQ
+ 139857187U, // MMX_MASKMOVQ64
+ 139857197U, // MMX_MOVD64from64rr
+ 139857197U, // MMX_MOVD64grr
+ 406850861U, // MMX_MOVD64mr
+ 139988269U, // MMX_MOVD64rm
+ 139857197U, // MMX_MOVD64rr
+ 139857197U, // MMX_MOVD64rrv164
+ 139857197U, // MMX_MOVD64to64rr
+ 139857203U, // MMX_MOVDQ2Qrr
+ 541068604U, // MMX_MOVNTQmr
+ 139857220U, // MMX_MOVQ2DQrr
+ 139857220U, // MMX_MOVQ2FR64rr
+ 541068621U, // MMX_MOVQ64gmr
+ 541068621U, // MMX_MOVQ64mr
+ 140119373U, // MMX_MOVQ64rm
+ 139857229U, // MMX_MOVQ64rr
+ 139988269U, // MMX_MOVZDI2PDIrm
+ 139857197U, // MMX_MOVZDI2PDIrr
+ 138939731U, // MMX_PACKSSDWrm
+ 138546515U, // MMX_PACKSSDWrr
+ 138939741U, // MMX_PACKSSWBrm
+ 138546525U, // MMX_PACKSSWBrr
+ 138939751U, // MMX_PACKUSWBrm
+ 138546535U, // MMX_PACKUSWBrr
+ 138939761U, // MMX_PADDBrm
+ 138546545U, // MMX_PADDBrr
+ 138939768U, // MMX_PADDDrm
+ 138546552U, // MMX_PADDDrr
+ 138939775U, // MMX_PADDQrm
+ 138546559U, // MMX_PADDQrr
+ 138939782U, // MMX_PADDSBrm
+ 138546566U, // MMX_PADDSBrr
+ 138939790U, // MMX_PADDSWrm
+ 138546574U, // MMX_PADDSWrr
+ 138939798U, // MMX_PADDUSBrm
+ 138546582U, // MMX_PADDUSBrr
+ 138939807U, // MMX_PADDUSWrm
+ 138546591U, // MMX_PADDUSWrr
+ 138939816U, // MMX_PADDWrm
+ 138546600U, // MMX_PADDWrr
+ 138939823U, // MMX_PANDNrm
+ 138546607U, // MMX_PANDNrr
+ 138939830U, // MMX_PANDrm
+ 138546614U, // MMX_PANDrr
+ 138939836U, // MMX_PAVGBrm
+ 138546620U, // MMX_PAVGBrr
+ 138939843U, // MMX_PAVGWrm
+ 138546627U, // MMX_PAVGWrr
+ 138939850U, // MMX_PCMPEQBrm
+ 138546634U, // MMX_PCMPEQBrr
+ 138939859U, // MMX_PCMPEQDrm
+ 138546643U, // MMX_PCMPEQDrr
+ 138939868U, // MMX_PCMPEQWrm
+ 138546652U, // MMX_PCMPEQWrr
+ 138939877U, // MMX_PCMPGTBrm
+ 138546661U, // MMX_PCMPGTBrr
+ 138939886U, // MMX_PCMPGTDrm
+ 138546670U, // MMX_PCMPGTDrr
+ 138939895U, // MMX_PCMPGTWrm
+ 138546679U, // MMX_PCMPGTWrr
+ 139873792U, // MMX_PEXTRWri
+ 138694152U, // MMX_PINSRWrmi
+ 138563080U, // MMX_PINSRWrri
+ 138939920U, // MMX_PMADDWDrm
+ 138546704U, // MMX_PMADDWDrr
+ 138939929U, // MMX_PMAXSWrm
+ 138546713U, // MMX_PMAXSWrr
+ 138939937U, // MMX_PMAXUBrm
+ 138546721U, // MMX_PMAXUBrr
+ 138939945U, // MMX_PMINSWrm
+ 138546729U, // MMX_PMINSWrr
+ 138939953U, // MMX_PMINUBrm
+ 138546737U, // MMX_PMINUBrr
+ 139857465U, // MMX_PMOVMSKBrr
+ 138939971U, // MMX_PMULHUWrm
+ 138546755U, // MMX_PMULHUWrr
+ 138939980U, // MMX_PMULHWrm
+ 138546764U, // MMX_PMULHWrr
+ 138939988U, // MMX_PMULLWrm
+ 138546772U, // MMX_PMULLWrr
+ 138939996U, // MMX_PMULUDQrm
+ 138546780U, // MMX_PMULUDQrr
+ 138940005U, // MMX_PORrm
+ 138546789U, // MMX_PORrr
+ 138940010U, // MMX_PSADBWrm
+ 138546794U, // MMX_PSADBWrr
+ 140136050U, // MMX_PSHUFWmi
+ 139873906U, // MMX_PSHUFWri
+ 138546810U, // MMX_PSLLDri
+ 138940026U, // MMX_PSLLDrm
+ 138546810U, // MMX_PSLLDrr
+ 138546817U, // MMX_PSLLQri
+ 138940033U, // MMX_PSLLQrm
+ 138546817U, // MMX_PSLLQrr
+ 138546824U, // MMX_PSLLWri
+ 138940040U, // MMX_PSLLWrm
+ 138546824U, // MMX_PSLLWrr
+ 138546831U, // MMX_PSRADri
+ 138940047U, // MMX_PSRADrm
+ 138546831U, // MMX_PSRADrr
+ 138546838U, // MMX_PSRAWri
+ 138940054U, // MMX_PSRAWrm
+ 138546838U, // MMX_PSRAWrr
+ 138546845U, // MMX_PSRLDri
+ 138940061U, // MMX_PSRLDrm
+ 138546845U, // MMX_PSRLDrr
+ 138546852U, // MMX_PSRLQri
+ 138940068U, // MMX_PSRLQrm
+ 138546852U, // MMX_PSRLQrr
+ 138546859U, // MMX_PSRLWri
+ 138940075U, // MMX_PSRLWrm
+ 138546859U, // MMX_PSRLWrr
+ 138940082U, // MMX_PSUBBrm
+ 138546866U, // MMX_PSUBBrr
+ 138940089U, // MMX_PSUBDrm
+ 138546873U, // MMX_PSUBDrr
+ 138940096U, // MMX_PSUBQrm
+ 138546880U, // MMX_PSUBQrr
+ 138940103U, // MMX_PSUBSBrm
+ 138546887U, // MMX_PSUBSBrr
+ 138940111U, // MMX_PSUBSWrm
+ 138546895U, // MMX_PSUBSWrr
+ 138940119U, // MMX_PSUBUSBrm
+ 138546903U, // MMX_PSUBUSBrr
+ 138940128U, // MMX_PSUBUSWrm
+ 138546912U, // MMX_PSUBUSWrr
+ 138940137U, // MMX_PSUBWrm
+ 138546921U, // MMX_PSUBWrr
+ 138940144U, // MMX_PUNPCKHBWrm
+ 138546928U, // MMX_PUNPCKHBWrr
+ 138940155U, // MMX_PUNPCKHDQrm
+ 138546939U, // MMX_PUNPCKHDQrr
+ 138940166U, // MMX_PUNPCKHWDrm
+ 138546950U, // MMX_PUNPCKHWDrr
+ 138940177U, // MMX_PUNPCKLBWrm
+ 138546961U, // MMX_PUNPCKLBWrr
+ 138940188U, // MMX_PUNPCKLDQrm
+ 138546972U, // MMX_PUNPCKLDQrr
+ 138940199U, // MMX_PUNPCKLWDrm
+ 138546983U, // MMX_PUNPCKLWDrr
+ 138940210U, // MMX_PXORrm
+ 138546994U, // MMX_PXORrr
+ 0U, // MMX_V_SET0
+ 0U, // MMX_V_SETALLONES
+ 3896U, // MONITOR
+ 1124077376U, // MOV16ao16
+ 272633664U, // MOV16mi
+ 272633664U, // MOV16mr
+ 272633664U, // MOV16ms
+ 1073745733U, // MOV16o16a
0U, // MOV16r0
- 139857709U, // MOV16ri
- 139726637U, // MOV16rm
- 139857709U, // MOV16rr
- 139857709U, // MOV16rr_REV
- 139857709U, // MOV16rs
- 139726637U, // MOV16sm
- 139857709U, // MOV16sr
- 1128271661U, // MOV32ao32
- 139857709U, // MOV32cr
- 139857709U, // MOV32dr
- 406851373U, // MOV32mi
- 406851373U, // MOV32mr
- 1073745724U, // MOV32o32a
- 140775239U, // MOV32r0
- 139857709U, // MOV32rc
- 139857709U, // MOV32rd
- 139857709U, // MOV32ri
- 139988781U, // MOV32rm
- 139857709U, // MOV32rr
- 139857709U, // MOV32rr_REV
- 2684358476U, // MOV64FSrm
- 2684358486U, // MOV64GSrm
- 1132465965U, // MOV64ao64
- 1132465965U, // MOV64ao8
- 139857709U, // MOV64cr
- 139857709U, // MOV64dr
- 541069101U, // MOV64mi32
- 541069101U, // MOV64mr
- 541069101U, // MOV64ms
- 1073745760U, // MOV64o64a
- 1073745760U, // MOV64o8a
+ 139857728U, // MOV16ri
+ 139726656U, // MOV16rm
+ 139857728U, // MOV16rr
+ 139857728U, // MOV16rr_REV
+ 139857728U, // MOV16rs
+ 139726656U, // MOV16sm
+ 139857728U, // MOV16sr
+ 1128271680U, // MOV32ao32
+ 139857728U, // MOV32cr
+ 139857728U, // MOV32dr
+ 406851392U, // MOV32mi
+ 406851392U, // MOV32mr
+ 1073745743U, // MOV32o32a
+ 0U, // MOV32r0
+ 139857728U, // MOV32rc
+ 139857728U, // MOV32rd
+ 139857728U, // MOV32ri
+ 139988800U, // MOV32rm
+ 139857728U, // MOV32rr
+ 139857728U, // MOV32rr_REV
+ 2684358490U, // MOV64FSrm
+ 2684358500U, // MOV64GSrm
+ 1132465984U, // MOV64ao64
+ 1132465984U, // MOV64ao8
+ 139857728U, // MOV64cr
+ 139857728U, // MOV64dr
+ 541069120U, // MOV64mi32
+ 541069120U, // MOV64mr
+ 541069120U, // MOV64ms
+ 1073745774U, // MOV64o64a
+ 1073745774U, // MOV64o8a
0U, // MOV64r0
- 139857709U, // MOV64rc
- 139857709U, // MOV64rd
- 139857771U, // MOV64ri
- 139857709U, // MOV64ri32
+ 139857728U, // MOV64rc
+ 139857728U, // MOV64rd
+ 139857785U, // MOV64ri
+ 139857728U, // MOV64ri32
0U, // MOV64ri64i32
- 140119853U, // MOV64rm
- 139857709U, // MOV64rr
- 139857709U, // MOV64rr_REV
- 139857709U, // MOV64rs
- 140119853U, // MOV64sm
- 139857709U, // MOV64sr
- 139857216U, // MOV64toPQIrr
- 140119360U, // MOV64toSDrm
- 139857216U, // MOV64toSDrr
- 1136660269U, // MOV8ao8
- 675286829U, // MOV8mi
- 675286829U, // MOV8mr
- 675335981U, // MOV8mr_NOREX
- 1073745779U, // MOV8o8a
- 140775239U, // MOV8r0
- 139857709U, // MOV8ri
- 140250925U, // MOV8rm
- 140300077U, // MOV8rm_NOREX
- 139857709U, // MOV8rr
- 139906861U, // MOV8rr_NOREX
- 139857709U, // MOV8rr_REV
- 2818574854U, // MOVAPDmr
- 140380678U, // MOVAPDrm
- 139856390U, // MOVAPDrr
- 2818574862U, // MOVAPSmr
- 140380686U, // MOVAPSrm
- 139856398U, // MOVAPSrr
- 140513149U, // MOVDDUPrm
- 139857789U, // MOVDDUPrr
- 139988256U, // MOVDI2PDIrm
- 139857184U, // MOVDI2PDIrr
- 139988256U, // MOVDI2SSrm
- 139857184U, // MOVDI2SSrr
- 1480593286U, // MOVDQAmr
- 140906374U, // MOVDQArm
- 139857798U, // MOVDQArr
- 1480593294U, // MOVDQUmr
- 1480593294U, // MOVDQUmr_Int
- 140906382U, // MOVDQUrm
- 140906382U, // MOVDQUrm_Int
- 138547094U, // MOVHLPSrr
- 943722399U, // MOVHPDmr
- 139333535U, // MOVHPDrm
- 943722407U, // MOVHPSmr
- 139333543U, // MOVHPSrm
- 138547119U, // MOVLHPSrr
- 943722424U, // MOVLPDmr
- 139333560U, // MOVLPDrm
- 138547136U, // MOVLPDrr
- 943722439U, // MOVLPSmr
- 139333575U, // MOVLPSrm
- 138547151U, // MOVLPSrr
- 541068608U, // MOVLQ128mr
- 138547136U, // MOVLSD2PDrr
- 138547151U, // MOVLSS2PSrr
- 139857878U, // MOVMSKPDrr
- 139857888U, // MOVMSKPSrr
- 140906474U, // MOVNTDQArm
- 2818576372U, // MOVNTDQmr
- 406851581U, // MOVNTImr
- 1480593413U, // MOVNTPDmr
- 1480593422U, // MOVNTPSmr
+ 140119872U, // MOV64rm
+ 139857728U, // MOV64rr
+ 139857728U, // MOV64rr_REV
+ 139857728U, // MOV64rs
+ 140119872U, // MOV64sm
+ 139857728U, // MOV64sr
+ 139857229U, // MOV64toPQIrr
+ 140119373U, // MOV64toSDrm
+ 139857229U, // MOV64toSDrr
+ 1136660288U, // MOV8ao8
+ 675286848U, // MOV8mi
+ 675286848U, // MOV8mr
+ 675336000U, // MOV8mr_NOREX
+ 1073745793U, // MOV8o8a
+ 0U, // MOV8r0
+ 139857728U, // MOV8ri
+ 140250944U, // MOV8rm
+ 140300096U, // MOV8rm_NOREX
+ 139857728U, // MOV8rr
+ 139906880U, // MOV8rr_NOREX
+ 139857728U, // MOV8rr_REV
+ 2818574850U, // MOVAPDmr
+ 140380674U, // MOVAPDrm
+ 139856386U, // MOVAPDrr
+ 2818574858U, // MOVAPSmr
+ 140380682U, // MOVAPSrm
+ 139856394U, // MOVAPSrr
+ 140513163U, // MOVDDUPrm
+ 139857803U, // MOVDDUPrr
+ 139988269U, // MOVDI2PDIrm
+ 139857197U, // MOVDI2PDIrr
+ 139988269U, // MOVDI2SSrm
+ 139857197U, // MOVDI2SSrr
+ 1480593300U, // MOVDQAmr
+ 140775316U, // MOVDQArm
+ 139857812U, // MOVDQArr
+ 1480593308U, // MOVDQUmr
+ 1480593308U, // MOVDQUmr_Int
+ 140775324U, // MOVDQUrm
+ 140775324U, // MOVDQUrm_Int
+ 138547108U, // MOVHLPSrr
+ 943722413U, // MOVHPDmr
+ 139333549U, // MOVHPDrm
+ 943722421U, // MOVHPSmr
+ 139333557U, // MOVHPSrm
+ 138547133U, // MOVLHPSrr
+ 943722438U, // MOVLPDmr
+ 139333574U, // MOVLPDrm
+ 138547150U, // MOVLPDrr
+ 943722453U, // MOVLPSmr
+ 139333589U, // MOVLPSrm
+ 138547165U, // MOVLPSrr
+ 541068621U, // MOVLQ128mr
+ 138547150U, // MOVLSD2PDrr
+ 138547165U, // MOVLSS2PSrr
+ 139857892U, // MOVMSKPDrr
+ 139857902U, // MOVMSKPSrr
+ 140775416U, // MOVNTDQArm
+ 2818576386U, // MOVNTDQmr
+ 406851595U, // MOVNTImr
+ 1480593427U, // MOVNTPDmr
+ 1480593436U, // MOVNTPSmr
0U, // MOVPC32r
- 943722432U, // MOVPD2SDmr
- 139857856U, // MOVPD2SDrr
- 406850848U, // MOVPDI2DImr
- 139857184U, // MOVPDI2DIrr
- 541068608U, // MOVPQI2QImr
- 139857216U, // MOVPQIto64rr
- 809504719U, // MOVPS2SSmr
- 139857871U, // MOVPS2SSrr
- 140119360U, // MOVQI2PQIrm
- 139857216U, // MOVQxrxr
- 140513216U, // MOVSD2PDrm
- 139857856U, // MOVSD2PDrr
- 943722432U, // MOVSDmr
- 140513216U, // MOVSDrm
- 139857856U, // MOVSDrr
- 541068608U, // MOVSDto64mr
- 139857216U, // MOVSDto64rr
- 140382231U, // MOVSHDUPrm
- 139857943U, // MOVSHDUPrr
- 140382241U, // MOVSLDUPrm
- 139857953U, // MOVSLDUPrr
- 406850848U, // MOVSS2DImr
- 139857184U, // MOVSS2DIrr
- 140644303U, // MOVSS2PSrm
- 139857871U, // MOVSS2PSrr
- 809504719U, // MOVSSmr
- 140644303U, // MOVSSrm
- 139857871U, // MOVSSrr
+ 943722446U, // MOVPD2SDmr
+ 139857870U, // MOVPD2SDrr
+ 406850861U, // MOVPDI2DImr
+ 139857197U, // MOVPDI2DIrr
+ 541068621U, // MOVPQI2QImr
+ 139857229U, // MOVPQIto64rr
+ 809504733U, // MOVPS2SSmr
+ 139857885U, // MOVPS2SSrr
+ 140119373U, // MOVQI2PQIrm
+ 139857229U, // MOVQxrxr
+ 4133U, // MOVSB
+ 4134U, // MOVSD
+ 140513230U, // MOVSD2PDrm
+ 139857870U, // MOVSD2PDrr
+ 943722446U, // MOVSDmr
+ 140513230U, // MOVSDrm
+ 139857870U, // MOVSDrr
+ 541068621U, // MOVSDto64mr
+ 139857229U, // MOVSDto64rr
+ 140382252U, // MOVSHDUPrm
+ 139857964U, // MOVSHDUPrr
+ 140382262U, // MOVSLDUPrm
+ 139857974U, // MOVSLDUPrr
+ 406850861U, // MOVSS2DImr
+ 139857197U, // MOVSS2DIrr
+ 140644317U, // MOVSS2PSrm
+ 139857885U, // MOVSS2PSrr
+ 809504733U, // MOVSSmr
+ 140644317U, // MOVSSrm
+ 139857885U, // MOVSSrr
+ 4133U, // MOVSW
0U, // MOVSX16rm8
- 140251179U, // MOVSX16rm8W
+ 140251200U, // MOVSX16rm8W
0U, // MOVSX16rr8
- 139857963U, // MOVSX16rr8W
- 139726891U, // MOVSX32rm16
- 140251179U, // MOVSX32rm8
- 139857963U, // MOVSX32rr16
- 139857963U, // MOVSX32rr8
- 139726891U, // MOVSX64rm16
- 139989042U, // MOVSX64rm32
- 140251179U, // MOVSX64rm8
- 139857963U, // MOVSX64rr16
- 139857970U, // MOVSX64rr32
- 139857963U, // MOVSX64rr8
- 2818576442U, // MOVUPDmr
- 2818576442U, // MOVUPDmr_Int
- 140382266U, // MOVUPDrm
- 140382266U, // MOVUPDrm_Int
- 139857978U, // MOVUPDrr
- 2818576450U, // MOVUPSmr
- 2818576450U, // MOVUPSmr_Int
- 140382274U, // MOVUPSrm
- 140382274U, // MOVUPSrm_Int
- 139857986U, // MOVUPSrr
- 139988256U, // MOVZDI2PDIrm
- 139857184U, // MOVZDI2PDIrr
- 140905792U, // MOVZPQILo2PQIrm
- 139857216U, // MOVZPQILo2PQIrr
- 140119360U, // MOVZQI2PQIrm
- 139857216U, // MOVZQI2PQIrr
- 140513216U, // MOVZSD2PDrm
- 140644303U, // MOVZSS2PSrm
+ 139857984U, // MOVSX16rr8W
+ 139726912U, // MOVSX32rm16
+ 140251200U, // MOVSX32rm8
+ 139857984U, // MOVSX32rr16
+ 139857984U, // MOVSX32rr8
+ 139726912U, // MOVSX64rm16
+ 139989063U, // MOVSX64rm32
+ 140251200U, // MOVSX64rm8
+ 139857984U, // MOVSX64rr16
+ 139857991U, // MOVSX64rr32
+ 139857984U, // MOVSX64rr8
+ 2818576463U, // MOVUPDmr
+ 2818576463U, // MOVUPDmr_Int
+ 140382287U, // MOVUPDrm
+ 140382287U, // MOVUPDrm_Int
+ 139857999U, // MOVUPDrr
+ 2818576471U, // MOVUPSmr
+ 2818576471U, // MOVUPSmr_Int
+ 140382295U, // MOVUPSrm
+ 140382295U, // MOVUPSrm_Int
+ 139858007U, // MOVUPSrr
+ 139988269U, // MOVZDI2PDIrm
+ 139857197U, // MOVZDI2PDIrr
+ 140774733U, // MOVZPQILo2PQIrm
+ 139857229U, // MOVZPQILo2PQIrr
+ 140119373U, // MOVZQI2PQIrm
+ 139857229U, // MOVZQI2PQIrr
+ 140513230U, // MOVZSD2PDrm
+ 140644317U, // MOVZSS2PSrm
0U, // MOVZX16rm8
- 140251210U, // MOVZX16rm8W
+ 140251231U, // MOVZX16rm8W
0U, // MOVZX16rr8
- 139857994U, // MOVZX16rr8W
- 140300362U, // MOVZX32_NOREXrm8
- 139907146U, // MOVZX32_NOREXrr8
- 139726922U, // MOVZX32rm16
- 140251210U, // MOVZX32rm8
- 139857994U, // MOVZX32rr16
- 139857994U, // MOVZX32rr8
+ 139858015U, // MOVZX16rr8W
+ 140300383U, // MOVZX32_NOREXrm8
+ 139907167U, // MOVZX32_NOREXrr8
+ 139726943U, // MOVZX32rm16
+ 140251231U, // MOVZX32rm8
+ 139858015U, // MOVZX32rr16
+ 139858015U, // MOVZX32rr8
0U, // MOVZX64rm16
- 139726922U, // MOVZX64rm16_Q
+ 139726943U, // MOVZX64rm16_Q
0U, // MOVZX64rm32
0U, // MOVZX64rm8
- 140251210U, // MOVZX64rm8_Q
+ 140251231U, // MOVZX64rm8_Q
0U, // MOVZX64rr16
- 139857994U, // MOVZX64rr16_Q
+ 139858015U, // MOVZX64rr16_Q
0U, // MOVZX64rr32
0U, // MOVZX64rr8
- 139857994U, // MOVZX64rr8_Q
+ 139858015U, // MOVZX64rr8_Q
0U, // MOV_Fp3232
0U, // MOV_Fp3264
0U, // MOV_Fp3280
@@ -1457,34 +1465,34 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // MOV_Fp8032
0U, // MOV_Fp8064
0U, // MOV_Fp8080
- 139612241U, // MPSADBWrmi
- 138563665U, // MPSADBWrri
- 268439642U, // MUL16m
- 134221914U, // MUL16r
- 402657370U, // MUL32m
- 134221914U, // MUL32r
- 536875098U, // MUL64m
- 134221914U, // MUL64r
- 671092826U, // MUL8m
- 134221914U, // MUL8r
- 139202655U, // MULPDrm
- 138547295U, // MULPDrr
- 139202662U, // MULPSrm
- 138547302U, // MULPSrr
- 139333741U, // MULSDrm
- 139333741U, // MULSDrm_Int
- 138547309U, // MULSDrr
- 138547309U, // MULSDrr_Int
- 139464820U, // MULSSrm
- 139464820U, // MULSSrm_Int
- 138547316U, // MULSSrr
- 138547316U, // MULSSrr_Int
- 805310587U, // MUL_F32m
- 939528315U, // MUL_F64m
- 268439681U, // MUL_FI16m
- 402657409U, // MUL_FI32m
- 134221960U, // MUL_FPrST0
- 134221947U, // MUL_FST0r
+ 139612262U, // MPSADBWrmi
+ 138563686U, // MPSADBWrri
+ 268439663U, // MUL16m
+ 134221935U, // MUL16r
+ 402657391U, // MUL32m
+ 134221935U, // MUL32r
+ 536875119U, // MUL64m
+ 134221935U, // MUL64r
+ 671092847U, // MUL8m
+ 134221935U, // MUL8r
+ 139202676U, // MULPDrm
+ 138547316U, // MULPDrr
+ 139202683U, // MULPSrm
+ 138547323U, // MULPSrr
+ 139333762U, // MULSDrm
+ 139333762U, // MULSDrm_Int
+ 138547330U, // MULSDrr
+ 138547330U, // MULSDrr_Int
+ 139464841U, // MULSSrm
+ 139464841U, // MULSSrm_Int
+ 138547337U, // MULSSrr
+ 138547337U, // MULSSrr_Int
+ 805310608U, // MUL_F32m
+ 939528336U, // MUL_F64m
+ 268439702U, // MUL_FI16m
+ 402657430U, // MUL_FI32m
+ 134221981U, // MUL_FPrST0
+ 134221968U, // MUL_FST0r
0U, // MUL_Fp32
0U, // MUL_Fp32m
0U, // MUL_Fp64
@@ -1499,785 +1507,792 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // MUL_FpI32m32
0U, // MUL_FpI32m64
0U, // MUL_FpI32m80
- 142610555U, // MUL_FrST0
- 4239U, // MWAIT
- 268439701U, // NEG16m
- 134221973U, // NEG16r
- 402657429U, // NEG32m
- 134221973U, // NEG32r
- 536875157U, // NEG64m
- 134221973U, // NEG64r
- 671092885U, // NEG8m
- 134221973U, // NEG8r
- 4250U, // NOOP
- 402657438U, // NOOPL
- 268439710U, // NOOPW
- 268439715U, // NOT16m
- 134221987U, // NOT16r
- 402657443U, // NOT32m
- 134221987U, // NOT32r
- 536875171U, // NOT64m
- 134221987U, // NOT64r
- 671092899U, // NOT8m
- 134221987U, // NOT8r
- 134221992U, // OR16i16
- 272634033U, // OR16mi
- 272634033U, // OR16mi8
- 272634033U, // OR16mr
- 138547377U, // OR16ri
- 138547377U, // OR16ri8
- 138678449U, // OR16rm
- 138547377U, // OR16rr
- 138547377U, // OR16rr_REV
- 134222005U, // OR32i32
- 406851761U, // OR32mi
- 406851761U, // OR32mi8
- 406851761U, // OR32mr
- 138547377U, // OR32ri
- 138547377U, // OR32ri8
- 138809521U, // OR32rm
- 138547377U, // OR32rr
- 138547377U, // OR32rr_REV
- 134222015U, // OR64i32
- 541069489U, // OR64mi32
- 541069489U, // OR64mi8
- 541069489U, // OR64mr
- 138547377U, // OR64ri32
- 138547377U, // OR64ri8
- 138940593U, // OR64rm
- 138547377U, // OR64rr
- 138547377U, // OR64rr_REV
- 134222025U, // OR8i8
- 675287217U, // OR8mi
- 675287217U, // OR8mr
- 138547377U, // OR8ri
- 139071665U, // OR8rm
- 138547377U, // OR8rr
- 138547377U, // OR8rr_REV
- 139201046U, // ORPDrm
- 138545686U, // ORPDrr
- 139201052U, // ORPSrm
- 138545692U, // ORPSrr
- 201330898U, // OUT16ir
- 4311U, // OUT16rr
- 205525202U, // OUT32ir
- 4324U, // OUT32rr
- 209719506U, // OUT8ir
- 4338U, // OUT8rr
- 4351U, // OUTSB
- 4357U, // OUTSD
- 4363U, // OUTSW
- 140906769U, // PABSBrm128
- 140120337U, // PABSBrm64
- 139858193U, // PABSBrr128
- 139858193U, // PABSBrr64
- 140906776U, // PABSDrm128
- 140120344U, // PABSDrm64
- 139858200U, // PABSDrr128
- 139858200U, // PABSDrr64
- 140906783U, // PABSWrm128
- 140120351U, // PABSWrm64
- 139858207U, // PABSWrr128
- 139858207U, // PABSWrr64
- 139595078U, // PACKSSDWrm
- 138546502U, // PACKSSDWrr
- 139595088U, // PACKSSWBrm
- 138546512U, // PACKSSWBrr
- 139596070U, // PACKUSDWrm
- 138547494U, // PACKUSDWrr
- 139595098U, // PACKUSWBrm
- 138546522U, // PACKUSWBrr
- 139595108U, // PADDBrm
- 138546532U, // PADDBrr
- 139595115U, // PADDDrm
- 138546539U, // PADDDrr
- 139595122U, // PADDQrm
- 138546546U, // PADDQrr
- 139595129U, // PADDSBrm
- 138546553U, // PADDSBrr
- 139595137U, // PADDSWrm
- 138546561U, // PADDSWrr
- 139595145U, // PADDUSBrm
- 138546569U, // PADDUSBrr
- 139595154U, // PADDUSWrm
- 138546578U, // PADDUSWrr
- 139595163U, // PADDWrm
- 138546587U, // PADDWrr
- 139612464U, // PALIGNR128rm
- 138563888U, // PALIGNR128rr
- 138957104U, // PALIGNR64rm
- 138563888U, // PALIGNR64rr
- 139595170U, // PANDNrm
- 138546594U, // PANDNrr
- 139595177U, // PANDrm
- 138546601U, // PANDrr
- 139595183U, // PAVGBrm
- 138546607U, // PAVGBrr
- 139595190U, // PAVGWrm
- 138546614U, // PAVGWrr
- 139628857U, // PBLENDVBrm0
- 138580281U, // PBLENDVBrr0
- 139612483U, // PBLENDWrmi
- 138563907U, // PBLENDWrri
- 139595197U, // PCMPEQBrm
- 138546621U, // PCMPEQBrr
- 139595206U, // PCMPEQDrm
- 138546630U, // PCMPEQDrr
- 139596108U, // PCMPEQQrm
- 138547532U, // PCMPEQQrr
- 139595215U, // PCMPEQWrm
- 138546639U, // PCMPEQWrr
- 140923221U, // PCMPESTRIArm
- 139874645U, // PCMPESTRIArr
- 140923221U, // PCMPESTRICrm
- 139874645U, // PCMPESTRICrr
- 140923221U, // PCMPESTRIOrm
- 139874645U, // PCMPESTRIOrr
- 140923221U, // PCMPESTRISrm
- 139874645U, // PCMPESTRISrr
- 140923221U, // PCMPESTRIZrm
- 139874645U, // PCMPESTRIZrr
- 140923221U, // PCMPESTRIrm
- 139874645U, // PCMPESTRIrr
- 4448U, // PCMPESTRM128MEM
- 4472U, // PCMPESTRM128REG
- 140923280U, // PCMPESTRM128rm
- 139874704U, // PCMPESTRM128rr
- 139595224U, // PCMPGTBrm
- 138546648U, // PCMPGTBrr
- 139595233U, // PCMPGTDrm
- 138546657U, // PCMPGTDrr
- 139596187U, // PCMPGTQrm
- 138547611U, // PCMPGTQrr
- 139595242U, // PCMPGTWrm
- 138546666U, // PCMPGTWrr
- 140923300U, // PCMPISTRIArm
- 139874724U, // PCMPISTRIArr
- 140923300U, // PCMPISTRICrm
- 139874724U, // PCMPISTRICrr
- 140923300U, // PCMPISTRIOrm
- 139874724U, // PCMPISTRIOrr
- 140923300U, // PCMPISTRISrm
- 139874724U, // PCMPISTRISrr
- 140923300U, // PCMPISTRIZrm
- 139874724U, // PCMPISTRIZrr
- 140923300U, // PCMPISTRIrm
- 139874724U, // PCMPISTRIrr
- 4527U, // PCMPISTRM128MEM
- 4551U, // PCMPISTRM128REG
- 140923359U, // PCMPISTRM128rm
- 139874783U, // PCMPISTRM128rr
- 675303914U, // PEXTRBmr
- 139874794U, // PEXTRBrr
- 406868466U, // PEXTRDmr
- 139874802U, // PEXTRDrr
- 541086202U, // PEXTRQmr
- 139874810U, // PEXTRQrr
- 272649715U, // PEXTRWmr
- 139873779U, // PEXTRWri
- 139596290U, // PHADDDrm128
- 138940930U, // PHADDDrm64
- 138547714U, // PHADDDrr128
- 138547714U, // PHADDDrr64
- 139596298U, // PHADDSWrm128
- 138940938U, // PHADDSWrm64
- 138547722U, // PHADDSWrr128
- 138547722U, // PHADDSWrr64
- 139596307U, // PHADDWrm128
- 138940947U, // PHADDWrm64
- 138547731U, // PHADDWrr128
- 138547731U, // PHADDWrr64
- 140907035U, // PHMINPOSUWrm128
- 139858459U, // PHMINPOSUWrr128
- 139596327U, // PHSUBDrm128
- 138940967U, // PHSUBDrm64
- 138547751U, // PHSUBDrr128
- 138547751U, // PHSUBDrr64
- 139596335U, // PHSUBSWrm128
- 138940975U, // PHSUBSWrm64
- 138547759U, // PHSUBSWrr128
- 138547759U, // PHSUBSWrr64
- 139596344U, // PHSUBWrm128
- 138940984U, // PHSUBWrm64
- 138547768U, // PHSUBWrr128
- 138547768U, // PHSUBWrr64
- 139088448U, // PINSRBrm
- 138564160U, // PINSRBrr
- 138826312U, // PINSRDrm
- 138564168U, // PINSRDrr
- 138957392U, // PINSRQrm
- 138564176U, // PINSRQrr
- 138694139U, // PINSRWrmi
- 138563067U, // PINSRWrri
- 139596376U, // PMADDUBSWrm128
- 138941016U, // PMADDUBSWrm64
- 138547800U, // PMADDUBSWrr128
- 138547800U, // PMADDUBSWrr64
- 139595267U, // PMADDWDrm
- 138546691U, // PMADDWDrr
- 139596387U, // PMAXSBrm
- 138547811U, // PMAXSBrr
- 139596395U, // PMAXSDrm
- 138547819U, // PMAXSDrr
- 139595276U, // PMAXSWrm
- 138546700U, // PMAXSWrr
- 139595284U, // PMAXUBrm
- 138546708U, // PMAXUBrr
- 139596403U, // PMAXUDrm
- 138547827U, // PMAXUDrr
- 139596411U, // PMAXUWrm
- 138547835U, // PMAXUWrr
- 139596419U, // PMINSBrm
- 138547843U, // PMINSBrr
- 139596427U, // PMINSDrm
- 138547851U, // PMINSDrr
- 139595292U, // PMINSWrm
- 138546716U, // PMINSWrr
- 139595300U, // PMINUBrm
- 138546724U, // PMINUBrr
- 139596435U, // PMINUDrm
- 138547859U, // PMINUDrr
- 139596443U, // PMINUWrm
- 138547867U, // PMINUWrr
- 139857452U, // PMOVMSKBrr
- 139989667U, // PMOVSXBDrm
- 139858595U, // PMOVSXBDrr
- 139727533U, // PMOVSXBQrm
- 139858605U, // PMOVSXBQrr
- 140120759U, // PMOVSXBWrm
- 139858615U, // PMOVSXBWrr
- 140120769U, // PMOVSXDQrm
- 139858625U, // PMOVSXDQrr
- 140120779U, // PMOVSXWDrm
- 139858635U, // PMOVSXWDrr
- 139989717U, // PMOVSXWQrm
- 139858645U, // PMOVSXWQrr
- 139989727U, // PMOVZXBDrm
- 139858655U, // PMOVZXBDrr
- 139727593U, // PMOVZXBQrm
- 139858665U, // PMOVZXBQrr
- 140120819U, // PMOVZXBWrm
- 139858675U, // PMOVZXBWrr
- 140120829U, // PMOVZXDQrm
- 139858685U, // PMOVZXDQrr
- 140120839U, // PMOVZXWDrm
- 139858695U, // PMOVZXWDrr
- 139989777U, // PMOVZXWQrm
- 139858705U, // PMOVZXWQrr
- 139596571U, // PMULDQrm
- 138547995U, // PMULDQrr
- 139596579U, // PMULHRSWrm128
- 138941219U, // PMULHRSWrm64
- 138548003U, // PMULHRSWrr128
- 138548003U, // PMULHRSWrr64
- 139595318U, // PMULHUWrm
- 138546742U, // PMULHUWrr
- 139595327U, // PMULHWrm
- 138546751U, // PMULHWrr
- 139596589U, // PMULLDrm
- 139596589U, // PMULLDrm_int
- 138548013U, // PMULLDrr
- 138548013U, // PMULLDrr_int
- 139595335U, // PMULLWrm
- 138546759U, // PMULLWrr
- 139595343U, // PMULUDQrm
- 138546767U, // PMULUDQrr
- 134222645U, // POP16r
- 268440373U, // POP16rmm
- 134222645U, // POP16rmr
- 134222645U, // POP32r
- 402658101U, // POP32rmm
- 134222645U, // POP32rmr
- 134222645U, // POP64r
- 536875829U, // POP64rmm
- 134222645U, // POP64rmr
- 139727674U, // POPCNT16rm
- 139858746U, // POPCNT16rr
- 139989818U, // POPCNT32rm
- 139858746U, // POPCNT32rr
- 140120890U, // POPCNT64rm
- 139858746U, // POPCNT64rr
- 4930U, // POPF
- 4930U, // POPFD
- 4930U, // POPFQ
- 4935U, // POPFS16
- 4935U, // POPFS32
- 4935U, // POPFS64
- 4943U, // POPGS16
- 4943U, // POPGS32
- 4943U, // POPGS64
- 139595352U, // PORrm
- 138546776U, // PORrr
- 671093591U, // PREFETCHNTA
- 671093604U, // PREFETCHT0
- 671093616U, // PREFETCHT1
- 671093628U, // PREFETCHT2
- 139595357U, // PSADBWrm
- 138546781U, // PSADBWrr
- 139596680U, // PSHUFBrm128
- 138941320U, // PSHUFBrm64
- 138548104U, // PSHUFBrr128
- 138548104U, // PSHUFBrr64
- 140923792U, // PSHUFDmi
- 139875216U, // PSHUFDri
- 140923800U, // PSHUFHWmi
- 139875224U, // PSHUFHWri
- 140923809U, // PSHUFLWmi
- 139875233U, // PSHUFLWri
- 139596714U, // PSIGNBrm128
- 138941354U, // PSIGNBrm64
- 138548138U, // PSIGNBrr128
- 138548138U, // PSIGNBrr64
- 139596722U, // PSIGNDrm128
- 138941362U, // PSIGNDrm64
- 138548146U, // PSIGNDrr128
- 138548146U, // PSIGNDrr64
- 139596730U, // PSIGNWrm128
- 138941370U, // PSIGNWrm64
- 138548154U, // PSIGNWrr128
- 138548154U, // PSIGNWrr64
- 138548162U, // PSLLDQri
- 138546797U, // PSLLDri
- 139595373U, // PSLLDrm
- 138546797U, // PSLLDrr
- 138546804U, // PSLLQri
- 139595380U, // PSLLQrm
- 138546804U, // PSLLQrr
- 138546811U, // PSLLWri
- 139595387U, // PSLLWrm
- 138546811U, // PSLLWrr
- 138546818U, // PSRADri
- 139595394U, // PSRADrm
- 138546818U, // PSRADrr
- 138546825U, // PSRAWri
- 139595401U, // PSRAWrm
- 138546825U, // PSRAWrr
- 138548170U, // PSRLDQri
- 138546832U, // PSRLDri
- 139595408U, // PSRLDrm
- 138546832U, // PSRLDrr
- 138546839U, // PSRLQri
- 139595415U, // PSRLQrm
- 138546839U, // PSRLQrr
- 138546846U, // PSRLWri
- 139595422U, // PSRLWrm
- 138546846U, // PSRLWrr
- 139595429U, // PSUBBrm
- 138546853U, // PSUBBrr
- 139595436U, // PSUBDrm
- 138546860U, // PSUBDrr
- 139595443U, // PSUBQrm
- 138546867U, // PSUBQrr
- 139595450U, // PSUBSBrm
- 138546874U, // PSUBSBrr
- 139595458U, // PSUBSWrm
- 138546882U, // PSUBSWrr
- 139595466U, // PSUBUSBrm
- 138546890U, // PSUBUSBrr
- 139595475U, // PSUBUSWrm
- 138546899U, // PSUBUSWrr
- 139595484U, // PSUBWrm
- 138546908U, // PSUBWrr
- 140907474U, // PTESTrm
- 139858898U, // PTESTrr
- 139595491U, // PUNPCKHBWrm
- 138546915U, // PUNPCKHBWrr
- 139595502U, // PUNPCKHDQrm
- 138546926U, // PUNPCKHDQrr
- 139596762U, // PUNPCKHQDQrm
- 138548186U, // PUNPCKHQDQrr
- 139595513U, // PUNPCKHWDrm
- 138546937U, // PUNPCKHWDrr
- 139595524U, // PUNPCKLBWrm
- 138546948U, // PUNPCKLBWrr
- 139595535U, // PUNPCKLDQrm
- 138546959U, // PUNPCKLDQrr
- 139596774U, // PUNPCKLQDQrm
- 138548198U, // PUNPCKLQDQrr
- 139595546U, // PUNPCKLWDrm
- 138546970U, // PUNPCKLWDrr
- 134222834U, // PUSH16r
- 268440562U, // PUSH16rmm
- 134222834U, // PUSH16rmr
- 134222834U, // PUSH32i16
- 134222834U, // PUSH32i32
- 134222834U, // PUSH32i8
- 134222834U, // PUSH32r
- 402658290U, // PUSH32rmm
- 134222834U, // PUSH32rmr
- 134222834U, // PUSH64i16
- 134222834U, // PUSH64i32
- 134222834U, // PUSH64i8
- 134222834U, // PUSH64r
- 536876018U, // PUSH64rmm
- 134222834U, // PUSH64rmr
- 5112U, // PUSHF
- 5112U, // PUSHFD
- 5112U, // PUSHFQ64
- 5118U, // PUSHFS16
- 5118U, // PUSHFS32
- 5118U, // PUSHFS64
- 5127U, // PUSHGS16
- 5127U, // PUSHGS32
- 5127U, // PUSHGS64
- 139594240U, // PXORrm
- 138545664U, // PXORrr
- 348132368U, // RCL16m1
- 352326672U, // RCL16mCL
- 275780624U, // RCL16mi
- 213914640U, // RCL16r1
- 218108944U, // RCL16rCL
- 138548240U, // RCL16ri
- 482350096U, // RCL32m1
- 486544400U, // RCL32mCL
- 409998352U, // RCL32mi
- 213914640U, // RCL32r1
- 218108944U, // RCL32rCL
- 138548240U, // RCL32ri
- 616567824U, // RCL64m1
- 620762128U, // RCL64mCL
- 544216080U, // RCL64mi
- 213914640U, // RCL64r1
- 218108944U, // RCL64rCL
- 138548240U, // RCL64ri
- 750785552U, // RCL8m1
- 754979856U, // RCL8mCL
- 678433808U, // RCL8mi
- 213914640U, // RCL8r1
- 218108944U, // RCL8rCL
- 138548240U, // RCL8ri
- 140383253U, // RCPPSm
- 140383253U, // RCPPSm_Int
- 139858965U, // RCPPSr
- 139858965U, // RCPPSr_Int
- 140645404U, // RCPSSm
- 140645404U, // RCPSSm_Int
- 139858972U, // RCPSSr
- 139858972U, // RCPSSr_Int
- 348132387U, // RCR16m1
- 352326691U, // RCR16mCL
- 275780643U, // RCR16mi
- 213914659U, // RCR16r1
- 218108963U, // RCR16rCL
- 138548259U, // RCR16ri
- 482350115U, // RCR32m1
- 486544419U, // RCR32mCL
- 409998371U, // RCR32mi
- 213914659U, // RCR32r1
- 218108963U, // RCR32rCL
- 138548259U, // RCR32ri
- 616567843U, // RCR64m1
- 620762147U, // RCR64mCL
- 544216099U, // RCR64mi
- 213914659U, // RCR64r1
- 218108963U, // RCR64rCL
- 138548259U, // RCR64ri
- 750785571U, // RCR8m1
- 754979875U, // RCR8mCL
- 678433827U, // RCR8mi
- 213914659U, // RCR8r1
- 218108963U, // RCR8rCL
- 138548259U, // RCR8ri
- 5160U, // RDMSR
- 5166U, // RDPMC
- 5172U, // RDTSC
- 5178U, // REP_MOVSB
- 5188U, // REP_MOVSD
- 5198U, // REP_MOVSQ
- 5208U, // REP_MOVSW
- 5218U, // REP_STOSB
- 5228U, // REP_STOSD
- 5238U, // REP_STOSQ
- 5248U, // REP_STOSW
- 5258U, // RET
- 134222990U, // RETI
- 268440723U, // ROL16m1
- 352326803U, // ROL16mCL
- 272635027U, // ROL16mi
- 134222995U, // ROL16r1
- 218109075U, // ROL16rCL
- 138548371U, // ROL16ri
- 402658451U, // ROL32m1
- 486544531U, // ROL32mCL
- 406852755U, // ROL32mi
- 134222995U, // ROL32r1
- 218109075U, // ROL32rCL
- 138548371U, // ROL32ri
- 536876179U, // ROL64m1
- 624956563U, // ROL64mCL
- 541070483U, // ROL64mi
- 134222995U, // ROL64r1
- 222303379U, // ROL64rCL
- 138548371U, // ROL64ri
- 671093907U, // ROL8m1
- 754979987U, // ROL8mCL
- 675288211U, // ROL8mi
- 134222995U, // ROL8r1
- 218109075U, // ROL8rCL
- 138548371U, // ROL8ri
- 268440728U, // ROR16m1
- 352326808U, // ROR16mCL
- 272635032U, // ROR16mi
- 134223000U, // ROR16r1
- 218109080U, // ROR16rCL
- 138548376U, // ROR16ri
- 402658456U, // ROR32m1
- 486544536U, // ROR32mCL
- 406852760U, // ROR32mi
- 134223000U, // ROR32r1
- 218109080U, // ROR32rCL
- 138548376U, // ROR32ri
- 536876184U, // ROR64m1
- 624956568U, // ROR64mCL
- 541070488U, // ROR64mi
- 134223000U, // ROR64r1
- 222303384U, // ROR64rCL
- 138548376U, // ROR64ri
- 671093912U, // ROR8m1
- 754979992U, // ROR8mCL
- 675288216U, // ROR8mi
- 134223000U, // ROR8r1
- 218109080U, // ROR8rCL
- 138548376U, // ROR8ri
- 140399773U, // ROUNDPDm_Int
- 139875485U, // ROUNDPDr_Int
- 140399782U, // ROUNDPSm_Int
- 139875494U, // ROUNDPSr_Int
- 139351215U, // ROUNDSDm_Int
- 138564783U, // ROUNDSDr_Int
- 139482296U, // ROUNDSSm_Int
- 138564792U, // ROUNDSSr_Int
- 5313U, // RSM
- 140383429U, // RSQRTPSm
- 140383429U, // RSQRTPSm_Int
- 139859141U, // RSQRTPSr
- 139859141U, // RSQRTPSr_Int
- 140645582U, // RSQRTSSm
- 140645582U, // RSQRTSSm_Int
- 139859150U, // RSQRTSSr
- 139859150U, // RSQRTSSr_Int
- 5335U, // SAHF
- 268440796U, // SAR16m1
- 352326876U, // SAR16mCL
- 272635100U, // SAR16mi
- 134223068U, // SAR16r1
- 218109148U, // SAR16rCL
- 138548444U, // SAR16ri
- 402658524U, // SAR32m1
- 486544604U, // SAR32mCL
- 406852828U, // SAR32mi
- 134223068U, // SAR32r1
- 218109148U, // SAR32rCL
- 138548444U, // SAR32ri
- 536876252U, // SAR64m1
- 624956636U, // SAR64mCL
- 541070556U, // SAR64mi
- 134223068U, // SAR64r1
- 222303452U, // SAR64rCL
- 138548444U, // SAR64ri
- 671093980U, // SAR8m1
- 754980060U, // SAR8mCL
- 675288284U, // SAR8mi
- 134223068U, // SAR8r1
- 218109148U, // SAR8rCL
- 138548444U, // SAR8ri
- 134223073U, // SBB16i16
- 272635115U, // SBB16mi
- 272635115U, // SBB16mi8
- 272635115U, // SBB16mr
- 138548459U, // SBB16ri
- 138548459U, // SBB16ri8
- 138679531U, // SBB16rm
- 138548459U, // SBB16rr
- 138548459U, // SBB16rr_REV
- 134223088U, // SBB32i32
- 406852843U, // SBB32mi
- 406852843U, // SBB32mi8
- 406852843U, // SBB32mr
- 138548459U, // SBB32ri
- 138548459U, // SBB32ri8
- 138810603U, // SBB32rm
- 138548459U, // SBB32rr
- 138548459U, // SBB32rr_REV
- 134223099U, // SBB64i32
- 541070571U, // SBB64mi32
- 541070571U, // SBB64mi8
- 541070571U, // SBB64mr
- 138548459U, // SBB64ri32
- 138548459U, // SBB64ri8
- 138941675U, // SBB64rm
- 138548459U, // SBB64rr
- 138548459U, // SBB64rr_REV
- 134223110U, // SBB8i8
- 675288299U, // SBB8mi
- 675288299U, // SBB8mr
- 138548459U, // SBB8ri
- 139072747U, // SBB8rm
- 138548459U, // SBB8rr
- 138548459U, // SBB8rr_REV
- 5392U, // SCAS16
- 5392U, // SCAS32
- 5392U, // SCAS64
- 5392U, // SCAS8
- 671094037U, // SETAEm
- 134223125U, // SETAEr
- 671094044U, // SETAm
- 134223132U, // SETAr
- 671094050U, // SETBEm
- 134223138U, // SETBEr
- 140776683U, // SETB_C16r
- 140776683U, // SETB_C32r
- 140776683U, // SETB_C64r
- 140776683U, // SETB_C8r
- 671094057U, // SETBm
- 134223145U, // SETBr
- 671094063U, // SETEm
- 134223151U, // SETEr
- 671094069U, // SETGEm
- 134223157U, // SETGEr
- 671094076U, // SETGm
- 134223164U, // SETGr
- 671094082U, // SETLEm
- 134223170U, // SETLEr
- 671094089U, // SETLm
- 134223177U, // SETLr
- 671094095U, // SETNEm
- 134223183U, // SETNEr
- 671094102U, // SETNOm
- 134223190U, // SETNOr
- 671094109U, // SETNPm
- 134223197U, // SETNPr
- 671094116U, // SETNSm
- 134223204U, // SETNSr
- 671094123U, // SETOm
- 134223211U, // SETOr
- 671094129U, // SETPm
- 134223217U, // SETPr
- 671094135U, // SETSm
- 134223223U, // SETSr
- 5501U, // SFENCE
- 1744835972U, // SGDTm
- 268440970U, // SHL16m1
- 352327050U, // SHL16mCL
- 272635274U, // SHL16mi
- 134223242U, // SHL16r1
- 218109322U, // SHL16rCL
- 138548618U, // SHL16ri
- 402658698U, // SHL32m1
- 486544778U, // SHL32mCL
- 406853002U, // SHL32mi
- 134223242U, // SHL32r1
- 218109322U, // SHL32rCL
- 138548618U, // SHL32ri
- 536876426U, // SHL64m1
- 624956810U, // SHL64mCL
- 541070730U, // SHL64mi
- 134223242U, // SHL64r1
- 222303626U, // SHL64rCL
- 138548618U, // SHL64ri
- 671094154U, // SHL8m1
- 754980234U, // SHL8mCL
- 675288458U, // SHL8mi
- 134223242U, // SHL8r1
- 218109322U, // SHL8rCL
- 138548618U, // SHL8ri
- 272700815U, // SHLD16mrCL
- 272651663U, // SHLD16mri8
- 138614159U, // SHLD16rrCL
- 138565007U, // SHLD16rri8
- 406918543U, // SHLD32mrCL
- 406869391U, // SHLD32mri8
- 138614159U, // SHLD32rrCL
- 138565007U, // SHLD32rri8
- 541152655U, // SHLD64mrCL
- 541087119U, // SHLD64mri8
- 138630543U, // SHLD64rrCL
- 138565007U, // SHLD64rri8
- 268440981U, // SHR16m1
- 352327061U, // SHR16mCL
- 272635285U, // SHR16mi
- 134223253U, // SHR16r1
- 218109333U, // SHR16rCL
- 138548629U, // SHR16ri
- 402658709U, // SHR32m1
- 486544789U, // SHR32mCL
- 406853013U, // SHR32mi
- 134223253U, // SHR32r1
- 218109333U, // SHR32rCL
- 138548629U, // SHR32ri
- 536876437U, // SHR64m1
- 624956821U, // SHR64mCL
- 541070741U, // SHR64mi
- 134223253U, // SHR64r1
- 222303637U, // SHR64rCL
- 138548629U, // SHR64ri
- 671094165U, // SHR8m1
- 754980245U, // SHR8mCL
- 675288469U, // SHR8mi
- 134223253U, // SHR8r1
- 218109333U, // SHR8rCL
- 138548629U, // SHR8ri
- 272700826U, // SHRD16mrCL
- 272651674U, // SHRD16mri8
- 138614170U, // SHRD16rrCL
- 138565018U, // SHRD16rri8
- 406918554U, // SHRD32mrCL
- 406869402U, // SHRD32mri8
- 138614170U, // SHRD32rrCL
- 138565018U, // SHRD32rri8
- 541152666U, // SHRD64mrCL
- 541087130U, // SHRD64mri8
- 138630554U, // SHRD64rrCL
- 138565018U, // SHRD64rri8
- 139220384U, // SHUFPDrmi
- 138565024U, // SHUFPDrri
- 139220392U, // SHUFPSrmi
- 138565032U, // SHUFPSrri
- 1744836016U, // SIDTm
- 5558U, // SIN_F
+ 142610576U, // MUL_FrST0
+ 4260U, // MWAIT
+ 268439722U, // NEG16m
+ 134221994U, // NEG16r
+ 402657450U, // NEG32m
+ 134221994U, // NEG32r
+ 536875178U, // NEG64m
+ 134221994U, // NEG64r
+ 671092906U, // NEG8m
+ 134221994U, // NEG8r
+ 4271U, // NOOP
+ 402657459U, // NOOPL
+ 268439731U, // NOOPW
+ 268439736U, // NOT16m
+ 134222008U, // NOT16r
+ 402657464U, // NOT32m
+ 134222008U, // NOT32r
+ 536875192U, // NOT64m
+ 134222008U, // NOT64r
+ 671092920U, // NOT8m
+ 134222008U, // NOT8r
+ 134222013U, // OR16i16
+ 272634054U, // OR16mi
+ 272634054U, // OR16mi8
+ 272634054U, // OR16mr
+ 138547398U, // OR16ri
+ 138547398U, // OR16ri8
+ 138678470U, // OR16rm
+ 138547398U, // OR16rr
+ 138547398U, // OR16rr_REV
+ 134222026U, // OR32i32
+ 406851782U, // OR32mi
+ 406851782U, // OR32mi8
+ 406851782U, // OR32mr
+ 138547398U, // OR32ri
+ 138547398U, // OR32ri8
+ 138809542U, // OR32rm
+ 138547398U, // OR32rr
+ 138547398U, // OR32rr_REV
+ 134222036U, // OR64i32
+ 541069510U, // OR64mi32
+ 541069510U, // OR64mi8
+ 541069510U, // OR64mr
+ 138547398U, // OR64ri32
+ 138547398U, // OR64ri8
+ 138940614U, // OR64rm
+ 138547398U, // OR64rr
+ 138547398U, // OR64rr_REV
+ 134222046U, // OR8i8
+ 675287238U, // OR8mi
+ 675287238U, // OR8mr
+ 138547398U, // OR8ri
+ 139071686U, // OR8rm
+ 138547398U, // OR8rr
+ 138547398U, // OR8rr_REV
+ 139201042U, // ORPDrm
+ 138545682U, // ORPDrr
+ 139201048U, // ORPSrm
+ 138545688U, // ORPSrr
+ 201330919U, // OUT16ir
+ 4332U, // OUT16rr
+ 205525223U, // OUT32ir
+ 4345U, // OUT32rr
+ 209719527U, // OUT8ir
+ 4359U, // OUT8rr
+ 4372U, // OUTSB
+ 4378U, // OUTSD
+ 4384U, // OUTSW
+ 140775718U, // PABSBrm128
+ 140120358U, // PABSBrm64
+ 139858214U, // PABSBrr128
+ 139858214U, // PABSBrr64
+ 140775725U, // PABSDrm128
+ 140120365U, // PABSDrm64
+ 139858221U, // PABSDrr128
+ 139858221U, // PABSDrr64
+ 140775732U, // PABSWrm128
+ 140120372U, // PABSWrm64
+ 139858228U, // PABSWrr128
+ 139858228U, // PABSWrr64
+ 139595091U, // PACKSSDWrm
+ 138546515U, // PACKSSDWrr
+ 139595101U, // PACKSSWBrm
+ 138546525U, // PACKSSWBrr
+ 139596091U, // PACKUSDWrm
+ 138547515U, // PACKUSDWrr
+ 139595111U, // PACKUSWBrm
+ 138546535U, // PACKUSWBrr
+ 139595121U, // PADDBrm
+ 138546545U, // PADDBrr
+ 139595128U, // PADDDrm
+ 138546552U, // PADDDrr
+ 139595135U, // PADDQrm
+ 138546559U, // PADDQrr
+ 139595142U, // PADDSBrm
+ 138546566U, // PADDSBrr
+ 139595150U, // PADDSWrm
+ 138546574U, // PADDSWrr
+ 139595158U, // PADDUSBrm
+ 138546582U, // PADDUSBrr
+ 139595167U, // PADDUSWrm
+ 138546591U, // PADDUSWrr
+ 139595176U, // PADDWrm
+ 138546600U, // PADDWrr
+ 139612485U, // PALIGNR128rm
+ 138563909U, // PALIGNR128rr
+ 138957125U, // PALIGNR64rm
+ 138563909U, // PALIGNR64rr
+ 139595183U, // PANDNrm
+ 138546607U, // PANDNrr
+ 139595190U, // PANDrm
+ 138546614U, // PANDrr
+ 139595196U, // PAVGBrm
+ 138546620U, // PAVGBrr
+ 139595203U, // PAVGWrm
+ 138546627U, // PAVGWrr
+ 139628878U, // PBLENDVBrm0
+ 138580302U, // PBLENDVBrr0
+ 139612504U, // PBLENDWrmi
+ 138563928U, // PBLENDWrri
+ 139595210U, // PCMPEQBrm
+ 138546634U, // PCMPEQBrr
+ 139595219U, // PCMPEQDrm
+ 138546643U, // PCMPEQDrr
+ 139596129U, // PCMPEQQrm
+ 138547553U, // PCMPEQQrr
+ 139595228U, // PCMPEQWrm
+ 138546652U, // PCMPEQWrr
+ 140792170U, // PCMPESTRIArm
+ 139874666U, // PCMPESTRIArr
+ 140792170U, // PCMPESTRICrm
+ 139874666U, // PCMPESTRICrr
+ 140792170U, // PCMPESTRIOrm
+ 139874666U, // PCMPESTRIOrr
+ 140792170U, // PCMPESTRISrm
+ 139874666U, // PCMPESTRISrr
+ 140792170U, // PCMPESTRIZrm
+ 139874666U, // PCMPESTRIZrr
+ 140792170U, // PCMPESTRIrm
+ 139874666U, // PCMPESTRIrr
+ 4469U, // PCMPESTRM128MEM
+ 4493U, // PCMPESTRM128REG
+ 140792229U, // PCMPESTRM128rm
+ 139874725U, // PCMPESTRM128rr
+ 139595237U, // PCMPGTBrm
+ 138546661U, // PCMPGTBrr
+ 139595246U, // PCMPGTDrm
+ 138546670U, // PCMPGTDrr
+ 139596208U, // PCMPGTQrm
+ 138547632U, // PCMPGTQrr
+ 139595255U, // PCMPGTWrm
+ 138546679U, // PCMPGTWrr
+ 140792249U, // PCMPISTRIArm
+ 139874745U, // PCMPISTRIArr
+ 140792249U, // PCMPISTRICrm
+ 139874745U, // PCMPISTRICrr
+ 140792249U, // PCMPISTRIOrm
+ 139874745U, // PCMPISTRIOrr
+ 140792249U, // PCMPISTRISrm
+ 139874745U, // PCMPISTRISrr
+ 140792249U, // PCMPISTRIZrm
+ 139874745U, // PCMPISTRIZrr
+ 140792249U, // PCMPISTRIrm
+ 139874745U, // PCMPISTRIrr
+ 4548U, // PCMPISTRM128MEM
+ 4572U, // PCMPISTRM128REG
+ 140792308U, // PCMPISTRM128rm
+ 139874804U, // PCMPISTRM128rr
+ 675303935U, // PEXTRBmr
+ 139874815U, // PEXTRBrr
+ 406868487U, // PEXTRDmr
+ 139874823U, // PEXTRDrr
+ 541086223U, // PEXTRQmr
+ 139874831U, // PEXTRQrr
+ 272649728U, // PEXTRWmr
+ 139873792U, // PEXTRWri
+ 139596311U, // PHADDDrm128
+ 138940951U, // PHADDDrm64
+ 138547735U, // PHADDDrr128
+ 138547735U, // PHADDDrr64
+ 139596319U, // PHADDSWrm128
+ 138940959U, // PHADDSWrm64
+ 138547743U, // PHADDSWrr128
+ 138547743U, // PHADDSWrr64
+ 139596328U, // PHADDWrm128
+ 138940968U, // PHADDWrm64
+ 138547752U, // PHADDWrr128
+ 138547752U, // PHADDWrr64
+ 140775984U, // PHMINPOSUWrm128
+ 139858480U, // PHMINPOSUWrr128
+ 139596348U, // PHSUBDrm128
+ 138940988U, // PHSUBDrm64
+ 138547772U, // PHSUBDrr128
+ 138547772U, // PHSUBDrr64
+ 139596356U, // PHSUBSWrm128
+ 138940996U, // PHSUBSWrm64
+ 138547780U, // PHSUBSWrr128
+ 138547780U, // PHSUBSWrr64
+ 139596365U, // PHSUBWrm128
+ 138941005U, // PHSUBWrm64
+ 138547789U, // PHSUBWrr128
+ 138547789U, // PHSUBWrr64
+ 139088469U, // PINSRBrm
+ 138564181U, // PINSRBrr
+ 138826333U, // PINSRDrm
+ 138564189U, // PINSRDrr
+ 138957413U, // PINSRQrm
+ 138564197U, // PINSRQrr
+ 138694152U, // PINSRWrmi
+ 138563080U, // PINSRWrri
+ 139596397U, // PMADDUBSWrm128
+ 138941037U, // PMADDUBSWrm64
+ 138547821U, // PMADDUBSWrr128
+ 138547821U, // PMADDUBSWrr64
+ 139595280U, // PMADDWDrm
+ 138546704U, // PMADDWDrr
+ 139596408U, // PMAXSBrm
+ 138547832U, // PMAXSBrr
+ 139596416U, // PMAXSDrm
+ 138547840U, // PMAXSDrr
+ 139595289U, // PMAXSWrm
+ 138546713U, // PMAXSWrr
+ 139595297U, // PMAXUBrm
+ 138546721U, // PMAXUBrr
+ 139596424U, // PMAXUDrm
+ 138547848U, // PMAXUDrr
+ 139596432U, // PMAXUWrm
+ 138547856U, // PMAXUWrr
+ 139596440U, // PMINSBrm
+ 138547864U, // PMINSBrr
+ 139596448U, // PMINSDrm
+ 138547872U, // PMINSDrr
+ 139595305U, // PMINSWrm
+ 138546729U, // PMINSWrr
+ 139595313U, // PMINUBrm
+ 138546737U, // PMINUBrr
+ 139596456U, // PMINUDrm
+ 138547880U, // PMINUDrr
+ 139596464U, // PMINUWrm
+ 138547888U, // PMINUWrr
+ 139857465U, // PMOVMSKBrr
+ 139989688U, // PMOVSXBDrm
+ 139858616U, // PMOVSXBDrr
+ 139727554U, // PMOVSXBQrm
+ 139858626U, // PMOVSXBQrr
+ 140120780U, // PMOVSXBWrm
+ 139858636U, // PMOVSXBWrr
+ 140120790U, // PMOVSXDQrm
+ 139858646U, // PMOVSXDQrr
+ 140120800U, // PMOVSXWDrm
+ 139858656U, // PMOVSXWDrr
+ 139989738U, // PMOVSXWQrm
+ 139858666U, // PMOVSXWQrr
+ 139989748U, // PMOVZXBDrm
+ 139858676U, // PMOVZXBDrr
+ 139727614U, // PMOVZXBQrm
+ 139858686U, // PMOVZXBQrr
+ 140120840U, // PMOVZXBWrm
+ 139858696U, // PMOVZXBWrr
+ 140120850U, // PMOVZXDQrm
+ 139858706U, // PMOVZXDQrr
+ 140120860U, // PMOVZXWDrm
+ 139858716U, // PMOVZXWDrr
+ 139989798U, // PMOVZXWQrm
+ 139858726U, // PMOVZXWQrr
+ 139596592U, // PMULDQrm
+ 138548016U, // PMULDQrr
+ 139596600U, // PMULHRSWrm128
+ 138941240U, // PMULHRSWrm64
+ 138548024U, // PMULHRSWrr128
+ 138548024U, // PMULHRSWrr64
+ 139595331U, // PMULHUWrm
+ 138546755U, // PMULHUWrr
+ 139595340U, // PMULHWrm
+ 138546764U, // PMULHWrr
+ 139596610U, // PMULLDrm
+ 139596610U, // PMULLDrm_int
+ 138548034U, // PMULLDrr
+ 138548034U, // PMULLDrr_int
+ 139595348U, // PMULLWrm
+ 138546772U, // PMULLWrr
+ 139595356U, // PMULUDQrm
+ 138546780U, // PMULUDQrr
+ 134222666U, // POP16r
+ 268440394U, // POP16rmm
+ 134222666U, // POP16rmr
+ 134222666U, // POP32r
+ 402658122U, // POP32rmm
+ 134222666U, // POP32rmr
+ 134222666U, // POP64r
+ 536875850U, // POP64rmm
+ 134222666U, // POP64rmr
+ 139727695U, // POPCNT16rm
+ 139858767U, // POPCNT16rr
+ 139989839U, // POPCNT32rm
+ 139858767U, // POPCNT32rr
+ 140120911U, // POPCNT64rm
+ 139858767U, // POPCNT64rr
+ 4951U, // POPF
+ 4951U, // POPFD
+ 4951U, // POPFQ
+ 4956U, // POPFS16
+ 4956U, // POPFS32
+ 4956U, // POPFS64
+ 4964U, // POPGS16
+ 4964U, // POPGS32
+ 4964U, // POPGS64
+ 139595365U, // PORrm
+ 138546789U, // PORrr
+ 671093612U, // PREFETCHNTA
+ 671093625U, // PREFETCHT0
+ 671093637U, // PREFETCHT1
+ 671093649U, // PREFETCHT2
+ 139595370U, // PSADBWrm
+ 138546794U, // PSADBWrr
+ 139596701U, // PSHUFBrm128
+ 138941341U, // PSHUFBrm64
+ 138548125U, // PSHUFBrr128
+ 138548125U, // PSHUFBrr64
+ 140792741U, // PSHUFDmi
+ 139875237U, // PSHUFDri
+ 140792749U, // PSHUFHWmi
+ 139875245U, // PSHUFHWri
+ 140792758U, // PSHUFLWmi
+ 139875254U, // PSHUFLWri
+ 139596735U, // PSIGNBrm128
+ 138941375U, // PSIGNBrm64
+ 138548159U, // PSIGNBrr128
+ 138548159U, // PSIGNBrr64
+ 139596743U, // PSIGNDrm128
+ 138941383U, // PSIGNDrm64
+ 138548167U, // PSIGNDrr128
+ 138548167U, // PSIGNDrr64
+ 139596751U, // PSIGNWrm128
+ 138941391U, // PSIGNWrm64
+ 138548175U, // PSIGNWrr128
+ 138548175U, // PSIGNWrr64
+ 138548183U, // PSLLDQri
+ 138546810U, // PSLLDri
+ 139595386U, // PSLLDrm
+ 138546810U, // PSLLDrr
+ 138546817U, // PSLLQri
+ 139595393U, // PSLLQrm
+ 138546817U, // PSLLQrr
+ 138546824U, // PSLLWri
+ 139595400U, // PSLLWrm
+ 138546824U, // PSLLWrr
+ 138546831U, // PSRADri
+ 139595407U, // PSRADrm
+ 138546831U, // PSRADrr
+ 138546838U, // PSRAWri
+ 139595414U, // PSRAWrm
+ 138546838U, // PSRAWrr
+ 138548191U, // PSRLDQri
+ 138546845U, // PSRLDri
+ 139595421U, // PSRLDrm
+ 138546845U, // PSRLDrr
+ 138546852U, // PSRLQri
+ 139595428U, // PSRLQrm
+ 138546852U, // PSRLQrr
+ 138546859U, // PSRLWri
+ 139595435U, // PSRLWrm
+ 138546859U, // PSRLWrr
+ 139595442U, // PSUBBrm
+ 138546866U, // PSUBBrr
+ 139595449U, // PSUBDrm
+ 138546873U, // PSUBDrr
+ 139595456U, // PSUBQrm
+ 138546880U, // PSUBQrr
+ 139595463U, // PSUBSBrm
+ 138546887U, // PSUBSBrr
+ 139595471U, // PSUBSWrm
+ 138546895U, // PSUBSWrr
+ 139595479U, // PSUBUSBrm
+ 138546903U, // PSUBUSBrr
+ 139595488U, // PSUBUSWrm
+ 138546912U, // PSUBUSWrr
+ 139595497U, // PSUBWrm
+ 138546921U, // PSUBWrr
+ 140776423U, // PTESTrm
+ 139858919U, // PTESTrr
+ 139595504U, // PUNPCKHBWrm
+ 138546928U, // PUNPCKHBWrr
+ 139595515U, // PUNPCKHDQrm
+ 138546939U, // PUNPCKHDQrr
+ 139596783U, // PUNPCKHQDQrm
+ 138548207U, // PUNPCKHQDQrr
+ 139595526U, // PUNPCKHWDrm
+ 138546950U, // PUNPCKHWDrr
+ 139595537U, // PUNPCKLBWrm
+ 138546961U, // PUNPCKLBWrr
+ 139595548U, // PUNPCKLDQrm
+ 138546972U, // PUNPCKLDQrr
+ 139596795U, // PUNPCKLQDQrm
+ 138548219U, // PUNPCKLQDQrr
+ 139595559U, // PUNPCKLWDrm
+ 138546983U, // PUNPCKLWDrr
+ 134222855U, // PUSH16r
+ 268440583U, // PUSH16rmm
+ 134222855U, // PUSH16rmr
+ 134222855U, // PUSH32i16
+ 134222855U, // PUSH32i32
+ 134222855U, // PUSH32i8
+ 134222855U, // PUSH32r
+ 402658311U, // PUSH32rmm
+ 134222855U, // PUSH32rmr
+ 134222855U, // PUSH64i16
+ 134222855U, // PUSH64i32
+ 134222855U, // PUSH64i8
+ 134222855U, // PUSH64r
+ 536876039U, // PUSH64rmm
+ 134222855U, // PUSH64rmr
+ 5133U, // PUSHF
+ 5133U, // PUSHFD
+ 5133U, // PUSHFQ64
+ 5139U, // PUSHFS16
+ 5139U, // PUSHFS32
+ 5139U, // PUSHFS64
+ 5148U, // PUSHGS16
+ 5148U, // PUSHGS32
+ 5148U, // PUSHGS64
+ 139595570U, // PXORrm
+ 138546994U, // PXORrr
+ 348132389U, // RCL16m1
+ 352326693U, // RCL16mCL
+ 272634917U, // RCL16mi
+ 213914661U, // RCL16r1
+ 218108965U, // RCL16rCL
+ 138548261U, // RCL16ri
+ 482350117U, // RCL32m1
+ 486544421U, // RCL32mCL
+ 406852645U, // RCL32mi
+ 213914661U, // RCL32r1
+ 218108965U, // RCL32rCL
+ 138548261U, // RCL32ri
+ 616567845U, // RCL64m1
+ 620762149U, // RCL64mCL
+ 541070373U, // RCL64mi
+ 213914661U, // RCL64r1
+ 218108965U, // RCL64rCL
+ 138548261U, // RCL64ri
+ 750785573U, // RCL8m1
+ 754979877U, // RCL8mCL
+ 675288101U, // RCL8mi
+ 213914661U, // RCL8r1
+ 218108965U, // RCL8rCL
+ 138548261U, // RCL8ri
+ 140383274U, // RCPPSm
+ 140383274U, // RCPPSm_Int
+ 139858986U, // RCPPSr
+ 139858986U, // RCPPSr_Int
+ 140645425U, // RCPSSm
+ 140645425U, // RCPSSm_Int
+ 139858993U, // RCPSSr
+ 139858993U, // RCPSSr_Int
+ 348132408U, // RCR16m1
+ 352326712U, // RCR16mCL
+ 272634936U, // RCR16mi
+ 213914680U, // RCR16r1
+ 218108984U, // RCR16rCL
+ 138548280U, // RCR16ri
+ 482350136U, // RCR32m1
+ 486544440U, // RCR32mCL
+ 406852664U, // RCR32mi
+ 213914680U, // RCR32r1
+ 218108984U, // RCR32rCL
+ 138548280U, // RCR32ri
+ 616567864U, // RCR64m1
+ 620762168U, // RCR64mCL
+ 541070392U, // RCR64mi
+ 213914680U, // RCR64r1
+ 218108984U, // RCR64rCL
+ 138548280U, // RCR64ri
+ 750785592U, // RCR8m1
+ 754979896U, // RCR8mCL
+ 675288120U, // RCR8mi
+ 213914680U, // RCR8r1
+ 218108984U, // RCR8rCL
+ 138548280U, // RCR8ri
+ 5181U, // RDMSR
+ 5187U, // RDPMC
+ 5193U, // RDTSC
+ 5199U, // RDTSCP
+ 5206U, // REPNE_PREFIX
+ 5212U, // REP_MOVSB
+ 5222U, // REP_MOVSD
+ 5232U, // REP_MOVSQ
+ 5242U, // REP_MOVSW
+ 5252U, // REP_PREFIX
+ 5256U, // REP_STOSB
+ 5266U, // REP_STOSD
+ 5276U, // REP_STOSQ
+ 5286U, // REP_STOSW
+ 5296U, // RET
+ 134223028U, // RETI
+ 268440761U, // ROL16m1
+ 352326841U, // ROL16mCL
+ 272635065U, // ROL16mi
+ 134223033U, // ROL16r1
+ 218109113U, // ROL16rCL
+ 138548409U, // ROL16ri
+ 402658489U, // ROL32m1
+ 486544569U, // ROL32mCL
+ 406852793U, // ROL32mi
+ 134223033U, // ROL32r1
+ 218109113U, // ROL32rCL
+ 138548409U, // ROL32ri
+ 536876217U, // ROL64m1
+ 624956601U, // ROL64mCL
+ 541070521U, // ROL64mi
+ 134223033U, // ROL64r1
+ 222303417U, // ROL64rCL
+ 138548409U, // ROL64ri
+ 671093945U, // ROL8m1
+ 754980025U, // ROL8mCL
+ 675288249U, // ROL8mi
+ 134223033U, // ROL8r1
+ 218109113U, // ROL8rCL
+ 138548409U, // ROL8ri
+ 268440766U, // ROR16m1
+ 352326846U, // ROR16mCL
+ 272635070U, // ROR16mi
+ 134223038U, // ROR16r1
+ 218109118U, // ROR16rCL
+ 138548414U, // ROR16ri
+ 402658494U, // ROR32m1
+ 486544574U, // ROR32mCL
+ 406852798U, // ROR32mi
+ 134223038U, // ROR32r1
+ 218109118U, // ROR32rCL
+ 138548414U, // ROR32ri
+ 536876222U, // ROR64m1
+ 624956606U, // ROR64mCL
+ 541070526U, // ROR64mi
+ 134223038U, // ROR64r1
+ 222303422U, // ROR64rCL
+ 138548414U, // ROR64ri
+ 671093950U, // ROR8m1
+ 754980030U, // ROR8mCL
+ 675288254U, // ROR8mi
+ 134223038U, // ROR8r1
+ 218109118U, // ROR8rCL
+ 138548414U, // ROR8ri
+ 140399811U, // ROUNDPDm_Int
+ 139875523U, // ROUNDPDr_Int
+ 140399820U, // ROUNDPSm_Int
+ 139875532U, // ROUNDPSr_Int
+ 139351253U, // ROUNDSDm_Int
+ 138564821U, // ROUNDSDr_Int
+ 139482334U, // ROUNDSSm_Int
+ 138564830U, // ROUNDSSr_Int
+ 5351U, // RSM
+ 140383467U, // RSQRTPSm
+ 140383467U, // RSQRTPSm_Int
+ 139859179U, // RSQRTPSr
+ 139859179U, // RSQRTPSr_Int
+ 140645620U, // RSQRTSSm
+ 140645620U, // RSQRTSSm_Int
+ 139859188U, // RSQRTSSr
+ 139859188U, // RSQRTSSr_Int
+ 5373U, // SAHF
+ 268440834U, // SAR16m1
+ 352326914U, // SAR16mCL
+ 272635138U, // SAR16mi
+ 134223106U, // SAR16r1
+ 218109186U, // SAR16rCL
+ 138548482U, // SAR16ri
+ 402658562U, // SAR32m1
+ 486544642U, // SAR32mCL
+ 406852866U, // SAR32mi
+ 134223106U, // SAR32r1
+ 218109186U, // SAR32rCL
+ 138548482U, // SAR32ri
+ 536876290U, // SAR64m1
+ 624956674U, // SAR64mCL
+ 541070594U, // SAR64mi
+ 134223106U, // SAR64r1
+ 222303490U, // SAR64rCL
+ 138548482U, // SAR64ri
+ 671094018U, // SAR8m1
+ 754980098U, // SAR8mCL
+ 675288322U, // SAR8mi
+ 134223106U, // SAR8r1
+ 218109186U, // SAR8rCL
+ 138548482U, // SAR8ri
+ 134223111U, // SBB16i16
+ 272635153U, // SBB16mi
+ 272635153U, // SBB16mi8
+ 272635153U, // SBB16mr
+ 138548497U, // SBB16ri
+ 138548497U, // SBB16ri8
+ 138679569U, // SBB16rm
+ 138548497U, // SBB16rr
+ 138548497U, // SBB16rr_REV
+ 134223126U, // SBB32i32
+ 406852881U, // SBB32mi
+ 406852881U, // SBB32mi8
+ 406852881U, // SBB32mr
+ 138548497U, // SBB32ri
+ 138548497U, // SBB32ri8
+ 138810641U, // SBB32rm
+ 138548497U, // SBB32rr
+ 138548497U, // SBB32rr_REV
+ 134223137U, // SBB64i32
+ 541070609U, // SBB64mi32
+ 541070609U, // SBB64mi8
+ 541070609U, // SBB64mr
+ 138548497U, // SBB64ri32
+ 138548497U, // SBB64ri8
+ 138941713U, // SBB64rm
+ 138548497U, // SBB64rr
+ 138548497U, // SBB64rr_REV
+ 134223148U, // SBB8i8
+ 675288337U, // SBB8mi
+ 675288337U, // SBB8mr
+ 138548497U, // SBB8ri
+ 139072785U, // SBB8rm
+ 138548497U, // SBB8rr
+ 138548497U, // SBB8rr_REV
+ 5430U, // SCAS16
+ 5430U, // SCAS32
+ 5430U, // SCAS64
+ 5430U, // SCAS8
+ 671094075U, // SETAEm
+ 134223163U, // SETAEr
+ 671094082U, // SETAm
+ 134223170U, // SETAr
+ 671094088U, // SETBEm
+ 134223176U, // SETBEr
+ 0U, // SETB_C16r
+ 0U, // SETB_C32r
+ 0U, // SETB_C64r
+ 0U, // SETB_C8r
+ 671094095U, // SETBm
+ 134223183U, // SETBr
+ 671094101U, // SETEm
+ 134223189U, // SETEr
+ 671094107U, // SETGEm
+ 134223195U, // SETGEr
+ 671094114U, // SETGm
+ 134223202U, // SETGr
+ 671094120U, // SETLEm
+ 134223208U, // SETLEr
+ 671094127U, // SETLm
+ 134223215U, // SETLr
+ 671094133U, // SETNEm
+ 134223221U, // SETNEr
+ 671094140U, // SETNOm
+ 134223228U, // SETNOr
+ 671094147U, // SETNPm
+ 134223235U, // SETNPr
+ 671094154U, // SETNSm
+ 134223242U, // SETNSr
+ 671094161U, // SETOm
+ 134223249U, // SETOr
+ 671094167U, // SETPm
+ 134223255U, // SETPr
+ 671094173U, // SETSm
+ 134223261U, // SETSr
+ 5539U, // SFENCE
+ 1744836010U, // SGDTm
+ 268441008U, // SHL16m1
+ 352327088U, // SHL16mCL
+ 272635312U, // SHL16mi
+ 134223280U, // SHL16r1
+ 218109360U, // SHL16rCL
+ 138548656U, // SHL16ri
+ 402658736U, // SHL32m1
+ 486544816U, // SHL32mCL
+ 406853040U, // SHL32mi
+ 134223280U, // SHL32r1
+ 218109360U, // SHL32rCL
+ 138548656U, // SHL32ri
+ 536876464U, // SHL64m1
+ 624956848U, // SHL64mCL
+ 541070768U, // SHL64mi
+ 134223280U, // SHL64r1
+ 222303664U, // SHL64rCL
+ 138548656U, // SHL64ri
+ 671094192U, // SHL8m1
+ 754980272U, // SHL8mCL
+ 675288496U, // SHL8mi
+ 134223280U, // SHL8r1
+ 218109360U, // SHL8rCL
+ 138548656U, // SHL8ri
+ 272700853U, // SHLD16mrCL
+ 272651701U, // SHLD16mri8
+ 138614197U, // SHLD16rrCL
+ 138565045U, // SHLD16rri8
+ 406918581U, // SHLD32mrCL
+ 406869429U, // SHLD32mri8
+ 138614197U, // SHLD32rrCL
+ 138565045U, // SHLD32rri8
+ 541152693U, // SHLD64mrCL
+ 541087157U, // SHLD64mri8
+ 138630581U, // SHLD64rrCL
+ 138565045U, // SHLD64rri8
+ 268441019U, // SHR16m1
+ 352327099U, // SHR16mCL
+ 272635323U, // SHR16mi
+ 134223291U, // SHR16r1
+ 218109371U, // SHR16rCL
+ 138548667U, // SHR16ri
+ 402658747U, // SHR32m1
+ 486544827U, // SHR32mCL
+ 406853051U, // SHR32mi
+ 134223291U, // SHR32r1
+ 218109371U, // SHR32rCL
+ 138548667U, // SHR32ri
+ 536876475U, // SHR64m1
+ 624956859U, // SHR64mCL
+ 541070779U, // SHR64mi
+ 134223291U, // SHR64r1
+ 222303675U, // SHR64rCL
+ 138548667U, // SHR64ri
+ 671094203U, // SHR8m1
+ 754980283U, // SHR8mCL
+ 675288507U, // SHR8mi
+ 134223291U, // SHR8r1
+ 218109371U, // SHR8rCL
+ 138548667U, // SHR8ri
+ 272700864U, // SHRD16mrCL
+ 272651712U, // SHRD16mri8
+ 138614208U, // SHRD16rrCL
+ 138565056U, // SHRD16rri8
+ 406918592U, // SHRD32mrCL
+ 406869440U, // SHRD32mri8
+ 138614208U, // SHRD32rrCL
+ 138565056U, // SHRD32rri8
+ 541152704U, // SHRD64mrCL
+ 541087168U, // SHRD64mri8
+ 138630592U, // SHRD64rrCL
+ 138565056U, // SHRD64rri8
+ 139220422U, // SHUFPDrmi
+ 138565062U, // SHUFPDrri
+ 139220430U, // SHUFPSrmi
+ 138565070U, // SHUFPSrri
+ 1744836054U, // SIDTm
+ 5596U, // SIN_F
0U, // SIN_Fp32
0U, // SIN_Fp64
0U, // SIN_Fp80
- 268441019U, // SLDT16m
- 134223291U, // SLDT16r
- 268441019U, // SLDT64m
- 134223291U, // SLDT64r
- 268441025U, // SMSW16m
- 134223297U, // SMSW16r
- 134223297U, // SMSW32r
- 134223297U, // SMSW64r
- 140383687U, // SQRTPDm
- 140383687U, // SQRTPDm_Int
- 139859399U, // SQRTPDr
- 139859399U, // SQRTPDr_Int
- 140383695U, // SQRTPSm
- 140383695U, // SQRTPSm_Int
- 139859407U, // SQRTPSr
- 139859407U, // SQRTPSr_Int
- 140514775U, // SQRTSDm
- 140514775U, // SQRTSDm_Int
- 139859415U, // SQRTSDr
- 139859415U, // SQRTSDr_Int
- 140645855U, // SQRTSSm
- 140645855U, // SQRTSSm_Int
- 139859423U, // SQRTSSr
- 139859423U, // SQRTSSr_Int
- 5607U, // SQRT_F
+ 268441057U, // SLDT16m
+ 134223329U, // SLDT16r
+ 268441057U, // SLDT64m
+ 134223329U, // SLDT64r
+ 268441063U, // SMSW16m
+ 134223335U, // SMSW16r
+ 134223335U, // SMSW32r
+ 134223335U, // SMSW64r
+ 140383725U, // SQRTPDm
+ 140383725U, // SQRTPDm_Int
+ 139859437U, // SQRTPDr
+ 139859437U, // SQRTPDr_Int
+ 140383733U, // SQRTPSm
+ 140383733U, // SQRTPSm_Int
+ 139859445U, // SQRTPSr
+ 139859445U, // SQRTPSr_Int
+ 140514813U, // SQRTSDm
+ 140514813U, // SQRTSDm_Int
+ 139859453U, // SQRTSDr
+ 139859453U, // SQRTSDr_Int
+ 140645893U, // SQRTSSm
+ 140645893U, // SQRTSSm_Int
+ 139859461U, // SQRTSSr
+ 139859461U, // SQRTSSr_Int
+ 5645U, // SQRT_F
0U, // SQRT_Fp32
0U, // SQRT_Fp64
0U, // SQRT_Fp80
- 5613U, // STC
- 5617U, // STD
- 5621U, // STI
- 402658809U, // STMXCSR
- 5634U, // STRm
- 5634U, // STRr
- 805312007U, // ST_F32m
- 939529735U, // ST_F64m
- 805312012U, // ST_FP32m
- 939529740U, // ST_FP64m
- 2147489292U, // ST_FP80m
- 134223372U, // ST_FPrr
+ 5651U, // SS_PREFIX
+ 5654U, // STC
+ 5658U, // STD
+ 5662U, // STI
+ 402658850U, // STMXCSR
+ 4133U, // STOSB
+ 5675U, // STOSD
+ 4133U, // STOSW
+ 5681U, // STRm
+ 5681U, // STRr
+ 805312054U, // ST_F32m
+ 939529782U, // ST_F64m
+ 805312059U, // ST_FP32m
+ 939529787U, // ST_FP64m
+ 2147489339U, // ST_FP80m
+ 134223419U, // ST_FPrr
0U, // ST_Fp32m
0U, // ST_Fp64m
0U, // ST_Fp64m32
@@ -2289,51 +2304,51 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // ST_FpP80m
0U, // ST_FpP80m32
0U, // ST_FpP80m64
- 134223367U, // ST_Frr
- 134223378U, // SUB16i16
- 272635420U, // SUB16mi
- 272635420U, // SUB16mi8
- 272635420U, // SUB16mr
- 138548764U, // SUB16ri
- 138548764U, // SUB16ri8
- 138679836U, // SUB16rm
- 138548764U, // SUB16rr
- 138548764U, // SUB16rr_REV
- 134223393U, // SUB32i32
- 406853148U, // SUB32mi
- 406853148U, // SUB32mi8
- 406853148U, // SUB32mr
- 138548764U, // SUB32ri
- 138548764U, // SUB32ri8
- 138810908U, // SUB32rm
- 138548764U, // SUB32rr
- 138548764U, // SUB32rr_REV
- 134223404U, // SUB64i32
- 541070876U, // SUB64mi32
- 541070876U, // SUB64mi8
- 541070876U, // SUB64mr
- 138548764U, // SUB64ri32
- 138548764U, // SUB64ri8
- 138941980U, // SUB64rm
- 138548764U, // SUB64rr
- 138548764U, // SUB64rr_REV
- 134223415U, // SUB8i8
- 675288604U, // SUB8mi
- 675288604U, // SUB8mr
- 138548764U, // SUB8ri
- 139073052U, // SUB8rm
- 138548764U, // SUB8rr
- 138548764U, // SUB8rr_REV
- 139204161U, // SUBPDrm
- 138548801U, // SUBPDrr
- 139204168U, // SUBPSrm
- 138548808U, // SUBPSrr
- 805312079U, // SUBR_F32m
- 939529807U, // SUBR_F64m
- 268441174U, // SUBR_FI16m
- 402658902U, // SUBR_FI32m
- 134223454U, // SUBR_FPrST0
- 134223439U, // SUBR_FST0r
+ 134223414U, // ST_Frr
+ 134223425U, // SUB16i16
+ 272635467U, // SUB16mi
+ 272635467U, // SUB16mi8
+ 272635467U, // SUB16mr
+ 138548811U, // SUB16ri
+ 138548811U, // SUB16ri8
+ 138679883U, // SUB16rm
+ 138548811U, // SUB16rr
+ 138548811U, // SUB16rr_REV
+ 134223440U, // SUB32i32
+ 406853195U, // SUB32mi
+ 406853195U, // SUB32mi8
+ 406853195U, // SUB32mr
+ 138548811U, // SUB32ri
+ 138548811U, // SUB32ri8
+ 138810955U, // SUB32rm
+ 138548811U, // SUB32rr
+ 138548811U, // SUB32rr_REV
+ 134223451U, // SUB64i32
+ 541070923U, // SUB64mi32
+ 541070923U, // SUB64mi8
+ 541070923U, // SUB64mr
+ 138548811U, // SUB64ri32
+ 138548811U, // SUB64ri8
+ 138942027U, // SUB64rm
+ 138548811U, // SUB64rr
+ 138548811U, // SUB64rr_REV
+ 134223462U, // SUB8i8
+ 675288651U, // SUB8mi
+ 675288651U, // SUB8mr
+ 138548811U, // SUB8ri
+ 139073099U, // SUB8rm
+ 138548811U, // SUB8rr
+ 138548811U, // SUB8rr_REV
+ 139204208U, // SUBPDrm
+ 138548848U, // SUBPDrr
+ 139204215U, // SUBPSrm
+ 138548855U, // SUBPSrr
+ 805312126U, // SUBR_F32m
+ 939529854U, // SUBR_F64m
+ 268441221U, // SUBR_FI16m
+ 402658949U, // SUBR_FI32m
+ 134223501U, // SUBR_FPrST0
+ 134223486U, // SUBR_FST0r
0U, // SUBR_Fp32m
0U, // SUBR_Fp64m
0U, // SUBR_Fp64m32
@@ -2345,21 +2360,21 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // SUBR_FpI32m32
0U, // SUBR_FpI32m64
0U, // SUBR_FpI32m80
- 142612047U, // SUBR_FrST0
- 139335270U, // SUBSDrm
- 139335270U, // SUBSDrm_Int
- 138548838U, // SUBSDrr
- 138548838U, // SUBSDrr_Int
- 139466349U, // SUBSSrm
- 139466349U, // SUBSSrm_Int
- 138548845U, // SUBSSrr
- 138548845U, // SUBSSrr_Int
- 805312116U, // SUB_F32m
- 939529844U, // SUB_F64m
- 268441210U, // SUB_FI16m
- 402658938U, // SUB_FI32m
- 134223489U, // SUB_FPrST0
- 134223476U, // SUB_FST0r
+ 142612094U, // SUBR_FrST0
+ 139335317U, // SUBSDrm
+ 139335317U, // SUBSDrm_Int
+ 138548885U, // SUBSDrr
+ 138548885U, // SUBSDrr_Int
+ 139466396U, // SUBSSrm
+ 139466396U, // SUBSSrm_Int
+ 138548892U, // SUBSSrr
+ 138548892U, // SUBSSrr_Int
+ 805312163U, // SUB_F32m
+ 939529891U, // SUB_F64m
+ 268441257U, // SUB_FI16m
+ 402658985U, // SUB_FI32m
+ 134223536U, // SUB_FPrST0
+ 134223523U, // SUB_FST0r
0U, // SUB_Fp32
0U, // SUB_Fp32m
0U, // SUB_Fp64
@@ -2374,182 +2389,182 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // SUB_FpI32m32
0U, // SUB_FpI32m64
0U, // SUB_FpI32m80
- 142612084U, // SUB_FrST0
- 5768U, // SWPGS
- 5774U, // SYSCALL
- 5782U, // SYSENTER
- 5791U, // SYSEXIT
- 5791U, // SYSEXIT64
- 5799U, // SYSRET
- 1166019461U, // TAILJMPd
- 494930821U, // TAILJMPm
- 226495365U, // TAILJMPr
- 226495365U, // TAILJMPr64
- 230692526U, // TCRETURNdi
- 230692526U, // TCRETURNdi64
- 230692526U, // TCRETURNri
- 230692526U, // TCRETURNri64
- 134223546U, // TEST16i16
- 272635589U, // TEST16mi
- 139859653U, // TEST16ri
- 139728581U, // TEST16rm
- 139859653U, // TEST16rr
- 134223563U, // TEST32i32
- 406853317U, // TEST32mi
- 139859653U, // TEST32ri
- 139990725U, // TEST32rm
- 139859653U, // TEST32rr
- 134223575U, // TEST64i32
- 541071045U, // TEST64mi32
- 139859653U, // TEST64ri32
- 140121797U, // TEST64rm
- 139859653U, // TEST64rr
- 134223587U, // TEST8i8
- 675288773U, // TEST8mi
- 139859653U, // TEST8ri
- 140252869U, // TEST8rm
- 139859653U, // TEST8rr
- 2952795886U, // TLS_addr32
- 3087013620U, // TLS_addr64
- 5894U, // TRAP
- 5898U, // TST_F
+ 142612131U, // SUB_FrST0
+ 5815U, // SWAPGS
+ 5822U, // SYSCALL
+ 5830U, // SYSENTER
+ 5839U, // SYSEXIT
+ 5839U, // SYSEXIT64
+ 5847U, // SYSRET
+ 1166019469U, // TAILJMPd
+ 494930829U, // TAILJMPm
+ 226495373U, // TAILJMPr
+ 226495373U, // TAILJMPr64
+ 230692574U, // TCRETURNdi
+ 230692574U, // TCRETURNdi64
+ 230692574U, // TCRETURNri
+ 230692574U, // TCRETURNri64
+ 134223594U, // TEST16i16
+ 272635637U, // TEST16mi
+ 139859701U, // TEST16ri
+ 139728629U, // TEST16rm
+ 139859701U, // TEST16rr
+ 134223611U, // TEST32i32
+ 406853365U, // TEST32mi
+ 139859701U, // TEST32ri
+ 139990773U, // TEST32rm
+ 139859701U, // TEST32rr
+ 134223623U, // TEST64i32
+ 541071093U, // TEST64mi32
+ 139859701U, // TEST64ri32
+ 140121845U, // TEST64rm
+ 139859701U, // TEST64rr
+ 134223635U, // TEST8i8
+ 675288821U, // TEST8mi
+ 139859701U, // TEST8ri
+ 140252917U, // TEST8rm
+ 139859701U, // TEST8rr
+ 2952795934U, // TLS_addr32
+ 3087013668U, // TLS_addr64
+ 5942U, // TRAP
+ 5946U, // TST_F
0U, // TST_Fp32
0U, // TST_Fp64
0U, // TST_Fp80
- 140512069U, // UCOMISDrm
- 139856709U, // UCOMISDrr
- 140643150U, // UCOMISSrm
- 139856718U, // UCOMISSrr
- 134223631U, // UCOM_FIPr
- 134223648U, // UCOM_FIr
- 5936U, // UCOM_FPPr
- 134223672U, // UCOM_FPr
+ 140512077U, // UCOMISDrm
+ 139856717U, // UCOMISDrr
+ 140643158U, // UCOMISSrm
+ 139856726U, // UCOMISSrr
+ 134223679U, // UCOM_FIPr
+ 134223696U, // UCOM_FIr
+ 5984U, // UCOM_FPPr
+ 134223720U, // UCOM_FPr
0U, // UCOM_FpIr32
0U, // UCOM_FpIr64
0U, // UCOM_FpIr80
0U, // UCOM_Fpr32
0U, // UCOM_Fpr64
0U, // UCOM_Fpr80
- 134223680U, // UCOM_Fr
- 139204423U, // UNPCKHPDrm
- 138549063U, // UNPCKHPDrr
- 139204433U, // UNPCKHPSrm
- 138549073U, // UNPCKHPSrr
- 139204443U, // UNPCKLPDrm
- 138549083U, // UNPCKLPDrr
- 139204453U, // UNPCKLPSrm
- 138549093U, // UNPCKLPSrr
- 139876207U, // VASTART_SAVE_XMM_REGS
- 268441479U, // VERRm
- 134223751U, // VERRr
- 268441485U, // VERWm
- 134223757U, // VERWr
- 6035U, // VMCALL
- 536876954U, // VMCLEARm
- 6051U, // VMLAUNCH
- 536876972U, // VMPTRLDm
- 536876981U, // VMPTRSTm
- 406853566U, // VMREAD32rm
- 139859902U, // VMREAD32rr
- 541071294U, // VMREAD64rm
- 139859902U, // VMREAD64rr
- 6086U, // VMRESUME
- 139990991U, // VMWRITE32rm
- 139859919U, // VMWRITE32rr
- 140122063U, // VMWRITE64rm
- 139859919U, // VMWRITE64rr
- 6104U, // VMXOFF
- 6111U, // VMXON
- 140773929U, // V_SET0
- 140774854U, // V_SETALLONES
- 6118U, // WAIT
- 6123U, // WBINVD
- 536871959U, // WINCALL64m
- 1073742871U, // WINCALL64pcrel32
- 134218775U, // WINCALL64r
- 6130U, // WRMSR
- 272635896U, // XADD16rm
- 139859960U, // XADD16rr
- 406853624U, // XADD32rm
- 139859960U, // XADD32rr
- 541071352U, // XADD64rm
- 139859960U, // XADD64rr
- 675289080U, // XADD8rm
- 139859960U, // XADD8rr
- 134223870U, // XCHG16ar
- 2281707529U, // XCHG16rm
- 3221231625U, // XCHG16rr
- 134223887U, // XCHG32ar
- 2415925257U, // XCHG32rm
- 3221231625U, // XCHG32rr
- 134223899U, // XCHG64ar
- 3355449353U, // XCHG64rm
- 3221231625U, // XCHG64rr
- 2550142985U, // XCHG8rm
- 3221231625U, // XCHG8rr
- 134223911U, // XCH_F
- 6189U, // XLAT
- 134223923U, // XOR16i16
- 272633671U, // XOR16mi
- 272633671U, // XOR16mi8
- 272633671U, // XOR16mr
- 138547015U, // XOR16ri
- 138547015U, // XOR16ri8
- 138678087U, // XOR16rm
- 138547015U, // XOR16rr
- 138547015U, // XOR16rr_REV
- 134223933U, // XOR32i32
- 406851399U, // XOR32mi
- 406851399U, // XOR32mi8
- 406851399U, // XOR32mr
- 138547015U, // XOR32ri
- 138547015U, // XOR32ri8
- 138809159U, // XOR32rm
- 138547015U, // XOR32rr
- 138547015U, // XOR32rr_REV
- 134223944U, // XOR64i32
- 541069127U, // XOR64mi32
- 541069127U, // XOR64mi8
- 541069127U, // XOR64mr
- 138547015U, // XOR64ri32
- 138547015U, // XOR64ri8
- 138940231U, // XOR64rm
- 138547015U, // XOR64rr
- 138547015U, // XOR64rr_REV
- 134223955U, // XOR8i8
- 675286855U, // XOR8mi
- 675286855U, // XOR8mr
- 138547015U, // XOR8ri
- 139071303U, // XOR8rm
- 138547015U, // XOR8rr
- 138547015U, // XOR8rr_REV
- 139201058U, // XORPDrm
- 138545698U, // XORPDrr
- 139201065U, // XORPSrm
- 138545705U, // XORPSrr
+ 134223728U, // UCOM_Fr
+ 139204471U, // UNPCKHPDrm
+ 138549111U, // UNPCKHPDrr
+ 139204481U, // UNPCKHPSrm
+ 138549121U, // UNPCKHPSrr
+ 139204491U, // UNPCKLPDrm
+ 138549131U, // UNPCKLPDrr
+ 139204501U, // UNPCKLPSrm
+ 138549141U, // UNPCKLPSrr
+ 139876255U, // VASTART_SAVE_XMM_REGS
+ 268441527U, // VERRm
+ 134223799U, // VERRr
+ 268441533U, // VERWm
+ 134223805U, // VERWr
+ 6083U, // VMCALL
+ 536877002U, // VMCLEARm
+ 6099U, // VMLAUNCH
+ 536877020U, // VMPTRLDm
+ 536877029U, // VMPTRSTm
+ 406853614U, // VMREAD32rm
+ 139859950U, // VMREAD32rr
+ 541071342U, // VMREAD64rm
+ 139859950U, // VMREAD64rr
+ 6134U, // VMRESUME
+ 139991039U, // VMWRITE32rm
+ 139859967U, // VMWRITE32rr
+ 140122111U, // VMWRITE64rm
+ 139859967U, // VMWRITE64rr
+ 6152U, // VMXOFF
+ 6159U, // VMXON
+ 0U, // V_SET0
+ 0U, // V_SETALLONES
+ 6166U, // WAIT
+ 6171U, // WBINVD
+ 536871957U, // WINCALL64m
+ 1073742869U, // WINCALL64pcrel32
+ 134218773U, // WINCALL64r
+ 6178U, // WRMSR
+ 272635944U, // XADD16rm
+ 139860008U, // XADD16rr
+ 406853672U, // XADD32rm
+ 139860008U, // XADD32rr
+ 541071400U, // XADD64rm
+ 139860008U, // XADD64rr
+ 675289128U, // XADD8rm
+ 139860008U, // XADD8rr
+ 134223918U, // XCHG16ar
+ 2281707577U, // XCHG16rm
+ 3221231673U, // XCHG16rr
+ 134223935U, // XCHG32ar
+ 2415925305U, // XCHG32rm
+ 3221231673U, // XCHG32rr
+ 134223947U, // XCHG64ar
+ 3355449401U, // XCHG64rm
+ 3221231673U, // XCHG64rr
+ 2550143033U, // XCHG8rm
+ 3221231673U, // XCHG8rr
+ 134223959U, // XCH_F
+ 6237U, // XLAT
+ 134223971U, // XOR16i16
+ 272636013U, // XOR16mi
+ 272636013U, // XOR16mi8
+ 272636013U, // XOR16mr
+ 138549357U, // XOR16ri
+ 138549357U, // XOR16ri8
+ 138680429U, // XOR16rm
+ 138549357U, // XOR16rr
+ 138549357U, // XOR16rr_REV
+ 134223986U, // XOR32i32
+ 406853741U, // XOR32mi
+ 406853741U, // XOR32mi8
+ 406853741U, // XOR32mr
+ 138549357U, // XOR32ri
+ 138549357U, // XOR32ri8
+ 138811501U, // XOR32rm
+ 138549357U, // XOR32rr
+ 138549357U, // XOR32rr_REV
+ 134223997U, // XOR64i32
+ 541071469U, // XOR64mi32
+ 541071469U, // XOR64mi8
+ 541071469U, // XOR64mr
+ 138549357U, // XOR64ri32
+ 138549357U, // XOR64ri8
+ 138942573U, // XOR64rm
+ 138549357U, // XOR64rr
+ 138549357U, // XOR64rr_REV
+ 134224008U, // XOR8i8
+ 675289197U, // XOR8mi
+ 675289197U, // XOR8mr
+ 138549357U, // XOR8ri
+ 139073645U, // XOR8rm
+ 138549357U, // XOR8rr
+ 138549357U, // XOR8rr_REV
+ 139201054U, // XORPDrm
+ 138545694U, // XORPDrr
+ 139201061U, // XORPSrm
+ 138545701U, // XORPSrr
0U
};
const char *AsmStrs =
- "DEBUG_VALUE\000fabs\000adc\t%ax, \000adc\t\000adc\t%eax, \000adc\t%rax,"
- " \000adc\t%al, \000add\t%ax, \000add\t\000add\t%eax, \000add\t%rax, \000"
- "add\t%al, \000addpd\t\000addps\t\000addsd\t\000addss\t\000addsubpd\t\000"
- "addsubps\t\000fadd\t\000fiadd\t\000faddp\t\000#ADJCALLSTACKDOWN\000#ADJ"
- "CALLSTACKUP\000and\t%ax, \000and\t\000and\t%eax, \000and\t%rax, \000and"
- "\t%al, \000andnpd\t\000andnps\t\000andpd\t\000andps\t\000#ATOMADD6432 P"
- "SEUDO!\000#ATOMAND16 PSEUDO!\000#ATOMAND32 PSEUDO!\000#ATOMAND64 PSEUDO"
- "!\000#ATOMAND6432 PSEUDO!\000#ATOMAND8 PSEUDO!\000#ATOMMAX16 PSEUDO!\000"
- "#ATOMMAX32 PSEUDO!\000#ATOMMAX64 PSEUDO!\000#ATOMMIN16 PSEUDO!\000#ATOM"
- "MIN32 PSEUDO!\000#ATOMMIN64 PSEUDO!\000#ATOMNAND16 PSEUDO!\000#ATOMNAND"
- "32 PSEUDO!\000#ATOMNAND64 PSEUDO!\000#ATOMNAND6432 PSEUDO!\000#ATOMNAND"
- "8 PSEUDO!\000#ATOMOR16 PSEUDO!\000#ATOMOR32 PSEUDO!\000#ATOMOR64 PSEUDO"
- "!\000#ATOMOR6432 PSEUDO!\000#ATOMOR8 PSEUDO!\000#ATOMSUB6432 PSEUDO!\000"
- "#ATOMSWAP6432 PSEUDO!\000#ATOMUMAX16 PSEUDO!\000#ATOMUMAX32 PSEUDO!\000"
- "#ATOMUMAX64 PSEUDO!\000#ATOMUMIN16 PSEUDO!\000#ATOMUMIN32 PSEUDO!\000#A"
- "TOMUMIN64 PSEUDO!\000#ATOMXOR16 PSEUDO!\000#ATOMXOR32 PSEUDO!\000#ATOMX"
- "OR64 PSEUDO!\000#ATOMXOR6432 PSEUDO!\000#ATOMXOR8 PSEUDO!\000blendpd\t\000"
- "blendps\t\000blendvpd\t\000blendvps\t\000bsf\t\000bsr\t\000bswap\t\000b"
- "t\t\000btc\t\000btr\t\000bts\t\000call\t\000cbw\000cdq\000cdqe\000fchs\000"
+ "DBG_VALUE\000fabs\000adc\t%ax, \000adc\t\000adc\t%eax, \000adc\t%rax, \000"
+ "adc\t%al, \000add\t%ax, \000add\t\000add\t%eax, \000add\t%rax, \000add\t"
+ "%al, \000addpd\t\000addps\t\000addsd\t\000addss\t\000addsubpd\t\000adds"
+ "ubps\t\000fadd\t\000fiadd\t\000faddp\t\000#ADJCALLSTACKDOWN\000#ADJCALL"
+ "STACKUP\000and\t%ax, \000and\t\000and\t%eax, \000and\t%rax, \000and\t%a"
+ "l, \000andnpd\t\000andnps\t\000andpd\t\000andps\t\000#ATOMADD6432 PSEUD"
+ "O!\000#ATOMAND16 PSEUDO!\000#ATOMAND32 PSEUDO!\000#ATOMAND64 PSEUDO!\000"
+ "#ATOMAND6432 PSEUDO!\000#ATOMAND8 PSEUDO!\000#ATOMMAX16 PSEUDO!\000#ATO"
+ "MMAX32 PSEUDO!\000#ATOMMAX64 PSEUDO!\000#ATOMMIN16 PSEUDO!\000#ATOMMIN3"
+ "2 PSEUDO!\000#ATOMMIN64 PSEUDO!\000#ATOMNAND16 PSEUDO!\000#ATOMNAND32 P"
+ "SEUDO!\000#ATOMNAND64 PSEUDO!\000#ATOMNAND6432 PSEUDO!\000#ATOMNAND8 PS"
+ "EUDO!\000#ATOMOR16 PSEUDO!\000#ATOMOR32 PSEUDO!\000#ATOMOR64 PSEUDO!\000"
+ "#ATOMOR6432 PSEUDO!\000#ATOMOR8 PSEUDO!\000#ATOMSUB6432 PSEUDO!\000#ATO"
+ "MSWAP6432 PSEUDO!\000#ATOMUMAX16 PSEUDO!\000#ATOMUMAX32 PSEUDO!\000#ATO"
+ "MUMAX64 PSEUDO!\000#ATOMUMIN16 PSEUDO!\000#ATOMUMIN32 PSEUDO!\000#ATOMU"
+ "MIN64 PSEUDO!\000#ATOMXOR16 PSEUDO!\000#ATOMXOR32 PSEUDO!\000#ATOMXOR64"
+ " PSEUDO!\000#ATOMXOR6432 PSEUDO!\000#ATOMXOR8 PSEUDO!\000blendpd\t\000b"
+ "lendps\t\000blendvpd\t\000blendvps\t\000bsf\t\000bsr\t\000bswap\t\000bt"
+ "\t\000btc\t\000btr\t\000bts\t\000call\t\000cbw\000cdq\000cdqe\000fchs\000"
"clc\000cld\000clflush\t\000cli\000clts\000cmc\000cmova\t\000cmovae\t\000"
"cmovb\t\000cmovbe\t\000fcmovbe\t%ST(0), \000fcmovb\t%ST(0), \000cmove\t"
"\000fcmove\t%ST(0), \000cmovg\t\000cmovge\t\000cmovl\t\000cmovle\t\000f"
@@ -2561,119 +2576,102 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
"cmp\t\000cmp\t%eax, \000cmp\t%rax, \000cmp\t%al, \000cmp\000cmps\000cmp"
"xchg16b\t\000cmpxchg\t\000cmpxchg8b\t\000comisd\t\000comiss\t\000fcomp\t"
"\000fcomip\t%ST(0), \000fcomi\t%ST(0), \000fcom\t\000fcos\000cpuid\000c"
- "qo\000crc32 \t\000cvtdq2pd\t\000cvtdq2ps\t\000cvtpd2dq\t\000cvtpd2ps\t\000"
- "cvtps2dq\t\000cvtps2pd\t\000cvtsd2si\t\000cvtsd2ss\t\000cvtsi2sd\t\000c"
- "vtsi2ss\t\000cvtss2sd\t\000cvtss2si\t\000cvttps2dq\t\000cvttsd2si\t\000"
- "cvttss2si\t\000cwd\000cwde\000dec\t\000div\t\000divpd\t\000divps\t\000f"
- "divr\t\000fidivr\t\000fdivrp\t\000divsd\t\000divss\t\000fdiv\t\000fidiv"
- "\t\000fdivp\t\000dppd\t\000dpps\t\000ret\t#eh_return, addr: \000enter\t"
- "\000extractps\t\000f2xm1\000lcall\t\000ljmp\t\000fbld\t\000fbstp\t\000f"
- "compp\000fdecstp\000ffree\t\000ficom\t\000ficomp\t\000fincstp\000fisttp"
- "\t\000fldcw\t\000fldenv\t\000fldl2e\000fldl2t\000fldlg2\000fldln2\000fl"
- "dpi\000fnclex\000fninit\000fnop\000fnstcw\t\000fnstsw %ax\000fnstsw\t\000"
- "##FP32_TO_INT16_IN_MEM PSEUDO!\000##FP32_TO_INT32_IN_MEM PSEUDO!\000##F"
- "P32_TO_INT64_IN_MEM PSEUDO!\000##FP64_TO_INT16_IN_MEM PSEUDO!\000##FP64"
- "_TO_INT32_IN_MEM PSEUDO!\000##FP64_TO_INT64_IN_MEM PSEUDO!\000##FP80_TO"
- "_INT16_IN_MEM PSEUDO!\000##FP80_TO_INT32_IN_MEM PSEUDO!\000##FP80_TO_IN"
- "T64_IN_MEM PSEUDO!\000fpatan\000fprem\000fprem1\000fptan\000##FP_REG_KI"
- "LL\000frndint\000frstor\t\000fnsave\t\000fscale\000fsincos\000fnstenv\t"
- "\000movl\t%fs:\000fxam\000fxrstor\t\000fxsave\t\000fxtract\000fyl2x\000"
- "fyl2xp1\000pxor\t\000movapd\t\000movaps\t\000orpd\t\000orps\t\000xorpd\t"
- "\000xorps\t\000movl\t%gs:\000haddpd\t\000haddps\t\000hlt\000hsubpd\t\000"
- "hsubps\t\000idiv\t\000fild\t\000imul\t\000ins\000in\t%AX, \000in\t%AX, "
- "%DX\000in\t%EAX, \000in\t%EAX, %DX\000in\t%AL, \000in\t%AL, %DX\000inc\t"
- "\000insertps\t\000int\t\000int\t3\000invd\000invept\000invlpg\000invvpi"
- "d\000iret\000fist\t\000fistp\t\000cvtpd2pi\t\000cvtpi2pd\t\000cvtpi2ps\t"
- "\000cvtps2pi\t\000cvttpd2dq\t\000cvttpd2pi\t\000cvttps2pi\t\000ucomisd\t"
- "\000ucomiss\t\000ja\t\000jae\t\000jb\t\000jbe\t\000jcxz\t\000je\t\000jg"
- "\t\000jge\t\000jl\t\000jle\t\000jmp\t\000jne\t\000jno\t\000jnp\t\000jns"
- "\t\000jo\t\000jp\t\000js\t\000lahf\000lar\t\000lock\n\tcmpxchg\t\000loc"
- "k\n\tcmpxchgq\t\000lock\n\tcmpxchg8b\t\000lddqu\t\000ldmxcsr\t\000lds\t"
- "\000fldz\000fld1\000fld\t\000lea\t\000leave\000les\t\000lfence\000lfs\t"
- "\000lgdt\t\000lgs\t\000lidt\t\000lldt\t\000lmsw\t\000lock\n\tadd\t\000l"
- "ock\n\tdec\t\000lock\n\tinc\t\000lock\n\tsub\t\000lodsb\000lodsd\000lod"
- "sq\000lodsw\000loop\t\000loope\t\000loopne\t\000lret\000lret\t\000lsl\t"
- "\000lss\t\000ltr\t\000lock\n\txadd\t\000maskmovdqu\t\000maxpd\t\000maxp"
- "s\t\000maxsd\t\000maxss\t\000mfence\000minpd\t\000minps\t\000minsd\t\000"
- "minss\t\000emms\000femms\000maskmovq\t\000movd\t\000movdq2q\t\000movntq"
- "\t\000movq2dq\t\000movq\t\000packssdw\t\000packsswb\t\000packuswb\t\000"
- "paddb\t\000paddd\t\000paddq\t\000paddsb\t\000paddsw\t\000paddusb\t\000p"
- "addusw\t\000paddw\t\000pandn\t\000pand\t\000pavgb\t\000pavgw\t\000pcmpe"
- "qb\t\000pcmpeqd\t\000pcmpeqw\t\000pcmpgtb\t\000pcmpgtd\t\000pcmpgtw\t\000"
- "pextrw\t\000pinsrw\t\000pmaddwd\t\000pmaxsw\t\000pmaxub\t\000pminsw\t\000"
- "pminub\t\000pmovmskb\t\000pmulhuw\t\000pmulhw\t\000pmullw\t\000pmuludq\t"
- "\000por\t\000psadbw\t\000pshufw\t\000pslld\t\000psllq\t\000psllw\t\000p"
- "srad\t\000psraw\t\000psrld\t\000psrlq\t\000psrlw\t\000psubb\t\000psubd\t"
- "\000psubq\t\000psubsb\t\000psubsw\t\000psubusb\t\000psubusw\t\000psubw\t"
- "\000punpckhbw\t\000punpckhdq\t\000punpckhwd\t\000punpcklbw\t\000punpckl"
- "dq\t\000punpcklwd\t\000monitor\000mov\t\000mov\t%ax, \000mov\t%eax, \000"
- "xor\t\000movq\t%fs:\000movq\t%gs:\000mov\t%rax, \000movabs\t\000mov\t%a"
- "l, \000movddup\t\000movdqa\t\000movdqu\t\000movhlps\t\000movhpd\t\000mo"
- "vhps\t\000movlhps\t\000movlpd\t\000movsd\t\000movlps\t\000movss\t\000mo"
- "vmskpd\t\000movmskps\t\000movntdqa\t\000movntdq\t\000movnti\t\000movntp"
- "d\t\000movntps\t\000movshdup\t\000movsldup\t\000movsx\t\000movsxd\t\000"
- "movupd\t\000movups\t\000movzx\t\000mpsadbw\t\000mul\t\000mulpd\t\000mul"
- "ps\t\000mulsd\t\000mulss\t\000fmul\t\000fimul\t\000fmulp\t\000mwait\000"
- "neg\t\000nop\000nop\t\000not\t\000or\t%ax, \000or\t\000or\t%eax, \000or"
- "\t%rax, \000or\t%al, \000out\t\000out\t%DX, %AX\000out\t%DX, %EAX\000ou"
- "t\t%DX, %AL\000outsb\000outsd\000outsw\000pabsb\t\000pabsd\t\000pabsw\t"
- "\000packusdw\t\000palignr\t\000pblendvb\t\000pblendw\t\000pcmpeqq\t\000"
- "pcmpestri\t\000#PCMPESTRM128rm PSEUDO!\000#PCMPESTRM128rr PSEUDO!\000pc"
- "mpestrm\t\000pcmpgtq\t\000pcmpistri\t\000#PCMPISTRM128rm PSEUDO!\000#PC"
- "MPISTRM128rr PSEUDO!\000pcmpistrm\t\000pextrb\t\000pextrd\t\000pextrq\t"
- "\000phaddd\t\000phaddsw\t\000phaddw\t\000phminposuw\t\000phsubd\t\000ph"
- "subsw\t\000phsubw\t\000pinsrb\t\000pinsrd\t\000pinsrq\t\000pmaddubsw\t\000"
- "pmaxsb\t\000pmaxsd\t\000pmaxud\t\000pmaxuw\t\000pminsb\t\000pminsd\t\000"
- "pminud\t\000pminuw\t\000pmovsxbd\t\000pmovsxbq\t\000pmovsxbw\t\000pmovs"
- "xdq\t\000pmovsxwd\t\000pmovsxwq\t\000pmovzxbd\t\000pmovzxbq\t\000pmovzx"
- "bw\t\000pmovzxdq\t\000pmovzxwd\t\000pmovzxwq\t\000pmuldq\t\000pmulhrsw\t"
- "\000pmulld\t\000pop\t\000popcnt\t\000popf\000pop\t%fs\000pop\t%gs\000pr"
- "efetchnta\t\000prefetcht0\t\000prefetcht1\t\000prefetcht2\t\000pshufb\t"
- "\000pshufd\t\000pshufhw\t\000pshuflw\t\000psignb\t\000psignd\t\000psign"
- "w\t\000pslldq\t\000psrldq\t\000ptest \t\000punpckhqdq\t\000punpcklqdq\t"
- "\000push\t\000pushf\000push\t%fs\000push\t%gs\000rcl\t\000rcpps\t\000rc"
- "pss\t\000rcr\t\000rdmsr\000rdpmc\000rdtsc\000rep movsb\000rep movsd\000"
- "rep movsq\000rep movsw\000rep stosb\000rep stosd\000rep stosq\000rep st"
- "osw\000ret\000ret\t\000rol\t\000ror\t\000roundpd\t\000roundps\t\000roun"
- "dsd\t\000roundss\t\000rsm\000rsqrtps\t\000rsqrtss\t\000sahf\000sar\t\000"
- "sbb\t%ax, \000sbb\t\000sbb\t%eax, \000sbb\t%rax, \000sbb\t%al, \000scas"
- "\000setae\t\000seta\t\000setbe\t\000setb\t\000sete\t\000setge\t\000setg"
- "\t\000setle\t\000setl\t\000setne\t\000setno\t\000setnp\t\000setns\t\000"
- "seto\t\000setp\t\000sets\t\000sfence\000sgdt\t\000shl\t\000shld\t\000sh"
- "r\t\000shrd\t\000shufpd\t\000shufps\t\000sidt\t\000fsin\000sldt\t\000sm"
- "sw\t\000sqrtpd\t\000sqrtps\t\000sqrtsd\t\000sqrtss\t\000fsqrt\000stc\000"
- "std\000sti\000stmxcsr\t\000str\t\000fst\t\000fstp\t\000sub\t%ax, \000su"
- "b\t\000sub\t%eax, \000sub\t%rax, \000sub\t%al, \000subpd\t\000subps\t\000"
- "fsubr\t\000fisubr\t\000fsubrp\t\000subsd\t\000subss\t\000fsub\t\000fisu"
- "b\t\000fsubp\t\000swpgs\000syscall\000sysenter\000sysexit\000sysret\000"
- "#TC_RETURN \000test\t%ax, \000test\t\000test\t%eax, \000test\t%rax, \000"
- "test\t%al, \000leal\t\000.byte\t0x66; leaq\t\000ud2\000ftst\000fucomip\t"
- "%ST(0), \000fucomi\t%ST(0), \000fucompp\000fucomp\t\000fucom\t\000unpck"
- "hpd\t\000unpckhps\t\000unpcklpd\t\000unpcklps\t\000#VASTART_SAVE_XMM_RE"
- "GS \000verr\t\000verw\t\000vmcall\000vmclear\t\000vmlaunch\000vmptrld\t"
- "\000vmptrst\t\000vmread\t\000vmresume\000vmwrite\t\000vmxoff\000vmxon\t"
- "\000wait\000wbinvd\000wrmsr\000xadd\t\000xchg\t%ax, \000xchg\t\000xchg\t"
- "%eax, \000xchg\t%rax, \000fxch\t\000xlatb\000xor\t%ax, \000xor\t%eax, \000"
- "xor\t%rax, \000xor\t%al, \000";
+ "qo\000crc32 \t\000cs\000cvtdq2pd\t\000cvtdq2ps\t\000cvtpd2dq\t\000cvtpd"
+ "2ps\t\000cvtps2dq\t\000cvtps2pd\t\000cvtsd2si\t\000cvtsd2ss\t\000cvtsi2"
+ "sd\t\000cvtsi2ss\t\000cvtss2sd\t\000cvtss2si\t\000cvttps2dq\t\000cvttsd"
+ "2si\t\000cvttss2si\t\000cwd\000cwde\000dec\t\000div\t\000divpd\t\000div"
+ "ps\t\000fdivr\t\000fidivr\t\000fdivrp\t\000divsd\t\000divss\t\000fdiv\t"
+ "\000fidiv\t\000fdivp\t\000dppd\t\000dpps\t\000ds\000ret\t#eh_return, ad"
+ "dr: \000enter\t\000es\000extractps\t\000f2xm1\000lcall\t\000ljmp\t\000f"
+ "bld\t\000fbstp\t\000fcompp\000fdecstp\000ffree\t\000ficom\t\000ficomp\t"
+ "\000fincstp\000fldcw\t\000fldenv\t\000fldl2e\000fldl2t\000fldlg2\000fld"
+ "ln2\000fldpi\000fnclex\000fninit\000fnop\000fnstcw\t\000fnstsw %ax\000f"
+ "nstsw\t\000##FP32_TO_INT16_IN_MEM PSEUDO!\000##FP32_TO_INT32_IN_MEM PSE"
+ "UDO!\000##FP32_TO_INT64_IN_MEM PSEUDO!\000##FP64_TO_INT16_IN_MEM PSEUDO"
+ "!\000##FP64_TO_INT32_IN_MEM PSEUDO!\000##FP64_TO_INT64_IN_MEM PSEUDO!\000"
+ "##FP80_TO_INT16_IN_MEM PSEUDO!\000##FP80_TO_INT32_IN_MEM PSEUDO!\000##F"
+ "P80_TO_INT64_IN_MEM PSEUDO!\000fpatan\000fprem\000fprem1\000fptan\000##"
+ "FP_REG_KILL\000frndint\000frstor\t\000fnsave\t\000fscale\000fsincos\000"
+ "fnstenv\t\000movl\t%fs:\000fs\000fxam\000fxrstor\t\000fxsave\t\000fxtra"
+ "ct\000fyl2x\000fyl2xp1\000movapd\t\000movaps\t\000orpd\t\000orps\t\000x"
+ "orpd\t\000xorps\t\000movl\t%gs:\000gs\000haddpd\t\000haddps\t\000hlt\000"
+ "hsubpd\t\000hsubps\t\000idiv\t\000fild\t\000imul\t\000ins\000in\t%AX, \000"
+ "in\t%AX, %DX\000in\t%EAX, \000in\t%EAX, %DX\000in\t%AL, \000in\t%AL, %D"
+ "X\000inc\t\000insertps\t\000int\t\000int\t3\000invd\000invept\000invlpg"
+ "\t\000invvpid\000iret\000fisttp\t\000fist\t\000fistp\t\000cvtpd2pi\t\000"
+ "cvtpi2pd\t\000cvtpi2ps\t\000cvtps2pi\t\000cvttpd2dq\t\000cvttpd2pi\t\000"
+ "cvttps2pi\t\000ucomisd\t\000ucomiss\t\000jae\t\000ja\t\000jbe\t\000jb\t"
+ "\000jcxz\t\000je\t\000jge\t\000jg\t\000jle\t\000jl\t\000jmp\t\000jne\t\000"
+ "jno\t\000jnp\t\000jns\t\000jo\t\000jp\t\000js\t\000lahf\000lar\t\000loc"
+ "k\n\tcmpxchg\t\000lock\n\tcmpxchgq\t\000lock\n\tcmpxchg8b\t\000lddqu\t\000"
+ "ldmxcsr\t\000lds\t\000fldz\000fld1\000fld\t\000lea\t\000leave\000les\t\000"
+ "lfence\000lfs\t\000lgdt\t\000lgs\t\000lidt\t\000lldt\t\000lmsw\t\000loc"
+ "k\n\tadd\t\000lock\n\tdec\t\000lock\n\tinc\t\000lock\000lock\n\tsub\t\000"
+ "lodsb\000lodsd\000lodsq\000lodsw\000loop\t\000loope\t\000loopne\t\000lr"
+ "et\000lret\t\000lsl\t\000lss\t\000ltr\t\000lock\n\txadd\t\000maskmovdqu"
+ "\t\000maxpd\t\000maxps\t\000maxsd\t\000maxss\t\000mfence\000minpd\t\000"
+ "minps\t\000minsd\t\000minss\t\000emms\000femms\000maskmovq\t\000movd\t\000"
+ "movdq2q\t\000movntq\t\000movq2dq\t\000movq\t\000packssdw\t\000packsswb\t"
+ "\000packuswb\t\000paddb\t\000paddd\t\000paddq\t\000paddsb\t\000paddsw\t"
+ "\000paddusb\t\000paddusw\t\000paddw\t\000pandn\t\000pand\t\000pavgb\t\000"
+ "pavgw\t\000pcmpeqb\t\000pcmpeqd\t\000pcmpeqw\t\000pcmpgtb\t\000pcmpgtd\t"
+ "\000pcmpgtw\t\000pextrw\t\000pinsrw\t\000pmaddwd\t\000pmaxsw\t\000pmaxu"
+ "b\t\000pminsw\t\000pminub\t\000pmovmskb\t\000pmulhuw\t\000pmulhw\t\000p"
+ "mullw\t\000pmuludq\t\000por\t\000psadbw\t\000pshufw\t\000pslld\t\000psl"
+ "lq\t\000psllw\t\000psrad\t\000psraw\t\000psrld\t\000psrlq\t\000psrlw\t\000"
+ "psubb\t\000psubd\t\000psubq\t\000psubsb\t\000psubsw\t\000psubusb\t\000p"
+ "subusw\t\000psubw\t\000punpckhbw\t\000punpckhdq\t\000punpckhwd\t\000pun"
+ "pcklbw\t\000punpckldq\t\000punpcklwd\t\000pxor\t\000monitor\000mov\t\000"
+ "mov\t%ax, \000mov\t%eax, \000movq\t%fs:\000movq\t%gs:\000mov\t%rax, \000"
+ "movabs\t\000mov\t%al, \000movddup\t\000movdqa\t\000movdqu\t\000movhlps\t"
+ "\000movhpd\t\000movhps\t\000movlhps\t\000movlpd\t\000movsd\t\000movlps\t"
+ "\000movss\t\000movmskpd\t\000movmskps\t\000movntdqa\t\000movntdq\t\000m"
+ "ovnti\t\000movntpd\t\000movntps\t\000\000movsd\000movshdup\t\000movsldu"
+ "p\t\000movsx\t\000movsxd\t\000movupd\t\000movups\t\000movzx\t\000mpsadb"
+ "w\t\000mul\t\000mulpd\t\000mulps\t\000mulsd\t\000mulss\t\000fmul\t\000f"
+ "imul\t\000fmulp\t\000mwait\000neg\t\000nop\000nop\t\000not\t\000or\t%ax"
+ ", \000or\t\000or\t%eax, \000or\t%rax, \000or\t%al, \000out\t\000out\t%D"
+ "X, %AX\000out\t%DX, %EAX\000out\t%DX, %AL\000outsb\000outsd\000outsw\000"
+ "pabsb\t\000pabsd\t\000pabsw\t\000packusdw\t\000palignr\t\000pblendvb\t\000"
+ "pblendw\t\000pcmpeqq\t\000pcmpestri\t\000#PCMPESTRM128rm PSEUDO!\000#PC"
+ "MPESTRM128rr PSEUDO!\000pcmpestrm\t\000pcmpgtq\t\000pcmpistri\t\000#PCM"
+ "PISTRM128rm PSEUDO!\000#PCMPISTRM128rr PSEUDO!\000pcmpistrm\t\000pextrb"
+ "\t\000pextrd\t\000pextrq\t\000phaddd\t\000phaddsw\t\000phaddw\t\000phmi"
+ "nposuw\t\000phsubd\t\000phsubsw\t\000phsubw\t\000pinsrb\t\000pinsrd\t\000"
+ "pinsrq\t\000pmaddubsw\t\000pmaxsb\t\000pmaxsd\t\000pmaxud\t\000pmaxuw\t"
+ "\000pminsb\t\000pminsd\t\000pminud\t\000pminuw\t\000pmovsxbd\t\000pmovs"
+ "xbq\t\000pmovsxbw\t\000pmovsxdq\t\000pmovsxwd\t\000pmovsxwq\t\000pmovzx"
+ "bd\t\000pmovzxbq\t\000pmovzxbw\t\000pmovzxdq\t\000pmovzxwd\t\000pmovzxw"
+ "q\t\000pmuldq\t\000pmulhrsw\t\000pmulld\t\000pop\t\000popcnt\t\000popf\000"
+ "pop\t%fs\000pop\t%gs\000prefetchnta\t\000prefetcht0\t\000prefetcht1\t\000"
+ "prefetcht2\t\000pshufb\t\000pshufd\t\000pshufhw\t\000pshuflw\t\000psign"
+ "b\t\000psignd\t\000psignw\t\000pslldq\t\000psrldq\t\000ptest \t\000punp"
+ "ckhqdq\t\000punpcklqdq\t\000push\t\000pushf\000push\t%fs\000push\t%gs\000"
+ "rcl\t\000rcpps\t\000rcpss\t\000rcr\t\000rdmsr\000rdpmc\000rdtsc\000rdts"
+ "cp\000repne\000rep movsb\000rep movsd\000rep movsq\000rep movsw\000rep\000"
+ "rep stosb\000rep stosd\000rep stosq\000rep stosw\000ret\000ret\t\000rol"
+ "\t\000ror\t\000roundpd\t\000roundps\t\000roundsd\t\000roundss\t\000rsm\000"
+ "rsqrtps\t\000rsqrtss\t\000sahf\000sar\t\000sbb\t%ax, \000sbb\t\000sbb\t"
+ "%eax, \000sbb\t%rax, \000sbb\t%al, \000scas\000setae\t\000seta\t\000set"
+ "be\t\000setb\t\000sete\t\000setge\t\000setg\t\000setle\t\000setl\t\000s"
+ "etne\t\000setno\t\000setnp\t\000setns\t\000seto\t\000setp\t\000sets\t\000"
+ "sfence\000sgdt\t\000shl\t\000shld\t\000shr\t\000shrd\t\000shufpd\t\000s"
+ "hufps\t\000sidt\t\000fsin\000sldt\t\000smsw\t\000sqrtpd\t\000sqrtps\t\000"
+ "sqrtsd\t\000sqrtss\t\000fsqrt\000ss\000stc\000std\000sti\000stmxcsr\t\000"
+ "stosd\000str\t\000fst\t\000fstp\t\000sub\t%ax, \000sub\t\000sub\t%eax, "
+ "\000sub\t%rax, \000sub\t%al, \000subpd\t\000subps\t\000fsubr\t\000fisub"
+ "r\t\000fsubrp\t\000subsd\t\000subss\t\000fsub\t\000fisub\t\000fsubp\t\000"
+ "swapgs\000syscall\000sysenter\000sysexit\000sysret\000#TC_RETURN \000te"
+ "st\t%ax, \000test\t\000test\t%eax, \000test\t%rax, \000test\t%al, \000l"
+ "eal\t\000.byte\t0x66; leaq\t\000ud2\000ftst\000fucomip\t%ST(0), \000fuc"
+ "omi\t%ST(0), \000fucompp\000fucomp\t\000fucom\t\000unpckhpd\t\000unpckh"
+ "ps\t\000unpcklpd\t\000unpcklps\t\000#VASTART_SAVE_XMM_REGS \000verr\t\000"
+ "verw\t\000vmcall\000vmclear\t\000vmlaunch\000vmptrld\t\000vmptrst\t\000"
+ "vmread\t\000vmresume\000vmwrite\t\000vmxoff\000vmxon\t\000wait\000wbinv"
+ "d\000wrmsr\000xadd\t\000xchg\t%ax, \000xchg\t\000xchg\t%eax, \000xchg\t"
+ "%rax, \000fxch\t\000xlatb\000xor\t%ax, \000xor\t\000xor\t%eax, \000xor\t"
+ "%rax, \000xor\t%al, \000";
-
-#ifndef NO_ASM_WRITER_BOILERPLATE
- if (MI->getOpcode() == TargetInstrInfo::INLINEASM) {
- printInlineAsm(MI);
- return;
- } else if (MI->isLabel()) {
- printLabel(MI);
- return;
- } else if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
- printImplicitDef(MI);
- return;
- } else if (MI->getOpcode() == TargetInstrInfo::KILL) {
- printKill(MI);
- return;
- }
-
-
-#endif
O << "\t";
// Emit the opcode for the instruction.
@@ -2686,7 +2684,7 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
switch ((Bits >> 27) & 31) {
default: // unreachable.
case 0:
- // DEBUG_VALUE, ABS_F, ADJCALLSTACKDOWN32, ADJCALLSTACKDOWN64, ADJCALLSTA...
+ // DBG_VALUE, ABS_F, ADJCALLSTACKDOWN32, ADJCALLSTACKDOWN64, ADJCALLSTACK...
return;
break;
case 1:
@@ -2718,7 +2716,7 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
printf64mem(MI, 0);
break;
case 8:
- // CALL64pcrel32, CALLpcrel32, JA, JA8, JAE, JAE8, JB, JB8, JBE, JBE8, JC...
+ // CALL64pcrel32, CALLpcrel32, JAE_1, JAE_4, JA_1, JA_4, JBE_1, JBE_4, JB...
print_pcrel_imm(MI, 0);
break;
case 9:
@@ -2955,7 +2953,7 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
}
- // Fragment 2 encoded into 5 bits for 25 unique commands.
+ // Fragment 2 encoded into 5 bits for 23 unique commands.
switch ((Bits >> 17) & 31) {
default: // unreachable.
case 0:
@@ -3033,39 +3031,29 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
return;
break;
case 18:
- // FsFLD0SD, FsFLD0SS, MMX_V_SET0, MMX_V_SETALLONES, MOV32r0, MOV8r0, SET...
- printOperand(MI, 0);
- return;
- break;
- case 19:
// Int_CVTDQ2PSrm, LDDQUrm, MOVDQArm, MOVDQUrm, MOVDQUrm_Int, MOVNTDQArm,...
printi128mem(MI, 1);
break;
- case 20:
+ case 19:
// LDS16rm, LDS32rm, LES16rm, LES32rm, LFS16rm, LFS32rm, LFS64rm, LGS16rm...
printopaquemem(MI, 1);
return;
break;
- case 21:
+ case 20:
// LEA16r, LEA32r
printlea32mem(MI, 1);
return;
break;
- case 22:
+ case 21:
// LEA64_32r
printlea64_32mem(MI, 1);
return;
break;
- case 23:
+ case 22:
// LEA64r
printlea64mem(MI, 1);
return;
break;
- case 24:
- // RCL16mi, RCL32mi, RCL64mi, RCL8mi, RCR16mi, RCR32mi, RCR64mi, RCR8mi
- printOperand(MI, 10);
- return;
- break;
}
@@ -3377,3 +3365,659 @@ const char *X86IntelInstPrinter::getRegisterName(unsigned RegNo) {
"\000ymm7\000ymm8\000ymm9\000";
return AsmStrs+RegAsmOffset[RegNo-1];
}
+
+
+#ifdef GET_INSTRUCTION_NAME
+#undef GET_INSTRUCTION_NAME
+
+/// getInstructionName: This method is automatically generated by tblgen
+/// from the instruction set description. This returns the enum name of the
+/// specified instruction.
+const char *X86IntelInstPrinter::getInstructionName(unsigned Opcode) {
+ assert(Opcode < 2532 && "Invalid instruction number!");
+
+ static const unsigned InstAsmOffset[] = {
+ 0, 4, 14, 24, 33, 42, 47, 62, 76, 89, 103, 120, 130, 136,
+ 145, 154, 163, 172, 180, 189, 197, 205, 214, 222, 230, 242, 251, 259,
+ 268, 276, 284, 293, 301, 309, 321, 330, 340, 349, 357, 367, 376, 384,
+ 392, 404, 411, 418, 425, 432, 439, 446, 457, 466, 474, 483, 491, 502,
+ 510, 519, 527, 535, 544, 552, 561, 569, 580, 588, 597, 605, 613, 622,
+ 632, 641, 649, 660, 670, 679, 687, 695, 702, 709, 716, 726, 733, 740,
+ 747, 755, 763, 771, 779, 787, 799, 807, 819, 827, 839, 847, 859, 870,
+ 881, 892, 903, 912, 921, 931, 941, 952, 962, 971, 981, 990, 1000, 1012,
+ 1021, 1033, 1045, 1058, 1071, 1084, 1097, 1110, 1123, 1133, 1152, 1171, 1188, 1205,
+ 1214, 1222, 1231, 1239, 1247, 1256, 1264, 1272, 1284, 1293, 1301, 1310, 1318, 1326,
+ 1335, 1343, 1351, 1363, 1372, 1382, 1391, 1399, 1409, 1418, 1426, 1434, 1446, 1453,
+ 1460, 1467, 1474, 1481, 1488, 1499, 1508, 1517, 1526, 1535, 1543, 1551, 1559, 1567,
+ 1579, 1589, 1599, 1609, 1621, 1630, 1640, 1650, 1660, 1670, 1680, 1690, 1701, 1712,
+ 1723, 1736, 1746, 1755, 1764, 1773, 1784, 1792, 1804, 1817, 1828, 1839, 1850, 1861,
+ 1872, 1883, 1893, 1903, 1913, 1925, 1934, 1945, 1956, 1967, 1978, 1990, 2002, 2014,
+ 2026, 2034, 2042, 2050, 2058, 2066, 2074, 2082, 2090, 2098, 2106, 2114, 2122, 2131,
+ 2140, 2148, 2155, 2163, 2170, 2178, 2185, 2193, 2200, 2208, 2215, 2223, 2230, 2239,
+ 2247, 2256, 2264, 2273, 2281, 2290, 2298, 2307, 2315, 2324, 2332, 2341, 2349, 2358,
+ 2366, 2375, 2383, 2392, 2400, 2409, 2417, 2426, 2434, 2443, 2451, 2460, 2468, 2477,
+ 2485, 2494, 2502, 2511, 2519, 2528, 2536, 2544, 2552, 2560, 2574, 2582, 2594, 2598,
+ 2602, 2607, 2613, 2622, 2631, 2640, 2644, 2648, 2656, 2660, 2665, 2669, 2679, 2689,
+ 2699, 2709, 2719, 2729, 2740, 2751, 2762, 2773, 2784, 2795, 2805, 2815, 2825, 2835,
+ 2845, 2855, 2866, 2877, 2888, 2899, 2910, 2921, 2930, 2942, 2954, 2966, 2974, 2985,
+ 2996, 3007, 3017, 3027, 3037, 3047, 3057, 3067, 3075, 3086, 3097, 3108, 3118, 3128,
+ 3138, 3148, 3158, 3168, 3179, 3190, 3201, 3212, 3223, 3234, 3244, 3254, 3264, 3274,
+ 3284, 3294, 3305, 3316, 3327, 3338, 3349, 3360, 3370, 3383, 3396, 3409, 3418, 3430,
+ 3442, 3454, 3465, 3476, 3487, 3498, 3509, 3520, 3529, 3541, 3553, 3565, 3576, 3587,
+ 3598, 3609, 3620, 3631, 3642, 3653, 3664, 3675, 3686, 3697, 3706, 3718, 3730, 3742,
+ 3753, 3764, 3775, 3786, 3797, 3808, 3818, 3828, 3838, 3848, 3858, 3868, 3878, 3888,
+ 3898, 3908, 3918, 3928, 3936, 3947, 3958, 3969, 3979, 3989, 3999, 4009, 4019, 4029,
+ 4039, 4049, 4058, 4069, 4080, 4091, 4102, 4111, 4119, 4128, 4136, 4147, 4155, 4164,
+ 4172, 4180, 4189, 4197, 4206, 4214, 4225, 4233, 4242, 4250, 4258, 4267, 4277, 4286,
+ 4294, 4305, 4315, 4324, 4332, 4340, 4347, 4354, 4361, 4371, 4378, 4385, 4392, 4401,
+ 4410, 4419, 4428, 4435, 4442, 4449, 4455, 4463, 4471, 4479, 4487, 4498, 4510, 4522,
+ 4534, 4546, 4558, 4570, 4580, 4591, 4602, 4611, 4620, 4629, 4638, 4649, 4658, 4666,
+ 4676, 4682, 4691, 4700, 4709, 4715, 4719, 4728, 4737, 4745, 4754, 4763, 4771, 4780,
+ 4789, 4799, 4810, 4821, 4832, 4843, 4854, 4865, 4876, 4887, 4898, 4909, 4920, 4931,
+ 4944, 4957, 4968, 4979, 4992, 5005, 5016, 5027, 5040, 5053, 5064, 5075, 5086, 5097,
+ 5110, 5123, 5134, 5145, 5157, 5169, 5183, 5197, 5209, 5221, 5235, 5249, 5261, 5273,
+ 5277, 5282, 5289, 5296, 5303, 5310, 5320, 5330, 5340, 5350, 5357, 5364, 5370, 5376,
+ 5383, 5390, 5397, 5404, 5411, 5418, 5424, 5430, 5438, 5446, 5454, 5462, 5472, 5482,
+ 5493, 5504, 5516, 5527, 5538, 5549, 5562, 5575, 5588, 5602, 5616, 5630, 5644, 5658,
+ 5672, 5683, 5691, 5703, 5711, 5723, 5731, 5743, 5751, 5763, 5772, 5781, 5791, 5801,
+ 5812, 5822, 5831, 5841, 5850, 5860, 5872, 5881, 5893, 5905, 5918, 5931, 5944, 5957,
+ 5970, 5983, 5993, 6001, 6009, 6017, 6025, 6035, 6045, 6057, 6063, 6073, 6085, 6097,
+ 6103, 6114, 6125, 6136, 6147, 6157, 6167, 6177, 6187, 6197, 6206, 6212, 6219, 6227,
+ 6235, 6244, 6253, 6260, 6268, 6274, 6283, 6292, 6302, 6312, 6320, 6329, 6337, 6344,
+ 6351, 6358, 6365, 6371, 6378, 6385, 6390, 6400, 6409, 6417, 6438, 6459, 6480, 6501,
+ 6522, 6543, 6564, 6585, 6606, 6613, 6619, 6626, 6632, 6644, 6652, 6660, 6667, 6674,
+ 6682, 6690, 6701, 6711, 6716, 6724, 6731, 6739, 6745, 6753, 6766, 6779, 6792, 6805,
+ 6818, 6831, 6844, 6857, 6870, 6883, 6896, 6909, 6920, 6931, 6942, 6953, 6963, 6973,
+ 6983, 6993, 7002, 7011, 7022, 7033, 7044, 7055, 7064, 7073, 7082, 7091, 7101, 7111,
+ 7121, 7131, 7142, 7152, 7161, 7170, 7179, 7188, 7192, 7201, 7210, 7219, 7228, 7236,
+ 7244, 7252, 7260, 7268, 7276, 7283, 7290, 7299, 7308, 7317, 7329, 7341, 7353, 7365,
+ 7377, 7389, 7401, 7413, 7425, 7433, 7441, 7450, 7460, 7471, 7480, 7490, 7501, 7509,
+ 7517, 7526, 7536, 7547, 7556, 7566, 7577, 7585, 7593, 7602, 7614, 7625, 7634, 7646,
+ 7657, 7664, 7671, 7676, 7683, 7690, 7695, 7702, 7709, 7713, 7719, 7725, 7732, 7739,
+ 7746, 7753, 7763, 7773, 7783, 7793, 7800, 7807, 7813, 7819, 7830, 7841, 7845, 7850,
+ 7855, 7862, 7869, 7877, 7884, 7891, 7898, 7909, 7920, 7931, 7944, 7957, 7970, 7983,
+ 7996, 8009, 8022, 8035, 8048, 8057, 8066, 8076, 8086, 8096, 8108, 8120, 8132, 8144,
+ 8156, 8168, 8180, 8192, 8204, 8216, 8228, 8240, 8252, 8265, 8278, 8291, 8304, 8319,
+ 8334, 8349, 8364, 8379, 8394, 8409, 8424, 8439, 8454, 8469, 8484, 8499, 8514, 8529,
+ 8544, 8559, 8574, 8589, 8604, 8621, 8638, 8653, 8668, 8683, 8698, 8715, 8732, 8747,
+ 8762, 8779, 8796, 8811, 8826, 8841, 8856, 8873, 8890, 8905, 8920, 8936, 8952, 8968,
+ 8984, 9000, 9016, 9032, 9048, 9066, 9084, 9100, 9116, 9134, 9152, 9168, 9184, 9198,
+ 9212, 9226, 9240, 9246, 9252, 9257, 9262, 9268, 9274, 9279, 9284, 9290, 9295, 9300,
+ 9306, 9312, 9317, 9322, 9328, 9334, 9339, 9344, 9351, 9358, 9365, 9378, 9385, 9391,
+ 9397, 9403, 9409, 9415, 9421, 9427, 9433, 9439, 9445, 9450, 9455, 9460, 9465, 9470,
+ 9475, 9480, 9488, 9496, 9504, 9512, 9520, 9528, 9539, 9550, 9561, 9571, 9582, 9590,
+ 9598, 9606, 9614, 9620, 9626, 9634, 9642, 9650, 9659, 9668, 9677, 9686, 9695, 9704,
+ 9713, 9724, 9735, 9744, 9755, 9764, 9771, 9778, 9785, 9795, 9802, 9808, 9816, 9824,
+ 9832, 9839, 9847, 9855, 9863, 9869, 9877, 9885, 9893, 9899, 9907, 9915, 9923, 9931,
+ 9944, 9958, 9971, 9984, 9998, 10011, 10026, 10040, 10053, 10065, 10077, 10089, 10101, 10113,
+ 10124, 10136, 10148, 10160, 10171, 10183, 10196, 10210, 10223, 10236, 10250, 10263, 10278, 10292,
+ 10305, 10317, 10329, 10335, 10341, 10347, 10353, 10358, 10364, 10371, 10376, 10382, 10390, 10398,
+ 10406, 10414, 10422, 10430, 10438, 10446, 10454, 10459, 10464, 10472, 10480, 10488, 10495, 10506,
+ 10519, 10527, 10539, 10547, 10559, 10567, 10579, 10587, 10599, 10607, 10619, 10627, 10639, 10647,
+ 10659, 10667, 10679, 10686, 10694, 10706, 10714, 10726, 10734, 10746, 10754, 10766, 10774, 10786,
+ 10794, 10806, 10814, 10826, 10834, 10846, 10861, 10876, 10891, 10906, 10921, 10936, 10951, 10966,
+ 10982, 10998, 11014, 11030, 11039, 11049, 11062, 11077, 11096, 11110, 11123, 11136, 11149, 11166,
+ 11183, 11197, 11210, 11224, 11240, 11254, 11267, 11280, 11293, 11310, 11327, 11342, 11357, 11372,
+ 11387, 11402, 11417, 11429, 11441, 11453, 11465, 11477, 11489, 11502, 11515, 11528, 11541, 11555,
+ 11569, 11583, 11597, 11609, 11621, 11633, 11645, 11656, 11667, 11679, 11691, 11703, 11715, 11729,
+ 11743, 11757, 11771, 11785, 11799, 11813, 11827, 11841, 11855, 11869, 11883, 11896, 11910, 11924,
+ 11938, 11952, 11965, 11978, 11991, 12004, 12017, 12030, 12043, 12056, 12071, 12085, 12099, 12112,
+ 12125, 12138, 12151, 12165, 12179, 12189, 12199, 12212, 12225, 12238, 12251, 12263, 12275, 12287,
+ 12299, 12311, 12323, 12335, 12347, 12359, 12371, 12383, 12395, 12407, 12419, 12431, 12443, 12455,
+ 12467, 12479, 12491, 12503, 12515, 12527, 12539, 12551, 12563, 12575, 12587, 12599, 12611, 12624,
+ 12637, 12650, 12663, 12677, 12691, 12705, 12719, 12731, 12743, 12759, 12775, 12791, 12807, 12823,
+ 12839, 12855, 12871, 12887, 12903, 12919, 12935, 12946, 12957, 12968, 12985, 12993, 13003, 13011,
+ 13019, 13027, 13037, 13045, 13053, 13061, 13069, 13081, 13089, 13097, 13105, 13115, 13123, 13131,
+ 13139, 13147, 13157, 13165, 13173, 13181, 13189, 13197, 13205, 13217, 13227, 13237, 13247, 13256,
+ 13264, 13272, 13282, 13290, 13298, 13308, 13317, 13325, 13333, 13341, 13349, 13359, 13372, 13380,
+ 13388, 13400, 13408, 13416, 13424, 13437, 13449, 13461, 13469, 13476, 13483, 13496, 13504, 13511,
+ 13518, 13525, 13538, 13545, 13558, 13569, 13578, 13587, 13596, 13605, 13614, 13623, 13633, 13643,
+ 13655, 13667, 13678, 13689, 13698, 13707, 13716, 13725, 13738, 13747, 13760, 13770, 13779, 13788,
+ 13797, 13806, 13816, 13825, 13834, 13843, 13852, 13861, 13870, 13881, 13893, 13905, 13916, 13927,
+ 13938, 13948, 13957, 13967, 13977, 13986, 13997, 14008, 14020, 14032, 14044, 14057, 14068, 14079,
+ 14091, 14100, 14106, 14112, 14123, 14134, 14142, 14150, 14158, 14170, 14182, 14193, 14204, 14215,
+ 14226, 14237, 14248, 14259, 14270, 14278, 14286, 14294, 14300, 14311, 14323, 14334, 14346, 14358,
+ 14369, 14381, 14392, 14404, 14416, 14427, 14439, 14451, 14462, 14471, 14484, 14493, 14506, 14515,
+ 14524, 14537, 14546, 14559, 14568, 14581, 14594, 14610, 14626, 14639, 14652, 14664, 14676, 14687,
+ 14699, 14710, 14722, 14739, 14756, 14768, 14779, 14791, 14802, 14814, 14828, 14840, 14851, 14864,
+ 14876, 14890, 14902, 14913, 14926, 14937, 14948, 14959, 14970, 14981, 14992, 15003, 15014, 15025,
+ 15036, 15047, 15054, 15061, 15068, 15075, 15082, 15089, 15095, 15101, 15109, 15117, 15125, 15133,
+ 15141, 15153, 15161, 15173, 15181, 15193, 15201, 15213, 15222, 15231, 15241, 15251, 15262, 15272,
+ 15281, 15291, 15300, 15310, 15322, 15331, 15343, 15355, 15368, 15381, 15394, 15407, 15420, 15433,
+ 15443, 15449, 15456, 15463, 15470, 15477, 15484, 15491, 15497, 15503, 15508, 15514, 15520, 15527,
+ 15534, 15541, 15548, 15555, 15562, 15568, 15574, 15582, 15589, 15597, 15604, 15611, 15619, 15626,
+ 15633, 15644, 15652, 15659, 15667, 15674, 15681, 15689, 15696, 15703, 15714, 15722, 15731, 15739,
+ 15746, 15755, 15763, 15770, 15777, 15788, 15794, 15800, 15806, 15812, 15818, 15824, 15834, 15841,
+ 15848, 15855, 15862, 15870, 15878, 15886, 15894, 15901, 15908, 15914, 15920, 15926, 15937, 15947,
+ 15958, 15968, 15979, 15989, 16000, 16010, 16021, 16031, 16042, 16052, 16063, 16074, 16085, 16096,
+ 16107, 16118, 16129, 16140, 16148, 16156, 16164, 16172, 16180, 16188, 16197, 16206, 16215, 16224,
+ 16234, 16244, 16254, 16264, 16272, 16280, 16293, 16306, 16318, 16330, 16338, 16346, 16353, 16360,
+ 16368, 16376, 16384, 16392, 16404, 16416, 16427, 16438, 16448, 16458, 16468, 16478, 16488, 16498,
+ 16508, 16518, 16531, 16544, 16557, 16570, 16583, 16596, 16609, 16622, 16635, 16648, 16660, 16672,
+ 16688, 16704, 16719, 16734, 16744, 16754, 16764, 16774, 16784, 16794, 16804, 16814, 16827, 16840,
+ 16853, 16866, 16879, 16892, 16905, 16918, 16931, 16944, 16956, 16968, 16984, 17000, 17015, 17030,
+ 17039, 17048, 17057, 17066, 17075, 17084, 17093, 17102, 17114, 17125, 17137, 17148, 17161, 17173,
+ 17186, 17198, 17210, 17221, 17233, 17244, 17260, 17276, 17288, 17299, 17311, 17322, 17335, 17347,
+ 17360, 17372, 17384, 17395, 17407, 17418, 17427, 17436, 17445, 17454, 17463, 17472, 17482, 17492,
+ 17507, 17521, 17536, 17550, 17560, 17570, 17579, 17588, 17597, 17606, 17615, 17624, 17633, 17642,
+ 17651, 17660, 17669, 17678, 17687, 17696, 17705, 17714, 17723, 17732, 17741, 17750, 17759, 17768,
+ 17777, 17786, 17797, 17808, 17819, 17830, 17841, 17852, 17863, 17874, 17885, 17896, 17907, 17918,
+ 17929, 17940, 17951, 17962, 17973, 17984, 17995, 18006, 18017, 18028, 18039, 18050, 18061, 18070,
+ 18079, 18093, 18106, 18120, 18133, 18143, 18153, 18162, 18171, 18180, 18193, 18202, 18215, 18224,
+ 18233, 18243, 18253, 18260, 18269, 18278, 18285, 18294, 18303, 18310, 18319, 18328, 18339, 18350,
+ 18361, 18372, 18383, 18394, 18399, 18405, 18411, 18419, 18427, 18435, 18443, 18451, 18459, 18465,
+ 18471, 18483, 18494, 18505, 18516, 18525, 18534, 18546, 18557, 18569, 18580, 18589, 18598, 18608,
+ 18618, 18628, 18638, 18650, 18661, 18673, 18684, 18696, 18707, 18719, 18730, 18742, 18753, 18765,
+ 18776, 18785, 18793, 18801, 18809, 18817, 18825, 18833, 18841, 18849, 18857, 18865, 18873, 18881,
+ 18889, 18897, 18905, 18914, 18922, 18930, 18938, 18946, 18954, 18962, 18970, 18978, 18986, 18994,
+ 19002, 19010, 19018, 19026, 19034, 19043, 19052, 19061, 19070, 19080, 19090, 19100, 19110, 19118,
+ 19126, 19134, 19142, 19154, 19166, 19178, 19190, 19203, 19216, 19228, 19240, 19252, 19264, 19276,
+ 19288, 19301, 19314, 19326, 19338, 19346, 19356, 19366, 19376, 19386, 19395, 19403, 19413, 19423,
+ 19433, 19443, 19452, 19460, 19470, 19480, 19486, 19493, 19502, 19511, 19520, 19529, 19538, 19547,
+ 19556, 19563, 19570, 19578, 19587, 19595, 19603, 19612, 19620, 19628, 19637, 19645, 19653, 19662,
+ 19670, 19678, 19687, 19695, 19703, 19712, 19720, 19727, 19735, 19742, 19749, 19757, 19764, 19771,
+ 19782, 19789, 19800, 19807, 19818, 19825, 19836, 19844, 19853, 19861, 19869, 19878, 19886, 19894,
+ 19903, 19911, 19919, 19928, 19936, 19944, 19953, 19961, 19969, 19978, 19986, 19993, 20001, 20008,
+ 20015, 20023, 20030, 20036, 20042, 20048, 20055, 20068, 20078, 20088, 20098, 20108, 20119, 20129,
+ 20139, 20149, 20159, 20163, 20168, 20176, 20185, 20193, 20201, 20210, 20218, 20226, 20235, 20243,
+ 20251, 20260, 20268, 20276, 20285, 20293, 20301, 20310, 20318, 20325, 20333, 20340, 20347, 20355,
+ 20362, 20370, 20379, 20387, 20395, 20404, 20412, 20420, 20429, 20437, 20445, 20454, 20462, 20470,
+ 20479, 20487, 20495, 20504, 20512, 20519, 20527, 20534, 20541, 20549, 20556, 20569, 20582, 20595,
+ 20608, 20621, 20634, 20647, 20660, 20664, 20673, 20686, 20695, 20708, 20717, 20730, 20739, 20752,
+ 20757, 20765, 20774, 20782, 20790, 20799, 20807, 20815, 20824, 20832, 20840, 20849, 20857, 20865,
+ 20874, 20882, 20890, 20899, 20907, 20914, 20922, 20929, 20936, 20944, 20951, 20960, 20968, 20977,
+ 20985, 20993, 21002, 21010, 21018, 21030, 21039, 21047, 21056, 21064, 21072, 21081, 21089, 21097,
+ 21109, 21118, 21128, 21137, 21145, 21155, 21164, 21172, 21180, 21192, 21199, 21206, 21213, 21220,
+ 21227, 21234, 21245, 21252, 21259, 21266, 21272, 21279, 21286, 21292, 21298, 21305, 21312, 21322,
+ 21332, 21342, 21351, 21357, 21363, 21369, 21375, 21382, 21389, 21395, 21401, 21408, 21415, 21421,
+ 21427, 21434, 21441, 21448, 21455, 21462, 21469, 21476, 21483, 21489, 21495, 21501, 21507, 21513,
+ 21519, 21526, 21532, 21540, 21549, 21557, 21565, 21574, 21582, 21590, 21599, 21607, 21615, 21624,
+ 21632, 21640, 21649, 21657, 21665, 21674, 21682, 21689, 21697, 21704, 21711, 21719, 21726, 21737,
+ 21748, 21759, 21770, 21781, 21792, 21803, 21814, 21825, 21836, 21847, 21858, 21866, 21875, 21883,
+ 21891, 21900, 21908, 21916, 21925, 21933, 21941, 21950, 21958, 21966, 21975, 21983, 21991, 22000,
+ 22008, 22015, 22023, 22030, 22037, 22045, 22052, 22063, 22074, 22085, 22096, 22107, 22118, 22129,
+ 22140, 22151, 22162, 22173, 22184, 22194, 22204, 22214, 22224, 22230, 22236, 22245, 22254, 22263,
+ 22271, 22279, 22287, 22295, 22303, 22311, 22319, 22327, 22335, 22347, 22355, 22367, 22375, 22387,
+ 22395, 22407, 22415, 22427, 22435, 22447, 22455, 22467, 22475, 22487, 22494, 22504, 22514, 22524,
+ 22534, 22538, 22542, 22546, 22554, 22560, 22566, 22572, 22577, 22582, 22590, 22598, 22607, 22616,
+ 22625, 22633, 22642, 22651, 22662, 22673, 22684, 22694, 22704, 22716, 22726, 22738, 22750, 22757,
+ 22766, 22774, 22783, 22791, 22799, 22808, 22816, 22824, 22836, 22845, 22853, 22862, 22870, 22878,
+ 22887, 22895, 22903, 22915, 22924, 22934, 22943, 22951, 22961, 22970, 22978, 22986, 22998, 23005,
+ 23012, 23019, 23026, 23033, 23040, 23051, 23059, 23067, 23075, 23083, 23093, 23103, 23114, 23125,
+ 23137, 23148, 23159, 23170, 23183, 23196, 23209, 23223, 23237, 23251, 23265, 23279, 23293, 23304,
+ 23312, 23324, 23332, 23344, 23352, 23364, 23372, 23384, 23393, 23402, 23412, 23422, 23433, 23443,
+ 23452, 23462, 23471, 23481, 23493, 23502, 23514, 23526, 23539, 23552, 23565, 23578, 23591, 23604,
+ 23614, 23621, 23629, 23638, 23646, 23656, 23663, 23672, 23681, 23690, 23701, 23712, 23725, 23736,
+ 23749, 23759, 23768, 23777, 23786, 23795, 23805, 23814, 23823, 23832, 23841, 23851, 23862, 23873,
+ 23882, 23891, 23899, 23907, 23915, 23923, 23931, 23942, 23953, 23958, 23964, 23973, 23982, 23991,
+ 24001, 24011, 24021, 24031, 24041, 24050, 24060, 24069, 24081, 24093, 24105, 24116, 24127, 24138,
+ 24146, 24157, 24168, 24179, 24190, 24201, 24212, 24223, 24234, 24256, 24262, 24268, 24274, 24280,
+ 24287, 24296, 24305, 24314, 24323, 24334, 24345, 24356, 24367, 24376, 24388, 24400, 24412, 24424,
+ 24431, 24437, 24444, 24457, 24462, 24469, 24480, 24497, 24508, 24514, 24523, 24532, 24541, 24550,
+ 24559, 24568, 24576, 24584, 24593, 24602, 24611, 24620, 24629, 24638, 24647, 24656, 24665, 24673,
+ 24681, 24687, 24692, 24701, 24709, 24718, 24726, 24734, 24743, 24751, 24759, 24771, 24780, 24788,
+ 24797, 24805, 24813, 24822, 24830, 24838, 24850, 24859, 24869, 24878, 24886, 24896, 24905, 24913,
+ 24921, 24933, 24940, 24947, 24954, 24961, 24968, 24975, 24986, 24994, 25002, 25010, 0
+ };
+
+ const char *Strs =
+ "PHI\000INLINEASM\000DBG_LABEL\000EH_LABEL\000GC_LABEL\000KILL\000EXTRAC"
+ "T_SUBREG\000INSERT_SUBREG\000IMPLICIT_DEF\000SUBREG_TO_REG\000COPY_TO_R"
+ "EGCLASS\000DBG_VALUE\000ABS_F\000ABS_Fp32\000ABS_Fp64\000ABS_Fp80\000AD"
+ "C16i16\000ADC16mi\000ADC16mi8\000ADC16mr\000ADC16ri\000ADC16ri8\000ADC1"
+ "6rm\000ADC16rr\000ADC16rr_REV\000ADC32i32\000ADC32mi\000ADC32mi8\000ADC"
+ "32mr\000ADC32ri\000ADC32ri8\000ADC32rm\000ADC32rr\000ADC32rr_REV\000ADC"
+ "64i32\000ADC64mi32\000ADC64mi8\000ADC64mr\000ADC64ri32\000ADC64ri8\000A"
+ "DC64rm\000ADC64rr\000ADC64rr_REV\000ADC8i8\000ADC8mi\000ADC8mr\000ADC8r"
+ "i\000ADC8rm\000ADC8rr\000ADC8rr_REV\000ADD16i16\000ADD16mi\000ADD16mi8\000"
+ "ADD16mr\000ADD16mrmrr\000ADD16ri\000ADD16ri8\000ADD16rm\000ADD16rr\000A"
+ "DD32i32\000ADD32mi\000ADD32mi8\000ADD32mr\000ADD32mrmrr\000ADD32ri\000A"
+ "DD32ri8\000ADD32rm\000ADD32rr\000ADD64i32\000ADD64mi32\000ADD64mi8\000A"
+ "DD64mr\000ADD64mrmrr\000ADD64ri32\000ADD64ri8\000ADD64rm\000ADD64rr\000"
+ "ADD8i8\000ADD8mi\000ADD8mr\000ADD8mrmrr\000ADD8ri\000ADD8rm\000ADD8rr\000"
+ "ADDPDrm\000ADDPDrr\000ADDPSrm\000ADDPSrr\000ADDSDrm\000ADDSDrm_Int\000A"
+ "DDSDrr\000ADDSDrr_Int\000ADDSSrm\000ADDSSrm_Int\000ADDSSrr\000ADDSSrr_I"
+ "nt\000ADDSUBPDrm\000ADDSUBPDrr\000ADDSUBPSrm\000ADDSUBPSrr\000ADD_F32m\000"
+ "ADD_F64m\000ADD_FI16m\000ADD_FI32m\000ADD_FPrST0\000ADD_FST0r\000ADD_Fp"
+ "32\000ADD_Fp32m\000ADD_Fp64\000ADD_Fp64m\000ADD_Fp64m32\000ADD_Fp80\000"
+ "ADD_Fp80m32\000ADD_Fp80m64\000ADD_FpI16m32\000ADD_FpI16m64\000ADD_FpI16"
+ "m80\000ADD_FpI32m32\000ADD_FpI32m64\000ADD_FpI32m80\000ADD_FrST0\000ADJ"
+ "CALLSTACKDOWN32\000ADJCALLSTACKDOWN64\000ADJCALLSTACKUP32\000ADJCALLSTA"
+ "CKUP64\000AND16i16\000AND16mi\000AND16mi8\000AND16mr\000AND16ri\000AND1"
+ "6ri8\000AND16rm\000AND16rr\000AND16rr_REV\000AND32i32\000AND32mi\000AND"
+ "32mi8\000AND32mr\000AND32ri\000AND32ri8\000AND32rm\000AND32rr\000AND32r"
+ "r_REV\000AND64i32\000AND64mi32\000AND64mi8\000AND64mr\000AND64ri32\000A"
+ "ND64ri8\000AND64rm\000AND64rr\000AND64rr_REV\000AND8i8\000AND8mi\000AND"
+ "8mr\000AND8ri\000AND8rm\000AND8rr\000AND8rr_REV\000ANDNPDrm\000ANDNPDrr"
+ "\000ANDNPSrm\000ANDNPSrr\000ANDPDrm\000ANDPDrr\000ANDPSrm\000ANDPSrr\000"
+ "ATOMADD6432\000ATOMAND16\000ATOMAND32\000ATOMAND64\000ATOMAND6432\000AT"
+ "OMAND8\000ATOMMAX16\000ATOMMAX32\000ATOMMAX64\000ATOMMIN16\000ATOMMIN32"
+ "\000ATOMMIN64\000ATOMNAND16\000ATOMNAND32\000ATOMNAND64\000ATOMNAND6432"
+ "\000ATOMNAND8\000ATOMOR16\000ATOMOR32\000ATOMOR64\000ATOMOR6432\000ATOM"
+ "OR8\000ATOMSUB6432\000ATOMSWAP6432\000ATOMUMAX16\000ATOMUMAX32\000ATOMU"
+ "MAX64\000ATOMUMIN16\000ATOMUMIN32\000ATOMUMIN64\000ATOMXOR16\000ATOMXOR"
+ "32\000ATOMXOR64\000ATOMXOR6432\000ATOMXOR8\000BLENDPDrmi\000BLENDPDrri\000"
+ "BLENDPSrmi\000BLENDPSrri\000BLENDVPDrm0\000BLENDVPDrr0\000BLENDVPSrm0\000"
+ "BLENDVPSrr0\000BSF16rm\000BSF16rr\000BSF32rm\000BSF32rr\000BSF64rm\000B"
+ "SF64rr\000BSR16rm\000BSR16rr\000BSR32rm\000BSR32rr\000BSR64rm\000BSR64r"
+ "r\000BSWAP32r\000BSWAP64r\000BT16mi8\000BT16mr\000BT16ri8\000BT16rr\000"
+ "BT32mi8\000BT32mr\000BT32ri8\000BT32rr\000BT64mi8\000BT64mr\000BT64ri8\000"
+ "BT64rr\000BTC16mi8\000BTC16mr\000BTC16ri8\000BTC16rr\000BTC32mi8\000BTC"
+ "32mr\000BTC32ri8\000BTC32rr\000BTC64mi8\000BTC64mr\000BTC64ri8\000BTC64"
+ "rr\000BTR16mi8\000BTR16mr\000BTR16ri8\000BTR16rr\000BTR32mi8\000BTR32mr"
+ "\000BTR32ri8\000BTR32rr\000BTR64mi8\000BTR64mr\000BTR64ri8\000BTR64rr\000"
+ "BTS16mi8\000BTS16mr\000BTS16ri8\000BTS16rr\000BTS32mi8\000BTS32mr\000BT"
+ "S32ri8\000BTS32rr\000BTS64mi8\000BTS64mr\000BTS64ri8\000BTS64rr\000CALL"
+ "32m\000CALL32r\000CALL64m\000CALL64pcrel32\000CALL64r\000CALLpcrel32\000"
+ "CBW\000CDQ\000CDQE\000CHS_F\000CHS_Fp32\000CHS_Fp64\000CHS_Fp80\000CLC\000"
+ "CLD\000CLFLUSH\000CLI\000CLTS\000CMC\000CMOVA16rm\000CMOVA16rr\000CMOVA"
+ "32rm\000CMOVA32rr\000CMOVA64rm\000CMOVA64rr\000CMOVAE16rm\000CMOVAE16rr"
+ "\000CMOVAE32rm\000CMOVAE32rr\000CMOVAE64rm\000CMOVAE64rr\000CMOVB16rm\000"
+ "CMOVB16rr\000CMOVB32rm\000CMOVB32rr\000CMOVB64rm\000CMOVB64rr\000CMOVBE"
+ "16rm\000CMOVBE16rr\000CMOVBE32rm\000CMOVBE32rr\000CMOVBE64rm\000CMOVBE6"
+ "4rr\000CMOVBE_F\000CMOVBE_Fp32\000CMOVBE_Fp64\000CMOVBE_Fp80\000CMOVB_F"
+ "\000CMOVB_Fp32\000CMOVB_Fp64\000CMOVB_Fp80\000CMOVE16rm\000CMOVE16rr\000"
+ "CMOVE32rm\000CMOVE32rr\000CMOVE64rm\000CMOVE64rr\000CMOVE_F\000CMOVE_Fp"
+ "32\000CMOVE_Fp64\000CMOVE_Fp80\000CMOVG16rm\000CMOVG16rr\000CMOVG32rm\000"
+ "CMOVG32rr\000CMOVG64rm\000CMOVG64rr\000CMOVGE16rm\000CMOVGE16rr\000CMOV"
+ "GE32rm\000CMOVGE32rr\000CMOVGE64rm\000CMOVGE64rr\000CMOVL16rm\000CMOVL1"
+ "6rr\000CMOVL32rm\000CMOVL32rr\000CMOVL64rm\000CMOVL64rr\000CMOVLE16rm\000"
+ "CMOVLE16rr\000CMOVLE32rm\000CMOVLE32rr\000CMOVLE64rm\000CMOVLE64rr\000C"
+ "MOVNBE_F\000CMOVNBE_Fp32\000CMOVNBE_Fp64\000CMOVNBE_Fp80\000CMOVNB_F\000"
+ "CMOVNB_Fp32\000CMOVNB_Fp64\000CMOVNB_Fp80\000CMOVNE16rm\000CMOVNE16rr\000"
+ "CMOVNE32rm\000CMOVNE32rr\000CMOVNE64rm\000CMOVNE64rr\000CMOVNE_F\000CMO"
+ "VNE_Fp32\000CMOVNE_Fp64\000CMOVNE_Fp80\000CMOVNO16rm\000CMOVNO16rr\000C"
+ "MOVNO32rm\000CMOVNO32rr\000CMOVNO64rm\000CMOVNO64rr\000CMOVNP16rm\000CM"
+ "OVNP16rr\000CMOVNP32rm\000CMOVNP32rr\000CMOVNP64rm\000CMOVNP64rr\000CMO"
+ "VNP_F\000CMOVNP_Fp32\000CMOVNP_Fp64\000CMOVNP_Fp80\000CMOVNS16rm\000CMO"
+ "VNS16rr\000CMOVNS32rm\000CMOVNS32rr\000CMOVNS64rm\000CMOVNS64rr\000CMOV"
+ "O16rm\000CMOVO16rr\000CMOVO32rm\000CMOVO32rr\000CMOVO64rm\000CMOVO64rr\000"
+ "CMOVP16rm\000CMOVP16rr\000CMOVP32rm\000CMOVP32rr\000CMOVP64rm\000CMOVP6"
+ "4rr\000CMOVP_F\000CMOVP_Fp32\000CMOVP_Fp64\000CMOVP_Fp80\000CMOVS16rm\000"
+ "CMOVS16rr\000CMOVS32rm\000CMOVS32rr\000CMOVS64rm\000CMOVS64rr\000CMOV_F"
+ "R32\000CMOV_FR64\000CMOV_GR8\000CMOV_V1I64\000CMOV_V2F64\000CMOV_V2I64\000"
+ "CMOV_V4F32\000CMP16i16\000CMP16mi\000CMP16mi8\000CMP16mr\000CMP16mrmrr\000"
+ "CMP16ri\000CMP16ri8\000CMP16rm\000CMP16rr\000CMP32i32\000CMP32mi\000CMP"
+ "32mi8\000CMP32mr\000CMP32mrmrr\000CMP32ri\000CMP32ri8\000CMP32rm\000CMP"
+ "32rr\000CMP64i32\000CMP64mi32\000CMP64mi8\000CMP64mr\000CMP64mrmrr\000C"
+ "MP64ri32\000CMP64ri8\000CMP64rm\000CMP64rr\000CMP8i8\000CMP8mi\000CMP8m"
+ "r\000CMP8mrmrr\000CMP8ri\000CMP8rm\000CMP8rr\000CMPPDrmi\000CMPPDrri\000"
+ "CMPPSrmi\000CMPPSrri\000CMPS16\000CMPS32\000CMPS64\000CMPS8\000CMPSDrm\000"
+ "CMPSDrr\000CMPSSrm\000CMPSSrr\000CMPXCHG16B\000CMPXCHG16rm\000CMPXCHG16"
+ "rr\000CMPXCHG32rm\000CMPXCHG32rr\000CMPXCHG64rm\000CMPXCHG64rr\000CMPXC"
+ "HG8B\000CMPXCHG8rm\000CMPXCHG8rr\000COMISDrm\000COMISDrr\000COMISSrm\000"
+ "COMISSrr\000COMP_FST0r\000COM_FIPr\000COM_FIr\000COM_FST0r\000COS_F\000"
+ "COS_Fp32\000COS_Fp64\000COS_Fp80\000CPUID\000CQO\000CRC32m16\000CRC32m3"
+ "2\000CRC32m8\000CRC32r16\000CRC32r32\000CRC32r8\000CRC64m64\000CRC64r64"
+ "\000CS_PREFIX\000CVTDQ2PDrm\000CVTDQ2PDrr\000CVTDQ2PSrm\000CVTDQ2PSrr\000"
+ "CVTPD2DQrm\000CVTPD2DQrr\000CVTPD2PSrm\000CVTPD2PSrr\000CVTPS2DQrm\000C"
+ "VTPS2DQrr\000CVTPS2PDrm\000CVTPS2PDrr\000CVTSD2SI64rm\000CVTSD2SI64rr\000"
+ "CVTSD2SSrm\000CVTSD2SSrr\000CVTSI2SD64rm\000CVTSI2SD64rr\000CVTSI2SDrm\000"
+ "CVTSI2SDrr\000CVTSI2SS64rm\000CVTSI2SS64rr\000CVTSI2SSrm\000CVTSI2SSrr\000"
+ "CVTSS2SDrm\000CVTSS2SDrr\000CVTSS2SI64rm\000CVTSS2SI64rr\000CVTSS2SIrm\000"
+ "CVTSS2SIrr\000CVTTPS2DQrm\000CVTTPS2DQrr\000CVTTSD2SI64rm\000CVTTSD2SI6"
+ "4rr\000CVTTSD2SIrm\000CVTTSD2SIrr\000CVTTSS2SI64rm\000CVTTSS2SI64rr\000"
+ "CVTTSS2SIrm\000CVTTSS2SIrr\000CWD\000CWDE\000DEC16m\000DEC16r\000DEC32m"
+ "\000DEC32r\000DEC64_16m\000DEC64_16r\000DEC64_32m\000DEC64_32r\000DEC64"
+ "m\000DEC64r\000DEC8m\000DEC8r\000DIV16m\000DIV16r\000DIV32m\000DIV32r\000"
+ "DIV64m\000DIV64r\000DIV8m\000DIV8r\000DIVPDrm\000DIVPDrr\000DIVPSrm\000"
+ "DIVPSrr\000DIVR_F32m\000DIVR_F64m\000DIVR_FI16m\000DIVR_FI32m\000DIVR_F"
+ "PrST0\000DIVR_FST0r\000DIVR_Fp32m\000DIVR_Fp64m\000DIVR_Fp64m32\000DIVR"
+ "_Fp80m32\000DIVR_Fp80m64\000DIVR_FpI16m32\000DIVR_FpI16m64\000DIVR_FpI1"
+ "6m80\000DIVR_FpI32m32\000DIVR_FpI32m64\000DIVR_FpI32m80\000DIVR_FrST0\000"
+ "DIVSDrm\000DIVSDrm_Int\000DIVSDrr\000DIVSDrr_Int\000DIVSSrm\000DIVSSrm_"
+ "Int\000DIVSSrr\000DIVSSrr_Int\000DIV_F32m\000DIV_F64m\000DIV_FI16m\000D"
+ "IV_FI32m\000DIV_FPrST0\000DIV_FST0r\000DIV_Fp32\000DIV_Fp32m\000DIV_Fp6"
+ "4\000DIV_Fp64m\000DIV_Fp64m32\000DIV_Fp80\000DIV_Fp80m32\000DIV_Fp80m64"
+ "\000DIV_FpI16m32\000DIV_FpI16m64\000DIV_FpI16m80\000DIV_FpI32m32\000DIV"
+ "_FpI32m64\000DIV_FpI32m80\000DIV_FrST0\000DPPDrmi\000DPPDrri\000DPPSrmi"
+ "\000DPPSrri\000DS_PREFIX\000EH_RETURN\000EH_RETURN64\000ENTER\000ES_PRE"
+ "FIX\000EXTRACTPSmr\000EXTRACTPSrr\000F2XM1\000FARCALL16i\000FARCALL16m\000"
+ "FARCALL32i\000FARCALL32m\000FARCALL64\000FARJMP16i\000FARJMP16m\000FARJ"
+ "MP32i\000FARJMP32m\000FARJMP64\000FBLDm\000FBSTPm\000FCOM32m\000FCOM64m"
+ "\000FCOMP32m\000FCOMP64m\000FCOMPP\000FDECSTP\000FFREE\000FICOM16m\000F"
+ "ICOM32m\000FICOMP16m\000FICOMP32m\000FINCSTP\000FLDCW16m\000FLDENVm\000"
+ "FLDL2E\000FLDL2T\000FLDLG2\000FLDLN2\000FLDPI\000FNCLEX\000FNINIT\000FN"
+ "OP\000FNSTCW16m\000FNSTSW8r\000FNSTSWm\000FP32_TO_INT16_IN_MEM\000FP32_"
+ "TO_INT32_IN_MEM\000FP32_TO_INT64_IN_MEM\000FP64_TO_INT16_IN_MEM\000FP64"
+ "_TO_INT32_IN_MEM\000FP64_TO_INT64_IN_MEM\000FP80_TO_INT16_IN_MEM\000FP8"
+ "0_TO_INT32_IN_MEM\000FP80_TO_INT64_IN_MEM\000FPATAN\000FPREM\000FPREM1\000"
+ "FPTAN\000FP_REG_KILL\000FRNDINT\000FRSTORm\000FSAVEm\000FSCALE\000FSINC"
+ "OS\000FSTENVm\000FS_MOV32rm\000FS_PREFIX\000FXAM\000FXRSTOR\000FXSAVE\000"
+ "FXTRACT\000FYL2X\000FYL2XP1\000FpGET_ST0_32\000FpGET_ST0_64\000FpGET_ST"
+ "0_80\000FpGET_ST1_32\000FpGET_ST1_64\000FpGET_ST1_80\000FpSET_ST0_32\000"
+ "FpSET_ST0_64\000FpSET_ST0_80\000FpSET_ST1_32\000FpSET_ST1_64\000FpSET_S"
+ "T1_80\000FsANDNPDrm\000FsANDNPDrr\000FsANDNPSrm\000FsANDNPSrr\000FsANDP"
+ "Drm\000FsANDPDrr\000FsANDPSrm\000FsANDPSrr\000FsFLD0SD\000FsFLD0SS\000F"
+ "sMOVAPDrm\000FsMOVAPDrr\000FsMOVAPSrm\000FsMOVAPSrr\000FsORPDrm\000FsOR"
+ "PDrr\000FsORPSrm\000FsORPSrr\000FsXORPDrm\000FsXORPDrr\000FsXORPSrm\000"
+ "FsXORPSrr\000GS_MOV32rm\000GS_PREFIX\000HADDPDrm\000HADDPDrr\000HADDPSr"
+ "m\000HADDPSrr\000HLT\000HSUBPDrm\000HSUBPDrr\000HSUBPSrm\000HSUBPSrr\000"
+ "IDIV16m\000IDIV16r\000IDIV32m\000IDIV32r\000IDIV64m\000IDIV64r\000IDIV8"
+ "m\000IDIV8r\000ILD_F16m\000ILD_F32m\000ILD_F64m\000ILD_Fp16m32\000ILD_F"
+ "p16m64\000ILD_Fp16m80\000ILD_Fp32m32\000ILD_Fp32m64\000ILD_Fp32m80\000I"
+ "LD_Fp64m32\000ILD_Fp64m64\000ILD_Fp64m80\000IMUL16m\000IMUL16r\000IMUL1"
+ "6rm\000IMUL16rmi\000IMUL16rmi8\000IMUL16rr\000IMUL16rri\000IMUL16rri8\000"
+ "IMUL32m\000IMUL32r\000IMUL32rm\000IMUL32rmi\000IMUL32rmi8\000IMUL32rr\000"
+ "IMUL32rri\000IMUL32rri8\000IMUL64m\000IMUL64r\000IMUL64rm\000IMUL64rmi3"
+ "2\000IMUL64rmi8\000IMUL64rr\000IMUL64rri32\000IMUL64rri8\000IMUL8m\000I"
+ "MUL8r\000IN16\000IN16ri\000IN16rr\000IN32\000IN32ri\000IN32rr\000IN8\000"
+ "IN8ri\000IN8rr\000INC16m\000INC16r\000INC32m\000INC32r\000INC64_16m\000"
+ "INC64_16r\000INC64_32m\000INC64_32r\000INC64m\000INC64r\000INC8m\000INC"
+ "8r\000INSERTPSrm\000INSERTPSrr\000INT\000INT3\000INVD\000INVEPT\000INVL"
+ "PG\000INVVPID\000IRET16\000IRET32\000IRET64\000ISTT_FP16m\000ISTT_FP32m"
+ "\000ISTT_FP64m\000ISTT_Fp16m32\000ISTT_Fp16m64\000ISTT_Fp16m80\000ISTT_"
+ "Fp32m32\000ISTT_Fp32m64\000ISTT_Fp32m80\000ISTT_Fp64m32\000ISTT_Fp64m64"
+ "\000ISTT_Fp64m80\000IST_F16m\000IST_F32m\000IST_FP16m\000IST_FP32m\000I"
+ "ST_FP64m\000IST_Fp16m32\000IST_Fp16m64\000IST_Fp16m80\000IST_Fp32m32\000"
+ "IST_Fp32m64\000IST_Fp32m80\000IST_Fp64m32\000IST_Fp64m64\000IST_Fp64m80"
+ "\000Int_CMPSDrm\000Int_CMPSDrr\000Int_CMPSSrm\000Int_CMPSSrr\000Int_COM"
+ "ISDrm\000Int_COMISDrr\000Int_COMISSrm\000Int_COMISSrr\000Int_CVTDQ2PDrm"
+ "\000Int_CVTDQ2PDrr\000Int_CVTDQ2PSrm\000Int_CVTDQ2PSrr\000Int_CVTPD2DQr"
+ "m\000Int_CVTPD2DQrr\000Int_CVTPD2PIrm\000Int_CVTPD2PIrr\000Int_CVTPD2PS"
+ "rm\000Int_CVTPD2PSrr\000Int_CVTPI2PDrm\000Int_CVTPI2PDrr\000Int_CVTPI2P"
+ "Srm\000Int_CVTPI2PSrr\000Int_CVTPS2DQrm\000Int_CVTPS2DQrr\000Int_CVTPS2"
+ "PDrm\000Int_CVTPS2PDrr\000Int_CVTPS2PIrm\000Int_CVTPS2PIrr\000Int_CVTSD"
+ "2SI64rm\000Int_CVTSD2SI64rr\000Int_CVTSD2SIrm\000Int_CVTSD2SIrr\000Int_"
+ "CVTSD2SSrm\000Int_CVTSD2SSrr\000Int_CVTSI2SD64rm\000Int_CVTSI2SD64rr\000"
+ "Int_CVTSI2SDrm\000Int_CVTSI2SDrr\000Int_CVTSI2SS64rm\000Int_CVTSI2SS64r"
+ "r\000Int_CVTSI2SSrm\000Int_CVTSI2SSrr\000Int_CVTSS2SDrm\000Int_CVTSS2SD"
+ "rr\000Int_CVTSS2SI64rm\000Int_CVTSS2SI64rr\000Int_CVTSS2SIrm\000Int_CVT"
+ "SS2SIrr\000Int_CVTTPD2DQrm\000Int_CVTTPD2DQrr\000Int_CVTTPD2PIrm\000Int"
+ "_CVTTPD2PIrr\000Int_CVTTPS2DQrm\000Int_CVTTPS2DQrr\000Int_CVTTPS2PIrm\000"
+ "Int_CVTTPS2PIrr\000Int_CVTTSD2SI64rm\000Int_CVTTSD2SI64rr\000Int_CVTTSD"
+ "2SIrm\000Int_CVTTSD2SIrr\000Int_CVTTSS2SI64rm\000Int_CVTTSS2SI64rr\000I"
+ "nt_CVTTSS2SIrm\000Int_CVTTSS2SIrr\000Int_UCOMISDrm\000Int_UCOMISDrr\000"
+ "Int_UCOMISSrm\000Int_UCOMISSrr\000JAE_1\000JAE_4\000JA_1\000JA_4\000JBE"
+ "_1\000JBE_4\000JB_1\000JB_4\000JCXZ8\000JE_1\000JE_4\000JGE_1\000JGE_4\000"
+ "JG_1\000JG_4\000JLE_1\000JLE_4\000JL_1\000JL_4\000JMP32m\000JMP32r\000J"
+ "MP64m\000JMP64pcrel32\000JMP64r\000JMP_1\000JMP_4\000JNE_1\000JNE_4\000"
+ "JNO_1\000JNO_4\000JNP_1\000JNP_4\000JNS_1\000JNS_4\000JO_1\000JO_4\000J"
+ "P_1\000JP_4\000JS_1\000JS_4\000LAHF\000LAR16rm\000LAR16rr\000LAR32rm\000"
+ "LAR32rr\000LAR64rm\000LAR64rr\000LCMPXCHG16\000LCMPXCHG32\000LCMPXCHG64"
+ "\000LCMPXCHG8\000LCMPXCHG8B\000LDDQUrm\000LDMXCSR\000LDS16rm\000LDS32rm"
+ "\000LD_F0\000LD_F1\000LD_F32m\000LD_F64m\000LD_F80m\000LD_Fp032\000LD_F"
+ "p064\000LD_Fp080\000LD_Fp132\000LD_Fp164\000LD_Fp180\000LD_Fp32m\000LD_"
+ "Fp32m64\000LD_Fp32m80\000LD_Fp64m\000LD_Fp64m80\000LD_Fp80m\000LD_Frr\000"
+ "LEA16r\000LEA32r\000LEA64_32r\000LEA64r\000LEAVE\000LEAVE64\000LES16rm\000"
+ "LES32rm\000LFENCE\000LFS16rm\000LFS32rm\000LFS64rm\000LGDTm\000LGS16rm\000"
+ "LGS32rm\000LGS64rm\000LIDTm\000LLDT16m\000LLDT16r\000LMSW16m\000LMSW16r"
+ "\000LOCK_ADD16mi\000LOCK_ADD16mi8\000LOCK_ADD16mr\000LOCK_ADD32mi\000LO"
+ "CK_ADD32mi8\000LOCK_ADD32mr\000LOCK_ADD64mi32\000LOCK_ADD64mi8\000LOCK_"
+ "ADD64mr\000LOCK_ADD8mi\000LOCK_ADD8mr\000LOCK_DEC16m\000LOCK_DEC32m\000"
+ "LOCK_DEC64m\000LOCK_DEC8m\000LOCK_INC16m\000LOCK_INC32m\000LOCK_INC64m\000"
+ "LOCK_INC8m\000LOCK_PREFIX\000LOCK_SUB16mi\000LOCK_SUB16mi8\000LOCK_SUB1"
+ "6mr\000LOCK_SUB32mi\000LOCK_SUB32mi8\000LOCK_SUB32mr\000LOCK_SUB64mi32\000"
+ "LOCK_SUB64mi8\000LOCK_SUB64mr\000LOCK_SUB8mi\000LOCK_SUB8mr\000LODSB\000"
+ "LODSD\000LODSQ\000LODSW\000LOOP\000LOOPE\000LOOPNE\000LRET\000LRETI\000"
+ "LSL16rm\000LSL16rr\000LSL32rm\000LSL32rr\000LSL64rm\000LSL64rr\000LSS16"
+ "rm\000LSS32rm\000LSS64rm\000LTRm\000LTRr\000LXADD16\000LXADD32\000LXADD"
+ "64\000LXADD8\000MASKMOVDQU\000MASKMOVDQU64\000MAXPDrm\000MAXPDrm_Int\000"
+ "MAXPDrr\000MAXPDrr_Int\000MAXPSrm\000MAXPSrm_Int\000MAXPSrr\000MAXPSrr_"
+ "Int\000MAXSDrm\000MAXSDrm_Int\000MAXSDrr\000MAXSDrr_Int\000MAXSSrm\000M"
+ "AXSSrm_Int\000MAXSSrr\000MAXSSrr_Int\000MFENCE\000MINPDrm\000MINPDrm_In"
+ "t\000MINPDrr\000MINPDrr_Int\000MINPSrm\000MINPSrm_Int\000MINPSrr\000MIN"
+ "PSrr_Int\000MINSDrm\000MINSDrm_Int\000MINSDrr\000MINSDrr_Int\000MINSSrm"
+ "\000MINSSrm_Int\000MINSSrr\000MINSSrr_Int\000MMX_CVTPD2PIrm\000MMX_CVTP"
+ "D2PIrr\000MMX_CVTPI2PDrm\000MMX_CVTPI2PDrr\000MMX_CVTPI2PSrm\000MMX_CVT"
+ "PI2PSrr\000MMX_CVTPS2PIrm\000MMX_CVTPS2PIrr\000MMX_CVTTPD2PIrm\000MMX_C"
+ "VTTPD2PIrr\000MMX_CVTTPS2PIrm\000MMX_CVTTPS2PIrr\000MMX_EMMS\000MMX_FEM"
+ "MS\000MMX_MASKMOVQ\000MMX_MASKMOVQ64\000MMX_MOVD64from64rr\000MMX_MOVD6"
+ "4grr\000MMX_MOVD64mr\000MMX_MOVD64rm\000MMX_MOVD64rr\000MMX_MOVD64rrv16"
+ "4\000MMX_MOVD64to64rr\000MMX_MOVDQ2Qrr\000MMX_MOVNTQmr\000MMX_MOVQ2DQrr"
+ "\000MMX_MOVQ2FR64rr\000MMX_MOVQ64gmr\000MMX_MOVQ64mr\000MMX_MOVQ64rm\000"
+ "MMX_MOVQ64rr\000MMX_MOVZDI2PDIrm\000MMX_MOVZDI2PDIrr\000MMX_PACKSSDWrm\000"
+ "MMX_PACKSSDWrr\000MMX_PACKSSWBrm\000MMX_PACKSSWBrr\000MMX_PACKUSWBrm\000"
+ "MMX_PACKUSWBrr\000MMX_PADDBrm\000MMX_PADDBrr\000MMX_PADDDrm\000MMX_PADD"
+ "Drr\000MMX_PADDQrm\000MMX_PADDQrr\000MMX_PADDSBrm\000MMX_PADDSBrr\000MM"
+ "X_PADDSWrm\000MMX_PADDSWrr\000MMX_PADDUSBrm\000MMX_PADDUSBrr\000MMX_PAD"
+ "DUSWrm\000MMX_PADDUSWrr\000MMX_PADDWrm\000MMX_PADDWrr\000MMX_PANDNrm\000"
+ "MMX_PANDNrr\000MMX_PANDrm\000MMX_PANDrr\000MMX_PAVGBrm\000MMX_PAVGBrr\000"
+ "MMX_PAVGWrm\000MMX_PAVGWrr\000MMX_PCMPEQBrm\000MMX_PCMPEQBrr\000MMX_PCM"
+ "PEQDrm\000MMX_PCMPEQDrr\000MMX_PCMPEQWrm\000MMX_PCMPEQWrr\000MMX_PCMPGT"
+ "Brm\000MMX_PCMPGTBrr\000MMX_PCMPGTDrm\000MMX_PCMPGTDrr\000MMX_PCMPGTWrm"
+ "\000MMX_PCMPGTWrr\000MMX_PEXTRWri\000MMX_PINSRWrmi\000MMX_PINSRWrri\000"
+ "MMX_PMADDWDrm\000MMX_PMADDWDrr\000MMX_PMAXSWrm\000MMX_PMAXSWrr\000MMX_P"
+ "MAXUBrm\000MMX_PMAXUBrr\000MMX_PMINSWrm\000MMX_PMINSWrr\000MMX_PMINUBrm"
+ "\000MMX_PMINUBrr\000MMX_PMOVMSKBrr\000MMX_PMULHUWrm\000MMX_PMULHUWrr\000"
+ "MMX_PMULHWrm\000MMX_PMULHWrr\000MMX_PMULLWrm\000MMX_PMULLWrr\000MMX_PMU"
+ "LUDQrm\000MMX_PMULUDQrr\000MMX_PORrm\000MMX_PORrr\000MMX_PSADBWrm\000MM"
+ "X_PSADBWrr\000MMX_PSHUFWmi\000MMX_PSHUFWri\000MMX_PSLLDri\000MMX_PSLLDr"
+ "m\000MMX_PSLLDrr\000MMX_PSLLQri\000MMX_PSLLQrm\000MMX_PSLLQrr\000MMX_PS"
+ "LLWri\000MMX_PSLLWrm\000MMX_PSLLWrr\000MMX_PSRADri\000MMX_PSRADrm\000MM"
+ "X_PSRADrr\000MMX_PSRAWri\000MMX_PSRAWrm\000MMX_PSRAWrr\000MMX_PSRLDri\000"
+ "MMX_PSRLDrm\000MMX_PSRLDrr\000MMX_PSRLQri\000MMX_PSRLQrm\000MMX_PSRLQrr"
+ "\000MMX_PSRLWri\000MMX_PSRLWrm\000MMX_PSRLWrr\000MMX_PSUBBrm\000MMX_PSU"
+ "BBrr\000MMX_PSUBDrm\000MMX_PSUBDrr\000MMX_PSUBQrm\000MMX_PSUBQrr\000MMX"
+ "_PSUBSBrm\000MMX_PSUBSBrr\000MMX_PSUBSWrm\000MMX_PSUBSWrr\000MMX_PSUBUS"
+ "Brm\000MMX_PSUBUSBrr\000MMX_PSUBUSWrm\000MMX_PSUBUSWrr\000MMX_PSUBWrm\000"
+ "MMX_PSUBWrr\000MMX_PUNPCKHBWrm\000MMX_PUNPCKHBWrr\000MMX_PUNPCKHDQrm\000"
+ "MMX_PUNPCKHDQrr\000MMX_PUNPCKHWDrm\000MMX_PUNPCKHWDrr\000MMX_PUNPCKLBWr"
+ "m\000MMX_PUNPCKLBWrr\000MMX_PUNPCKLDQrm\000MMX_PUNPCKLDQrr\000MMX_PUNPC"
+ "KLWDrm\000MMX_PUNPCKLWDrr\000MMX_PXORrm\000MMX_PXORrr\000MMX_V_SET0\000"
+ "MMX_V_SETALLONES\000MONITOR\000MOV16ao16\000MOV16mi\000MOV16mr\000MOV16"
+ "ms\000MOV16o16a\000MOV16r0\000MOV16ri\000MOV16rm\000MOV16rr\000MOV16rr_"
+ "REV\000MOV16rs\000MOV16sm\000MOV16sr\000MOV32ao32\000MOV32cr\000MOV32dr"
+ "\000MOV32mi\000MOV32mr\000MOV32o32a\000MOV32r0\000MOV32rc\000MOV32rd\000"
+ "MOV32ri\000MOV32rm\000MOV32rr\000MOV32rr_REV\000MOV64FSrm\000MOV64GSrm\000"
+ "MOV64ao64\000MOV64ao8\000MOV64cr\000MOV64dr\000MOV64mi32\000MOV64mr\000"
+ "MOV64ms\000MOV64o64a\000MOV64o8a\000MOV64r0\000MOV64rc\000MOV64rd\000MO"
+ "V64ri\000MOV64ri32\000MOV64ri64i32\000MOV64rm\000MOV64rr\000MOV64rr_REV"
+ "\000MOV64rs\000MOV64sm\000MOV64sr\000MOV64toPQIrr\000MOV64toSDrm\000MOV"
+ "64toSDrr\000MOV8ao8\000MOV8mi\000MOV8mr\000MOV8mr_NOREX\000MOV8o8a\000M"
+ "OV8r0\000MOV8ri\000MOV8rm\000MOV8rm_NOREX\000MOV8rr\000MOV8rr_NOREX\000"
+ "MOV8rr_REV\000MOVAPDmr\000MOVAPDrm\000MOVAPDrr\000MOVAPSmr\000MOVAPSrm\000"
+ "MOVAPSrr\000MOVDDUPrm\000MOVDDUPrr\000MOVDI2PDIrm\000MOVDI2PDIrr\000MOV"
+ "DI2SSrm\000MOVDI2SSrr\000MOVDQAmr\000MOVDQArm\000MOVDQArr\000MOVDQUmr\000"
+ "MOVDQUmr_Int\000MOVDQUrm\000MOVDQUrm_Int\000MOVHLPSrr\000MOVHPDmr\000MO"
+ "VHPDrm\000MOVHPSmr\000MOVHPSrm\000MOVLHPSrr\000MOVLPDmr\000MOVLPDrm\000"
+ "MOVLPDrr\000MOVLPSmr\000MOVLPSrm\000MOVLPSrr\000MOVLQ128mr\000MOVLSD2PD"
+ "rr\000MOVLSS2PSrr\000MOVMSKPDrr\000MOVMSKPSrr\000MOVNTDQArm\000MOVNTDQm"
+ "r\000MOVNTImr\000MOVNTPDmr\000MOVNTPSmr\000MOVPC32r\000MOVPD2SDmr\000MO"
+ "VPD2SDrr\000MOVPDI2DImr\000MOVPDI2DIrr\000MOVPQI2QImr\000MOVPQIto64rr\000"
+ "MOVPS2SSmr\000MOVPS2SSrr\000MOVQI2PQIrm\000MOVQxrxr\000MOVSB\000MOVSD\000"
+ "MOVSD2PDrm\000MOVSD2PDrr\000MOVSDmr\000MOVSDrm\000MOVSDrr\000MOVSDto64m"
+ "r\000MOVSDto64rr\000MOVSHDUPrm\000MOVSHDUPrr\000MOVSLDUPrm\000MOVSLDUPr"
+ "r\000MOVSS2DImr\000MOVSS2DIrr\000MOVSS2PSrm\000MOVSS2PSrr\000MOVSSmr\000"
+ "MOVSSrm\000MOVSSrr\000MOVSW\000MOVSX16rm8\000MOVSX16rm8W\000MOVSX16rr8\000"
+ "MOVSX16rr8W\000MOVSX32rm16\000MOVSX32rm8\000MOVSX32rr16\000MOVSX32rr8\000"
+ "MOVSX64rm16\000MOVSX64rm32\000MOVSX64rm8\000MOVSX64rr16\000MOVSX64rr32\000"
+ "MOVSX64rr8\000MOVUPDmr\000MOVUPDmr_Int\000MOVUPDrm\000MOVUPDrm_Int\000M"
+ "OVUPDrr\000MOVUPSmr\000MOVUPSmr_Int\000MOVUPSrm\000MOVUPSrm_Int\000MOVU"
+ "PSrr\000MOVZDI2PDIrm\000MOVZDI2PDIrr\000MOVZPQILo2PQIrm\000MOVZPQILo2PQ"
+ "Irr\000MOVZQI2PQIrm\000MOVZQI2PQIrr\000MOVZSD2PDrm\000MOVZSS2PSrm\000MO"
+ "VZX16rm8\000MOVZX16rm8W\000MOVZX16rr8\000MOVZX16rr8W\000MOVZX32_NOREXrm"
+ "8\000MOVZX32_NOREXrr8\000MOVZX32rm16\000MOVZX32rm8\000MOVZX32rr16\000MO"
+ "VZX32rr8\000MOVZX64rm16\000MOVZX64rm16_Q\000MOVZX64rm32\000MOVZX64rm8\000"
+ "MOVZX64rm8_Q\000MOVZX64rr16\000MOVZX64rr16_Q\000MOVZX64rr32\000MOVZX64r"
+ "r8\000MOVZX64rr8_Q\000MOV_Fp3232\000MOV_Fp3264\000MOV_Fp3280\000MOV_Fp6"
+ "432\000MOV_Fp6464\000MOV_Fp6480\000MOV_Fp8032\000MOV_Fp8064\000MOV_Fp80"
+ "80\000MPSADBWrmi\000MPSADBWrri\000MUL16m\000MUL16r\000MUL32m\000MUL32r\000"
+ "MUL64m\000MUL64r\000MUL8m\000MUL8r\000MULPDrm\000MULPDrr\000MULPSrm\000"
+ "MULPSrr\000MULSDrm\000MULSDrm_Int\000MULSDrr\000MULSDrr_Int\000MULSSrm\000"
+ "MULSSrm_Int\000MULSSrr\000MULSSrr_Int\000MUL_F32m\000MUL_F64m\000MUL_FI"
+ "16m\000MUL_FI32m\000MUL_FPrST0\000MUL_FST0r\000MUL_Fp32\000MUL_Fp32m\000"
+ "MUL_Fp64\000MUL_Fp64m\000MUL_Fp64m32\000MUL_Fp80\000MUL_Fp80m32\000MUL_"
+ "Fp80m64\000MUL_FpI16m32\000MUL_FpI16m64\000MUL_FpI16m80\000MUL_FpI32m32"
+ "\000MUL_FpI32m64\000MUL_FpI32m80\000MUL_FrST0\000MWAIT\000NEG16m\000NEG"
+ "16r\000NEG32m\000NEG32r\000NEG64m\000NEG64r\000NEG8m\000NEG8r\000NOOP\000"
+ "NOOPL\000NOOPW\000NOT16m\000NOT16r\000NOT32m\000NOT32r\000NOT64m\000NOT"
+ "64r\000NOT8m\000NOT8r\000OR16i16\000OR16mi\000OR16mi8\000OR16mr\000OR16"
+ "ri\000OR16ri8\000OR16rm\000OR16rr\000OR16rr_REV\000OR32i32\000OR32mi\000"
+ "OR32mi8\000OR32mr\000OR32ri\000OR32ri8\000OR32rm\000OR32rr\000OR32rr_RE"
+ "V\000OR64i32\000OR64mi32\000OR64mi8\000OR64mr\000OR64ri32\000OR64ri8\000"
+ "OR64rm\000OR64rr\000OR64rr_REV\000OR8i8\000OR8mi\000OR8mr\000OR8ri\000O"
+ "R8rm\000OR8rr\000OR8rr_REV\000ORPDrm\000ORPDrr\000ORPSrm\000ORPSrr\000O"
+ "UT16ir\000OUT16rr\000OUT32ir\000OUT32rr\000OUT8ir\000OUT8rr\000OUTSB\000"
+ "OUTSD\000OUTSW\000PABSBrm128\000PABSBrm64\000PABSBrr128\000PABSBrr64\000"
+ "PABSDrm128\000PABSDrm64\000PABSDrr128\000PABSDrr64\000PABSWrm128\000PAB"
+ "SWrm64\000PABSWrr128\000PABSWrr64\000PACKSSDWrm\000PACKSSDWrr\000PACKSS"
+ "WBrm\000PACKSSWBrr\000PACKUSDWrm\000PACKUSDWrr\000PACKUSWBrm\000PACKUSW"
+ "Brr\000PADDBrm\000PADDBrr\000PADDDrm\000PADDDrr\000PADDQrm\000PADDQrr\000"
+ "PADDSBrm\000PADDSBrr\000PADDSWrm\000PADDSWrr\000PADDUSBrm\000PADDUSBrr\000"
+ "PADDUSWrm\000PADDUSWrr\000PADDWrm\000PADDWrr\000PALIGNR128rm\000PALIGNR"
+ "128rr\000PALIGNR64rm\000PALIGNR64rr\000PANDNrm\000PANDNrr\000PANDrm\000"
+ "PANDrr\000PAVGBrm\000PAVGBrr\000PAVGWrm\000PAVGWrr\000PBLENDVBrm0\000PB"
+ "LENDVBrr0\000PBLENDWrmi\000PBLENDWrri\000PCMPEQBrm\000PCMPEQBrr\000PCMP"
+ "EQDrm\000PCMPEQDrr\000PCMPEQQrm\000PCMPEQQrr\000PCMPEQWrm\000PCMPEQWrr\000"
+ "PCMPESTRIArm\000PCMPESTRIArr\000PCMPESTRICrm\000PCMPESTRICrr\000PCMPEST"
+ "RIOrm\000PCMPESTRIOrr\000PCMPESTRISrm\000PCMPESTRISrr\000PCMPESTRIZrm\000"
+ "PCMPESTRIZrr\000PCMPESTRIrm\000PCMPESTRIrr\000PCMPESTRM128MEM\000PCMPES"
+ "TRM128REG\000PCMPESTRM128rm\000PCMPESTRM128rr\000PCMPGTBrm\000PCMPGTBrr"
+ "\000PCMPGTDrm\000PCMPGTDrr\000PCMPGTQrm\000PCMPGTQrr\000PCMPGTWrm\000PC"
+ "MPGTWrr\000PCMPISTRIArm\000PCMPISTRIArr\000PCMPISTRICrm\000PCMPISTRICrr"
+ "\000PCMPISTRIOrm\000PCMPISTRIOrr\000PCMPISTRISrm\000PCMPISTRISrr\000PCM"
+ "PISTRIZrm\000PCMPISTRIZrr\000PCMPISTRIrm\000PCMPISTRIrr\000PCMPISTRM128"
+ "MEM\000PCMPISTRM128REG\000PCMPISTRM128rm\000PCMPISTRM128rr\000PEXTRBmr\000"
+ "PEXTRBrr\000PEXTRDmr\000PEXTRDrr\000PEXTRQmr\000PEXTRQrr\000PEXTRWmr\000"
+ "PEXTRWri\000PHADDDrm128\000PHADDDrm64\000PHADDDrr128\000PHADDDrr64\000P"
+ "HADDSWrm128\000PHADDSWrm64\000PHADDSWrr128\000PHADDSWrr64\000PHADDWrm12"
+ "8\000PHADDWrm64\000PHADDWrr128\000PHADDWrr64\000PHMINPOSUWrm128\000PHMI"
+ "NPOSUWrr128\000PHSUBDrm128\000PHSUBDrm64\000PHSUBDrr128\000PHSUBDrr64\000"
+ "PHSUBSWrm128\000PHSUBSWrm64\000PHSUBSWrr128\000PHSUBSWrr64\000PHSUBWrm1"
+ "28\000PHSUBWrm64\000PHSUBWrr128\000PHSUBWrr64\000PINSRBrm\000PINSRBrr\000"
+ "PINSRDrm\000PINSRDrr\000PINSRQrm\000PINSRQrr\000PINSRWrmi\000PINSRWrri\000"
+ "PMADDUBSWrm128\000PMADDUBSWrm64\000PMADDUBSWrr128\000PMADDUBSWrr64\000P"
+ "MADDWDrm\000PMADDWDrr\000PMAXSBrm\000PMAXSBrr\000PMAXSDrm\000PMAXSDrr\000"
+ "PMAXSWrm\000PMAXSWrr\000PMAXUBrm\000PMAXUBrr\000PMAXUDrm\000PMAXUDrr\000"
+ "PMAXUWrm\000PMAXUWrr\000PMINSBrm\000PMINSBrr\000PMINSDrm\000PMINSDrr\000"
+ "PMINSWrm\000PMINSWrr\000PMINUBrm\000PMINUBrr\000PMINUDrm\000PMINUDrr\000"
+ "PMINUWrm\000PMINUWrr\000PMOVMSKBrr\000PMOVSXBDrm\000PMOVSXBDrr\000PMOVS"
+ "XBQrm\000PMOVSXBQrr\000PMOVSXBWrm\000PMOVSXBWrr\000PMOVSXDQrm\000PMOVSX"
+ "DQrr\000PMOVSXWDrm\000PMOVSXWDrr\000PMOVSXWQrm\000PMOVSXWQrr\000PMOVZXB"
+ "Drm\000PMOVZXBDrr\000PMOVZXBQrm\000PMOVZXBQrr\000PMOVZXBWrm\000PMOVZXBW"
+ "rr\000PMOVZXDQrm\000PMOVZXDQrr\000PMOVZXWDrm\000PMOVZXWDrr\000PMOVZXWQr"
+ "m\000PMOVZXWQrr\000PMULDQrm\000PMULDQrr\000PMULHRSWrm128\000PMULHRSWrm6"
+ "4\000PMULHRSWrr128\000PMULHRSWrr64\000PMULHUWrm\000PMULHUWrr\000PMULHWr"
+ "m\000PMULHWrr\000PMULLDrm\000PMULLDrm_int\000PMULLDrr\000PMULLDrr_int\000"
+ "PMULLWrm\000PMULLWrr\000PMULUDQrm\000PMULUDQrr\000POP16r\000POP16rmm\000"
+ "POP16rmr\000POP32r\000POP32rmm\000POP32rmr\000POP64r\000POP64rmm\000POP"
+ "64rmr\000POPCNT16rm\000POPCNT16rr\000POPCNT32rm\000POPCNT32rr\000POPCNT"
+ "64rm\000POPCNT64rr\000POPF\000POPFD\000POPFQ\000POPFS16\000POPFS32\000P"
+ "OPFS64\000POPGS16\000POPGS32\000POPGS64\000PORrm\000PORrr\000PREFETCHNT"
+ "A\000PREFETCHT0\000PREFETCHT1\000PREFETCHT2\000PSADBWrm\000PSADBWrr\000"
+ "PSHUFBrm128\000PSHUFBrm64\000PSHUFBrr128\000PSHUFBrr64\000PSHUFDmi\000P"
+ "SHUFDri\000PSHUFHWmi\000PSHUFHWri\000PSHUFLWmi\000PSHUFLWri\000PSIGNBrm"
+ "128\000PSIGNBrm64\000PSIGNBrr128\000PSIGNBrr64\000PSIGNDrm128\000PSIGND"
+ "rm64\000PSIGNDrr128\000PSIGNDrr64\000PSIGNWrm128\000PSIGNWrm64\000PSIGN"
+ "Wrr128\000PSIGNWrr64\000PSLLDQri\000PSLLDri\000PSLLDrm\000PSLLDrr\000PS"
+ "LLQri\000PSLLQrm\000PSLLQrr\000PSLLWri\000PSLLWrm\000PSLLWrr\000PSRADri"
+ "\000PSRADrm\000PSRADrr\000PSRAWri\000PSRAWrm\000PSRAWrr\000PSRLDQri\000"
+ "PSRLDri\000PSRLDrm\000PSRLDrr\000PSRLQri\000PSRLQrm\000PSRLQrr\000PSRLW"
+ "ri\000PSRLWrm\000PSRLWrr\000PSUBBrm\000PSUBBrr\000PSUBDrm\000PSUBDrr\000"
+ "PSUBQrm\000PSUBQrr\000PSUBSBrm\000PSUBSBrr\000PSUBSWrm\000PSUBSWrr\000P"
+ "SUBUSBrm\000PSUBUSBrr\000PSUBUSWrm\000PSUBUSWrr\000PSUBWrm\000PSUBWrr\000"
+ "PTESTrm\000PTESTrr\000PUNPCKHBWrm\000PUNPCKHBWrr\000PUNPCKHDQrm\000PUNP"
+ "CKHDQrr\000PUNPCKHQDQrm\000PUNPCKHQDQrr\000PUNPCKHWDrm\000PUNPCKHWDrr\000"
+ "PUNPCKLBWrm\000PUNPCKLBWrr\000PUNPCKLDQrm\000PUNPCKLDQrr\000PUNPCKLQDQr"
+ "m\000PUNPCKLQDQrr\000PUNPCKLWDrm\000PUNPCKLWDrr\000PUSH16r\000PUSH16rmm"
+ "\000PUSH16rmr\000PUSH32i16\000PUSH32i32\000PUSH32i8\000PUSH32r\000PUSH3"
+ "2rmm\000PUSH32rmr\000PUSH64i16\000PUSH64i32\000PUSH64i8\000PUSH64r\000P"
+ "USH64rmm\000PUSH64rmr\000PUSHF\000PUSHFD\000PUSHFQ64\000PUSHFS16\000PUS"
+ "HFS32\000PUSHFS64\000PUSHGS16\000PUSHGS32\000PUSHGS64\000PXORrm\000PXOR"
+ "rr\000RCL16m1\000RCL16mCL\000RCL16mi\000RCL16r1\000RCL16rCL\000RCL16ri\000"
+ "RCL32m1\000RCL32mCL\000RCL32mi\000RCL32r1\000RCL32rCL\000RCL32ri\000RCL"
+ "64m1\000RCL64mCL\000RCL64mi\000RCL64r1\000RCL64rCL\000RCL64ri\000RCL8m1"
+ "\000RCL8mCL\000RCL8mi\000RCL8r1\000RCL8rCL\000RCL8ri\000RCPPSm\000RCPPS"
+ "m_Int\000RCPPSr\000RCPPSr_Int\000RCPSSm\000RCPSSm_Int\000RCPSSr\000RCPS"
+ "Sr_Int\000RCR16m1\000RCR16mCL\000RCR16mi\000RCR16r1\000RCR16rCL\000RCR1"
+ "6ri\000RCR32m1\000RCR32mCL\000RCR32mi\000RCR32r1\000RCR32rCL\000RCR32ri"
+ "\000RCR64m1\000RCR64mCL\000RCR64mi\000RCR64r1\000RCR64rCL\000RCR64ri\000"
+ "RCR8m1\000RCR8mCL\000RCR8mi\000RCR8r1\000RCR8rCL\000RCR8ri\000RDMSR\000"
+ "RDPMC\000RDTSC\000RDTSCP\000REPNE_PREFIX\000REP_MOVSB\000REP_MOVSD\000R"
+ "EP_MOVSQ\000REP_MOVSW\000REP_PREFIX\000REP_STOSB\000REP_STOSD\000REP_ST"
+ "OSQ\000REP_STOSW\000RET\000RETI\000ROL16m1\000ROL16mCL\000ROL16mi\000RO"
+ "L16r1\000ROL16rCL\000ROL16ri\000ROL32m1\000ROL32mCL\000ROL32mi\000ROL32"
+ "r1\000ROL32rCL\000ROL32ri\000ROL64m1\000ROL64mCL\000ROL64mi\000ROL64r1\000"
+ "ROL64rCL\000ROL64ri\000ROL8m1\000ROL8mCL\000ROL8mi\000ROL8r1\000ROL8rCL"
+ "\000ROL8ri\000ROR16m1\000ROR16mCL\000ROR16mi\000ROR16r1\000ROR16rCL\000"
+ "ROR16ri\000ROR32m1\000ROR32mCL\000ROR32mi\000ROR32r1\000ROR32rCL\000ROR"
+ "32ri\000ROR64m1\000ROR64mCL\000ROR64mi\000ROR64r1\000ROR64rCL\000ROR64r"
+ "i\000ROR8m1\000ROR8mCL\000ROR8mi\000ROR8r1\000ROR8rCL\000ROR8ri\000ROUN"
+ "DPDm_Int\000ROUNDPDr_Int\000ROUNDPSm_Int\000ROUNDPSr_Int\000ROUNDSDm_In"
+ "t\000ROUNDSDr_Int\000ROUNDSSm_Int\000ROUNDSSr_Int\000RSM\000RSQRTPSm\000"
+ "RSQRTPSm_Int\000RSQRTPSr\000RSQRTPSr_Int\000RSQRTSSm\000RSQRTSSm_Int\000"
+ "RSQRTSSr\000RSQRTSSr_Int\000SAHF\000SAR16m1\000SAR16mCL\000SAR16mi\000S"
+ "AR16r1\000SAR16rCL\000SAR16ri\000SAR32m1\000SAR32mCL\000SAR32mi\000SAR3"
+ "2r1\000SAR32rCL\000SAR32ri\000SAR64m1\000SAR64mCL\000SAR64mi\000SAR64r1"
+ "\000SAR64rCL\000SAR64ri\000SAR8m1\000SAR8mCL\000SAR8mi\000SAR8r1\000SAR"
+ "8rCL\000SAR8ri\000SBB16i16\000SBB16mi\000SBB16mi8\000SBB16mr\000SBB16ri"
+ "\000SBB16ri8\000SBB16rm\000SBB16rr\000SBB16rr_REV\000SBB32i32\000SBB32m"
+ "i\000SBB32mi8\000SBB32mr\000SBB32ri\000SBB32ri8\000SBB32rm\000SBB32rr\000"
+ "SBB32rr_REV\000SBB64i32\000SBB64mi32\000SBB64mi8\000SBB64mr\000SBB64ri3"
+ "2\000SBB64ri8\000SBB64rm\000SBB64rr\000SBB64rr_REV\000SBB8i8\000SBB8mi\000"
+ "SBB8mr\000SBB8ri\000SBB8rm\000SBB8rr\000SBB8rr_REV\000SCAS16\000SCAS32\000"
+ "SCAS64\000SCAS8\000SETAEm\000SETAEr\000SETAm\000SETAr\000SETBEm\000SETB"
+ "Er\000SETB_C16r\000SETB_C32r\000SETB_C64r\000SETB_C8r\000SETBm\000SETBr"
+ "\000SETEm\000SETEr\000SETGEm\000SETGEr\000SETGm\000SETGr\000SETLEm\000S"
+ "ETLEr\000SETLm\000SETLr\000SETNEm\000SETNEr\000SETNOm\000SETNOr\000SETN"
+ "Pm\000SETNPr\000SETNSm\000SETNSr\000SETOm\000SETOr\000SETPm\000SETPr\000"
+ "SETSm\000SETSr\000SFENCE\000SGDTm\000SHL16m1\000SHL16mCL\000SHL16mi\000"
+ "SHL16r1\000SHL16rCL\000SHL16ri\000SHL32m1\000SHL32mCL\000SHL32mi\000SHL"
+ "32r1\000SHL32rCL\000SHL32ri\000SHL64m1\000SHL64mCL\000SHL64mi\000SHL64r"
+ "1\000SHL64rCL\000SHL64ri\000SHL8m1\000SHL8mCL\000SHL8mi\000SHL8r1\000SH"
+ "L8rCL\000SHL8ri\000SHLD16mrCL\000SHLD16mri8\000SHLD16rrCL\000SHLD16rri8"
+ "\000SHLD32mrCL\000SHLD32mri8\000SHLD32rrCL\000SHLD32rri8\000SHLD64mrCL\000"
+ "SHLD64mri8\000SHLD64rrCL\000SHLD64rri8\000SHR16m1\000SHR16mCL\000SHR16m"
+ "i\000SHR16r1\000SHR16rCL\000SHR16ri\000SHR32m1\000SHR32mCL\000SHR32mi\000"
+ "SHR32r1\000SHR32rCL\000SHR32ri\000SHR64m1\000SHR64mCL\000SHR64mi\000SHR"
+ "64r1\000SHR64rCL\000SHR64ri\000SHR8m1\000SHR8mCL\000SHR8mi\000SHR8r1\000"
+ "SHR8rCL\000SHR8ri\000SHRD16mrCL\000SHRD16mri8\000SHRD16rrCL\000SHRD16rr"
+ "i8\000SHRD32mrCL\000SHRD32mri8\000SHRD32rrCL\000SHRD32rri8\000SHRD64mrC"
+ "L\000SHRD64mri8\000SHRD64rrCL\000SHRD64rri8\000SHUFPDrmi\000SHUFPDrri\000"
+ "SHUFPSrmi\000SHUFPSrri\000SIDTm\000SIN_F\000SIN_Fp32\000SIN_Fp64\000SIN"
+ "_Fp80\000SLDT16m\000SLDT16r\000SLDT64m\000SLDT64r\000SMSW16m\000SMSW16r"
+ "\000SMSW32r\000SMSW64r\000SQRTPDm\000SQRTPDm_Int\000SQRTPDr\000SQRTPDr_"
+ "Int\000SQRTPSm\000SQRTPSm_Int\000SQRTPSr\000SQRTPSr_Int\000SQRTSDm\000S"
+ "QRTSDm_Int\000SQRTSDr\000SQRTSDr_Int\000SQRTSSm\000SQRTSSm_Int\000SQRTS"
+ "Sr\000SQRTSSr_Int\000SQRT_F\000SQRT_Fp32\000SQRT_Fp64\000SQRT_Fp80\000S"
+ "S_PREFIX\000STC\000STD\000STI\000STMXCSR\000STOSB\000STOSD\000STOSW\000"
+ "STRm\000STRr\000ST_F32m\000ST_F64m\000ST_FP32m\000ST_FP64m\000ST_FP80m\000"
+ "ST_FPrr\000ST_Fp32m\000ST_Fp64m\000ST_Fp64m32\000ST_Fp80m32\000ST_Fp80m"
+ "64\000ST_FpP32m\000ST_FpP64m\000ST_FpP64m32\000ST_FpP80m\000ST_FpP80m32"
+ "\000ST_FpP80m64\000ST_Frr\000SUB16i16\000SUB16mi\000SUB16mi8\000SUB16mr"
+ "\000SUB16ri\000SUB16ri8\000SUB16rm\000SUB16rr\000SUB16rr_REV\000SUB32i3"
+ "2\000SUB32mi\000SUB32mi8\000SUB32mr\000SUB32ri\000SUB32ri8\000SUB32rm\000"
+ "SUB32rr\000SUB32rr_REV\000SUB64i32\000SUB64mi32\000SUB64mi8\000SUB64mr\000"
+ "SUB64ri32\000SUB64ri8\000SUB64rm\000SUB64rr\000SUB64rr_REV\000SUB8i8\000"
+ "SUB8mi\000SUB8mr\000SUB8ri\000SUB8rm\000SUB8rr\000SUB8rr_REV\000SUBPDrm"
+ "\000SUBPDrr\000SUBPSrm\000SUBPSrr\000SUBR_F32m\000SUBR_F64m\000SUBR_FI1"
+ "6m\000SUBR_FI32m\000SUBR_FPrST0\000SUBR_FST0r\000SUBR_Fp32m\000SUBR_Fp6"
+ "4m\000SUBR_Fp64m32\000SUBR_Fp80m32\000SUBR_Fp80m64\000SUBR_FpI16m32\000"
+ "SUBR_FpI16m64\000SUBR_FpI16m80\000SUBR_FpI32m32\000SUBR_FpI32m64\000SUB"
+ "R_FpI32m80\000SUBR_FrST0\000SUBSDrm\000SUBSDrm_Int\000SUBSDrr\000SUBSDr"
+ "r_Int\000SUBSSrm\000SUBSSrm_Int\000SUBSSrr\000SUBSSrr_Int\000SUB_F32m\000"
+ "SUB_F64m\000SUB_FI16m\000SUB_FI32m\000SUB_FPrST0\000SUB_FST0r\000SUB_Fp"
+ "32\000SUB_Fp32m\000SUB_Fp64\000SUB_Fp64m\000SUB_Fp64m32\000SUB_Fp80\000"
+ "SUB_Fp80m32\000SUB_Fp80m64\000SUB_FpI16m32\000SUB_FpI16m64\000SUB_FpI16"
+ "m80\000SUB_FpI32m32\000SUB_FpI32m64\000SUB_FpI32m80\000SUB_FrST0\000SWA"
+ "PGS\000SYSCALL\000SYSENTER\000SYSEXIT\000SYSEXIT64\000SYSRET\000TAILJMP"
+ "d\000TAILJMPm\000TAILJMPr\000TAILJMPr64\000TCRETURNdi\000TCRETURNdi64\000"
+ "TCRETURNri\000TCRETURNri64\000TEST16i16\000TEST16mi\000TEST16ri\000TEST"
+ "16rm\000TEST16rr\000TEST32i32\000TEST32mi\000TEST32ri\000TEST32rm\000TE"
+ "ST32rr\000TEST64i32\000TEST64mi32\000TEST64ri32\000TEST64rm\000TEST64rr"
+ "\000TEST8i8\000TEST8mi\000TEST8ri\000TEST8rm\000TEST8rr\000TLS_addr32\000"
+ "TLS_addr64\000TRAP\000TST_F\000TST_Fp32\000TST_Fp64\000TST_Fp80\000UCOM"
+ "ISDrm\000UCOMISDrr\000UCOMISSrm\000UCOMISSrr\000UCOM_FIPr\000UCOM_FIr\000"
+ "UCOM_FPPr\000UCOM_FPr\000UCOM_FpIr32\000UCOM_FpIr64\000UCOM_FpIr80\000U"
+ "COM_Fpr32\000UCOM_Fpr64\000UCOM_Fpr80\000UCOM_Fr\000UNPCKHPDrm\000UNPCK"
+ "HPDrr\000UNPCKHPSrm\000UNPCKHPSrr\000UNPCKLPDrm\000UNPCKLPDrr\000UNPCKL"
+ "PSrm\000UNPCKLPSrr\000VASTART_SAVE_XMM_REGS\000VERRm\000VERRr\000VERWm\000"
+ "VERWr\000VMCALL\000VMCLEARm\000VMLAUNCH\000VMPTRLDm\000VMPTRSTm\000VMRE"
+ "AD32rm\000VMREAD32rr\000VMREAD64rm\000VMREAD64rr\000VMRESUME\000VMWRITE"
+ "32rm\000VMWRITE32rr\000VMWRITE64rm\000VMWRITE64rr\000VMXOFF\000VMXON\000"
+ "V_SET0\000V_SETALLONES\000WAIT\000WBINVD\000WINCALL64m\000WINCALL64pcre"
+ "l32\000WINCALL64r\000WRMSR\000XADD16rm\000XADD16rr\000XADD32rm\000XADD3"
+ "2rr\000XADD64rm\000XADD64rr\000XADD8rm\000XADD8rr\000XCHG16ar\000XCHG16"
+ "rm\000XCHG16rr\000XCHG32ar\000XCHG32rm\000XCHG32rr\000XCHG64ar\000XCHG6"
+ "4rm\000XCHG64rr\000XCHG8rm\000XCHG8rr\000XCH_F\000XLAT\000XOR16i16\000X"
+ "OR16mi\000XOR16mi8\000XOR16mr\000XOR16ri\000XOR16ri8\000XOR16rm\000XOR1"
+ "6rr\000XOR16rr_REV\000XOR32i32\000XOR32mi\000XOR32mi8\000XOR32mr\000XOR"
+ "32ri\000XOR32ri8\000XOR32rm\000XOR32rr\000XOR32rr_REV\000XOR64i32\000XO"
+ "R64mi32\000XOR64mi8\000XOR64mr\000XOR64ri32\000XOR64ri8\000XOR64rm\000X"
+ "OR64rr\000XOR64rr_REV\000XOR8i8\000XOR8mi\000XOR8mr\000XOR8ri\000XOR8rm"
+ "\000XOR8rr\000XOR8rr_REV\000XORPDrm\000XORPDrr\000XORPSrm\000XORPSrr\000";
+ return Strs+InstAsmOffset[Opcode];
+}
+
+#endif
diff --git a/libclamav/c++/X86GenDAGISel.inc b/libclamav/c++/X86GenDAGISel.inc
index 36bd51a..75e490e 100644
--- a/libclamav/c++/X86GenDAGISel.inc
+++ b/libclamav/c++/X86GenDAGISel.inc
@@ -352,7 +352,7 @@ inline bool Predicate_cvtuu(SDNode *N) {
inline bool Predicate_def32(SDNode *N) {
return N->getOpcode() != ISD::TRUNCATE &&
- N->getOpcode() != TargetInstrInfo::EXTRACT_SUBREG &&
+ N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
N->getOpcode() != ISD::CopyFromReg &&
N->getOpcode() != X86ISD::CMOV;
@@ -1018,7 +1018,7 @@ DISABLE_INLINE SDNode *Emit_4(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0
return ResNode;
}
SDNode *Select_ISD_ADD_i8(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
// Pattern: (add:i8 GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
@@ -1067,9 +1067,6 @@ SDNode *Select_ISD_ADD_i8(SDNode *N) {
}
}
}
- }
- {
- SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
{
ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
@@ -1123,7 +1120,7 @@ DISABLE_INLINE SDNode *Emit_6(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0
return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, Tmp3);
}
SDNode *Select_ISD_ADD_i16(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
// Pattern: (add:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
@@ -1292,7 +1289,7 @@ DISABLE_INLINE SDNode *Emit_11(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT
return CurDAG->SelectNodeTo(N, Opc0, VT0, N1, N00);
}
SDNode *Select_ISD_ADD_i32(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
// Pattern: (add:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
@@ -1571,7 +1568,7 @@ DISABLE_INLINE SDNode *Emit_14(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT
return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, Tmp3);
}
SDNode *Select_ISD_ADD_i64(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
// Pattern: (add:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
@@ -1737,74 +1734,73 @@ DISABLE_INLINE SDNode *Emit_17(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT
return ResNode;
}
SDNode *Select_ISD_ADD_v8i8(SDNode *N) {
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasMMX())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (add:v8i8 VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PADDBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
+ if ((Subtarget->hasMMX())) {
{
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_16(N, X86::MMX_PADDBrm, MVT::v8i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
+ SDValue N0 = N->getOperand(0);
+
+ // Pattern: (add:v8i8 VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PADDBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_16(N, X86::MMX_PADDBrm, MVT::v8i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
}
}
}
}
- }
- // Pattern: (add:v8i8 (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v8i8:$src1)
- // Emits: (MMX_PADDBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N0.hasOneUse()) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::LOAD &&
- N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
- SDValue Chain00 = N00.getNode()->getOperand(0);
- if (Predicate_unindexedload(N00.getNode()) &&
- Predicate_load(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N1 = N->getOperand(1);
- if (N00.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_17(N, X86::MMX_PADDBrm, MVT::v8i8, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
+ // Pattern: (add:v8i8 (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v8i8:$src1)
+ // Emits: (MMX_PADDBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N0.hasOneUse()) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::LOAD &&
+ N00.hasOneUse() &&
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
+ SDValue Chain00 = N00.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N00.getNode()) &&
+ Predicate_load(N00.getNode())) {
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
+ SDValue N1 = N->getOperand(1);
+ if (N00.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_17(N, X86::MMX_PADDBrm, MVT::v8i8, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
+ }
}
}
}
}
}
- }
- // Pattern: (add:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
- // Emits: (MMX_PADDBrr:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasMMX())) {
+ // Pattern: (add:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Emits: (MMX_PADDBrr:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
SDNode *Result = Emit_15(N, X86::MMX_PADDBrr, MVT::v8i8);
return Result;
}
@@ -1814,76 +1810,75 @@ SDNode *Select_ISD_ADD_v8i8(SDNode *N) {
}
SDNode *Select_ISD_ADD_v16i8(SDNode *N) {
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (add:v16i8 VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PADDBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
{
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_16(N, X86::PADDBrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
+ SDValue N0 = N->getOperand(0);
+
+ // Pattern: (add:v16i8 VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PADDBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_16(N, X86::PADDBrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
}
}
}
}
- }
- // Pattern: (add:v16i8 (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v16i8:$src1)
- // Emits: (PADDBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N0.hasOneUse()) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::LOAD &&
- N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
- SDValue Chain00 = N00.getNode()->getOperand(0);
- if (Predicate_unindexedload(N00.getNode()) &&
- Predicate_load(N00.getNode()) &&
- Predicate_memop(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N1 = N->getOperand(1);
- if (N00.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_17(N, X86::PADDBrm, MVT::v16i8, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
+ // Pattern: (add:v16i8 (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v16i8:$src1)
+ // Emits: (PADDBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N0.hasOneUse()) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::LOAD &&
+ N00.hasOneUse() &&
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
+ SDValue Chain00 = N00.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N00.getNode()) &&
+ Predicate_load(N00.getNode()) &&
+ Predicate_memop(N00.getNode())) {
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
+ SDValue N1 = N->getOperand(1);
+ if (N00.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_17(N, X86::PADDBrm, MVT::v16i8, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
+ }
}
}
}
}
}
- }
- // Pattern: (add:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Emits: (PADDBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
+ // Pattern: (add:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Emits: (PADDBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
SDNode *Result = Emit_15(N, X86::PADDBrr, MVT::v16i8);
return Result;
}
@@ -1893,74 +1888,73 @@ SDNode *Select_ISD_ADD_v16i8(SDNode *N) {
}
SDNode *Select_ISD_ADD_v4i16(SDNode *N) {
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasMMX())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (add:v4i16 VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PADDWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
+ if ((Subtarget->hasMMX())) {
{
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_16(N, X86::MMX_PADDWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
+ SDValue N0 = N->getOperand(0);
+
+ // Pattern: (add:v4i16 VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PADDWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_16(N, X86::MMX_PADDWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
}
}
}
}
- }
- // Pattern: (add:v4i16 (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v4i16:$src1)
- // Emits: (MMX_PADDWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N0.hasOneUse()) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::LOAD &&
- N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
- SDValue Chain00 = N00.getNode()->getOperand(0);
- if (Predicate_unindexedload(N00.getNode()) &&
- Predicate_load(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N1 = N->getOperand(1);
- if (N00.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_17(N, X86::MMX_PADDWrm, MVT::v4i16, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
+ // Pattern: (add:v4i16 (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v4i16:$src1)
+ // Emits: (MMX_PADDWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N0.hasOneUse()) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::LOAD &&
+ N00.hasOneUse() &&
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
+ SDValue Chain00 = N00.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N00.getNode()) &&
+ Predicate_load(N00.getNode())) {
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
+ SDValue N1 = N->getOperand(1);
+ if (N00.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_17(N, X86::MMX_PADDWrm, MVT::v4i16, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
+ }
}
}
}
}
}
- }
- // Pattern: (add:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
- // Emits: (MMX_PADDWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasMMX())) {
+ // Pattern: (add:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Emits: (MMX_PADDWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
SDNode *Result = Emit_15(N, X86::MMX_PADDWrr, MVT::v4i16);
return Result;
}
@@ -1970,76 +1964,75 @@ SDNode *Select_ISD_ADD_v4i16(SDNode *N) {
}
SDNode *Select_ISD_ADD_v8i16(SDNode *N) {
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (add:v8i16 VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PADDWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
{
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_16(N, X86::PADDWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
+ SDValue N0 = N->getOperand(0);
+
+ // Pattern: (add:v8i16 VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PADDWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_16(N, X86::PADDWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
}
}
}
}
- }
- // Pattern: (add:v8i16 (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
- // Emits: (PADDWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N0.hasOneUse()) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::LOAD &&
- N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
- SDValue Chain00 = N00.getNode()->getOperand(0);
- if (Predicate_unindexedload(N00.getNode()) &&
- Predicate_load(N00.getNode()) &&
- Predicate_memop(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N1 = N->getOperand(1);
- if (N00.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_17(N, X86::PADDWrm, MVT::v8i16, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
+ // Pattern: (add:v8i16 (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
+ // Emits: (PADDWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N0.hasOneUse()) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::LOAD &&
+ N00.hasOneUse() &&
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
+ SDValue Chain00 = N00.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N00.getNode()) &&
+ Predicate_load(N00.getNode()) &&
+ Predicate_memop(N00.getNode())) {
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
+ SDValue N1 = N->getOperand(1);
+ if (N00.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_17(N, X86::PADDWrm, MVT::v8i16, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
+ }
}
}
}
}
}
- }
- // Pattern: (add:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Emits: (PADDWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
+ // Pattern: (add:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Emits: (PADDWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
SDNode *Result = Emit_15(N, X86::PADDWrr, MVT::v8i16);
return Result;
}
@@ -2049,74 +2042,73 @@ SDNode *Select_ISD_ADD_v8i16(SDNode *N) {
}
SDNode *Select_ISD_ADD_v2i32(SDNode *N) {
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasMMX())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (add:v2i32 VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PADDDrm:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
+ if ((Subtarget->hasMMX())) {
{
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_16(N, X86::MMX_PADDDrm, MVT::v2i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
+ SDValue N0 = N->getOperand(0);
+
+ // Pattern: (add:v2i32 VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PADDDrm:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_16(N, X86::MMX_PADDDrm, MVT::v2i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
}
}
}
}
- }
- // Pattern: (add:v2i32 (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v2i32:$src1)
- // Emits: (MMX_PADDDrm:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N0.hasOneUse()) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::LOAD &&
- N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
- SDValue Chain00 = N00.getNode()->getOperand(0);
- if (Predicate_unindexedload(N00.getNode()) &&
- Predicate_load(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N1 = N->getOperand(1);
- if (N00.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_17(N, X86::MMX_PADDDrm, MVT::v2i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
+ // Pattern: (add:v2i32 (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v2i32:$src1)
+ // Emits: (MMX_PADDDrm:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N0.hasOneUse()) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::LOAD &&
+ N00.hasOneUse() &&
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
+ SDValue Chain00 = N00.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N00.getNode()) &&
+ Predicate_load(N00.getNode())) {
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
+ SDValue N1 = N->getOperand(1);
+ if (N00.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_17(N, X86::MMX_PADDDrm, MVT::v2i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
+ }
}
}
}
}
}
- }
- // Pattern: (add:v2i32 VR64:v2i32:$src1, VR64:v2i32:$src2)
- // Emits: (MMX_PADDDrr:v2i32 VR64:v2i32:$src1, VR64:v2i32:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasMMX())) {
+ // Pattern: (add:v2i32 VR64:v2i32:$src1, VR64:v2i32:$src2)
+ // Emits: (MMX_PADDDrr:v2i32 VR64:v2i32:$src1, VR64:v2i32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
SDNode *Result = Emit_15(N, X86::MMX_PADDDrr, MVT::v2i32);
return Result;
}
@@ -2126,76 +2118,75 @@ SDNode *Select_ISD_ADD_v2i32(SDNode *N) {
}
SDNode *Select_ISD_ADD_v4i32(SDNode *N) {
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (add:v4i32 VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PADDDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
{
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_16(N, X86::PADDDrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
+ SDValue N0 = N->getOperand(0);
+
+ // Pattern: (add:v4i32 VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PADDDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_16(N, X86::PADDDrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
}
}
}
}
- }
- // Pattern: (add:v4i32 (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v4i32:$src1)
- // Emits: (PADDDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N0.hasOneUse()) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::LOAD &&
- N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
- SDValue Chain00 = N00.getNode()->getOperand(0);
- if (Predicate_unindexedload(N00.getNode()) &&
- Predicate_load(N00.getNode()) &&
- Predicate_memop(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N1 = N->getOperand(1);
- if (N00.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_17(N, X86::PADDDrm, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
+ // Pattern: (add:v4i32 (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v4i32:$src1)
+ // Emits: (PADDDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N0.hasOneUse()) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::LOAD &&
+ N00.hasOneUse() &&
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
+ SDValue Chain00 = N00.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N00.getNode()) &&
+ Predicate_load(N00.getNode()) &&
+ Predicate_memop(N00.getNode())) {
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
+ SDValue N1 = N->getOperand(1);
+ if (N00.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_17(N, X86::PADDDrm, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
+ }
}
}
}
}
}
- }
- // Pattern: (add:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
- // Emits: (PADDDrr:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
+ // Pattern: (add:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Emits: (PADDDrr:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
SDNode *Result = Emit_15(N, X86::PADDDrr, MVT::v4i32);
return Result;
}
@@ -2205,74 +2196,73 @@ SDNode *Select_ISD_ADD_v4i32(SDNode *N) {
}
SDNode *Select_ISD_ADD_v1i64(SDNode *N) {
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasMMX())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (add:v1i64 VR64:v1i64:$src1, (bitconvert:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PADDQrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
+ if ((Subtarget->hasMMX())) {
{
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_16(N, X86::MMX_PADDQrm, MVT::v1i64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
+ SDValue N0 = N->getOperand(0);
+
+ // Pattern: (add:v1i64 VR64:v1i64:$src1, (bitconvert:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PADDQrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_16(N, X86::MMX_PADDQrm, MVT::v1i64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
}
}
}
}
- }
- // Pattern: (add:v1i64 (bitconvert:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v1i64:$src1)
- // Emits: (MMX_PADDQrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N0.hasOneUse()) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::LOAD &&
- N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
- SDValue Chain00 = N00.getNode()->getOperand(0);
- if (Predicate_unindexedload(N00.getNode()) &&
- Predicate_load(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N1 = N->getOperand(1);
- if (N00.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_17(N, X86::MMX_PADDQrm, MVT::v1i64, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
+ // Pattern: (add:v1i64 (bitconvert:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v1i64:$src1)
+ // Emits: (MMX_PADDQrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N0.hasOneUse()) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::LOAD &&
+ N00.hasOneUse() &&
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
+ SDValue Chain00 = N00.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N00.getNode()) &&
+ Predicate_load(N00.getNode())) {
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
+ SDValue N1 = N->getOperand(1);
+ if (N00.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_17(N, X86::MMX_PADDQrm, MVT::v1i64, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
+ }
}
}
}
}
}
- }
- // Pattern: (add:v1i64 VR64:v1i64:$src1, VR64:v1i64:$src2)
- // Emits: (MMX_PADDQrr:v1i64 VR64:v1i64:$src1, VR64:v1i64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasMMX())) {
+ // Pattern: (add:v1i64 VR64:v1i64:$src1, VR64:v1i64:$src2)
+ // Emits: (MMX_PADDQrr:v1i64 VR64:v1i64:$src1, VR64:v1i64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
SDNode *Result = Emit_15(N, X86::MMX_PADDQrr, MVT::v1i64);
return Result;
}
@@ -2308,64 +2298,63 @@ DISABLE_INLINE SDNode *Emit_19(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT
return ResNode;
}
SDNode *Select_ISD_ADD_v2i64(SDNode *N) {
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (add:v2i64 VR128:v2i64:$src1, (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (PADDQrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
{
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::PADDQrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
+ SDValue N0 = N->getOperand(0);
+
+ // Pattern: (add:v2i64 VR128:v2i64:$src1, (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (PADDQrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::PADDQrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
}
}
}
- }
- // Pattern: (add:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, VR128:v2i64:$src1)
- // Emits: (PADDQrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_19(N, X86::PADDQrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
+ // Pattern: (add:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, VR128:v2i64:$src1)
+ // Emits: (PADDQrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_19(N, X86::PADDQrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
}
}
}
- }
- // Pattern: (add:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
- // Emits: (PADDQrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
+ // Pattern: (add:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
+ // Emits: (PADDQrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
SDNode *Result = Emit_15(N, X86::PADDQrr, MVT::v2i64);
return Result;
}
@@ -2436,7 +2425,7 @@ DISABLE_INLINE SDNode *Emit_23(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT
return ResNode;
}
SDNode *Select_ISD_ADDC_i32(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
// Pattern: (addc:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
@@ -2485,9 +2474,6 @@ SDNode *Select_ISD_ADDC_i32(SDNode *N) {
}
}
}
- }
- {
- SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::Constant) {
@@ -2524,7 +2510,7 @@ DISABLE_INLINE SDNode *Emit_24(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT
return ResNode;
}
SDNode *Select_ISD_ADDC_i64(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
// Pattern: (addc:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
@@ -2573,9 +2559,6 @@ SDNode *Select_ISD_ADDC_i64(SDNode *N) {
}
}
}
- }
- {
- SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::Constant) {
@@ -2670,7 +2653,7 @@ DISABLE_INLINE SDNode *Emit_28(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT
return ResNode;
}
SDNode *Select_ISD_ADDE_i8(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
// Pattern: (adde:i8 GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
@@ -2719,13 +2702,10 @@ SDNode *Select_ISD_ADDE_i8(SDNode *N) {
}
}
}
- }
- // Pattern: (adde:i8 GR8:i8:$src1, (imm:i8):$src2)
- // Emits: (ADC8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- {
- SDValue N0 = N->getOperand(0);
+ // Pattern: (adde:i8 GR8:i8:$src1, (imm:i8):$src2)
+ // Emits: (ADC8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_27(N, X86::ADC8ri, MVT::i8);
@@ -2751,7 +2731,7 @@ DISABLE_INLINE SDNode *Emit_29(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT
return ResNode;
}
SDNode *Select_ISD_ADDE_i16(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
// Pattern: (adde:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
@@ -2800,9 +2780,6 @@ SDNode *Select_ISD_ADDE_i16(SDNode *N) {
}
}
}
- }
- {
- SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::Constant) {
@@ -2840,7 +2817,7 @@ DISABLE_INLINE SDNode *Emit_30(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT
return ResNode;
}
SDNode *Select_ISD_ADDE_i32(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
// Pattern: (adde:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
@@ -2889,9 +2866,6 @@ SDNode *Select_ISD_ADDE_i32(SDNode *N) {
}
}
}
- }
- {
- SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::Constant) {
@@ -2929,7 +2903,7 @@ DISABLE_INLINE SDNode *Emit_31(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT
return ResNode;
}
SDNode *Select_ISD_ADDE_i64(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
// Pattern: (adde:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
@@ -2978,9 +2952,6 @@ SDNode *Select_ISD_ADDE_i64(SDNode *N) {
}
}
}
- }
- {
- SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::Constant) {
@@ -3010,7 +2981,7 @@ SDNode *Select_ISD_ADDE_i64(SDNode *N) {
}
SDNode *Select_ISD_AND_i8(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
// Pattern: (and:i8 GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>)
@@ -3061,13 +3032,10 @@ SDNode *Select_ISD_AND_i8(SDNode *N) {
}
}
}
- }
- // Pattern: (and:i8 GR8:i8:$src1, (imm:i8):$src2)
- // Emits: (AND8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- {
- SDValue N0 = N->getOperand(0);
+ // Pattern: (and:i8 GR8:i8:$src1, (imm:i8):$src2)
+ // Emits: (AND8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_3(N, X86::AND8ri, MVT::i8);
@@ -3099,7 +3067,7 @@ DISABLE_INLINE SDNode *Emit_33(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::Sim
return CurDAG->SelectNodeTo(N, Opc1, VT1, Tmp3);
}
SDNode *Select_ISD_AND_i16(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
// Pattern: (and:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>)
@@ -3159,7 +3127,7 @@ SDNode *Select_ISD_AND_i16(SDNode *N) {
ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0 &&
CheckAndMask(N0, Tmp0, INT64_C(255))) {
- SDNode *Result = Emit_33(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX16rr8, MVT::i8, MVT::i16);
+ SDNode *Result = Emit_33(N, TargetOpcode::EXTRACT_SUBREG, X86::MOVZX16rr8, MVT::i8, MVT::i16);
return Result;
}
}
@@ -3173,7 +3141,7 @@ SDNode *Select_ISD_AND_i16(SDNode *N) {
ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0 &&
CheckAndMask(N0, Tmp0, INT64_C(255))) {
- SDNode *Result = Emit_32(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX16rr8, MVT::i16, MVT::i8, MVT::i16);
+ SDNode *Result = Emit_32(N, TargetOpcode::COPY_TO_REGCLASS, TargetOpcode::EXTRACT_SUBREG, X86::MOVZX16rr8, MVT::i16, MVT::i8, MVT::i16);
return Result;
}
}
@@ -3246,7 +3214,7 @@ DISABLE_INLINE SDNode *Emit_37(SDNode *N, unsigned Opc0, unsigned Opc1, unsigned
return CurDAG->SelectNodeTo(N, Opc2, VT2, Tmp7);
}
SDNode *Select_ISD_AND_i32(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
{
SDValue N1 = N->getOperand(1);
@@ -3366,7 +3334,7 @@ SDNode *Select_ISD_AND_i32(SDNode *N) {
int64_t CN2 = Tmp1->getSExtValue();
if (CN2 == INT64_C(8) &&
N01.getValueType() == MVT::i8) {
- SDNode *Result = Emit_37(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX32rr8, MVT::i32, MVT::i8, MVT::i32);
+ SDNode *Result = Emit_37(N, TargetOpcode::COPY_TO_REGCLASS, TargetOpcode::EXTRACT_SUBREG, X86::MOVZX32rr8, MVT::i32, MVT::i8, MVT::i32);
return Result;
}
}
@@ -3391,7 +3359,7 @@ SDNode *Select_ISD_AND_i32(SDNode *N) {
int64_t CN2 = Tmp1->getSExtValue();
if (CN2 == INT64_C(8) &&
N01.getValueType() == MVT::i8) {
- SDNode *Result = Emit_37(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX32_NOREXrr8, MVT::i32, MVT::i8, MVT::i32);
+ SDNode *Result = Emit_37(N, TargetOpcode::COPY_TO_REGCLASS, TargetOpcode::EXTRACT_SUBREG, X86::MOVZX32_NOREXrr8, MVT::i32, MVT::i8, MVT::i32);
return Result;
}
}
@@ -3407,7 +3375,7 @@ SDNode *Select_ISD_AND_i32(SDNode *N) {
ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0 &&
CheckAndMask(N0, Tmp0, INT64_C(65535))) {
- SDNode *Result = Emit_35(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX32rr16, MVT::i16, MVT::i32);
+ SDNode *Result = Emit_35(N, TargetOpcode::EXTRACT_SUBREG, X86::MOVZX32rr16, MVT::i16, MVT::i32);
return Result;
}
}
@@ -3421,7 +3389,7 @@ SDNode *Select_ISD_AND_i32(SDNode *N) {
ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0 &&
CheckAndMask(N0, Tmp0, INT64_C(255))) {
- SDNode *Result = Emit_33(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX32rr8, MVT::i8, MVT::i32);
+ SDNode *Result = Emit_33(N, TargetOpcode::EXTRACT_SUBREG, X86::MOVZX32rr8, MVT::i8, MVT::i32);
return Result;
}
}
@@ -3435,7 +3403,7 @@ SDNode *Select_ISD_AND_i32(SDNode *N) {
ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0 &&
CheckAndMask(N0, Tmp0, INT64_C(255))) {
- SDNode *Result = Emit_36(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX32rr8, MVT::i32, MVT::i8, MVT::i32);
+ SDNode *Result = Emit_36(N, TargetOpcode::COPY_TO_REGCLASS, TargetOpcode::EXTRACT_SUBREG, X86::MOVZX32rr8, MVT::i32, MVT::i8, MVT::i32);
return Result;
}
}
@@ -3500,7 +3468,7 @@ DISABLE_INLINE SDNode *Emit_40(SDNode *N, unsigned Opc0, unsigned Opc1, unsigned
return CurDAG->SelectNodeTo(N, Opc3, VT3, Tmp3, Tmp9, Tmp10);
}
SDNode *Select_ISD_AND_i64(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
// Pattern: (and:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
@@ -3549,9 +3517,6 @@ SDNode *Select_ISD_AND_i64(SDNode *N) {
}
}
}
- }
- {
- SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
{
ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
@@ -3570,7 +3535,7 @@ SDNode *Select_ISD_AND_i64(SDNode *N) {
int64_t CN2 = Tmp1->getSExtValue();
if (CN2 == INT64_C(8) &&
N01.getValueType() == MVT::i8) {
- SDNode *Result = Emit_40(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX32_NOREXrr8, TargetInstrInfo::SUBREG_TO_REG, MVT::i64, MVT::i8, MVT::i32, MVT::i64);
+ SDNode *Result = Emit_40(N, TargetOpcode::COPY_TO_REGCLASS, TargetOpcode::EXTRACT_SUBREG, X86::MOVZX32_NOREXrr8, TargetOpcode::SUBREG_TO_REG, MVT::i64, MVT::i8, MVT::i32, MVT::i64);
return Result;
}
}
@@ -3580,7 +3545,7 @@ SDNode *Select_ISD_AND_i64(SDNode *N) {
// Emits: (MOVZX64rr32:i64 (EXTRACT_SUBREG:i32 GR64:i64:$src, 4:i32))
// Pattern complexity = 8 cost = 2 size = 3
if (CheckAndMask(N0, Tmp0, INT64_C(4294967295))) {
- SDNode *Result = Emit_39(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX64rr32, MVT::i32, MVT::i64);
+ SDNode *Result = Emit_39(N, TargetOpcode::EXTRACT_SUBREG, X86::MOVZX64rr32, MVT::i32, MVT::i64);
return Result;
}
@@ -3588,7 +3553,7 @@ SDNode *Select_ISD_AND_i64(SDNode *N) {
// Emits: (MOVZX64rr16:i64 (EXTRACT_SUBREG:i16 GR64:i64:$src, 3:i32))
// Pattern complexity = 8 cost = 2 size = 3
if (CheckAndMask(N0, Tmp0, INT64_C(65535))) {
- SDNode *Result = Emit_35(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX64rr16, MVT::i16, MVT::i64);
+ SDNode *Result = Emit_35(N, TargetOpcode::EXTRACT_SUBREG, X86::MOVZX64rr16, MVT::i16, MVT::i64);
return Result;
}
@@ -3596,7 +3561,7 @@ SDNode *Select_ISD_AND_i64(SDNode *N) {
// Emits: (MOVZX64rr8:i64 (EXTRACT_SUBREG:i8 GR64:i64:$src, 1:i32))
// Pattern complexity = 8 cost = 2 size = 3
if (CheckAndMask(N0, Tmp0, INT64_C(255))) {
- SDNode *Result = Emit_33(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX64rr8, MVT::i8, MVT::i64);
+ SDNode *Result = Emit_33(N, TargetOpcode::EXTRACT_SUBREG, X86::MOVZX64rr8, MVT::i8, MVT::i64);
return Result;
}
}
@@ -3623,7 +3588,7 @@ SDNode *Select_ISD_AND_i64(SDNode *N) {
// Emits: (SUBREG_TO_REG:i64 0:i64, (AND32ri:i32 (EXTRACT_SUBREG:i32 GR64:i64:$src, 4:i32), (imm:i32):$imm), 4:i32)
// Pattern complexity = 7 cost = 3 size = 3
if (Predicate_i64immZExt32(N1.getNode())) {
- SDNode *Result = Emit_38(N, TargetInstrInfo::EXTRACT_SUBREG, X86::AND32ri, TargetInstrInfo::SUBREG_TO_REG, MVT::i32, MVT::i32, MVT::i64);
+ SDNode *Result = Emit_38(N, TargetOpcode::EXTRACT_SUBREG, X86::AND32ri, TargetOpcode::SUBREG_TO_REG, MVT::i32, MVT::i32, MVT::i64);
return Result;
}
}
@@ -3821,89 +3786,20 @@ DISABLE_INLINE SDNode *Emit_56(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT
return ResNode;
}
SDNode *Select_ISD_AND_v1i64(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
- {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N010 = N01.getNode()->getOperand(0);
-
- // Pattern: (and:v1i64 (xor:v1i64 VR64:v1i64:$src1, (bitconvert:v1i64 (build_vector:v2i32)<<P:Predicate_immAllOnesV>>)), (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (MMX_PANDNrm:v1i64 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 35 cost = 1 size = 3
- if (N010.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N010.getNode())) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
- N010.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_44(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- if (N010.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N010.getNode())) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
-
- // Pattern: (and:v1i64 (xor:v1i64 VR64:v1i64:$src1, (bitconvert:v1i64 (bitconvert:v4i16)<<P:Predicate_immAllOnesV_bc>>)), (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (MMX_PANDNrm:v1i64 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 35 cost = 1 size = 3
- if (N010.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_44(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (and:v1i64 (xor:v1i64 VR64:v1i64:$src1, (bitconvert:v1i64 (bitconvert:v8i8)<<P:Predicate_immAllOnesV_bc>>)), (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (MMX_PANDNrm:v1i64 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 35 cost = 1 size = 3
- if (N010.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_44(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
+ {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N010 = N01.getNode()->getOperand(0);
- // Pattern: (and:v1i64 (xor:v1i64 (bitconvert:v1i64 (build_vector:v2i32)<<P:Predicate_immAllOnesV>>), VR64:v1i64:$src1), (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (MMX_PANDNrm:v1i64 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 35 cost = 1 size = 3
- if (N00.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N000 = N00.getNode()->getOperand(0);
- if (N000.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N000.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
+ // Pattern: (and:v1i64 (xor:v1i64 VR64:v1i64:$src1, (bitconvert:v1i64 (build_vector:v2i32)<<P:Predicate_immAllOnesV>>)), (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (MMX_PANDNrm:v1i64 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 35 cost = 1 size = 3
+ if (N010.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N010.getNode())) {
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
@@ -3918,77 +3814,15 @@ SDNode *Select_ISD_AND_v1i64(SDNode *N) {
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
- N000.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_54(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ N010.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_44(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
}
}
- }
- }
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getNode()->getOperand(0);
-
- // Pattern: (and:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (xor:v1i64 VR64:v1i64:$src1, (bitconvert:v1i64 (build_vector:v2i32)<<P:Predicate_immAllOnesV>>)))
- // Emits: (MMX_PANDNrm:v1i64 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 35 cost = 1 size = 3
- {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N110.getNode()) &&
- N110.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_55(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
-
- // Pattern: (and:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (xor:v1i64 (bitconvert:v1i64 (build_vector:v2i32)<<P:Predicate_immAllOnesV>>), VR64:v1i64:$src1))
- // Emits: (MMX_PANDNrm:v1i64 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 35 cost = 1 size = 3
- if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N100.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N100.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_56(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (and:v1i64 (xor:v1i64 (bitconvert:v1i64 (bitconvert:v4i16)<<P:Predicate_immAllOnesV_bc>>), VR64:v1i64:$src1), (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (MMX_PANDNrm:v1i64 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 35 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N000 = N00.getNode()->getOperand(0);
- if (N000.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N000.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
+ if (N010.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N010.getNode())) {
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
@@ -4002,59 +3836,21 @@ SDNode *Select_ISD_AND_v1i64(SDNode *N) {
SDValue CPTmpN11_2;
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
- N000.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_54(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getNode()->getOperand(0);
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- // Pattern: (and:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (xor:v1i64 VR64:v1i64:$src1, (bitconvert:v1i64 (bitconvert:v4i16)<<P:Predicate_immAllOnesV_bc>>)))
- // Emits: (MMX_PANDNrm:v1i64 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 35 cost = 1 size = 3
- {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N110.getNode()) &&
- N110.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_55(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ // Pattern: (and:v1i64 (xor:v1i64 VR64:v1i64:$src1, (bitconvert:v1i64 (bitconvert:v4i16)<<P:Predicate_immAllOnesV_bc>>)), (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (MMX_PANDNrm:v1i64 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 35 cost = 1 size = 3
+ if (N010.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_44(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
- }
- }
- // Pattern: (and:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (xor:v1i64 (bitconvert:v1i64 (bitconvert:v4i16)<<P:Predicate_immAllOnesV_bc>>), VR64:v1i64:$src1))
- // Emits: (MMX_PANDNrm:v1i64 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 35 cost = 1 size = 3
- if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N100.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N100.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_56(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ // Pattern: (and:v1i64 (xor:v1i64 VR64:v1i64:$src1, (bitconvert:v1i64 (bitconvert:v8i8)<<P:Predicate_immAllOnesV_bc>>)), (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (MMX_PANDNrm:v1i64 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 35 cost = 1 size = 3
+ if (N010.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_44(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -4064,84 +3860,81 @@ SDNode *Select_ISD_AND_v1i64(SDNode *N) {
}
}
- // Pattern: (and:v1i64 (xor:v1i64 (bitconvert:v1i64 (bitconvert:v8i8)<<P:Predicate_immAllOnesV_bc>>), VR64:v1i64:$src1), (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Pattern: (and:v1i64 (xor:v1i64 (bitconvert:v1i64 (build_vector:v2i32)<<P:Predicate_immAllOnesV>>), VR64:v1i64:$src1), (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (MMX_PANDNrm:v1i64 VR64:v8i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 35 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N000 = N00.getNode()->getOperand(0);
- if (N000.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N000.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
- N000.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_54(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
+ if (N00.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ if (N000.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N000.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
+ N000.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_54(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
}
}
}
}
}
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getNode()->getOperand(0);
+ }
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getNode()->getOperand(0);
- // Pattern: (and:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (xor:v1i64 VR64:v1i64:$src1, (bitconvert:v1i64 (bitconvert:v8i8)<<P:Predicate_immAllOnesV_bc>>)))
- // Emits: (MMX_PANDNrm:v1i64 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 35 cost = 1 size = 3
- {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N110.getNode()) &&
- N110.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_55(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
+ // Pattern: (and:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (xor:v1i64 VR64:v1i64:$src1, (bitconvert:v1i64 (build_vector:v2i32)<<P:Predicate_immAllOnesV>>)))
+ // Emits: (MMX_PANDNrm:v1i64 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 35 cost = 1 size = 3
+ {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N110.getNode()) &&
+ N110.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_55(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
}
}
+ }
- // Pattern: (and:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (xor:v1i64 (bitconvert:v1i64 (bitconvert:v8i8)<<P:Predicate_immAllOnesV_bc>>), VR64:v1i64:$src1))
- // Emits: (MMX_PANDNrm:v1i64 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 35 cost = 1 size = 3
- if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- Predicate_immAllOnesV_bc(N100.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N100.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_56(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
+ // Pattern: (and:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (xor:v1i64 (bitconvert:v1i64 (build_vector:v2i32)<<P:Predicate_immAllOnesV>>), VR64:v1i64:$src1))
+ // Emits: (MMX_PANDNrm:v1i64 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 35 cost = 1 size = 3
+ if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N100.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N100.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_56(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
}
}
}
@@ -4149,45 +3942,101 @@ SDNode *Select_ISD_AND_v1i64(SDNode *N) {
}
}
}
- if ((Subtarget->hasMMX())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- // Pattern: (and:v1i64 (xor:v1i64 VR64:v1i64:$src1, (build_vector:v1i64)<<P:Predicate_immAllOnesV>>), (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (MMX_PANDNrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 32 cost = 1 size = 3
- {
+ // Pattern: (and:v1i64 (xor:v1i64 (bitconvert:v1i64 (bitconvert:v4i16)<<P:Predicate_immAllOnesV_bc>>), VR64:v1i64:$src1), (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (MMX_PANDNrm:v1i64 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 35 cost = 1 size = 3
+ if (N0.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ if (N000.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N000.getNode())) {
SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N01.getNode())) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
+ N000.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_54(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+
+ // Pattern: (and:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (xor:v1i64 VR64:v1i64:$src1, (bitconvert:v1i64 (bitconvert:v4i16)<<P:Predicate_immAllOnesV_bc>>)))
+ // Emits: (MMX_PANDNrm:v1i64 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 35 cost = 1 size = 3
+ {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N110.getNode()) &&
+ N110.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_55(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (and:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (xor:v1i64 (bitconvert:v1i64 (bitconvert:v4i16)<<P:Predicate_immAllOnesV_bc>>), VR64:v1i64:$src1))
+ // Emits: (MMX_PANDNrm:v1i64 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 35 cost = 1 size = 3
+ if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N100.getNode())) {
SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_42(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ if (N100.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_56(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
}
}
}
+ }
+ }
- // Pattern: (and:v1i64 (xor:v1i64 (build_vector:v1i64)<<P:Predicate_immAllOnesV>>, VR64:v1i64:$src1), (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (MMX_PANDNrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 32 cost = 1 size = 3
- if (N00.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N00.getNode())) {
+ // Pattern: (and:v1i64 (xor:v1i64 (bitconvert:v1i64 (bitconvert:v8i8)<<P:Predicate_immAllOnesV_bc>>), VR64:v1i64:$src1), (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (MMX_PANDNrm:v1i64 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 35 cost = 1 size = 3
+ if (N0.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ if (N000.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N000.getNode())) {
SDValue N01 = N0.getNode()->getOperand(1);
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::LOAD &&
@@ -4202,49 +4051,95 @@ SDNode *Select_ISD_AND_v1i64(SDNode *N) {
SDValue CPTmpN11_2;
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_48(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
+ N000.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_54(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
}
}
}
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getNode()->getOperand(0);
+ }
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getNode()->getOperand(0);
- // Pattern: (and:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (xor:v1i64 VR64:v1i64:$src1, (build_vector:v1i64)<<P:Predicate_immAllOnesV>>))
- // Emits: (MMX_PANDNrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 32 cost = 1 size = 3
- {
+ // Pattern: (and:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (xor:v1i64 VR64:v1i64:$src1, (bitconvert:v1i64 (bitconvert:v8i8)<<P:Predicate_immAllOnesV_bc>>)))
+ // Emits: (MMX_PANDNrm:v1i64 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 35 cost = 1 size = 3
+ {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N110.getNode()) &&
+ N110.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_55(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (and:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (xor:v1i64 (bitconvert:v1i64 (bitconvert:v8i8)<<P:Predicate_immAllOnesV_bc>>), VR64:v1i64:$src1))
+ // Emits: (MMX_PANDNrm:v1i64 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 35 cost = 1 size = 3
+ if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_immAllOnesV_bc(N100.getNode())) {
SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N11.getNode())) {
- SDNode *Result = Emit_49(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ if (N100.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_56(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasMMX())) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
- // Pattern: (and:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (xor:v1i64 (build_vector:v1i64)<<P:Predicate_immAllOnesV>>, VR64:v1i64:$src1))
- // Emits: (MMX_PANDNrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 32 cost = 1 size = 3
- if (N10.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N10.getNode())) {
- SDNode *Result = Emit_50(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ // Pattern: (and:v1i64 (xor:v1i64 VR64:v1i64:$src1, (build_vector:v1i64)<<P:Predicate_immAllOnesV>>), (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (MMX_PANDNrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 32 cost = 1 size = 3
+ {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N01.getNode())) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_42(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -4252,10 +4147,12 @@ SDNode *Select_ISD_AND_v1i64(SDNode *N) {
}
}
- // Pattern: (and:v1i64 VR64:v1i64:$src1, (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (MMX_PANDrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
+ // Pattern: (and:v1i64 (xor:v1i64 (build_vector:v1i64)<<P:Predicate_immAllOnesV>>, VR64:v1i64:$src1), (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (MMX_PANDNrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 32 cost = 1 size = 3
+ if (N00.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N00.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
@@ -4270,35 +4167,101 @@ SDNode *Select_ISD_AND_v1i64(SDNode *N) {
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::MMX_PANDrm, MVT::v1i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_48(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
}
}
+ }
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getNode()->getOperand(0);
- // Pattern: (and:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, VR64:v1i64:$src1)
- // Emits: (MMX_PANDrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_19(N, X86::MMX_PANDrm, MVT::v1i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ // Pattern: (and:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (xor:v1i64 VR64:v1i64:$src1, (build_vector:v1i64)<<P:Predicate_immAllOnesV>>))
+ // Emits: (MMX_PANDNrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 32 cost = 1 size = 3
+ {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N11.getNode())) {
+ SDNode *Result = Emit_49(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (and:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (xor:v1i64 (build_vector:v1i64)<<P:Predicate_immAllOnesV>>, VR64:v1i64:$src1))
+ // Emits: (MMX_PANDNrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 32 cost = 1 size = 3
+ if (N10.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N10.getNode())) {
+ SDNode *Result = Emit_50(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (and:v1i64 VR64:v1i64:$src1, (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (MMX_PANDrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::MMX_PANDrm, MVT::v1i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
}
}
+
+ // Pattern: (and:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, VR64:v1i64:$src1)
+ // Emits: (MMX_PANDrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_19(N, X86::MMX_PANDrm, MVT::v1i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
}
{
SDValue N0 = N->getOperand(0);
@@ -4776,177 +4739,16 @@ DISABLE_INLINE SDNode *Emit_71(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT
return ResNode;
}
SDNode *Select_ISD_AND_v2i64(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
- if ((Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N000 = N00.getNode()->getOperand(0);
-
- // Pattern: (and:v2i64 (xor:v2i64 (bitconvert:v2i64 VR128:v4f32:$src1), (bitconvert:v2i64 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>)), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (ANDNPSrm:v2i64 VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 38 cost = 1 size = 3
- {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N010 = N01.getNode()->getOperand(0);
- if (N010.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N010.getNode())) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
- N000.getValueType() == MVT::v4f32 &&
- N010.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_58(N, X86::ANDNPSrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (and:v2i64 (xor:v2i64 (bitconvert:v2i64 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>), (bitconvert:v2i64 VR128:v4f32:$src1)), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (ANDNPSrm:v2i64 VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 38 cost = 1 size = 3
- if (N000.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N000.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N010 = N01.getNode()->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
- N000.getValueType() == MVT::v4i32 &&
- N010.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_63(N, X86::ANDNPSrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N100 = N10.getNode()->getOperand(0);
-
- // Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (xor:v2i64 (bitconvert:v2i64 VR128:v4f32:$src1), (bitconvert:v2i64 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>)))
- // Emits: (ANDNPSrm:v2i64 VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 38 cost = 1 size = 3
- {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N110.getNode()) &&
- N100.getValueType() == MVT::v4f32 &&
- N110.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_64(N, X86::ANDNPSrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
-
- // Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (xor:v2i64 (bitconvert:v2i64 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>), (bitconvert:v2i64 VR128:v4f32:$src1)))
- // Emits: (ANDNPSrm:v2i64 VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 38 cost = 1 size = 3
- if (N100.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N100.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N100.getValueType() == MVT::v4i32 &&
- N110.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_65(N, X86::ANDNPSrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
+ if ((Subtarget->hasSSE1())) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N000 = N00.getNode()->getOperand(0);
- // Pattern: (and:v2i64 (xor:v2i64 (bitconvert:v2i64 VR128:v2f64:$src1), (build_vector:v2i64)<<P:Predicate_immAllOnesV>>), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (ANDNPDrm:v2i64 VR128:v2f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 35 cost = 1 size = 3
- if (N00.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N000 = N00.getNode()->getOperand(0);
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N01.getNode())) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
- N000.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_61(N, X86::ANDNPDrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- }
+ // Pattern: (and:v2i64 (xor:v2i64 (bitconvert:v2i64 VR128:v4f32:$src1), (bitconvert:v2i64 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>)), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (ANDNPSrm:v2i64 VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 38 cost = 1 size = 3
{
SDValue N01 = N0.getNode()->getOperand(1);
if (N01.getNode()->getOpcode() == ISD::BIT_CONVERT) {
@@ -4967,31 +4769,11 @@ SDNode *Select_ISD_AND_v2i64(SDNode *N) {
SDValue CPTmpN11_2;
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
-
- // Pattern: (and:v2i64 (xor:v2i64 VR128:v2i64:$src1, (bitconvert:v2i64 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>)), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (PANDNrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 35 cost = 1 size = 3
- if (N010.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_44(N, X86::PANDNrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (and:v2i64 (xor:v2i64 VR128:v2i64:$src1, (bitconvert:v2i64 (build_vector:v8i16)<<P:Predicate_immAllOnesV>>)), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (PANDNrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 35 cost = 1 size = 3
- if (N010.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_44(N, X86::PANDNrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (and:v2i64 (xor:v2i64 VR128:v2i64:$src1, (bitconvert:v2i64 (build_vector:v16i8)<<P:Predicate_immAllOnesV>>)), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (PANDNrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 35 cost = 1 size = 3
- if (N010.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_44(N, X86::PANDNrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
+ N000.getValueType() == MVT::v4f32 &&
+ N010.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_58(N, X86::ANDNPSrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
}
}
}
@@ -4999,11 +4781,11 @@ SDNode *Select_ISD_AND_v2i64(SDNode *N) {
}
}
- // Pattern: (and:v2i64 (xor:v2i64 (build_vector:v2i64)<<P:Predicate_immAllOnesV>>, (bitconvert:v2i64 VR128:v2f64:$src1)), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (ANDNPDrm:v2i64 VR128:v2f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 35 cost = 1 size = 3
- if (N00.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N00.getNode())) {
+ // Pattern: (and:v2i64 (xor:v2i64 (bitconvert:v2i64 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>), (bitconvert:v2i64 VR128:v4f32:$src1)), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (ANDNPSrm:v2i64 VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 38 cost = 1 size = 3
+ if (N000.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N000.getNode())) {
SDValue N01 = N0.getNode()->getOperand(1);
if (N01.getNode()->getOpcode() == ISD::BIT_CONVERT) {
SDValue N010 = N01.getNode()->getOperand(0);
@@ -5022,8 +4804,9 @@ SDNode *Select_ISD_AND_v2i64(SDNode *N) {
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
- N010.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_69(N, X86::ANDNPDrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ N000.getValueType() == MVT::v4i32 &&
+ N010.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_63(N, X86::ANDNPSrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -5031,48 +4814,55 @@ SDNode *Select_ISD_AND_v2i64(SDNode *N) {
}
}
}
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getNode()->getOperand(0);
+ }
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N100 = N10.getNode()->getOperand(0);
- // Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (xor:v2i64 (bitconvert:v2i64 VR128:v2f64:$src1), (build_vector:v2i64)<<P:Predicate_immAllOnesV>>))
- // Emits: (ANDNPDrm:v2i64 VR128:v2f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 35 cost = 1 size = 3
- if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N100 = N10.getNode()->getOperand(0);
+ // Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (xor:v2i64 (bitconvert:v2i64 VR128:v4f32:$src1), (bitconvert:v2i64 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>)))
+ // Emits: (ANDNPSrm:v2i64 VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 38 cost = 1 size = 3
+ {
SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N11.getNode()) &&
- N100.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_70(N, X86::ANDNPDrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
+ if (N11.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N110.getNode()) &&
+ N100.getValueType() == MVT::v4f32 &&
+ N110.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_64(N, X86::ANDNPSrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
}
}
- // Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (xor:v2i64 (build_vector:v2i64)<<P:Predicate_immAllOnesV>>, (bitconvert:v2i64 VR128:v2f64:$src1)))
- // Emits: (ANDNPDrm:v2i64 VR128:v2f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 35 cost = 1 size = 3
- if (N10.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N10.getNode())) {
+ // Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (xor:v2i64 (bitconvert:v2i64 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>), (bitconvert:v2i64 VR128:v4f32:$src1)))
+ // Emits: (ANDNPSrm:v2i64 VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 38 cost = 1 size = 3
+ if (N100.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N100.getNode())) {
SDValue N11 = N1.getNode()->getOperand(1);
if (N11.getNode()->getOpcode() == ISD::BIT_CONVERT) {
SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_71(N, X86::ANDNPDrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ if (N100.getValueType() == MVT::v4i32 &&
+ N110.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_65(N, X86::ANDNPSrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -5081,17 +4871,50 @@ SDNode *Select_ISD_AND_v2i64(SDNode *N) {
}
}
}
+ }
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
- // Pattern: (and:v2i64 (xor:v2i64 (bitconvert:v2i64 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>), VR128:v2i64:$src1), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (PANDNrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern: (and:v2i64 (xor:v2i64 (bitconvert:v2i64 VR128:v2f64:$src1), (build_vector:v2i64)<<P:Predicate_immAllOnesV>>), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (ANDNPDrm:v2i64 VR128:v2f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 35 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N000 = N00.getNode()->getOperand(0);
- if (N000.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N000.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
+ if (N00.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N01.getNode())) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
+ N000.getValueType() == MVT::v2f64) {
+ SDNode *Result = Emit_61(N, X86::ANDNPDrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ if (N010.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N010.getNode())) {
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
@@ -5106,60 +4929,29 @@ SDNode *Select_ISD_AND_v2i64(SDNode *N) {
SDValue CPTmpN11_2;
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
- N000.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_54(N, X86::PANDNrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getNode()->getOperand(0);
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- // Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (xor:v2i64 VR128:v2i64:$src1, (bitconvert:v2i64 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>)))
- // Emits: (PANDNrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 35 cost = 1 size = 3
- {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N110.getNode()) &&
- N110.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_55(N, X86::PANDNrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ // Pattern: (and:v2i64 (xor:v2i64 VR128:v2i64:$src1, (bitconvert:v2i64 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>)), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (PANDNrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 35 cost = 1 size = 3
+ if (N010.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_44(N, X86::PANDNrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
- }
- }
- // Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (xor:v2i64 (bitconvert:v2i64 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>), VR128:v2i64:$src1))
- // Emits: (PANDNrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 35 cost = 1 size = 3
- if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N100.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N100.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_56(N, X86::PANDNrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ // Pattern: (and:v2i64 (xor:v2i64 VR128:v2i64:$src1, (bitconvert:v2i64 (build_vector:v8i16)<<P:Predicate_immAllOnesV>>)), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (PANDNrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 35 cost = 1 size = 3
+ if (N010.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_44(N, X86::PANDNrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+
+ // Pattern: (and:v2i64 (xor:v2i64 VR128:v2i64:$src1, (bitconvert:v2i64 (build_vector:v16i8)<<P:Predicate_immAllOnesV>>)), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (PANDNrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 35 cost = 1 size = 3
+ if (N010.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_44(N, X86::PANDNrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -5169,217 +4961,272 @@ SDNode *Select_ISD_AND_v2i64(SDNode *N) {
}
}
- // Pattern: (and:v2i64 (xor:v2i64 (bitconvert:v2i64 (build_vector:v8i16)<<P:Predicate_immAllOnesV>>), VR128:v2i64:$src1), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (PANDNrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern: (and:v2i64 (xor:v2i64 (build_vector:v2i64)<<P:Predicate_immAllOnesV>>, (bitconvert:v2i64 VR128:v2f64:$src1)), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (ANDNPDrm:v2i64 VR128:v2f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 35 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N000 = N00.getNode()->getOperand(0);
- if (N000.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N000.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
- N000.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_54(N, X86::PANDNrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
+ if (N00.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N00.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
+ N010.getValueType() == MVT::v2f64) {
+ SDNode *Result = Emit_69(N, X86::ANDNPDrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
}
}
}
}
}
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getNode()->getOperand(0);
+ }
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getNode()->getOperand(0);
- // Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (xor:v2i64 VR128:v2i64:$src1, (bitconvert:v2i64 (build_vector:v8i16)<<P:Predicate_immAllOnesV>>)))
- // Emits: (PANDNrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 35 cost = 1 size = 3
- {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N110.getNode()) &&
- N110.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_55(N, X86::PANDNrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
+ // Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (xor:v2i64 (bitconvert:v2i64 VR128:v2f64:$src1), (build_vector:v2i64)<<P:Predicate_immAllOnesV>>))
+ // Emits: (ANDNPDrm:v2i64 VR128:v2f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 35 cost = 1 size = 3
+ if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N11.getNode()) &&
+ N100.getValueType() == MVT::v2f64) {
+ SDNode *Result = Emit_70(N, X86::ANDNPDrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
}
+ }
- // Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (xor:v2i64 (bitconvert:v2i64 (build_vector:v8i16)<<P:Predicate_immAllOnesV>>), VR128:v2i64:$src1))
- // Emits: (PANDNrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 35 cost = 1 size = 3
- if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N100.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N100.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_56(N, X86::PANDNrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
+ // Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (xor:v2i64 (build_vector:v2i64)<<P:Predicate_immAllOnesV>>, (bitconvert:v2i64 VR128:v2f64:$src1)))
+ // Emits: (ANDNPDrm:v2i64 VR128:v2f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 35 cost = 1 size = 3
+ if (N10.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N10.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getValueType() == MVT::v2f64) {
+ SDNode *Result = Emit_71(N, X86::ANDNPDrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
}
}
}
}
}
}
+ }
- // Pattern: (and:v2i64 (xor:v2i64 (bitconvert:v2i64 (build_vector:v16i8)<<P:Predicate_immAllOnesV>>), VR128:v2i64:$src1), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (PANDNrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 35 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N000 = N00.getNode()->getOperand(0);
- if (N000.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N000.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
- N000.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_54(N, X86::PANDNrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
+ // Pattern: (and:v2i64 (xor:v2i64 (bitconvert:v2i64 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>), VR128:v2i64:$src1), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (PANDNrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 35 cost = 1 size = 3
+ if (N0.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ if (N000.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N000.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
+ N000.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_54(N, X86::PANDNrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
}
}
}
}
}
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getNode()->getOperand(0);
+ }
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getNode()->getOperand(0);
- // Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (xor:v2i64 VR128:v2i64:$src1, (bitconvert:v2i64 (build_vector:v16i8)<<P:Predicate_immAllOnesV>>)))
- // Emits: (PANDNrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 35 cost = 1 size = 3
- {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N110.getNode()) &&
- N110.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_55(N, X86::PANDNrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
+ // Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (xor:v2i64 VR128:v2i64:$src1, (bitconvert:v2i64 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>)))
+ // Emits: (PANDNrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 35 cost = 1 size = 3
+ {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N110.getNode()) &&
+ N110.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_55(N, X86::PANDNrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
}
}
+ }
- // Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (xor:v2i64 (bitconvert:v2i64 (build_vector:v16i8)<<P:Predicate_immAllOnesV>>), VR128:v2i64:$src1))
- // Emits: (PANDNrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 35 cost = 1 size = 3
- if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N100.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N100.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_56(N, X86::PANDNrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
+ // Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (xor:v2i64 (bitconvert:v2i64 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>), VR128:v2i64:$src1))
+ // Emits: (PANDNrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 35 cost = 1 size = 3
+ if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N100.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N100.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_56(N, X86::PANDNrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
}
}
}
}
}
}
- if (N0.getNode()->getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getNode()->getOperand(0);
+ }
- // Pattern: (and:v2i64 (xor:v2i64 VR128:v2i64:$src1, (build_vector:v2i64)<<P:Predicate_immAllOnesV>>), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (PANDNrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 32 cost = 1 size = 3
- {
+ // Pattern: (and:v2i64 (xor:v2i64 (bitconvert:v2i64 (build_vector:v8i16)<<P:Predicate_immAllOnesV>>), VR128:v2i64:$src1), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (PANDNrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 35 cost = 1 size = 3
+ if (N0.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ if (N000.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N000.getNode())) {
SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N01.getNode())) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
+ N000.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_54(N, X86::PANDNrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+
+ // Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (xor:v2i64 VR128:v2i64:$src1, (bitconvert:v2i64 (build_vector:v8i16)<<P:Predicate_immAllOnesV>>)))
+ // Emits: (PANDNrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 35 cost = 1 size = 3
+ {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N110.getNode()) &&
+ N110.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_55(N, X86::PANDNrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (xor:v2i64 (bitconvert:v2i64 (build_vector:v8i16)<<P:Predicate_immAllOnesV>>), VR128:v2i64:$src1))
+ // Emits: (PANDNrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 35 cost = 1 size = 3
+ if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N100.getNode())) {
SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_42(N, X86::PANDNrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ if (N100.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_56(N, X86::PANDNrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
}
}
}
+ }
+ }
- // Pattern: (and:v2i64 (xor:v2i64 (build_vector:v2i64)<<P:Predicate_immAllOnesV>>, VR128:v2i64:$src1), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (PANDNrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 32 cost = 1 size = 3
- if (N00.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N00.getNode())) {
+ // Pattern: (and:v2i64 (xor:v2i64 (bitconvert:v2i64 (build_vector:v16i8)<<P:Predicate_immAllOnesV>>), VR128:v2i64:$src1), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (PANDNrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 35 cost = 1 size = 3
+ if (N0.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ if (N000.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N000.getNode())) {
SDValue N01 = N0.getNode()->getOperand(1);
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::LOAD &&
@@ -5395,96 +5242,107 @@ SDNode *Select_ISD_AND_v2i64(SDNode *N) {
SDValue CPTmpN11_2;
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_48(N, X86::PANDNrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
+ N000.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_54(N, X86::PANDNrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
}
}
}
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getNode()->getOperand(0);
+ }
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getNode()->getOperand(0);
- // Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (xor:v2i64 VR128:v2i64:$src1, (build_vector:v2i64)<<P:Predicate_immAllOnesV>>))
- // Emits: (PANDNrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 32 cost = 1 size = 3
- {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N11.getNode())) {
- SDNode *Result = Emit_49(N, X86::PANDNrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ // Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (xor:v2i64 VR128:v2i64:$src1, (bitconvert:v2i64 (build_vector:v16i8)<<P:Predicate_immAllOnesV>>)))
+ // Emits: (PANDNrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 35 cost = 1 size = 3
+ {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N110.getNode()) &&
+ N110.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_55(N, X86::PANDNrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
+ }
- // Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (xor:v2i64 (build_vector:v2i64)<<P:Predicate_immAllOnesV>>, VR128:v2i64:$src1))
- // Emits: (PANDNrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 32 cost = 1 size = 3
- if (N10.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllOnesV(N10.getNode())) {
- SDNode *Result = Emit_50(N, X86::PANDNrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
+ // Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (xor:v2i64 (bitconvert:v2i64 (build_vector:v16i8)<<P:Predicate_immAllOnesV>>), VR128:v2i64:$src1))
+ // Emits: (PANDNrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 35 cost = 1 size = 3
+ if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N100.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N100.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_56(N, X86::PANDNrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
}
}
}
}
}
}
+ if (N0.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
- // Pattern: (and:v2i64 (bitconvert:v2i64 VR128:v4f32:$src1), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (ANDPSrm:v2i64 VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
- N00.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_57(N, X86::ANDPSrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
+ // Pattern: (and:v2i64 (xor:v2i64 VR128:v2i64:$src1, (build_vector:v2i64)<<P:Predicate_immAllOnesV>>), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (PANDNrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 32 cost = 1 size = 3
+ {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N01.getNode())) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_42(N, X86::PANDNrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
}
}
}
}
- }
- // Pattern: (and:v2i64 (bitconvert:v2i64 VR128:v2f64:$src1), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (ANDPDrm:v2i64 VR128:v2f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N00 = N0.getNode()->getOperand(0);
+ // Pattern: (and:v2i64 (xor:v2i64 (build_vector:v2i64)<<P:Predicate_immAllOnesV>>, VR128:v2i64:$src1), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (PANDNrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 32 cost = 1 size = 3
+ if (N00.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N00.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
@@ -5499,131 +5357,231 @@ SDNode *Select_ISD_AND_v2i64(SDNode *N) {
SDValue CPTmpN11_2;
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
- N00.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_57(N, X86::ANDPDrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_48(N, X86::PANDNrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
}
}
}
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getNode()->getOperand(0);
- // Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (bitconvert:v2i64 VR128:v4f32:$src1))
- // Emits: (ANDPSrm:v2i64 VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_62(N, X86::ANDPSrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ // Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (xor:v2i64 VR128:v2i64:$src1, (build_vector:v2i64)<<P:Predicate_immAllOnesV>>))
+ // Emits: (PANDNrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 32 cost = 1 size = 3
+ {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N11.getNode())) {
+ SDNode *Result = Emit_49(N, X86::PANDNrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
+
+ // Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (xor:v2i64 (build_vector:v2i64)<<P:Predicate_immAllOnesV>>, VR128:v2i64:$src1))
+ // Emits: (PANDNrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 32 cost = 1 size = 3
+ if (N10.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllOnesV(N10.getNode())) {
+ SDNode *Result = Emit_50(N, X86::PANDNrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
}
}
}
}
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
+ }
- // Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (bitconvert:v2i64 VR128:v2f64:$src1))
- // Emits: (ANDPDrm:v2i64 VR128:v2f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_62(N, X86::ANDPDrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
+ // Pattern: (and:v2i64 (bitconvert:v2i64 VR128:v4f32:$src1), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (ANDPSrm:v2i64 VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
+ N00.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_57(N, X86::ANDPSrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (and:v2i64 (bitconvert:v2i64 VR128:v2f64:$src1), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (ANDPDrm:v2i64 VR128:v2f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
+ N00.getValueType() == MVT::v2f64) {
+ SDNode *Result = Emit_57(N, X86::ANDPDrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (bitconvert:v2i64 VR128:v4f32:$src1))
+ // Emits: (ANDPSrm:v2i64 VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_62(N, X86::ANDPSrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
}
}
}
}
+ }
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N->getOperand(0);
- // Pattern: (and:v2i64 VR128:v2i64:$src1, (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (PANDrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::PANDrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ // Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (bitconvert:v2i64 VR128:v2f64:$src1))
+ // Emits: (ANDPDrm:v2i64 VR128:v2f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getValueType() == MVT::v2f64) {
+ SDNode *Result = Emit_62(N, X86::ANDPDrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
}
}
+ }
- // Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, VR128:v2i64:$src1)
- // Emits: (PANDrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_19(N, X86::PANDrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ // Pattern: (and:v2i64 VR128:v2i64:$src1, (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (PANDrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::PANDrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
}
}
- }
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
+
+ // Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, VR128:v2i64:$src1)
+ // Emits: (PANDrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_19(N, X86::PANDrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
if (N0.getNode()->getOpcode() == ISD::XOR) {
SDValue N00 = N0.getNode()->getOperand(0);
@@ -6157,7 +6115,7 @@ SDNode *Select_ISD_ANY_EXTEND_i32(SDNode *N) {
if (CN1 == INT64_C(8) &&
N0.getValueType() == MVT::i16 &&
N01.getValueType() == MVT::i8) {
- SDNode *Result = Emit_74(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX32rr8, MVT::i16, MVT::i8, MVT::i32);
+ SDNode *Result = Emit_74(N, TargetOpcode::COPY_TO_REGCLASS, TargetOpcode::EXTRACT_SUBREG, X86::MOVZX32rr8, MVT::i16, MVT::i8, MVT::i32);
return Result;
}
}
@@ -6179,7 +6137,7 @@ SDNode *Select_ISD_ANY_EXTEND_i32(SDNode *N) {
if (CN1 == INT64_C(8) &&
N0.getValueType() == MVT::i16 &&
N01.getValueType() == MVT::i8) {
- SDNode *Result = Emit_74(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX32_NOREXrr8, MVT::i16, MVT::i8, MVT::i32);
+ SDNode *Result = Emit_74(N, TargetOpcode::COPY_TO_REGCLASS, TargetOpcode::EXTRACT_SUBREG, X86::MOVZX32_NOREXrr8, MVT::i16, MVT::i8, MVT::i32);
return Result;
}
}
@@ -6260,7 +6218,7 @@ SDNode *Select_ISD_ANY_EXTEND_i64(SDNode *N) {
if (CN1 == INT64_C(8) &&
N0.getValueType() == MVT::i16 &&
N01.getValueType() == MVT::i8) {
- SDNode *Result = Emit_76(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX32_NOREXrr8, TargetInstrInfo::SUBREG_TO_REG, MVT::i16, MVT::i8, MVT::i32, MVT::i64);
+ SDNode *Result = Emit_76(N, TargetOpcode::COPY_TO_REGCLASS, TargetOpcode::EXTRACT_SUBREG, X86::MOVZX32_NOREXrr8, TargetOpcode::SUBREG_TO_REG, MVT::i16, MVT::i8, MVT::i32, MVT::i64);
return Result;
}
}
@@ -6288,7 +6246,7 @@ SDNode *Select_ISD_ANY_EXTEND_i64(SDNode *N) {
// Emits: (SUBREG_TO_REG:i64 0:i64, GR32:i32:$src, 4:i32)
// Pattern complexity = 3 cost = 1 size = 0
if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_75(N, TargetInstrInfo::SUBREG_TO_REG, MVT::i64);
+ SDNode *Result = Emit_75(N, TargetOpcode::SUBREG_TO_REG, MVT::i64);
return Result;
}
@@ -7102,13 +7060,12 @@ DISABLE_INLINE SDNode *Emit_79(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT
return ResNode;
}
SDNode *Select_ISD_BIT_CONVERT_f32(SDNode *N) {
-
- // Pattern: (bitconvert:f32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
- // Emits: (MOVDI2SSrm:f32 addr:iPTR:$src)
- // Pattern complexity = 25 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSE2())) {
+ if ((Subtarget->hasSSE2())) {
SDValue N0 = N->getOperand(0);
+
+ // Pattern: (bitconvert:f32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
+ // Emits: (MOVDI2SSrm:f32 addr:iPTR:$src)
+ // Pattern complexity = 25 cost = 1 size = 3
if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse()) {
SDValue Chain0 = N0.getNode()->getOperand(0);
@@ -7127,13 +7084,10 @@ SDNode *Select_ISD_BIT_CONVERT_f32(SDNode *N) {
}
}
}
- }
- // Pattern: (bitconvert:f32 GR32:i32:$src)
- // Emits: (MOVDI2SSrr:f32 GR32:i32:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
+ // Pattern: (bitconvert:f32 GR32:i32:$src)
+ // Emits: (MOVDI2SSrr:f32 GR32:i32:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
if (N0.getValueType() == MVT::i32) {
SDNode *Result = Emit_72(N, X86::MOVDI2SSrr, MVT::f32);
return Result;
@@ -7145,13 +7099,12 @@ SDNode *Select_ISD_BIT_CONVERT_f32(SDNode *N) {
}
SDNode *Select_ISD_BIT_CONVERT_f64(SDNode *N) {
-
- // Pattern: (bitconvert:f64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
- // Emits: (MOV64toSDrm:f64 addr:iPTR:$src)
- // Pattern complexity = 25 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSE2())) {
+ if ((Subtarget->hasSSE2())) {
SDValue N0 = N->getOperand(0);
+
+ // Pattern: (bitconvert:f64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
+ // Emits: (MOV64toSDrm:f64 addr:iPTR:$src)
+ // Pattern complexity = 25 cost = 1 size = 3
if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse()) {
SDValue Chain0 = N0.getNode()->getOperand(0);
@@ -7171,13 +7124,10 @@ SDNode *Select_ISD_BIT_CONVERT_f64(SDNode *N) {
}
}
}
- }
- // Pattern: (bitconvert:f64 GR64:i64:$src)
- // Emits: (MOV64toSDrr:f64 GR64:i64:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
+ // Pattern: (bitconvert:f64 GR64:i64:$src)
+ // Emits: (MOV64toSDrr:f64 GR64:i64:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
if (N0.getValueType() == MVT::i64) {
SDNode *Result = Emit_72(N, X86::MOV64toSDrr, MVT::f64);
return Result;
@@ -7475,47 +7425,44 @@ DISABLE_INLINE SDNode *Emit_82(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT
return ResNode;
}
SDNode *Select_ISD_BIT_CONVERT_v2i32(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
// Pattern: (bitconvert:v2i32 (vector_shuffle:v2i32 (build_vector:v2i32)<<P:Predicate_immAllZerosV>>, (scalar_to_vector:v2i32 (ld:v1i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>))<<P:Predicate_mmx_unpckl>>)
// Emits: (MMX_PUNPCKLDQrm:v2i32 VR64:v8i8:$src, VR64:v8i8:$src)
// Pattern complexity = 56 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::VECTOR_SHUFFLE &&
- N0.hasOneUse() &&
- Predicate_mmx_unpckl(N0.getNode())) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
- Predicate_immAllZerosV(N00.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N01.hasOneUse()) {
- SDValue N010 = N01.getNode()->getOperand(0);
- if (N010.getNode()->getOpcode() == ISD::LOAD &&
- N010.hasOneUse() &&
- IsLegalAndProfitableToFold(N010.getNode(), N01.getNode(), N)) {
- SDValue Chain010 = N010.getNode()->getOperand(0);
- if (Predicate_unindexedload(N010.getNode()) &&
- Predicate_load(N010.getNode())) {
- SDValue N0101 = N010.getNode()->getOperand(1);
- SDValue CPTmpN0101_0;
- SDValue CPTmpN0101_1;
- SDValue CPTmpN0101_2;
- SDValue CPTmpN0101_3;
- SDValue CPTmpN0101_4;
- if (SelectAddr(N, N0101, CPTmpN0101_0, CPTmpN0101_1, CPTmpN0101_2, CPTmpN0101_3, CPTmpN0101_4) &&
- N0.getValueType() == MVT::v2i32 &&
- N010.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_82(N, X86::MMX_PUNPCKLDQrm, MVT::v2i32, CPTmpN0101_0, CPTmpN0101_1, CPTmpN0101_2, CPTmpN0101_3, CPTmpN0101_4);
- return Result;
- }
+ if (N0.getNode()->getOpcode() == ISD::VECTOR_SHUFFLE &&
+ N0.hasOneUse() &&
+ Predicate_mmx_unpckl(N0.getNode())) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
+ Predicate_immAllZerosV(N00.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N01.hasOneUse()) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ if (N010.getNode()->getOpcode() == ISD::LOAD &&
+ N010.hasOneUse() &&
+ IsLegalAndProfitableToFold(N010.getNode(), N01.getNode(), N)) {
+ SDValue Chain010 = N010.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N010.getNode()) &&
+ Predicate_load(N010.getNode())) {
+ SDValue N0101 = N010.getNode()->getOperand(1);
+ SDValue CPTmpN0101_0;
+ SDValue CPTmpN0101_1;
+ SDValue CPTmpN0101_2;
+ SDValue CPTmpN0101_3;
+ SDValue CPTmpN0101_4;
+ if (SelectAddr(N, N0101, CPTmpN0101_0, CPTmpN0101_1, CPTmpN0101_2, CPTmpN0101_3, CPTmpN0101_4) &&
+ N0.getValueType() == MVT::v2i32 &&
+ N010.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_82(N, X86::MMX_PUNPCKLDQrm, MVT::v2i32, CPTmpN0101_0, CPTmpN0101_1, CPTmpN0101_2, CPTmpN0101_3, CPTmpN0101_4);
+ return Result;
}
}
}
}
}
}
- SDValue N0 = N->getOperand(0);
// Pattern: (bitconvert:v2i32 (vector_extract:i64 VR128:v2i64:$src, 0:iPTR))
// Emits: (MMX_MOVDQ2Qrr:v2i32 VR128:v16i8:$src)
@@ -7899,7 +7846,7 @@ SDNode *Select_ISD_BR(SDNode *N) {
SDValue Chain = N->getOperand(0);
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::BasicBlock) {
- SDNode *Result = Emit_83(N, X86::JMP);
+ SDNode *Result = Emit_83(N, X86::JMP_4);
return Result;
}
@@ -8695,110 +8642,110 @@ DISABLE_INLINE SDNode *Emit_97(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT
return ResNode;
}
SDNode *Select_ISD_FADD_f32(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
- if ((!Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
+ if ((!Subtarget->hasSSE1())) {
+ SDValue N0 = N->getOperand(0);
- // Pattern: (fadd:f32 RFP32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>)
- // Emits: (ADD_Fp32m:f32 RFP32:f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_loadf32(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::ADD_Fp32m, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
+ // Pattern: (fadd:f32 RFP32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>)
+ // Emits: (ADD_Fp32m:f32 RFP32:f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 0
+ {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_loadf32(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::ADD_Fp32m, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
}
}
}
+ }
- // Pattern: (fadd:f32 (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>, RFP32:f32:$src1)
- // Emits: (ADD_Fp32m:f32 RFP32:f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_loadf32(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_19(N, X86::ADD_Fp32m, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
+ // Pattern: (fadd:f32 (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>, RFP32:f32:$src1)
+ // Emits: (ADD_Fp32m:f32 RFP32:f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 0
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_loadf32(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_19(N, X86::ADD_Fp32m, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
}
}
}
- if ((Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
+ }
+ if ((Subtarget->hasSSE1())) {
+ SDValue N0 = N->getOperand(0);
- // Pattern: (fadd:f32 FR32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (ADDSSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::ADDSSrm, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
+ // Pattern: (fadd:f32 FR32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (ADDSSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::ADDSSrm, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
}
}
}
+ }
- // Pattern: (fadd:f32 (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, FR32:f32:$src1)
- // Emits: (ADDSSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_19(N, X86::ADDSSrm, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
+ // Pattern: (fadd:f32 (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, FR32:f32:$src1)
+ // Emits: (ADDSSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_19(N, X86::ADDSSrm, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
}
}
}
- if ((!Subtarget->hasSSE1())) {
+ }
+ if ((!Subtarget->hasSSE1())) {
+ {
SDValue N0 = N->getOperand(0);
{
SDValue N1 = N->getOperand(1);
@@ -8864,12 +8811,10 @@ SDNode *Select_ISD_FADD_f32(SDNode *N) {
}
}
}
- }
- // Pattern: (fadd:f32 RFP32:f32:$src1, RFP32:f32:$src2)
- // Emits: (ADD_Fp32:f32 RFP32:f32:$src1, RFP32:f32:$src2)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((!Subtarget->hasSSE1())) {
+ // Pattern: (fadd:f32 RFP32:f32:$src1, RFP32:f32:$src2)
+ // Emits: (ADD_Fp32:f32 RFP32:f32:$src1, RFP32:f32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 0
SDNode *Result = Emit_15(N, X86::ADD_Fp32, MVT::f32);
return Result;
}
@@ -8887,109 +8832,38 @@ SDNode *Select_ISD_FADD_f32(SDNode *N) {
}
SDNode *Select_ISD_FADD_f64(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
- if ((!Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode())) {
-
- // Pattern: (fadd:f64 RFP64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>)
- // Emits: (ADD_Fp64m:f64 RFP64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 0
- if (Predicate_load(N1.getNode()) &&
- Predicate_loadf64(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::ADD_Fp64m, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
-
- // Pattern: (fadd:f64 RFP64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf32>>)
- // Emits: (ADD_Fp64m32:f64 RFP64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 0
- if (Predicate_extload(N1.getNode()) &&
- Predicate_extloadf32(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::ADD_Fp64m32, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode())) {
+ if ((!Subtarget->hasSSE2())) {
+ SDValue N0 = N->getOperand(0);
+ {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode())) {
- // Pattern: (fadd:f64 (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>, RFP64:f64:$src1)
+ // Pattern: (fadd:f64 RFP64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>)
// Emits: (ADD_Fp64m:f64 RFP64:f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 0
- if (Predicate_load(N0.getNode()) &&
- Predicate_loadf64(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_19(N, X86::ADD_Fp64m, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ if (Predicate_load(N1.getNode()) &&
+ Predicate_loadf64(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::ADD_Fp64m, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
- // Pattern: (fadd:f64 (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf32>>, RFP64:f64:$src1)
+ // Pattern: (fadd:f64 RFP64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf32>>)
// Emits: (ADD_Fp64m32:f64 RFP64:f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 0
- if (Predicate_extload(N0.getNode()) &&
- Predicate_extloadf32(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_19(N, X86::ADD_Fp64m32, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (fadd:f64 FR64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (ADDSDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
+ if (Predicate_extload(N1.getNode()) &&
+ Predicate_extloadf32(N1.getNode())) {
SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
@@ -8997,22 +8871,41 @@ SDNode *Select_ISD_FADD_f64(SDNode *N) {
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::ADDSDrm, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_18(N, X86::ADD_Fp64m32, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
}
}
+ }
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode())) {
- // Pattern: (fadd:f64 (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, FR64:f64:$src1)
- // Emits: (ADDSDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode())) {
+ // Pattern: (fadd:f64 (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>, RFP64:f64:$src1)
+ // Emits: (ADD_Fp64m:f64 RFP64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 0
+ if (Predicate_load(N0.getNode()) &&
+ Predicate_loadf64(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_19(N, X86::ADD_Fp64m, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (fadd:f64 (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf32>>, RFP64:f64:$src1)
+ // Emits: (ADD_Fp64m32:f64 RFP64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 0
+ if (Predicate_extload(N0.getNode()) &&
+ Predicate_extloadf32(N0.getNode())) {
SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
@@ -9020,13 +8913,65 @@ SDNode *Select_ISD_FADD_f64(SDNode *N) {
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_19(N, X86::ADDSDrm, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_19(N, X86::ADD_Fp64m32, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
}
}
- if ((!Subtarget->hasSSE2())) {
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N->getOperand(0);
+
+ // Pattern: (fadd:f64 FR64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (ADDSDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::ADDSDrm, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (fadd:f64 (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, FR64:f64:$src1)
+ // Emits: (ADDSDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_19(N, X86::ADDSDrm, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ if ((!Subtarget->hasSSE2())) {
+ {
SDValue N0 = N->getOperand(0);
{
SDValue N1 = N->getOperand(1);
@@ -9092,12 +9037,10 @@ SDNode *Select_ISD_FADD_f64(SDNode *N) {
}
}
}
- }
- // Pattern: (fadd:f64 RFP64:f64:$src1, RFP64:f64:$src2)
- // Emits: (ADD_Fp64:f64 RFP64:f64:$src1, RFP64:f64:$src2)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((!Subtarget->hasSSE2())) {
+ // Pattern: (fadd:f64 RFP64:f64:$src1, RFP64:f64:$src2)
+ // Emits: (ADD_Fp64:f64 RFP64:f64:$src1, RFP64:f64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 0
SDNode *Result = Emit_15(N, X86::ADD_Fp64, MVT::f64);
return Result;
}
@@ -9115,7 +9058,7 @@ SDNode *Select_ISD_FADD_f64(SDNode *N) {
}
SDNode *Select_ISD_FADD_f80(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
{
SDValue N1 = N->getOperand(1);
@@ -9273,64 +9216,63 @@ SDNode *Select_ISD_FADD_f80(SDNode *N) {
}
SDNode *Select_ISD_FADD_v4f32(SDNode *N) {
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (fadd:v4f32 VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (ADDPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
{
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::ADDPSrm, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
+ SDValue N0 = N->getOperand(0);
+
+ // Pattern: (fadd:v4f32 VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (ADDPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::ADDPSrm, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
}
}
}
- }
- // Pattern: (fadd:v4f32 (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, VR128:v4f32:$src1)
- // Emits: (ADDPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_19(N, X86::ADDPSrm, MVT::v4f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
+ // Pattern: (fadd:v4f32 (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, VR128:v4f32:$src1)
+ // Emits: (ADDPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_19(N, X86::ADDPSrm, MVT::v4f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
}
}
}
- }
- // Pattern: (fadd:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
- // Emits: (ADDPSrr:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
+ // Pattern: (fadd:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Emits: (ADDPSrr:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
SDNode *Result = Emit_15(N, X86::ADDPSrr, MVT::v4f32);
return Result;
}
@@ -9340,64 +9282,63 @@ SDNode *Select_ISD_FADD_v4f32(SDNode *N) {
}
SDNode *Select_ISD_FADD_v2f64(SDNode *N) {
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (fadd:v2f64 VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (ADDPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
{
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::ADDPDrm, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
+ SDValue N0 = N->getOperand(0);
+
+ // Pattern: (fadd:v2f64 VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (ADDPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::ADDPDrm, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
}
}
}
- }
- // Pattern: (fadd:v2f64 (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, VR128:v2f64:$src1)
- // Emits: (ADDPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_19(N, X86::ADDPDrm, MVT::v2f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
+ // Pattern: (fadd:v2f64 (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, VR128:v2f64:$src1)
+ // Emits: (ADDPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_19(N, X86::ADDPDrm, MVT::v2f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
}
}
}
- }
- // Pattern: (fadd:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
- // Emits: (ADDPDrr:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
+ // Pattern: (fadd:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Emits: (ADDPDrr:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
SDNode *Result = Emit_15(N, X86::ADDPDrr, MVT::v2f64);
return Result;
}
@@ -9432,69 +9373,69 @@ SDNode *Select_ISD_FCOS_f80(SDNode *N) {
}
SDNode *Select_ISD_FDIV_f32(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
- if ((!Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_loadf32(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
-
- // Pattern: (fdiv:f32 RFP32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>)
- // Emits: (DIV_Fp32m:f32 RFP32:f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 0
- {
- SDNode *Result = Emit_18(N, X86::DIV_Fp32m, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
+ if ((!Subtarget->hasSSE1())) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_loadf32(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- // Pattern: (fdiv:f32 RFP32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>)
- // Emits: (DIVR_Fp32m:f32 RFP32:f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 0
- SDNode *Result = Emit_18(N, X86::DIVR_Fp32m, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ // Pattern: (fdiv:f32 RFP32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>)
+ // Emits: (DIV_Fp32m:f32 RFP32:f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 0
+ {
+ SDNode *Result = Emit_18(N, X86::DIV_Fp32m, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
+
+ // Pattern: (fdiv:f32 RFP32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>)
+ // Emits: (DIVR_Fp32m:f32 RFP32:f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 0
+ SDNode *Result = Emit_18(N, X86::DIVR_Fp32m, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
}
}
}
+ }
- // Pattern: (fdiv:f32 FR32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (DIVSSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::DIVSSrm, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
+ // Pattern: (fdiv:f32 FR32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (DIVSSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::DIVSSrm, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
}
}
}
- if ((!Subtarget->hasSSE1())) {
+ }
+ if ((!Subtarget->hasSSE1())) {
+ {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == X86ISD::FILD &&
@@ -9544,12 +9485,10 @@ SDNode *Select_ISD_FDIV_f32(SDNode *N) {
}
}
}
- }
- // Pattern: (fdiv:f32 RFP32:f32:$src1, RFP32:f32:$src2)
- // Emits: (DIV_Fp32:f32 RFP32:f32:$src1, RFP32:f32:$src2)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((!Subtarget->hasSSE1())) {
+ // Pattern: (fdiv:f32 RFP32:f32:$src1, RFP32:f32:$src2)
+ // Emits: (DIV_Fp32:f32 RFP32:f32:$src1, RFP32:f32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 0
SDNode *Result = Emit_15(N, X86::DIV_Fp32, MVT::f32);
return Result;
}
@@ -9567,99 +9506,71 @@ SDNode *Select_ISD_FDIV_f32(SDNode *N) {
}
SDNode *Select_ISD_FDIV_f64(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
- if ((!Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode())) {
-
- // Pattern: (fdiv:f64 RFP64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>)
- // Emits: (DIV_Fp64m:f64 RFP64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 0
- if (Predicate_load(N1.getNode()) &&
- Predicate_loadf64(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::DIV_Fp64m, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
+ if ((!Subtarget->hasSSE2())) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode())) {
- // Pattern: (fdiv:f64 RFP64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf32>>)
- // Emits: (DIV_Fp64m32:f64 RFP64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 0
- if (Predicate_extload(N1.getNode()) &&
- Predicate_extloadf32(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::DIV_Fp64m32, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
+ // Pattern: (fdiv:f64 RFP64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>)
+ // Emits: (DIV_Fp64m:f64 RFP64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 0
+ if (Predicate_load(N1.getNode()) &&
+ Predicate_loadf64(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::DIV_Fp64m, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
}
+ }
- // Pattern: (fdiv:f64 RFP64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>)
- // Emits: (DIVR_Fp64m:f64 RFP64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 0
- if (Predicate_load(N1.getNode()) &&
- Predicate_loadf64(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::DIVR_Fp64m, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
+ // Pattern: (fdiv:f64 RFP64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf32>>)
+ // Emits: (DIV_Fp64m32:f64 RFP64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 0
+ if (Predicate_extload(N1.getNode()) &&
+ Predicate_extloadf32(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::DIV_Fp64m32, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
}
+ }
- // Pattern: (fdiv:f64 RFP64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf32>>)
- // Emits: (DIVR_Fp64m32:f64 RFP64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 0
- if (Predicate_extload(N1.getNode()) &&
- Predicate_extloadf32(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::DIVR_Fp64m32, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
+ // Pattern: (fdiv:f64 RFP64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>)
+ // Emits: (DIVR_Fp64m:f64 RFP64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 0
+ if (Predicate_load(N1.getNode()) &&
+ Predicate_loadf64(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::DIVR_Fp64m, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
}
}
- }
- }
- // Pattern: (fdiv:f64 FR64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (DIVSDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
+ // Pattern: (fdiv:f64 RFP64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf32>>)
+ // Emits: (DIVR_Fp64m32:f64 RFP64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 0
+ if (Predicate_extload(N1.getNode()) &&
+ Predicate_extloadf32(N1.getNode())) {
SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
@@ -9667,13 +9578,41 @@ SDNode *Select_ISD_FDIV_f64(SDNode *N) {
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::DIVSDrm, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_18(N, X86::DIVR_Fp64m32, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
}
}
- if ((!Subtarget->hasSSE2())) {
+ }
+
+ // Pattern: (fdiv:f64 FR64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (DIVSDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::DIVSDrm, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ if ((!Subtarget->hasSSE2())) {
+ {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == X86ISD::FILD &&
@@ -9723,12 +9662,10 @@ SDNode *Select_ISD_FDIV_f64(SDNode *N) {
}
}
}
- }
- // Pattern: (fdiv:f64 RFP64:f64:$src1, RFP64:f64:$src2)
- // Emits: (DIV_Fp64:f64 RFP64:f64:$src1, RFP64:f64:$src2)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((!Subtarget->hasSSE2())) {
+ // Pattern: (fdiv:f64 RFP64:f64:$src1, RFP64:f64:$src2)
+ // Emits: (DIV_Fp64:f64 RFP64:f64:$src1, RFP64:f64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 0
SDNode *Result = Emit_15(N, X86::DIV_Fp64, MVT::f64);
return Result;
}
@@ -9746,7 +9683,7 @@ SDNode *Select_ISD_FDIV_f64(SDNode *N) {
}
SDNode *Select_ISD_FDIV_f80(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::LOAD &&
@@ -9877,39 +9814,38 @@ SDNode *Select_ISD_FDIV_f80(SDNode *N) {
}
SDNode *Select_ISD_FDIV_v4f32(SDNode *N) {
+ if ((Subtarget->hasSSE1())) {
- // Pattern: (fdiv:v4f32 VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (DIVPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::DIVPSrm, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
+ // Pattern: (fdiv:v4f32 VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (DIVPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::DIVPSrm, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
}
}
}
- }
- // Pattern: (fdiv:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
- // Emits: (DIVPSrr:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
+ // Pattern: (fdiv:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Emits: (DIVPSrr:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
SDNode *Result = Emit_15(N, X86::DIVPSrr, MVT::v4f32);
return Result;
}
@@ -9919,39 +9855,38 @@ SDNode *Select_ISD_FDIV_v4f32(SDNode *N) {
}
SDNode *Select_ISD_FDIV_v2f64(SDNode *N) {
+ if ((Subtarget->hasSSE2())) {
- // Pattern: (fdiv:v2f64 VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (DIVPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::DIVPDrm, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
+ // Pattern: (fdiv:v2f64 VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (DIVPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::DIVPDrm, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
}
}
}
- }
- // Pattern: (fdiv:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
- // Emits: (DIVPDrr:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
+ // Pattern: (fdiv:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Emits: (DIVPDrr:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
SDNode *Result = Emit_15(N, X86::DIVPDrr, MVT::v2f64);
return Result;
}
@@ -9961,110 +9896,110 @@ SDNode *Select_ISD_FDIV_v2f64(SDNode *N) {
}
SDNode *Select_ISD_FMUL_f32(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
- if ((!Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
+ if ((!Subtarget->hasSSE1())) {
+ SDValue N0 = N->getOperand(0);
- // Pattern: (fmul:f32 RFP32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>)
- // Emits: (MUL_Fp32m:f32 RFP32:f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 0
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_loadf32(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::MUL_Fp32m, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
+ // Pattern: (fmul:f32 RFP32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>)
+ // Emits: (MUL_Fp32m:f32 RFP32:f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 0
+ {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_loadf32(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::MUL_Fp32m, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
}
}
}
+ }
- // Pattern: (fmul:f32 (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>, RFP32:f32:$src1)
- // Emits: (MUL_Fp32m:f32 RFP32:f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 0
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_loadf32(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_19(N, X86::MUL_Fp32m, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
+ // Pattern: (fmul:f32 (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>, RFP32:f32:$src1)
+ // Emits: (MUL_Fp32m:f32 RFP32:f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 0
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_loadf32(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_19(N, X86::MUL_Fp32m, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
}
}
}
- if ((Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
+ }
+ if ((Subtarget->hasSSE1())) {
+ SDValue N0 = N->getOperand(0);
- // Pattern: (fmul:f32 FR32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (MULSSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::MULSSrm, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
+ // Pattern: (fmul:f32 FR32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (MULSSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::MULSSrm, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
}
}
}
+ }
- // Pattern: (fmul:f32 (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, FR32:f32:$src1)
- // Emits: (MULSSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_19(N, X86::MULSSrm, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
+ // Pattern: (fmul:f32 (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, FR32:f32:$src1)
+ // Emits: (MULSSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_19(N, X86::MULSSrm, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
}
}
}
- if ((!Subtarget->hasSSE1())) {
+ }
+ if ((!Subtarget->hasSSE1())) {
+ {
SDValue N0 = N->getOperand(0);
{
SDValue N1 = N->getOperand(1);
@@ -10130,12 +10065,10 @@ SDNode *Select_ISD_FMUL_f32(SDNode *N) {
}
}
}
- }
- // Pattern: (fmul:f32 RFP32:f32:$src1, RFP32:f32:$src2)
- // Emits: (MUL_Fp32:f32 RFP32:f32:$src1, RFP32:f32:$src2)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((!Subtarget->hasSSE1())) {
+ // Pattern: (fmul:f32 RFP32:f32:$src1, RFP32:f32:$src2)
+ // Emits: (MUL_Fp32:f32 RFP32:f32:$src1, RFP32:f32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 0
SDNode *Result = Emit_15(N, X86::MUL_Fp32, MVT::f32);
return Result;
}
@@ -10153,109 +10086,38 @@ SDNode *Select_ISD_FMUL_f32(SDNode *N) {
}
SDNode *Select_ISD_FMUL_f64(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
- if ((!Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode())) {
-
- // Pattern: (fmul:f64 RFP64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>)
- // Emits: (MUL_Fp64m:f64 RFP64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 0
- if (Predicate_load(N1.getNode()) &&
- Predicate_loadf64(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::MUL_Fp64m, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
-
- // Pattern: (fmul:f64 RFP64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf32>>)
- // Emits: (MUL_Fp64m32:f64 RFP64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 0
- if (Predicate_extload(N1.getNode()) &&
- Predicate_extloadf32(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::MUL_Fp64m32, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode())) {
+ if ((!Subtarget->hasSSE2())) {
+ SDValue N0 = N->getOperand(0);
+ {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode())) {
- // Pattern: (fmul:f64 (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>, RFP64:f64:$src1)
+ // Pattern: (fmul:f64 RFP64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>)
// Emits: (MUL_Fp64m:f64 RFP64:f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 0
- if (Predicate_load(N0.getNode()) &&
- Predicate_loadf64(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_19(N, X86::MUL_Fp64m, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ if (Predicate_load(N1.getNode()) &&
+ Predicate_loadf64(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::MUL_Fp64m, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
- // Pattern: (fmul:f64 (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf32>>, RFP64:f64:$src1)
+ // Pattern: (fmul:f64 RFP64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf32>>)
// Emits: (MUL_Fp64m32:f64 RFP64:f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 0
- if (Predicate_extload(N0.getNode()) &&
- Predicate_extloadf32(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_19(N, X86::MUL_Fp64m32, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (fmul:f64 FR64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (MULSDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
+ if (Predicate_extload(N1.getNode()) &&
+ Predicate_extloadf32(N1.getNode())) {
SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
@@ -10263,22 +10125,41 @@ SDNode *Select_ISD_FMUL_f64(SDNode *N) {
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::MULSDrm, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_18(N, X86::MUL_Fp64m32, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
}
}
+ }
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode())) {
- // Pattern: (fmul:f64 (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, FR64:f64:$src1)
- // Emits: (MULSDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode())) {
+ // Pattern: (fmul:f64 (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>, RFP64:f64:$src1)
+ // Emits: (MUL_Fp64m:f64 RFP64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 0
+ if (Predicate_load(N0.getNode()) &&
+ Predicate_loadf64(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_19(N, X86::MUL_Fp64m, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (fmul:f64 (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf32>>, RFP64:f64:$src1)
+ // Emits: (MUL_Fp64m32:f64 RFP64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 0
+ if (Predicate_extload(N0.getNode()) &&
+ Predicate_extloadf32(N0.getNode())) {
SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
@@ -10286,13 +10167,65 @@ SDNode *Select_ISD_FMUL_f64(SDNode *N) {
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_19(N, X86::MULSDrm, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_19(N, X86::MUL_Fp64m32, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
}
}
- if ((!Subtarget->hasSSE2())) {
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N->getOperand(0);
+
+ // Pattern: (fmul:f64 FR64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (MULSDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::MULSDrm, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (fmul:f64 (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, FR64:f64:$src1)
+ // Emits: (MULSDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_19(N, X86::MULSDrm, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ if ((!Subtarget->hasSSE2())) {
+ {
SDValue N0 = N->getOperand(0);
{
SDValue N1 = N->getOperand(1);
@@ -10358,12 +10291,10 @@ SDNode *Select_ISD_FMUL_f64(SDNode *N) {
}
}
}
- }
- // Pattern: (fmul:f64 RFP64:f64:$src1, RFP64:f64:$src2)
- // Emits: (MUL_Fp64:f64 RFP64:f64:$src1, RFP64:f64:$src2)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((!Subtarget->hasSSE2())) {
+ // Pattern: (fmul:f64 RFP64:f64:$src1, RFP64:f64:$src2)
+ // Emits: (MUL_Fp64:f64 RFP64:f64:$src1, RFP64:f64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 0
SDNode *Result = Emit_15(N, X86::MUL_Fp64, MVT::f64);
return Result;
}
@@ -10381,7 +10312,7 @@ SDNode *Select_ISD_FMUL_f64(SDNode *N) {
}
SDNode *Select_ISD_FMUL_f80(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
{
SDValue N1 = N->getOperand(1);
@@ -10539,64 +10470,63 @@ SDNode *Select_ISD_FMUL_f80(SDNode *N) {
}
SDNode *Select_ISD_FMUL_v4f32(SDNode *N) {
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (fmul:v4f32 VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (MULPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
{
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::MULPSrm, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
+ SDValue N0 = N->getOperand(0);
+
+ // Pattern: (fmul:v4f32 VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (MULPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::MULPSrm, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
}
}
}
- }
- // Pattern: (fmul:v4f32 (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, VR128:v4f32:$src1)
- // Emits: (MULPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_19(N, X86::MULPSrm, MVT::v4f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
+ // Pattern: (fmul:v4f32 (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, VR128:v4f32:$src1)
+ // Emits: (MULPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_19(N, X86::MULPSrm, MVT::v4f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
}
}
}
- }
- // Pattern: (fmul:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
- // Emits: (MULPSrr:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
+ // Pattern: (fmul:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Emits: (MULPSrr:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
SDNode *Result = Emit_15(N, X86::MULPSrr, MVT::v4f32);
return Result;
}
@@ -10606,64 +10536,63 @@ SDNode *Select_ISD_FMUL_v4f32(SDNode *N) {
}
SDNode *Select_ISD_FMUL_v2f64(SDNode *N) {
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (fmul:v2f64 VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (MULPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
{
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::MULPDrm, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
+ SDValue N0 = N->getOperand(0);
+
+ // Pattern: (fmul:v2f64 VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (MULPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::MULPDrm, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
}
}
}
- }
- // Pattern: (fmul:v2f64 (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, VR128:v2f64:$src1)
- // Emits: (MULPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_19(N, X86::MULPDrm, MVT::v2f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
+ // Pattern: (fmul:v2f64 (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, VR128:v2f64:$src1)
+ // Emits: (MULPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_19(N, X86::MULPDrm, MVT::v2f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
}
}
}
- }
- // Pattern: (fmul:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
- // Emits: (MULPDrr:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
+ // Pattern: (fmul:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Emits: (MULPDrr:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
SDNode *Result = Emit_15(N, X86::MULPDrr, MVT::v2f64);
return Result;
}
@@ -10702,8 +10631,7 @@ SDNode *Select_ISD_FP_EXTEND_f64(SDNode *N) {
// Pattern: (fextend:f64 (ld:f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>)
// Emits: (CVTSS2SDrm:f64 addr:iPTR:$src)
// Pattern complexity = 25 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSE2())) {
+ if ((Subtarget->hasSSE2())) {
SDValue N0 = N->getOperand(0);
if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse()) {
@@ -10785,8 +10713,7 @@ SDNode *Select_ISD_FP_ROUND_f32(SDNode *N) {
// Pattern: (fround:f32 (ld:f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>)
// Emits: (CVTSD2SSrm:f32 addr:iPTR:$src)
// Pattern complexity = 25 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSE2()) && (OptForSize)) {
+ if ((Subtarget->hasSSE2()) && (OptForSize)) {
SDValue N0 = N->getOperand(0);
if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse()) {
@@ -10857,56 +10784,54 @@ SDNode *Select_ISD_FP_ROUND_f64(SDNode *N) {
}
SDNode *Select_ISD_FP_TO_SINT_i32(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
- // Pattern: (fp_to_sint:i32 (ld:f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>)
- // Emits: (CVTTSS2SIrm:i32 addr:iPTR:$src)
- // Pattern complexity = 25 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse()) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_loadf32(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
- N0.getValueType() == MVT::f32) {
- SDNode *Result = Emit_79(N, X86::CVTTSS2SIrm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
+ // Pattern: (fp_to_sint:i32 (ld:f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>)
+ // Emits: (CVTTSS2SIrm:i32 addr:iPTR:$src)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse()) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_loadf32(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
+ N0.getValueType() == MVT::f32) {
+ SDNode *Result = Emit_79(N, X86::CVTTSS2SIrm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
}
}
}
+ }
- // Pattern: (fp_to_sint:i32 (ld:f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>)
- // Emits: (CVTTSD2SIrm:i32 addr:iPTR:$src)
- // Pattern complexity = 25 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse()) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_loadf64(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
- N0.getValueType() == MVT::f64) {
- SDNode *Result = Emit_79(N, X86::CVTTSD2SIrm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
+ // Pattern: (fp_to_sint:i32 (ld:f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>)
+ // Emits: (CVTTSD2SIrm:i32 addr:iPTR:$src)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse()) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_loadf64(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
+ N0.getValueType() == MVT::f64) {
+ SDNode *Result = Emit_79(N, X86::CVTTSD2SIrm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
}
}
}
@@ -10939,56 +10864,54 @@ SDNode *Select_ISD_FP_TO_SINT_i32(SDNode *N) {
}
SDNode *Select_ISD_FP_TO_SINT_i64(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
- // Pattern: (fp_to_sint:i64 (ld:f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>)
- // Emits: (CVTTSD2SI64rm:i64 addr:iPTR:$src)
- // Pattern complexity = 25 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse()) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_loadf64(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
- N0.getValueType() == MVT::f64) {
- SDNode *Result = Emit_79(N, X86::CVTTSD2SI64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
+ // Pattern: (fp_to_sint:i64 (ld:f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>)
+ // Emits: (CVTTSD2SI64rm:i64 addr:iPTR:$src)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse()) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_loadf64(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
+ N0.getValueType() == MVT::f64) {
+ SDNode *Result = Emit_79(N, X86::CVTTSD2SI64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
}
}
}
+ }
- // Pattern: (fp_to_sint:i64 (ld:f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>)
- // Emits: (CVTTSS2SI64rm:i64 addr:iPTR:$src)
- // Pattern complexity = 25 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse()) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_loadf32(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
- N0.getValueType() == MVT::f32) {
- SDNode *Result = Emit_79(N, X86::CVTTSS2SI64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
+ // Pattern: (fp_to_sint:i64 (ld:f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>)
+ // Emits: (CVTTSS2SI64rm:i64 addr:iPTR:$src)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse()) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_loadf32(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
+ N0.getValueType() == MVT::f32) {
+ SDNode *Result = Emit_79(N, X86::CVTTSS2SI64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
}
}
}
@@ -11076,8 +10999,7 @@ SDNode *Select_ISD_FSQRT_f32(SDNode *N) {
// Pattern: (fsqrt:f32 (ld:f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (SQRTSSm:f32 addr:iPTR:$src)
// Pattern complexity = 25 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSE1()) && (OptForSize)) {
+ if ((Subtarget->hasSSE1()) && (OptForSize)) {
SDValue N0 = N->getOperand(0);
if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse()) {
@@ -11123,8 +11045,7 @@ SDNode *Select_ISD_FSQRT_f64(SDNode *N) {
// Pattern: (fsqrt:f64 (ld:f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (SQRTSDm:f64 addr:iPTR:$src)
// Pattern complexity = 25 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSE2())) {
+ if ((Subtarget->hasSSE2())) {
SDValue N0 = N->getOperand(0);
if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse()) {
@@ -11171,37 +11092,36 @@ SDNode *Select_ISD_FSQRT_f80(SDNode *N) {
}
SDNode *Select_ISD_FSQRT_v4f32(SDNode *N) {
+ if ((Subtarget->hasSSE1())) {
- // Pattern: (fsqrt:v4f32 (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (SQRTPSm:v4f32 addr:iPTR:$src)
- // Pattern complexity = 25 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse()) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_79(N, X86::SQRTPSm, MVT::v4f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
+ // Pattern: (fsqrt:v4f32 (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (SQRTPSm:v4f32 addr:iPTR:$src)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse()) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_79(N, X86::SQRTPSm, MVT::v4f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
}
}
}
- }
- // Pattern: (fsqrt:v4f32 VR128:v4f32:$src)
- // Emits: (SQRTPSr:v4f32 VR128:v4f32:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
+ // Pattern: (fsqrt:v4f32 VR128:v4f32:$src)
+ // Emits: (SQRTPSr:v4f32 VR128:v4f32:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
SDNode *Result = Emit_72(N, X86::SQRTPSr, MVT::v4f32);
return Result;
}
@@ -11211,37 +11131,36 @@ SDNode *Select_ISD_FSQRT_v4f32(SDNode *N) {
}
SDNode *Select_ISD_FSQRT_v2f64(SDNode *N) {
+ if ((Subtarget->hasSSE2())) {
- // Pattern: (fsqrt:v2f64 (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (SQRTPDm:v2f64 addr:iPTR:$src)
- // Pattern complexity = 25 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse()) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_79(N, X86::SQRTPDm, MVT::v2f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
+ // Pattern: (fsqrt:v2f64 (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (SQRTPDm:v2f64 addr:iPTR:$src)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse()) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_79(N, X86::SQRTPDm, MVT::v2f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
}
}
}
- }
- // Pattern: (fsqrt:v2f64 VR128:v2f64:$src)
- // Emits: (SQRTPDr:v2f64 VR128:v2f64:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
+ // Pattern: (fsqrt:v2f64 VR128:v2f64:$src)
+ // Emits: (SQRTPDr:v2f64 VR128:v2f64:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
SDNode *Result = Emit_72(N, X86::SQRTPDr, MVT::v2f64);
return Result;
}
@@ -11251,69 +11170,69 @@ SDNode *Select_ISD_FSQRT_v2f64(SDNode *N) {
}
SDNode *Select_ISD_FSUB_f32(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
- if ((!Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_loadf32(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
-
- // Pattern: (fsub:f32 RFP32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>)
- // Emits: (SUB_Fp32m:f32 RFP32:f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 0
- {
- SDNode *Result = Emit_18(N, X86::SUB_Fp32m, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
+ if ((!Subtarget->hasSSE1())) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_loadf32(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- // Pattern: (fsub:f32 RFP32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>)
- // Emits: (SUBR_Fp32m:f32 RFP32:f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 0
- SDNode *Result = Emit_18(N, X86::SUBR_Fp32m, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ // Pattern: (fsub:f32 RFP32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>)
+ // Emits: (SUB_Fp32m:f32 RFP32:f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 0
+ {
+ SDNode *Result = Emit_18(N, X86::SUB_Fp32m, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
+
+ // Pattern: (fsub:f32 RFP32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>)
+ // Emits: (SUBR_Fp32m:f32 RFP32:f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 0
+ SDNode *Result = Emit_18(N, X86::SUBR_Fp32m, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
}
}
}
+ }
- // Pattern: (fsub:f32 FR32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (SUBSSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::SUBSSrm, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
+ // Pattern: (fsub:f32 FR32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (SUBSSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::SUBSSrm, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
}
}
}
- if ((!Subtarget->hasSSE1())) {
+ }
+ if ((!Subtarget->hasSSE1())) {
+ {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == X86ISD::FILD &&
@@ -11363,12 +11282,10 @@ SDNode *Select_ISD_FSUB_f32(SDNode *N) {
}
}
}
- }
- // Pattern: (fsub:f32 RFP32:f32:$src1, RFP32:f32:$src2)
- // Emits: (SUB_Fp32:f32 RFP32:f32:$src1, RFP32:f32:$src2)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((!Subtarget->hasSSE1())) {
+ // Pattern: (fsub:f32 RFP32:f32:$src1, RFP32:f32:$src2)
+ // Emits: (SUB_Fp32:f32 RFP32:f32:$src1, RFP32:f32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 0
SDNode *Result = Emit_15(N, X86::SUB_Fp32, MVT::f32);
return Result;
}
@@ -11386,99 +11303,71 @@ SDNode *Select_ISD_FSUB_f32(SDNode *N) {
}
SDNode *Select_ISD_FSUB_f64(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
- if ((!Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode())) {
-
- // Pattern: (fsub:f64 RFP64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>)
- // Emits: (SUB_Fp64m:f64 RFP64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 0
- if (Predicate_load(N1.getNode()) &&
- Predicate_loadf64(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::SUB_Fp64m, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
+ if ((!Subtarget->hasSSE2())) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode())) {
- // Pattern: (fsub:f64 RFP64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf32>>)
- // Emits: (SUB_Fp64m32:f64 RFP64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 0
- if (Predicate_extload(N1.getNode()) &&
- Predicate_extloadf32(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::SUB_Fp64m32, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
+ // Pattern: (fsub:f64 RFP64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>)
+ // Emits: (SUB_Fp64m:f64 RFP64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 0
+ if (Predicate_load(N1.getNode()) &&
+ Predicate_loadf64(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::SUB_Fp64m, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
}
+ }
- // Pattern: (fsub:f64 RFP64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>)
- // Emits: (SUBR_Fp64m:f64 RFP64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 0
- if (Predicate_load(N1.getNode()) &&
- Predicate_loadf64(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::SUBR_Fp64m, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
+ // Pattern: (fsub:f64 RFP64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf32>>)
+ // Emits: (SUB_Fp64m32:f64 RFP64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 0
+ if (Predicate_extload(N1.getNode()) &&
+ Predicate_extloadf32(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::SUB_Fp64m32, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
}
+ }
- // Pattern: (fsub:f64 RFP64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf32>>)
- // Emits: (SUBR_Fp64m32:f64 RFP64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 0
- if (Predicate_extload(N1.getNode()) &&
- Predicate_extloadf32(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::SUBR_Fp64m32, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
+ // Pattern: (fsub:f64 RFP64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>)
+ // Emits: (SUBR_Fp64m:f64 RFP64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 0
+ if (Predicate_load(N1.getNode()) &&
+ Predicate_loadf64(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::SUBR_Fp64m, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
}
}
- }
- }
- // Pattern: (fsub:f64 FR64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (SUBSDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
+ // Pattern: (fsub:f64 RFP64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf32>>)
+ // Emits: (SUBR_Fp64m32:f64 RFP64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 0
+ if (Predicate_extload(N1.getNode()) &&
+ Predicate_extloadf32(N1.getNode())) {
SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
@@ -11486,13 +11375,41 @@ SDNode *Select_ISD_FSUB_f64(SDNode *N) {
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::SUBSDrm, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_18(N, X86::SUBR_Fp64m32, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
}
}
- if ((!Subtarget->hasSSE2())) {
+ }
+
+ // Pattern: (fsub:f64 FR64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (SUBSDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::SUBSDrm, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ if ((!Subtarget->hasSSE2())) {
+ {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == X86ISD::FILD &&
@@ -11542,12 +11459,10 @@ SDNode *Select_ISD_FSUB_f64(SDNode *N) {
}
}
}
- }
- // Pattern: (fsub:f64 RFP64:f64:$src1, RFP64:f64:$src2)
- // Emits: (SUB_Fp64:f64 RFP64:f64:$src1, RFP64:f64:$src2)
- // Pattern complexity = 3 cost = 1 size = 0
- if ((!Subtarget->hasSSE2())) {
+ // Pattern: (fsub:f64 RFP64:f64:$src1, RFP64:f64:$src2)
+ // Emits: (SUB_Fp64:f64 RFP64:f64:$src1, RFP64:f64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 0
SDNode *Result = Emit_15(N, X86::SUB_Fp64, MVT::f64);
return Result;
}
@@ -11565,7 +11480,7 @@ SDNode *Select_ISD_FSUB_f64(SDNode *N) {
}
SDNode *Select_ISD_FSUB_f80(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::LOAD &&
@@ -11696,39 +11611,38 @@ SDNode *Select_ISD_FSUB_f80(SDNode *N) {
}
SDNode *Select_ISD_FSUB_v4f32(SDNode *N) {
+ if ((Subtarget->hasSSE1())) {
- // Pattern: (fsub:v4f32 VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (SUBPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::SUBPSrm, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
+ // Pattern: (fsub:v4f32 VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (SUBPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::SUBPSrm, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
}
}
}
- }
- // Pattern: (fsub:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
- // Emits: (SUBPSrr:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
+ // Pattern: (fsub:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Emits: (SUBPSrr:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
SDNode *Result = Emit_15(N, X86::SUBPSrr, MVT::v4f32);
return Result;
}
@@ -11738,39 +11652,38 @@ SDNode *Select_ISD_FSUB_v4f32(SDNode *N) {
}
SDNode *Select_ISD_FSUB_v2f64(SDNode *N) {
+ if ((Subtarget->hasSSE2())) {
- // Pattern: (fsub:v2f64 VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (SUBPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::SUBPDrm, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
+ // Pattern: (fsub:v2f64 VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (SUBPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::SUBPDrm, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
}
}
}
- }
- // Pattern: (fsub:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
- // Emits: (SUBPDrr:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
+ // Pattern: (fsub:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Emits: (SUBPDrr:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
SDNode *Result = Emit_15(N, X86::SUBPDrr, MVT::v2f64);
return Result;
}
@@ -11850,14 +11763,13 @@ DISABLE_INLINE SDNode *Emit_99(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT
return ResNode;
}
SDNode *Select_ISD_INSERT_VECTOR_ELT_v4i32(SDNode *N) {
-
- // Pattern: (insertelt:v4i32 VR128:v4i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:iPTR):$src3)
- // Emits: (PINSRDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2, (imm:i32):$src3)
- // Pattern complexity = 28 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSE41())) {
+ if ((Subtarget->hasSSE41())) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
+
+ // Pattern: (insertelt:v4i32 VR128:v4i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:iPTR):$src3)
+ // Emits: (PINSRDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2, (imm:i32):$src3)
+ // Pattern complexity = 28 cost = 1 size = 3
if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
@@ -11879,14 +11791,10 @@ SDNode *Select_ISD_INSERT_VECTOR_ELT_v4i32(SDNode *N) {
}
}
}
- }
- // Pattern: (insertelt:v4i32 VR128:v4i32:$src1, GR32:i32:$src2, (imm:iPTR):$src3)
- // Emits: (PINSRDrr:v4i32 VR128:v4i32:$src1, GR32:i32:$src2, (imm:i32):$src3)
- // Pattern complexity = 6 cost = 1 size = 3
- if ((Subtarget->hasSSE41())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
+ // Pattern: (insertelt:v4i32 VR128:v4i32:$src1, GR32:i32:$src2, (imm:iPTR):$src3)
+ // Emits: (PINSRDrr:v4i32 VR128:v4i32:$src1, GR32:i32:$src2, (imm:i32):$src3)
+ // Pattern complexity = 6 cost = 1 size = 3
SDValue N2 = N->getOperand(2);
if (N2.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_98(N, X86::PINSRDrr, MVT::v4i32);
@@ -11899,14 +11807,13 @@ SDNode *Select_ISD_INSERT_VECTOR_ELT_v4i32(SDNode *N) {
}
SDNode *Select_ISD_INSERT_VECTOR_ELT_v2i64(SDNode *N) {
-
- // Pattern: (insertelt:v2i64 VR128:v2i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:iPTR):$src3)
- // Emits: (PINSRQrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2, (imm:i32):$src3)
- // Pattern complexity = 28 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSE41())) {
+ if ((Subtarget->hasSSE41())) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
+
+ // Pattern: (insertelt:v2i64 VR128:v2i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:iPTR):$src3)
+ // Emits: (PINSRQrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2, (imm:i32):$src3)
+ // Pattern complexity = 28 cost = 1 size = 3
if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
@@ -11929,14 +11836,10 @@ SDNode *Select_ISD_INSERT_VECTOR_ELT_v2i64(SDNode *N) {
}
}
}
- }
- // Pattern: (insertelt:v2i64 VR128:v2i64:$src1, GR64:i64:$src2, (imm:iPTR):$src3)
- // Emits: (PINSRQrr:v2i64 VR128:v2i64:$src1, GR64:i64:$src2, (imm:i32):$src3)
- // Pattern complexity = 6 cost = 1 size = 3
- if ((Subtarget->hasSSE41())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
+ // Pattern: (insertelt:v2i64 VR128:v2i64:$src1, GR64:i64:$src2, (imm:iPTR):$src3)
+ // Emits: (PINSRQrr:v2i64 VR128:v2i64:$src1, GR64:i64:$src2, (imm:i32):$src3)
+ // Pattern complexity = 6 cost = 1 size = 3
SDValue N2 = N->getOperand(2);
if (N2.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_98(N, X86::PINSRQrr, MVT::v2i64);
@@ -12034,10 +11937,10 @@ SDNode *Select_ISD_INTRINSIC_VOID(SDNode *N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_void:isVoid 714:iPTR, addr:iPTR:$dst, VR128:v4f32:$src)
+ // Pattern: (intrinsic_void:isVoid 715:iPTR, addr:iPTR:$dst, VR128:v4f32:$src)
// Emits: (MOVUPSmr_Int:isVoid addr:iPTR:$dst, VR128:v4f32:$src)
// Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(714)) {
+ if (CN1 == INT64_C(715)) {
SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
@@ -12050,10 +11953,10 @@ SDNode *Select_ISD_INTRINSIC_VOID(SDNode *N) {
}
}
- // Pattern: (intrinsic_void:isVoid 704:iPTR, addr:iPTR:$dst, VR128:v4f32:$src)
+ // Pattern: (intrinsic_void:isVoid 705:iPTR, addr:iPTR:$dst, VR128:v4f32:$src)
// Emits: (MOVNTPSmr:isVoid addr:iPTR:$dst, VR128:v4f32:$src)
// Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(704)) {
+ if (CN1 == INT64_C(705)) {
SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
@@ -12066,10 +11969,10 @@ SDNode *Select_ISD_INTRINSIC_VOID(SDNode *N) {
}
}
- // Pattern: (intrinsic_void:isVoid 697:iPTR, addr:iPTR:$src)
+ // Pattern: (intrinsic_void:isVoid 698:iPTR, addr:iPTR:$src)
// Emits: (LDMXCSR:isVoid addr:iPTR:$src)
// Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(697)) {
+ if (CN1 == INT64_C(698)) {
SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
@@ -12082,10 +11985,10 @@ SDNode *Select_ISD_INTRINSIC_VOID(SDNode *N) {
}
}
- // Pattern: (intrinsic_void:isVoid 713:iPTR, addr:iPTR:$dst)
+ // Pattern: (intrinsic_void:isVoid 714:iPTR, addr:iPTR:$dst)
// Emits: (STMXCSR:isVoid addr:iPTR:$dst)
// Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(713)) {
+ if (CN1 == INT64_C(714)) {
SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
@@ -12106,10 +12009,10 @@ SDNode *Select_ISD_INTRINSIC_VOID(SDNode *N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_void:isVoid 592:iPTR, addr:iPTR:$dst, VR128:v2f64:$src)
+ // Pattern: (intrinsic_void:isVoid 593:iPTR, addr:iPTR:$dst, VR128:v2f64:$src)
// Emits: (MOVUPDmr_Int:isVoid addr:iPTR:$dst, VR128:v2f64:$src)
// Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(592)) {
+ if (CN1 == INT64_C(593)) {
SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
@@ -12122,10 +12025,10 @@ SDNode *Select_ISD_INTRINSIC_VOID(SDNode *N) {
}
}
- // Pattern: (intrinsic_void:isVoid 591:iPTR, addr:iPTR:$dst, VR128:v16i8:$src)
+ // Pattern: (intrinsic_void:isVoid 592:iPTR, addr:iPTR:$dst, VR128:v16i8:$src)
// Emits: (MOVDQUmr_Int:isVoid addr:iPTR:$dst, VR128:v16i8:$src)
// Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(591)) {
+ if (CN1 == INT64_C(592)) {
SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
@@ -12138,10 +12041,10 @@ SDNode *Select_ISD_INTRINSIC_VOID(SDNode *N) {
}
}
- // Pattern: (intrinsic_void:isVoid 537:iPTR, addr:iPTR:$dst, VR128:v2f64:$src)
+ // Pattern: (intrinsic_void:isVoid 538:iPTR, addr:iPTR:$dst, VR128:v2f64:$src)
// Emits: (MOVNTPDmr:isVoid addr:iPTR:$dst, VR128:v2f64:$src)
// Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(537)) {
+ if (CN1 == INT64_C(538)) {
SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
@@ -12154,10 +12057,10 @@ SDNode *Select_ISD_INTRINSIC_VOID(SDNode *N) {
}
}
- // Pattern: (intrinsic_void:isVoid 535:iPTR, addr:iPTR:$dst, VR128:v2i64:$src)
+ // Pattern: (intrinsic_void:isVoid 536:iPTR, addr:iPTR:$dst, VR128:v2i64:$src)
// Emits: (MOVNTDQmr:isVoid addr:iPTR:$dst, VR128:v2i64:$src)
// Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(535)) {
+ if (CN1 == INT64_C(536)) {
SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
@@ -12170,10 +12073,10 @@ SDNode *Select_ISD_INTRINSIC_VOID(SDNode *N) {
}
}
- // Pattern: (intrinsic_void:isVoid 536:iPTR, addr:iPTR:$dst, GR32:i32:$src)
+ // Pattern: (intrinsic_void:isVoid 537:iPTR, addr:iPTR:$dst, GR32:i32:$src)
// Emits: (MOVNTImr:isVoid addr:iPTR:$dst, GR32:i32:$src)
// Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(536)) {
+ if (CN1 == INT64_C(537)) {
SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
@@ -12186,10 +12089,10 @@ SDNode *Select_ISD_INTRINSIC_VOID(SDNode *N) {
}
}
- // Pattern: (intrinsic_void:isVoid 499:iPTR, addr:iPTR:$src)
+ // Pattern: (intrinsic_void:isVoid 500:iPTR, addr:iPTR:$src)
// Emits: (CLFLUSH:isVoid addr:iPTR:$src)
// Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(499)) {
+ if (CN1 == INT64_C(500)) {
SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
@@ -12202,10 +12105,10 @@ SDNode *Select_ISD_INTRINSIC_VOID(SDNode *N) {
}
}
- // Pattern: (intrinsic_void:isVoid 590:iPTR, addr:iPTR:$dst, VR128:v4i32:$src)
+ // Pattern: (intrinsic_void:isVoid 591:iPTR, addr:iPTR:$dst, VR128:v4i32:$src)
// Emits: (MOVLQ128mr:isVoid addr:iPTR:$dst, VR128:v4i32:$src)
// Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(590)) {
+ if (CN1 == INT64_C(591)) {
SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
@@ -12220,7 +12123,7 @@ SDNode *Select_ISD_INTRINSIC_VOID(SDNode *N) {
}
}
- // Pattern: (intrinsic_void:isVoid 452:iPTR, addr:iPTR:$dst, VR64:v1i64:$src)
+ // Pattern: (intrinsic_void:isVoid 453:iPTR, addr:iPTR:$dst, VR64:v1i64:$src)
// Emits: (MMX_MOVNTQmr:isVoid addr:iPTR:$dst, VR64:v1i64:$src)
// Pattern complexity = 26 cost = 1 size = 3
if ((Subtarget->hasMMX())) {
@@ -12229,7 +12132,7 @@ SDNode *Select_ISD_INTRINSIC_VOID(SDNode *N) {
ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(452)) {
+ if (CN1 == INT64_C(453)) {
SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
@@ -12244,7 +12147,7 @@ SDNode *Select_ISD_INTRINSIC_VOID(SDNode *N) {
}
}
- // Pattern: (intrinsic_void:isVoid 710:iPTR)
+ // Pattern: (intrinsic_void:isVoid 711:iPTR)
// Emits: (SFENCE:isVoid)
// Pattern complexity = 8 cost = 1 size = 3
if ((Subtarget->hasSSE1())) {
@@ -12253,7 +12156,7 @@ SDNode *Select_ISD_INTRINSIC_VOID(SDNode *N) {
ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(710)) {
+ if (CN1 == INT64_C(711)) {
SDNode *Result = Emit_101(N, X86::SFENCE);
return Result;
}
@@ -12265,12 +12168,12 @@ SDNode *Select_ISD_INTRINSIC_VOID(SDNode *N) {
ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(528)) {
+ if (CN1 == INT64_C(529)) {
SDValue N2 = N->getOperand(2);
SDValue N3 = N->getOperand(3);
SDValue N4 = N->getOperand(4);
- // Pattern: (intrinsic_void:isVoid 528:iPTR, VR128:v16i8:$src, VR128:v16i8:$mask, EDI:i32)
+ // Pattern: (intrinsic_void:isVoid 529:iPTR, VR128:v16i8:$src, VR128:v16i8:$mask, EDI:i32)
// Emits: (MASKMOVDQU:isVoid VR128:v16i8:$src, VR128:v16i8:$mask)
// Pattern complexity = 8 cost = 1 size = 3
if (N4.getValueType() == MVT::i32) {
@@ -12278,7 +12181,7 @@ SDNode *Select_ISD_INTRINSIC_VOID(SDNode *N) {
return Result;
}
- // Pattern: (intrinsic_void:isVoid 528:iPTR, VR128:v16i8:$src, VR128:v16i8:$mask, RDI:i64)
+ // Pattern: (intrinsic_void:isVoid 529:iPTR, VR128:v16i8:$src, VR128:v16i8:$mask, RDI:i64)
// Emits: (MASKMOVDQU64:isVoid VR128:v16i8:$src, VR128:v16i8:$mask)
// Pattern complexity = 8 cost = 1 size = 3
if (N4.getValueType() == MVT::i64) {
@@ -12287,18 +12190,18 @@ SDNode *Select_ISD_INTRINSIC_VOID(SDNode *N) {
}
}
- // Pattern: (intrinsic_void:isVoid 525:iPTR)
+ // Pattern: (intrinsic_void:isVoid 526:iPTR)
// Emits: (LFENCE:isVoid)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(525)) {
+ if (CN1 == INT64_C(526)) {
SDNode *Result = Emit_101(N, X86::LFENCE);
return Result;
}
- // Pattern: (intrinsic_void:isVoid 531:iPTR)
+ // Pattern: (intrinsic_void:isVoid 532:iPTR)
// Emits: (MFENCE:isVoid)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(531)) {
+ if (CN1 == INT64_C(532)) {
SDNode *Result = Emit_101(N, X86::MFENCE);
return Result;
}
@@ -12311,10 +12214,10 @@ SDNode *Select_ISD_INTRINSIC_VOID(SDNode *N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_void:isVoid 607:iPTR, EAX:i32, ECX:i32, EDX:i32)
+ // Pattern: (intrinsic_void:isVoid 608:iPTR, EAX:i32, ECX:i32, EDX:i32)
// Emits: (MONITOR:isVoid)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(607)) {
+ if (CN1 == INT64_C(608)) {
SDValue N2 = N->getOperand(2);
SDValue N3 = N->getOperand(3);
SDValue N4 = N->getOperand(4);
@@ -12324,10 +12227,10 @@ SDNode *Select_ISD_INTRINSIC_VOID(SDNode *N) {
}
}
- // Pattern: (intrinsic_void:isVoid 608:iPTR, ECX:i32, EAX:i32)
+ // Pattern: (intrinsic_void:isVoid 609:iPTR, ECX:i32, EAX:i32)
// Emits: (MWAIT:isVoid)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(608)) {
+ if (CN1 == INT64_C(609)) {
SDNode *Result = Emit_106(N, X86::MWAIT);
return Result;
}
@@ -12340,26 +12243,26 @@ SDNode *Select_ISD_INTRINSIC_VOID(SDNode *N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_void:isVoid 449:iPTR)
+ // Pattern: (intrinsic_void:isVoid 450:iPTR)
// Emits: (MMX_EMMS:isVoid)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(449)) {
+ if (CN1 == INT64_C(450)) {
SDNode *Result = Emit_101(N, X86::MMX_EMMS);
return Result;
}
- // Pattern: (intrinsic_void:isVoid 450:iPTR)
+ // Pattern: (intrinsic_void:isVoid 451:iPTR)
// Emits: (MMX_FEMMS:isVoid)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(450)) {
+ if (CN1 == INT64_C(451)) {
SDNode *Result = Emit_101(N, X86::MMX_FEMMS);
return Result;
}
- // Pattern: (intrinsic_void:isVoid 451:iPTR, VR64:v8i8:$src, VR64:v8i8:$mask, EDI:i32)
+ // Pattern: (intrinsic_void:isVoid 452:iPTR, VR64:v8i8:$src, VR64:v8i8:$mask, EDI:i32)
// Emits: (MMX_MASKMOVQ:isVoid VR64:v8i8:$src, VR64:v8i8:$mask)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(451)) {
+ if (CN1 == INT64_C(452)) {
SDValue N2 = N->getOperand(2);
SDValue N3 = N->getOperand(3);
SDValue N4 = N->getOperand(4);
@@ -12371,7 +12274,7 @@ SDNode *Select_ISD_INTRINSIC_VOID(SDNode *N) {
}
}
- // Pattern: (intrinsic_void:isVoid 451:iPTR, VR64:v8i8:$src, VR64:v8i8:$mask, RDI:i64)
+ // Pattern: (intrinsic_void:isVoid 452:iPTR, VR64:v8i8:$src, VR64:v8i8:$mask, RDI:i64)
// Emits: (MMX_MASKMOVQ64:isVoid VR64:v8i8:$src, VR64:v8i8:$mask)
// Pattern complexity = 8 cost = 1 size = 3
if ((Subtarget->hasMMX()) && (Subtarget->is64Bit())) {
@@ -12380,7 +12283,7 @@ SDNode *Select_ISD_INTRINSIC_VOID(SDNode *N) {
ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(451)) {
+ if (CN1 == INT64_C(452)) {
SDValue N2 = N->getOperand(2);
SDValue N3 = N->getOperand(3);
SDValue N4 = N->getOperand(4);
@@ -12503,584 +12406,575 @@ DISABLE_INLINE SDNode *Emit_114(SDNode *N, unsigned Opc0, SDValue &CPTmpN31_0, S
return ResNode;
}
SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
- if ((Subtarget->hasSSE42())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
+ if ((Subtarget->hasSSE42())) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:i32 668:iPTR, VR128:v16i8:$src1, (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i8):$src3)
- // Emits: (PCMPISTRIrm:isVoid VR128:v16i8:$src1, addr:iPTR:$src2, (imm:i8):$src3)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(668)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_112(N, X86::PCMPISTRIrm, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:i32 669:iPTR, VR128:v16i8:$src1, (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i8):$src3)
+ // Emits: (PCMPISTRIrm:isVoid VR128:v16i8:$src1, addr:iPTR:$src2, (imm:i8):$src3)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(669)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode())) {
+ SDValue N21 = N2.getNode()->getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_112(N, X86::PCMPISTRIrm, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:i32 669:iPTR, VR128:v16i8:$src1, (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i8):$src3)
- // Emits: (PCMPISTRIArm:isVoid VR128:v16i8:$src1, addr:iPTR:$src2, (imm:i8):$src3)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(669)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_112(N, X86::PCMPISTRIArm, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:i32 670:iPTR, VR128:v16i8:$src1, (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i8):$src3)
+ // Emits: (PCMPISTRIArm:isVoid VR128:v16i8:$src1, addr:iPTR:$src2, (imm:i8):$src3)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(670)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode())) {
+ SDValue N21 = N2.getNode()->getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_112(N, X86::PCMPISTRIArm, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:i32 670:iPTR, VR128:v16i8:$src1, (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i8):$src3)
- // Emits: (PCMPISTRICrm:isVoid VR128:v16i8:$src1, addr:iPTR:$src2, (imm:i8):$src3)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(670)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_112(N, X86::PCMPISTRICrm, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:i32 671:iPTR, VR128:v16i8:$src1, (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i8):$src3)
+ // Emits: (PCMPISTRICrm:isVoid VR128:v16i8:$src1, addr:iPTR:$src2, (imm:i8):$src3)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(671)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode())) {
+ SDValue N21 = N2.getNode()->getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_112(N, X86::PCMPISTRICrm, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:i32 671:iPTR, VR128:v16i8:$src1, (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i8):$src3)
- // Emits: (PCMPISTRIOrm:isVoid VR128:v16i8:$src1, addr:iPTR:$src2, (imm:i8):$src3)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(671)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_112(N, X86::PCMPISTRIOrm, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:i32 672:iPTR, VR128:v16i8:$src1, (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i8):$src3)
+ // Emits: (PCMPISTRIOrm:isVoid VR128:v16i8:$src1, addr:iPTR:$src2, (imm:i8):$src3)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(672)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode())) {
+ SDValue N21 = N2.getNode()->getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_112(N, X86::PCMPISTRIOrm, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:i32 672:iPTR, VR128:v16i8:$src1, (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i8):$src3)
- // Emits: (PCMPISTRISrm:isVoid VR128:v16i8:$src1, addr:iPTR:$src2, (imm:i8):$src3)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(672)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_112(N, X86::PCMPISTRISrm, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:i32 673:iPTR, VR128:v16i8:$src1, (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i8):$src3)
+ // Emits: (PCMPISTRISrm:isVoid VR128:v16i8:$src1, addr:iPTR:$src2, (imm:i8):$src3)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(673)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode())) {
+ SDValue N21 = N2.getNode()->getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_112(N, X86::PCMPISTRISrm, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:i32 673:iPTR, VR128:v16i8:$src1, (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i8):$src3)
- // Emits: (PCMPISTRIZrm:isVoid VR128:v16i8:$src1, addr:iPTR:$src2, (imm:i8):$src3)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(673)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_112(N, X86::PCMPISTRIZrm, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:i32 674:iPTR, VR128:v16i8:$src1, (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i8):$src3)
+ // Emits: (PCMPISTRIZrm:isVoid VR128:v16i8:$src1, addr:iPTR:$src2, (imm:i8):$src3)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(674)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode())) {
+ SDValue N21 = N2.getNode()->getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_112(N, X86::PCMPISTRIZrm, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:i32 660:iPTR, VR128:v16i8:$src1, EAX:i32, (ld:v16i8 addr:iPTR:$src3)<<P:Predicate_unindexedload>><<P:Predicate_load>>, EDX:i32, (imm:i8):$src5)
- // Emits: (PCMPESTRIrm:isVoid VR128:v16i8:$src1, addr:iPTR:$src3, (imm:i8):$src5)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(660)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::LOAD &&
- N3.hasOneUse() &&
- IsLegalAndProfitableToFold(N3.getNode(), N, N)) {
- SDValue Chain3 = N3.getNode()->getOperand(0);
- if (Predicate_unindexedload(N3.getNode()) &&
- Predicate_load(N3.getNode())) {
- SDValue N31 = N3.getNode()->getOperand(1);
- SDValue CPTmpN31_0;
- SDValue CPTmpN31_1;
- SDValue CPTmpN31_2;
- SDValue CPTmpN31_3;
- SDValue CPTmpN31_4;
- if (SelectAddr(N, N31, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4)) {
- SDValue N4 = N->getOperand(4);
- SDValue N5 = N->getOperand(5);
- if (N5.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_114(N, X86::PCMPESTRIrm, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:i32 661:iPTR, VR128:v16i8:$src1, EAX:i32, (ld:v16i8 addr:iPTR:$src3)<<P:Predicate_unindexedload>><<P:Predicate_load>>, EDX:i32, (imm:i8):$src5)
+ // Emits: (PCMPESTRIrm:isVoid VR128:v16i8:$src1, addr:iPTR:$src3, (imm:i8):$src5)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(661)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::LOAD &&
+ N3.hasOneUse() &&
+ IsLegalAndProfitableToFold(N3.getNode(), N, N)) {
+ SDValue Chain3 = N3.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N3.getNode()) &&
+ Predicate_load(N3.getNode())) {
+ SDValue N31 = N3.getNode()->getOperand(1);
+ SDValue CPTmpN31_0;
+ SDValue CPTmpN31_1;
+ SDValue CPTmpN31_2;
+ SDValue CPTmpN31_3;
+ SDValue CPTmpN31_4;
+ if (SelectAddr(N, N31, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4)) {
+ SDValue N4 = N->getOperand(4);
+ SDValue N5 = N->getOperand(5);
+ if (N5.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_114(N, X86::PCMPESTRIrm, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:i32 661:iPTR, VR128:v16i8:$src1, EAX:i32, (ld:v16i8 addr:iPTR:$src3)<<P:Predicate_unindexedload>><<P:Predicate_load>>, EDX:i32, (imm:i8):$src5)
- // Emits: (PCMPESTRIArm:isVoid VR128:v16i8:$src1, addr:iPTR:$src3, (imm:i8):$src5)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(661)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::LOAD &&
- N3.hasOneUse() &&
- IsLegalAndProfitableToFold(N3.getNode(), N, N)) {
- SDValue Chain3 = N3.getNode()->getOperand(0);
- if (Predicate_unindexedload(N3.getNode()) &&
- Predicate_load(N3.getNode())) {
- SDValue N31 = N3.getNode()->getOperand(1);
- SDValue CPTmpN31_0;
- SDValue CPTmpN31_1;
- SDValue CPTmpN31_2;
- SDValue CPTmpN31_3;
- SDValue CPTmpN31_4;
- if (SelectAddr(N, N31, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4)) {
- SDValue N4 = N->getOperand(4);
- SDValue N5 = N->getOperand(5);
- if (N5.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_114(N, X86::PCMPESTRIArm, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:i32 662:iPTR, VR128:v16i8:$src1, EAX:i32, (ld:v16i8 addr:iPTR:$src3)<<P:Predicate_unindexedload>><<P:Predicate_load>>, EDX:i32, (imm:i8):$src5)
+ // Emits: (PCMPESTRIArm:isVoid VR128:v16i8:$src1, addr:iPTR:$src3, (imm:i8):$src5)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(662)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::LOAD &&
+ N3.hasOneUse() &&
+ IsLegalAndProfitableToFold(N3.getNode(), N, N)) {
+ SDValue Chain3 = N3.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N3.getNode()) &&
+ Predicate_load(N3.getNode())) {
+ SDValue N31 = N3.getNode()->getOperand(1);
+ SDValue CPTmpN31_0;
+ SDValue CPTmpN31_1;
+ SDValue CPTmpN31_2;
+ SDValue CPTmpN31_3;
+ SDValue CPTmpN31_4;
+ if (SelectAddr(N, N31, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4)) {
+ SDValue N4 = N->getOperand(4);
+ SDValue N5 = N->getOperand(5);
+ if (N5.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_114(N, X86::PCMPESTRIArm, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:i32 662:iPTR, VR128:v16i8:$src1, EAX:i32, (ld:v16i8 addr:iPTR:$src3)<<P:Predicate_unindexedload>><<P:Predicate_load>>, EDX:i32, (imm:i8):$src5)
- // Emits: (PCMPESTRICrm:isVoid VR128:v16i8:$src1, addr:iPTR:$src3, (imm:i8):$src5)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(662)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::LOAD &&
- N3.hasOneUse() &&
- IsLegalAndProfitableToFold(N3.getNode(), N, N)) {
- SDValue Chain3 = N3.getNode()->getOperand(0);
- if (Predicate_unindexedload(N3.getNode()) &&
- Predicate_load(N3.getNode())) {
- SDValue N31 = N3.getNode()->getOperand(1);
- SDValue CPTmpN31_0;
- SDValue CPTmpN31_1;
- SDValue CPTmpN31_2;
- SDValue CPTmpN31_3;
- SDValue CPTmpN31_4;
- if (SelectAddr(N, N31, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4)) {
- SDValue N4 = N->getOperand(4);
- SDValue N5 = N->getOperand(5);
- if (N5.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_114(N, X86::PCMPESTRICrm, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:i32 663:iPTR, VR128:v16i8:$src1, EAX:i32, (ld:v16i8 addr:iPTR:$src3)<<P:Predicate_unindexedload>><<P:Predicate_load>>, EDX:i32, (imm:i8):$src5)
+ // Emits: (PCMPESTRICrm:isVoid VR128:v16i8:$src1, addr:iPTR:$src3, (imm:i8):$src5)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(663)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::LOAD &&
+ N3.hasOneUse() &&
+ IsLegalAndProfitableToFold(N3.getNode(), N, N)) {
+ SDValue Chain3 = N3.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N3.getNode()) &&
+ Predicate_load(N3.getNode())) {
+ SDValue N31 = N3.getNode()->getOperand(1);
+ SDValue CPTmpN31_0;
+ SDValue CPTmpN31_1;
+ SDValue CPTmpN31_2;
+ SDValue CPTmpN31_3;
+ SDValue CPTmpN31_4;
+ if (SelectAddr(N, N31, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4)) {
+ SDValue N4 = N->getOperand(4);
+ SDValue N5 = N->getOperand(5);
+ if (N5.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_114(N, X86::PCMPESTRICrm, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:i32 663:iPTR, VR128:v16i8:$src1, EAX:i32, (ld:v16i8 addr:iPTR:$src3)<<P:Predicate_unindexedload>><<P:Predicate_load>>, EDX:i32, (imm:i8):$src5)
- // Emits: (PCMPESTRIOrm:isVoid VR128:v16i8:$src1, addr:iPTR:$src3, (imm:i8):$src5)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(663)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::LOAD &&
- N3.hasOneUse() &&
- IsLegalAndProfitableToFold(N3.getNode(), N, N)) {
- SDValue Chain3 = N3.getNode()->getOperand(0);
- if (Predicate_unindexedload(N3.getNode()) &&
- Predicate_load(N3.getNode())) {
- SDValue N31 = N3.getNode()->getOperand(1);
- SDValue CPTmpN31_0;
- SDValue CPTmpN31_1;
- SDValue CPTmpN31_2;
- SDValue CPTmpN31_3;
- SDValue CPTmpN31_4;
- if (SelectAddr(N, N31, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4)) {
- SDValue N4 = N->getOperand(4);
- SDValue N5 = N->getOperand(5);
- if (N5.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_114(N, X86::PCMPESTRIOrm, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:i32 664:iPTR, VR128:v16i8:$src1, EAX:i32, (ld:v16i8 addr:iPTR:$src3)<<P:Predicate_unindexedload>><<P:Predicate_load>>, EDX:i32, (imm:i8):$src5)
+ // Emits: (PCMPESTRIOrm:isVoid VR128:v16i8:$src1, addr:iPTR:$src3, (imm:i8):$src5)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(664)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::LOAD &&
+ N3.hasOneUse() &&
+ IsLegalAndProfitableToFold(N3.getNode(), N, N)) {
+ SDValue Chain3 = N3.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N3.getNode()) &&
+ Predicate_load(N3.getNode())) {
+ SDValue N31 = N3.getNode()->getOperand(1);
+ SDValue CPTmpN31_0;
+ SDValue CPTmpN31_1;
+ SDValue CPTmpN31_2;
+ SDValue CPTmpN31_3;
+ SDValue CPTmpN31_4;
+ if (SelectAddr(N, N31, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4)) {
+ SDValue N4 = N->getOperand(4);
+ SDValue N5 = N->getOperand(5);
+ if (N5.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_114(N, X86::PCMPESTRIOrm, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:i32 664:iPTR, VR128:v16i8:$src1, EAX:i32, (ld:v16i8 addr:iPTR:$src3)<<P:Predicate_unindexedload>><<P:Predicate_load>>, EDX:i32, (imm:i8):$src5)
- // Emits: (PCMPESTRISrm:isVoid VR128:v16i8:$src1, addr:iPTR:$src3, (imm:i8):$src5)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(664)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::LOAD &&
- N3.hasOneUse() &&
- IsLegalAndProfitableToFold(N3.getNode(), N, N)) {
- SDValue Chain3 = N3.getNode()->getOperand(0);
- if (Predicate_unindexedload(N3.getNode()) &&
- Predicate_load(N3.getNode())) {
- SDValue N31 = N3.getNode()->getOperand(1);
- SDValue CPTmpN31_0;
- SDValue CPTmpN31_1;
- SDValue CPTmpN31_2;
- SDValue CPTmpN31_3;
- SDValue CPTmpN31_4;
- if (SelectAddr(N, N31, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4)) {
- SDValue N4 = N->getOperand(4);
- SDValue N5 = N->getOperand(5);
- if (N5.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_114(N, X86::PCMPESTRISrm, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:i32 665:iPTR, VR128:v16i8:$src1, EAX:i32, (ld:v16i8 addr:iPTR:$src3)<<P:Predicate_unindexedload>><<P:Predicate_load>>, EDX:i32, (imm:i8):$src5)
+ // Emits: (PCMPESTRISrm:isVoid VR128:v16i8:$src1, addr:iPTR:$src3, (imm:i8):$src5)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(665)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::LOAD &&
+ N3.hasOneUse() &&
+ IsLegalAndProfitableToFold(N3.getNode(), N, N)) {
+ SDValue Chain3 = N3.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N3.getNode()) &&
+ Predicate_load(N3.getNode())) {
+ SDValue N31 = N3.getNode()->getOperand(1);
+ SDValue CPTmpN31_0;
+ SDValue CPTmpN31_1;
+ SDValue CPTmpN31_2;
+ SDValue CPTmpN31_3;
+ SDValue CPTmpN31_4;
+ if (SelectAddr(N, N31, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4)) {
+ SDValue N4 = N->getOperand(4);
+ SDValue N5 = N->getOperand(5);
+ if (N5.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_114(N, X86::PCMPESTRISrm, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:i32 665:iPTR, VR128:v16i8:$src1, EAX:i32, (ld:v16i8 addr:iPTR:$src3)<<P:Predicate_unindexedload>><<P:Predicate_load>>, EDX:i32, (imm:i8):$src5)
- // Emits: (PCMPESTRIZrm:isVoid VR128:v16i8:$src1, addr:iPTR:$src3, (imm:i8):$src5)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(665)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::LOAD &&
- N3.hasOneUse() &&
- IsLegalAndProfitableToFold(N3.getNode(), N, N)) {
- SDValue Chain3 = N3.getNode()->getOperand(0);
- if (Predicate_unindexedload(N3.getNode()) &&
- Predicate_load(N3.getNode())) {
- SDValue N31 = N3.getNode()->getOperand(1);
- SDValue CPTmpN31_0;
- SDValue CPTmpN31_1;
- SDValue CPTmpN31_2;
- SDValue CPTmpN31_3;
- SDValue CPTmpN31_4;
- if (SelectAddr(N, N31, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4)) {
- SDValue N4 = N->getOperand(4);
- SDValue N5 = N->getOperand(5);
- if (N5.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_114(N, X86::PCMPESTRIZrm, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:i32 666:iPTR, VR128:v16i8:$src1, EAX:i32, (ld:v16i8 addr:iPTR:$src3)<<P:Predicate_unindexedload>><<P:Predicate_load>>, EDX:i32, (imm:i8):$src5)
+ // Emits: (PCMPESTRIZrm:isVoid VR128:v16i8:$src1, addr:iPTR:$src3, (imm:i8):$src5)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(666)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::LOAD &&
+ N3.hasOneUse() &&
+ IsLegalAndProfitableToFold(N3.getNode(), N, N)) {
+ SDValue Chain3 = N3.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N3.getNode()) &&
+ Predicate_load(N3.getNode())) {
+ SDValue N31 = N3.getNode()->getOperand(1);
+ SDValue CPTmpN31_0;
+ SDValue CPTmpN31_1;
+ SDValue CPTmpN31_2;
+ SDValue CPTmpN31_3;
+ SDValue CPTmpN31_4;
+ if (SelectAddr(N, N31, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4)) {
+ SDValue N4 = N->getOperand(4);
+ SDValue N5 = N->getOperand(5);
+ if (N5.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_114(N, X86::PCMPESTRIZrm, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4);
+ return Result;
}
}
}
}
}
}
- if ((Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
+ }
+ if ((Subtarget->hasSSE1())) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:i32 690:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (Int_CVTSS2SIrm:i32 addr:iPTR:$src)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(690)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTSS2SIrm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:i32 691:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (Int_CVTSS2SIrm:i32 addr:iPTR:$src)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(691)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_108(N, X86::Int_CVTSS2SIrm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:i32 694:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (Int_CVTTSS2SIrm:i32 addr:iPTR:$src)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(694)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTTSS2SIrm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:i32 695:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (Int_CVTTSS2SIrm:i32 addr:iPTR:$src)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(695)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_108(N, X86::Int_CVTTSS2SIrm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
}
}
}
}
}
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:i32 514:iPTR, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (Int_CVTSD2SIrm:i32 addr:iPTR:$src)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(514)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTSD2SIrm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:i32 515:iPTR, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (Int_CVTSD2SIrm:i32 addr:iPTR:$src)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(515)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_108(N, X86::Int_CVTSD2SIrm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:i32 522:iPTR, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (Int_CVTTSD2SIrm:i32 addr:iPTR:$src)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(522)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTTSD2SIrm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:i32 523:iPTR, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (Int_CVTTSD2SIrm:i32 addr:iPTR:$src)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(523)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_108(N, X86::Int_CVTTSD2SIrm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
}
}
}
}
}
- if ((Subtarget->hasSSE42())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
+ }
+ if ((Subtarget->hasSSE42())) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:i32 659:iPTR, GR32:i32:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (CRC32m8:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(659)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_109(N, X86::CRC32m8, MVT::i32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:i32 660:iPTR, GR32:i32:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (CRC32m8:i32 GR32:i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(660)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode())) {
+ SDValue N21 = N2.getNode()->getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDNode *Result = Emit_109(N, X86::CRC32m8, MVT::i32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:i32 656:iPTR, GR32:i32:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (CRC32m16:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(656)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_109(N, X86::CRC32m16, MVT::i32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:i32 657:iPTR, GR32:i32:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (CRC32m16:i32 GR32:i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(657)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode())) {
+ SDValue N21 = N2.getNode()->getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDNode *Result = Emit_109(N, X86::CRC32m16, MVT::i32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:i32 657:iPTR, GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (CRC32m32:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(657)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_109(N, X86::CRC32m32, MVT::i32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:i32 658:iPTR, GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (CRC32m32:i32 GR32:i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(658)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode())) {
+ SDValue N21 = N2.getNode()->getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDNode *Result = Emit_109(N, X86::CRC32m32, MVT::i32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
}
}
}
}
- }
- }
- if ((Subtarget->hasSSE42())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:i32 668:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
+ // Pattern: (intrinsic_wo_chain:i32 669:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
// Emits: (PCMPISTRIrr:isVoid VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(668)) {
+ if (CN1 == INT64_C(669)) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
SDValue N3 = N->getOperand(3);
@@ -13090,10 +12984,10 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(SDNode *N) {
}
}
- // Pattern: (intrinsic_wo_chain:i32 669:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
+ // Pattern: (intrinsic_wo_chain:i32 670:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
// Emits: (PCMPISTRIArr:isVoid VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(669)) {
+ if (CN1 == INT64_C(670)) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
SDValue N3 = N->getOperand(3);
@@ -13103,10 +12997,10 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(SDNode *N) {
}
}
- // Pattern: (intrinsic_wo_chain:i32 670:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
+ // Pattern: (intrinsic_wo_chain:i32 671:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
// Emits: (PCMPISTRICrr:isVoid VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(670)) {
+ if (CN1 == INT64_C(671)) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
SDValue N3 = N->getOperand(3);
@@ -13116,10 +13010,10 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(SDNode *N) {
}
}
- // Pattern: (intrinsic_wo_chain:i32 671:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
+ // Pattern: (intrinsic_wo_chain:i32 672:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
// Emits: (PCMPISTRIOrr:isVoid VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(671)) {
+ if (CN1 == INT64_C(672)) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
SDValue N3 = N->getOperand(3);
@@ -13129,10 +13023,10 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(SDNode *N) {
}
}
- // Pattern: (intrinsic_wo_chain:i32 672:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
+ // Pattern: (intrinsic_wo_chain:i32 673:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
// Emits: (PCMPISTRISrr:isVoid VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(672)) {
+ if (CN1 == INT64_C(673)) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
SDValue N3 = N->getOperand(3);
@@ -13142,10 +13036,10 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(SDNode *N) {
}
}
- // Pattern: (intrinsic_wo_chain:i32 673:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
+ // Pattern: (intrinsic_wo_chain:i32 674:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
// Emits: (PCMPISTRIZrr:isVoid VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(673)) {
+ if (CN1 == INT64_C(674)) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
SDValue N3 = N->getOperand(3);
@@ -13155,10 +13049,10 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(SDNode *N) {
}
}
- // Pattern: (intrinsic_wo_chain:i32 660:iPTR, VR128:v16i8:$src1, EAX:i32, VR128:v16i8:$src3, EDX:i32, (imm:i8):$src5)
+ // Pattern: (intrinsic_wo_chain:i32 661:iPTR, VR128:v16i8:$src1, EAX:i32, VR128:v16i8:$src3, EDX:i32, (imm:i8):$src5)
// Emits: (PCMPESTRIrr:isVoid VR128:v16i8:$src1, VR128:v16i8:$src3, (imm:i8):$src5)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(660)) {
+ if (CN1 == INT64_C(661)) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
SDValue N3 = N->getOperand(3);
@@ -13170,10 +13064,10 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(SDNode *N) {
}
}
- // Pattern: (intrinsic_wo_chain:i32 661:iPTR, VR128:v16i8:$src1, EAX:i32, VR128:v16i8:$src3, EDX:i32, (imm:i8):$src5)
+ // Pattern: (intrinsic_wo_chain:i32 662:iPTR, VR128:v16i8:$src1, EAX:i32, VR128:v16i8:$src3, EDX:i32, (imm:i8):$src5)
// Emits: (PCMPESTRIArr:isVoid VR128:v16i8:$src1, VR128:v16i8:$src3, (imm:i8):$src5)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(661)) {
+ if (CN1 == INT64_C(662)) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
SDValue N3 = N->getOperand(3);
@@ -13185,10 +13079,10 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(SDNode *N) {
}
}
- // Pattern: (intrinsic_wo_chain:i32 662:iPTR, VR128:v16i8:$src1, EAX:i32, VR128:v16i8:$src3, EDX:i32, (imm:i8):$src5)
+ // Pattern: (intrinsic_wo_chain:i32 663:iPTR, VR128:v16i8:$src1, EAX:i32, VR128:v16i8:$src3, EDX:i32, (imm:i8):$src5)
// Emits: (PCMPESTRICrr:isVoid VR128:v16i8:$src1, VR128:v16i8:$src3, (imm:i8):$src5)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(662)) {
+ if (CN1 == INT64_C(663)) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
SDValue N3 = N->getOperand(3);
@@ -13200,10 +13094,10 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(SDNode *N) {
}
}
- // Pattern: (intrinsic_wo_chain:i32 663:iPTR, VR128:v16i8:$src1, EAX:i32, VR128:v16i8:$src3, EDX:i32, (imm:i8):$src5)
+ // Pattern: (intrinsic_wo_chain:i32 664:iPTR, VR128:v16i8:$src1, EAX:i32, VR128:v16i8:$src3, EDX:i32, (imm:i8):$src5)
// Emits: (PCMPESTRIOrr:isVoid VR128:v16i8:$src1, VR128:v16i8:$src3, (imm:i8):$src5)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(663)) {
+ if (CN1 == INT64_C(664)) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
SDValue N3 = N->getOperand(3);
@@ -13215,10 +13109,10 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(SDNode *N) {
}
}
- // Pattern: (intrinsic_wo_chain:i32 664:iPTR, VR128:v16i8:$src1, EAX:i32, VR128:v16i8:$src3, EDX:i32, (imm:i8):$src5)
+ // Pattern: (intrinsic_wo_chain:i32 665:iPTR, VR128:v16i8:$src1, EAX:i32, VR128:v16i8:$src3, EDX:i32, (imm:i8):$src5)
// Emits: (PCMPESTRISrr:isVoid VR128:v16i8:$src1, VR128:v16i8:$src3, (imm:i8):$src5)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(664)) {
+ if (CN1 == INT64_C(665)) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
SDValue N3 = N->getOperand(3);
@@ -13230,10 +13124,10 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(SDNode *N) {
}
}
- // Pattern: (intrinsic_wo_chain:i32 665:iPTR, VR128:v16i8:$src1, EAX:i32, VR128:v16i8:$src3, EDX:i32, (imm:i8):$src5)
+ // Pattern: (intrinsic_wo_chain:i32 666:iPTR, VR128:v16i8:$src1, EAX:i32, VR128:v16i8:$src3, EDX:i32, (imm:i8):$src5)
// Emits: (PCMPESTRIZrr:isVoid VR128:v16i8:$src1, VR128:v16i8:$src3, (imm:i8):$src5)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(665)) {
+ if (CN1 == INT64_C(666)) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
SDValue N3 = N->getOperand(3);
@@ -13252,26 +13146,26 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(SDNode *N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:i32 690:iPTR, VR128:v4f32:$src)
+ // Pattern: (intrinsic_wo_chain:i32 691:iPTR, VR128:v4f32:$src)
// Emits: (Int_CVTSS2SIrr:i32 VR128:v4f32:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(690)) {
+ if (CN1 == INT64_C(691)) {
SDNode *Result = Emit_107(N, X86::Int_CVTSS2SIrr, MVT::i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:i32 694:iPTR, VR128:v4f32:$src)
+ // Pattern: (intrinsic_wo_chain:i32 695:iPTR, VR128:v4f32:$src)
// Emits: (Int_CVTTSS2SIrr:i32 VR128:v4f32:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(694)) {
+ if (CN1 == INT64_C(695)) {
SDNode *Result = Emit_107(N, X86::Int_CVTTSS2SIrr, MVT::i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:i32 703:iPTR, VR128:v4f32:$src)
+ // Pattern: (intrinsic_wo_chain:i32 704:iPTR, VR128:v4f32:$src)
// Emits: (MOVMSKPSrr:i32 VR128:v4f32:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(703)) {
+ if (CN1 == INT64_C(704)) {
SDNode *Result = Emit_107(N, X86::MOVMSKPSrr, MVT::i32);
return Result;
}
@@ -13283,34 +13177,34 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(SDNode *N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:i32 534:iPTR, VR128:v2f64:$src)
+ // Pattern: (intrinsic_wo_chain:i32 535:iPTR, VR128:v2f64:$src)
// Emits: (MOVMSKPDrr:i32 VR128:v2f64:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(534)) {
+ if (CN1 == INT64_C(535)) {
SDNode *Result = Emit_107(N, X86::MOVMSKPDrr, MVT::i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:i32 514:iPTR, VR128:v2f64:$src)
+ // Pattern: (intrinsic_wo_chain:i32 515:iPTR, VR128:v2f64:$src)
// Emits: (Int_CVTSD2SIrr:i32 VR128:v2f64:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(514)) {
+ if (CN1 == INT64_C(515)) {
SDNode *Result = Emit_107(N, X86::Int_CVTSD2SIrr, MVT::i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:i32 522:iPTR, VR128:v2f64:$src)
+ // Pattern: (intrinsic_wo_chain:i32 523:iPTR, VR128:v2f64:$src)
// Emits: (Int_CVTTSD2SIrr:i32 VR128:v2f64:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(522)) {
+ if (CN1 == INT64_C(523)) {
SDNode *Result = Emit_107(N, X86::Int_CVTTSD2SIrr, MVT::i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:i32 559:iPTR, VR128:v16i8:$src)
+ // Pattern: (intrinsic_wo_chain:i32 560:iPTR, VR128:v16i8:$src)
// Emits: (PMOVMSKBrr:i32 VR128:v16i8:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(559)) {
+ if (CN1 == INT64_C(560)) {
SDNode *Result = Emit_107(N, X86::PMOVMSKBrr, MVT::i32);
return Result;
}
@@ -13322,33 +13216,33 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(SDNode *N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:i32 659:iPTR, GR32:i32:$src1, GR8:i8:$src2)
+ // Pattern: (intrinsic_wo_chain:i32 660:iPTR, GR32:i32:$src1, GR8:i8:$src2)
// Emits: (CRC32r8:i32 GR32:i32:$src1, GR8:i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(659)) {
+ if (CN1 == INT64_C(660)) {
SDNode *Result = Emit_110(N, X86::CRC32r8, MVT::i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:i32 656:iPTR, GR32:i32:$src1, GR16:i16:$src2)
+ // Pattern: (intrinsic_wo_chain:i32 657:iPTR, GR32:i32:$src1, GR16:i16:$src2)
// Emits: (CRC32r16:i32 GR32:i32:$src1, GR16:i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(656)) {
+ if (CN1 == INT64_C(657)) {
SDNode *Result = Emit_110(N, X86::CRC32r16, MVT::i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:i32 657:iPTR, GR32:i32:$src1, GR32:i32:$src2)
+ // Pattern: (intrinsic_wo_chain:i32 658:iPTR, GR32:i32:$src1, GR32:i32:$src2)
// Emits: (CRC32r32:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(657)) {
+ if (CN1 == INT64_C(658)) {
SDNode *Result = Emit_110(N, X86::CRC32r32, MVT::i32);
return Result;
}
}
}
- // Pattern: (intrinsic_wo_chain:i32 473:iPTR, VR64:v8i8:$src)
+ // Pattern: (intrinsic_wo_chain:i32 474:iPTR, VR64:v8i8:$src)
// Emits: (MMX_PMOVMSKBrr:i32 VR64:v8i8:$src)
// Pattern complexity = 8 cost = 1 size = 3
if ((Subtarget->hasMMX())) {
@@ -13356,7 +13250,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(SDNode *N) {
ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(473)) {
+ if (CN1 == INT64_C(474)) {
SDNode *Result = Emit_107(N, X86::MMX_PMOVMSKBrr, MVT::i32);
return Result;
}
@@ -13368,149 +13262,147 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(SDNode *N) {
}
SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i64(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:i64 515:iPTR, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (Int_CVTSD2SI64rm:i64 addr:iPTR:$src)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(515)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTSD2SI64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:i64 516:iPTR, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (Int_CVTSD2SI64rm:i64 addr:iPTR:$src)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(516)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_108(N, X86::Int_CVTSD2SI64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:i64 523:iPTR, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (Int_CVTTSD2SI64rm:i64 addr:iPTR:$src)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(523)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTTSD2SI64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:i64 524:iPTR, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (Int_CVTTSD2SI64rm:i64 addr:iPTR:$src)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(524)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_108(N, X86::Int_CVTTSD2SI64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
}
}
}
}
}
- if ((Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
+ }
+ if ((Subtarget->hasSSE1())) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:i64 691:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (Int_CVTSS2SI64rm:i64 addr:iPTR:$src)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(691)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTSS2SI64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:i64 692:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (Int_CVTSS2SI64rm:i64 addr:iPTR:$src)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(692)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_108(N, X86::Int_CVTSS2SI64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:i64 695:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (Int_CVTTSS2SI64rm:i64 addr:iPTR:$src)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(695)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTTSS2SI64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:i64 696:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (Int_CVTTSS2SI64rm:i64 addr:iPTR:$src)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(696)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_108(N, X86::Int_CVTTSS2SI64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
}
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:i64 658:iPTR, GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (CRC64m64:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if ((Subtarget->hasSSE42())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(658)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_109(N, X86::CRC64m64, MVT::i64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:i64 659:iPTR, GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (CRC64m64:i64 GR64:i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if ((Subtarget->hasSSE42())) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(659)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode())) {
+ SDValue N21 = N2.getNode()->getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDNode *Result = Emit_109(N, X86::CRC64m64, MVT::i64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
}
}
}
@@ -13523,18 +13415,18 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i64(SDNode *N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:i64 515:iPTR, VR128:v2f64:$src)
+ // Pattern: (intrinsic_wo_chain:i64 516:iPTR, VR128:v2f64:$src)
// Emits: (Int_CVTSD2SI64rr:i64 VR128:v2f64:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(515)) {
+ if (CN1 == INT64_C(516)) {
SDNode *Result = Emit_107(N, X86::Int_CVTSD2SI64rr, MVT::i64);
return Result;
}
- // Pattern: (intrinsic_wo_chain:i64 523:iPTR, VR128:v2f64:$src)
+ // Pattern: (intrinsic_wo_chain:i64 524:iPTR, VR128:v2f64:$src)
// Emits: (Int_CVTTSD2SI64rr:i64 VR128:v2f64:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(523)) {
+ if (CN1 == INT64_C(524)) {
SDNode *Result = Emit_107(N, X86::Int_CVTTSD2SI64rr, MVT::i64);
return Result;
}
@@ -13546,25 +13438,25 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i64(SDNode *N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:i64 691:iPTR, VR128:v4f32:$src)
+ // Pattern: (intrinsic_wo_chain:i64 692:iPTR, VR128:v4f32:$src)
// Emits: (Int_CVTSS2SI64rr:i64 VR128:v4f32:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(691)) {
+ if (CN1 == INT64_C(692)) {
SDNode *Result = Emit_107(N, X86::Int_CVTSS2SI64rr, MVT::i64);
return Result;
}
- // Pattern: (intrinsic_wo_chain:i64 695:iPTR, VR128:v4f32:$src)
+ // Pattern: (intrinsic_wo_chain:i64 696:iPTR, VR128:v4f32:$src)
// Emits: (Int_CVTTSS2SI64rr:i64 VR128:v4f32:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(695)) {
+ if (CN1 == INT64_C(696)) {
SDNode *Result = Emit_107(N, X86::Int_CVTTSS2SI64rr, MVT::i64);
return Result;
}
}
}
- // Pattern: (intrinsic_wo_chain:i64 658:iPTR, GR64:i64:$src1, GR64:i64:$src2)
+ // Pattern: (intrinsic_wo_chain:i64 659:iPTR, GR64:i64:$src1, GR64:i64:$src2)
// Emits: (CRC64r64:i64 GR64:i64:$src1, GR64:i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if ((Subtarget->hasSSE42())) {
@@ -13572,7 +13464,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i64(SDNode *N) {
ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(658)) {
+ if (CN1 == INT64_C(659)) {
SDNode *Result = Emit_110(N, X86::CRC64r64, MVT::i64);
return Result;
}
@@ -13628,610 +13520,608 @@ DISABLE_INLINE SDNode *Emit_117(SDNode *N, unsigned Opc0, MVT::SimpleValueType V
return ResNode;
}
SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
- if ((Subtarget->hasSSSE3())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
+ if ((Subtarget->hasSSSE3())) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v8i8 722:iPTR, (bitconvert:v8i8 (ld:v8i8 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
- // Emits: (PABSBrm64:v8i8 addr:iPTR:$src)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(722)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop64(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_115(N, X86::PABSBrm64, MVT::v8i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v8i8 723:iPTR, (bitconvert:v8i8 (ld:v8i8 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Emits: (PABSBrm64:v8i8 addr:iPTR:$src)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(723)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop64(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_115(N, X86::PABSBrm64, MVT::v8i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v8i8 746:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v8i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
- // Emits: (PSHUFBrm64:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(746)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop64(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_116(N, X86::PSHUFBrm64, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v8i8 747:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v8i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Emits: (PSHUFBrm64:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(747)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop64(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_116(N, X86::PSHUFBrm64, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v8i8 748:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v8i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
- // Emits: (PSIGNBrm64:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(748)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop64(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_116(N, X86::PSIGNBrm64, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v8i8 749:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v8i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Emits: (PSIGNBrm64:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(749)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop64(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_116(N, X86::PSIGNBrm64, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
}
}
- if ((Subtarget->hasMMX())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
+ }
+ if ((Subtarget->hasMMX())) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v8i8 456:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PADDSBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(456)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PADDSBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v8i8 457:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PADDSBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(457)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_116(N, X86::MMX_PADDSBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v8i8 458:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PADDUSBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(458)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PADDUSBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v8i8 459:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PADDUSBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(459)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_116(N, X86::MMX_PADDUSBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v8i8 494:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PSUBSBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(494)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PSUBSBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v8i8 495:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PSUBSBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(495)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_116(N, X86::MMX_PSUBSBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v8i8 496:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PSUBUSBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(496)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PSUBUSBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v8i8 497:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PSUBUSBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(497)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_116(N, X86::MMX_PSUBUSBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v8i8 460:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PAVGBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(460)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PAVGBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v8i8 461:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PAVGBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(461)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_116(N, X86::MMX_PAVGBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v8i8 472:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PMINUBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(472)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PMINUBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v8i8 473:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PMINUBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(473)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_116(N, X86::MMX_PMINUBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v8i8 470:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PMAXUBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(470)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PMAXUBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v8i8 471:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PMAXUBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(471)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_116(N, X86::MMX_PMAXUBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v8i8 462:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PCMPEQBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(462)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PCMPEQBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v8i8 463:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PCMPEQBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(463)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_116(N, X86::MMX_PCMPEQBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v8i8 465:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PCMPGTBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(465)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PCMPGTBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v8i8 466:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PCMPGTBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(466)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_116(N, X86::MMX_PCMPGTBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v8i8 454:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PACKSSWBrm:v8i8 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(454)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PACKSSWBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v8i8 455:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PACKSSWBrm:v8i8 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(455)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_116(N, X86::MMX_PACKSSWBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v8i8 455:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PACKUSWBrm:v8i8 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(455)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PACKUSWBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v8i8 456:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PACKUSWBrm:v8i8 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(456)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_116(N, X86::MMX_PACKUSWBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v8i8 456:iPTR, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v8i8:$src1)
- // Emits: (MMX_PADDSBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(456)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PADDSBrm, MVT::v8i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v8i8 457:iPTR, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v8i8:$src1)
+ // Emits: (MMX_PADDSBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(457)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N10.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_117(N, X86::MMX_PADDSBrm, MVT::v8i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v8i8 458:iPTR, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v8i8:$src1)
- // Emits: (MMX_PADDUSBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(458)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PADDUSBrm, MVT::v8i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v8i8 459:iPTR, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v8i8:$src1)
+ // Emits: (MMX_PADDUSBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(459)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N10.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_117(N, X86::MMX_PADDUSBrm, MVT::v8i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v8i8 460:iPTR, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v8i8:$src1)
- // Emits: (MMX_PAVGBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(460)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PAVGBrm, MVT::v8i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v8i8 461:iPTR, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v8i8:$src1)
+ // Emits: (MMX_PAVGBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(461)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N10.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_117(N, X86::MMX_PAVGBrm, MVT::v8i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v8i8 472:iPTR, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v8i8:$src1)
- // Emits: (MMX_PMINUBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(472)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PMINUBrm, MVT::v8i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v8i8 473:iPTR, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v8i8:$src1)
+ // Emits: (MMX_PMINUBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(473)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N10.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_117(N, X86::MMX_PMINUBrm, MVT::v8i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v8i8 470:iPTR, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v8i8:$src1)
- // Emits: (MMX_PMAXUBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(470)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PMAXUBrm, MVT::v8i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v8i8 471:iPTR, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v8i8:$src1)
+ // Emits: (MMX_PMAXUBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(471)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N10.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_117(N, X86::MMX_PMAXUBrm, MVT::v8i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
@@ -14246,26 +14136,26 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(SDNode *N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v8i8 722:iPTR, VR64:v8i8:$src)
+ // Pattern: (intrinsic_wo_chain:v8i8 723:iPTR, VR64:v8i8:$src)
// Emits: (PABSBrr64:v8i8 VR64:v8i8:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(722)) {
+ if (CN1 == INT64_C(723)) {
SDNode *Result = Emit_107(N, X86::PABSBrr64, MVT::v8i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i8 746:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i8 747:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
// Emits: (PSHUFBrr64:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(746)) {
+ if (CN1 == INT64_C(747)) {
SDNode *Result = Emit_110(N, X86::PSHUFBrr64, MVT::v8i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i8 748:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i8 749:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
// Emits: (PSIGNBrr64:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(748)) {
+ if (CN1 == INT64_C(749)) {
SDNode *Result = Emit_110(N, X86::PSIGNBrr64, MVT::v8i8);
return Result;
}
@@ -14277,90 +14167,90 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(SDNode *N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v8i8 456:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i8 457:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
// Emits: (MMX_PADDSBrr:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(456)) {
+ if (CN1 == INT64_C(457)) {
SDNode *Result = Emit_110(N, X86::MMX_PADDSBrr, MVT::v8i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i8 458:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i8 459:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
// Emits: (MMX_PADDUSBrr:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(458)) {
+ if (CN1 == INT64_C(459)) {
SDNode *Result = Emit_110(N, X86::MMX_PADDUSBrr, MVT::v8i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i8 494:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i8 495:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
// Emits: (MMX_PSUBSBrr:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(494)) {
+ if (CN1 == INT64_C(495)) {
SDNode *Result = Emit_110(N, X86::MMX_PSUBSBrr, MVT::v8i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i8 496:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i8 497:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
// Emits: (MMX_PSUBUSBrr:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(496)) {
+ if (CN1 == INT64_C(497)) {
SDNode *Result = Emit_110(N, X86::MMX_PSUBUSBrr, MVT::v8i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i8 460:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i8 461:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
// Emits: (MMX_PAVGBrr:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(460)) {
+ if (CN1 == INT64_C(461)) {
SDNode *Result = Emit_110(N, X86::MMX_PAVGBrr, MVT::v8i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i8 472:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i8 473:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
// Emits: (MMX_PMINUBrr:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(472)) {
+ if (CN1 == INT64_C(473)) {
SDNode *Result = Emit_110(N, X86::MMX_PMINUBrr, MVT::v8i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i8 470:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i8 471:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
// Emits: (MMX_PMAXUBrr:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(470)) {
+ if (CN1 == INT64_C(471)) {
SDNode *Result = Emit_110(N, X86::MMX_PMAXUBrr, MVT::v8i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i8 462:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i8 463:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
// Emits: (MMX_PCMPEQBrr:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(462)) {
+ if (CN1 == INT64_C(463)) {
SDNode *Result = Emit_110(N, X86::MMX_PCMPEQBrr, MVT::v8i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i8 465:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i8 466:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
// Emits: (MMX_PCMPGTBrr:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(465)) {
+ if (CN1 == INT64_C(466)) {
SDNode *Result = Emit_110(N, X86::MMX_PCMPGTBrr, MVT::v8i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i8 454:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i8 455:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
// Emits: (MMX_PACKSSWBrr:v8i8 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(454)) {
+ if (CN1 == INT64_C(455)) {
SDNode *Result = Emit_110(N, X86::MMX_PACKSSWBrr, MVT::v8i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i8 455:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i8 456:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
// Emits: (MMX_PACKUSWBrr:v8i8 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(455)) {
+ if (CN1 == INT64_C(456)) {
SDNode *Result = Emit_110(N, X86::MMX_PACKUSWBrr, MVT::v8i8);
return Result;
}
@@ -14514,94 +14404,18 @@ DISABLE_INLINE SDNode *Emit_126(SDNode *N, unsigned Opc0, MVT::SimpleValueType V
return ResNode;
}
SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
- if ((Subtarget->hasSSE41())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(618)) {
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (intrinsic_wo_chain:v16i8 618:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (imm:i32):$src3)
- // Emits: (MPSADBWrmi:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2, (imm:i32):$src3)
- // Pattern complexity = 36 cost = 1 size = 3
- {
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4)) {
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant &&
- N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_119(N, X86::MPSADBWrmi, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v16i8 618:iPTR, (bitconvert:v16i8 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v16i8:$src1, (imm:i32):$src3)
- // Emits: (MPSADBWrmi:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2, (imm:i32):$src3)
- // Pattern complexity = 36 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant &&
- N10.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_126(N, X86::MPSADBWrmi, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
+ if ((Subtarget->hasSSE41())) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(619)) {
+ SDValue N1 = N->getOperand(1);
- // Pattern: (intrinsic_wo_chain:v16i8 542:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PADDSBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(542)) {
- SDValue N1 = N->getOperand(1);
+ // Pattern: (intrinsic_wo_chain:v16i8 619:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (imm:i32):$src3)
+ // Emits: (MPSADBWrmi:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2, (imm:i32):$src3)
+ // Pattern complexity = 36 cost = 1 size = 3
+ {
SDValue N2 = N->getOperand(2);
if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
@@ -14619,537 +14433,611 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(SDNode *N) {
SDValue CPTmpN201_2;
SDValue CPTmpN201_3;
SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PADDSBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4)) {
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant &&
+ N20.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_119(N, X86::MPSADBWrmi, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
}
}
}
}
}
- // Pattern: (intrinsic_wo_chain:v16i8 544:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PADDUSBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(544)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PADDUSBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ // Pattern: (intrinsic_wo_chain:v16i8 619:iPTR, (bitconvert:v16i8 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v16i8:$src1, (imm:i32):$src3)
+ // Emits: (MPSADBWrmi:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2, (imm:i32):$src3)
+ // Pattern complexity = 36 cost = 1 size = 3
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant &&
+ N10.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_126(N, X86::MPSADBWrmi, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
}
}
}
+ }
+ }
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v16i8 584:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PSUBSBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(584)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PSUBSBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v16i8 543:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PADDSBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(543)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_116(N, X86::PADDSBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v16i8 586:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PSUBUSBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(586)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PSUBUSBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v16i8 545:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PADDUSBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(545)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_116(N, X86::PADDUSBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v16i8 546:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PAVGBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(546)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PAVGBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v16i8 585:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PSUBSBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(585)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_116(N, X86::PSUBSBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v16i8 558:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PMINUBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(558)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PMINUBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v16i8 587:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PSUBUSBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(587)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_116(N, X86::PSUBUSBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v16i8 556:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PMAXUBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(556)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PMAXUBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v16i8 547:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PAVGBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(547)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_116(N, X86::PAVGBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v16i8 548:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PCMPEQBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(548)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PCMPEQBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v16i8 559:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PMINUBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(559)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_116(N, X86::PMINUBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v16i8 551:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PCMPGTBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(551)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PCMPGTBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v16i8 557:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PMAXUBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(557)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_116(N, X86::PMAXUBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v16i8 540:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PACKSSWBrm:v16i8 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(540)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PACKSSWBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v16i8 549:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PCMPEQBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(549)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_116(N, X86::PCMPEQBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v16i8 541:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PACKUSWBrm:v16i8 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(541)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PACKUSWBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v16i8 552:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PCMPGTBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(552)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_116(N, X86::PCMPGTBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 541:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PACKSSWBrm:v16i8 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(541)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_116(N, X86::PACKSSWBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v16i8 542:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PACKUSWBrm:v16i8 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(542)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_116(N, X86::PACKUSWBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
}
}
- if ((Subtarget->hasSSSE3())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
+ }
+ if ((Subtarget->hasSSSE3())) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v16i8 723:iPTR, (bitconvert:v16i8 (ld:v16i8 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PABSBrm128:v16i8 addr:iPTR:$src)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(723)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_115(N, X86::PABSBrm128, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v16i8 724:iPTR, (bitconvert:v16i8 (ld:v16i8 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PABSBrm128:v16i8 addr:iPTR:$src)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(724)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_115(N, X86::PABSBrm128, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v16i8 747:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PSHUFBrm128:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(747)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_116(N, X86::PSHUFBrm128, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v16i8 748:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PSHUFBrm128:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(748)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_116(N, X86::PSHUFBrm128, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v16i8 749:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PSIGNBrm128:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(749)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_116(N, X86::PSIGNBrm128, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v16i8 750:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PSIGNBrm128:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(750)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_116(N, X86::PSIGNBrm128, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
}
}
- if ((Subtarget->hasSSE41())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
+ }
+ if ((Subtarget->hasSSE41())) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v16i8 631:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PMINSBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(631)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_116(N, X86::PMINSBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v16i8 632:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PMINSBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(632)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_116(N, X86::PMINSBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v16i8 627:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PMAXSBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(627)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_116(N, X86::PMAXSBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v16i8 628:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PMAXSBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(628)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_116(N, X86::PMAXSBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v16i8 620:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), XMM0:v16i8)
- // Emits: (PBLENDVBrm0:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(620)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4)) {
- SDValue N3 = N->getOperand(3);
- if (N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_121(N, X86::PBLENDVBrm0, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v16i8 621:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), XMM0:v16i8)
+ // Emits: (PBLENDVBrm0:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(621)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4)) {
+ SDValue N3 = N->getOperand(3);
+ if (N20.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_121(N, X86::PBLENDVBrm0, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
@@ -15157,171 +15045,171 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(SDNode *N) {
}
}
}
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v16i8 542:iPTR, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v16i8:$src1)
- // Emits: (PADDSBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(542)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PADDSBrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v16i8 543:iPTR, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v16i8:$src1)
+ // Emits: (PADDSBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(543)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_117(N, X86::PADDSBrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v16i8 544:iPTR, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v16i8:$src1)
- // Emits: (PADDUSBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(544)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PADDUSBrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v16i8 545:iPTR, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v16i8:$src1)
+ // Emits: (PADDUSBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(545)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_117(N, X86::PADDUSBrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v16i8 546:iPTR, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v16i8:$src1)
- // Emits: (PAVGBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(546)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PAVGBrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v16i8 547:iPTR, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v16i8:$src1)
+ // Emits: (PAVGBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(547)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_117(N, X86::PAVGBrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v16i8 558:iPTR, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v16i8:$src1)
- // Emits: (PMINUBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(558)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PMINUBrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v16i8 559:iPTR, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v16i8:$src1)
+ // Emits: (PMINUBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(559)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_117(N, X86::PMINUBrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v16i8 556:iPTR, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v16i8:$src1)
- // Emits: (PMAXUBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(556)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PMAXUBrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v16i8 557:iPTR, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v16i8:$src1)
+ // Emits: (PMAXUBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(557)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_117(N, X86::PMAXUBrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
@@ -15329,72 +15217,72 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(SDNode *N) {
}
}
}
- if ((Subtarget->hasSSE41())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
+ }
+ if ((Subtarget->hasSSE41())) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v16i8 631:iPTR, (bitconvert:v16i8 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v16i8:$src1)
- // Emits: (PMINSBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(631)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_117(N, X86::PMINSBrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v16i8 632:iPTR, (bitconvert:v16i8 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v16i8:$src1)
+ // Emits: (PMINSBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(632)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N10.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_117(N, X86::PMINSBrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v16i8 627:iPTR, (bitconvert:v16i8 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v16i8:$src1)
- // Emits: (PMAXSBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(627)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_117(N, X86::PMAXSBrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v16i8 628:iPTR, (bitconvert:v16i8 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v16i8:$src1)
+ // Emits: (PMAXSBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(628)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N10.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_117(N, X86::PMAXSBrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
@@ -15402,67 +15290,67 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(SDNode *N) {
}
}
}
- if ((Subtarget->hasSSE42())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
+ }
+ if ((Subtarget->hasSSE42())) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v16i8 674:iPTR, VR128:v16i8:$src1, (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i8):$src3)
- // Emits: (PCMPISTRM128MEM:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2, (imm:i8):$src3)
- // Pattern complexity = 33 cost = 11 size = 3
- if (CN1 == INT64_C(674)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_123(N, X86::PCMPISTRM128MEM, MVT::v16i8, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v16i8 675:iPTR, VR128:v16i8:$src1, (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i8):$src3)
+ // Emits: (PCMPISTRM128MEM:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2, (imm:i8):$src3)
+ // Pattern complexity = 33 cost = 11 size = 3
+ if (CN1 == INT64_C(675)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode())) {
+ SDValue N21 = N2.getNode()->getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_123(N, X86::PCMPISTRM128MEM, MVT::v16i8, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v16i8 666:iPTR, VR128:v16i8:$src1, EAX:i32, (ld:v16i8 addr:iPTR:$src3)<<P:Predicate_unindexedload>><<P:Predicate_load>>, EDX:i32, (imm:i8):$src5)
- // Emits: (PCMPESTRM128MEM:v16i8 VR128:v16i8:$src1, addr:iPTR:$src3, (imm:i8):$src5)
- // Pattern complexity = 33 cost = 11 size = 3
- if (CN1 == INT64_C(666)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::LOAD &&
- N3.hasOneUse() &&
- IsLegalAndProfitableToFold(N3.getNode(), N, N)) {
- SDValue Chain3 = N3.getNode()->getOperand(0);
- if (Predicate_unindexedload(N3.getNode()) &&
- Predicate_load(N3.getNode())) {
- SDValue N31 = N3.getNode()->getOperand(1);
- SDValue CPTmpN31_0;
- SDValue CPTmpN31_1;
- SDValue CPTmpN31_2;
- SDValue CPTmpN31_3;
- SDValue CPTmpN31_4;
- if (SelectAddr(N, N31, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4)) {
- SDValue N4 = N->getOperand(4);
- SDValue N5 = N->getOperand(5);
- if (N5.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_125(N, X86::PCMPESTRM128MEM, MVT::v16i8, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v16i8 667:iPTR, VR128:v16i8:$src1, EAX:i32, (ld:v16i8 addr:iPTR:$src3)<<P:Predicate_unindexedload>><<P:Predicate_load>>, EDX:i32, (imm:i8):$src5)
+ // Emits: (PCMPESTRM128MEM:v16i8 VR128:v16i8:$src1, addr:iPTR:$src3, (imm:i8):$src5)
+ // Pattern complexity = 33 cost = 11 size = 3
+ if (CN1 == INT64_C(667)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::LOAD &&
+ N3.hasOneUse() &&
+ IsLegalAndProfitableToFold(N3.getNode(), N, N)) {
+ SDValue Chain3 = N3.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N3.getNode()) &&
+ Predicate_load(N3.getNode())) {
+ SDValue N31 = N3.getNode()->getOperand(1);
+ SDValue CPTmpN31_0;
+ SDValue CPTmpN31_1;
+ SDValue CPTmpN31_2;
+ SDValue CPTmpN31_3;
+ SDValue CPTmpN31_4;
+ if (SelectAddr(N, N31, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4)) {
+ SDValue N4 = N->getOperand(4);
+ SDValue N5 = N->getOperand(5);
+ if (N5.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_125(N, X86::PCMPESTRM128MEM, MVT::v16i8, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4);
+ return Result;
}
}
}
@@ -15471,7 +15359,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(SDNode *N) {
}
}
- // Pattern: (intrinsic_wo_chain:v16i8 618:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i32):$src3)
+ // Pattern: (intrinsic_wo_chain:v16i8 619:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i32):$src3)
// Emits: (MPSADBWrri:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i32):$src3)
// Pattern complexity = 11 cost = 1 size = 3
if ((Subtarget->hasSSE41())) {
@@ -15479,7 +15367,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(SDNode *N) {
ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(618)) {
+ if (CN1 == INT64_C(619)) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
SDValue N3 = N->getOperand(3);
@@ -15496,10 +15384,10 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(SDNode *N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v16i8 674:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
+ // Pattern: (intrinsic_wo_chain:v16i8 675:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
// Emits: (PCMPISTRM128REG:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
// Pattern complexity = 11 cost = 11 size = 3
- if (CN1 == INT64_C(674)) {
+ if (CN1 == INT64_C(675)) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
SDValue N3 = N->getOperand(3);
@@ -15509,10 +15397,10 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(SDNode *N) {
}
}
- // Pattern: (intrinsic_wo_chain:v16i8 666:iPTR, VR128:v16i8:$src1, EAX:i32, VR128:v16i8:$src3, EDX:i32, (imm:i8):$src5)
+ // Pattern: (intrinsic_wo_chain:v16i8 667:iPTR, VR128:v16i8:$src1, EAX:i32, VR128:v16i8:$src3, EDX:i32, (imm:i8):$src5)
// Emits: (PCMPESTRM128REG:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src3, (imm:i8):$src5)
// Pattern complexity = 11 cost = 11 size = 3
- if (CN1 == INT64_C(666)) {
+ if (CN1 == INT64_C(667)) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
SDValue N3 = N->getOperand(3);
@@ -15531,90 +15419,90 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(SDNode *N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v16i8 542:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern: (intrinsic_wo_chain:v16i8 543:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
// Emits: (PADDSBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(542)) {
+ if (CN1 == INT64_C(543)) {
SDNode *Result = Emit_110(N, X86::PADDSBrr, MVT::v16i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v16i8 544:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern: (intrinsic_wo_chain:v16i8 545:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
// Emits: (PADDUSBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(544)) {
+ if (CN1 == INT64_C(545)) {
SDNode *Result = Emit_110(N, X86::PADDUSBrr, MVT::v16i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v16i8 584:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern: (intrinsic_wo_chain:v16i8 585:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
// Emits: (PSUBSBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(584)) {
+ if (CN1 == INT64_C(585)) {
SDNode *Result = Emit_110(N, X86::PSUBSBrr, MVT::v16i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v16i8 586:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern: (intrinsic_wo_chain:v16i8 587:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
// Emits: (PSUBUSBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(586)) {
+ if (CN1 == INT64_C(587)) {
SDNode *Result = Emit_110(N, X86::PSUBUSBrr, MVT::v16i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v16i8 546:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern: (intrinsic_wo_chain:v16i8 547:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
// Emits: (PAVGBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(546)) {
+ if (CN1 == INT64_C(547)) {
SDNode *Result = Emit_110(N, X86::PAVGBrr, MVT::v16i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v16i8 558:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern: (intrinsic_wo_chain:v16i8 559:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
// Emits: (PMINUBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(558)) {
+ if (CN1 == INT64_C(559)) {
SDNode *Result = Emit_110(N, X86::PMINUBrr, MVT::v16i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v16i8 556:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern: (intrinsic_wo_chain:v16i8 557:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
// Emits: (PMAXUBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(556)) {
+ if (CN1 == INT64_C(557)) {
SDNode *Result = Emit_110(N, X86::PMAXUBrr, MVT::v16i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v16i8 548:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern: (intrinsic_wo_chain:v16i8 549:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
// Emits: (PCMPEQBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(548)) {
+ if (CN1 == INT64_C(549)) {
SDNode *Result = Emit_110(N, X86::PCMPEQBrr, MVT::v16i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v16i8 551:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern: (intrinsic_wo_chain:v16i8 552:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
// Emits: (PCMPGTBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(551)) {
+ if (CN1 == INT64_C(552)) {
SDNode *Result = Emit_110(N, X86::PCMPGTBrr, MVT::v16i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v16i8 540:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v16i8 541:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
// Emits: (PACKSSWBrr:v16i8 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(540)) {
+ if (CN1 == INT64_C(541)) {
SDNode *Result = Emit_110(N, X86::PACKSSWBrr, MVT::v16i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v16i8 541:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v16i8 542:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
// Emits: (PACKUSWBrr:v16i8 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(541)) {
+ if (CN1 == INT64_C(542)) {
SDNode *Result = Emit_110(N, X86::PACKUSWBrr, MVT::v16i8);
return Result;
}
@@ -15626,26 +15514,26 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(SDNode *N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v16i8 723:iPTR, VR128:v16i8:$src)
+ // Pattern: (intrinsic_wo_chain:v16i8 724:iPTR, VR128:v16i8:$src)
// Emits: (PABSBrr128:v16i8 VR128:v16i8:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(723)) {
+ if (CN1 == INT64_C(724)) {
SDNode *Result = Emit_107(N, X86::PABSBrr128, MVT::v16i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v16i8 747:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern: (intrinsic_wo_chain:v16i8 748:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
// Emits: (PSHUFBrr128:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(747)) {
+ if (CN1 == INT64_C(748)) {
SDNode *Result = Emit_110(N, X86::PSHUFBrr128, MVT::v16i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v16i8 749:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern: (intrinsic_wo_chain:v16i8 750:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
// Emits: (PSIGNBrr128:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(749)) {
+ if (CN1 == INT64_C(750)) {
SDNode *Result = Emit_110(N, X86::PSIGNBrr128, MVT::v16i8);
return Result;
}
@@ -15657,26 +15545,26 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(SDNode *N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v16i8 631:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern: (intrinsic_wo_chain:v16i8 632:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
// Emits: (PMINSBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(631)) {
+ if (CN1 == INT64_C(632)) {
SDNode *Result = Emit_110(N, X86::PMINSBrr, MVT::v16i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v16i8 627:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern: (intrinsic_wo_chain:v16i8 628:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
// Emits: (PMAXSBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(627)) {
+ if (CN1 == INT64_C(628)) {
SDNode *Result = Emit_110(N, X86::PMAXSBrr, MVT::v16i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v16i8 620:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2, XMM0:v16i8)
+ // Pattern: (intrinsic_wo_chain:v16i8 621:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2, XMM0:v16i8)
// Emits: (PBLENDVBrr0:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(620)) {
+ if (CN1 == INT64_C(621)) {
SDNode *Result = Emit_120(N, X86::PBLENDVBrr0, MVT::v16i8);
return Result;
}
@@ -15695,805 +15583,803 @@ DISABLE_INLINE SDNode *Emit_127(SDNode *N, unsigned Opc0, MVT::SimpleValueType V
return CurDAG->SelectNodeTo(N, Opc0, VT0, N1, Tmp3);
}
SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
- if ((Subtarget->hasSSSE3())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
+ if ((Subtarget->hasSSSE3())) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v4i16 726:iPTR, (bitconvert:v4i16 (ld:v4i16 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
- // Emits: (PABSWrm64:v4i16 addr:iPTR:$src)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(726)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop64(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_115(N, X86::PABSWrm64, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i16 727:iPTR, (bitconvert:v4i16 (ld:v4i16 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Emits: (PABSWrm64:v4i16 addr:iPTR:$src)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(727)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop64(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_115(N, X86::PABSWrm64, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4i16 734:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v4i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
- // Emits: (PHADDWrm64:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(734)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop64(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_116(N, X86::PHADDWrm64, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i16 735:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v4i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Emits: (PHADDWrm64:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(735)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop64(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_116(N, X86::PHADDWrm64, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4i16 732:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v4i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
- // Emits: (PHADDSWrm64:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(732)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop64(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_116(N, X86::PHADDSWrm64, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i16 733:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v4i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Emits: (PHADDSWrm64:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(733)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop64(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_116(N, X86::PHADDSWrm64, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4i16 740:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v4i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
- // Emits: (PHSUBWrm64:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(740)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop64(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_116(N, X86::PHSUBWrm64, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i16 741:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v4i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Emits: (PHSUBWrm64:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(741)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop64(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_116(N, X86::PHSUBWrm64, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4i16 738:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v4i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
- // Emits: (PHSUBSWrm64:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(738)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop64(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_116(N, X86::PHSUBSWrm64, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i16 739:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v4i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Emits: (PHSUBSWrm64:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(739)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop64(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_116(N, X86::PHSUBSWrm64, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4i16 742:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v8i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
- // Emits: (PMADDUBSWrm64:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(742)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop64(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_116(N, X86::PMADDUBSWrm64, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i16 743:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v8i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Emits: (PMADDUBSWrm64:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(743)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop64(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v8i8) {
+ SDNode *Result = Emit_116(N, X86::PMADDUBSWrm64, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4i16 744:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v4i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
- // Emits: (PMULHRSWrm64:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(744)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop64(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_116(N, X86::PMULHRSWrm64, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i16 745:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v4i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Emits: (PMULHRSWrm64:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(745)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop64(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_116(N, X86::PMULHRSWrm64, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4i16 752:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v4i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
- // Emits: (PSIGNWrm64:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(752)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop64(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_116(N, X86::PSIGNWrm64, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i16 753:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v4i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Emits: (PSIGNWrm64:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(753)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop64(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_116(N, X86::PSIGNWrm64, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
}
}
- if ((Subtarget->hasMMX())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
+ }
+ if ((Subtarget->hasMMX())) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v4i16 457:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PADDSWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(457)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PADDSWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i16 458:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PADDSWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(458)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_116(N, X86::MMX_PADDSWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4i16 459:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PADDUSWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(459)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PADDUSWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i16 460:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PADDUSWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(460)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_116(N, X86::MMX_PADDUSWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4i16 495:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PSUBSWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(495)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PSUBSWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i16 496:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PSUBSWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(496)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_116(N, X86::MMX_PSUBSWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4i16 497:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PSUBUSWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(497)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PSUBUSWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i16 498:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PSUBUSWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(498)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_116(N, X86::MMX_PSUBUSWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4i16 474:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PMULHWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(474)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PMULHWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i16 475:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PMULHWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(475)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_116(N, X86::MMX_PMULHWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4i16 475:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PMULHUWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(475)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PMULHUWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i16 476:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PMULHUWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(476)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_116(N, X86::MMX_PMULHUWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4i16 461:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PAVGWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(461)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PAVGWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i16 462:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PAVGWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(462)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_116(N, X86::MMX_PAVGWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4i16 471:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PMINSWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(471)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PMINSWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i16 472:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PMINSWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(472)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_116(N, X86::MMX_PMINSWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4i16 469:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PMAXSWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(469)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PMAXSWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i16 470:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PMAXSWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(470)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_116(N, X86::MMX_PMAXSWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4i16 477:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PSADBWrm:v4i16 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(477)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PSADBWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i16 478:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PSADBWrm:v4i16 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(478)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_116(N, X86::MMX_PSADBWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4i16 490:iPTR, VR64:v4i16:$src1, (bitconvert:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PSRLWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(490)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PSRLWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i16 491:iPTR, VR64:v4i16:$src1, (bitconvert:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PSRLWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(491)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_116(N, X86::MMX_PSRLWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4i16 480:iPTR, VR64:v4i16:$src1, (bitconvert:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PSLLWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(480)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PSLLWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i16 481:iPTR, VR64:v4i16:$src1, (bitconvert:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PSLLWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(481)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_116(N, X86::MMX_PSLLWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4i16 485:iPTR, VR64:v4i16:$src1, (bitconvert:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PSRAWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(485)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PSRAWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i16 486:iPTR, VR64:v4i16:$src1, (bitconvert:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PSRAWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(486)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_116(N, X86::MMX_PSRAWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4i16 464:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PCMPEQWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(464)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PCMPEQWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i16 465:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PCMPEQWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(465)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_116(N, X86::MMX_PCMPEQWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4i16 467:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PCMPGTWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(467)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PCMPGTWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i16 468:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PCMPGTWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(468)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_116(N, X86::MMX_PCMPGTWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4i16 453:iPTR, VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PACKSSDWrm:v4i16 VR64:v2i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(453)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PACKSSDWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i16 454:iPTR, VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PACKSSDWrm:v4i16 VR64:v2i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(454)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_116(N, X86::MMX_PACKSSDWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4i16 744:iPTR, (bitconvert:v4i16 (ld:v4i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>), VR64:v4i16:$src1)
- // Emits: (PMULHRSWrm64:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if ((Subtarget->hasSSSE3())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(744)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop64(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_117(N, X86::PMULHRSWrm64, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i16 745:iPTR, (bitconvert:v4i16 (ld:v4i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>), VR64:v4i16:$src1)
+ // Emits: (PMULHRSWrm64:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if ((Subtarget->hasSSSE3())) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(745)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop64(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N10.getValueType() == MVT::v4i16) {
+ SDNode *Result = Emit_117(N, X86::PMULHRSWrm64, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
@@ -16501,280 +16387,273 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(SDNode *N) {
}
}
}
- if ((Subtarget->hasMMX())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
+ }
+ if ((Subtarget->hasMMX())) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v4i16 457:iPTR, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v4i16:$src1)
- // Emits: (MMX_PADDSWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(457)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PADDSWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i16 458:iPTR, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v4i16:$src1)
+ // Emits: (MMX_PADDSWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(458)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N10.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_117(N, X86::MMX_PADDSWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4i16 459:iPTR, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v4i16:$src1)
- // Emits: (MMX_PADDUSWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(459)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PADDUSWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i16 460:iPTR, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v4i16:$src1)
+ // Emits: (MMX_PADDUSWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(460)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N10.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_117(N, X86::MMX_PADDUSWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4i16 474:iPTR, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v4i16:$src1)
- // Emits: (MMX_PMULHWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(474)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PMULHWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i16 475:iPTR, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v4i16:$src1)
+ // Emits: (MMX_PMULHWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(475)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N10.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_117(N, X86::MMX_PMULHWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4i16 475:iPTR, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v4i16:$src1)
- // Emits: (MMX_PMULHUWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(475)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PMULHUWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i16 476:iPTR, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v4i16:$src1)
+ // Emits: (MMX_PMULHUWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(476)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N10.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_117(N, X86::MMX_PMULHUWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4i16 461:iPTR, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v4i16:$src1)
- // Emits: (MMX_PAVGWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(461)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PAVGWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i16 462:iPTR, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v4i16:$src1)
+ // Emits: (MMX_PAVGWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(462)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N10.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_117(N, X86::MMX_PAVGWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4i16 471:iPTR, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v4i16:$src1)
- // Emits: (MMX_PMINSWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(471)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PMINSWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i16 472:iPTR, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v4i16:$src1)
+ // Emits: (MMX_PMINSWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(472)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N10.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_117(N, X86::MMX_PMINSWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4i16 469:iPTR, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v4i16:$src1)
- // Emits: (MMX_PMAXSWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(469)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PMAXSWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i16 470:iPTR, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v4i16:$src1)
+ // Emits: (MMX_PMAXSWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(470)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N10.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_117(N, X86::MMX_PMAXSWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4i16 477:iPTR, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v8i8:$src1)
- // Emits: (MMX_PSADBWrm:v4i16 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(477)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PSADBWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i16 478:iPTR, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v8i8:$src1)
+ // Emits: (MMX_PSADBWrm:v4i16 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(478)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N10.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_117(N, X86::MMX_PSADBWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
}
}
- }
- }
- if ((Subtarget->hasMMX())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v4i16 493:iPTR, VR64:v4i16:$src1, (imm:i32):$src2)
+ // Pattern: (intrinsic_wo_chain:v4i16 494:iPTR, VR64:v4i16:$src1, (imm:i32):$src2)
// Emits: (MMX_PSRLWri:v4i16 VR64:v4i16:$src1, (imm:i32):$src2)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(493)) {
+ if (CN1 == INT64_C(494)) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
if (N2.getNode()->getOpcode() == ISD::Constant) {
@@ -16783,10 +16662,10 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(SDNode *N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4i16 483:iPTR, VR64:v4i16:$src1, (imm:i32):$src2)
+ // Pattern: (intrinsic_wo_chain:v4i16 484:iPTR, VR64:v4i16:$src1, (imm:i32):$src2)
// Emits: (MMX_PSLLWri:v4i16 VR64:v4i16:$src1, (imm:i32):$src2)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(483)) {
+ if (CN1 == INT64_C(484)) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
if (N2.getNode()->getOpcode() == ISD::Constant) {
@@ -16795,10 +16674,10 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(SDNode *N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4i16 487:iPTR, VR64:v4i16:$src1, (imm:i32):$src2)
+ // Pattern: (intrinsic_wo_chain:v4i16 488:iPTR, VR64:v4i16:$src1, (imm:i32):$src2)
// Emits: (MMX_PSRAWri:v4i16 VR64:v4i16:$src1, (imm:i32):$src2)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(487)) {
+ if (CN1 == INT64_C(488)) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
if (N2.getNode()->getOpcode() == ISD::Constant) {
@@ -16814,66 +16693,66 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(SDNode *N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v4i16 726:iPTR, VR64:v4i16:$src)
+ // Pattern: (intrinsic_wo_chain:v4i16 727:iPTR, VR64:v4i16:$src)
// Emits: (PABSWrr64:v4i16 VR64:v4i16:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(726)) {
+ if (CN1 == INT64_C(727)) {
SDNode *Result = Emit_107(N, X86::PABSWrr64, MVT::v4i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i16 734:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i16 735:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
// Emits: (PHADDWrr64:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(734)) {
+ if (CN1 == INT64_C(735)) {
SDNode *Result = Emit_110(N, X86::PHADDWrr64, MVT::v4i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i16 732:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i16 733:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
// Emits: (PHADDSWrr64:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(732)) {
+ if (CN1 == INT64_C(733)) {
SDNode *Result = Emit_110(N, X86::PHADDSWrr64, MVT::v4i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i16 740:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i16 741:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
// Emits: (PHSUBWrr64:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(740)) {
+ if (CN1 == INT64_C(741)) {
SDNode *Result = Emit_110(N, X86::PHSUBWrr64, MVT::v4i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i16 738:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i16 739:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
// Emits: (PHSUBSWrr64:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(738)) {
+ if (CN1 == INT64_C(739)) {
SDNode *Result = Emit_110(N, X86::PHSUBSWrr64, MVT::v4i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i16 742:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i16 743:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
// Emits: (PMADDUBSWrr64:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(742)) {
+ if (CN1 == INT64_C(743)) {
SDNode *Result = Emit_110(N, X86::PMADDUBSWrr64, MVT::v4i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i16 744:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i16 745:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
// Emits: (PMULHRSWrr64:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(744)) {
+ if (CN1 == INT64_C(745)) {
SDNode *Result = Emit_110(N, X86::PMULHRSWrr64, MVT::v4i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i16 752:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i16 753:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
// Emits: (PSIGNWrr64:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(752)) {
+ if (CN1 == INT64_C(753)) {
SDNode *Result = Emit_110(N, X86::PSIGNWrr64, MVT::v4i16);
return Result;
}
@@ -16885,130 +16764,130 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(SDNode *N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v4i16 457:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i16 458:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
// Emits: (MMX_PADDSWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(457)) {
+ if (CN1 == INT64_C(458)) {
SDNode *Result = Emit_110(N, X86::MMX_PADDSWrr, MVT::v4i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i16 459:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i16 460:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
// Emits: (MMX_PADDUSWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(459)) {
+ if (CN1 == INT64_C(460)) {
SDNode *Result = Emit_110(N, X86::MMX_PADDUSWrr, MVT::v4i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i16 495:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i16 496:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
// Emits: (MMX_PSUBSWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(495)) {
+ if (CN1 == INT64_C(496)) {
SDNode *Result = Emit_110(N, X86::MMX_PSUBSWrr, MVT::v4i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i16 497:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i16 498:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
// Emits: (MMX_PSUBUSWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(497)) {
+ if (CN1 == INT64_C(498)) {
SDNode *Result = Emit_110(N, X86::MMX_PSUBUSWrr, MVT::v4i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i16 474:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i16 475:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
// Emits: (MMX_PMULHWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(474)) {
+ if (CN1 == INT64_C(475)) {
SDNode *Result = Emit_110(N, X86::MMX_PMULHWrr, MVT::v4i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i16 475:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i16 476:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
// Emits: (MMX_PMULHUWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(475)) {
+ if (CN1 == INT64_C(476)) {
SDNode *Result = Emit_110(N, X86::MMX_PMULHUWrr, MVT::v4i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i16 461:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i16 462:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
// Emits: (MMX_PAVGWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(461)) {
+ if (CN1 == INT64_C(462)) {
SDNode *Result = Emit_110(N, X86::MMX_PAVGWrr, MVT::v4i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i16 471:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i16 472:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
// Emits: (MMX_PMINSWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(471)) {
+ if (CN1 == INT64_C(472)) {
SDNode *Result = Emit_110(N, X86::MMX_PMINSWrr, MVT::v4i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i16 469:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i16 470:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
// Emits: (MMX_PMAXSWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(469)) {
+ if (CN1 == INT64_C(470)) {
SDNode *Result = Emit_110(N, X86::MMX_PMAXSWrr, MVT::v4i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i16 477:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i16 478:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
// Emits: (MMX_PSADBWrr:v4i16 VR64:v8i8:$src1, VR64:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(477)) {
+ if (CN1 == INT64_C(478)) {
SDNode *Result = Emit_110(N, X86::MMX_PSADBWrr, MVT::v4i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i16 490:iPTR, VR64:v4i16:$src1, VR64:v1i64:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i16 491:iPTR, VR64:v4i16:$src1, VR64:v1i64:$src2)
// Emits: (MMX_PSRLWrr:v4i16 VR64:v4i16:$src1, VR64:v1i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(490)) {
+ if (CN1 == INT64_C(491)) {
SDNode *Result = Emit_110(N, X86::MMX_PSRLWrr, MVT::v4i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i16 480:iPTR, VR64:v4i16:$src1, VR64:v1i64:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i16 481:iPTR, VR64:v4i16:$src1, VR64:v1i64:$src2)
// Emits: (MMX_PSLLWrr:v4i16 VR64:v4i16:$src1, VR64:v1i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(480)) {
+ if (CN1 == INT64_C(481)) {
SDNode *Result = Emit_110(N, X86::MMX_PSLLWrr, MVT::v4i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i16 485:iPTR, VR64:v4i16:$src1, VR64:v1i64:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i16 486:iPTR, VR64:v4i16:$src1, VR64:v1i64:$src2)
// Emits: (MMX_PSRAWrr:v4i16 VR64:v4i16:$src1, VR64:v1i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(485)) {
+ if (CN1 == INT64_C(486)) {
SDNode *Result = Emit_110(N, X86::MMX_PSRAWrr, MVT::v4i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i16 464:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i16 465:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
// Emits: (MMX_PCMPEQWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(464)) {
+ if (CN1 == INT64_C(465)) {
SDNode *Result = Emit_110(N, X86::MMX_PCMPEQWrr, MVT::v4i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i16 467:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i16 468:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
// Emits: (MMX_PCMPGTWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(467)) {
+ if (CN1 == INT64_C(468)) {
SDNode *Result = Emit_110(N, X86::MMX_PCMPGTWrr, MVT::v4i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i16 453:iPTR, VR64:v2i32:$src1, VR64:v2i32:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i16 454:iPTR, VR64:v2i32:$src1, VR64:v2i32:$src2)
// Emits: (MMX_PACKSSDWrr:v4i16 VR64:v2i32:$src1, VR64:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(453)) {
+ if (CN1 == INT64_C(454)) {
SDNode *Result = Emit_110(N, X86::MMX_PACKSSDWrr, MVT::v4i16);
return Result;
}
@@ -17062,194 +16941,192 @@ DISABLE_INLINE SDNode *Emit_130(SDNode *N, unsigned Opc0, MVT::SimpleValueType V
return ResNode;
}
SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
- if ((Subtarget->hasSSE41())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
+ if ((Subtarget->hasSSE41())) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v8i16 637:iPTR, (bitconvert:v16i8 (X86vzmovl:v2i64 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>))))
- // Emits: (PMOVSXBWrm:v8i16 addr:iPTR:$src)
- // Pattern complexity = 39 cost = 1 size = 3
- if (CN1 == INT64_C(637)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == X86ISD::VZEXT_MOVL &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N100.hasOneUse()) {
- SDValue N1000 = N100.getNode()->getOperand(0);
- if (N1000.getNode()->getOpcode() == ISD::LOAD &&
- N1000.hasOneUse() &&
- IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N)) {
- SDValue Chain1000 = N1000.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1000.getNode()) &&
- Predicate_load(N1000.getNode()) &&
- Predicate_loadi64(N1000.getNode())) {
- SDValue N10001 = N1000.getNode()->getOperand(1);
- SDValue CPTmpN10001_0;
- SDValue CPTmpN10001_1;
- SDValue CPTmpN10001_2;
- SDValue CPTmpN10001_3;
- SDValue CPTmpN10001_4;
- if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
- N10.getValueType() == MVT::v2i64 &&
- N1000.getValueType() == MVT::i64) {
- SDNode *Result = Emit_129(N, X86::PMOVSXBWrm, MVT::v8i16, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v8i16 638:iPTR, (bitconvert:v16i8 (X86vzmovl:v2i64 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>))))
+ // Emits: (PMOVSXBWrm:v8i16 addr:iPTR:$src)
+ // Pattern complexity = 39 cost = 1 size = 3
+ if (CN1 == INT64_C(638)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == X86ISD::VZEXT_MOVL &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N100.hasOneUse()) {
+ SDValue N1000 = N100.getNode()->getOperand(0);
+ if (N1000.getNode()->getOpcode() == ISD::LOAD &&
+ N1000.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N)) {
+ SDValue Chain1000 = N1000.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1000.getNode()) &&
+ Predicate_load(N1000.getNode()) &&
+ Predicate_loadi64(N1000.getNode())) {
+ SDValue N10001 = N1000.getNode()->getOperand(1);
+ SDValue CPTmpN10001_0;
+ SDValue CPTmpN10001_1;
+ SDValue CPTmpN10001_2;
+ SDValue CPTmpN10001_3;
+ SDValue CPTmpN10001_4;
+ if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
+ N10.getValueType() == MVT::v2i64 &&
+ N1000.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_129(N, X86::PMOVSXBWrm, MVT::v8i16, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
+ return Result;
}
}
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v8i16 643:iPTR, (bitconvert:v16i8 (X86vzmovl:v2i64 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>))))
- // Emits: (PMOVZXBWrm:v8i16 addr:iPTR:$src)
- // Pattern complexity = 39 cost = 1 size = 3
- if (CN1 == INT64_C(643)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == X86ISD::VZEXT_MOVL &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N100.hasOneUse()) {
- SDValue N1000 = N100.getNode()->getOperand(0);
- if (N1000.getNode()->getOpcode() == ISD::LOAD &&
- N1000.hasOneUse() &&
- IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N)) {
- SDValue Chain1000 = N1000.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1000.getNode()) &&
- Predicate_load(N1000.getNode()) &&
- Predicate_loadi64(N1000.getNode())) {
- SDValue N10001 = N1000.getNode()->getOperand(1);
- SDValue CPTmpN10001_0;
- SDValue CPTmpN10001_1;
- SDValue CPTmpN10001_2;
- SDValue CPTmpN10001_3;
- SDValue CPTmpN10001_4;
- if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
- N10.getValueType() == MVT::v2i64 &&
- N1000.getValueType() == MVT::i64) {
- SDNode *Result = Emit_129(N, X86::PMOVZXBWrm, MVT::v8i16, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v8i16 644:iPTR, (bitconvert:v16i8 (X86vzmovl:v2i64 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>))))
+ // Emits: (PMOVZXBWrm:v8i16 addr:iPTR:$src)
+ // Pattern complexity = 39 cost = 1 size = 3
+ if (CN1 == INT64_C(644)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == X86ISD::VZEXT_MOVL &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N100.hasOneUse()) {
+ SDValue N1000 = N100.getNode()->getOperand(0);
+ if (N1000.getNode()->getOpcode() == ISD::LOAD &&
+ N1000.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N)) {
+ SDValue Chain1000 = N1000.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1000.getNode()) &&
+ Predicate_load(N1000.getNode()) &&
+ Predicate_loadi64(N1000.getNode())) {
+ SDValue N10001 = N1000.getNode()->getOperand(1);
+ SDValue CPTmpN10001_0;
+ SDValue CPTmpN10001_1;
+ SDValue CPTmpN10001_2;
+ SDValue CPTmpN10001_3;
+ SDValue CPTmpN10001_4;
+ if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
+ N10.getValueType() == MVT::v2i64 &&
+ N1000.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_129(N, X86::PMOVZXBWrm, MVT::v8i16, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
+ return Result;
}
}
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v8i16 621:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (imm:i32):$src3)
- // Emits: (PBLENDWrmi:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2, (imm:i32):$src3)
- // Pattern complexity = 36 cost = 1 size = 3
- if (CN1 == INT64_C(621)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4)) {
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant &&
- N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_119(N, X86::PBLENDWrmi, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v8i16 622:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (imm:i32):$src3)
+ // Emits: (PBLENDWrmi:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2, (imm:i32):$src3)
+ // Pattern complexity = 36 cost = 1 size = 3
+ if (CN1 == INT64_C(622)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4)) {
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant &&
+ N20.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_119(N, X86::PBLENDWrmi, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v8i16 637:iPTR, (bitconvert:v16i8 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)))
- // Emits: (PMOVSXBWrm:v8i16 addr:iPTR:$src)
- // Pattern complexity = 36 cost = 1 size = 3
- if (CN1 == INT64_C(637)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::LOAD &&
- N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N)) {
- SDValue Chain100 = N100.getNode()->getOperand(0);
- if (Predicate_unindexedload(N100.getNode()) &&
- Predicate_load(N100.getNode()) &&
- Predicate_loadi64(N100.getNode())) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue CPTmpN1001_0;
- SDValue CPTmpN1001_1;
- SDValue CPTmpN1001_2;
- SDValue CPTmpN1001_3;
- SDValue CPTmpN1001_4;
- if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
- N10.getValueType() == MVT::v2i64 &&
- N100.getValueType() == MVT::i64) {
- SDNode *Result = Emit_128(N, X86::PMOVSXBWrm, MVT::v8i16, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v8i16 638:iPTR, (bitconvert:v16i8 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)))
+ // Emits: (PMOVSXBWrm:v8i16 addr:iPTR:$src)
+ // Pattern complexity = 36 cost = 1 size = 3
+ if (CN1 == INT64_C(638)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::LOAD &&
+ N100.hasOneUse() &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N)) {
+ SDValue Chain100 = N100.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N100.getNode()) &&
+ Predicate_load(N100.getNode()) &&
+ Predicate_loadi64(N100.getNode())) {
+ SDValue N1001 = N100.getNode()->getOperand(1);
+ SDValue CPTmpN1001_0;
+ SDValue CPTmpN1001_1;
+ SDValue CPTmpN1001_2;
+ SDValue CPTmpN1001_3;
+ SDValue CPTmpN1001_4;
+ if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
+ N10.getValueType() == MVT::v2i64 &&
+ N100.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_128(N, X86::PMOVSXBWrm, MVT::v8i16, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ return Result;
}
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v8i16 643:iPTR, (bitconvert:v16i8 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)))
- // Emits: (PMOVZXBWrm:v8i16 addr:iPTR:$src)
- // Pattern complexity = 36 cost = 1 size = 3
- if (CN1 == INT64_C(643)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::LOAD &&
- N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N)) {
- SDValue Chain100 = N100.getNode()->getOperand(0);
- if (Predicate_unindexedload(N100.getNode()) &&
- Predicate_load(N100.getNode()) &&
- Predicate_loadi64(N100.getNode())) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue CPTmpN1001_0;
- SDValue CPTmpN1001_1;
- SDValue CPTmpN1001_2;
- SDValue CPTmpN1001_3;
- SDValue CPTmpN1001_4;
- if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
- N10.getValueType() == MVT::v2i64 &&
- N100.getValueType() == MVT::i64) {
- SDNode *Result = Emit_128(N, X86::PMOVZXBWrm, MVT::v8i16, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v8i16 644:iPTR, (bitconvert:v16i8 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)))
+ // Emits: (PMOVZXBWrm:v8i16 addr:iPTR:$src)
+ // Pattern complexity = 36 cost = 1 size = 3
+ if (CN1 == INT64_C(644)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::LOAD &&
+ N100.hasOneUse() &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N)) {
+ SDValue Chain100 = N100.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N100.getNode()) &&
+ Predicate_load(N100.getNode()) &&
+ Predicate_loadi64(N100.getNode())) {
+ SDValue N1001 = N100.getNode()->getOperand(1);
+ SDValue CPTmpN1001_0;
+ SDValue CPTmpN1001_1;
+ SDValue CPTmpN1001_2;
+ SDValue CPTmpN1001_3;
+ SDValue CPTmpN1001_4;
+ if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
+ N10.getValueType() == MVT::v2i64 &&
+ N100.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_128(N, X86::PMOVZXBWrm, MVT::v8i16, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ return Result;
}
}
}
@@ -17257,1088 +17134,1088 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(SDNode *N) {
}
}
}
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v8i16 543:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PADDSWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(543)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PADDSWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v8i16 544:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PADDSWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(544)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_116(N, X86::PADDSWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v8i16 545:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PADDUSWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(545)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PADDUSWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v8i16 546:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PADDUSWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(546)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_116(N, X86::PADDUSWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v8i16 585:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PSUBSWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(585)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PSUBSWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v8i16 586:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PSUBSWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(586)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_116(N, X86::PSUBSWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v8i16 587:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PSUBUSWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(587)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PSUBUSWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v8i16 588:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PSUBUSWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(588)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_116(N, X86::PSUBUSWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v8i16 561:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PMULHUWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(561)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PMULHUWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v8i16 562:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PMULHUWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(562)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_116(N, X86::PMULHUWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v8i16 560:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PMULHWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(560)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PMULHWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v8i16 561:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PMULHWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(561)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_116(N, X86::PMULHWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v8i16 547:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PAVGWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(547)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PAVGWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v8i16 548:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PAVGWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(548)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_116(N, X86::PAVGWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v8i16 557:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PMINSWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(557)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PMINSWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v8i16 558:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PMINSWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(558)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_116(N, X86::PMINSWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v8i16 555:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PMAXSWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(555)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PMAXSWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v8i16 556:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PMAXSWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(556)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_116(N, X86::PMAXSWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v8i16 568:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PSLLWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(568)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PSLLWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v8i16 569:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PSLLWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(569)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_116(N, X86::PSLLWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v8i16 580:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PSRLWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(580)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PSRLWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v8i16 581:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PSRLWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(581)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_116(N, X86::PSRLWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v8i16 573:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PSRAWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(573)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PSRAWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v8i16 574:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PSRAWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(574)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_116(N, X86::PSRAWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v8i16 550:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PCMPEQWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(550)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PCMPEQWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v8i16 551:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PCMPEQWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(551)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_116(N, X86::PCMPEQWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v8i16 553:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PCMPGTWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(553)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PCMPGTWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v8i16 554:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PCMPGTWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(554)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_116(N, X86::PCMPGTWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v8i16 539:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PACKSSDWrm:v8i16 VR128:v4i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(539)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PACKSSDWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v8i16 540:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PACKSSDWrm:v8i16 VR128:v4i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(540)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_116(N, X86::PACKSSDWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
}
}
- if ((Subtarget->hasSSSE3())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
+ }
+ if ((Subtarget->hasSSSE3())) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v8i16 727:iPTR, (bitconvert:v8i16 (ld:v8i16 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
- // Emits: (PABSWrm128:v8i16 addr:iPTR:$src)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(727)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop64(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_115(N, X86::PABSWrm128, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v8i16 728:iPTR, (bitconvert:v8i16 (ld:v8i16 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Emits: (PABSWrm128:v8i16 addr:iPTR:$src)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(728)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop64(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_115(N, X86::PABSWrm128, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v8i16 735:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v8i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
- // Emits: (PHADDWrm128:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(735)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop64(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_116(N, X86::PHADDWrm128, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v8i16 736:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v8i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Emits: (PHADDWrm128:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(736)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop64(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_116(N, X86::PHADDWrm128, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v8i16 741:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v8i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
- // Emits: (PHSUBWrm128:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(741)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop64(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_116(N, X86::PHSUBWrm128, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v8i16 742:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v8i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Emits: (PHSUBWrm128:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(742)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop64(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_116(N, X86::PHSUBWrm128, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v8i16 739:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v8i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
- // Emits: (PHSUBSWrm128:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(739)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop64(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_116(N, X86::PHSUBSWrm128, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v8i16 740:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v8i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Emits: (PHSUBSWrm128:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(740)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop64(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_116(N, X86::PHSUBSWrm128, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v8i16 743:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PMADDUBSWrm128:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(743)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_116(N, X86::PMADDUBSWrm128, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v8i16 744:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PMADDUBSWrm128:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(744)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_116(N, X86::PMADDUBSWrm128, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v8i16 745:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v8i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
- // Emits: (PMULHRSWrm128:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(745)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop64(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_116(N, X86::PMULHRSWrm128, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v8i16 746:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v8i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Emits: (PMULHRSWrm128:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(746)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop64(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_116(N, X86::PMULHRSWrm128, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v8i16 753:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v8i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
- // Emits: (PSIGNWrm128:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(753)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop64(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_116(N, X86::PSIGNWrm128, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v8i16 754:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v8i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Emits: (PSIGNWrm128:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(754)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop64(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_116(N, X86::PSIGNWrm128, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
}
}
- if ((Subtarget->hasSSE41())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
+ }
+ if ((Subtarget->hasSSE41())) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v8i16 626:iPTR, (bitconvert:v8i16 (ld:v8i16 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
- // Emits: (PHMINPOSUWrm128:v8i16 addr:iPTR:$src)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(626)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop64(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_115(N, X86::PHMINPOSUWrm128, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v8i16 627:iPTR, (bitconvert:v8i16 (ld:v8i16 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Emits: (PHMINPOSUWrm128:v8i16 addr:iPTR:$src)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(627)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop64(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_115(N, X86::PHMINPOSUWrm128, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v8i16 619:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PACKUSDWrm:v8i16 VR128:v4i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(619)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_116(N, X86::PACKUSDWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v8i16 620:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PACKUSDWrm:v8i16 VR128:v4i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(620)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_116(N, X86::PACKUSDWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v8i16 634:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PMINUWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(634)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_116(N, X86::PMINUWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v8i16 635:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PMINUWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(635)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_116(N, X86::PMINUWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v8i16 630:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PMAXUWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(630)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_116(N, X86::PMAXUWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v8i16 631:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PMAXUWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(631)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_116(N, X86::PMAXUWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
}
}
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v8i16 543:iPTR, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
- // Emits: (PADDSWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(543)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PADDSWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v8i16 544:iPTR, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
+ // Emits: (PADDSWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(544)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_117(N, X86::PADDSWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v8i16 545:iPTR, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
- // Emits: (PADDUSWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(545)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PADDUSWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v8i16 546:iPTR, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
+ // Emits: (PADDUSWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(546)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_117(N, X86::PADDUSWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v8i16 561:iPTR, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
- // Emits: (PMULHUWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(561)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PMULHUWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v8i16 562:iPTR, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
+ // Emits: (PMULHUWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(562)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_117(N, X86::PMULHUWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v8i16 560:iPTR, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
- // Emits: (PMULHWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(560)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PMULHWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v8i16 561:iPTR, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
+ // Emits: (PMULHWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(561)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_117(N, X86::PMULHWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v8i16 547:iPTR, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
- // Emits: (PAVGWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(547)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PAVGWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v8i16 548:iPTR, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
+ // Emits: (PAVGWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(548)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_117(N, X86::PAVGWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v8i16 557:iPTR, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
- // Emits: (PMINSWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(557)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PMINSWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v8i16 558:iPTR, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
+ // Emits: (PMINSWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(558)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_117(N, X86::PMINSWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v8i16 555:iPTR, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
- // Emits: (PMAXSWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(555)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PMAXSWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v8i16 556:iPTR, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
+ // Emits: (PMAXSWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(556)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_117(N, X86::PMAXSWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
@@ -18346,39 +18223,39 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(SDNode *N) {
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v8i16 745:iPTR, (bitconvert:v8i16 (ld:v8i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>), VR128:v8i16:$src1)
- // Emits: (PMULHRSWrm128:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if ((Subtarget->hasSSSE3())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(745)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop64(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_117(N, X86::PMULHRSWrm128, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v8i16 746:iPTR, (bitconvert:v8i16 (ld:v8i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>), VR128:v8i16:$src1)
+ // Emits: (PMULHRSWrm128:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if ((Subtarget->hasSSSE3())) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(746)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop64(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N10.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_117(N, X86::PMULHRSWrm128, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
@@ -18386,132 +18263,132 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(SDNode *N) {
}
}
}
- if ((Subtarget->hasSSE41())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v8i16 634:iPTR, (bitconvert:v8i16 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
- // Emits: (PMINUWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(634)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_117(N, X86::PMINUWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v8i16 630:iPTR, (bitconvert:v8i16 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
- // Emits: (PMAXUWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(630)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_117(N, X86::PMAXUWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
+ }
+ if ((Subtarget->hasSSE41())) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v8i16 637:iPTR, (bitconvert:v16i8 (X86vzload:v2i64 addr:iPTR:$src)))
- // Emits: (PMOVSXBWrm:v8i16 addr:iPTR:$src)
- // Pattern complexity = 32 cost = 1 size = 3
- if (CN1 == INT64_C(637)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == X86ISD::VZEXT_LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
+ // Pattern: (intrinsic_wo_chain:v8i16 635:iPTR, (bitconvert:v8i16 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
+ // Emits: (PMINUWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(635)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_130(N, X86::PMOVSXBWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N10.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_117(N, X86::PMINUWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v8i16 643:iPTR, (bitconvert:v16i8 (X86vzload:v2i64 addr:iPTR:$src)))
- // Emits: (PMOVZXBWrm:v8i16 addr:iPTR:$src)
- // Pattern complexity = 32 cost = 1 size = 3
- if (CN1 == INT64_C(643)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == X86ISD::VZEXT_LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
+ // Pattern: (intrinsic_wo_chain:v8i16 631:iPTR, (bitconvert:v8i16 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
+ // Emits: (PMAXUWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(631)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_130(N, X86::PMOVZXBWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N10.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_117(N, X86::PMAXUWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
}
}
}
}
}
+
+ // Pattern: (intrinsic_wo_chain:v8i16 638:iPTR, (bitconvert:v16i8 (X86vzload:v2i64 addr:iPTR:$src)))
+ // Emits: (PMOVSXBWrm:v8i16 addr:iPTR:$src)
+ // Pattern complexity = 32 cost = 1 size = 3
+ if (CN1 == INT64_C(638)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == X86ISD::VZEXT_LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_130(N, X86::PMOVSXBWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v8i16 644:iPTR, (bitconvert:v16i8 (X86vzload:v2i64 addr:iPTR:$src)))
+ // Emits: (PMOVZXBWrm:v8i16 addr:iPTR:$src)
+ // Pattern complexity = 32 cost = 1 size = 3
+ if (CN1 == INT64_C(644)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == X86ISD::VZEXT_LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_130(N, X86::PMOVZXBWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
}
}
if ((Subtarget->hasSSE2())) {
@@ -18520,10 +18397,10 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(SDNode *N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v8i16 571:iPTR, VR128:v8i16:$src1, (imm:i32):$src2)
+ // Pattern: (intrinsic_wo_chain:v8i16 572:iPTR, VR128:v8i16:$src1, (imm:i32):$src2)
// Emits: (PSLLWri:v8i16 VR128:v8i16:$src1, (imm:i32):$src2)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(571)) {
+ if (CN1 == INT64_C(572)) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
if (N2.getNode()->getOpcode() == ISD::Constant) {
@@ -18532,10 +18409,10 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(SDNode *N) {
}
}
- // Pattern: (intrinsic_wo_chain:v8i16 583:iPTR, VR128:v8i16:$src1, (imm:i32):$src2)
+ // Pattern: (intrinsic_wo_chain:v8i16 584:iPTR, VR128:v8i16:$src1, (imm:i32):$src2)
// Emits: (PSRLWri:v8i16 VR128:v8i16:$src1, (imm:i32):$src2)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(583)) {
+ if (CN1 == INT64_C(584)) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
if (N2.getNode()->getOpcode() == ISD::Constant) {
@@ -18544,10 +18421,10 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(SDNode *N) {
}
}
- // Pattern: (intrinsic_wo_chain:v8i16 575:iPTR, VR128:v8i16:$src1, (imm:i32):$src2)
+ // Pattern: (intrinsic_wo_chain:v8i16 576:iPTR, VR128:v8i16:$src1, (imm:i32):$src2)
// Emits: (PSRAWri:v8i16 VR128:v8i16:$src1, (imm:i32):$src2)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(575)) {
+ if (CN1 == INT64_C(576)) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
if (N2.getNode()->getOpcode() == ISD::Constant) {
@@ -18558,7 +18435,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(SDNode *N) {
}
}
- // Pattern: (intrinsic_wo_chain:v8i16 621:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2, (imm:i32):$src3)
+ // Pattern: (intrinsic_wo_chain:v8i16 622:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2, (imm:i32):$src3)
// Emits: (PBLENDWrri:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2, (imm:i32):$src3)
// Pattern complexity = 11 cost = 1 size = 3
if ((Subtarget->hasSSE41())) {
@@ -18566,7 +18443,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(SDNode *N) {
ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(621)) {
+ if (CN1 == INT64_C(622)) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
SDValue N3 = N->getOperand(3);
@@ -18583,122 +18460,122 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(SDNode *N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v8i16 543:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i16 544:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
// Emits: (PADDSWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(543)) {
+ if (CN1 == INT64_C(544)) {
SDNode *Result = Emit_110(N, X86::PADDSWrr, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 545:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i16 546:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
// Emits: (PADDUSWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(545)) {
+ if (CN1 == INT64_C(546)) {
SDNode *Result = Emit_110(N, X86::PADDUSWrr, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 585:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i16 586:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
// Emits: (PSUBSWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(585)) {
+ if (CN1 == INT64_C(586)) {
SDNode *Result = Emit_110(N, X86::PSUBSWrr, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 587:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i16 588:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
// Emits: (PSUBUSWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(587)) {
+ if (CN1 == INT64_C(588)) {
SDNode *Result = Emit_110(N, X86::PSUBUSWrr, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 561:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i16 562:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
// Emits: (PMULHUWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(561)) {
+ if (CN1 == INT64_C(562)) {
SDNode *Result = Emit_110(N, X86::PMULHUWrr, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 560:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i16 561:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
// Emits: (PMULHWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(560)) {
+ if (CN1 == INT64_C(561)) {
SDNode *Result = Emit_110(N, X86::PMULHWrr, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 547:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i16 548:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
// Emits: (PAVGWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(547)) {
+ if (CN1 == INT64_C(548)) {
SDNode *Result = Emit_110(N, X86::PAVGWrr, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 557:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i16 558:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
// Emits: (PMINSWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(557)) {
+ if (CN1 == INT64_C(558)) {
SDNode *Result = Emit_110(N, X86::PMINSWrr, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 555:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i16 556:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
// Emits: (PMAXSWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(555)) {
+ if (CN1 == INT64_C(556)) {
SDNode *Result = Emit_110(N, X86::PMAXSWrr, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 568:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i16 569:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
// Emits: (PSLLWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(568)) {
+ if (CN1 == INT64_C(569)) {
SDNode *Result = Emit_110(N, X86::PSLLWrr, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 580:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i16 581:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
// Emits: (PSRLWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(580)) {
+ if (CN1 == INT64_C(581)) {
SDNode *Result = Emit_110(N, X86::PSRLWrr, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 573:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i16 574:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
// Emits: (PSRAWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(573)) {
+ if (CN1 == INT64_C(574)) {
SDNode *Result = Emit_110(N, X86::PSRAWrr, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 550:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i16 551:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
// Emits: (PCMPEQWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(550)) {
+ if (CN1 == INT64_C(551)) {
SDNode *Result = Emit_110(N, X86::PCMPEQWrr, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 553:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i16 554:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
// Emits: (PCMPGTWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(553)) {
+ if (CN1 == INT64_C(554)) {
SDNode *Result = Emit_110(N, X86::PCMPGTWrr, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 539:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i16 540:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
// Emits: (PACKSSDWrr:v8i16 VR128:v4i32:$src1, VR128:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(539)) {
+ if (CN1 == INT64_C(540)) {
SDNode *Result = Emit_110(N, X86::PACKSSDWrr, MVT::v8i16);
return Result;
}
@@ -18710,58 +18587,58 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(SDNode *N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v8i16 727:iPTR, VR128:v8i16:$src)
+ // Pattern: (intrinsic_wo_chain:v8i16 728:iPTR, VR128:v8i16:$src)
// Emits: (PABSWrr128:v8i16 VR128:v8i16:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(727)) {
+ if (CN1 == INT64_C(728)) {
SDNode *Result = Emit_107(N, X86::PABSWrr128, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 735:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i16 736:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
// Emits: (PHADDWrr128:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(735)) {
+ if (CN1 == INT64_C(736)) {
SDNode *Result = Emit_110(N, X86::PHADDWrr128, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 741:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i16 742:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
// Emits: (PHSUBWrr128:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(741)) {
+ if (CN1 == INT64_C(742)) {
SDNode *Result = Emit_110(N, X86::PHSUBWrr128, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 739:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i16 740:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
// Emits: (PHSUBSWrr128:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(739)) {
+ if (CN1 == INT64_C(740)) {
SDNode *Result = Emit_110(N, X86::PHSUBSWrr128, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 743:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i16 744:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
// Emits: (PMADDUBSWrr128:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(743)) {
+ if (CN1 == INT64_C(744)) {
SDNode *Result = Emit_110(N, X86::PMADDUBSWrr128, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 745:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i16 746:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
// Emits: (PMULHRSWrr128:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(745)) {
+ if (CN1 == INT64_C(746)) {
SDNode *Result = Emit_110(N, X86::PMULHRSWrr128, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 753:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i16 754:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
// Emits: (PSIGNWrr128:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(753)) {
+ if (CN1 == INT64_C(754)) {
SDNode *Result = Emit_110(N, X86::PSIGNWrr128, MVT::v8i16);
return Result;
}
@@ -18773,50 +18650,50 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(SDNode *N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v8i16 626:iPTR, VR128:v8i16:$src)
+ // Pattern: (intrinsic_wo_chain:v8i16 627:iPTR, VR128:v8i16:$src)
// Emits: (PHMINPOSUWrr128:v8i16 VR128:v8i16:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(626)) {
+ if (CN1 == INT64_C(627)) {
SDNode *Result = Emit_107(N, X86::PHMINPOSUWrr128, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 619:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i16 620:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
// Emits: (PACKUSDWrr:v8i16 VR128:v4i32:$src1, VR128:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(619)) {
+ if (CN1 == INT64_C(620)) {
SDNode *Result = Emit_110(N, X86::PACKUSDWrr, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 634:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i16 635:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
// Emits: (PMINUWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(634)) {
+ if (CN1 == INT64_C(635)) {
SDNode *Result = Emit_110(N, X86::PMINUWrr, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 630:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i16 631:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
// Emits: (PMAXUWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(630)) {
+ if (CN1 == INT64_C(631)) {
SDNode *Result = Emit_110(N, X86::PMAXUWrr, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 637:iPTR, VR128:v16i8:$src)
+ // Pattern: (intrinsic_wo_chain:v8i16 638:iPTR, VR128:v16i8:$src)
// Emits: (PMOVSXBWrr:v8i16 VR128:v16i8:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(637)) {
+ if (CN1 == INT64_C(638)) {
SDNode *Result = Emit_107(N, X86::PMOVSXBWrr, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 643:iPTR, VR128:v16i8:$src)
+ // Pattern: (intrinsic_wo_chain:v8i16 644:iPTR, VR128:v16i8:$src)
// Emits: (PMOVZXBWrr:v8i16 VR128:v16i8:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(643)) {
+ if (CN1 == INT64_C(644)) {
SDNode *Result = Emit_107(N, X86::PMOVZXBWrr, MVT::v8i16);
return Result;
}
@@ -18828,422 +18705,420 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(SDNode *N) {
}
SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
- if ((Subtarget->hasSSSE3())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
+ if ((Subtarget->hasSSSE3())) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v2i32 724:iPTR, (bitconvert:v2i32 (ld:v2i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
- // Emits: (PABSDrm64:v2i32 addr:iPTR:$src)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(724)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop64(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_115(N, X86::PABSDrm64, MVT::v2i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v2i32 725:iPTR, (bitconvert:v2i32 (ld:v2i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Emits: (PABSDrm64:v2i32 addr:iPTR:$src)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(725)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop64(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_115(N, X86::PABSDrm64, MVT::v2i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v2i32 730:iPTR, VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v2i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
- // Emits: (PHADDDrm64:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(730)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop64(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_116(N, X86::PHADDDrm64, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v2i32 731:iPTR, VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v2i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Emits: (PHADDDrm64:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(731)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop64(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_116(N, X86::PHADDDrm64, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v2i32 736:iPTR, VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v2i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
- // Emits: (PHSUBDrm64:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(736)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop64(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_116(N, X86::PHSUBDrm64, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v2i32 737:iPTR, VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v2i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Emits: (PHSUBDrm64:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(737)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop64(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_116(N, X86::PHSUBDrm64, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v2i32 750:iPTR, VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v2i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
- // Emits: (PSIGNDrm64:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(750)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop64(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_116(N, X86::PSIGNDrm64, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v2i32 751:iPTR, VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v2i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Emits: (PSIGNDrm64:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(751)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop64(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i32) {
+ SDNode *Result = Emit_116(N, X86::PSIGNDrm64, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
}
}
- if ((Subtarget->hasMMX())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
+ }
+ if ((Subtarget->hasMMX())) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v2i32 476:iPTR, VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PMULUDQrm:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(476)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PMULUDQrm, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v2i32 477:iPTR, VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PMULUDQrm:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(477)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_116(N, X86::MMX_PMULUDQrm, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v2i32 468:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PMADDWDrm:v2i32 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(468)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PMADDWDrm, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v2i32 469:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PMADDWDrm:v2i32 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(469)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_116(N, X86::MMX_PMADDWDrm, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v2i32 488:iPTR, VR64:v2i32:$src1, (bitconvert:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PSRLDrm:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(488)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PSRLDrm, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v2i32 489:iPTR, VR64:v2i32:$src1, (bitconvert:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PSRLDrm:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(489)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_116(N, X86::MMX_PSRLDrm, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v2i32 478:iPTR, VR64:v2i32:$src1, (bitconvert:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PSLLDrm:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(478)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PSLLDrm, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v2i32 479:iPTR, VR64:v2i32:$src1, (bitconvert:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PSLLDrm:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(479)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_116(N, X86::MMX_PSLLDrm, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v2i32 484:iPTR, VR64:v2i32:$src1, (bitconvert:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PSRADrm:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(484)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PSRADrm, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v2i32 485:iPTR, VR64:v2i32:$src1, (bitconvert:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PSRADrm:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(485)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_116(N, X86::MMX_PSRADrm, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v2i32 463:iPTR, VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PCMPEQDrm:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(463)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PCMPEQDrm, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v2i32 464:iPTR, VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PCMPEQDrm:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(464)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_116(N, X86::MMX_PCMPEQDrm, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v2i32 466:iPTR, VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PCMPGTDrm:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(466)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PCMPGTDrm, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v2i32 467:iPTR, VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PCMPGTDrm:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(467)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_116(N, X86::MMX_PCMPGTDrm, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v2i32 476:iPTR, (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v2i32:$src1)
- // Emits: (MMX_PMULUDQrm:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(476)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PMULUDQrm, MVT::v2i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v2i32 477:iPTR, (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v2i32:$src1)
+ // Emits: (MMX_PMULUDQrm:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(477)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N10.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_117(N, X86::MMX_PMULUDQrm, MVT::v2i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v2i32 468:iPTR, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v4i16:$src1)
- // Emits: (MMX_PMADDWDrm:v2i32 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(468)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PMADDWDrm, MVT::v2i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v2i32 469:iPTR, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v4i16:$src1)
+ // Emits: (MMX_PMADDWDrm:v2i32 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(469)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N10.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_117(N, X86::MMX_PMADDWDrm, MVT::v2i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
@@ -19251,117 +19126,117 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(SDNode *N) {
}
}
}
- if ((Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
+ }
+ if ((Subtarget->hasSSE1())) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v2i32 687:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (Int_CVTPS2PIrm:v2i32 addr:iPTR:$src)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(687)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTPS2PIrm, MVT::v2i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v2i32 688:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (Int_CVTPS2PIrm:v2i32 addr:iPTR:$src)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(688)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_108(N, X86::Int_CVTPS2PIrm, MVT::v2i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v2i32 693:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (Int_CVTTPS2PIrm:v2i32 addr:iPTR:$src)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(693)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTTPS2PIrm, MVT::v2i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v2i32 694:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (Int_CVTTPS2PIrm:v2i32 addr:iPTR:$src)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(694)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_108(N, X86::Int_CVTTPS2PIrm, MVT::v2i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
}
}
}
}
}
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v2i32 684:iPTR, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (Int_CVTPD2PIrm:v2i32 addr:iPTR:$src)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(684)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTPD2PIrm, MVT::v2i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v2i32 685:iPTR, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (Int_CVTPD2PIrm:v2i32 addr:iPTR:$src)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(685)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_108(N, X86::Int_CVTPD2PIrm, MVT::v2i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v2i32 692:iPTR, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (Int_CVTTPD2PIrm:v2i32 addr:iPTR:$src)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(692)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTTPD2PIrm, MVT::v2i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v2i32 693:iPTR, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (Int_CVTTPD2PIrm:v2i32 addr:iPTR:$src)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(693)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_108(N, X86::Int_CVTTPD2PIrm, MVT::v2i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
}
}
}
@@ -19374,10 +19249,10 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(SDNode *N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v2i32 491:iPTR, VR64:v2i32:$src1, (imm:i32):$src2)
+ // Pattern: (intrinsic_wo_chain:v2i32 492:iPTR, VR64:v2i32:$src1, (imm:i32):$src2)
// Emits: (MMX_PSRLDri:v2i32 VR64:v2i32:$src1, (imm:i32):$src2)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(491)) {
+ if (CN1 == INT64_C(492)) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
if (N2.getNode()->getOpcode() == ISD::Constant) {
@@ -19386,10 +19261,10 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(SDNode *N) {
}
}
- // Pattern: (intrinsic_wo_chain:v2i32 481:iPTR, VR64:v2i32:$src1, (imm:i32):$src2)
+ // Pattern: (intrinsic_wo_chain:v2i32 482:iPTR, VR64:v2i32:$src1, (imm:i32):$src2)
// Emits: (MMX_PSLLDri:v2i32 VR64:v2i32:$src1, (imm:i32):$src2)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(481)) {
+ if (CN1 == INT64_C(482)) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
if (N2.getNode()->getOpcode() == ISD::Constant) {
@@ -19398,10 +19273,10 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(SDNode *N) {
}
}
- // Pattern: (intrinsic_wo_chain:v2i32 486:iPTR, VR64:v2i32:$src1, (imm:i32):$src2)
+ // Pattern: (intrinsic_wo_chain:v2i32 487:iPTR, VR64:v2i32:$src1, (imm:i32):$src2)
// Emits: (MMX_PSRADri:v2i32 VR64:v2i32:$src1, (imm:i32):$src2)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(486)) {
+ if (CN1 == INT64_C(487)) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
if (N2.getNode()->getOpcode() == ISD::Constant) {
@@ -19417,18 +19292,18 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(SDNode *N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v2i32 687:iPTR, VR128:v4f32:$src)
+ // Pattern: (intrinsic_wo_chain:v2i32 688:iPTR, VR128:v4f32:$src)
// Emits: (Int_CVTPS2PIrr:v2i32 VR128:v4f32:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(687)) {
+ if (CN1 == INT64_C(688)) {
SDNode *Result = Emit_107(N, X86::Int_CVTPS2PIrr, MVT::v2i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2i32 693:iPTR, VR128:v4f32:$src)
+ // Pattern: (intrinsic_wo_chain:v2i32 694:iPTR, VR128:v4f32:$src)
// Emits: (Int_CVTTPS2PIrr:v2i32 VR128:v4f32:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(693)) {
+ if (CN1 == INT64_C(694)) {
SDNode *Result = Emit_107(N, X86::Int_CVTTPS2PIrr, MVT::v2i32);
return Result;
}
@@ -19440,18 +19315,18 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(SDNode *N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v2i32 684:iPTR, VR128:v2f64:$src)
+ // Pattern: (intrinsic_wo_chain:v2i32 685:iPTR, VR128:v2f64:$src)
// Emits: (Int_CVTPD2PIrr:v2i32 VR128:v2f64:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(684)) {
+ if (CN1 == INT64_C(685)) {
SDNode *Result = Emit_107(N, X86::Int_CVTPD2PIrr, MVT::v2i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2i32 692:iPTR, VR128:v2f64:$src)
+ // Pattern: (intrinsic_wo_chain:v2i32 693:iPTR, VR128:v2f64:$src)
// Emits: (Int_CVTTPD2PIrr:v2i32 VR128:v2f64:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(692)) {
+ if (CN1 == INT64_C(693)) {
SDNode *Result = Emit_107(N, X86::Int_CVTTPD2PIrr, MVT::v2i32);
return Result;
}
@@ -19463,34 +19338,34 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(SDNode *N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v2i32 724:iPTR, VR64:v2i32:$src)
+ // Pattern: (intrinsic_wo_chain:v2i32 725:iPTR, VR64:v2i32:$src)
// Emits: (PABSDrr64:v2i32 VR64:v2i32:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(724)) {
+ if (CN1 == INT64_C(725)) {
SDNode *Result = Emit_107(N, X86::PABSDrr64, MVT::v2i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2i32 730:iPTR, VR64:v2i32:$src1, VR64:v2i32:$src2)
+ // Pattern: (intrinsic_wo_chain:v2i32 731:iPTR, VR64:v2i32:$src1, VR64:v2i32:$src2)
// Emits: (PHADDDrr64:v2i32 VR64:v2i32:$src1, VR64:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(730)) {
+ if (CN1 == INT64_C(731)) {
SDNode *Result = Emit_110(N, X86::PHADDDrr64, MVT::v2i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2i32 736:iPTR, VR64:v2i32:$src1, VR64:v2i32:$src2)
+ // Pattern: (intrinsic_wo_chain:v2i32 737:iPTR, VR64:v2i32:$src1, VR64:v2i32:$src2)
// Emits: (PHSUBDrr64:v2i32 VR64:v2i32:$src1, VR64:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(736)) {
+ if (CN1 == INT64_C(737)) {
SDNode *Result = Emit_110(N, X86::PHSUBDrr64, MVT::v2i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2i32 750:iPTR, VR64:v2i32:$src1, VR64:v2i32:$src2)
+ // Pattern: (intrinsic_wo_chain:v2i32 751:iPTR, VR64:v2i32:$src1, VR64:v2i32:$src2)
// Emits: (PSIGNDrr64:v2i32 VR64:v2i32:$src1, VR64:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(750)) {
+ if (CN1 == INT64_C(751)) {
SDNode *Result = Emit_110(N, X86::PSIGNDrr64, MVT::v2i32);
return Result;
}
@@ -19502,58 +19377,58 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(SDNode *N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v2i32 476:iPTR, VR64:v2i32:$src1, VR64:v2i32:$src2)
+ // Pattern: (intrinsic_wo_chain:v2i32 477:iPTR, VR64:v2i32:$src1, VR64:v2i32:$src2)
// Emits: (MMX_PMULUDQrr:v2i32 VR64:v2i32:$src1, VR64:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(476)) {
+ if (CN1 == INT64_C(477)) {
SDNode *Result = Emit_110(N, X86::MMX_PMULUDQrr, MVT::v2i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2i32 468:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v2i32 469:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
// Emits: (MMX_PMADDWDrr:v2i32 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(468)) {
+ if (CN1 == INT64_C(469)) {
SDNode *Result = Emit_110(N, X86::MMX_PMADDWDrr, MVT::v2i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2i32 488:iPTR, VR64:v2i32:$src1, VR64:v1i64:$src2)
+ // Pattern: (intrinsic_wo_chain:v2i32 489:iPTR, VR64:v2i32:$src1, VR64:v1i64:$src2)
// Emits: (MMX_PSRLDrr:v2i32 VR64:v2i32:$src1, VR64:v1i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(488)) {
+ if (CN1 == INT64_C(489)) {
SDNode *Result = Emit_110(N, X86::MMX_PSRLDrr, MVT::v2i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2i32 478:iPTR, VR64:v2i32:$src1, VR64:v1i64:$src2)
+ // Pattern: (intrinsic_wo_chain:v2i32 479:iPTR, VR64:v2i32:$src1, VR64:v1i64:$src2)
// Emits: (MMX_PSLLDrr:v2i32 VR64:v2i32:$src1, VR64:v1i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(478)) {
+ if (CN1 == INT64_C(479)) {
SDNode *Result = Emit_110(N, X86::MMX_PSLLDrr, MVT::v2i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2i32 484:iPTR, VR64:v2i32:$src1, VR64:v1i64:$src2)
+ // Pattern: (intrinsic_wo_chain:v2i32 485:iPTR, VR64:v2i32:$src1, VR64:v1i64:$src2)
// Emits: (MMX_PSRADrr:v2i32 VR64:v2i32:$src1, VR64:v1i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(484)) {
+ if (CN1 == INT64_C(485)) {
SDNode *Result = Emit_110(N, X86::MMX_PSRADrr, MVT::v2i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2i32 463:iPTR, VR64:v2i32:$src1, VR64:v2i32:$src2)
+ // Pattern: (intrinsic_wo_chain:v2i32 464:iPTR, VR64:v2i32:$src1, VR64:v2i32:$src2)
// Emits: (MMX_PCMPEQDrr:v2i32 VR64:v2i32:$src1, VR64:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(463)) {
+ if (CN1 == INT64_C(464)) {
SDNode *Result = Emit_110(N, X86::MMX_PCMPEQDrr, MVT::v2i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2i32 466:iPTR, VR64:v2i32:$src1, VR64:v2i32:$src2)
+ // Pattern: (intrinsic_wo_chain:v2i32 467:iPTR, VR64:v2i32:$src1, VR64:v2i32:$src2)
// Emits: (MMX_PCMPGTDrr:v2i32 VR64:v2i32:$src1, VR64:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(466)) {
+ if (CN1 == INT64_C(467)) {
SDNode *Result = Emit_110(N, X86::MMX_PCMPGTDrr, MVT::v2i32);
return Result;
}
@@ -19579,307 +19454,305 @@ DISABLE_INLINE SDNode *Emit_131(SDNode *N, unsigned Opc0, MVT::SimpleValueType V
return ResNode;
}
SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
- if ((Subtarget->hasSSE41())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
+ if ((Subtarget->hasSSE41())) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v4i32 639:iPTR, (bitconvert:v8i16 (X86vzmovl:v2i64 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>))))
- // Emits: (PMOVSXWDrm:v4i32 addr:iPTR:$src)
- // Pattern complexity = 39 cost = 1 size = 3
- if (CN1 == INT64_C(639)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == X86ISD::VZEXT_MOVL &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N100.hasOneUse()) {
- SDValue N1000 = N100.getNode()->getOperand(0);
- if (N1000.getNode()->getOpcode() == ISD::LOAD &&
- N1000.hasOneUse() &&
- IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N)) {
- SDValue Chain1000 = N1000.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1000.getNode()) &&
- Predicate_load(N1000.getNode()) &&
- Predicate_loadi64(N1000.getNode())) {
- SDValue N10001 = N1000.getNode()->getOperand(1);
- SDValue CPTmpN10001_0;
- SDValue CPTmpN10001_1;
- SDValue CPTmpN10001_2;
- SDValue CPTmpN10001_3;
- SDValue CPTmpN10001_4;
- if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
- N10.getValueType() == MVT::v2i64 &&
- N1000.getValueType() == MVT::i64) {
- SDNode *Result = Emit_129(N, X86::PMOVSXWDrm, MVT::v4i32, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i32 640:iPTR, (bitconvert:v8i16 (X86vzmovl:v2i64 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>))))
+ // Emits: (PMOVSXWDrm:v4i32 addr:iPTR:$src)
+ // Pattern complexity = 39 cost = 1 size = 3
+ if (CN1 == INT64_C(640)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == X86ISD::VZEXT_MOVL &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N100.hasOneUse()) {
+ SDValue N1000 = N100.getNode()->getOperand(0);
+ if (N1000.getNode()->getOpcode() == ISD::LOAD &&
+ N1000.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N)) {
+ SDValue Chain1000 = N1000.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1000.getNode()) &&
+ Predicate_load(N1000.getNode()) &&
+ Predicate_loadi64(N1000.getNode())) {
+ SDValue N10001 = N1000.getNode()->getOperand(1);
+ SDValue CPTmpN10001_0;
+ SDValue CPTmpN10001_1;
+ SDValue CPTmpN10001_2;
+ SDValue CPTmpN10001_3;
+ SDValue CPTmpN10001_4;
+ if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
+ N10.getValueType() == MVT::v2i64 &&
+ N1000.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_129(N, X86::PMOVSXWDrm, MVT::v4i32, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
+ return Result;
}
}
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4i32 645:iPTR, (bitconvert:v8i16 (X86vzmovl:v2i64 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>))))
- // Emits: (PMOVZXWDrm:v4i32 addr:iPTR:$src)
- // Pattern complexity = 39 cost = 1 size = 3
- if (CN1 == INT64_C(645)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == X86ISD::VZEXT_MOVL &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N100.hasOneUse()) {
- SDValue N1000 = N100.getNode()->getOperand(0);
- if (N1000.getNode()->getOpcode() == ISD::LOAD &&
- N1000.hasOneUse() &&
- IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N)) {
- SDValue Chain1000 = N1000.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1000.getNode()) &&
- Predicate_load(N1000.getNode()) &&
- Predicate_loadi64(N1000.getNode())) {
- SDValue N10001 = N1000.getNode()->getOperand(1);
- SDValue CPTmpN10001_0;
- SDValue CPTmpN10001_1;
- SDValue CPTmpN10001_2;
- SDValue CPTmpN10001_3;
- SDValue CPTmpN10001_4;
- if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
- N10.getValueType() == MVT::v2i64 &&
- N1000.getValueType() == MVT::i64) {
- SDNode *Result = Emit_129(N, X86::PMOVZXWDrm, MVT::v4i32, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i32 646:iPTR, (bitconvert:v8i16 (X86vzmovl:v2i64 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>))))
+ // Emits: (PMOVZXWDrm:v4i32 addr:iPTR:$src)
+ // Pattern complexity = 39 cost = 1 size = 3
+ if (CN1 == INT64_C(646)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == X86ISD::VZEXT_MOVL &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N100.hasOneUse()) {
+ SDValue N1000 = N100.getNode()->getOperand(0);
+ if (N1000.getNode()->getOpcode() == ISD::LOAD &&
+ N1000.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N)) {
+ SDValue Chain1000 = N1000.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1000.getNode()) &&
+ Predicate_load(N1000.getNode()) &&
+ Predicate_loadi64(N1000.getNode())) {
+ SDValue N10001 = N1000.getNode()->getOperand(1);
+ SDValue CPTmpN10001_0;
+ SDValue CPTmpN10001_1;
+ SDValue CPTmpN10001_2;
+ SDValue CPTmpN10001_3;
+ SDValue CPTmpN10001_4;
+ if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
+ N10.getValueType() == MVT::v2i64 &&
+ N1000.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_129(N, X86::PMOVZXWDrm, MVT::v4i32, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
+ return Result;
}
}
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4i32 635:iPTR, (bitconvert:v16i8 (X86vzmovl:v4i32 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>))))
- // Emits: (PMOVSXBDrm:v4i32 addr:iPTR:$src)
- // Pattern complexity = 39 cost = 1 size = 3
- if (CN1 == INT64_C(635)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == X86ISD::VZEXT_MOVL &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N100.hasOneUse()) {
- SDValue N1000 = N100.getNode()->getOperand(0);
- if (N1000.getNode()->getOpcode() == ISD::LOAD &&
- N1000.hasOneUse() &&
- IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N)) {
- SDValue Chain1000 = N1000.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1000.getNode()) &&
- Predicate_loadi32(N1000.getNode())) {
- SDValue N10001 = N1000.getNode()->getOperand(1);
- SDValue CPTmpN10001_0;
- SDValue CPTmpN10001_1;
- SDValue CPTmpN10001_2;
- SDValue CPTmpN10001_3;
- SDValue CPTmpN10001_4;
- if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
- N10.getValueType() == MVT::v4i32 &&
- N1000.getValueType() == MVT::i32) {
- SDNode *Result = Emit_129(N, X86::PMOVSXBDrm, MVT::v4i32, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i32 636:iPTR, (bitconvert:v16i8 (X86vzmovl:v4i32 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>))))
+ // Emits: (PMOVSXBDrm:v4i32 addr:iPTR:$src)
+ // Pattern complexity = 39 cost = 1 size = 3
+ if (CN1 == INT64_C(636)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == X86ISD::VZEXT_MOVL &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N100.hasOneUse()) {
+ SDValue N1000 = N100.getNode()->getOperand(0);
+ if (N1000.getNode()->getOpcode() == ISD::LOAD &&
+ N1000.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N)) {
+ SDValue Chain1000 = N1000.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1000.getNode()) &&
+ Predicate_loadi32(N1000.getNode())) {
+ SDValue N10001 = N1000.getNode()->getOperand(1);
+ SDValue CPTmpN10001_0;
+ SDValue CPTmpN10001_1;
+ SDValue CPTmpN10001_2;
+ SDValue CPTmpN10001_3;
+ SDValue CPTmpN10001_4;
+ if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
+ N10.getValueType() == MVT::v4i32 &&
+ N1000.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_129(N, X86::PMOVSXBDrm, MVT::v4i32, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
+ return Result;
}
}
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4i32 641:iPTR, (bitconvert:v16i8 (X86vzmovl:v4i32 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>))))
- // Emits: (PMOVZXBDrm:v4i32 addr:iPTR:$src)
- // Pattern complexity = 39 cost = 1 size = 3
- if (CN1 == INT64_C(641)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == X86ISD::VZEXT_MOVL &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N100.hasOneUse()) {
- SDValue N1000 = N100.getNode()->getOperand(0);
- if (N1000.getNode()->getOpcode() == ISD::LOAD &&
- N1000.hasOneUse() &&
- IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N)) {
- SDValue Chain1000 = N1000.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1000.getNode()) &&
- Predicate_loadi32(N1000.getNode())) {
- SDValue N10001 = N1000.getNode()->getOperand(1);
- SDValue CPTmpN10001_0;
- SDValue CPTmpN10001_1;
- SDValue CPTmpN10001_2;
- SDValue CPTmpN10001_3;
- SDValue CPTmpN10001_4;
- if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
- N10.getValueType() == MVT::v4i32 &&
- N1000.getValueType() == MVT::i32) {
- SDNode *Result = Emit_129(N, X86::PMOVZXBDrm, MVT::v4i32, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i32 642:iPTR, (bitconvert:v16i8 (X86vzmovl:v4i32 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>))))
+ // Emits: (PMOVZXBDrm:v4i32 addr:iPTR:$src)
+ // Pattern complexity = 39 cost = 1 size = 3
+ if (CN1 == INT64_C(642)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == X86ISD::VZEXT_MOVL &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N100.hasOneUse()) {
+ SDValue N1000 = N100.getNode()->getOperand(0);
+ if (N1000.getNode()->getOpcode() == ISD::LOAD &&
+ N1000.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N)) {
+ SDValue Chain1000 = N1000.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1000.getNode()) &&
+ Predicate_loadi32(N1000.getNode())) {
+ SDValue N10001 = N1000.getNode()->getOperand(1);
+ SDValue CPTmpN10001_0;
+ SDValue CPTmpN10001_1;
+ SDValue CPTmpN10001_2;
+ SDValue CPTmpN10001_3;
+ SDValue CPTmpN10001_4;
+ if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
+ N10.getValueType() == MVT::v4i32 &&
+ N1000.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_129(N, X86::PMOVZXBDrm, MVT::v4i32, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
+ return Result;
}
}
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4i32 639:iPTR, (bitconvert:v8i16 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)))
- // Emits: (PMOVSXWDrm:v4i32 addr:iPTR:$src)
- // Pattern complexity = 36 cost = 1 size = 3
- if (CN1 == INT64_C(639)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::LOAD &&
- N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N)) {
- SDValue Chain100 = N100.getNode()->getOperand(0);
- if (Predicate_unindexedload(N100.getNode()) &&
- Predicate_load(N100.getNode()) &&
- Predicate_loadi64(N100.getNode())) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue CPTmpN1001_0;
- SDValue CPTmpN1001_1;
- SDValue CPTmpN1001_2;
- SDValue CPTmpN1001_3;
- SDValue CPTmpN1001_4;
- if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
- N10.getValueType() == MVT::v2i64 &&
- N100.getValueType() == MVT::i64) {
- SDNode *Result = Emit_128(N, X86::PMOVSXWDrm, MVT::v4i32, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i32 640:iPTR, (bitconvert:v8i16 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)))
+ // Emits: (PMOVSXWDrm:v4i32 addr:iPTR:$src)
+ // Pattern complexity = 36 cost = 1 size = 3
+ if (CN1 == INT64_C(640)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::LOAD &&
+ N100.hasOneUse() &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N)) {
+ SDValue Chain100 = N100.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N100.getNode()) &&
+ Predicate_load(N100.getNode()) &&
+ Predicate_loadi64(N100.getNode())) {
+ SDValue N1001 = N100.getNode()->getOperand(1);
+ SDValue CPTmpN1001_0;
+ SDValue CPTmpN1001_1;
+ SDValue CPTmpN1001_2;
+ SDValue CPTmpN1001_3;
+ SDValue CPTmpN1001_4;
+ if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
+ N10.getValueType() == MVT::v2i64 &&
+ N100.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_128(N, X86::PMOVSXWDrm, MVT::v4i32, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ return Result;
}
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4i32 645:iPTR, (bitconvert:v8i16 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)))
- // Emits: (PMOVZXWDrm:v4i32 addr:iPTR:$src)
- // Pattern complexity = 36 cost = 1 size = 3
- if (CN1 == INT64_C(645)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::LOAD &&
- N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N)) {
- SDValue Chain100 = N100.getNode()->getOperand(0);
- if (Predicate_unindexedload(N100.getNode()) &&
- Predicate_load(N100.getNode()) &&
- Predicate_loadi64(N100.getNode())) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue CPTmpN1001_0;
- SDValue CPTmpN1001_1;
- SDValue CPTmpN1001_2;
- SDValue CPTmpN1001_3;
- SDValue CPTmpN1001_4;
- if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
- N10.getValueType() == MVT::v2i64 &&
- N100.getValueType() == MVT::i64) {
- SDNode *Result = Emit_128(N, X86::PMOVZXWDrm, MVT::v4i32, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i32 646:iPTR, (bitconvert:v8i16 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)))
+ // Emits: (PMOVZXWDrm:v4i32 addr:iPTR:$src)
+ // Pattern complexity = 36 cost = 1 size = 3
+ if (CN1 == INT64_C(646)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::LOAD &&
+ N100.hasOneUse() &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N)) {
+ SDValue Chain100 = N100.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N100.getNode()) &&
+ Predicate_load(N100.getNode()) &&
+ Predicate_loadi64(N100.getNode())) {
+ SDValue N1001 = N100.getNode()->getOperand(1);
+ SDValue CPTmpN1001_0;
+ SDValue CPTmpN1001_1;
+ SDValue CPTmpN1001_2;
+ SDValue CPTmpN1001_3;
+ SDValue CPTmpN1001_4;
+ if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
+ N10.getValueType() == MVT::v2i64 &&
+ N100.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_128(N, X86::PMOVZXWDrm, MVT::v4i32, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ return Result;
}
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4i32 635:iPTR, (bitconvert:v16i8 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)))
- // Emits: (PMOVSXBDrm:v4i32 addr:iPTR:$src)
- // Pattern complexity = 36 cost = 1 size = 3
- if (CN1 == INT64_C(635)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::LOAD &&
- N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N)) {
- SDValue Chain100 = N100.getNode()->getOperand(0);
- if (Predicate_unindexedload(N100.getNode()) &&
- Predicate_loadi32(N100.getNode())) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue CPTmpN1001_0;
- SDValue CPTmpN1001_1;
- SDValue CPTmpN1001_2;
- SDValue CPTmpN1001_3;
- SDValue CPTmpN1001_4;
- if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
- N10.getValueType() == MVT::v4i32 &&
- N100.getValueType() == MVT::i32) {
- SDNode *Result = Emit_128(N, X86::PMOVSXBDrm, MVT::v4i32, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i32 636:iPTR, (bitconvert:v16i8 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)))
+ // Emits: (PMOVSXBDrm:v4i32 addr:iPTR:$src)
+ // Pattern complexity = 36 cost = 1 size = 3
+ if (CN1 == INT64_C(636)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::LOAD &&
+ N100.hasOneUse() &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N)) {
+ SDValue Chain100 = N100.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N100.getNode()) &&
+ Predicate_loadi32(N100.getNode())) {
+ SDValue N1001 = N100.getNode()->getOperand(1);
+ SDValue CPTmpN1001_0;
+ SDValue CPTmpN1001_1;
+ SDValue CPTmpN1001_2;
+ SDValue CPTmpN1001_3;
+ SDValue CPTmpN1001_4;
+ if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
+ N10.getValueType() == MVT::v4i32 &&
+ N100.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_128(N, X86::PMOVSXBDrm, MVT::v4i32, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ return Result;
}
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4i32 641:iPTR, (bitconvert:v16i8 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)))
- // Emits: (PMOVZXBDrm:v4i32 addr:iPTR:$src)
- // Pattern complexity = 36 cost = 1 size = 3
- if (CN1 == INT64_C(641)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::LOAD &&
- N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N)) {
- SDValue Chain100 = N100.getNode()->getOperand(0);
- if (Predicate_unindexedload(N100.getNode()) &&
- Predicate_loadi32(N100.getNode())) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue CPTmpN1001_0;
- SDValue CPTmpN1001_1;
- SDValue CPTmpN1001_2;
- SDValue CPTmpN1001_3;
- SDValue CPTmpN1001_4;
- if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
- N10.getValueType() == MVT::v4i32 &&
- N100.getValueType() == MVT::i32) {
- SDNode *Result = Emit_128(N, X86::PMOVZXBDrm, MVT::v4i32, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i32 642:iPTR, (bitconvert:v16i8 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)))
+ // Emits: (PMOVZXBDrm:v4i32 addr:iPTR:$src)
+ // Pattern complexity = 36 cost = 1 size = 3
+ if (CN1 == INT64_C(642)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::LOAD &&
+ N100.hasOneUse() &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N)) {
+ SDValue Chain100 = N100.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N100.getNode()) &&
+ Predicate_loadi32(N100.getNode())) {
+ SDValue N1001 = N100.getNode()->getOperand(1);
+ SDValue CPTmpN1001_0;
+ SDValue CPTmpN1001_1;
+ SDValue CPTmpN1001_2;
+ SDValue CPTmpN1001_3;
+ SDValue CPTmpN1001_4;
+ if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
+ N10.getValueType() == MVT::v4i32 &&
+ N100.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_128(N, X86::PMOVZXBDrm, MVT::v4i32, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ return Result;
}
}
}
@@ -19887,539 +19760,539 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(SDNode *N) {
}
}
}
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v4i32 554:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PMADDWDrm:v4i32 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(554)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PMADDWDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i32 555:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PMADDWDrm:v4i32 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(555)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_116(N, X86::PMADDWDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4i32 564:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PSLLDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(564)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PSLLDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i32 565:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PSLLDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(565)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_116(N, X86::PSLLDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4i32 576:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PSRLDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(576)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PSRLDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i32 577:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PSRLDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(577)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_116(N, X86::PSRLDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4i32 572:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PSRADrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(572)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PSRADrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i32 573:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PSRADrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(573)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_116(N, X86::PSRADrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4i32 549:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PCMPEQDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(549)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PCMPEQDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i32 550:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PCMPEQDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(550)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_116(N, X86::PCMPEQDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4i32 552:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PCMPGTDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(552)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PCMPGTDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i32 553:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PCMPGTDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(553)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_116(N, X86::PCMPGTDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
}
}
- if ((Subtarget->hasSSSE3())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
+ }
+ if ((Subtarget->hasSSSE3())) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v4i32 725:iPTR, (bitconvert:v4i32 (ld:v4i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PABSDrm128:v4i32 addr:iPTR:$src)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(725)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_115(N, X86::PABSDrm128, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i32 726:iPTR, (bitconvert:v4i32 (ld:v4i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PABSDrm128:v4i32 addr:iPTR:$src)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(726)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_115(N, X86::PABSDrm128, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4i32 731:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v4i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PHADDDrm128:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(731)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_116(N, X86::PHADDDrm128, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i32 732:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v4i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PHADDDrm128:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(732)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_116(N, X86::PHADDDrm128, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4i32 733:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v8i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
- // Emits: (PHADDSWrm128:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(733)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop64(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_116(N, X86::PHADDSWrm128, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i32 734:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v8i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Emits: (PHADDSWrm128:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(734)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop64(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v8i16) {
+ SDNode *Result = Emit_116(N, X86::PHADDSWrm128, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4i32 737:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v4i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PHSUBDrm128:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(737)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_116(N, X86::PHSUBDrm128, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i32 738:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v4i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PHSUBDrm128:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(738)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_116(N, X86::PHSUBDrm128, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4i32 751:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v4i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PSIGNDrm128:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(751)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_116(N, X86::PSIGNDrm128, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i32 752:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v4i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PSIGNDrm128:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(752)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_116(N, X86::PSIGNDrm128, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
}
}
- if ((Subtarget->hasSSE41())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
+ }
+ if ((Subtarget->hasSSE41())) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v4i32 632:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PMINSDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(632)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_116(N, X86::PMINSDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i32 633:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PMINSDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(633)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_116(N, X86::PMINSDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4i32 633:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PMINUDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(633)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_116(N, X86::PMINUDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i32 634:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PMINUDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(634)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_116(N, X86::PMINUDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4i32 628:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PMAXSDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(628)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_116(N, X86::PMAXSDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i32 629:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PMAXSDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(629)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_116(N, X86::PMAXSDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4i32 629:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PMAXUDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(629)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_116(N, X86::PMAXUDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i32 630:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PMAXUDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(630)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_116(N, X86::PMAXUDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4i32 554:iPTR, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
- // Emits: (PMADDWDrm:v4i32 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(554)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PMADDWDrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i32 555:iPTR, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
+ // Emits: (PMADDWDrm:v4i32 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(555)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_117(N, X86::PMADDWDrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
@@ -20427,364 +20300,364 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(SDNode *N) {
}
}
}
- if ((Subtarget->hasSSE41())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v4i32 632:iPTR, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v4i32:$src1)
- // Emits: (PMINSDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(632)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_117(N, X86::PMINSDrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4i32 633:iPTR, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v4i32:$src1)
- // Emits: (PMINUDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(633)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_117(N, X86::PMINUDrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- }
+ }
+ if ((Subtarget->hasSSE41())) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v4i32 628:iPTR, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v4i32:$src1)
- // Emits: (PMAXSDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(628)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_117(N, X86::PMAXSDrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i32 633:iPTR, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v4i32:$src1)
+ // Emits: (PMINSDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(633)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N10.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_117(N, X86::PMINSDrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4i32 629:iPTR, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v4i32:$src1)
- // Emits: (PMAXUDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(629)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_117(N, X86::PMAXUDrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i32 634:iPTR, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v4i32:$src1)
+ // Emits: (PMINUDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(634)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N10.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_117(N, X86::PMINUDrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4i32 639:iPTR, (bitconvert:v8i16 (X86vzload:v2i64 addr:iPTR:$src)))
- // Emits: (PMOVSXWDrm:v4i32 addr:iPTR:$src)
- // Pattern complexity = 32 cost = 1 size = 3
- if (CN1 == INT64_C(639)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == X86ISD::VZEXT_LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
+ // Pattern: (intrinsic_wo_chain:v4i32 629:iPTR, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v4i32:$src1)
+ // Emits: (PMAXSDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(629)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_130(N, X86::PMOVSXWDrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N10.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_117(N, X86::PMAXSDrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4i32 645:iPTR, (bitconvert:v8i16 (X86vzload:v2i64 addr:iPTR:$src)))
- // Emits: (PMOVZXWDrm:v4i32 addr:iPTR:$src)
- // Pattern complexity = 32 cost = 1 size = 3
- if (CN1 == INT64_C(645)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == X86ISD::VZEXT_LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
+ // Pattern: (intrinsic_wo_chain:v4i32 630:iPTR, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v4i32:$src1)
+ // Emits: (PMAXUDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(630)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_130(N, X86::PMOVZXWDrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N10.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_117(N, X86::PMAXUDrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
}
}
}
}
}
+
+ // Pattern: (intrinsic_wo_chain:v4i32 640:iPTR, (bitconvert:v8i16 (X86vzload:v2i64 addr:iPTR:$src)))
+ // Emits: (PMOVSXWDrm:v4i32 addr:iPTR:$src)
+ // Pattern complexity = 32 cost = 1 size = 3
+ if (CN1 == INT64_C(640)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == X86ISD::VZEXT_LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_130(N, X86::PMOVSXWDrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v4i32 646:iPTR, (bitconvert:v8i16 (X86vzload:v2i64 addr:iPTR:$src)))
+ // Emits: (PMOVZXWDrm:v4i32 addr:iPTR:$src)
+ // Pattern complexity = 32 cost = 1 size = 3
+ if (CN1 == INT64_C(646)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == X86ISD::VZEXT_LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_130(N, X86::PMOVZXWDrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
}
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v4i32 512:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (Int_CVTPS2DQrm:v4i32 addr:iPTR:$src)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(512)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTPS2DQrm, MVT::v4i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i32 513:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (Int_CVTPS2DQrm:v4i32 addr:iPTR:$src)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(513)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_108(N, X86::Int_CVTPS2DQrm, MVT::v4i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4i32 521:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (Int_CVTTPS2DQrm:v4i32 addr:iPTR:$src)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(521)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTTPS2DQrm, MVT::v4i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i32 522:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (Int_CVTTPS2DQrm:v4i32 addr:iPTR:$src)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(522)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_108(N, X86::Int_CVTTPS2DQrm, MVT::v4i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4i32 510:iPTR, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (Int_CVTPD2DQrm:v4i32 addr:iPTR:$src)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(510)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTPD2DQrm, MVT::v4i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i32 511:iPTR, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (Int_CVTPD2DQrm:v4i32 addr:iPTR:$src)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(511)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_108(N, X86::Int_CVTPD2DQrm, MVT::v4i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4i32 520:iPTR, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (Int_CVTTPD2DQrm:v4i32 addr:iPTR:$src)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(520)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTTPD2DQrm, MVT::v4i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i32 521:iPTR, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (Int_CVTTPD2DQrm:v4i32 addr:iPTR:$src)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(521)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_108(N, X86::Int_CVTTPD2DQrm, MVT::v4i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
}
}
}
}
}
- if ((Subtarget->hasSSE41())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(648)) {
- SDValue N1 = N->getOperand(1);
+ }
+ if ((Subtarget->hasSSE41())) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(649)) {
+ SDValue N1 = N->getOperand(1);
- // Pattern: (intrinsic_wo_chain:v4i32 648:iPTR, VR128:v4i32:$src1, (ld:v4i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (PMULLDrm_int:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- {
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode()) &&
- Predicate_memop(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_109(N, X86::PMULLDrm_int, MVT::v4i32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i32 649:iPTR, VR128:v4i32:$src1, (ld:v4i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (PMULLDrm_int:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ {
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode()) &&
+ Predicate_memop(N2.getNode())) {
+ SDValue N21 = N2.getNode()->getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDNode *Result = Emit_109(N, X86::PMULLDrm_int, MVT::v4i32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4i32 648:iPTR, (ld:v4i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, VR128:v4i32:$src1)
- // Emits: (PMULLDrm_int:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_131(N, X86::PMULLDrm_int, MVT::v4i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4i32 649:iPTR, (ld:v4i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, VR128:v4i32:$src1)
+ // Emits: (PMULLDrm_int:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_131(N, X86::PMULLDrm_int, MVT::v4i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
}
}
}
@@ -20797,10 +20670,10 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(SDNode *N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v4i32 569:iPTR, VR128:v4i32:$src1, (imm:i32):$src2)
+ // Pattern: (intrinsic_wo_chain:v4i32 570:iPTR, VR128:v4i32:$src1, (imm:i32):$src2)
// Emits: (PSLLDri:v4i32 VR128:v4i32:$src1, (imm:i32):$src2)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(569)) {
+ if (CN1 == INT64_C(570)) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
if (N2.getNode()->getOpcode() == ISD::Constant) {
@@ -20809,10 +20682,10 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(SDNode *N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4i32 581:iPTR, VR128:v4i32:$src1, (imm:i32):$src2)
+ // Pattern: (intrinsic_wo_chain:v4i32 582:iPTR, VR128:v4i32:$src1, (imm:i32):$src2)
// Emits: (PSRLDri:v4i32 VR128:v4i32:$src1, (imm:i32):$src2)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(581)) {
+ if (CN1 == INT64_C(582)) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
if (N2.getNode()->getOpcode() == ISD::Constant) {
@@ -20821,10 +20694,10 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(SDNode *N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4i32 574:iPTR, VR128:v4i32:$src1, (imm:i32):$src2)
+ // Pattern: (intrinsic_wo_chain:v4i32 575:iPTR, VR128:v4i32:$src1, (imm:i32):$src2)
// Emits: (PSRADri:v4i32 VR128:v4i32:$src1, (imm:i32):$src2)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(574)) {
+ if (CN1 == INT64_C(575)) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
if (N2.getNode()->getOpcode() == ISD::Constant) {
@@ -20833,82 +20706,82 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(SDNode *N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4i32 512:iPTR, VR128:v4f32:$src)
+ // Pattern: (intrinsic_wo_chain:v4i32 513:iPTR, VR128:v4f32:$src)
// Emits: (Int_CVTPS2DQrr:v4i32 VR128:v4f32:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(512)) {
+ if (CN1 == INT64_C(513)) {
SDNode *Result = Emit_107(N, X86::Int_CVTPS2DQrr, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 521:iPTR, VR128:v4f32:$src)
+ // Pattern: (intrinsic_wo_chain:v4i32 522:iPTR, VR128:v4f32:$src)
// Emits: (Int_CVTTPS2DQrr:v4i32 VR128:v4f32:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(521)) {
+ if (CN1 == INT64_C(522)) {
SDNode *Result = Emit_107(N, X86::Int_CVTTPS2DQrr, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 510:iPTR, VR128:v2f64:$src)
+ // Pattern: (intrinsic_wo_chain:v4i32 511:iPTR, VR128:v2f64:$src)
// Emits: (Int_CVTPD2DQrr:v4i32 VR128:v2f64:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(510)) {
+ if (CN1 == INT64_C(511)) {
SDNode *Result = Emit_107(N, X86::Int_CVTPD2DQrr, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 520:iPTR, VR128:v2f64:$src)
+ // Pattern: (intrinsic_wo_chain:v4i32 521:iPTR, VR128:v2f64:$src)
// Emits: (Int_CVTTPD2DQrr:v4i32 VR128:v2f64:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(520)) {
+ if (CN1 == INT64_C(521)) {
SDNode *Result = Emit_107(N, X86::Int_CVTTPD2DQrr, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 554:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i32 555:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
// Emits: (PMADDWDrr:v4i32 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(554)) {
+ if (CN1 == INT64_C(555)) {
SDNode *Result = Emit_110(N, X86::PMADDWDrr, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 564:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i32 565:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
// Emits: (PSLLDrr:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(564)) {
+ if (CN1 == INT64_C(565)) {
SDNode *Result = Emit_110(N, X86::PSLLDrr, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 576:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i32 577:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
// Emits: (PSRLDrr:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(576)) {
+ if (CN1 == INT64_C(577)) {
SDNode *Result = Emit_110(N, X86::PSRLDrr, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 572:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i32 573:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
// Emits: (PSRADrr:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(572)) {
+ if (CN1 == INT64_C(573)) {
SDNode *Result = Emit_110(N, X86::PSRADrr, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 549:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i32 550:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
// Emits: (PCMPEQDrr:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(549)) {
+ if (CN1 == INT64_C(550)) {
SDNode *Result = Emit_110(N, X86::PCMPEQDrr, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 552:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i32 553:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
// Emits: (PCMPGTDrr:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(552)) {
+ if (CN1 == INT64_C(553)) {
SDNode *Result = Emit_110(N, X86::PCMPGTDrr, MVT::v4i32);
return Result;
}
@@ -20920,42 +20793,42 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(SDNode *N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v4i32 725:iPTR, VR128:v4i32:$src)
+ // Pattern: (intrinsic_wo_chain:v4i32 726:iPTR, VR128:v4i32:$src)
// Emits: (PABSDrr128:v4i32 VR128:v4i32:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(725)) {
+ if (CN1 == INT64_C(726)) {
SDNode *Result = Emit_107(N, X86::PABSDrr128, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 731:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i32 732:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
// Emits: (PHADDDrr128:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(731)) {
+ if (CN1 == INT64_C(732)) {
SDNode *Result = Emit_110(N, X86::PHADDDrr128, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 733:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i32 734:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
// Emits: (PHADDSWrr128:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(733)) {
+ if (CN1 == INT64_C(734)) {
SDNode *Result = Emit_110(N, X86::PHADDSWrr128, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 737:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i32 738:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
// Emits: (PHSUBDrr128:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(737)) {
+ if (CN1 == INT64_C(738)) {
SDNode *Result = Emit_110(N, X86::PHSUBDrr128, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 751:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i32 752:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
// Emits: (PSIGNDrr128:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(751)) {
+ if (CN1 == INT64_C(752)) {
SDNode *Result = Emit_110(N, X86::PSIGNDrr128, MVT::v4i32);
return Result;
}
@@ -20967,74 +20840,74 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(SDNode *N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v4i32 632:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i32 633:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
// Emits: (PMINSDrr:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(632)) {
+ if (CN1 == INT64_C(633)) {
SDNode *Result = Emit_110(N, X86::PMINSDrr, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 633:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i32 634:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
// Emits: (PMINUDrr:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(633)) {
+ if (CN1 == INT64_C(634)) {
SDNode *Result = Emit_110(N, X86::PMINUDrr, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 628:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i32 629:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
// Emits: (PMAXSDrr:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(628)) {
+ if (CN1 == INT64_C(629)) {
SDNode *Result = Emit_110(N, X86::PMAXSDrr, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 629:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i32 630:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
// Emits: (PMAXUDrr:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(629)) {
+ if (CN1 == INT64_C(630)) {
SDNode *Result = Emit_110(N, X86::PMAXUDrr, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 648:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i32 649:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
// Emits: (PMULLDrr_int:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(648)) {
+ if (CN1 == INT64_C(649)) {
SDNode *Result = Emit_110(N, X86::PMULLDrr_int, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 639:iPTR, VR128:v8i16:$src)
+ // Pattern: (intrinsic_wo_chain:v4i32 640:iPTR, VR128:v8i16:$src)
// Emits: (PMOVSXWDrr:v4i32 VR128:v8i16:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(639)) {
+ if (CN1 == INT64_C(640)) {
SDNode *Result = Emit_107(N, X86::PMOVSXWDrr, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 645:iPTR, VR128:v8i16:$src)
+ // Pattern: (intrinsic_wo_chain:v4i32 646:iPTR, VR128:v8i16:$src)
// Emits: (PMOVZXWDrr:v4i32 VR128:v8i16:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(645)) {
+ if (CN1 == INT64_C(646)) {
SDNode *Result = Emit_107(N, X86::PMOVZXWDrr, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 635:iPTR, VR128:v16i8:$src)
+ // Pattern: (intrinsic_wo_chain:v4i32 636:iPTR, VR128:v16i8:$src)
// Emits: (PMOVSXBDrr:v4i32 VR128:v16i8:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(635)) {
+ if (CN1 == INT64_C(636)) {
SDNode *Result = Emit_107(N, X86::PMOVSXBDrr, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 641:iPTR, VR128:v16i8:$src)
+ // Pattern: (intrinsic_wo_chain:v4i32 642:iPTR, VR128:v16i8:$src)
// Emits: (PMOVZXBDrr:v4i32 VR128:v16i8:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(641)) {
+ if (CN1 == INT64_C(642)) {
SDNode *Result = Emit_107(N, X86::PMOVZXBDrr, MVT::v4i32);
return Result;
}
@@ -21072,107 +20945,105 @@ DISABLE_INLINE SDNode *Emit_133(SDNode *N, unsigned Opc0, MVT::SimpleValueType V
return ResNode;
}
SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v1i64(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
- if ((Subtarget->hasMMX())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
+ if ((Subtarget->hasMMX())) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v1i64 489:iPTR, VR64:v1i64:$src1, (bitconvert:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PSRLQrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(489)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PSRLQrm, MVT::v1i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v1i64 490:iPTR, VR64:v1i64:$src1, (bitconvert:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PSRLQrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(490)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_116(N, X86::MMX_PSRLQrm, MVT::v1i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v1i64 479:iPTR, VR64:v1i64:$src1, (bitconvert:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PSLLQrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(479)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_116(N, X86::MMX_PSLLQrm, MVT::v1i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v1i64 480:iPTR, VR64:v1i64:$src1, (bitconvert:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PSLLQrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(480)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_116(N, X86::MMX_PSLLQrm, MVT::v1i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v1i64 728:iPTR, VR64:v1i64:$src1, (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>, (imm:i8):$src3)
- // Emits: (PALIGNR64rm:v1i64 VR64:v8i8:$src1, addr:iPTR:$src2, (BYTE_imm:i8 (imm:i8):$src3))
- // Pattern complexity = 33 cost = 1 size = 3
- if ((Subtarget->hasSSSE3())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(728)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode()) &&
- Predicate_memop64(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_133(N, X86::PALIGNR64rm, MVT::v1i64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v1i64 729:iPTR, VR64:v1i64:$src1, (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>, (imm:i8):$src3)
+ // Emits: (PALIGNR64rm:v1i64 VR64:v8i8:$src1, addr:iPTR:$src2, (BYTE_imm:i8 (imm:i8):$src3))
+ // Pattern complexity = 33 cost = 1 size = 3
+ if ((Subtarget->hasSSSE3())) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(729)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode()) &&
+ Predicate_memop64(N2.getNode())) {
+ SDValue N21 = N2.getNode()->getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_133(N, X86::PALIGNR64rm, MVT::v1i64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
}
}
}
@@ -21186,10 +21057,10 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v1i64(SDNode *N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v1i64 492:iPTR, VR64:v1i64:$src1, (imm:i32):$src2)
+ // Pattern: (intrinsic_wo_chain:v1i64 493:iPTR, VR64:v1i64:$src1, (imm:i32):$src2)
// Emits: (MMX_PSRLQri:v1i64 VR64:v1i64:$src1, (imm:i32):$src2)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(492)) {
+ if (CN1 == INT64_C(493)) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
if (N2.getNode()->getOpcode() == ISD::Constant) {
@@ -21198,10 +21069,10 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v1i64(SDNode *N) {
}
}
- // Pattern: (intrinsic_wo_chain:v1i64 482:iPTR, VR64:v1i64:$src1, (imm:i32):$src2)
+ // Pattern: (intrinsic_wo_chain:v1i64 483:iPTR, VR64:v1i64:$src1, (imm:i32):$src2)
// Emits: (MMX_PSLLQri:v1i64 VR64:v1i64:$src1, (imm:i32):$src2)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(482)) {
+ if (CN1 == INT64_C(483)) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
if (N2.getNode()->getOpcode() == ISD::Constant) {
@@ -21212,7 +21083,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v1i64(SDNode *N) {
}
}
- // Pattern: (intrinsic_wo_chain:v1i64 728:iPTR, VR64:v1i64:$src1, VR64:v1i64:$src2, (imm:i8):$src3)
+ // Pattern: (intrinsic_wo_chain:v1i64 729:iPTR, VR64:v1i64:$src1, VR64:v1i64:$src2, (imm:i8):$src3)
// Emits: (PALIGNR64rr:v1i64 VR64:v8i8:$src1, VR64:v8i8:$src2, (BYTE_imm:i8 (imm:i8):$src3))
// Pattern complexity = 11 cost = 1 size = 3
if ((Subtarget->hasSSSE3())) {
@@ -21220,7 +21091,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v1i64(SDNode *N) {
ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(728)) {
+ if (CN1 == INT64_C(729)) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
SDValue N3 = N->getOperand(3);
@@ -21237,18 +21108,18 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v1i64(SDNode *N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v1i64 489:iPTR, VR64:v1i64:$src1, VR64:v1i64:$src2)
+ // Pattern: (intrinsic_wo_chain:v1i64 490:iPTR, VR64:v1i64:$src1, VR64:v1i64:$src2)
// Emits: (MMX_PSRLQrr:v1i64 VR64:v1i64:$src1, VR64:v1i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(489)) {
+ if (CN1 == INT64_C(490)) {
SDNode *Result = Emit_110(N, X86::MMX_PSRLQrr, MVT::v1i64);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v1i64 479:iPTR, VR64:v1i64:$src1, VR64:v1i64:$src2)
+ // Pattern: (intrinsic_wo_chain:v1i64 480:iPTR, VR64:v1i64:$src1, VR64:v1i64:$src2)
// Emits: (MMX_PSLLQrr:v1i64 VR64:v1i64:$src1, VR64:v1i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(479)) {
+ if (CN1 == INT64_C(480)) {
SDNode *Result = Emit_110(N, X86::MMX_PSLLQrr, MVT::v1i64);
return Result;
}
@@ -21268,277 +21139,200 @@ DISABLE_INLINE SDNode *Emit_134(SDNode *N, unsigned Opc0, MVT::SimpleValueType V
return CurDAG->SelectNodeTo(N, Opc0, VT0, N1, Tmp4);
}
SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
- if ((Subtarget->hasSSE41())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (intrinsic_wo_chain:v2i64 638:iPTR, (bitconvert:v4i32 (X86vzmovl:v2i64 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>))))
- // Emits: (PMOVSXDQrm:v2i64 addr:iPTR:$src)
- // Pattern complexity = 39 cost = 1 size = 3
- if (CN1 == INT64_C(638)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == X86ISD::VZEXT_MOVL &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N100.hasOneUse()) {
- SDValue N1000 = N100.getNode()->getOperand(0);
- if (N1000.getNode()->getOpcode() == ISD::LOAD &&
- N1000.hasOneUse() &&
- IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N)) {
- SDValue Chain1000 = N1000.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1000.getNode()) &&
- Predicate_load(N1000.getNode()) &&
- Predicate_loadi64(N1000.getNode())) {
- SDValue N10001 = N1000.getNode()->getOperand(1);
- SDValue CPTmpN10001_0;
- SDValue CPTmpN10001_1;
- SDValue CPTmpN10001_2;
- SDValue CPTmpN10001_3;
- SDValue CPTmpN10001_4;
- if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
- N10.getValueType() == MVT::v2i64 &&
- N1000.getValueType() == MVT::i64) {
- SDNode *Result = Emit_129(N, X86::PMOVSXDQrm, MVT::v2i64, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v2i64 644:iPTR, (bitconvert:v4i32 (X86vzmovl:v2i64 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>))))
- // Emits: (PMOVZXDQrm:v2i64 addr:iPTR:$src)
- // Pattern complexity = 39 cost = 1 size = 3
- if (CN1 == INT64_C(644)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == X86ISD::VZEXT_MOVL &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N100.hasOneUse()) {
- SDValue N1000 = N100.getNode()->getOperand(0);
- if (N1000.getNode()->getOpcode() == ISD::LOAD &&
- N1000.hasOneUse() &&
- IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N)) {
- SDValue Chain1000 = N1000.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1000.getNode()) &&
- Predicate_load(N1000.getNode()) &&
- Predicate_loadi64(N1000.getNode())) {
- SDValue N10001 = N1000.getNode()->getOperand(1);
- SDValue CPTmpN10001_0;
- SDValue CPTmpN10001_1;
- SDValue CPTmpN10001_2;
- SDValue CPTmpN10001_3;
- SDValue CPTmpN10001_4;
- if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
- N10.getValueType() == MVT::v2i64 &&
- N1000.getValueType() == MVT::i64) {
- SDNode *Result = Emit_129(N, X86::PMOVZXDQrm, MVT::v2i64, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
+ if ((Subtarget->hasSSE41())) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v2i64 640:iPTR, (bitconvert:v8i16 (X86vzmovl:v4i32 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>))))
- // Emits: (PMOVSXWQrm:v2i64 addr:iPTR:$src)
- // Pattern complexity = 39 cost = 1 size = 3
- if (CN1 == INT64_C(640)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == X86ISD::VZEXT_MOVL &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N100.hasOneUse()) {
- SDValue N1000 = N100.getNode()->getOperand(0);
- if (N1000.getNode()->getOpcode() == ISD::LOAD &&
- N1000.hasOneUse() &&
- IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N)) {
- SDValue Chain1000 = N1000.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1000.getNode()) &&
- Predicate_loadi32(N1000.getNode())) {
- SDValue N10001 = N1000.getNode()->getOperand(1);
- SDValue CPTmpN10001_0;
- SDValue CPTmpN10001_1;
- SDValue CPTmpN10001_2;
- SDValue CPTmpN10001_3;
- SDValue CPTmpN10001_4;
- if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
- N10.getValueType() == MVT::v4i32 &&
- N1000.getValueType() == MVT::i32) {
- SDNode *Result = Emit_129(N, X86::PMOVSXWQrm, MVT::v2i64, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v2i64 639:iPTR, (bitconvert:v4i32 (X86vzmovl:v2i64 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>))))
+ // Emits: (PMOVSXDQrm:v2i64 addr:iPTR:$src)
+ // Pattern complexity = 39 cost = 1 size = 3
+ if (CN1 == INT64_C(639)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == X86ISD::VZEXT_MOVL &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N100.hasOneUse()) {
+ SDValue N1000 = N100.getNode()->getOperand(0);
+ if (N1000.getNode()->getOpcode() == ISD::LOAD &&
+ N1000.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N)) {
+ SDValue Chain1000 = N1000.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1000.getNode()) &&
+ Predicate_load(N1000.getNode()) &&
+ Predicate_loadi64(N1000.getNode())) {
+ SDValue N10001 = N1000.getNode()->getOperand(1);
+ SDValue CPTmpN10001_0;
+ SDValue CPTmpN10001_1;
+ SDValue CPTmpN10001_2;
+ SDValue CPTmpN10001_3;
+ SDValue CPTmpN10001_4;
+ if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
+ N10.getValueType() == MVT::v2i64 &&
+ N1000.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_129(N, X86::PMOVSXDQrm, MVT::v2i64, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
+ return Result;
}
}
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v2i64 646:iPTR, (bitconvert:v8i16 (X86vzmovl:v4i32 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>))))
- // Emits: (PMOVZXWQrm:v2i64 addr:iPTR:$src)
- // Pattern complexity = 39 cost = 1 size = 3
- if (CN1 == INT64_C(646)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == X86ISD::VZEXT_MOVL &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N100.hasOneUse()) {
- SDValue N1000 = N100.getNode()->getOperand(0);
- if (N1000.getNode()->getOpcode() == ISD::LOAD &&
- N1000.hasOneUse() &&
- IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N)) {
- SDValue Chain1000 = N1000.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1000.getNode()) &&
- Predicate_loadi32(N1000.getNode())) {
- SDValue N10001 = N1000.getNode()->getOperand(1);
- SDValue CPTmpN10001_0;
- SDValue CPTmpN10001_1;
- SDValue CPTmpN10001_2;
- SDValue CPTmpN10001_3;
- SDValue CPTmpN10001_4;
- if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
- N10.getValueType() == MVT::v4i32 &&
- N1000.getValueType() == MVT::i32) {
- SDNode *Result = Emit_129(N, X86::PMOVZXWQrm, MVT::v2i64, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v2i64 645:iPTR, (bitconvert:v4i32 (X86vzmovl:v2i64 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>))))
+ // Emits: (PMOVZXDQrm:v2i64 addr:iPTR:$src)
+ // Pattern complexity = 39 cost = 1 size = 3
+ if (CN1 == INT64_C(645)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == X86ISD::VZEXT_MOVL &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N100.hasOneUse()) {
+ SDValue N1000 = N100.getNode()->getOperand(0);
+ if (N1000.getNode()->getOpcode() == ISD::LOAD &&
+ N1000.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N)) {
+ SDValue Chain1000 = N1000.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1000.getNode()) &&
+ Predicate_load(N1000.getNode()) &&
+ Predicate_loadi64(N1000.getNode())) {
+ SDValue N10001 = N1000.getNode()->getOperand(1);
+ SDValue CPTmpN10001_0;
+ SDValue CPTmpN10001_1;
+ SDValue CPTmpN10001_2;
+ SDValue CPTmpN10001_3;
+ SDValue CPTmpN10001_4;
+ if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
+ N10.getValueType() == MVT::v2i64 &&
+ N1000.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_129(N, X86::PMOVZXDQrm, MVT::v2i64, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
+ return Result;
}
}
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v2i64 636:iPTR, (bitconvert:v16i8 (X86vzmovl:v4i32 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>))))
- // Emits: (PMOVSXBQrm:v2i64 addr:iPTR:$src)
- // Pattern complexity = 39 cost = 1 size = 3
- if (CN1 == INT64_C(636)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == X86ISD::VZEXT_MOVL &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N100.hasOneUse()) {
- SDValue N1000 = N100.getNode()->getOperand(0);
- if (N1000.getNode()->getOpcode() == ISD::LOAD &&
- N1000.hasOneUse() &&
- IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N)) {
- SDValue Chain1000 = N1000.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1000.getNode()) &&
- Predicate_loadi32(N1000.getNode())) {
- SDValue N10001 = N1000.getNode()->getOperand(1);
- SDValue CPTmpN10001_0;
- SDValue CPTmpN10001_1;
- SDValue CPTmpN10001_2;
- SDValue CPTmpN10001_3;
- SDValue CPTmpN10001_4;
- if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
- N10.getValueType() == MVT::v4i32 &&
- N1000.getValueType() == MVT::i32) {
- SDNode *Result = Emit_129(N, X86::PMOVSXBQrm, MVT::v2i64, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v2i64 641:iPTR, (bitconvert:v8i16 (X86vzmovl:v4i32 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>))))
+ // Emits: (PMOVSXWQrm:v2i64 addr:iPTR:$src)
+ // Pattern complexity = 39 cost = 1 size = 3
+ if (CN1 == INT64_C(641)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == X86ISD::VZEXT_MOVL &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N100.hasOneUse()) {
+ SDValue N1000 = N100.getNode()->getOperand(0);
+ if (N1000.getNode()->getOpcode() == ISD::LOAD &&
+ N1000.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N)) {
+ SDValue Chain1000 = N1000.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1000.getNode()) &&
+ Predicate_loadi32(N1000.getNode())) {
+ SDValue N10001 = N1000.getNode()->getOperand(1);
+ SDValue CPTmpN10001_0;
+ SDValue CPTmpN10001_1;
+ SDValue CPTmpN10001_2;
+ SDValue CPTmpN10001_3;
+ SDValue CPTmpN10001_4;
+ if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
+ N10.getValueType() == MVT::v4i32 &&
+ N1000.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_129(N, X86::PMOVSXWQrm, MVT::v2i64, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
+ return Result;
}
}
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v2i64 642:iPTR, (bitconvert:v16i8 (X86vzmovl:v4i32 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>))))
- // Emits: (PMOVZXBQrm:v2i64 addr:iPTR:$src)
- // Pattern complexity = 39 cost = 1 size = 3
- if (CN1 == INT64_C(642)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == X86ISD::VZEXT_MOVL &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N100.hasOneUse()) {
- SDValue N1000 = N100.getNode()->getOperand(0);
- if (N1000.getNode()->getOpcode() == ISD::LOAD &&
- N1000.hasOneUse() &&
- IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N)) {
- SDValue Chain1000 = N1000.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1000.getNode()) &&
- Predicate_loadi32(N1000.getNode())) {
- SDValue N10001 = N1000.getNode()->getOperand(1);
- SDValue CPTmpN10001_0;
- SDValue CPTmpN10001_1;
- SDValue CPTmpN10001_2;
- SDValue CPTmpN10001_3;
- SDValue CPTmpN10001_4;
- if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
- N10.getValueType() == MVT::v4i32 &&
- N1000.getValueType() == MVT::i32) {
- SDNode *Result = Emit_129(N, X86::PMOVZXBQrm, MVT::v2i64, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v2i64 647:iPTR, (bitconvert:v8i16 (X86vzmovl:v4i32 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>))))
+ // Emits: (PMOVZXWQrm:v2i64 addr:iPTR:$src)
+ // Pattern complexity = 39 cost = 1 size = 3
+ if (CN1 == INT64_C(647)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == X86ISD::VZEXT_MOVL &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N100.hasOneUse()) {
+ SDValue N1000 = N100.getNode()->getOperand(0);
+ if (N1000.getNode()->getOpcode() == ISD::LOAD &&
+ N1000.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N)) {
+ SDValue Chain1000 = N1000.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1000.getNode()) &&
+ Predicate_loadi32(N1000.getNode())) {
+ SDValue N10001 = N1000.getNode()->getOperand(1);
+ SDValue CPTmpN10001_0;
+ SDValue CPTmpN10001_1;
+ SDValue CPTmpN10001_2;
+ SDValue CPTmpN10001_3;
+ SDValue CPTmpN10001_4;
+ if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
+ N10.getValueType() == MVT::v4i32 &&
+ N1000.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_129(N, X86::PMOVZXWQrm, MVT::v2i64, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
+ return Result;
}
}
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v2i64 638:iPTR, (bitconvert:v4i32 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)))
- // Emits: (PMOVSXDQrm:v2i64 addr:iPTR:$src)
- // Pattern complexity = 36 cost = 1 size = 3
- if (CN1 == INT64_C(638)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::LOAD &&
- N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N)) {
- SDValue Chain100 = N100.getNode()->getOperand(0);
- if (Predicate_unindexedload(N100.getNode()) &&
- Predicate_load(N100.getNode()) &&
- Predicate_loadi64(N100.getNode())) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue CPTmpN1001_0;
- SDValue CPTmpN1001_1;
- SDValue CPTmpN1001_2;
- SDValue CPTmpN1001_3;
- SDValue CPTmpN1001_4;
- if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
- N10.getValueType() == MVT::v2i64 &&
- N100.getValueType() == MVT::i64) {
- SDNode *Result = Emit_128(N, X86::PMOVSXDQrm, MVT::v2i64, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ // Pattern: (intrinsic_wo_chain:v2i64 637:iPTR, (bitconvert:v16i8 (X86vzmovl:v4i32 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>))))
+ // Emits: (PMOVSXBQrm:v2i64 addr:iPTR:$src)
+ // Pattern complexity = 39 cost = 1 size = 3
+ if (CN1 == INT64_C(637)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == X86ISD::VZEXT_MOVL &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N100.hasOneUse()) {
+ SDValue N1000 = N100.getNode()->getOperand(0);
+ if (N1000.getNode()->getOpcode() == ISD::LOAD &&
+ N1000.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N)) {
+ SDValue Chain1000 = N1000.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1000.getNode()) &&
+ Predicate_loadi32(N1000.getNode())) {
+ SDValue N10001 = N1000.getNode()->getOperand(1);
+ SDValue CPTmpN10001_0;
+ SDValue CPTmpN10001_1;
+ SDValue CPTmpN10001_2;
+ SDValue CPTmpN10001_3;
+ SDValue CPTmpN10001_4;
+ if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
+ N10.getValueType() == MVT::v4i32 &&
+ N1000.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_129(N, X86::PMOVSXBQrm, MVT::v2i64, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
return Result;
}
}
@@ -21546,35 +21340,38 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(SDNode *N) {
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v2i64 644:iPTR, (bitconvert:v4i32 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)))
- // Emits: (PMOVZXDQrm:v2i64 addr:iPTR:$src)
- // Pattern complexity = 36 cost = 1 size = 3
- if (CN1 == INT64_C(644)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::LOAD &&
- N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N)) {
- SDValue Chain100 = N100.getNode()->getOperand(0);
- if (Predicate_unindexedload(N100.getNode()) &&
- Predicate_load(N100.getNode()) &&
- Predicate_loadi64(N100.getNode())) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue CPTmpN1001_0;
- SDValue CPTmpN1001_1;
- SDValue CPTmpN1001_2;
- SDValue CPTmpN1001_3;
- SDValue CPTmpN1001_4;
- if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
- N10.getValueType() == MVT::v2i64 &&
- N100.getValueType() == MVT::i64) {
- SDNode *Result = Emit_128(N, X86::PMOVZXDQrm, MVT::v2i64, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ // Pattern: (intrinsic_wo_chain:v2i64 643:iPTR, (bitconvert:v16i8 (X86vzmovl:v4i32 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>))))
+ // Emits: (PMOVZXBQrm:v2i64 addr:iPTR:$src)
+ // Pattern complexity = 39 cost = 1 size = 3
+ if (CN1 == INT64_C(643)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == X86ISD::VZEXT_MOVL &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N100.hasOneUse()) {
+ SDValue N1000 = N100.getNode()->getOperand(0);
+ if (N1000.getNode()->getOpcode() == ISD::LOAD &&
+ N1000.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N)) {
+ SDValue Chain1000 = N1000.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1000.getNode()) &&
+ Predicate_loadi32(N1000.getNode())) {
+ SDValue N10001 = N1000.getNode()->getOperand(1);
+ SDValue CPTmpN10001_0;
+ SDValue CPTmpN10001_1;
+ SDValue CPTmpN10001_2;
+ SDValue CPTmpN10001_3;
+ SDValue CPTmpN10001_4;
+ if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
+ N10.getValueType() == MVT::v4i32 &&
+ N1000.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_129(N, X86::PMOVZXBQrm, MVT::v2i64, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
return Result;
}
}
@@ -21582,629 +21379,701 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(SDNode *N) {
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v2i64 640:iPTR, (bitconvert:v8i16 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)))
- // Emits: (PMOVSXWQrm:v2i64 addr:iPTR:$src)
- // Pattern complexity = 36 cost = 1 size = 3
- if (CN1 == INT64_C(640)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::LOAD &&
- N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N)) {
- SDValue Chain100 = N100.getNode()->getOperand(0);
- if (Predicate_unindexedload(N100.getNode()) &&
- Predicate_loadi32(N100.getNode())) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue CPTmpN1001_0;
- SDValue CPTmpN1001_1;
- SDValue CPTmpN1001_2;
- SDValue CPTmpN1001_3;
- SDValue CPTmpN1001_4;
- if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
- N10.getValueType() == MVT::v4i32 &&
- N100.getValueType() == MVT::i32) {
- SDNode *Result = Emit_128(N, X86::PMOVSXWQrm, MVT::v2i64, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v2i64 639:iPTR, (bitconvert:v4i32 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)))
+ // Emits: (PMOVSXDQrm:v2i64 addr:iPTR:$src)
+ // Pattern complexity = 36 cost = 1 size = 3
+ if (CN1 == INT64_C(639)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::LOAD &&
+ N100.hasOneUse() &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N)) {
+ SDValue Chain100 = N100.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N100.getNode()) &&
+ Predicate_load(N100.getNode()) &&
+ Predicate_loadi64(N100.getNode())) {
+ SDValue N1001 = N100.getNode()->getOperand(1);
+ SDValue CPTmpN1001_0;
+ SDValue CPTmpN1001_1;
+ SDValue CPTmpN1001_2;
+ SDValue CPTmpN1001_3;
+ SDValue CPTmpN1001_4;
+ if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
+ N10.getValueType() == MVT::v2i64 &&
+ N100.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_128(N, X86::PMOVSXDQrm, MVT::v2i64, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ return Result;
}
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v2i64 646:iPTR, (bitconvert:v8i16 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)))
- // Emits: (PMOVZXWQrm:v2i64 addr:iPTR:$src)
- // Pattern complexity = 36 cost = 1 size = 3
- if (CN1 == INT64_C(646)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::LOAD &&
- N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N)) {
- SDValue Chain100 = N100.getNode()->getOperand(0);
- if (Predicate_unindexedload(N100.getNode()) &&
- Predicate_loadi32(N100.getNode())) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue CPTmpN1001_0;
- SDValue CPTmpN1001_1;
- SDValue CPTmpN1001_2;
- SDValue CPTmpN1001_3;
- SDValue CPTmpN1001_4;
- if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
- N10.getValueType() == MVT::v4i32 &&
- N100.getValueType() == MVT::i32) {
- SDNode *Result = Emit_128(N, X86::PMOVZXWQrm, MVT::v2i64, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v2i64 645:iPTR, (bitconvert:v4i32 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)))
+ // Emits: (PMOVZXDQrm:v2i64 addr:iPTR:$src)
+ // Pattern complexity = 36 cost = 1 size = 3
+ if (CN1 == INT64_C(645)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::LOAD &&
+ N100.hasOneUse() &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N)) {
+ SDValue Chain100 = N100.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N100.getNode()) &&
+ Predicate_load(N100.getNode()) &&
+ Predicate_loadi64(N100.getNode())) {
+ SDValue N1001 = N100.getNode()->getOperand(1);
+ SDValue CPTmpN1001_0;
+ SDValue CPTmpN1001_1;
+ SDValue CPTmpN1001_2;
+ SDValue CPTmpN1001_3;
+ SDValue CPTmpN1001_4;
+ if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
+ N10.getValueType() == MVT::v2i64 &&
+ N100.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_128(N, X86::PMOVZXDQrm, MVT::v2i64, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ return Result;
}
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v2i64 636:iPTR, (bitconvert:v16i8 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi16_anyext>>)))
- // Emits: (PMOVSXBQrm:v2i64 addr:iPTR:$src)
- // Pattern complexity = 36 cost = 1 size = 3
- if (CN1 == INT64_C(636)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::LOAD &&
- N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N)) {
- SDValue Chain100 = N100.getNode()->getOperand(0);
- if (Predicate_unindexedload(N100.getNode()) &&
- Predicate_loadi16_anyext(N100.getNode())) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue CPTmpN1001_0;
- SDValue CPTmpN1001_1;
- SDValue CPTmpN1001_2;
- SDValue CPTmpN1001_3;
- SDValue CPTmpN1001_4;
- if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
- N10.getValueType() == MVT::v4i32 &&
- N100.getValueType() == MVT::i32) {
- SDNode *Result = Emit_128(N, X86::PMOVSXBQrm, MVT::v2i64, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v2i64 641:iPTR, (bitconvert:v8i16 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)))
+ // Emits: (PMOVSXWQrm:v2i64 addr:iPTR:$src)
+ // Pattern complexity = 36 cost = 1 size = 3
+ if (CN1 == INT64_C(641)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::LOAD &&
+ N100.hasOneUse() &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N)) {
+ SDValue Chain100 = N100.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N100.getNode()) &&
+ Predicate_loadi32(N100.getNode())) {
+ SDValue N1001 = N100.getNode()->getOperand(1);
+ SDValue CPTmpN1001_0;
+ SDValue CPTmpN1001_1;
+ SDValue CPTmpN1001_2;
+ SDValue CPTmpN1001_3;
+ SDValue CPTmpN1001_4;
+ if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
+ N10.getValueType() == MVT::v4i32 &&
+ N100.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_128(N, X86::PMOVSXWQrm, MVT::v2i64, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ return Result;
}
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v2i64 642:iPTR, (bitconvert:v16i8 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi16_anyext>>)))
- // Emits: (PMOVZXBQrm:v2i64 addr:iPTR:$src)
- // Pattern complexity = 36 cost = 1 size = 3
- if (CN1 == INT64_C(642)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::LOAD &&
- N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N)) {
- SDValue Chain100 = N100.getNode()->getOperand(0);
- if (Predicate_unindexedload(N100.getNode()) &&
- Predicate_loadi16_anyext(N100.getNode())) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue CPTmpN1001_0;
- SDValue CPTmpN1001_1;
- SDValue CPTmpN1001_2;
- SDValue CPTmpN1001_3;
- SDValue CPTmpN1001_4;
- if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
- N10.getValueType() == MVT::v4i32 &&
- N100.getValueType() == MVT::i32) {
- SDNode *Result = Emit_128(N, X86::PMOVZXBQrm, MVT::v2i64, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v2i64 647:iPTR, (bitconvert:v8i16 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)))
+ // Emits: (PMOVZXWQrm:v2i64 addr:iPTR:$src)
+ // Pattern complexity = 36 cost = 1 size = 3
+ if (CN1 == INT64_C(647)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::LOAD &&
+ N100.hasOneUse() &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N)) {
+ SDValue Chain100 = N100.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N100.getNode()) &&
+ Predicate_loadi32(N100.getNode())) {
+ SDValue N1001 = N100.getNode()->getOperand(1);
+ SDValue CPTmpN1001_0;
+ SDValue CPTmpN1001_1;
+ SDValue CPTmpN1001_2;
+ SDValue CPTmpN1001_3;
+ SDValue CPTmpN1001_4;
+ if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
+ N10.getValueType() == MVT::v4i32 &&
+ N100.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_128(N, X86::PMOVZXWQrm, MVT::v2i64, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ return Result;
}
}
}
}
}
}
- }
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v2i64 562:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PMULUDQrm:v2i64 VR128:v4i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(562)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PMULUDQrm, MVT::v2i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ // Pattern: (intrinsic_wo_chain:v2i64 637:iPTR, (bitconvert:v16i8 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi16_anyext>>)))
+ // Emits: (PMOVSXBQrm:v2i64 addr:iPTR:$src)
+ // Pattern complexity = 36 cost = 1 size = 3
+ if (CN1 == INT64_C(637)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::LOAD &&
+ N100.hasOneUse() &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N)) {
+ SDValue Chain100 = N100.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N100.getNode()) &&
+ Predicate_loadi16_anyext(N100.getNode())) {
+ SDValue N1001 = N100.getNode()->getOperand(1);
+ SDValue CPTmpN1001_0;
+ SDValue CPTmpN1001_1;
+ SDValue CPTmpN1001_2;
+ SDValue CPTmpN1001_3;
+ SDValue CPTmpN1001_4;
+ if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
+ N10.getValueType() == MVT::v4i32 &&
+ N100.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_128(N, X86::PMOVSXBQrm, MVT::v2i64, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v2i64 563:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PSADBWrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(563)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PSADBWrm, MVT::v2i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ // Pattern: (intrinsic_wo_chain:v2i64 643:iPTR, (bitconvert:v16i8 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi16_anyext>>)))
+ // Emits: (PMOVZXBQrm:v2i64 addr:iPTR:$src)
+ // Pattern complexity = 36 cost = 1 size = 3
+ if (CN1 == INT64_C(643)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::LOAD &&
+ N100.hasOneUse() &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N)) {
+ SDValue Chain100 = N100.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N100.getNode()) &&
+ Predicate_loadi16_anyext(N100.getNode())) {
+ SDValue N1001 = N100.getNode()->getOperand(1);
+ SDValue CPTmpN1001_0;
+ SDValue CPTmpN1001_1;
+ SDValue CPTmpN1001_2;
+ SDValue CPTmpN1001_3;
+ SDValue CPTmpN1001_4;
+ if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
+ N10.getValueType() == MVT::v4i32 &&
+ N100.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_128(N, X86::PMOVZXBQrm, MVT::v2i64, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
}
}
}
+ }
+ }
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v2i64 567:iPTR, VR128:v2i64:$src1, (bitconvert:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PSLLQrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(567)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PSLLQrm, MVT::v2i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v2i64 563:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PMULUDQrm:v2i64 VR128:v4i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(563)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_116(N, X86::PMULUDQrm, MVT::v2i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v2i64 579:iPTR, VR128:v2i64:$src1, (bitconvert:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PSRLQrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(579)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::PSRLQrm, MVT::v2i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v2i64 564:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PSADBWrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(564)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_116(N, X86::PSADBWrm, MVT::v2i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
}
- }
- if ((Subtarget->hasSSE41())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v2i64 622:iPTR, VR128:v2i64:$src1, (bitconvert:v2i64 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PCMPEQQrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(622)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_116(N, X86::PCMPEQQrm, MVT::v2i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v2i64 568:iPTR, VR128:v2i64:$src1, (bitconvert:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PSLLQrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(568)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_116(N, X86::PSLLQrm, MVT::v2i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v2i64 647:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PMULDQrm:v2i64 VR128:v4i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(647)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_116(N, X86::PMULDQrm, MVT::v2i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v2i64 580:iPTR, VR128:v2i64:$src1, (bitconvert:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PSRLQrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(580)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_116(N, X86::PSRLQrm, MVT::v2i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
}
}
+ }
+ if ((Subtarget->hasSSE41())) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v2i64 667:iPTR, VR128:v2i64:$src1, (bitconvert:v2i64 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PCMPGTQrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if ((Subtarget->hasSSE42())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(667)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
- N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_116(N, X86::PCMPGTQrm, MVT::v2i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v2i64 623:iPTR, VR128:v2i64:$src1, (bitconvert:v2i64 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PCMPEQQrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(623)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_116(N, X86::PCMPEQQrm, MVT::v2i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
}
- }
- // Pattern: (intrinsic_wo_chain:v2i64 729:iPTR, VR128:v2i64:$src1, (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (imm:i8):$src3)
- // Emits: (PALIGNR128rm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2, (BYTE_imm:i8 (imm:i8):$src3))
- // Pattern complexity = 33 cost = 1 size = 3
- if ((Subtarget->hasSSSE3())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(729)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode()) &&
- Predicate_memop(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_133(N, X86::PALIGNR128rm, MVT::v2i64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v2i64 648:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PMULDQrm:v2i64 VR128:v4i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(648)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_116(N, X86::PMULDQrm, MVT::v2i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
}
}
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
+ }
- // Pattern: (intrinsic_wo_chain:v2i64 562:iPTR, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v4i32:$src1)
- // Emits: (PMULUDQrm:v2i64 VR128:v4i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(562)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PMULUDQrm, MVT::v2i64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
+ // Pattern: (intrinsic_wo_chain:v2i64 668:iPTR, VR128:v2i64:$src1, (bitconvert:v2i64 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PCMPGTQrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if ((Subtarget->hasSSE42())) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(668)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
+ N20.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_116(N, X86::PCMPGTQrm, MVT::v2i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
}
+ }
+ }
+ }
- // Pattern: (intrinsic_wo_chain:v2i64 563:iPTR, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v16i8:$src1)
- // Emits: (PSADBWrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(563)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PSADBWrm, MVT::v2i64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
+ // Pattern: (intrinsic_wo_chain:v2i64 730:iPTR, VR128:v2i64:$src1, (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (imm:i8):$src3)
+ // Emits: (PALIGNR128rm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2, (BYTE_imm:i8 (imm:i8):$src3))
+ // Pattern complexity = 33 cost = 1 size = 3
+ if ((Subtarget->hasSSSE3())) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(730)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode()) &&
+ Predicate_memop(N2.getNode())) {
+ SDValue N21 = N2.getNode()->getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_133(N, X86::PALIGNR128rm, MVT::v2i64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
}
}
}
}
}
}
- if ((Subtarget->hasSSE41())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v2i64 622:iPTR, (bitconvert:v2i64 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v2i64:$src1)
- // Emits: (PCMPEQQrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(622)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_117(N, X86::PCMPEQQrm, MVT::v2i64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v2i64 563:iPTR, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v4i32:$src1)
+ // Emits: (PMULUDQrm:v2i64 VR128:v4i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(563)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_117(N, X86::PMULUDQrm, MVT::v2i64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v2i64 647:iPTR, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v4i32:$src1)
- // Emits: (PMULDQrm:v2i64 VR128:v4i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(647)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N10.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_117(N, X86::PMULDQrm, MVT::v2i64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v2i64 564:iPTR, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v16i8:$src1)
+ // Emits: (PSADBWrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(564)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_117(N, X86::PSADBWrm, MVT::v2i64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
}
+ }
+ }
+ }
+ if ((Subtarget->hasSSE41())) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v2i64 638:iPTR, (bitconvert:v4i32 (X86vzload:v2i64 addr:iPTR:$src)))
- // Emits: (PMOVSXDQrm:v2i64 addr:iPTR:$src)
- // Pattern complexity = 32 cost = 1 size = 3
- if (CN1 == INT64_C(638)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == X86ISD::VZEXT_LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
+ // Pattern: (intrinsic_wo_chain:v2i64 623:iPTR, (bitconvert:v2i64 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v2i64:$src1)
+ // Emits: (PCMPEQQrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(623)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_130(N, X86::PMOVSXDQrm, MVT::v2i64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N10.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_117(N, X86::PCMPEQQrm, MVT::v2i64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v2i64 644:iPTR, (bitconvert:v4i32 (X86vzload:v2i64 addr:iPTR:$src)))
- // Emits: (PMOVZXDQrm:v2i64 addr:iPTR:$src)
- // Pattern complexity = 32 cost = 1 size = 3
- if (CN1 == INT64_C(644)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == X86ISD::VZEXT_LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
+ // Pattern: (intrinsic_wo_chain:v2i64 648:iPTR, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v4i32:$src1)
+ // Emits: (PMULDQrm:v2i64 VR128:v4i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(648)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_130(N, X86::PMOVZXDQrm, MVT::v2i64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N10.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_117(N, X86::PMULDQrm, MVT::v2i64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
}
}
}
}
}
+
+ // Pattern: (intrinsic_wo_chain:v2i64 639:iPTR, (bitconvert:v4i32 (X86vzload:v2i64 addr:iPTR:$src)))
+ // Emits: (PMOVSXDQrm:v2i64 addr:iPTR:$src)
+ // Pattern complexity = 32 cost = 1 size = 3
+ if (CN1 == INT64_C(639)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == X86ISD::VZEXT_LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_130(N, X86::PMOVSXDQrm, MVT::v2i64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (intrinsic_wo_chain:v2i64 645:iPTR, (bitconvert:v4i32 (X86vzload:v2i64 addr:iPTR:$src)))
+ // Emits: (PMOVZXDQrm:v2i64 addr:iPTR:$src)
+ // Pattern complexity = 32 cost = 1 size = 3
+ if (CN1 == INT64_C(645)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == X86ISD::VZEXT_LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_130(N, X86::PMOVZXDQrm, MVT::v2i64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
}
}
if ((Subtarget->hasSSE2())) {
@@ -22213,10 +22082,10 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(SDNode *N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v2i64 570:iPTR, VR128:v2i64:$src1, (imm:i32):$src2)
+ // Pattern: (intrinsic_wo_chain:v2i64 571:iPTR, VR128:v2i64:$src1, (imm:i32):$src2)
// Emits: (PSLLQri:v2i64 VR128:v2i64:$src1, (imm:i32):$src2)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(570)) {
+ if (CN1 == INT64_C(571)) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
if (N2.getNode()->getOpcode() == ISD::Constant) {
@@ -22225,10 +22094,10 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(SDNode *N) {
}
}
- // Pattern: (intrinsic_wo_chain:v2i64 582:iPTR, VR128:v2i64:$src1, (imm:i32):$src2)
+ // Pattern: (intrinsic_wo_chain:v2i64 583:iPTR, VR128:v2i64:$src1, (imm:i32):$src2)
// Emits: (PSRLQri:v2i64 VR128:v2i64:$src1, (imm:i32):$src2)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(582)) {
+ if (CN1 == INT64_C(583)) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
if (N2.getNode()->getOpcode() == ISD::Constant) {
@@ -22237,10 +22106,10 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(SDNode *N) {
}
}
- // Pattern: (intrinsic_wo_chain:v2i64 565:iPTR, VR128:v2i64:$src1, (imm:i32):$src2)
+ // Pattern: (intrinsic_wo_chain:v2i64 566:iPTR, VR128:v2i64:$src1, (imm:i32):$src2)
// Emits: (PSLLDQri:v2i64 VR128:v16i8:$src1, (BYTE_imm:i32 (imm:i32):$src2))
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(565)) {
+ if (CN1 == INT64_C(566)) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
if (N2.getNode()->getOpcode() == ISD::Constant) {
@@ -22249,10 +22118,10 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(SDNode *N) {
}
}
- // Pattern: (intrinsic_wo_chain:v2i64 577:iPTR, VR128:v2i64:$src1, (imm:i32):$src2)
+ // Pattern: (intrinsic_wo_chain:v2i64 578:iPTR, VR128:v2i64:$src1, (imm:i32):$src2)
// Emits: (PSRLDQri:v2i64 VR128:v16i8:$src1, (BYTE_imm:i32 (imm:i32):$src2))
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(577)) {
+ if (CN1 == INT64_C(578)) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
if (N2.getNode()->getOpcode() == ISD::Constant) {
@@ -22261,10 +22130,10 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(SDNode *N) {
}
}
- // Pattern: (intrinsic_wo_chain:v2i64 566:iPTR, VR128:v2i64:$src1, (imm:i32):$src2)
+ // Pattern: (intrinsic_wo_chain:v2i64 567:iPTR, VR128:v2i64:$src1, (imm:i32):$src2)
// Emits: (PSLLDQri:v2i64 VR128:v16i8:$src1, (imm:i32):$src2)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(566)) {
+ if (CN1 == INT64_C(567)) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
if (N2.getNode()->getOpcode() == ISD::Constant) {
@@ -22273,10 +22142,10 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(SDNode *N) {
}
}
- // Pattern: (intrinsic_wo_chain:v2i64 578:iPTR, VR128:v2i64:$src1, (imm:i32):$src2)
+ // Pattern: (intrinsic_wo_chain:v2i64 579:iPTR, VR128:v2i64:$src1, (imm:i32):$src2)
// Emits: (PSRLDQri:v2i64 VR128:v16i8:$src1, (imm:i32):$src2)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(578)) {
+ if (CN1 == INT64_C(579)) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
if (N2.getNode()->getOpcode() == ISD::Constant) {
@@ -22287,7 +22156,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(SDNode *N) {
}
}
- // Pattern: (intrinsic_wo_chain:v2i64 729:iPTR, VR128:v2i64:$src1, VR128:v2i64:$src2, (imm:i8):$src3)
+ // Pattern: (intrinsic_wo_chain:v2i64 730:iPTR, VR128:v2i64:$src1, VR128:v2i64:$src2, (imm:i8):$src3)
// Emits: (PALIGNR128rr:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src2, (BYTE_imm:i8 (imm:i8):$src3))
// Pattern complexity = 11 cost = 1 size = 3
if ((Subtarget->hasSSSE3())) {
@@ -22295,7 +22164,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(SDNode *N) {
ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(729)) {
+ if (CN1 == INT64_C(730)) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
SDValue N3 = N->getOperand(3);
@@ -22312,34 +22181,34 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(SDNode *N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v2i64 562:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Pattern: (intrinsic_wo_chain:v2i64 563:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
// Emits: (PMULUDQrr:v2i64 VR128:v4i32:$src1, VR128:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(562)) {
+ if (CN1 == INT64_C(563)) {
SDNode *Result = Emit_110(N, X86::PMULUDQrr, MVT::v2i64);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2i64 563:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern: (intrinsic_wo_chain:v2i64 564:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
// Emits: (PSADBWrr:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(563)) {
+ if (CN1 == INT64_C(564)) {
SDNode *Result = Emit_110(N, X86::PSADBWrr, MVT::v2i64);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2i64 567:iPTR, VR128:v2i64:$src1, VR128:v2i64:$src2)
+ // Pattern: (intrinsic_wo_chain:v2i64 568:iPTR, VR128:v2i64:$src1, VR128:v2i64:$src2)
// Emits: (PSLLQrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(567)) {
+ if (CN1 == INT64_C(568)) {
SDNode *Result = Emit_110(N, X86::PSLLQrr, MVT::v2i64);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2i64 579:iPTR, VR128:v2i64:$src1, VR128:v2i64:$src2)
+ // Pattern: (intrinsic_wo_chain:v2i64 580:iPTR, VR128:v2i64:$src1, VR128:v2i64:$src2)
// Emits: (PSRLQrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(579)) {
+ if (CN1 == INT64_C(580)) {
SDNode *Result = Emit_110(N, X86::PSRLQrr, MVT::v2i64);
return Result;
}
@@ -22351,73 +22220,73 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(SDNode *N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v2i64 622:iPTR, VR128:v2i64:$src1, VR128:v2i64:$src2)
+ // Pattern: (intrinsic_wo_chain:v2i64 623:iPTR, VR128:v2i64:$src1, VR128:v2i64:$src2)
// Emits: (PCMPEQQrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(622)) {
+ if (CN1 == INT64_C(623)) {
SDNode *Result = Emit_110(N, X86::PCMPEQQrr, MVT::v2i64);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2i64 647:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Pattern: (intrinsic_wo_chain:v2i64 648:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
// Emits: (PMULDQrr:v2i64 VR128:v4i32:$src1, VR128:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(647)) {
+ if (CN1 == INT64_C(648)) {
SDNode *Result = Emit_110(N, X86::PMULDQrr, MVT::v2i64);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2i64 638:iPTR, VR128:v4i32:$src)
+ // Pattern: (intrinsic_wo_chain:v2i64 639:iPTR, VR128:v4i32:$src)
// Emits: (PMOVSXDQrr:v2i64 VR128:v4i32:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(638)) {
+ if (CN1 == INT64_C(639)) {
SDNode *Result = Emit_107(N, X86::PMOVSXDQrr, MVT::v2i64);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2i64 644:iPTR, VR128:v4i32:$src)
+ // Pattern: (intrinsic_wo_chain:v2i64 645:iPTR, VR128:v4i32:$src)
// Emits: (PMOVZXDQrr:v2i64 VR128:v4i32:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(644)) {
+ if (CN1 == INT64_C(645)) {
SDNode *Result = Emit_107(N, X86::PMOVZXDQrr, MVT::v2i64);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2i64 640:iPTR, VR128:v8i16:$src)
+ // Pattern: (intrinsic_wo_chain:v2i64 641:iPTR, VR128:v8i16:$src)
// Emits: (PMOVSXWQrr:v2i64 VR128:v8i16:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(640)) {
+ if (CN1 == INT64_C(641)) {
SDNode *Result = Emit_107(N, X86::PMOVSXWQrr, MVT::v2i64);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2i64 646:iPTR, VR128:v8i16:$src)
+ // Pattern: (intrinsic_wo_chain:v2i64 647:iPTR, VR128:v8i16:$src)
// Emits: (PMOVZXWQrr:v2i64 VR128:v8i16:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(646)) {
+ if (CN1 == INT64_C(647)) {
SDNode *Result = Emit_107(N, X86::PMOVZXWQrr, MVT::v2i64);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2i64 636:iPTR, VR128:v16i8:$src)
+ // Pattern: (intrinsic_wo_chain:v2i64 637:iPTR, VR128:v16i8:$src)
// Emits: (PMOVSXBQrr:v2i64 VR128:v16i8:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(636)) {
+ if (CN1 == INT64_C(637)) {
SDNode *Result = Emit_107(N, X86::PMOVSXBQrr, MVT::v2i64);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2i64 642:iPTR, VR128:v16i8:$src)
+ // Pattern: (intrinsic_wo_chain:v2i64 643:iPTR, VR128:v16i8:$src)
// Emits: (PMOVZXBQrr:v2i64 VR128:v16i8:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(642)) {
+ if (CN1 == INT64_C(643)) {
SDNode *Result = Emit_107(N, X86::PMOVZXBQrr, MVT::v2i64);
return Result;
}
}
}
- // Pattern: (intrinsic_wo_chain:v2i64 667:iPTR, VR128:v2i64:$src1, VR128:v2i64:$src2)
+ // Pattern: (intrinsic_wo_chain:v2i64 668:iPTR, VR128:v2i64:$src1, VR128:v2i64:$src2)
// Emits: (PCMPGTQrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if ((Subtarget->hasSSE42())) {
@@ -22425,7 +22294,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(SDNode *N) {
ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(667)) {
+ if (CN1 == INT64_C(668)) {
SDNode *Result = Emit_110(N, X86::PCMPGTQrr, MVT::v2i64);
return Result;
}
@@ -22480,18 +22349,53 @@ DISABLE_INLINE SDNode *Emit_138(SDNode *N, unsigned Opc0, MVT::SimpleValueType V
return ResNode;
}
SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
- if ((Subtarget->hasSSE41())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
+ if ((Subtarget->hasSSE41())) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v4f32 610:iPTR, VR128:v4f32:$src1, (bitconvert:v4f32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (imm:i32):$src3)
- // Emits: (BLENDPSrmi:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2, (imm:i32):$src3)
+ // Pattern: (intrinsic_wo_chain:v4f32 611:iPTR, VR128:v4f32:$src1, (bitconvert:v4f32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (imm:i32):$src3)
+ // Emits: (BLENDPSrmi:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2, (imm:i32):$src3)
+ // Pattern complexity = 36 cost = 1 size = 3
+ if (CN1 == INT64_C(611)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4)) {
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant &&
+ N20.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_119(N, X86::BLENDPSrmi, MVT::v4f32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if (CN1 == INT64_C(615)) {
+ SDValue N1 = N->getOperand(1);
+
+ // Pattern: (intrinsic_wo_chain:v4f32 615:iPTR, VR128:v4f32:$src1, (bitconvert:v4f32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (imm:i32):$src3)
+ // Emits: (DPPSrmi:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2, (imm:i32):$src3)
// Pattern complexity = 36 cost = 1 size = 3
- if (CN1 == INT64_C(610)) {
- SDValue N1 = N->getOperand(1);
+ {
SDValue N2 = N->getOperand(2);
if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
@@ -22513,7 +22417,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(SDNode *N) {
SDValue N3 = N->getOperand(3);
if (N3.getNode()->getOpcode() == ISD::Constant &&
N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_119(N, X86::BLENDPSrmi, MVT::v4f32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_119(N, X86::DPPSrmi, MVT::v4f32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -22521,70 +22425,33 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(SDNode *N) {
}
}
}
- if (CN1 == INT64_C(614)) {
- SDValue N1 = N->getOperand(1);
- // Pattern: (intrinsic_wo_chain:v4f32 614:iPTR, VR128:v4f32:$src1, (bitconvert:v4f32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (imm:i32):$src3)
- // Emits: (DPPSrmi:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2, (imm:i32):$src3)
- // Pattern complexity = 36 cost = 1 size = 3
- {
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4)) {
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant &&
- N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_119(N, X86::DPPSrmi, MVT::v4f32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (intrinsic_wo_chain:v4f32 614:iPTR, (bitconvert:v4f32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v4f32:$src1, (imm:i32):$src3)
- // Emits: (DPPSrmi:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2, (imm:i32):$src3)
- // Pattern complexity = 36 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant &&
- N10.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_126(N, X86::DPPSrmi, MVT::v4f32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4f32 615:iPTR, (bitconvert:v4f32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v4f32:$src1, (imm:i32):$src3)
+ // Emits: (DPPSrmi:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2, (imm:i32):$src3)
+ // Pattern complexity = 36 cost = 1 size = 3
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant &&
+ N10.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_126(N, X86::DPPSrmi, MVT::v4f32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
@@ -22592,173 +22459,173 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(SDNode *N) {
}
}
}
- if ((Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
+ }
+ if ((Subtarget->hasSSE1())) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v4f32 677:iPTR, VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i8):$cc)
- // Emits: (Int_CMPSSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src, (imm:i8):$cc)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(677)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_123(N, X86::Int_CMPSSrm, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4f32 678:iPTR, VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i8):$cc)
+ // Emits: (Int_CMPSSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src, (imm:i8):$cc)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(678)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode())) {
+ SDValue N21 = N2.getNode()->getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_123(N, X86::Int_CMPSSrm, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4f32 676:iPTR, VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (imm:i8):$cc)
- // Emits: (CMPPSrmi:v4f32 VR128:v4f32:$src1, addr:iPTR:$src, (imm:i8):$cc)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(676)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode()) &&
- Predicate_memop(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_123(N, X86::CMPPSrmi, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4f32 677:iPTR, VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (imm:i8):$cc)
+ // Emits: (CMPPSrmi:v4f32 VR128:v4f32:$src1, addr:iPTR:$src, (imm:i8):$cc)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(677)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode()) &&
+ Predicate_memop(N2.getNode())) {
+ SDValue N21 = N2.getNode()->getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_123(N, X86::CMPPSrmi, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
}
}
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4f32 509:iPTR, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (Int_CVTDQ2PSrm:v4f32 addr:iPTR:$src)
- // Pattern complexity = 33 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(509)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_115(N, X86::Int_CVTDQ2PSrm, MVT::v4f32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4f32 510:iPTR, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (Int_CVTDQ2PSrm:v4f32 addr:iPTR:$src)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(510)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_115(N, X86::Int_CVTDQ2PSrm, MVT::v4f32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
}
}
- if ((Subtarget->hasSSE41())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
+ }
+ if ((Subtarget->hasSSE41())) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v4f32 653:iPTR, (ld:v4f32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (imm:i32):$src2)
- // Emits: (ROUNDPSm_Int:v4f32 addr:iPTR:$src1, (imm:i32):$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(653)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_137(N, X86::ROUNDPSm_Int, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4f32 654:iPTR, (ld:v4f32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (imm:i32):$src2)
+ // Emits: (ROUNDPSm_Int:v4f32 addr:iPTR:$src1, (imm:i32):$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(654)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_137(N, X86::ROUNDPSm_Int, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4f32 612:iPTR, VR128:v4f32:$src1, (bitconvert:v4f32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), XMM0:v4f32)
- // Emits: (BLENDVPSrm0:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(612)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4)) {
- SDValue N3 = N->getOperand(3);
- if (N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_121(N, X86::BLENDVPSrm0, MVT::v4f32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4f32 613:iPTR, VR128:v4f32:$src1, (bitconvert:v4f32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), XMM0:v4f32)
+ // Emits: (BLENDVPSrm0:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(613)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4)) {
+ SDValue N3 = N->getOperand(3);
+ if (N20.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_121(N, X86::BLENDVPSrm0, MVT::v4f32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
@@ -22766,586 +22633,579 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(SDNode *N) {
}
}
}
- if ((Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
+ }
+ if ((Subtarget->hasSSE1())) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v4f32 689:iPTR, VR128:v4f32:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
- // Emits: (Int_CVTSI2SS64rm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(689)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode()) &&
- Predicate_loadi64(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_109(N, X86::Int_CVTSI2SS64rm, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4f32 690:iPTR, VR128:v4f32:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
+ // Emits: (Int_CVTSI2SS64rm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(690)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode()) &&
+ Predicate_loadi64(N2.getNode())) {
+ SDValue N21 = N2.getNode()->getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDNode *Result = Emit_109(N, X86::Int_CVTSI2SS64rm, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4f32 686:iPTR, VR128:v4f32:$src1, (ld:v2i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (Int_CVTPI2PSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(686)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_109(N, X86::Int_CVTPI2PSrm, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4f32 687:iPTR, VR128:v4f32:$src1, (ld:v2i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (Int_CVTPI2PSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(687)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode())) {
+ SDValue N21 = N2.getNode()->getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDNode *Result = Emit_109(N, X86::Int_CVTPI2PSrm, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4f32 688:iPTR, VR128:v4f32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
- // Emits: (Int_CVTSI2SSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(688)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_loadi32(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_109(N, X86::Int_CVTSI2SSrm, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4f32 689:iPTR, VR128:v4f32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
+ // Emits: (Int_CVTSI2SSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(689)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_loadi32(N2.getNode())) {
+ SDValue N21 = N2.getNode()->getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDNode *Result = Emit_109(N, X86::Int_CVTSI2SSrm, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4f32 699:iPTR, VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (MAXPSrm_Int:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(699)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode()) &&
- Predicate_memop(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_109(N, X86::MAXPSrm_Int, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4f32 700:iPTR, VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (MAXPSrm_Int:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(700)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode()) &&
+ Predicate_memop(N2.getNode())) {
+ SDValue N21 = N2.getNode()->getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDNode *Result = Emit_109(N, X86::MAXPSrm_Int, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4f32 701:iPTR, VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (MINPSrm_Int:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(701)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode()) &&
- Predicate_memop(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_109(N, X86::MINPSrm_Int, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4f32 702:iPTR, VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (MINPSrm_Int:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(702)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode()) &&
+ Predicate_memop(N2.getNode())) {
+ SDValue N21 = N2.getNode()->getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDNode *Result = Emit_109(N, X86::MINPSrm_Int, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4f32 711:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (SQRTPSm_Int:v4f32 addr:iPTR:$src)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(711)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_108(N, X86::SQRTPSm_Int, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4f32 712:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (SQRTPSm_Int:v4f32 addr:iPTR:$src)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(712)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_108(N, X86::SQRTPSm_Int, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4f32 708:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (RSQRTPSm_Int:v4f32 addr:iPTR:$src)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(708)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_108(N, X86::RSQRTPSm_Int, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4f32 709:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (RSQRTPSm_Int:v4f32 addr:iPTR:$src)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(709)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_108(N, X86::RSQRTPSm_Int, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4f32 706:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (RCPPSm_Int:v4f32 addr:iPTR:$src)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(706)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_108(N, X86::RCPPSm_Int, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4f32 707:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (RCPPSm_Int:v4f32 addr:iPTR:$src)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(707)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_108(N, X86::RCPPSm_Int, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
}
}
}
}
}
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v4f32 511:iPTR, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (Int_CVTPD2PSrm:v4f32 addr:iPTR:$src)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(511)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTPD2PSrm, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4f32 512:iPTR, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (Int_CVTPD2PSrm:v4f32 addr:iPTR:$src)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(512)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_108(N, X86::Int_CVTPD2PSrm, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4f32 516:iPTR, VR128:v4f32:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (Int_CVTSD2SSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(516)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_109(N, X86::Int_CVTSD2SSrm, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4f32 517:iPTR, VR128:v4f32:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (Int_CVTSD2SSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(517)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode())) {
+ SDValue N21 = N2.getNode()->getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDNode *Result = Emit_109(N, X86::Int_CVTSD2SSrm, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
}
}
}
}
}
- if ((Subtarget->hasSSE3())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
+ }
+ if ((Subtarget->hasSSE3())) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v4f32 601:iPTR, VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (ADDSUBPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(601)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode()) &&
- Predicate_memop(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_109(N, X86::ADDSUBPSrm, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4f32 602:iPTR, VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (ADDSUBPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(602)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode()) &&
+ Predicate_memop(N2.getNode())) {
+ SDValue N21 = N2.getNode()->getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDNode *Result = Emit_109(N, X86::ADDSUBPSrm, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4f32 603:iPTR, VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (HADDPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(603)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode()) &&
- Predicate_memop(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_109(N, X86::HADDPSrm, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4f32 604:iPTR, VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (HADDPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(604)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode()) &&
+ Predicate_memop(N2.getNode())) {
+ SDValue N21 = N2.getNode()->getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDNode *Result = Emit_109(N, X86::HADDPSrm, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4f32 605:iPTR, VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (HSUBPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(605)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode()) &&
- Predicate_memop(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_109(N, X86::HSUBPSrm, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4f32 606:iPTR, VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (HSUBPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(606)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode()) &&
+ Predicate_memop(N2.getNode())) {
+ SDValue N21 = N2.getNode()->getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDNode *Result = Emit_109(N, X86::HSUBPSrm, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
}
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v4f32 655:iPTR, VR128:v4f32:$src1, sse_load_f32:v4f32:$src2, (imm:i32):$src3)
- // Emits: (ROUNDSSm_Int:v4f32 VR128:v4f32:$src1, sse_load_f32:v4f32:$src2, (imm:i32):$src3)
- // Pattern complexity = 29 cost = 1 size = 3
- if ((Subtarget->hasSSE41())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(655)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- SDValue CPInChain;
- SDValue Chain2;
- if (SelectScalarSSELoad(N, SDValue(N, 0), N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_138(N, X86::ROUNDSSm_Int, MVT::v4f32, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4f32 656:iPTR, VR128:v4f32:$src1, sse_load_f32:v4f32:$src2, (imm:i32):$src3)
+ // Emits: (ROUNDSSm_Int:v4f32 VR128:v4f32:$src1, sse_load_f32:v4f32:$src2, (imm:i32):$src3)
+ // Pattern complexity = 29 cost = 1 size = 3
+ if ((Subtarget->hasSSE41())) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(656)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ SDValue CPInChain;
+ SDValue Chain2;
+ if (SelectScalarSSELoad(N, SDValue(N, 0), N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_138(N, X86::ROUNDSSm_Int, MVT::v4f32, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
+ return Result;
}
}
}
}
- if ((Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
+ }
+ if ((Subtarget->hasSSE1())) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v4f32 675:iPTR, VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
- // Emits: (ADDSSrm_Int:v4f32 VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
- // Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(675)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- SDValue CPInChain;
- SDValue Chain2;
- if (SelectScalarSSELoad(N, SDValue(N, 0), N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
- SDNode *Result = Emit_135(N, X86::ADDSSrm_Int, MVT::v4f32, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4f32 676:iPTR, VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
+ // Emits: (ADDSSrm_Int:v4f32 VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
+ // Pattern complexity = 26 cost = 1 size = 3
+ if (CN1 == INT64_C(676)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ SDValue CPInChain;
+ SDValue Chain2;
+ if (SelectScalarSSELoad(N, SDValue(N, 0), N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
+ SDNode *Result = Emit_135(N, X86::ADDSSrm_Int, MVT::v4f32, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
+ return Result;
}
+ }
- // Pattern: (intrinsic_wo_chain:v4f32 705:iPTR, VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
- // Emits: (MULSSrm_Int:v4f32 VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
- // Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(705)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- SDValue CPInChain;
- SDValue Chain2;
- if (SelectScalarSSELoad(N, SDValue(N, 0), N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
- SDNode *Result = Emit_135(N, X86::MULSSrm_Int, MVT::v4f32, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4f32 706:iPTR, VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
+ // Emits: (MULSSrm_Int:v4f32 VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
+ // Pattern complexity = 26 cost = 1 size = 3
+ if (CN1 == INT64_C(706)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ SDValue CPInChain;
+ SDValue Chain2;
+ if (SelectScalarSSELoad(N, SDValue(N, 0), N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
+ SDNode *Result = Emit_135(N, X86::MULSSrm_Int, MVT::v4f32, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
+ return Result;
}
+ }
- // Pattern: (intrinsic_wo_chain:v4f32 715:iPTR, VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
- // Emits: (SUBSSrm_Int:v4f32 VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
- // Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(715)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- SDValue CPInChain;
- SDValue Chain2;
- if (SelectScalarSSELoad(N, SDValue(N, 0), N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
- SDNode *Result = Emit_135(N, X86::SUBSSrm_Int, MVT::v4f32, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4f32 716:iPTR, VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
+ // Emits: (SUBSSrm_Int:v4f32 VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
+ // Pattern complexity = 26 cost = 1 size = 3
+ if (CN1 == INT64_C(716)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ SDValue CPInChain;
+ SDValue Chain2;
+ if (SelectScalarSSELoad(N, SDValue(N, 0), N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
+ SDNode *Result = Emit_135(N, X86::SUBSSrm_Int, MVT::v4f32, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
+ return Result;
}
+ }
- // Pattern: (intrinsic_wo_chain:v4f32 696:iPTR, VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
- // Emits: (DIVSSrm_Int:v4f32 VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
- // Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(696)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- SDValue CPInChain;
- SDValue Chain2;
- if (SelectScalarSSELoad(N, SDValue(N, 0), N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
- SDNode *Result = Emit_135(N, X86::DIVSSrm_Int, MVT::v4f32, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4f32 697:iPTR, VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
+ // Emits: (DIVSSrm_Int:v4f32 VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
+ // Pattern complexity = 26 cost = 1 size = 3
+ if (CN1 == INT64_C(697)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ SDValue CPInChain;
+ SDValue Chain2;
+ if (SelectScalarSSELoad(N, SDValue(N, 0), N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
+ SDNode *Result = Emit_135(N, X86::DIVSSrm_Int, MVT::v4f32, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
+ return Result;
}
+ }
- // Pattern: (intrinsic_wo_chain:v4f32 700:iPTR, VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
- // Emits: (MAXSSrm_Int:v4f32 VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
- // Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(700)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- SDValue CPInChain;
- SDValue Chain2;
- if (SelectScalarSSELoad(N, SDValue(N, 0), N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
- SDNode *Result = Emit_135(N, X86::MAXSSrm_Int, MVT::v4f32, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4f32 701:iPTR, VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
+ // Emits: (MAXSSrm_Int:v4f32 VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
+ // Pattern complexity = 26 cost = 1 size = 3
+ if (CN1 == INT64_C(701)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ SDValue CPInChain;
+ SDValue Chain2;
+ if (SelectScalarSSELoad(N, SDValue(N, 0), N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
+ SDNode *Result = Emit_135(N, X86::MAXSSrm_Int, MVT::v4f32, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
+ return Result;
}
+ }
- // Pattern: (intrinsic_wo_chain:v4f32 702:iPTR, VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
- // Emits: (MINSSrm_Int:v4f32 VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
- // Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(702)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- SDValue CPInChain;
- SDValue Chain2;
- if (SelectScalarSSELoad(N, SDValue(N, 0), N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
- SDNode *Result = Emit_135(N, X86::MINSSrm_Int, MVT::v4f32, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4f32 703:iPTR, VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
+ // Emits: (MINSSrm_Int:v4f32 VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
+ // Pattern complexity = 26 cost = 1 size = 3
+ if (CN1 == INT64_C(703)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ SDValue CPInChain;
+ SDValue Chain2;
+ if (SelectScalarSSELoad(N, SDValue(N, 0), N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
+ SDNode *Result = Emit_135(N, X86::MINSSrm_Int, MVT::v4f32, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
+ return Result;
}
+ }
- // Pattern: (intrinsic_wo_chain:v4f32 712:iPTR, sse_load_f32:v4f32:$src)
- // Emits: (SQRTSSm_Int:v4f32 sse_load_f32:v4f32:$src)
- // Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(712)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- SDValue CPInChain;
- SDValue Chain1;
- if (SelectScalarSSELoad(N, SDValue(N, 0), N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, CPInChain, Chain1)) {
- SDNode *Result = Emit_136(N, X86::SQRTSSm_Int, MVT::v4f32, CPInChain, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain1);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4f32 713:iPTR, sse_load_f32:v4f32:$src)
+ // Emits: (SQRTSSm_Int:v4f32 sse_load_f32:v4f32:$src)
+ // Pattern complexity = 26 cost = 1 size = 3
+ if (CN1 == INT64_C(713)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ SDValue CPInChain;
+ SDValue Chain1;
+ if (SelectScalarSSELoad(N, SDValue(N, 0), N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, CPInChain, Chain1)) {
+ SDNode *Result = Emit_136(N, X86::SQRTSSm_Int, MVT::v4f32, CPInChain, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain1);
+ return Result;
}
+ }
- // Pattern: (intrinsic_wo_chain:v4f32 709:iPTR, sse_load_f32:v4f32:$src)
- // Emits: (RSQRTSSm_Int:v4f32 sse_load_f32:v4f32:$src)
- // Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(709)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- SDValue CPInChain;
- SDValue Chain1;
- if (SelectScalarSSELoad(N, SDValue(N, 0), N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, CPInChain, Chain1)) {
- SDNode *Result = Emit_136(N, X86::RSQRTSSm_Int, MVT::v4f32, CPInChain, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain1);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4f32 710:iPTR, sse_load_f32:v4f32:$src)
+ // Emits: (RSQRTSSm_Int:v4f32 sse_load_f32:v4f32:$src)
+ // Pattern complexity = 26 cost = 1 size = 3
+ if (CN1 == INT64_C(710)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ SDValue CPInChain;
+ SDValue Chain1;
+ if (SelectScalarSSELoad(N, SDValue(N, 0), N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, CPInChain, Chain1)) {
+ SDNode *Result = Emit_136(N, X86::RSQRTSSm_Int, MVT::v4f32, CPInChain, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain1);
+ return Result;
}
+ }
- // Pattern: (intrinsic_wo_chain:v4f32 707:iPTR, sse_load_f32:v4f32:$src)
- // Emits: (RCPSSm_Int:v4f32 sse_load_f32:v4f32:$src)
- // Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(707)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- SDValue CPInChain;
- SDValue Chain1;
- if (SelectScalarSSELoad(N, SDValue(N, 0), N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, CPInChain, Chain1)) {
- SDNode *Result = Emit_136(N, X86::RCPSSm_Int, MVT::v4f32, CPInChain, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain1);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v4f32 708:iPTR, sse_load_f32:v4f32:$src)
+ // Emits: (RCPSSm_Int:v4f32 sse_load_f32:v4f32:$src)
+ // Pattern complexity = 26 cost = 1 size = 3
+ if (CN1 == INT64_C(708)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ SDValue CPInChain;
+ SDValue Chain1;
+ if (SelectScalarSSELoad(N, SDValue(N, 0), N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, CPInChain, Chain1)) {
+ SDNode *Result = Emit_136(N, X86::RCPSSm_Int, MVT::v4f32, CPInChain, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain1);
+ return Result;
}
}
- }
- }
- if ((Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v4f32 677:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src, (imm:i8):$cc)
+ // Pattern: (intrinsic_wo_chain:v4f32 678:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src, (imm:i8):$cc)
// Emits: (Int_CMPSSrr:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src, (imm:i8):$cc)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(677)) {
+ if (CN1 == INT64_C(678)) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
SDValue N3 = N->getOperand(3);
@@ -23355,10 +23215,10 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(SDNode *N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4f32 676:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src, (imm:i8):$cc)
+ // Pattern: (intrinsic_wo_chain:v4f32 677:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src, (imm:i8):$cc)
// Emits: (CMPPSrri:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src, (imm:i8):$cc)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(676)) {
+ if (CN1 == INT64_C(677)) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
SDValue N3 = N->getOperand(3);
@@ -23375,10 +23235,10 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(SDNode *N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v4f32 653:iPTR, VR128:v4f32:$src1, (imm:i32):$src2)
+ // Pattern: (intrinsic_wo_chain:v4f32 654:iPTR, VR128:v4f32:$src1, (imm:i32):$src2)
// Emits: (ROUNDPSr_Int:v4f32 VR128:v4f32:$src1, (imm:i32):$src2)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(653)) {
+ if (CN1 == INT64_C(654)) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
if (N2.getNode()->getOpcode() == ISD::Constant) {
@@ -23387,10 +23247,10 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(SDNode *N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4f32 655:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2, (imm:i32):$src3)
+ // Pattern: (intrinsic_wo_chain:v4f32 656:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2, (imm:i32):$src3)
// Emits: (ROUNDSSr_Int:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2, (imm:i32):$src3)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(655)) {
+ if (CN1 == INT64_C(656)) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
SDValue N3 = N->getOperand(3);
@@ -23400,10 +23260,10 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(SDNode *N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4f32 610:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2, (imm:i32):$src3)
+ // Pattern: (intrinsic_wo_chain:v4f32 611:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2, (imm:i32):$src3)
// Emits: (BLENDPSrri:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2, (imm:i32):$src3)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(610)) {
+ if (CN1 == INT64_C(611)) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
SDValue N3 = N->getOperand(3);
@@ -23413,10 +23273,10 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(SDNode *N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4f32 614:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2, (imm:i32):$src3)
+ // Pattern: (intrinsic_wo_chain:v4f32 615:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2, (imm:i32):$src3)
// Emits: (DPPSrri:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2, (imm:i32):$src3)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(614)) {
+ if (CN1 == INT64_C(615)) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
SDValue N3 = N->getOperand(3);
@@ -23428,7 +23288,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(SDNode *N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4f32 616:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2, (imm:i32):$src3)
+ // Pattern: (intrinsic_wo_chain:v4f32 617:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2, (imm:i32):$src3)
// Emits: (INSERTPSrr:v4f32 VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i32):$src3)
// Pattern complexity = 11 cost = 1 size = 3
{
@@ -23436,7 +23296,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(SDNode *N) {
ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(616)) {
+ if (CN1 == INT64_C(617)) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
SDValue N3 = N->getOperand(3);
@@ -23453,138 +23313,138 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(SDNode *N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v4f32 689:iPTR, VR128:v4f32:$src1, GR64:i64:$src2)
+ // Pattern: (intrinsic_wo_chain:v4f32 690:iPTR, VR128:v4f32:$src1, GR64:i64:$src2)
// Emits: (Int_CVTSI2SS64rr:v4f32 VR128:v4f32:$src1, GR64:i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(689)) {
+ if (CN1 == INT64_C(690)) {
SDNode *Result = Emit_110(N, X86::Int_CVTSI2SS64rr, MVT::v4f32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4f32 686:iPTR, VR128:v4f32:$src1, VR64:v2i32:$src2)
+ // Pattern: (intrinsic_wo_chain:v4f32 687:iPTR, VR128:v4f32:$src1, VR64:v2i32:$src2)
// Emits: (Int_CVTPI2PSrr:v4f32 VR128:v4f32:$src1, VR64:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(686)) {
+ if (CN1 == INT64_C(687)) {
SDNode *Result = Emit_110(N, X86::Int_CVTPI2PSrr, MVT::v4f32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4f32 688:iPTR, VR128:v4f32:$src1, GR32:i32:$src2)
+ // Pattern: (intrinsic_wo_chain:v4f32 689:iPTR, VR128:v4f32:$src1, GR32:i32:$src2)
// Emits: (Int_CVTSI2SSrr:v4f32 VR128:v4f32:$src1, GR32:i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(688)) {
+ if (CN1 == INT64_C(689)) {
SDNode *Result = Emit_110(N, X86::Int_CVTSI2SSrr, MVT::v4f32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4f32 675:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Pattern: (intrinsic_wo_chain:v4f32 676:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
// Emits: (ADDSSrr_Int:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(675)) {
+ if (CN1 == INT64_C(676)) {
SDNode *Result = Emit_110(N, X86::ADDSSrr_Int, MVT::v4f32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4f32 705:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Pattern: (intrinsic_wo_chain:v4f32 706:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
// Emits: (MULSSrr_Int:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(705)) {
+ if (CN1 == INT64_C(706)) {
SDNode *Result = Emit_110(N, X86::MULSSrr_Int, MVT::v4f32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4f32 715:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Pattern: (intrinsic_wo_chain:v4f32 716:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
// Emits: (SUBSSrr_Int:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(715)) {
+ if (CN1 == INT64_C(716)) {
SDNode *Result = Emit_110(N, X86::SUBSSrr_Int, MVT::v4f32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4f32 696:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Pattern: (intrinsic_wo_chain:v4f32 697:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
// Emits: (DIVSSrr_Int:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(696)) {
+ if (CN1 == INT64_C(697)) {
SDNode *Result = Emit_110(N, X86::DIVSSrr_Int, MVT::v4f32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4f32 700:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Pattern: (intrinsic_wo_chain:v4f32 701:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
// Emits: (MAXSSrr_Int:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(700)) {
+ if (CN1 == INT64_C(701)) {
SDNode *Result = Emit_110(N, X86::MAXSSrr_Int, MVT::v4f32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4f32 699:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Pattern: (intrinsic_wo_chain:v4f32 700:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
// Emits: (MAXPSrr_Int:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(699)) {
+ if (CN1 == INT64_C(700)) {
SDNode *Result = Emit_110(N, X86::MAXPSrr_Int, MVT::v4f32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4f32 702:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Pattern: (intrinsic_wo_chain:v4f32 703:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
// Emits: (MINSSrr_Int:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(702)) {
+ if (CN1 == INT64_C(703)) {
SDNode *Result = Emit_110(N, X86::MINSSrr_Int, MVT::v4f32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4f32 701:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Pattern: (intrinsic_wo_chain:v4f32 702:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
// Emits: (MINPSrr_Int:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(701)) {
+ if (CN1 == INT64_C(702)) {
SDNode *Result = Emit_110(N, X86::MINPSrr_Int, MVT::v4f32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4f32 712:iPTR, VR128:v4f32:$src)
+ // Pattern: (intrinsic_wo_chain:v4f32 713:iPTR, VR128:v4f32:$src)
// Emits: (SQRTSSr_Int:v4f32 VR128:v4f32:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(712)) {
+ if (CN1 == INT64_C(713)) {
SDNode *Result = Emit_107(N, X86::SQRTSSr_Int, MVT::v4f32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4f32 711:iPTR, VR128:v4f32:$src)
+ // Pattern: (intrinsic_wo_chain:v4f32 712:iPTR, VR128:v4f32:$src)
// Emits: (SQRTPSr_Int:v4f32 VR128:v4f32:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(711)) {
+ if (CN1 == INT64_C(712)) {
SDNode *Result = Emit_107(N, X86::SQRTPSr_Int, MVT::v4f32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4f32 709:iPTR, VR128:v4f32:$src)
+ // Pattern: (intrinsic_wo_chain:v4f32 710:iPTR, VR128:v4f32:$src)
// Emits: (RSQRTSSr_Int:v4f32 VR128:v4f32:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(709)) {
+ if (CN1 == INT64_C(710)) {
SDNode *Result = Emit_107(N, X86::RSQRTSSr_Int, MVT::v4f32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4f32 708:iPTR, VR128:v4f32:$src)
+ // Pattern: (intrinsic_wo_chain:v4f32 709:iPTR, VR128:v4f32:$src)
// Emits: (RSQRTPSr_Int:v4f32 VR128:v4f32:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(708)) {
+ if (CN1 == INT64_C(709)) {
SDNode *Result = Emit_107(N, X86::RSQRTPSr_Int, MVT::v4f32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4f32 707:iPTR, VR128:v4f32:$src)
+ // Pattern: (intrinsic_wo_chain:v4f32 708:iPTR, VR128:v4f32:$src)
// Emits: (RCPSSr_Int:v4f32 VR128:v4f32:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(707)) {
+ if (CN1 == INT64_C(708)) {
SDNode *Result = Emit_107(N, X86::RCPSSr_Int, MVT::v4f32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4f32 706:iPTR, VR128:v4f32:$src)
+ // Pattern: (intrinsic_wo_chain:v4f32 707:iPTR, VR128:v4f32:$src)
// Emits: (RCPPSr_Int:v4f32 VR128:v4f32:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(706)) {
+ if (CN1 == INT64_C(707)) {
SDNode *Result = Emit_107(N, X86::RCPPSr_Int, MVT::v4f32);
return Result;
}
@@ -23596,26 +23456,26 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(SDNode *N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v4f32 509:iPTR, VR128:v4i32:$src)
+ // Pattern: (intrinsic_wo_chain:v4f32 510:iPTR, VR128:v4i32:$src)
// Emits: (Int_CVTDQ2PSrr:v4f32 VR128:v4i32:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(509)) {
+ if (CN1 == INT64_C(510)) {
SDNode *Result = Emit_107(N, X86::Int_CVTDQ2PSrr, MVT::v4f32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4f32 511:iPTR, VR128:v2f64:$src)
+ // Pattern: (intrinsic_wo_chain:v4f32 512:iPTR, VR128:v2f64:$src)
// Emits: (Int_CVTPD2PSrr:v4f32 VR128:v2f64:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(511)) {
+ if (CN1 == INT64_C(512)) {
SDNode *Result = Emit_107(N, X86::Int_CVTPD2PSrr, MVT::v4f32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4f32 516:iPTR, VR128:v4f32:$src1, VR128:v2f64:$src2)
+ // Pattern: (intrinsic_wo_chain:v4f32 517:iPTR, VR128:v4f32:$src1, VR128:v2f64:$src2)
// Emits: (Int_CVTSD2SSrr:v4f32 VR128:v4f32:$src1, VR128:v2f64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(516)) {
+ if (CN1 == INT64_C(517)) {
SDNode *Result = Emit_110(N, X86::Int_CVTSD2SSrr, MVT::v4f32);
return Result;
}
@@ -23627,33 +23487,33 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(SDNode *N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v4f32 601:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Pattern: (intrinsic_wo_chain:v4f32 602:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
// Emits: (ADDSUBPSrr:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(601)) {
+ if (CN1 == INT64_C(602)) {
SDNode *Result = Emit_110(N, X86::ADDSUBPSrr, MVT::v4f32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4f32 603:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Pattern: (intrinsic_wo_chain:v4f32 604:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
// Emits: (HADDPSrr:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(603)) {
+ if (CN1 == INT64_C(604)) {
SDNode *Result = Emit_110(N, X86::HADDPSrr, MVT::v4f32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4f32 605:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Pattern: (intrinsic_wo_chain:v4f32 606:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
// Emits: (HSUBPSrr:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(605)) {
+ if (CN1 == INT64_C(606)) {
SDNode *Result = Emit_110(N, X86::HSUBPSrr, MVT::v4f32);
return Result;
}
}
}
- // Pattern: (intrinsic_wo_chain:v4f32 612:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2, XMM0:v4f32)
+ // Pattern: (intrinsic_wo_chain:v4f32 613:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2, XMM0:v4f32)
// Emits: (BLENDVPSrr0:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if ((Subtarget->hasSSE41())) {
@@ -23661,7 +23521,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(SDNode *N) {
ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(612)) {
+ if (CN1 == INT64_C(613)) {
SDNode *Result = Emit_120(N, X86::BLENDVPSrr0, MVT::v4f32);
return Result;
}
@@ -23673,18 +23533,53 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(SDNode *N) {
}
SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
- if ((Subtarget->hasSSE41())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
+ if ((Subtarget->hasSSE41())) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (intrinsic_wo_chain:v2f64 610:iPTR, VR128:v2f64:$src1, (bitconvert:v2f64 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (imm:i32):$src3)
+ // Emits: (BLENDPDrmi:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2, (imm:i32):$src3)
+ // Pattern complexity = 36 cost = 1 size = 3
+ if (CN1 == INT64_C(610)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4)) {
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant &&
+ N20.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_119(N, X86::BLENDPDrmi, MVT::v2f64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if (CN1 == INT64_C(614)) {
+ SDValue N1 = N->getOperand(1);
- // Pattern: (intrinsic_wo_chain:v2f64 609:iPTR, VR128:v2f64:$src1, (bitconvert:v2f64 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (imm:i32):$src3)
- // Emits: (BLENDPDrmi:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2, (imm:i32):$src3)
+ // Pattern: (intrinsic_wo_chain:v2f64 614:iPTR, VR128:v2f64:$src1, (bitconvert:v2f64 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (imm:i32):$src3)
+ // Emits: (DPPDrmi:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2, (imm:i32):$src3)
// Pattern complexity = 36 cost = 1 size = 3
- if (CN1 == INT64_C(609)) {
- SDValue N1 = N->getOperand(1);
+ {
SDValue N2 = N->getOperand(2);
if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
@@ -23706,7 +23601,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(SDNode *N) {
SDValue N3 = N->getOperand(3);
if (N3.getNode()->getOpcode() == ISD::Constant &&
N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_119(N, X86::BLENDPDrmi, MVT::v2f64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_119(N, X86::DPPDrmi, MVT::v2f64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -23714,70 +23609,33 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(SDNode *N) {
}
}
}
- if (CN1 == INT64_C(613)) {
- SDValue N1 = N->getOperand(1);
-
- // Pattern: (intrinsic_wo_chain:v2f64 613:iPTR, VR128:v2f64:$src1, (bitconvert:v2f64 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (imm:i32):$src3)
- // Emits: (DPPDrmi:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2, (imm:i32):$src3)
- // Pattern complexity = 36 cost = 1 size = 3
- {
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4)) {
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant &&
- N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_119(N, X86::DPPDrmi, MVT::v2f64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
- }
- }
- }
- }
- }
- // Pattern: (intrinsic_wo_chain:v2f64 613:iPTR, (bitconvert:v2f64 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v2f64:$src1, (imm:i32):$src3)
- // Emits: (DPPDrmi:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2, (imm:i32):$src3)
- // Pattern complexity = 36 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant &&
- N10.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_126(N, X86::DPPDrmi, MVT::v2f64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v2f64 614:iPTR, (bitconvert:v2f64 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v2f64:$src1, (imm:i32):$src3)
+ // Emits: (DPPDrmi:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2, (imm:i32):$src3)
+ // Pattern complexity = 36 cost = 1 size = 3
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant &&
+ N10.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_126(N, X86::DPPDrmi, MVT::v2f64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
@@ -23785,166 +23643,166 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(SDNode *N) {
}
}
}
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v2f64 501:iPTR, VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i8):$cc)
- // Emits: (Int_CMPSDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src, (imm:i8):$cc)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(501)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_123(N, X86::Int_CMPSDrm, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v2f64 502:iPTR, VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i8):$cc)
+ // Emits: (Int_CMPSDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src, (imm:i8):$cc)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(502)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode())) {
+ SDValue N21 = N2.getNode()->getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_123(N, X86::Int_CMPSDrm, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v2f64 508:iPTR, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (Int_CVTDQ2PDrm:v2f64 addr:iPTR:$src)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(508)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_115(N, X86::Int_CVTDQ2PDrm, MVT::v2f64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v2f64 509:iPTR, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (Int_CVTDQ2PDrm:v2f64 addr:iPTR:$src)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(509)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_115(N, X86::Int_CVTDQ2PDrm, MVT::v2f64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v2f64 500:iPTR, VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (imm:i8):$cc)
- // Emits: (CMPPDrmi:v2f64 VR128:v2f64:$src1, addr:iPTR:$src, (imm:i8):$cc)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(500)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode()) &&
- Predicate_memop(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_123(N, X86::CMPPDrmi, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v2f64 501:iPTR, VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (imm:i8):$cc)
+ // Emits: (CMPPDrmi:v2f64 VR128:v2f64:$src1, addr:iPTR:$src, (imm:i8):$cc)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(501)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode()) &&
+ Predicate_memop(N2.getNode())) {
+ SDValue N21 = N2.getNode()->getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_123(N, X86::CMPPDrmi, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
}
}
}
}
}
}
- if ((Subtarget->hasSSE41())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
+ }
+ if ((Subtarget->hasSSE41())) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v2f64 652:iPTR, (ld:v2f64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (imm:i32):$src2)
- // Emits: (ROUNDPDm_Int:v2f64 addr:iPTR:$src1, (imm:i32):$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(652)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_137(N, X86::ROUNDPDm_Int, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v2f64 653:iPTR, (ld:v2f64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (imm:i32):$src2)
+ // Emits: (ROUNDPDm_Int:v2f64 addr:iPTR:$src1, (imm:i32):$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(653)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_137(N, X86::ROUNDPDm_Int, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v2f64 611:iPTR, VR128:v2f64:$src1, (bitconvert:v2f64 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), XMM0:v2f64)
- // Emits: (BLENDVPDrm0:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(611)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N2.hasOneUse()) {
- SDValue N20 = N2.getNode()->getOperand(0);
- if (N20.getNode()->getOpcode() == ISD::LOAD &&
- N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
- SDValue Chain20 = N20.getNode()->getOperand(0);
- if (Predicate_unindexedload(N20.getNode()) &&
- Predicate_load(N20.getNode()) &&
- Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getNode()->getOperand(1);
- SDValue CPTmpN201_0;
- SDValue CPTmpN201_1;
- SDValue CPTmpN201_2;
- SDValue CPTmpN201_3;
- SDValue CPTmpN201_4;
- if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4)) {
- SDValue N3 = N->getOperand(3);
- if (N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_121(N, X86::BLENDVPDrm0, MVT::v2f64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v2f64 612:iPTR, VR128:v2f64:$src1, (bitconvert:v2f64 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), XMM0:v2f64)
+ // Emits: (BLENDVPDrm0:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (CN1 == INT64_C(612)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N2.hasOneUse()) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
+ N20.hasOneUse() &&
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N20.getNode()) &&
+ Predicate_load(N20.getNode()) &&
+ Predicate_memop(N20.getNode())) {
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue CPTmpN201_0;
+ SDValue CPTmpN201_1;
+ SDValue CPTmpN201_2;
+ SDValue CPTmpN201_3;
+ SDValue CPTmpN201_4;
+ if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4)) {
+ SDValue N3 = N->getOperand(3);
+ if (N20.getValueType() == MVT::v16i8) {
+ SDNode *Result = Emit_121(N, X86::BLENDVPDrm0, MVT::v2f64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ return Result;
}
}
}
@@ -23952,489 +23810,482 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(SDNode *N) {
}
}
}
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v2f64 518:iPTR, VR128:v2f64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
- // Emits: (Int_CVTSI2SD64rm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(518)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode()) &&
- Predicate_loadi64(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_109(N, X86::Int_CVTSI2SD64rm, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v2f64 519:iPTR, VR128:v2f64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
+ // Emits: (Int_CVTSI2SD64rm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(519)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode()) &&
+ Predicate_loadi64(N2.getNode())) {
+ SDValue N21 = N2.getNode()->getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDNode *Result = Emit_109(N, X86::Int_CVTSI2SD64rm, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v2f64 685:iPTR, (ld:v2i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (Int_CVTPI2PDrm:v2f64 addr:iPTR:$src)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(685)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTPI2PDrm, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v2f64 686:iPTR, (ld:v2i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (Int_CVTPI2PDrm:v2f64 addr:iPTR:$src)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(686)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_108(N, X86::Int_CVTPI2PDrm, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v2f64 529:iPTR, VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (MAXPDrm_Int:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(529)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode()) &&
- Predicate_memop(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_109(N, X86::MAXPDrm_Int, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v2f64 530:iPTR, VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (MAXPDrm_Int:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(530)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode()) &&
+ Predicate_memop(N2.getNode())) {
+ SDValue N21 = N2.getNode()->getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDNode *Result = Emit_109(N, X86::MAXPDrm_Int, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v2f64 532:iPTR, VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (MINPDrm_Int:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(532)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode()) &&
- Predicate_memop(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_109(N, X86::MINPDrm_Int, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v2f64 533:iPTR, VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (MINPDrm_Int:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(533)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode()) &&
+ Predicate_memop(N2.getNode())) {
+ SDValue N21 = N2.getNode()->getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDNode *Result = Emit_109(N, X86::MINPDrm_Int, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v2f64 513:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (Int_CVTPS2PDrm:v2f64 addr:iPTR:$src)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(513)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTPS2PDrm, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v2f64 514:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (Int_CVTPS2PDrm:v2f64 addr:iPTR:$src)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(514)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_108(N, X86::Int_CVTPS2PDrm, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v2f64 517:iPTR, VR128:v2f64:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
- // Emits: (Int_CVTSI2SDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(517)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_loadi32(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_109(N, X86::Int_CVTSI2SDrm, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v2f64 518:iPTR, VR128:v2f64:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
+ // Emits: (Int_CVTSI2SDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(518)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_loadi32(N2.getNode())) {
+ SDValue N21 = N2.getNode()->getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDNode *Result = Emit_109(N, X86::Int_CVTSI2SDrm, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v2f64 519:iPTR, VR128:v2f64:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (Int_CVTSS2SDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(519)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_109(N, X86::Int_CVTSS2SDrm, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v2f64 520:iPTR, VR128:v2f64:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (Int_CVTSS2SDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(520)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode())) {
+ SDValue N21 = N2.getNode()->getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDNode *Result = Emit_109(N, X86::Int_CVTSS2SDrm, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v2f64 588:iPTR, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (SQRTPDm_Int:v2f64 addr:iPTR:$src)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(588)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_108(N, X86::SQRTPDm_Int, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v2f64 589:iPTR, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (SQRTPDm_Int:v2f64 addr:iPTR:$src)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(589)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_108(N, X86::SQRTPDm_Int, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
}
}
}
}
}
- if ((Subtarget->hasSSE3())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
+ }
+ if ((Subtarget->hasSSE3())) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v2f64 600:iPTR, VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (ADDSUBPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(600)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode()) &&
- Predicate_memop(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_109(N, X86::ADDSUBPDrm, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v2f64 601:iPTR, VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (ADDSUBPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(601)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode()) &&
+ Predicate_memop(N2.getNode())) {
+ SDValue N21 = N2.getNode()->getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDNode *Result = Emit_109(N, X86::ADDSUBPDrm, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v2f64 602:iPTR, VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (HADDPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(602)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode()) &&
- Predicate_memop(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_109(N, X86::HADDPDrm, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v2f64 603:iPTR, VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (HADDPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(603)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode()) &&
+ Predicate_memop(N2.getNode())) {
+ SDValue N21 = N2.getNode()->getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDNode *Result = Emit_109(N, X86::HADDPDrm, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v2f64 604:iPTR, VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (HSUBPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(604)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::LOAD &&
- N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
- SDValue Chain2 = N2.getNode()->getOperand(0);
- if (Predicate_unindexedload(N2.getNode()) &&
- Predicate_load(N2.getNode()) &&
- Predicate_memop(N2.getNode())) {
- SDValue N21 = N2.getNode()->getOperand(1);
- SDValue CPTmpN21_0;
- SDValue CPTmpN21_1;
- SDValue CPTmpN21_2;
- SDValue CPTmpN21_3;
- SDValue CPTmpN21_4;
- if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_109(N, X86::HSUBPDrm, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v2f64 605:iPTR, VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (HSUBPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(605)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
+ N2.hasOneUse() &&
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N2.getNode()) &&
+ Predicate_load(N2.getNode()) &&
+ Predicate_memop(N2.getNode())) {
+ SDValue N21 = N2.getNode()->getOperand(1);
+ SDValue CPTmpN21_0;
+ SDValue CPTmpN21_1;
+ SDValue CPTmpN21_2;
+ SDValue CPTmpN21_3;
+ SDValue CPTmpN21_4;
+ if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
+ SDNode *Result = Emit_109(N, X86::HSUBPDrm, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ return Result;
}
}
}
}
}
+ }
- // Pattern: (intrinsic_wo_chain:v2f64 654:iPTR, VR128:v2f64:$src1, sse_load_f64:v2f64:$src2, (imm:i32):$src3)
- // Emits: (ROUNDSDm_Int:v2f64 VR128:v2f64:$src1, sse_load_f64:v2f64:$src2, (imm:i32):$src3)
- // Pattern complexity = 29 cost = 1 size = 3
- if ((Subtarget->hasSSE41())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(654)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- SDValue CPInChain;
- SDValue Chain2;
- if (SelectScalarSSELoad(N, SDValue(N, 0), N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
- SDValue N3 = N->getOperand(3);
- if (N3.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_138(N, X86::ROUNDSDm_Int, MVT::v2f64, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v2f64 655:iPTR, VR128:v2f64:$src1, sse_load_f64:v2f64:$src2, (imm:i32):$src3)
+ // Emits: (ROUNDSDm_Int:v2f64 VR128:v2f64:$src1, sse_load_f64:v2f64:$src2, (imm:i32):$src3)
+ // Pattern complexity = 29 cost = 1 size = 3
+ if ((Subtarget->hasSSE41())) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(655)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ SDValue CPInChain;
+ SDValue Chain2;
+ if (SelectScalarSSELoad(N, SDValue(N, 0), N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_138(N, X86::ROUNDSDm_Int, MVT::v2f64, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
+ return Result;
}
}
}
}
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v2f64 498:iPTR, VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
- // Emits: (ADDSDrm_Int:v2f64 VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
- // Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(498)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- SDValue CPInChain;
- SDValue Chain2;
- if (SelectScalarSSELoad(N, SDValue(N, 0), N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
- SDNode *Result = Emit_135(N, X86::ADDSDrm_Int, MVT::v2f64, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v2f64 499:iPTR, VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
+ // Emits: (ADDSDrm_Int:v2f64 VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
+ // Pattern complexity = 26 cost = 1 size = 3
+ if (CN1 == INT64_C(499)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ SDValue CPInChain;
+ SDValue Chain2;
+ if (SelectScalarSSELoad(N, SDValue(N, 0), N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
+ SDNode *Result = Emit_135(N, X86::ADDSDrm_Int, MVT::v2f64, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
+ return Result;
}
+ }
- // Pattern: (intrinsic_wo_chain:v2f64 538:iPTR, VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
- // Emits: (MULSDrm_Int:v2f64 VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
- // Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(538)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- SDValue CPInChain;
- SDValue Chain2;
- if (SelectScalarSSELoad(N, SDValue(N, 0), N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
- SDNode *Result = Emit_135(N, X86::MULSDrm_Int, MVT::v2f64, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v2f64 539:iPTR, VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
+ // Emits: (MULSDrm_Int:v2f64 VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
+ // Pattern complexity = 26 cost = 1 size = 3
+ if (CN1 == INT64_C(539)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ SDValue CPInChain;
+ SDValue Chain2;
+ if (SelectScalarSSELoad(N, SDValue(N, 0), N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
+ SDNode *Result = Emit_135(N, X86::MULSDrm_Int, MVT::v2f64, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
+ return Result;
}
+ }
- // Pattern: (intrinsic_wo_chain:v2f64 593:iPTR, VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
- // Emits: (SUBSDrm_Int:v2f64 VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
- // Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(593)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- SDValue CPInChain;
- SDValue Chain2;
- if (SelectScalarSSELoad(N, SDValue(N, 0), N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
- SDNode *Result = Emit_135(N, X86::SUBSDrm_Int, MVT::v2f64, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v2f64 594:iPTR, VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
+ // Emits: (SUBSDrm_Int:v2f64 VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
+ // Pattern complexity = 26 cost = 1 size = 3
+ if (CN1 == INT64_C(594)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ SDValue CPInChain;
+ SDValue Chain2;
+ if (SelectScalarSSELoad(N, SDValue(N, 0), N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
+ SDNode *Result = Emit_135(N, X86::SUBSDrm_Int, MVT::v2f64, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
+ return Result;
}
+ }
- // Pattern: (intrinsic_wo_chain:v2f64 524:iPTR, VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
- // Emits: (DIVSDrm_Int:v2f64 VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
- // Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(524)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- SDValue CPInChain;
- SDValue Chain2;
- if (SelectScalarSSELoad(N, SDValue(N, 0), N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
- SDNode *Result = Emit_135(N, X86::DIVSDrm_Int, MVT::v2f64, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v2f64 525:iPTR, VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
+ // Emits: (DIVSDrm_Int:v2f64 VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
+ // Pattern complexity = 26 cost = 1 size = 3
+ if (CN1 == INT64_C(525)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ SDValue CPInChain;
+ SDValue Chain2;
+ if (SelectScalarSSELoad(N, SDValue(N, 0), N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
+ SDNode *Result = Emit_135(N, X86::DIVSDrm_Int, MVT::v2f64, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
+ return Result;
}
+ }
- // Pattern: (intrinsic_wo_chain:v2f64 530:iPTR, VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
- // Emits: (MAXSDrm_Int:v2f64 VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
- // Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(530)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- SDValue CPInChain;
- SDValue Chain2;
- if (SelectScalarSSELoad(N, SDValue(N, 0), N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
- SDNode *Result = Emit_135(N, X86::MAXSDrm_Int, MVT::v2f64, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v2f64 531:iPTR, VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
+ // Emits: (MAXSDrm_Int:v2f64 VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
+ // Pattern complexity = 26 cost = 1 size = 3
+ if (CN1 == INT64_C(531)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ SDValue CPInChain;
+ SDValue Chain2;
+ if (SelectScalarSSELoad(N, SDValue(N, 0), N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
+ SDNode *Result = Emit_135(N, X86::MAXSDrm_Int, MVT::v2f64, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
+ return Result;
}
+ }
- // Pattern: (intrinsic_wo_chain:v2f64 533:iPTR, VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
- // Emits: (MINSDrm_Int:v2f64 VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
- // Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(533)) {
- SDValue N1 = N->getOperand(1);
- SDValue N2 = N->getOperand(2);
- SDValue CPTmpN2_0;
- SDValue CPTmpN2_1;
- SDValue CPTmpN2_2;
- SDValue CPTmpN2_3;
- SDValue CPTmpN2_4;
- SDValue CPInChain;
- SDValue Chain2;
- if (SelectScalarSSELoad(N, SDValue(N, 0), N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
- SDNode *Result = Emit_135(N, X86::MINSDrm_Int, MVT::v2f64, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v2f64 534:iPTR, VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
+ // Emits: (MINSDrm_Int:v2f64 VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
+ // Pattern complexity = 26 cost = 1 size = 3
+ if (CN1 == INT64_C(534)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue CPTmpN2_0;
+ SDValue CPTmpN2_1;
+ SDValue CPTmpN2_2;
+ SDValue CPTmpN2_3;
+ SDValue CPTmpN2_4;
+ SDValue CPInChain;
+ SDValue Chain2;
+ if (SelectScalarSSELoad(N, SDValue(N, 0), N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
+ SDNode *Result = Emit_135(N, X86::MINSDrm_Int, MVT::v2f64, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
+ return Result;
}
+ }
- // Pattern: (intrinsic_wo_chain:v2f64 589:iPTR, sse_load_f64:v2f64:$src)
- // Emits: (SQRTSDm_Int:v2f64 sse_load_f64:v2f64:$src)
- // Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(589)) {
- SDValue N1 = N->getOperand(1);
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- SDValue CPTmpN1_3;
- SDValue CPTmpN1_4;
- SDValue CPInChain;
- SDValue Chain1;
- if (SelectScalarSSELoad(N, SDValue(N, 0), N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, CPInChain, Chain1)) {
- SDNode *Result = Emit_136(N, X86::SQRTSDm_Int, MVT::v2f64, CPInChain, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain1);
- return Result;
- }
+ // Pattern: (intrinsic_wo_chain:v2f64 590:iPTR, sse_load_f64:v2f64:$src)
+ // Emits: (SQRTSDm_Int:v2f64 sse_load_f64:v2f64:$src)
+ // Pattern complexity = 26 cost = 1 size = 3
+ if (CN1 == INT64_C(590)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ SDValue CPTmpN1_3;
+ SDValue CPTmpN1_4;
+ SDValue CPInChain;
+ SDValue Chain1;
+ if (SelectScalarSSELoad(N, SDValue(N, 0), N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, CPInChain, Chain1)) {
+ SDNode *Result = Emit_136(N, X86::SQRTSDm_Int, MVT::v2f64, CPInChain, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain1);
+ return Result;
}
}
- }
- }
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v2f64 501:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src, (imm:i8):$cc)
+ // Pattern: (intrinsic_wo_chain:v2f64 502:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src, (imm:i8):$cc)
// Emits: (Int_CMPSDrr:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src, (imm:i8):$cc)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(501)) {
+ if (CN1 == INT64_C(502)) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
SDValue N3 = N->getOperand(3);
@@ -24444,10 +24295,10 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(SDNode *N) {
}
}
- // Pattern: (intrinsic_wo_chain:v2f64 500:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src, (imm:i8):$cc)
+ // Pattern: (intrinsic_wo_chain:v2f64 501:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src, (imm:i8):$cc)
// Emits: (CMPPDrri:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src, (imm:i8):$cc)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(500)) {
+ if (CN1 == INT64_C(501)) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
SDValue N3 = N->getOperand(3);
@@ -24464,10 +24315,10 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(SDNode *N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v2f64 652:iPTR, VR128:v2f64:$src1, (imm:i32):$src2)
+ // Pattern: (intrinsic_wo_chain:v2f64 653:iPTR, VR128:v2f64:$src1, (imm:i32):$src2)
// Emits: (ROUNDPDr_Int:v2f64 VR128:v2f64:$src1, (imm:i32):$src2)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(652)) {
+ if (CN1 == INT64_C(653)) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
if (N2.getNode()->getOpcode() == ISD::Constant) {
@@ -24476,10 +24327,10 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(SDNode *N) {
}
}
- // Pattern: (intrinsic_wo_chain:v2f64 654:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2, (imm:i32):$src3)
+ // Pattern: (intrinsic_wo_chain:v2f64 655:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2, (imm:i32):$src3)
// Emits: (ROUNDSDr_Int:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2, (imm:i32):$src3)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(654)) {
+ if (CN1 == INT64_C(655)) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
SDValue N3 = N->getOperand(3);
@@ -24489,10 +24340,10 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(SDNode *N) {
}
}
- // Pattern: (intrinsic_wo_chain:v2f64 609:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2, (imm:i32):$src3)
+ // Pattern: (intrinsic_wo_chain:v2f64 610:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2, (imm:i32):$src3)
// Emits: (BLENDPDrri:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2, (imm:i32):$src3)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(609)) {
+ if (CN1 == INT64_C(610)) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
SDValue N3 = N->getOperand(3);
@@ -24502,10 +24353,10 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(SDNode *N) {
}
}
- // Pattern: (intrinsic_wo_chain:v2f64 613:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2, (imm:i32):$src3)
+ // Pattern: (intrinsic_wo_chain:v2f64 614:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2, (imm:i32):$src3)
// Emits: (DPPDrri:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2, (imm:i32):$src3)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(613)) {
+ if (CN1 == INT64_C(614)) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
SDValue N3 = N->getOperand(3);
@@ -24522,130 +24373,130 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(SDNode *N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v2f64 518:iPTR, VR128:v2f64:$src1, GR64:i64:$src2)
+ // Pattern: (intrinsic_wo_chain:v2f64 519:iPTR, VR128:v2f64:$src1, GR64:i64:$src2)
// Emits: (Int_CVTSI2SD64rr:v2f64 VR128:v2f64:$src1, GR64:i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(518)) {
+ if (CN1 == INT64_C(519)) {
SDNode *Result = Emit_110(N, X86::Int_CVTSI2SD64rr, MVT::v2f64);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2f64 685:iPTR, VR64:v2i32:$src)
+ // Pattern: (intrinsic_wo_chain:v2f64 686:iPTR, VR64:v2i32:$src)
// Emits: (Int_CVTPI2PDrr:v2f64 VR64:v2i32:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(685)) {
+ if (CN1 == INT64_C(686)) {
SDNode *Result = Emit_107(N, X86::Int_CVTPI2PDrr, MVT::v2f64);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2f64 498:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Pattern: (intrinsic_wo_chain:v2f64 499:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
// Emits: (ADDSDrr_Int:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(498)) {
+ if (CN1 == INT64_C(499)) {
SDNode *Result = Emit_110(N, X86::ADDSDrr_Int, MVT::v2f64);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2f64 538:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Pattern: (intrinsic_wo_chain:v2f64 539:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
// Emits: (MULSDrr_Int:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(538)) {
+ if (CN1 == INT64_C(539)) {
SDNode *Result = Emit_110(N, X86::MULSDrr_Int, MVT::v2f64);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2f64 593:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Pattern: (intrinsic_wo_chain:v2f64 594:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
// Emits: (SUBSDrr_Int:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(593)) {
+ if (CN1 == INT64_C(594)) {
SDNode *Result = Emit_110(N, X86::SUBSDrr_Int, MVT::v2f64);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2f64 524:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Pattern: (intrinsic_wo_chain:v2f64 525:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
// Emits: (DIVSDrr_Int:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(524)) {
+ if (CN1 == INT64_C(525)) {
SDNode *Result = Emit_110(N, X86::DIVSDrr_Int, MVT::v2f64);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2f64 530:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Pattern: (intrinsic_wo_chain:v2f64 531:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
// Emits: (MAXSDrr_Int:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(530)) {
+ if (CN1 == INT64_C(531)) {
SDNode *Result = Emit_110(N, X86::MAXSDrr_Int, MVT::v2f64);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2f64 529:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Pattern: (intrinsic_wo_chain:v2f64 530:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
// Emits: (MAXPDrr_Int:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(529)) {
+ if (CN1 == INT64_C(530)) {
SDNode *Result = Emit_110(N, X86::MAXPDrr_Int, MVT::v2f64);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2f64 533:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Pattern: (intrinsic_wo_chain:v2f64 534:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
// Emits: (MINSDrr_Int:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(533)) {
+ if (CN1 == INT64_C(534)) {
SDNode *Result = Emit_110(N, X86::MINSDrr_Int, MVT::v2f64);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2f64 532:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Pattern: (intrinsic_wo_chain:v2f64 533:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
// Emits: (MINPDrr_Int:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(532)) {
+ if (CN1 == INT64_C(533)) {
SDNode *Result = Emit_110(N, X86::MINPDrr_Int, MVT::v2f64);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2f64 508:iPTR, VR128:v4i32:$src)
+ // Pattern: (intrinsic_wo_chain:v2f64 509:iPTR, VR128:v4i32:$src)
// Emits: (Int_CVTDQ2PDrr:v2f64 VR128:v4i32:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(508)) {
+ if (CN1 == INT64_C(509)) {
SDNode *Result = Emit_107(N, X86::Int_CVTDQ2PDrr, MVT::v2f64);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2f64 513:iPTR, VR128:v4f32:$src)
+ // Pattern: (intrinsic_wo_chain:v2f64 514:iPTR, VR128:v4f32:$src)
// Emits: (Int_CVTPS2PDrr:v2f64 VR128:v4f32:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(513)) {
+ if (CN1 == INT64_C(514)) {
SDNode *Result = Emit_107(N, X86::Int_CVTPS2PDrr, MVT::v2f64);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2f64 517:iPTR, VR128:v2f64:$src1, GR32:i32:$src2)
+ // Pattern: (intrinsic_wo_chain:v2f64 518:iPTR, VR128:v2f64:$src1, GR32:i32:$src2)
// Emits: (Int_CVTSI2SDrr:v2f64 VR128:v2f64:$src1, GR32:i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(517)) {
+ if (CN1 == INT64_C(518)) {
SDNode *Result = Emit_110(N, X86::Int_CVTSI2SDrr, MVT::v2f64);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2f64 519:iPTR, VR128:v2f64:$src1, VR128:v4f32:$src2)
+ // Pattern: (intrinsic_wo_chain:v2f64 520:iPTR, VR128:v2f64:$src1, VR128:v4f32:$src2)
// Emits: (Int_CVTSS2SDrr:v2f64 VR128:v2f64:$src1, VR128:v4f32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(519)) {
+ if (CN1 == INT64_C(520)) {
SDNode *Result = Emit_110(N, X86::Int_CVTSS2SDrr, MVT::v2f64);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2f64 589:iPTR, VR128:v2f64:$src)
+ // Pattern: (intrinsic_wo_chain:v2f64 590:iPTR, VR128:v2f64:$src)
// Emits: (SQRTSDr_Int:v2f64 VR128:v2f64:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(589)) {
+ if (CN1 == INT64_C(590)) {
SDNode *Result = Emit_107(N, X86::SQRTSDr_Int, MVT::v2f64);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2f64 588:iPTR, VR128:v2f64:$src)
+ // Pattern: (intrinsic_wo_chain:v2f64 589:iPTR, VR128:v2f64:$src)
// Emits: (SQRTPDr_Int:v2f64 VR128:v2f64:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(588)) {
+ if (CN1 == INT64_C(589)) {
SDNode *Result = Emit_107(N, X86::SQRTPDr_Int, MVT::v2f64);
return Result;
}
@@ -24657,33 +24508,33 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(SDNode *N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v2f64 600:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Pattern: (intrinsic_wo_chain:v2f64 601:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
// Emits: (ADDSUBPDrr:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(600)) {
+ if (CN1 == INT64_C(601)) {
SDNode *Result = Emit_110(N, X86::ADDSUBPDrr, MVT::v2f64);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2f64 602:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Pattern: (intrinsic_wo_chain:v2f64 603:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
// Emits: (HADDPDrr:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(602)) {
+ if (CN1 == INT64_C(603)) {
SDNode *Result = Emit_110(N, X86::HADDPDrr, MVT::v2f64);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2f64 604:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Pattern: (intrinsic_wo_chain:v2f64 605:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
// Emits: (HSUBPDrr:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(604)) {
+ if (CN1 == INT64_C(605)) {
SDNode *Result = Emit_110(N, X86::HSUBPDrr, MVT::v2f64);
return Result;
}
}
}
- // Pattern: (intrinsic_wo_chain:v2f64 611:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2, XMM0:v2f64)
+ // Pattern: (intrinsic_wo_chain:v2f64 612:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2, XMM0:v2f64)
// Emits: (BLENDVPDrr0:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if ((Subtarget->hasSSE41())) {
@@ -24691,7 +24542,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(SDNode *N) {
ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(611)) {
+ if (CN1 == INT64_C(612)) {
SDNode *Result = Emit_120(N, X86::BLENDVPDrr0, MVT::v2f64);
return Result;
}
@@ -24711,7 +24562,7 @@ DISABLE_INLINE SDNode *Emit_139(SDNode *N, unsigned Opc0, MVT::SimpleValueType V
}
SDNode *Select_ISD_INTRINSIC_W_CHAIN_v16i8(SDNode *N) {
- // Pattern: (intrinsic_w_chain:v16i8 526:iPTR, addr:iPTR:$src)
+ // Pattern: (intrinsic_w_chain:v16i8 527:iPTR, addr:iPTR:$src)
// Emits: (MOVDQUrm_Int:v16i8 addr:iPTR:$src)
// Pattern complexity = 26 cost = 1 size = 3
if ((Subtarget->hasSSE2())) {
@@ -24720,7 +24571,7 @@ SDNode *Select_ISD_INTRINSIC_W_CHAIN_v16i8(SDNode *N) {
ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(526)) {
+ if (CN1 == INT64_C(527)) {
SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
@@ -24735,7 +24586,7 @@ SDNode *Select_ISD_INTRINSIC_W_CHAIN_v16i8(SDNode *N) {
}
}
- // Pattern: (intrinsic_w_chain:v16i8 606:iPTR, addr:iPTR:$src)
+ // Pattern: (intrinsic_w_chain:v16i8 607:iPTR, addr:iPTR:$src)
// Emits: (LDDQUrm:v16i8 addr:iPTR:$src)
// Pattern complexity = 26 cost = 1 size = 3
if ((Subtarget->hasSSE3())) {
@@ -24744,7 +24595,7 @@ SDNode *Select_ISD_INTRINSIC_W_CHAIN_v16i8(SDNode *N) {
ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(606)) {
+ if (CN1 == INT64_C(607)) {
SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
@@ -24770,7 +24621,7 @@ SDNode *Select_ISD_INTRINSIC_W_CHAIN_v2i64(SDNode *N) {
ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(617)) {
+ if (CN1 == INT64_C(618)) {
SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
@@ -24796,7 +24647,7 @@ SDNode *Select_ISD_INTRINSIC_W_CHAIN_v4f32(SDNode *N) {
ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(698)) {
+ if (CN1 == INT64_C(699)) {
SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
@@ -24822,7 +24673,7 @@ SDNode *Select_ISD_INTRINSIC_W_CHAIN_v2f64(SDNode *N) {
ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(527)) {
+ if (CN1 == INT64_C(528)) {
SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
@@ -25560,7 +25411,7 @@ SDNode *Select_ISD_LOAD_i64(SDNode *N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_141(N, X86::MOV32rm, TargetInstrInfo::SUBREG_TO_REG, MVT::i32, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_141(N, X86::MOV32rm, TargetOpcode::SUBREG_TO_REG, MVT::i32, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -26191,7 +26042,7 @@ SDNode *Select_ISD_MUL_i8(SDNode *N) {
// Pattern: (mul:i8 AL:i8, (ld:i8 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>)
// Emits: (MUL8m:isVoid addr:iPTR:$src)
// Pattern complexity = 25 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::LOAD &&
@@ -26237,7 +26088,7 @@ DISABLE_INLINE SDNode *Emit_146(SDNode *N, unsigned Opc0, MVT::SimpleValueType V
return ResNode;
}
SDNode *Select_ISD_MUL_i16(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
@@ -26319,9 +26170,6 @@ SDNode *Select_ISD_MUL_i16(SDNode *N) {
}
}
}
- }
- {
- SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::Constant) {
@@ -26363,7 +26211,7 @@ DISABLE_INLINE SDNode *Emit_147(SDNode *N, unsigned Opc0, MVT::SimpleValueType V
return ResNode;
}
SDNode *Select_ISD_MUL_i32(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
@@ -26517,7 +26365,7 @@ DISABLE_INLINE SDNode *Emit_148(SDNode *N, unsigned Opc0, MVT::SimpleValueType V
return ResNode;
}
SDNode *Select_ISD_MUL_i64(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
@@ -26647,8 +26495,7 @@ SDNode *Select_ISD_MUL_i64(SDNode *N) {
}
SDNode *Select_ISD_MUL_v16i8(SDNode *N) {
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSE41())) {
+ if ((Subtarget->hasSSE41())) {
SDValue N0 = N->getOperand(0);
// Pattern: (mul:v16i8 VR128:v16i8:$src1, (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
@@ -26706,74 +26553,73 @@ SDNode *Select_ISD_MUL_v16i8(SDNode *N) {
}
SDNode *Select_ISD_MUL_v4i16(SDNode *N) {
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasMMX())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (mul:v4i16 VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PMULLWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
+ if ((Subtarget->hasMMX())) {
{
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_16(N, X86::MMX_PMULLWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
+ SDValue N0 = N->getOperand(0);
+
+ // Pattern: (mul:v4i16 VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PMULLWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_16(N, X86::MMX_PMULLWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
}
}
}
}
- }
- // Pattern: (mul:v4i16 (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v4i16:$src1)
- // Emits: (MMX_PMULLWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N0.hasOneUse()) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::LOAD &&
- N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
- SDValue Chain00 = N00.getNode()->getOperand(0);
- if (Predicate_unindexedload(N00.getNode()) &&
- Predicate_load(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N1 = N->getOperand(1);
- if (N00.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_17(N, X86::MMX_PMULLWrm, MVT::v4i16, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
+ // Pattern: (mul:v4i16 (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v4i16:$src1)
+ // Emits: (MMX_PMULLWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N0.hasOneUse()) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::LOAD &&
+ N00.hasOneUse() &&
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
+ SDValue Chain00 = N00.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N00.getNode()) &&
+ Predicate_load(N00.getNode())) {
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
+ SDValue N1 = N->getOperand(1);
+ if (N00.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_17(N, X86::MMX_PMULLWrm, MVT::v4i16, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
+ }
}
}
}
}
}
- }
- // Pattern: (mul:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
- // Emits: (MMX_PMULLWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasMMX())) {
+ // Pattern: (mul:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Emits: (MMX_PMULLWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
SDNode *Result = Emit_15(N, X86::MMX_PMULLWrr, MVT::v4i16);
return Result;
}
@@ -26783,76 +26629,75 @@ SDNode *Select_ISD_MUL_v4i16(SDNode *N) {
}
SDNode *Select_ISD_MUL_v8i16(SDNode *N) {
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (mul:v8i16 VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PMULLWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
{
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_16(N, X86::PMULLWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
+ SDValue N0 = N->getOperand(0);
+
+ // Pattern: (mul:v8i16 VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PMULLWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_16(N, X86::PMULLWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
}
}
}
}
- }
- // Pattern: (mul:v8i16 (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
- // Emits: (PMULLWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N0.hasOneUse()) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::LOAD &&
- N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
- SDValue Chain00 = N00.getNode()->getOperand(0);
- if (Predicate_unindexedload(N00.getNode()) &&
- Predicate_load(N00.getNode()) &&
- Predicate_memop(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N1 = N->getOperand(1);
- if (N00.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_17(N, X86::PMULLWrm, MVT::v8i16, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
+ // Pattern: (mul:v8i16 (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
+ // Emits: (PMULLWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N0.hasOneUse()) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::LOAD &&
+ N00.hasOneUse() &&
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
+ SDValue Chain00 = N00.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N00.getNode()) &&
+ Predicate_load(N00.getNode()) &&
+ Predicate_memop(N00.getNode())) {
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
+ SDValue N1 = N->getOperand(1);
+ if (N00.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_17(N, X86::PMULLWrm, MVT::v8i16, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
+ }
}
}
}
}
}
- }
- // Pattern: (mul:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Emits: (PMULLWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
+ // Pattern: (mul:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Emits: (PMULLWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
SDNode *Result = Emit_15(N, X86::PMULLWrr, MVT::v8i16);
return Result;
}
@@ -26872,7 +26717,7 @@ SDNode *Select_ISD_MUL_v4i32(SDNode *N) {
}
SDNode *Select_ISD_OR_i8(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
// Pattern: (or:i8 GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
@@ -26921,13 +26766,10 @@ SDNode *Select_ISD_OR_i8(SDNode *N) {
}
}
}
- }
- // Pattern: (or:i8 GR8:i8:$src1, (imm:i8):$src2)
- // Emits: (OR8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- {
- SDValue N0 = N->getOperand(0);
+ // Pattern: (or:i8 GR8:i8:$src1, (imm:i8):$src2)
+ // Emits: (OR8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_3(N, X86::OR8ri, MVT::i8);
@@ -27031,7 +26873,7 @@ DISABLE_INLINE SDNode *Emit_154(SDNode *N, unsigned Opc0, MVT::SimpleValueType V
return CurDAG->SelectNodeTo(N, Opc0, VT0, N10, N00, Tmp2);
}
SDNode *Select_ISD_OR_i16(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
// Pattern: (or:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
@@ -27080,9 +26922,6 @@ SDNode *Select_ISD_OR_i16(SDNode *N) {
}
}
}
- }
- {
- SDValue N0 = N->getOperand(0);
// Pattern: (or:i16 (srl:i16 GR16:i16:$src1, (trunc:i8 CX:i16:$amt)), (shl:i16 GR16:i16:$src2, (trunc:i8 (sub:i16 16:i16, CX:i16:$amt))))
// Emits: (SHRD16rrCL:i16 GR16:i16:$src1, GR16:i16:$src2)
@@ -27526,7 +27365,7 @@ DISABLE_INLINE SDNode *Emit_156(SDNode *N, unsigned Opc0, MVT::SimpleValueType V
return CurDAG->SelectNodeTo(N, Opc0, VT0, N10, N00, InFlag);
}
SDNode *Select_ISD_OR_i32(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
// Pattern: (or:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
@@ -27575,9 +27414,6 @@ SDNode *Select_ISD_OR_i32(SDNode *N) {
}
}
}
- }
- {
- SDValue N0 = N->getOperand(0);
// Pattern: (or:i32 (srl:i32 GR32:i32:$src1, (trunc:i8 ECX:i32:$amt)), (shl:i32 GR32:i32:$src2, (trunc:i8 (sub:i32 32:i32, ECX:i32:$amt))))
// Emits: (SHRD32rrCL:i32 GR32:i32:$src1, GR32:i32:$src2)
@@ -28013,7 +27849,7 @@ SDNode *Select_ISD_OR_i32(SDNode *N) {
}
SDNode *Select_ISD_OR_i64(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
// Pattern: (or:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
@@ -28234,44 +28070,145 @@ SDNode *Select_ISD_OR_i64(SDNode *N) {
}
SDNode *Select_ISD_OR_v1i64(SDNode *N) {
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasMMX())) {
+ if ((Subtarget->hasMMX())) {
+ {
+ SDValue N0 = N->getOperand(0);
+
+ // Pattern: (or:v1i64 VR64:v1i64:$src1, (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (MMX_PORrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::MMX_PORrm, MVT::v1i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, VR64:v1i64:$src1)
+ // Emits: (MMX_PORrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_19(N, X86::MMX_PORrm, MVT::v1i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (or:v1i64 VR64:v1i64:$src1, VR64:v1i64:$src2)
+ // Emits: (MMX_PORrr:v1i64 VR64:v1i64:$src1, VR64:v1i64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_15(N, X86::MMX_PORrr, MVT::v1i64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_OR_v2i64(SDNode *N) {
+
+ // Pattern: (or:v2i64 (bitconvert:v2i64 VR128:v4f32:$src1), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (ORPSrm:v2i64 VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
+ N00.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_57(N, X86::ORPSrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
- // Pattern: (or:v1i64 VR64:v1i64:$src1, (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (MMX_PORrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
+ // Pattern: (or:v2i64 (bitconvert:v2i64 VR128:v2f64:$src1), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (ORPDrm:v2i64 VR128:v2f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N00 = N0.getNode()->getOperand(0);
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::MMX_PORrm, MVT::v1i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
+ N00.getValueType() == MVT::v2f64) {
+ SDNode *Result = Emit_57(N, X86::ORPDrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
}
}
+ }
- // Pattern: (or:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, VR64:v1i64:$src1)
- // Emits: (MMX_PORrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
+ // Pattern: (or:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (bitconvert:v2i64 VR128:v4f32:$src1))
+ // Emits: (ORPSrm:v2i64 VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDValue N0 = N->getOperand(0);
if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode())) {
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
@@ -28279,83 +28216,43 @@ SDNode *Select_ISD_OR_v1i64(SDNode *N) {
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_19(N, X86::MMX_PORrm, MVT::v1i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (or:v1i64 VR64:v1i64:$src1, VR64:v1i64:$src2)
- // Emits: (MMX_PORrr:v1i64 VR64:v1i64:$src1, VR64:v1i64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasMMX())) {
- SDNode *Result = Emit_15(N, X86::MMX_PORrr, MVT::v1i64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_OR_v2i64(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
-
- // Pattern: (or:v2i64 (bitconvert:v2i64 VR128:v4f32:$src1), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (ORPSrm:v2i64 VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
- N00.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_57(N, X86::ORPSrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_62(N, X86::ORPSrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
}
}
}
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N->getOperand(0);
- // Pattern: (or:v2i64 (bitconvert:v2i64 VR128:v2f64:$src1), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Pattern: (or:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (bitconvert:v2i64 VR128:v2f64:$src1))
// Emits: (ORPDrm:v2i64 VR128:v2f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 28 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
- N00.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_57(N, X86::ORPDrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getValueType() == MVT::v2f64) {
+ SDNode *Result = Emit_62(N, X86::ORPDrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -28363,125 +28260,58 @@ SDNode *Select_ISD_OR_v2i64(SDNode *N) {
}
}
- // Pattern: (or:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (bitconvert:v2i64 VR128:v4f32:$src1))
- // Emits: (ORPSrm:v2i64 VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_62(N, X86::ORPSrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
+ // Pattern: (or:v2i64 VR128:v2i64:$src1, (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (PORrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::PORrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
}
}
}
}
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- // Pattern: (or:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (bitconvert:v2i64 VR128:v2f64:$src1))
- // Emits: (ORPDrm:v2i64 VR128:v2f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_62(N, X86::ORPDrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (or:v2i64 VR128:v2i64:$src1, (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (PORrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::PORrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (or:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, VR128:v2i64:$src1)
- // Emits: (PORrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_19(N, X86::PORrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
+ // Pattern: (or:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, VR128:v2i64:$src1)
+ // Emits: (PORrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_19(N, X86::PORrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
}
}
}
- }
- // Pattern: (or:v2i64 (bitconvert:v2i64 VR128:v2f64:$src1), (bitconvert:v2i64 VR128:v2f64:$src2))
- // Emits: (ORPDrr:v2i64 VR128:v2f64:$src1, VR128:v2f64:$src2)
- // Pattern complexity = 9 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
+ // Pattern: (or:v2i64 (bitconvert:v2i64 VR128:v2f64:$src1), (bitconvert:v2i64 VR128:v2f64:$src2))
+ // Emits: (ORPDrr:v2i64 VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Pattern complexity = 9 cost = 1 size = 3
if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT) {
SDValue N00 = N0.getNode()->getOperand(0);
SDValue N1 = N->getOperand(1);
@@ -28922,13 +28752,12 @@ SDNode *Select_ISD_ROTR_i64(SDNode *N) {
}
SDNode *Select_ISD_SCALAR_TO_VECTOR_v2i32(SDNode *N) {
-
- // Pattern: (scalar_to_vector:v2i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
- // Emits: (MMX_MOVD64rm:v2i32 addr:iPTR:$src)
- // Pattern complexity = 25 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasMMX())) {
+ if ((Subtarget->hasMMX())) {
SDValue N0 = N->getOperand(0);
+
+ // Pattern: (scalar_to_vector:v2i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
+ // Emits: (MMX_MOVD64rm:v2i32 addr:iPTR:$src)
+ // Pattern complexity = 25 cost = 1 size = 3
if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse()) {
SDValue Chain0 = N0.getNode()->getOperand(0);
@@ -28947,13 +28776,10 @@ SDNode *Select_ISD_SCALAR_TO_VECTOR_v2i32(SDNode *N) {
}
}
}
- }
- // Pattern: (scalar_to_vector:v2i32 GR32:i32:$src)
- // Emits: (MMX_MOVD64rr:v2i32 GR32:i32:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasMMX())) {
- SDValue N0 = N->getOperand(0);
+ // Pattern: (scalar_to_vector:v2i32 GR32:i32:$src)
+ // Emits: (MMX_MOVD64rr:v2i32 GR32:i32:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
if (N0.getValueType() == MVT::i32) {
SDNode *Result = Emit_72(N, X86::MMX_MOVD64rr, MVT::v2i32);
return Result;
@@ -28965,13 +28791,12 @@ SDNode *Select_ISD_SCALAR_TO_VECTOR_v2i32(SDNode *N) {
}
SDNode *Select_ISD_SCALAR_TO_VECTOR_v4i32(SDNode *N) {
-
- // Pattern: (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
- // Emits: (MOVDI2PDIrm:v4i32 addr:iPTR:$src)
- // Pattern complexity = 25 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSE2())) {
+ if ((Subtarget->hasSSE2())) {
SDValue N0 = N->getOperand(0);
+
+ // Pattern: (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
+ // Emits: (MOVDI2PDIrm:v4i32 addr:iPTR:$src)
+ // Pattern complexity = 25 cost = 1 size = 3
if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse()) {
SDValue Chain0 = N0.getNode()->getOperand(0);
@@ -28990,13 +28815,10 @@ SDNode *Select_ISD_SCALAR_TO_VECTOR_v4i32(SDNode *N) {
}
}
}
- }
- // Pattern: (scalar_to_vector:v4i32 GR32:i32:$src)
- // Emits: (MOVDI2PDIrr:v4i32 GR32:i32:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
+ // Pattern: (scalar_to_vector:v4i32 GR32:i32:$src)
+ // Emits: (MOVDI2PDIrr:v4i32 GR32:i32:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
if (N0.getValueType() == MVT::i32) {
SDNode *Result = Emit_72(N, X86::MOVDI2PDIrr, MVT::v4i32);
return Result;
@@ -29030,8 +28852,7 @@ SDNode *Select_ISD_SCALAR_TO_VECTOR_v2i64(SDNode *N) {
// Pattern: (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
// Emits: (MOVQI2PQIrm:v2i64 addr:iPTR:$src)
// Pattern complexity = 25 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSE2())) {
+ if ((Subtarget->hasSSE2())) {
SDValue N0 = N->getOperand(0);
if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse()) {
@@ -29110,13 +28931,12 @@ SDNode *Select_ISD_SCALAR_TO_VECTOR_v2i64(SDNode *N) {
}
SDNode *Select_ISD_SCALAR_TO_VECTOR_v4f32(SDNode *N) {
-
- // Pattern: (scalar_to_vector:v4f32 (ld:f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>)
- // Emits: (MOVSS2PSrm:v4f32 addr:iPTR:$src)
- // Pattern complexity = 25 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSE1())) {
+ if ((Subtarget->hasSSE1())) {
SDValue N0 = N->getOperand(0);
+
+ // Pattern: (scalar_to_vector:v4f32 (ld:f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>)
+ // Emits: (MOVSS2PSrm:v4f32 addr:iPTR:$src)
+ // Pattern complexity = 25 cost = 1 size = 3
if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse()) {
SDValue Chain0 = N0.getNode()->getOperand(0);
@@ -29136,13 +28956,10 @@ SDNode *Select_ISD_SCALAR_TO_VECTOR_v4f32(SDNode *N) {
}
}
}
- }
- // Pattern: (scalar_to_vector:v4f32 FR32:f32:$src)
- // Emits: (MOVSS2PSrr:v4f32 FR32:f32:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
+ // Pattern: (scalar_to_vector:v4f32 FR32:f32:$src)
+ // Emits: (MOVSS2PSrr:v4f32 FR32:f32:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
if (N0.getValueType() == MVT::f32) {
SDNode *Result = Emit_72(N, X86::MOVSS2PSrr, MVT::v4f32);
return Result;
@@ -29154,13 +28971,12 @@ SDNode *Select_ISD_SCALAR_TO_VECTOR_v4f32(SDNode *N) {
}
SDNode *Select_ISD_SCALAR_TO_VECTOR_v2f64(SDNode *N) {
-
- // Pattern: (scalar_to_vector:v2f64 (ld:f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>)
- // Emits: (MOVSD2PDrm:v2f64 addr:iPTR:$src)
- // Pattern complexity = 25 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSE2())) {
+ if ((Subtarget->hasSSE2())) {
SDValue N0 = N->getOperand(0);
+
+ // Pattern: (scalar_to_vector:v2f64 (ld:f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>)
+ // Emits: (MOVSD2PDrm:v2f64 addr:iPTR:$src)
+ // Pattern complexity = 25 cost = 1 size = 3
if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse()) {
SDValue Chain0 = N0.getNode()->getOperand(0);
@@ -29180,13 +28996,10 @@ SDNode *Select_ISD_SCALAR_TO_VECTOR_v2f64(SDNode *N) {
}
}
}
- }
- // Pattern: (scalar_to_vector:v2f64 FR64:f64:$src)
- // Emits: (MOVSD2PDrr:v2f64 FR64:f64:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
+ // Pattern: (scalar_to_vector:v2f64 FR64:f64:$src)
+ // Emits: (MOVSD2PDrr:v2f64 FR64:f64:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
if (N0.getValueType() == MVT::f64) {
SDNode *Result = Emit_72(N, X86::MOVSD2PDrr, MVT::v2f64);
return Result;
@@ -29566,7 +29379,7 @@ SDNode *Select_ISD_SIGN_EXTEND_INREG_i16(SDNode *N) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i8) {
- SDNode *Result = Emit_164(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVSX16rr8, MVT::i8, MVT::i16);
+ SDNode *Result = Emit_164(N, TargetOpcode::EXTRACT_SUBREG, X86::MOVSX16rr8, MVT::i8, MVT::i16);
return Result;
}
}
@@ -29578,7 +29391,7 @@ SDNode *Select_ISD_SIGN_EXTEND_INREG_i16(SDNode *N) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i8) {
- SDNode *Result = Emit_163(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVSX16rr8, MVT::i16, MVT::i8, MVT::i16);
+ SDNode *Result = Emit_163(N, TargetOpcode::COPY_TO_REGCLASS, TargetOpcode::EXTRACT_SUBREG, X86::MOVSX16rr8, MVT::i16, MVT::i8, MVT::i16);
return Result;
}
}
@@ -29612,7 +29425,7 @@ SDNode *Select_ISD_SIGN_EXTEND_INREG_i32(SDNode *N) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i16) {
- SDNode *Result = Emit_165(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVSX32rr16, MVT::i16, MVT::i32);
+ SDNode *Result = Emit_165(N, TargetOpcode::EXTRACT_SUBREG, X86::MOVSX32rr16, MVT::i16, MVT::i32);
return Result;
}
}
@@ -29624,7 +29437,7 @@ SDNode *Select_ISD_SIGN_EXTEND_INREG_i32(SDNode *N) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i8) {
- SDNode *Result = Emit_164(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVSX32rr8, MVT::i8, MVT::i32);
+ SDNode *Result = Emit_164(N, TargetOpcode::EXTRACT_SUBREG, X86::MOVSX32rr8, MVT::i8, MVT::i32);
return Result;
}
}
@@ -29636,7 +29449,7 @@ SDNode *Select_ISD_SIGN_EXTEND_INREG_i32(SDNode *N) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i8) {
- SDNode *Result = Emit_166(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVSX32rr8, MVT::i32, MVT::i8, MVT::i32);
+ SDNode *Result = Emit_166(N, TargetOpcode::COPY_TO_REGCLASS, TargetOpcode::EXTRACT_SUBREG, X86::MOVSX32rr8, MVT::i32, MVT::i8, MVT::i32);
return Result;
}
}
@@ -29660,7 +29473,7 @@ SDNode *Select_ISD_SIGN_EXTEND_INREG_i64(SDNode *N) {
// Emits: (MOVSX64rr32:i64 (EXTRACT_SUBREG:i32 GR64:i64:$src, 4:i32))
// Pattern complexity = 3 cost = 2 size = 3
if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i32) {
- SDNode *Result = Emit_167(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVSX64rr32, MVT::i32, MVT::i64);
+ SDNode *Result = Emit_167(N, TargetOpcode::EXTRACT_SUBREG, X86::MOVSX64rr32, MVT::i32, MVT::i64);
return Result;
}
@@ -29668,7 +29481,7 @@ SDNode *Select_ISD_SIGN_EXTEND_INREG_i64(SDNode *N) {
// Emits: (MOVSX64rr16:i64 (EXTRACT_SUBREG:i16 GR64:i64:$src, 3:i32))
// Pattern complexity = 3 cost = 2 size = 3
if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i16) {
- SDNode *Result = Emit_165(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVSX64rr16, MVT::i16, MVT::i64);
+ SDNode *Result = Emit_165(N, TargetOpcode::EXTRACT_SUBREG, X86::MOVSX64rr16, MVT::i16, MVT::i64);
return Result;
}
@@ -29676,7 +29489,7 @@ SDNode *Select_ISD_SIGN_EXTEND_INREG_i64(SDNode *N) {
// Emits: (MOVSX64rr8:i64 (EXTRACT_SUBREG:i8 GR64:i64:$src, 1:i32))
// Pattern complexity = 3 cost = 2 size = 3
if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i8) {
- SDNode *Result = Emit_164(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVSX64rr8, MVT::i8, MVT::i64);
+ SDNode *Result = Emit_164(N, TargetOpcode::EXTRACT_SUBREG, X86::MOVSX64rr8, MVT::i8, MVT::i64);
return Result;
}
@@ -29685,8 +29498,7 @@ SDNode *Select_ISD_SIGN_EXTEND_INREG_i64(SDNode *N) {
}
SDNode *Select_ISD_SINT_TO_FP_f32(SDNode *N) {
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSE1())) {
+ if ((Subtarget->hasSSE1())) {
SDValue N0 = N->getOperand(0);
if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse()) {
@@ -29729,9 +29541,6 @@ SDNode *Select_ISD_SINT_TO_FP_f32(SDNode *N) {
}
}
}
- }
- if ((Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
// Pattern: (sint_to_fp:f32 GR64:i64:$src)
// Emits: (CVTSI2SS64rr:f32 GR64:i64:$src)
@@ -29755,8 +29564,7 @@ SDNode *Select_ISD_SINT_TO_FP_f32(SDNode *N) {
}
SDNode *Select_ISD_SINT_TO_FP_f64(SDNode *N) {
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSE2())) {
+ if ((Subtarget->hasSSE2())) {
SDValue N0 = N->getOperand(0);
if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse()) {
@@ -29799,9 +29607,6 @@ SDNode *Select_ISD_SINT_TO_FP_f64(SDNode *N) {
}
}
}
- }
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
// Pattern: (sint_to_fp:f64 GR64:i64:$src)
// Emits: (CVTSI2SD64rr:f64 GR64:i64:$src)
@@ -30181,7 +29986,7 @@ SDNode *Select_ISD_SRL_i16(SDNode *N) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(8) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_168(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX32rr8, TargetInstrInfo::EXTRACT_SUBREG, MVT::i16, MVT::i8, MVT::i32, MVT::i16);
+ SDNode *Result = Emit_168(N, TargetOpcode::COPY_TO_REGCLASS, TargetOpcode::EXTRACT_SUBREG, X86::MOVZX32rr8, TargetOpcode::EXTRACT_SUBREG, MVT::i16, MVT::i8, MVT::i32, MVT::i16);
return Result;
}
}
@@ -30198,7 +30003,7 @@ SDNode *Select_ISD_SRL_i16(SDNode *N) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(8) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_168(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX32_NOREXrr8, TargetInstrInfo::EXTRACT_SUBREG, MVT::i16, MVT::i8, MVT::i32, MVT::i16);
+ SDNode *Result = Emit_168(N, TargetOpcode::COPY_TO_REGCLASS, TargetOpcode::EXTRACT_SUBREG, X86::MOVZX32_NOREXrr8, TargetOpcode::EXTRACT_SUBREG, MVT::i16, MVT::i8, MVT::i32, MVT::i16);
return Result;
}
}
@@ -31848,64 +31653,62 @@ DISABLE_INLINE SDNode *Emit_221(SDNode *N, unsigned Opc0, SDValue &CPTmpN1101_0,
return ResNode;
}
SDNode *Select_ISD_STORE(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
- {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedstore(N) &&
- Predicate_store(N)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::OR &&
- N1.hasOneUse()) {
- {
- SDValue N10 = N1.getNode()->getOperand(0);
+ {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedstore(N) &&
+ Predicate_store(N)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::OR &&
+ N1.hasOneUse()) {
+ {
+ SDValue N10 = N1.getNode()->getOperand(0);
- // Pattern: (st:isVoid (or:i32 (srl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (trunc:i8 ECX:i32:$amt)), (shl:i32 GR32:i32:$src2, (trunc:i8 (sub:i32 32:i32, ECX:i32:$amt)))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHRD32mrCL:isVoid addr:iPTR:$dst, GR32:i32:$src2)
- // Pattern complexity = 67 cost = 1 size = 3
- if (N10.getNode()->getOpcode() == ISD::SRL &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::LOAD &&
- N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N) &&
- (Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
- SDValue Chain100 = N100.getNode()->getOperand(0);
- if (Predicate_unindexedload(N100.getNode()) &&
- Predicate_loadi32(N100.getNode())) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue CPTmpN1001_0;
- SDValue CPTmpN1001_1;
- SDValue CPTmpN1001_2;
- SDValue CPTmpN1001_3;
- SDValue CPTmpN1001_4;
- if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::TRUNCATE) {
- SDValue N1010 = N101.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SHL) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::TRUNCATE) {
- SDValue N1110 = N111.getNode()->getOperand(0);
- if (N1110.getNode()->getOpcode() == ISD::SUB) {
- SDValue N11100 = N1110.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11100.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(32)) {
- SDValue N11101 = N1110.getNode()->getOperand(1);
- if (N1010 == N11101) {
- SDValue N2 = N->getOperand(2);
- if (N1001 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i8 &&
- N1010.getValueType() == MVT::i32 &&
- N111.getValueType() == MVT::i8 &&
- N1110.getValueType() == MVT::i32) {
- SDNode *Result = Emit_203(N, X86::SHRD32mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
- return Result;
- }
+ // Pattern: (st:isVoid (or:i32 (srl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (trunc:i8 ECX:i32:$amt)), (shl:i32 GR32:i32:$src2, (trunc:i8 (sub:i32 32:i32, ECX:i32:$amt)))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHRD32mrCL:isVoid addr:iPTR:$dst, GR32:i32:$src2)
+ // Pattern complexity = 67 cost = 1 size = 3
+ if (N10.getNode()->getOpcode() == ISD::SRL &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::LOAD &&
+ N100.hasOneUse() &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N) &&
+ (Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
+ SDValue Chain100 = N100.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N100.getNode()) &&
+ Predicate_loadi32(N100.getNode())) {
+ SDValue N1001 = N100.getNode()->getOperand(1);
+ SDValue CPTmpN1001_0;
+ SDValue CPTmpN1001_1;
+ SDValue CPTmpN1001_2;
+ SDValue CPTmpN1001_3;
+ SDValue CPTmpN1001_4;
+ if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::TRUNCATE) {
+ SDValue N1010 = N101.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::TRUNCATE) {
+ SDValue N1110 = N111.getNode()->getOperand(0);
+ if (N1110.getNode()->getOpcode() == ISD::SUB) {
+ SDValue N11100 = N1110.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11100.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(32)) {
+ SDValue N11101 = N1110.getNode()->getOperand(1);
+ if (N1010 == N11101) {
+ SDValue N2 = N->getOperand(2);
+ if (N1001 == N2 &&
+ N1.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i8 &&
+ N1010.getValueType() == MVT::i32 &&
+ N111.getValueType() == MVT::i8 &&
+ N1110.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_203(N, X86::SHRD32mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ return Result;
}
}
}
@@ -31917,54 +31720,113 @@ SDNode *Select_ISD_STORE(SDNode *N) {
}
}
}
+ }
- // Pattern: (st:isVoid (or:i32 (shl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (trunc:i8 ECX:i32:$amt)), (srl:i32 GR32:i32:$src2, (trunc:i8 (sub:i32 32:i32, ECX:i32:$amt)))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHLD32mrCL:isVoid addr:iPTR:$dst, GR32:i32:$src2)
- // Pattern complexity = 67 cost = 1 size = 3
- if (N10.getNode()->getOpcode() == ISD::SHL &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::LOAD &&
- N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N) &&
- (Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
- SDValue Chain100 = N100.getNode()->getOperand(0);
- if (Predicate_unindexedload(N100.getNode()) &&
- Predicate_loadi32(N100.getNode())) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue CPTmpN1001_0;
- SDValue CPTmpN1001_1;
- SDValue CPTmpN1001_2;
- SDValue CPTmpN1001_3;
- SDValue CPTmpN1001_4;
- if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::TRUNCATE) {
- SDValue N1010 = N101.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SRL) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::TRUNCATE) {
- SDValue N1110 = N111.getNode()->getOperand(0);
- if (N1110.getNode()->getOpcode() == ISD::SUB) {
- SDValue N11100 = N1110.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11100.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(32)) {
- SDValue N11101 = N1110.getNode()->getOperand(1);
- if (N1010 == N11101) {
- SDValue N2 = N->getOperand(2);
- if (N1001 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i8 &&
- N1010.getValueType() == MVT::i32 &&
- N111.getValueType() == MVT::i8 &&
- N1110.getValueType() == MVT::i32) {
- SDNode *Result = Emit_203(N, X86::SHLD32mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
- return Result;
- }
+ // Pattern: (st:isVoid (or:i32 (shl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (trunc:i8 ECX:i32:$amt)), (srl:i32 GR32:i32:$src2, (trunc:i8 (sub:i32 32:i32, ECX:i32:$amt)))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHLD32mrCL:isVoid addr:iPTR:$dst, GR32:i32:$src2)
+ // Pattern complexity = 67 cost = 1 size = 3
+ if (N10.getNode()->getOpcode() == ISD::SHL &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::LOAD &&
+ N100.hasOneUse() &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N) &&
+ (Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
+ SDValue Chain100 = N100.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N100.getNode()) &&
+ Predicate_loadi32(N100.getNode())) {
+ SDValue N1001 = N100.getNode()->getOperand(1);
+ SDValue CPTmpN1001_0;
+ SDValue CPTmpN1001_1;
+ SDValue CPTmpN1001_2;
+ SDValue CPTmpN1001_3;
+ SDValue CPTmpN1001_4;
+ if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::TRUNCATE) {
+ SDValue N1010 = N101.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::TRUNCATE) {
+ SDValue N1110 = N111.getNode()->getOperand(0);
+ if (N1110.getNode()->getOpcode() == ISD::SUB) {
+ SDValue N11100 = N1110.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11100.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(32)) {
+ SDValue N11101 = N1110.getNode()->getOperand(1);
+ if (N1010 == N11101) {
+ SDValue N2 = N->getOperand(2);
+ if (N1001 == N2 &&
+ N1.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i8 &&
+ N1010.getValueType() == MVT::i32 &&
+ N111.getValueType() == MVT::i8 &&
+ N1110.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_203(N, X86::SHLD32mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (or:i16 (srl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (trunc:i8 CX:i16:$amt)), (shl:i16 GR16:i16:$src2, (trunc:i8 (sub:i16 16:i16, CX:i16:$amt)))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHRD16mrCL:isVoid addr:iPTR:$dst, GR16:i16:$src2)
+ // Pattern complexity = 67 cost = 1 size = 3
+ if (N10.getNode()->getOpcode() == ISD::SRL &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::LOAD &&
+ N100.hasOneUse() &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N) &&
+ (Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
+ SDValue Chain100 = N100.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N100.getNode()) &&
+ Predicate_loadi16(N100.getNode())) {
+ SDValue N1001 = N100.getNode()->getOperand(1);
+ SDValue CPTmpN1001_0;
+ SDValue CPTmpN1001_1;
+ SDValue CPTmpN1001_2;
+ SDValue CPTmpN1001_3;
+ SDValue CPTmpN1001_4;
+ if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::TRUNCATE) {
+ SDValue N1010 = N101.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::TRUNCATE) {
+ SDValue N1110 = N111.getNode()->getOperand(0);
+ if (N1110.getNode()->getOpcode() == ISD::SUB) {
+ SDValue N11100 = N1110.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11100.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N11101 = N1110.getNode()->getOperand(1);
+ if (N1010 == N11101) {
+ SDValue N2 = N->getOperand(2);
+ if (N1001 == N2 &&
+ N1.getValueType() == MVT::i16 &&
+ N101.getValueType() == MVT::i8 &&
+ N1010.getValueType() == MVT::i16 &&
+ N111.getValueType() == MVT::i8 &&
+ N1110.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_205(N, X86::SHRD16mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ return Result;
}
}
}
@@ -31976,12 +31838,13 @@ SDNode *Select_ISD_STORE(SDNode *N) {
}
}
}
+ }
+ if (N10.getNode()->getOpcode() == ISD::SHL) {
- // Pattern: (st:isVoid (or:i16 (srl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (trunc:i8 CX:i16:$amt)), (shl:i16 GR16:i16:$src2, (trunc:i8 (sub:i16 16:i16, CX:i16:$amt)))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHRD16mrCL:isVoid addr:iPTR:$dst, GR16:i16:$src2)
+ // Pattern: (st:isVoid (or:i16 (shl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (trunc:i8 CX:i16:$amt)), (srl:i16 GR16:i16:$src2, (trunc:i8 (sub:i16 16:i16, CX:i16:$amt)))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHLD16mrCL:isVoid addr:iPTR:$dst, GR16:i16:$src2)
// Pattern complexity = 67 cost = 1 size = 3
- if (N10.getNode()->getOpcode() == ISD::SRL &&
- N10.hasOneUse()) {
+ if (N10.hasOneUse()) {
SDValue N100 = N10.getNode()->getOperand(0);
if (N100.getNode()->getOpcode() == ISD::LOAD &&
N100.hasOneUse() &&
@@ -32001,7 +31864,7 @@ SDNode *Select_ISD_STORE(SDNode *N) {
if (N101.getNode()->getOpcode() == ISD::TRUNCATE) {
SDValue N1010 = N101.getNode()->getOperand(0);
SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SHL) {
+ if (N11.getNode()->getOpcode() == ISD::SRL) {
SDValue N110 = N11.getNode()->getOperand(0);
SDValue N111 = N11.getNode()->getOperand(1);
if (N111.getNode()->getOpcode() == ISD::TRUNCATE) {
@@ -32021,7 +31884,7 @@ SDNode *Select_ISD_STORE(SDNode *N) {
N1010.getValueType() == MVT::i16 &&
N111.getValueType() == MVT::i8 &&
N1110.getValueType() == MVT::i16) {
- SDNode *Result = Emit_205(N, X86::SHRD16mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ SDNode *Result = Emit_205(N, X86::SHLD16mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -32035,55 +31898,52 @@ SDNode *Select_ISD_STORE(SDNode *N) {
}
}
}
- if (N10.getNode()->getOpcode() == ISD::SHL) {
-
- // Pattern: (st:isVoid (or:i16 (shl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (trunc:i8 CX:i16:$amt)), (srl:i16 GR16:i16:$src2, (trunc:i8 (sub:i16 16:i16, CX:i16:$amt)))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHLD16mrCL:isVoid addr:iPTR:$dst, GR16:i16:$src2)
- // Pattern complexity = 67 cost = 1 size = 3
- if (N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::LOAD &&
- N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N) &&
- (Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
- SDValue Chain100 = N100.getNode()->getOperand(0);
- if (Predicate_unindexedload(N100.getNode()) &&
- Predicate_loadi16(N100.getNode())) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue CPTmpN1001_0;
- SDValue CPTmpN1001_1;
- SDValue CPTmpN1001_2;
- SDValue CPTmpN1001_3;
- SDValue CPTmpN1001_4;
- if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::TRUNCATE) {
- SDValue N1010 = N101.getNode()->getOperand(0);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SRL) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::TRUNCATE) {
- SDValue N1110 = N111.getNode()->getOperand(0);
- if (N1110.getNode()->getOpcode() == ISD::SUB) {
- SDValue N11100 = N1110.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11100.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N11101 = N1110.getNode()->getOperand(1);
- if (N1010 == N11101) {
- SDValue N2 = N->getOperand(2);
- if (N1001 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N101.getValueType() == MVT::i8 &&
- N1010.getValueType() == MVT::i16 &&
- N111.getValueType() == MVT::i8 &&
- N1110.getValueType() == MVT::i16) {
- SDNode *Result = Emit_205(N, X86::SHLD16mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
- return Result;
- }
- }
+
+ // Pattern: (st:isVoid (or:i32 (shl:i32 GR32:i32:$src2, (trunc:i8 (sub:i32 32:i32, ECX:i32:$amt))), (srl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (trunc:i8 ECX:i32:$amt))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHRD32mrCL:isVoid addr:iPTR:$dst, GR32:i32:$src2)
+ // Pattern complexity = 67 cost = 1 size = 3
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::TRUNCATE) {
+ SDValue N1010 = N101.getNode()->getOperand(0);
+ if (N1010.getNode()->getOpcode() == ISD::SUB) {
+ SDValue N10100 = N1010.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10100.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(32)) {
+ SDValue N10101 = N1010.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SRL &&
+ N11.hasOneUse()) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::LOAD &&
+ N110.hasOneUse() &&
+ IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N) &&
+ (Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
+ SDValue Chain110 = N110.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N110.getNode()) &&
+ Predicate_loadi32(N110.getNode())) {
+ SDValue N1101 = N110.getNode()->getOperand(1);
+ SDValue CPTmpN1101_0;
+ SDValue CPTmpN1101_1;
+ SDValue CPTmpN1101_2;
+ SDValue CPTmpN1101_3;
+ SDValue CPTmpN1101_4;
+ if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::TRUNCATE) {
+ SDValue N1110 = N111.getNode()->getOperand(0);
+ if (N10101 == N1110) {
+ SDValue N2 = N->getOperand(2);
+ if (N1101 == N2 &&
+ N1.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i8 &&
+ N1010.getValueType() == MVT::i32 &&
+ N111.getValueType() == MVT::i8 &&
+ N1110.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_219(N, X86::SHRD32mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
+ return Result;
}
}
}
@@ -32094,53 +31954,55 @@ SDNode *Select_ISD_STORE(SDNode *N) {
}
}
}
+ }
+ }
- // Pattern: (st:isVoid (or:i32 (shl:i32 GR32:i32:$src2, (trunc:i8 (sub:i32 32:i32, ECX:i32:$amt))), (srl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (trunc:i8 ECX:i32:$amt))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHRD32mrCL:isVoid addr:iPTR:$dst, GR32:i32:$src2)
- // Pattern complexity = 67 cost = 1 size = 3
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::TRUNCATE) {
- SDValue N1010 = N101.getNode()->getOperand(0);
- if (N1010.getNode()->getOpcode() == ISD::SUB) {
- SDValue N10100 = N1010.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10100.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(32)) {
- SDValue N10101 = N1010.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SRL &&
- N11.hasOneUse()) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::LOAD &&
- N110.hasOneUse() &&
- IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N) &&
- (Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
- SDValue Chain110 = N110.getNode()->getOperand(0);
- if (Predicate_unindexedload(N110.getNode()) &&
- Predicate_loadi32(N110.getNode())) {
- SDValue N1101 = N110.getNode()->getOperand(1);
- SDValue CPTmpN1101_0;
- SDValue CPTmpN1101_1;
- SDValue CPTmpN1101_2;
- SDValue CPTmpN1101_3;
- SDValue CPTmpN1101_4;
- if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::TRUNCATE) {
- SDValue N1110 = N111.getNode()->getOperand(0);
- if (N10101 == N1110) {
- SDValue N2 = N->getOperand(2);
- if (N1101 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i8 &&
- N1010.getValueType() == MVT::i32 &&
- N111.getValueType() == MVT::i8 &&
- N1110.getValueType() == MVT::i32) {
- SDNode *Result = Emit_219(N, X86::SHRD32mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (or:i32 (srl:i32 GR32:i32:$src2, (trunc:i8 (sub:i32 32:i32, ECX:i32:$amt))), (shl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (trunc:i8 ECX:i32:$amt))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHLD32mrCL:isVoid addr:iPTR:$dst, GR32:i32:$src2)
+ // Pattern complexity = 67 cost = 1 size = 3
+ if (N10.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::TRUNCATE) {
+ SDValue N1010 = N101.getNode()->getOperand(0);
+ if (N1010.getNode()->getOpcode() == ISD::SUB) {
+ SDValue N10100 = N1010.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10100.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(32)) {
+ SDValue N10101 = N1010.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SHL &&
+ N11.hasOneUse()) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::LOAD &&
+ N110.hasOneUse() &&
+ IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N) &&
+ (Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
+ SDValue Chain110 = N110.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N110.getNode()) &&
+ Predicate_loadi32(N110.getNode())) {
+ SDValue N1101 = N110.getNode()->getOperand(1);
+ SDValue CPTmpN1101_0;
+ SDValue CPTmpN1101_1;
+ SDValue CPTmpN1101_2;
+ SDValue CPTmpN1101_3;
+ SDValue CPTmpN1101_4;
+ if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::TRUNCATE) {
+ SDValue N1110 = N111.getNode()->getOperand(0);
+ if (N10101 == N1110) {
+ SDValue N2 = N->getOperand(2);
+ if (N1101 == N2 &&
+ N1.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i8 &&
+ N1010.getValueType() == MVT::i32 &&
+ N111.getValueType() == MVT::i8 &&
+ N1110.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_219(N, X86::SHLD32mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
+ return Result;
}
}
}
@@ -32152,54 +32014,54 @@ SDNode *Select_ISD_STORE(SDNode *N) {
}
}
}
+ }
- // Pattern: (st:isVoid (or:i32 (srl:i32 GR32:i32:$src2, (trunc:i8 (sub:i32 32:i32, ECX:i32:$amt))), (shl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (trunc:i8 ECX:i32:$amt))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHLD32mrCL:isVoid addr:iPTR:$dst, GR32:i32:$src2)
- // Pattern complexity = 67 cost = 1 size = 3
- if (N10.getNode()->getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::TRUNCATE) {
- SDValue N1010 = N101.getNode()->getOperand(0);
- if (N1010.getNode()->getOpcode() == ISD::SUB) {
- SDValue N10100 = N1010.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10100.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(32)) {
- SDValue N10101 = N1010.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SHL &&
- N11.hasOneUse()) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::LOAD &&
- N110.hasOneUse() &&
- IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N) &&
- (Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
- SDValue Chain110 = N110.getNode()->getOperand(0);
- if (Predicate_unindexedload(N110.getNode()) &&
- Predicate_loadi32(N110.getNode())) {
- SDValue N1101 = N110.getNode()->getOperand(1);
- SDValue CPTmpN1101_0;
- SDValue CPTmpN1101_1;
- SDValue CPTmpN1101_2;
- SDValue CPTmpN1101_3;
- SDValue CPTmpN1101_4;
- if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::TRUNCATE) {
- SDValue N1110 = N111.getNode()->getOperand(0);
- if (N10101 == N1110) {
- SDValue N2 = N->getOperand(2);
- if (N1101 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i8 &&
- N1010.getValueType() == MVT::i32 &&
- N111.getValueType() == MVT::i8 &&
- N1110.getValueType() == MVT::i32) {
- SDNode *Result = Emit_219(N, X86::SHLD32mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (or:i16 (shl:i16 GR16:i16:$src2, (trunc:i8 (sub:i16 16:i16, CX:i16:$amt))), (srl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (trunc:i8 CX:i16:$amt))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHRD16mrCL:isVoid addr:iPTR:$dst, GR16:i16:$src2)
+ // Pattern complexity = 67 cost = 1 size = 3
+ if (N10.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::TRUNCATE) {
+ SDValue N1010 = N101.getNode()->getOperand(0);
+ if (N1010.getNode()->getOpcode() == ISD::SUB) {
+ SDValue N10100 = N1010.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10100.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N10101 = N1010.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SRL &&
+ N11.hasOneUse()) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::LOAD &&
+ N110.hasOneUse() &&
+ IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N) &&
+ (Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
+ SDValue Chain110 = N110.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N110.getNode()) &&
+ Predicate_loadi16(N110.getNode())) {
+ SDValue N1101 = N110.getNode()->getOperand(1);
+ SDValue CPTmpN1101_0;
+ SDValue CPTmpN1101_1;
+ SDValue CPTmpN1101_2;
+ SDValue CPTmpN1101_3;
+ SDValue CPTmpN1101_4;
+ if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::TRUNCATE) {
+ SDValue N1110 = N111.getNode()->getOperand(0);
+ if (N10101 == N1110) {
+ SDValue N2 = N->getOperand(2);
+ if (N1101 == N2 &&
+ N1.getValueType() == MVT::i16 &&
+ N101.getValueType() == MVT::i8 &&
+ N1010.getValueType() == MVT::i16 &&
+ N111.getValueType() == MVT::i8 &&
+ N1110.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_221(N, X86::SHRD16mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
+ return Result;
}
}
}
@@ -32211,11 +32073,13 @@ SDNode *Select_ISD_STORE(SDNode *N) {
}
}
}
+ }
+ if (N10.getNode()->getOpcode() == ISD::SRL) {
- // Pattern: (st:isVoid (or:i16 (shl:i16 GR16:i16:$src2, (trunc:i8 (sub:i16 16:i16, CX:i16:$amt))), (srl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (trunc:i8 CX:i16:$amt))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHRD16mrCL:isVoid addr:iPTR:$dst, GR16:i16:$src2)
+ // Pattern: (st:isVoid (or:i16 (srl:i16 GR16:i16:$src2, (trunc:i8 (sub:i16 16:i16, CX:i16:$amt))), (shl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (trunc:i8 CX:i16:$amt))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHLD16mrCL:isVoid addr:iPTR:$dst, GR16:i16:$src2)
// Pattern complexity = 67 cost = 1 size = 3
- if (N10.getNode()->getOpcode() == ISD::SHL) {
+ {
SDValue N100 = N10.getNode()->getOperand(0);
SDValue N101 = N10.getNode()->getOperand(1);
if (N101.getNode()->getOpcode() == ISD::TRUNCATE) {
@@ -32228,7 +32092,7 @@ SDNode *Select_ISD_STORE(SDNode *N) {
if (CN1 == INT64_C(16)) {
SDValue N10101 = N1010.getNode()->getOperand(1);
SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SRL &&
+ if (N11.getNode()->getOpcode() == ISD::SHL &&
N11.hasOneUse()) {
SDValue N110 = N11.getNode()->getOperand(0);
if (N110.getNode()->getOpcode() == ISD::LOAD &&
@@ -32256,7 +32120,7 @@ SDNode *Select_ISD_STORE(SDNode *N) {
N1010.getValueType() == MVT::i16 &&
N111.getValueType() == MVT::i8 &&
N1110.getValueType() == MVT::i16) {
- SDNode *Result = Emit_221(N, X86::SHRD16mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
+ SDNode *Result = Emit_221(N, X86::SHLD16mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
return Result;
}
}
@@ -32270,123 +32134,11 @@ SDNode *Select_ISD_STORE(SDNode *N) {
}
}
}
- if (N10.getNode()->getOpcode() == ISD::SRL) {
-
- // Pattern: (st:isVoid (or:i16 (srl:i16 GR16:i16:$src2, (trunc:i8 (sub:i16 16:i16, CX:i16:$amt))), (shl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (trunc:i8 CX:i16:$amt))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHLD16mrCL:isVoid addr:iPTR:$dst, GR16:i16:$src2)
- // Pattern complexity = 67 cost = 1 size = 3
- {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::TRUNCATE) {
- SDValue N1010 = N101.getNode()->getOperand(0);
- if (N1010.getNode()->getOpcode() == ISD::SUB) {
- SDValue N10100 = N1010.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10100.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N10101 = N1010.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SHL &&
- N11.hasOneUse()) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::LOAD &&
- N110.hasOneUse() &&
- IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N) &&
- (Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
- SDValue Chain110 = N110.getNode()->getOperand(0);
- if (Predicate_unindexedload(N110.getNode()) &&
- Predicate_loadi16(N110.getNode())) {
- SDValue N1101 = N110.getNode()->getOperand(1);
- SDValue CPTmpN1101_0;
- SDValue CPTmpN1101_1;
- SDValue CPTmpN1101_2;
- SDValue CPTmpN1101_3;
- SDValue CPTmpN1101_4;
- if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::TRUNCATE) {
- SDValue N1110 = N111.getNode()->getOperand(0);
- if (N10101 == N1110) {
- SDValue N2 = N->getOperand(2);
- if (N1101 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N101.getValueType() == MVT::i8 &&
- N1010.getValueType() == MVT::i16 &&
- N111.getValueType() == MVT::i8 &&
- N1110.getValueType() == MVT::i16) {
- SDNode *Result = Emit_221(N, X86::SHLD16mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (or:i32 (srl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, CL:i8:$amt), (shl:i32 GR32:i32:$src2, (sub:i8 32:i8, CL:i8:$amt))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHRD32mrCL:isVoid addr:iPTR:$dst, GR32:i32:$src2)
- // Pattern complexity = 61 cost = 1 size = 3
- if (N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::LOAD &&
- N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N) &&
- (Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
- SDValue Chain100 = N100.getNode()->getOperand(0);
- if (Predicate_unindexedload(N100.getNode()) &&
- Predicate_loadi32(N100.getNode())) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue CPTmpN1001_0;
- SDValue CPTmpN1001_1;
- SDValue CPTmpN1001_2;
- SDValue CPTmpN1001_3;
- SDValue CPTmpN1001_4;
- if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SHL) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::SUB) {
- SDValue N1110 = N111.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1110.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(32)) {
- SDValue N1111 = N111.getNode()->getOperand(1);
- if (N101 == N1111) {
- SDValue N2 = N->getOperand(2);
- if (N1001 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i8 &&
- N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_202(N, X86::SHRD32mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- // Pattern: (st:isVoid (or:i32 (shl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, CL:i8:$amt), (srl:i32 GR32:i32:$src2, (sub:i8 32:i8, CL:i8:$amt))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHLD32mrCL:isVoid addr:iPTR:$dst, GR32:i32:$src2)
+ // Pattern: (st:isVoid (or:i32 (srl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, CL:i8:$amt), (shl:i32 GR32:i32:$src2, (sub:i8 32:i8, CL:i8:$amt))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHRD32mrCL:isVoid addr:iPTR:$dst, GR32:i32:$src2)
// Pattern complexity = 61 cost = 1 size = 3
- if (N10.getNode()->getOpcode() == ISD::SHL &&
- N10.hasOneUse()) {
+ if (N10.hasOneUse()) {
SDValue N100 = N10.getNode()->getOperand(0);
if (N100.getNode()->getOpcode() == ISD::LOAD &&
N100.hasOneUse() &&
@@ -32404,7 +32156,7 @@ SDNode *Select_ISD_STORE(SDNode *N) {
if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
SDValue N101 = N10.getNode()->getOperand(1);
SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SRL) {
+ if (N11.getNode()->getOpcode() == ISD::SHL) {
SDValue N110 = N11.getNode()->getOperand(0);
SDValue N111 = N11.getNode()->getOperand(1);
if (N111.getNode()->getOpcode() == ISD::SUB) {
@@ -32420,7 +32172,7 @@ SDNode *Select_ISD_STORE(SDNode *N) {
N1.getValueType() == MVT::i32 &&
N101.getValueType() == MVT::i8 &&
N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_202(N, X86::SHLD32mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ SDNode *Result = Emit_202(N, X86::SHRD32mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -32432,12 +32184,115 @@ SDNode *Select_ISD_STORE(SDNode *N) {
}
}
}
+ }
- // Pattern: (st:isVoid (or:i16 (srl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, CL:i8:$amt), (shl:i16 GR16:i16:$src2, (sub:i8 16:i8, CL:i8:$amt))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHRD16mrCL:isVoid addr:iPTR:$dst, GR16:i16:$src2)
+ // Pattern: (st:isVoid (or:i32 (shl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, CL:i8:$amt), (srl:i32 GR32:i32:$src2, (sub:i8 32:i8, CL:i8:$amt))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHLD32mrCL:isVoid addr:iPTR:$dst, GR32:i32:$src2)
+ // Pattern complexity = 61 cost = 1 size = 3
+ if (N10.getNode()->getOpcode() == ISD::SHL &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::LOAD &&
+ N100.hasOneUse() &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N) &&
+ (Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
+ SDValue Chain100 = N100.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N100.getNode()) &&
+ Predicate_loadi32(N100.getNode())) {
+ SDValue N1001 = N100.getNode()->getOperand(1);
+ SDValue CPTmpN1001_0;
+ SDValue CPTmpN1001_1;
+ SDValue CPTmpN1001_2;
+ SDValue CPTmpN1001_3;
+ SDValue CPTmpN1001_4;
+ if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::SUB) {
+ SDValue N1110 = N111.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1110.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(32)) {
+ SDValue N1111 = N111.getNode()->getOperand(1);
+ if (N101 == N1111) {
+ SDValue N2 = N->getOperand(2);
+ if (N1001 == N2 &&
+ N1.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i8 &&
+ N111.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_202(N, X86::SHLD32mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (or:i16 (srl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, CL:i8:$amt), (shl:i16 GR16:i16:$src2, (sub:i8 16:i8, CL:i8:$amt))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHRD16mrCL:isVoid addr:iPTR:$dst, GR16:i16:$src2)
+ // Pattern complexity = 61 cost = 1 size = 3
+ if (N10.getNode()->getOpcode() == ISD::SRL &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::LOAD &&
+ N100.hasOneUse() &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N) &&
+ (Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
+ SDValue Chain100 = N100.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N100.getNode()) &&
+ Predicate_loadi16(N100.getNode())) {
+ SDValue N1001 = N100.getNode()->getOperand(1);
+ SDValue CPTmpN1001_0;
+ SDValue CPTmpN1001_1;
+ SDValue CPTmpN1001_2;
+ SDValue CPTmpN1001_3;
+ SDValue CPTmpN1001_4;
+ if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::SUB) {
+ SDValue N1110 = N111.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1110.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N1111 = N111.getNode()->getOperand(1);
+ if (N101 == N1111) {
+ SDValue N2 = N->getOperand(2);
+ if (N1001 == N2 &&
+ N1.getValueType() == MVT::i16 &&
+ N101.getValueType() == MVT::i8 &&
+ N111.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_202(N, X86::SHRD16mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N10.getNode()->getOpcode() == ISD::SHL) {
+
+ // Pattern: (st:isVoid (or:i16 (shl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, CL:i8:$amt), (srl:i16 GR16:i16:$src2, (sub:i8 16:i8, CL:i8:$amt))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHLD16mrCL:isVoid addr:iPTR:$dst, GR16:i16:$src2)
// Pattern complexity = 61 cost = 1 size = 3
- if (N10.getNode()->getOpcode() == ISD::SRL &&
- N10.hasOneUse()) {
+ if (N10.hasOneUse()) {
SDValue N100 = N10.getNode()->getOperand(0);
if (N100.getNode()->getOpcode() == ISD::LOAD &&
N100.hasOneUse() &&
@@ -32455,7 +32310,7 @@ SDNode *Select_ISD_STORE(SDNode *N) {
if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
SDValue N101 = N10.getNode()->getOperand(1);
SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SHL) {
+ if (N11.getNode()->getOpcode() == ISD::SRL) {
SDValue N110 = N11.getNode()->getOperand(0);
SDValue N111 = N11.getNode()->getOperand(1);
if (N111.getNode()->getOpcode() == ISD::SUB) {
@@ -32471,7 +32326,7 @@ SDNode *Select_ISD_STORE(SDNode *N) {
N1.getValueType() == MVT::i16 &&
N101.getValueType() == MVT::i8 &&
N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_202(N, X86::SHRD16mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ SDNode *Result = Emit_202(N, X86::SHLD16mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -32483,49 +32338,46 @@ SDNode *Select_ISD_STORE(SDNode *N) {
}
}
}
- if (N10.getNode()->getOpcode() == ISD::SHL) {
-
- // Pattern: (st:isVoid (or:i16 (shl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, CL:i8:$amt), (srl:i16 GR16:i16:$src2, (sub:i8 16:i8, CL:i8:$amt))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHLD16mrCL:isVoid addr:iPTR:$dst, GR16:i16:$src2)
- // Pattern complexity = 61 cost = 1 size = 3
- if (N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::LOAD &&
- N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N) &&
- (Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
- SDValue Chain100 = N100.getNode()->getOperand(0);
- if (Predicate_unindexedload(N100.getNode()) &&
- Predicate_loadi16(N100.getNode())) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue CPTmpN1001_0;
- SDValue CPTmpN1001_1;
- SDValue CPTmpN1001_2;
- SDValue CPTmpN1001_3;
- SDValue CPTmpN1001_4;
- if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SRL) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::SUB) {
- SDValue N1110 = N111.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1110.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N1111 = N111.getNode()->getOperand(1);
- if (N101 == N1111) {
- SDValue N2 = N->getOperand(2);
- if (N1001 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N101.getValueType() == MVT::i8 &&
- N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_202(N, X86::SHLD16mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
- return Result;
- }
- }
+
+ // Pattern: (st:isVoid (or:i32 (shl:i32 GR32:i32:$src2, (sub:i8 32:i8, CL:i8:$amt)), (srl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, CL:i8:$amt)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHRD32mrCL:isVoid addr:iPTR:$dst, GR32:i32:$src2)
+ // Pattern complexity = 61 cost = 1 size = 3
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::SUB) {
+ SDValue N1010 = N101.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1010.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(32)) {
+ SDValue N1011 = N101.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SRL &&
+ N11.hasOneUse()) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::LOAD &&
+ N110.hasOneUse() &&
+ IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N) &&
+ (Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
+ SDValue Chain110 = N110.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N110.getNode()) &&
+ Predicate_loadi32(N110.getNode())) {
+ SDValue N1101 = N110.getNode()->getOperand(1);
+ SDValue CPTmpN1101_0;
+ SDValue CPTmpN1101_1;
+ SDValue CPTmpN1101_2;
+ SDValue CPTmpN1101_3;
+ SDValue CPTmpN1101_4;
+ if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N1011 == N111) {
+ SDValue N2 = N->getOperand(2);
+ if (N1101 == N2 &&
+ N1.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i8 &&
+ N111.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_218(N, X86::SHRD32mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
+ return Result;
}
}
}
@@ -32534,47 +32386,49 @@ SDNode *Select_ISD_STORE(SDNode *N) {
}
}
}
+ }
+ }
- // Pattern: (st:isVoid (or:i32 (shl:i32 GR32:i32:$src2, (sub:i8 32:i8, CL:i8:$amt)), (srl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, CL:i8:$amt)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHRD32mrCL:isVoid addr:iPTR:$dst, GR32:i32:$src2)
- // Pattern complexity = 61 cost = 1 size = 3
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::SUB) {
- SDValue N1010 = N101.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1010.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(32)) {
- SDValue N1011 = N101.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SRL &&
- N11.hasOneUse()) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::LOAD &&
- N110.hasOneUse() &&
- IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N) &&
- (Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
- SDValue Chain110 = N110.getNode()->getOperand(0);
- if (Predicate_unindexedload(N110.getNode()) &&
- Predicate_loadi32(N110.getNode())) {
- SDValue N1101 = N110.getNode()->getOperand(1);
- SDValue CPTmpN1101_0;
- SDValue CPTmpN1101_1;
- SDValue CPTmpN1101_2;
- SDValue CPTmpN1101_3;
- SDValue CPTmpN1101_4;
- if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N1011 == N111) {
- SDValue N2 = N->getOperand(2);
- if (N1101 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i8 &&
- N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_218(N, X86::SHRD32mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (or:i32 (srl:i32 GR32:i32:$src2, (sub:i8 32:i8, CL:i8:$amt)), (shl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, CL:i8:$amt)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHLD32mrCL:isVoid addr:iPTR:$dst, GR32:i32:$src2)
+ // Pattern complexity = 61 cost = 1 size = 3
+ if (N10.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::SUB) {
+ SDValue N1010 = N101.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1010.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(32)) {
+ SDValue N1011 = N101.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SHL &&
+ N11.hasOneUse()) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::LOAD &&
+ N110.hasOneUse() &&
+ IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N) &&
+ (Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
+ SDValue Chain110 = N110.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N110.getNode()) &&
+ Predicate_loadi32(N110.getNode())) {
+ SDValue N1101 = N110.getNode()->getOperand(1);
+ SDValue CPTmpN1101_0;
+ SDValue CPTmpN1101_1;
+ SDValue CPTmpN1101_2;
+ SDValue CPTmpN1101_3;
+ SDValue CPTmpN1101_4;
+ if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N1011 == N111) {
+ SDValue N2 = N->getOperand(2);
+ if (N1101 == N2 &&
+ N1.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i8 &&
+ N111.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_218(N, X86::SHLD32mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
+ return Result;
}
}
}
@@ -32584,48 +32438,48 @@ SDNode *Select_ISD_STORE(SDNode *N) {
}
}
}
+ }
- // Pattern: (st:isVoid (or:i32 (srl:i32 GR32:i32:$src2, (sub:i8 32:i8, CL:i8:$amt)), (shl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, CL:i8:$amt)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHLD32mrCL:isVoid addr:iPTR:$dst, GR32:i32:$src2)
- // Pattern complexity = 61 cost = 1 size = 3
- if (N10.getNode()->getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::SUB) {
- SDValue N1010 = N101.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1010.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(32)) {
- SDValue N1011 = N101.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SHL &&
- N11.hasOneUse()) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::LOAD &&
- N110.hasOneUse() &&
- IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N) &&
- (Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
- SDValue Chain110 = N110.getNode()->getOperand(0);
- if (Predicate_unindexedload(N110.getNode()) &&
- Predicate_loadi32(N110.getNode())) {
- SDValue N1101 = N110.getNode()->getOperand(1);
- SDValue CPTmpN1101_0;
- SDValue CPTmpN1101_1;
- SDValue CPTmpN1101_2;
- SDValue CPTmpN1101_3;
- SDValue CPTmpN1101_4;
- if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N1011 == N111) {
- SDValue N2 = N->getOperand(2);
- if (N1101 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i8 &&
- N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_218(N, X86::SHLD32mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (or:i16 (shl:i16 GR16:i16:$src2, (sub:i8 16:i8, CL:i8:$amt)), (srl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, CL:i8:$amt)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHRD16mrCL:isVoid addr:iPTR:$dst, GR16:i16:$src2)
+ // Pattern complexity = 61 cost = 1 size = 3
+ if (N10.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::SUB) {
+ SDValue N1010 = N101.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1010.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N1011 = N101.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SRL &&
+ N11.hasOneUse()) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::LOAD &&
+ N110.hasOneUse() &&
+ IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N) &&
+ (Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
+ SDValue Chain110 = N110.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N110.getNode()) &&
+ Predicate_loadi16(N110.getNode())) {
+ SDValue N1101 = N110.getNode()->getOperand(1);
+ SDValue CPTmpN1101_0;
+ SDValue CPTmpN1101_1;
+ SDValue CPTmpN1101_2;
+ SDValue CPTmpN1101_3;
+ SDValue CPTmpN1101_4;
+ if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N1011 == N111) {
+ SDValue N2 = N->getOperand(2);
+ if (N1101 == N2 &&
+ N1.getValueType() == MVT::i16 &&
+ N101.getValueType() == MVT::i8 &&
+ N111.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_218(N, X86::SHRD16mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
+ return Result;
}
}
}
@@ -32635,48 +32489,48 @@ SDNode *Select_ISD_STORE(SDNode *N) {
}
}
}
+ }
- // Pattern: (st:isVoid (or:i16 (shl:i16 GR16:i16:$src2, (sub:i8 16:i8, CL:i8:$amt)), (srl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, CL:i8:$amt)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHRD16mrCL:isVoid addr:iPTR:$dst, GR16:i16:$src2)
- // Pattern complexity = 61 cost = 1 size = 3
- if (N10.getNode()->getOpcode() == ISD::SHL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::SUB) {
- SDValue N1010 = N101.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1010.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N1011 = N101.getNode()->getOperand(1);
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SRL &&
- N11.hasOneUse()) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::LOAD &&
- N110.hasOneUse() &&
- IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N) &&
- (Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
- SDValue Chain110 = N110.getNode()->getOperand(0);
- if (Predicate_unindexedload(N110.getNode()) &&
- Predicate_loadi16(N110.getNode())) {
- SDValue N1101 = N110.getNode()->getOperand(1);
- SDValue CPTmpN1101_0;
- SDValue CPTmpN1101_1;
- SDValue CPTmpN1101_2;
- SDValue CPTmpN1101_3;
- SDValue CPTmpN1101_4;
- if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N1011 == N111) {
- SDValue N2 = N->getOperand(2);
- if (N1101 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N101.getValueType() == MVT::i8 &&
- N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_218(N, X86::SHRD16mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (or:i16 (srl:i16 GR16:i16:$src2, (sub:i8 16:i8, CL:i8:$amt)), (shl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, CL:i8:$amt)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHLD16mrCL:isVoid addr:iPTR:$dst, GR16:i16:$src2)
+ // Pattern complexity = 61 cost = 1 size = 3
+ if (N10.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::SUB) {
+ SDValue N1010 = N101.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1010.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(16)) {
+ SDValue N1011 = N101.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SHL &&
+ N11.hasOneUse()) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::LOAD &&
+ N110.hasOneUse() &&
+ IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N) &&
+ (Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
+ SDValue Chain110 = N110.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N110.getNode()) &&
+ Predicate_loadi16(N110.getNode())) {
+ SDValue N1101 = N110.getNode()->getOperand(1);
+ SDValue CPTmpN1101_0;
+ SDValue CPTmpN1101_1;
+ SDValue CPTmpN1101_2;
+ SDValue CPTmpN1101_3;
+ SDValue CPTmpN1101_4;
+ if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N1011 == N111) {
+ SDValue N2 = N->getOperand(2);
+ if (N1101 == N2 &&
+ N1.getValueType() == MVT::i16 &&
+ N101.getValueType() == MVT::i8 &&
+ N111.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_218(N, X86::SHLD16mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
+ return Result;
}
}
}
@@ -32686,50 +32540,45 @@ SDNode *Select_ISD_STORE(SDNode *N) {
}
}
}
+ }
+ }
- // Pattern: (st:isVoid (or:i16 (srl:i16 GR16:i16:$src2, (sub:i8 16:i8, CL:i8:$amt)), (shl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, CL:i8:$amt)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHLD16mrCL:isVoid addr:iPTR:$dst, GR16:i16:$src2)
- // Pattern complexity = 61 cost = 1 size = 3
- if (N10.getNode()->getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::SUB) {
- SDValue N1010 = N101.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1010.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N1011 = N101.getNode()->getOperand(1);
+ // Pattern: (st:isVoid (or:i32 (srl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i8):$amt1), (shl:i32 GR32:i32:$src2, (imm:i8):$amt2))<<P:Predicate_shrd>>, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHRD32mri8:isVoid addr:iPTR:$dst, GR32:i32:$src2, (imm:i8):$amt1)
+ // Pattern complexity = 60 cost = 1 size = 3
+ if (Predicate_shrd(N1.getNode())) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SRL &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::LOAD &&
+ N100.hasOneUse() &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N) &&
+ (Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
+ SDValue Chain100 = N100.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N100.getNode()) &&
+ Predicate_loadi32(N100.getNode())) {
+ SDValue N1001 = N100.getNode()->getOperand(1);
+ SDValue CPTmpN1001_0;
+ SDValue CPTmpN1001_1;
+ SDValue CPTmpN1001_2;
+ SDValue CPTmpN1001_3;
+ SDValue CPTmpN1001_4;
+ if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::Constant) {
SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SHL &&
- N11.hasOneUse()) {
+ if (N11.getNode()->getOpcode() == ISD::SHL) {
SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::LOAD &&
- N110.hasOneUse() &&
- IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N) &&
- (Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
- SDValue Chain110 = N110.getNode()->getOperand(0);
- if (Predicate_unindexedload(N110.getNode()) &&
- Predicate_loadi16(N110.getNode())) {
- SDValue N1101 = N110.getNode()->getOperand(1);
- SDValue CPTmpN1101_0;
- SDValue CPTmpN1101_1;
- SDValue CPTmpN1101_2;
- SDValue CPTmpN1101_3;
- SDValue CPTmpN1101_4;
- if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N1011 == N111) {
- SDValue N2 = N->getOperand(2);
- if (N1101 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N101.getValueType() == MVT::i8 &&
- N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_218(N, X86::SHLD16mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
- return Result;
- }
- }
- }
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N1001 == N2 &&
+ N1.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i8 &&
+ N111.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_204(N, X86::SHRD32mri8, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ return Result;
}
}
}
@@ -32738,44 +32587,44 @@ SDNode *Select_ISD_STORE(SDNode *N) {
}
}
}
+ }
- // Pattern: (st:isVoid (or:i32 (srl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i8):$amt1), (shl:i32 GR32:i32:$src2, (imm:i8):$amt2))<<P:Predicate_shrd>>, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHRD32mri8:isVoid addr:iPTR:$dst, GR32:i32:$src2, (imm:i8):$amt1)
- // Pattern complexity = 60 cost = 1 size = 3
- if (Predicate_shrd(N1.getNode())) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SRL &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::LOAD &&
- N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N) &&
- (Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
- SDValue Chain100 = N100.getNode()->getOperand(0);
- if (Predicate_unindexedload(N100.getNode()) &&
- Predicate_loadi32(N100.getNode())) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue CPTmpN1001_0;
- SDValue CPTmpN1001_1;
- SDValue CPTmpN1001_2;
- SDValue CPTmpN1001_3;
- SDValue CPTmpN1001_4;
- if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SHL) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N1001 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i8 &&
- N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_204(N, X86::SHRD32mri8, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
- return Result;
- }
+ // Pattern: (st:isVoid (or:i32 (shl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i8):$amt1), (srl:i32 GR32:i32:$src2, (imm:i8):$amt2))<<P:Predicate_shld>>, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHLD32mri8:isVoid addr:iPTR:$dst, GR32:i32:$src2, (imm:i8):$amt1)
+ // Pattern complexity = 60 cost = 1 size = 3
+ if (Predicate_shld(N1.getNode())) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SHL &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::LOAD &&
+ N100.hasOneUse() &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N) &&
+ (Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
+ SDValue Chain100 = N100.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N100.getNode()) &&
+ Predicate_loadi32(N100.getNode())) {
+ SDValue N1001 = N100.getNode()->getOperand(1);
+ SDValue CPTmpN1001_0;
+ SDValue CPTmpN1001_1;
+ SDValue CPTmpN1001_2;
+ SDValue CPTmpN1001_3;
+ SDValue CPTmpN1001_4;
+ if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N1001 == N2 &&
+ N1.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i8 &&
+ N111.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_204(N, X86::SHLD32mri8, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ return Result;
}
}
}
@@ -32784,44 +32633,44 @@ SDNode *Select_ISD_STORE(SDNode *N) {
}
}
}
+ }
- // Pattern: (st:isVoid (or:i32 (shl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i8):$amt1), (srl:i32 GR32:i32:$src2, (imm:i8):$amt2))<<P:Predicate_shld>>, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHLD32mri8:isVoid addr:iPTR:$dst, GR32:i32:$src2, (imm:i8):$amt1)
- // Pattern complexity = 60 cost = 1 size = 3
- if (Predicate_shld(N1.getNode())) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SHL &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::LOAD &&
- N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N) &&
- (Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
- SDValue Chain100 = N100.getNode()->getOperand(0);
- if (Predicate_unindexedload(N100.getNode()) &&
- Predicate_loadi32(N100.getNode())) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue CPTmpN1001_0;
- SDValue CPTmpN1001_1;
- SDValue CPTmpN1001_2;
- SDValue CPTmpN1001_3;
- SDValue CPTmpN1001_4;
- if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SRL) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N1001 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i8 &&
- N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_204(N, X86::SHLD32mri8, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
- return Result;
- }
+ // Pattern: (st:isVoid (or:i16 (srl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i8):$amt1), (shl:i16 GR16:i16:$src2, (imm:i8):$amt2))<<P:Predicate_shrd>>, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHRD16mri8:isVoid addr:iPTR:$dst, GR16:i16:$src2, (imm:i8):$amt1)
+ // Pattern complexity = 60 cost = 1 size = 3
+ if (Predicate_shrd(N1.getNode())) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SRL &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::LOAD &&
+ N100.hasOneUse() &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N) &&
+ (Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
+ SDValue Chain100 = N100.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N100.getNode()) &&
+ Predicate_loadi16(N100.getNode())) {
+ SDValue N1001 = N100.getNode()->getOperand(1);
+ SDValue CPTmpN1001_0;
+ SDValue CPTmpN1001_1;
+ SDValue CPTmpN1001_2;
+ SDValue CPTmpN1001_3;
+ SDValue CPTmpN1001_4;
+ if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N1001 == N2 &&
+ N1.getValueType() == MVT::i16 &&
+ N101.getValueType() == MVT::i8 &&
+ N111.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_204(N, X86::SHRD16mri8, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ return Result;
}
}
}
@@ -32830,44 +32679,44 @@ SDNode *Select_ISD_STORE(SDNode *N) {
}
}
}
+ }
- // Pattern: (st:isVoid (or:i16 (srl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i8):$amt1), (shl:i16 GR16:i16:$src2, (imm:i8):$amt2))<<P:Predicate_shrd>>, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHRD16mri8:isVoid addr:iPTR:$dst, GR16:i16:$src2, (imm:i8):$amt1)
- // Pattern complexity = 60 cost = 1 size = 3
- if (Predicate_shrd(N1.getNode())) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SRL &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::LOAD &&
- N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N) &&
- (Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
- SDValue Chain100 = N100.getNode()->getOperand(0);
- if (Predicate_unindexedload(N100.getNode()) &&
- Predicate_loadi16(N100.getNode())) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue CPTmpN1001_0;
- SDValue CPTmpN1001_1;
- SDValue CPTmpN1001_2;
- SDValue CPTmpN1001_3;
- SDValue CPTmpN1001_4;
- if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SHL) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N1001 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N101.getValueType() == MVT::i8 &&
- N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_204(N, X86::SHRD16mri8, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
- return Result;
- }
+ // Pattern: (st:isVoid (or:i16 (shl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i8):$amt1), (srl:i16 GR16:i16:$src2, (imm:i8):$amt2))<<P:Predicate_shld>>, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHLD16mri8:isVoid addr:iPTR:$dst, GR16:i16:$src2, (imm:i8):$amt1)
+ // Pattern complexity = 60 cost = 1 size = 3
+ if (Predicate_shld(N1.getNode())) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SHL &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::LOAD &&
+ N100.hasOneUse() &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N) &&
+ (Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
+ SDValue Chain100 = N100.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N100.getNode()) &&
+ Predicate_loadi16(N100.getNode())) {
+ SDValue N1001 = N100.getNode()->getOperand(1);
+ SDValue CPTmpN1001_0;
+ SDValue CPTmpN1001_1;
+ SDValue CPTmpN1001_2;
+ SDValue CPTmpN1001_3;
+ SDValue CPTmpN1001_4;
+ if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N1001 == N2 &&
+ N1.getValueType() == MVT::i16 &&
+ N101.getValueType() == MVT::i8 &&
+ N111.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_204(N, X86::SHLD16mri8, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ return Result;
}
}
}
@@ -32876,44 +32725,45 @@ SDNode *Select_ISD_STORE(SDNode *N) {
}
}
}
+ }
- // Pattern: (st:isVoid (or:i16 (shl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i8):$amt1), (srl:i16 GR16:i16:$src2, (imm:i8):$amt2))<<P:Predicate_shld>>, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHLD16mri8:isVoid addr:iPTR:$dst, GR16:i16:$src2, (imm:i8):$amt1)
- // Pattern complexity = 60 cost = 1 size = 3
- if (Predicate_shld(N1.getNode())) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SHL &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::LOAD &&
- N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N) &&
- (Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
- SDValue Chain100 = N100.getNode()->getOperand(0);
- if (Predicate_unindexedload(N100.getNode()) &&
- Predicate_loadi16(N100.getNode())) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue CPTmpN1001_0;
- SDValue CPTmpN1001_1;
- SDValue CPTmpN1001_2;
- SDValue CPTmpN1001_3;
- SDValue CPTmpN1001_4;
- if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SRL) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N1001 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N101.getValueType() == MVT::i8 &&
- N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_204(N, X86::SHLD16mri8, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
- return Result;
- }
+ // Pattern: (st:isVoid (or:i64 (srl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i8):$amt1), (shl:i64 GR64:i64:$src2, (imm:i8):$amt2))<<P:Predicate_shrd>>, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHRD64mri8:isVoid addr:iPTR:$dst, GR64:i64:$src2, (imm:i8):$amt1)
+ // Pattern complexity = 60 cost = 1 size = 3
+ if (Predicate_shrd(N1.getNode())) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SRL &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::LOAD &&
+ N100.hasOneUse() &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N) &&
+ (Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
+ SDValue Chain100 = N100.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N100.getNode()) &&
+ Predicate_load(N100.getNode()) &&
+ Predicate_loadi64(N100.getNode())) {
+ SDValue N1001 = N100.getNode()->getOperand(1);
+ SDValue CPTmpN1001_0;
+ SDValue CPTmpN1001_1;
+ SDValue CPTmpN1001_2;
+ SDValue CPTmpN1001_3;
+ SDValue CPTmpN1001_4;
+ if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N1001 == N2 &&
+ N1.getValueType() == MVT::i64 &&
+ N101.getValueType() == MVT::i8 &&
+ N111.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_204(N, X86::SHRD64mri8, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ return Result;
}
}
}
@@ -32922,45 +32772,45 @@ SDNode *Select_ISD_STORE(SDNode *N) {
}
}
}
+ }
- // Pattern: (st:isVoid (or:i64 (srl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i8):$amt1), (shl:i64 GR64:i64:$src2, (imm:i8):$amt2))<<P:Predicate_shrd>>, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHRD64mri8:isVoid addr:iPTR:$dst, GR64:i64:$src2, (imm:i8):$amt1)
- // Pattern complexity = 60 cost = 1 size = 3
- if (Predicate_shrd(N1.getNode())) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SRL &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::LOAD &&
- N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N) &&
- (Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
- SDValue Chain100 = N100.getNode()->getOperand(0);
- if (Predicate_unindexedload(N100.getNode()) &&
- Predicate_load(N100.getNode()) &&
- Predicate_loadi64(N100.getNode())) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue CPTmpN1001_0;
- SDValue CPTmpN1001_1;
- SDValue CPTmpN1001_2;
- SDValue CPTmpN1001_3;
- SDValue CPTmpN1001_4;
- if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SHL) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N1001 == N2 &&
- N1.getValueType() == MVT::i64 &&
- N101.getValueType() == MVT::i8 &&
- N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_204(N, X86::SHRD64mri8, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
- return Result;
- }
+ // Pattern: (st:isVoid (or:i64 (shl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i8):$amt1), (srl:i64 GR64:i64:$src2, (imm:i8):$amt2))<<P:Predicate_shld>>, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHLD64mri8:isVoid addr:iPTR:$dst, GR64:i64:$src2, (imm:i8):$amt1)
+ // Pattern complexity = 60 cost = 1 size = 3
+ if (Predicate_shld(N1.getNode())) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SHL &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::LOAD &&
+ N100.hasOneUse() &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N) &&
+ (Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
+ SDValue Chain100 = N100.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N100.getNode()) &&
+ Predicate_load(N100.getNode()) &&
+ Predicate_loadi64(N100.getNode())) {
+ SDValue N1001 = N100.getNode()->getOperand(1);
+ SDValue CPTmpN1001_0;
+ SDValue CPTmpN1001_1;
+ SDValue CPTmpN1001_2;
+ SDValue CPTmpN1001_3;
+ SDValue CPTmpN1001_4;
+ if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N1001 == N2 &&
+ N1.getValueType() == MVT::i64 &&
+ N101.getValueType() == MVT::i8 &&
+ N111.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_204(N, X86::SHLD64mri8, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ return Result;
}
}
}
@@ -32969,45 +32819,44 @@ SDNode *Select_ISD_STORE(SDNode *N) {
}
}
}
+ }
- // Pattern: (st:isVoid (or:i64 (shl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i8):$amt1), (srl:i64 GR64:i64:$src2, (imm:i8):$amt2))<<P:Predicate_shld>>, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHLD64mri8:isVoid addr:iPTR:$dst, GR64:i64:$src2, (imm:i8):$amt1)
- // Pattern complexity = 60 cost = 1 size = 3
- if (Predicate_shld(N1.getNode())) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SHL &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::LOAD &&
- N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N) &&
- (Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
- SDValue Chain100 = N100.getNode()->getOperand(0);
- if (Predicate_unindexedload(N100.getNode()) &&
- Predicate_load(N100.getNode()) &&
- Predicate_loadi64(N100.getNode())) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue CPTmpN1001_0;
- SDValue CPTmpN1001_1;
- SDValue CPTmpN1001_2;
- SDValue CPTmpN1001_3;
- SDValue CPTmpN1001_4;
- if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SRL) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N1001 == N2 &&
- N1.getValueType() == MVT::i64 &&
- N101.getValueType() == MVT::i8 &&
- N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_204(N, X86::SHLD64mri8, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
- return Result;
- }
+ // Pattern: (st:isVoid (or:i32 (shl:i32 GR32:i32:$src2, (imm:i8):$amt2), (srl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i8):$amt1))<<P:Predicate_shrd>>, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHRD32mri8:isVoid addr:iPTR:$dst, GR32:i32:$src2, (imm:i8):$amt1)
+ // Pattern complexity = 60 cost = 1 size = 3
+ if (Predicate_shrd(N1.getNode())) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SRL &&
+ N11.hasOneUse()) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::LOAD &&
+ N110.hasOneUse() &&
+ IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N) &&
+ (Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
+ SDValue Chain110 = N110.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N110.getNode()) &&
+ Predicate_loadi32(N110.getNode())) {
+ SDValue N1101 = N110.getNode()->getOperand(1);
+ SDValue CPTmpN1101_0;
+ SDValue CPTmpN1101_1;
+ SDValue CPTmpN1101_2;
+ SDValue CPTmpN1101_3;
+ SDValue CPTmpN1101_4;
+ if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N1101 == N2 &&
+ N1.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i8 &&
+ N111.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_220(N, X86::SHRD32mri8, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
+ return Result;
}
}
}
@@ -33016,44 +32865,44 @@ SDNode *Select_ISD_STORE(SDNode *N) {
}
}
}
+ }
- // Pattern: (st:isVoid (or:i32 (shl:i32 GR32:i32:$src2, (imm:i8):$amt2), (srl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i8):$amt1))<<P:Predicate_shrd>>, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHRD32mri8:isVoid addr:iPTR:$dst, GR32:i32:$src2, (imm:i8):$amt1)
- // Pattern complexity = 60 cost = 1 size = 3
- if (Predicate_shrd(N1.getNode())) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SHL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SRL &&
- N11.hasOneUse()) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::LOAD &&
- N110.hasOneUse() &&
- IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N) &&
- (Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
- SDValue Chain110 = N110.getNode()->getOperand(0);
- if (Predicate_unindexedload(N110.getNode()) &&
- Predicate_loadi32(N110.getNode())) {
- SDValue N1101 = N110.getNode()->getOperand(1);
- SDValue CPTmpN1101_0;
- SDValue CPTmpN1101_1;
- SDValue CPTmpN1101_2;
- SDValue CPTmpN1101_3;
- SDValue CPTmpN1101_4;
- if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N1101 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i8 &&
- N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_220(N, X86::SHRD32mri8, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (or:i32 (srl:i32 GR32:i32:$src2, (imm:i8):$amt2), (shl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i8):$amt1))<<P:Predicate_shld>>, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHLD32mri8:isVoid addr:iPTR:$dst, GR32:i32:$src2, (imm:i8):$amt1)
+ // Pattern complexity = 60 cost = 1 size = 3
+ if (Predicate_shld(N1.getNode())) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SHL &&
+ N11.hasOneUse()) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::LOAD &&
+ N110.hasOneUse() &&
+ IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N) &&
+ (Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
+ SDValue Chain110 = N110.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N110.getNode()) &&
+ Predicate_loadi32(N110.getNode())) {
+ SDValue N1101 = N110.getNode()->getOperand(1);
+ SDValue CPTmpN1101_0;
+ SDValue CPTmpN1101_1;
+ SDValue CPTmpN1101_2;
+ SDValue CPTmpN1101_3;
+ SDValue CPTmpN1101_4;
+ if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N1101 == N2 &&
+ N1.getValueType() == MVT::i32 &&
+ N101.getValueType() == MVT::i8 &&
+ N111.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_220(N, X86::SHLD32mri8, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
+ return Result;
}
}
}
@@ -33062,44 +32911,44 @@ SDNode *Select_ISD_STORE(SDNode *N) {
}
}
}
+ }
- // Pattern: (st:isVoid (or:i32 (srl:i32 GR32:i32:$src2, (imm:i8):$amt2), (shl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i8):$amt1))<<P:Predicate_shld>>, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHLD32mri8:isVoid addr:iPTR:$dst, GR32:i32:$src2, (imm:i8):$amt1)
- // Pattern complexity = 60 cost = 1 size = 3
- if (Predicate_shld(N1.getNode())) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SHL &&
- N11.hasOneUse()) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::LOAD &&
- N110.hasOneUse() &&
- IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N) &&
- (Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
- SDValue Chain110 = N110.getNode()->getOperand(0);
- if (Predicate_unindexedload(N110.getNode()) &&
- Predicate_loadi32(N110.getNode())) {
- SDValue N1101 = N110.getNode()->getOperand(1);
- SDValue CPTmpN1101_0;
- SDValue CPTmpN1101_1;
- SDValue CPTmpN1101_2;
- SDValue CPTmpN1101_3;
- SDValue CPTmpN1101_4;
- if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N1101 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N101.getValueType() == MVT::i8 &&
- N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_220(N, X86::SHLD32mri8, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (or:i16 (shl:i16 GR16:i16:$src2, (imm:i8):$amt2), (srl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i8):$amt1))<<P:Predicate_shrd>>, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHRD16mri8:isVoid addr:iPTR:$dst, GR16:i16:$src2, (imm:i8):$amt1)
+ // Pattern complexity = 60 cost = 1 size = 3
+ if (Predicate_shrd(N1.getNode())) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SRL &&
+ N11.hasOneUse()) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::LOAD &&
+ N110.hasOneUse() &&
+ IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N) &&
+ (Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
+ SDValue Chain110 = N110.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N110.getNode()) &&
+ Predicate_loadi16(N110.getNode())) {
+ SDValue N1101 = N110.getNode()->getOperand(1);
+ SDValue CPTmpN1101_0;
+ SDValue CPTmpN1101_1;
+ SDValue CPTmpN1101_2;
+ SDValue CPTmpN1101_3;
+ SDValue CPTmpN1101_4;
+ if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N1101 == N2 &&
+ N1.getValueType() == MVT::i16 &&
+ N101.getValueType() == MVT::i8 &&
+ N111.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_220(N, X86::SHRD16mri8, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
+ return Result;
}
}
}
@@ -33108,44 +32957,44 @@ SDNode *Select_ISD_STORE(SDNode *N) {
}
}
}
+ }
- // Pattern: (st:isVoid (or:i16 (shl:i16 GR16:i16:$src2, (imm:i8):$amt2), (srl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i8):$amt1))<<P:Predicate_shrd>>, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHRD16mri8:isVoid addr:iPTR:$dst, GR16:i16:$src2, (imm:i8):$amt1)
- // Pattern complexity = 60 cost = 1 size = 3
- if (Predicate_shrd(N1.getNode())) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SHL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SRL &&
- N11.hasOneUse()) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::LOAD &&
- N110.hasOneUse() &&
- IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N) &&
- (Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
- SDValue Chain110 = N110.getNode()->getOperand(0);
- if (Predicate_unindexedload(N110.getNode()) &&
- Predicate_loadi16(N110.getNode())) {
- SDValue N1101 = N110.getNode()->getOperand(1);
- SDValue CPTmpN1101_0;
- SDValue CPTmpN1101_1;
- SDValue CPTmpN1101_2;
- SDValue CPTmpN1101_3;
- SDValue CPTmpN1101_4;
- if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N1101 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N101.getValueType() == MVT::i8 &&
- N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_220(N, X86::SHRD16mri8, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (or:i16 (srl:i16 GR16:i16:$src2, (imm:i8):$amt2), (shl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i8):$amt1))<<P:Predicate_shld>>, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHLD16mri8:isVoid addr:iPTR:$dst, GR16:i16:$src2, (imm:i8):$amt1)
+ // Pattern complexity = 60 cost = 1 size = 3
+ if (Predicate_shld(N1.getNode())) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SHL &&
+ N11.hasOneUse()) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::LOAD &&
+ N110.hasOneUse() &&
+ IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N) &&
+ (Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
+ SDValue Chain110 = N110.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N110.getNode()) &&
+ Predicate_loadi16(N110.getNode())) {
+ SDValue N1101 = N110.getNode()->getOperand(1);
+ SDValue CPTmpN1101_0;
+ SDValue CPTmpN1101_1;
+ SDValue CPTmpN1101_2;
+ SDValue CPTmpN1101_3;
+ SDValue CPTmpN1101_4;
+ if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N1101 == N2 &&
+ N1.getValueType() == MVT::i16 &&
+ N101.getValueType() == MVT::i8 &&
+ N111.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_220(N, X86::SHLD16mri8, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
+ return Result;
}
}
}
@@ -33154,44 +33003,45 @@ SDNode *Select_ISD_STORE(SDNode *N) {
}
}
}
+ }
- // Pattern: (st:isVoid (or:i16 (srl:i16 GR16:i16:$src2, (imm:i8):$amt2), (shl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i8):$amt1))<<P:Predicate_shld>>, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHLD16mri8:isVoid addr:iPTR:$dst, GR16:i16:$src2, (imm:i8):$amt1)
- // Pattern complexity = 60 cost = 1 size = 3
- if (Predicate_shld(N1.getNode())) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SHL &&
- N11.hasOneUse()) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::LOAD &&
- N110.hasOneUse() &&
- IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N) &&
- (Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
- SDValue Chain110 = N110.getNode()->getOperand(0);
- if (Predicate_unindexedload(N110.getNode()) &&
- Predicate_loadi16(N110.getNode())) {
- SDValue N1101 = N110.getNode()->getOperand(1);
- SDValue CPTmpN1101_0;
- SDValue CPTmpN1101_1;
- SDValue CPTmpN1101_2;
- SDValue CPTmpN1101_3;
- SDValue CPTmpN1101_4;
- if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N1101 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N101.getValueType() == MVT::i8 &&
- N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_220(N, X86::SHLD16mri8, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (or:i64 (shl:i64 GR64:i64:$src2, (imm:i8):$amt2), (srl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i8):$amt1))<<P:Predicate_shrd>>, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHRD64mri8:isVoid addr:iPTR:$dst, GR64:i64:$src2, (imm:i8):$amt1)
+ // Pattern complexity = 60 cost = 1 size = 3
+ if (Predicate_shrd(N1.getNode())) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SRL &&
+ N11.hasOneUse()) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::LOAD &&
+ N110.hasOneUse() &&
+ IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N) &&
+ (Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
+ SDValue Chain110 = N110.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N110.getNode()) &&
+ Predicate_load(N110.getNode()) &&
+ Predicate_loadi64(N110.getNode())) {
+ SDValue N1101 = N110.getNode()->getOperand(1);
+ SDValue CPTmpN1101_0;
+ SDValue CPTmpN1101_1;
+ SDValue CPTmpN1101_2;
+ SDValue CPTmpN1101_3;
+ SDValue CPTmpN1101_4;
+ if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N1101 == N2 &&
+ N1.getValueType() == MVT::i64 &&
+ N101.getValueType() == MVT::i8 &&
+ N111.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_220(N, X86::SHRD64mri8, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
+ return Result;
}
}
}
@@ -33200,45 +33050,45 @@ SDNode *Select_ISD_STORE(SDNode *N) {
}
}
}
+ }
- // Pattern: (st:isVoid (or:i64 (shl:i64 GR64:i64:$src2, (imm:i8):$amt2), (srl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i8):$amt1))<<P:Predicate_shrd>>, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHRD64mri8:isVoid addr:iPTR:$dst, GR64:i64:$src2, (imm:i8):$amt1)
- // Pattern complexity = 60 cost = 1 size = 3
- if (Predicate_shrd(N1.getNode())) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SHL) {
- SDValue N100 = N10.getNode()->getOperand(0);
- SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SRL &&
- N11.hasOneUse()) {
- SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::LOAD &&
- N110.hasOneUse() &&
- IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N) &&
- (Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
- SDValue Chain110 = N110.getNode()->getOperand(0);
- if (Predicate_unindexedload(N110.getNode()) &&
- Predicate_load(N110.getNode()) &&
- Predicate_loadi64(N110.getNode())) {
- SDValue N1101 = N110.getNode()->getOperand(1);
- SDValue CPTmpN1101_0;
- SDValue CPTmpN1101_1;
- SDValue CPTmpN1101_2;
- SDValue CPTmpN1101_3;
- SDValue CPTmpN1101_4;
- if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N1101 == N2 &&
- N1.getValueType() == MVT::i64 &&
- N101.getValueType() == MVT::i8 &&
- N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_220(N, X86::SHRD64mri8, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (or:i64 (srl:i64 GR64:i64:$src2, (imm:i8):$amt2), (shl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i8):$amt1))<<P:Predicate_shld>>, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHLD64mri8:isVoid addr:iPTR:$dst, GR64:i64:$src2, (imm:i8):$amt1)
+ // Pattern complexity = 60 cost = 1 size = 3
+ if (Predicate_shld(N1.getNode())) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SHL &&
+ N11.hasOneUse()) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::LOAD &&
+ N110.hasOneUse() &&
+ IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N) &&
+ (Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
+ SDValue Chain110 = N110.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N110.getNode()) &&
+ Predicate_load(N110.getNode()) &&
+ Predicate_loadi64(N110.getNode())) {
+ SDValue N1101 = N110.getNode()->getOperand(1);
+ SDValue CPTmpN1101_0;
+ SDValue CPTmpN1101_1;
+ SDValue CPTmpN1101_2;
+ SDValue CPTmpN1101_3;
+ SDValue CPTmpN1101_4;
+ if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N1101 == N2 &&
+ N1.getValueType() == MVT::i64 &&
+ N101.getValueType() == MVT::i8 &&
+ N111.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_220(N, X86::SHLD64mri8, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
+ return Result;
}
}
}
@@ -33247,253 +33097,103 @@ SDNode *Select_ISD_STORE(SDNode *N) {
}
}
}
+ }
+ }
+ if (N1.getNode()->getOpcode() == ISD::SHL &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
- // Pattern: (st:isVoid (or:i64 (srl:i64 GR64:i64:$src2, (imm:i8):$amt2), (shl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i8):$amt1))<<P:Predicate_shld>>, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHLD64mri8:isVoid addr:iPTR:$dst, GR64:i64:$src2, (imm:i8):$amt1)
- // Pattern complexity = 60 cost = 1 size = 3
- if (Predicate_shld(N1.getNode())) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getNode()->getOperand(0);
+ // Pattern: (st:isVoid (shl:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (and:i8 CL:i8:$amt, 31:i8)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHL8mCL:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 55 cost = 1 size = 3
+ if (Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
SDValue N101 = N10.getNode()->getOperand(1);
- if (N101.getNode()->getOpcode() == ISD::Constant) {
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::SHL &&
- N11.hasOneUse()) {
+ if (N11.getNode()->getOpcode() == ISD::AND) {
SDValue N110 = N11.getNode()->getOperand(0);
- if (N110.getNode()->getOpcode() == ISD::LOAD &&
- N110.hasOneUse() &&
- IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N) &&
- (Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
- SDValue Chain110 = N110.getNode()->getOperand(0);
- if (Predicate_unindexedload(N110.getNode()) &&
- Predicate_load(N110.getNode()) &&
- Predicate_loadi64(N110.getNode())) {
- SDValue N1101 = N110.getNode()->getOperand(1);
- SDValue CPTmpN1101_0;
- SDValue CPTmpN1101_1;
- SDValue CPTmpN1101_2;
- SDValue CPTmpN1101_3;
- SDValue CPTmpN1101_4;
- if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
- SDValue N111 = N11.getNode()->getOperand(1);
- if (N111.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N1101 == N2 &&
- N1.getValueType() == MVT::i64 &&
- N101.getValueType() == MVT::i8 &&
- N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_220(N, X86::SHLD64mri8, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
- return Result;
- }
- }
- }
+ SDValue N111 = N11.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111.getNode());
+ if (Tmp0 &&
+ CheckAndMask(N110, Tmp0, INT64_C(31))) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i8 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_201(N, X86::SHL8mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
}
- }
- }
- if (N1.getNode()->getOpcode() == ISD::SHL &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (shl:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (and:i8 CL:i8:$amt, 31:i8)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHL8mCL:isVoid addr:iPTR:$dst)
- // Pattern complexity = 55 cost = 1 size = 3
- if (Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::AND) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111.getNode());
- if (Tmp0 &&
- CheckAndMask(N110, Tmp0, INT64_C(31))) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_201(N, X86::SHL8mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- // Pattern: (st:isVoid (shl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (and:i8 CL:i8:$amt, 31:i8)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHL16mCL:isVoid addr:iPTR:$dst)
- // Pattern complexity = 55 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::AND) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111.getNode());
- if (Tmp0 &&
- CheckAndMask(N110, Tmp0, INT64_C(31))) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_201(N, X86::SHL16mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (shl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (and:i8 CL:i8:$amt, 31:i8)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHL32mCL:isVoid addr:iPTR:$dst)
- // Pattern complexity = 55 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::AND) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111.getNode());
- if (Tmp0 &&
- CheckAndMask(N110, Tmp0, INT64_C(31))) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_201(N, X86::SHL32mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (shl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (and:i8 CL:i8:$amt, 31:i8)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHL16mCL:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 55 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::AND) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111.getNode());
+ if (Tmp0 &&
+ CheckAndMask(N110, Tmp0, INT64_C(31))) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_201(N, X86::SHL16mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
}
- }
- }
- if (N1.getNode()->getOpcode() == ISD::SRL &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (srl:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (and:i8 CL:i8:$amt, 31:i8)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHR8mCL:isVoid addr:iPTR:$dst)
- // Pattern complexity = 55 cost = 1 size = 3
- if (Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::AND) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111.getNode());
- if (Tmp0 &&
- CheckAndMask(N110, Tmp0, INT64_C(31))) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_201(N, X86::SHR8mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- // Pattern: (st:isVoid (srl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (and:i8 CL:i8:$amt, 31:i8)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHR16mCL:isVoid addr:iPTR:$dst)
- // Pattern complexity = 55 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::AND) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111.getNode());
- if (Tmp0 &&
- CheckAndMask(N110, Tmp0, INT64_C(31))) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_201(N, X86::SHR16mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (srl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (and:i8 CL:i8:$amt, 31:i8)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHR32mCL:isVoid addr:iPTR:$dst)
- // Pattern complexity = 55 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::AND) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111.getNode());
- if (Tmp0 &&
- CheckAndMask(N110, Tmp0, INT64_C(31))) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_201(N, X86::SHR32mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (shl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (and:i8 CL:i8:$amt, 31:i8)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHL32mCL:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 55 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::AND) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111.getNode());
+ if (Tmp0 &&
+ CheckAndMask(N110, Tmp0, INT64_C(31))) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_201(N, X86::SHL32mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
@@ -33501,124 +33201,52 @@ SDNode *Select_ISD_STORE(SDNode *N) {
}
}
}
- if (N1.getNode()->getOpcode() == ISD::SRA &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (sra:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (and:i8 CL:i8:$amt, 31:i8)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SAR8mCL:isVoid addr:iPTR:$dst)
- // Pattern complexity = 55 cost = 1 size = 3
- if (Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::AND) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111.getNode());
- if (Tmp0 &&
- CheckAndMask(N110, Tmp0, INT64_C(31))) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_201(N, X86::SAR8mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (sra:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (and:i8 CL:i8:$amt, 31:i8)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SAR16mCL:isVoid addr:iPTR:$dst)
- // Pattern complexity = 55 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::AND) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111.getNode());
- if (Tmp0 &&
- CheckAndMask(N110, Tmp0, INT64_C(31))) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_201(N, X86::SAR16mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
+ }
+ if (N1.getNode()->getOpcode() == ISD::SRL &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
- // Pattern: (st:isVoid (sra:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (and:i8 CL:i8:$amt, 31:i8)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SAR32mCL:isVoid addr:iPTR:$dst)
- // Pattern complexity = 55 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::AND) {
- SDValue N110 = N11.getNode()->getOperand(0);
- SDValue N111 = N11.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111.getNode());
- if (Tmp0 &&
- CheckAndMask(N110, Tmp0, INT64_C(31))) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_201(N, X86::SAR32mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (srl:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (and:i8 CL:i8:$amt, 31:i8)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHR8mCL:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 55 cost = 1 size = 3
+ if (Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::AND) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111.getNode());
+ if (Tmp0 &&
+ CheckAndMask(N110, Tmp0, INT64_C(31))) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i8 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_201(N, X86::SHR8mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
}
- }
- }
- // Pattern: (st:isVoid (shl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (and:i8 CL:i8:$amt, 63:i8)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHL64mCL:isVoid addr:iPTR:$dst)
- // Pattern complexity = 55 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::SHL &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi64(N10.getNode())) {
+ // Pattern: (st:isVoid (srl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (and:i8 CL:i8:$amt, 31:i8)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHR16mCL:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 55 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
@@ -33632,35 +33260,23 @@ SDNode *Select_ISD_STORE(SDNode *N) {
SDValue N111 = N11.getNode()->getOperand(1);
ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111.getNode());
if (Tmp0 &&
- CheckAndMask(N110, Tmp0, INT64_C(63))) {
+ CheckAndMask(N110, Tmp0, INT64_C(31))) {
SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
- N1.getValueType() == MVT::i64 &&
+ N1.getValueType() == MVT::i16 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_201(N, X86::SHL64mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_201(N, X86::SHR16mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
}
}
}
- }
- }
- // Pattern: (st:isVoid (srl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (and:i8 CL:i8:$amt, 63:i8)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHR64mCL:isVoid addr:iPTR:$dst)
- // Pattern complexity = 55 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::SRL &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi64(N10.getNode())) {
+ // Pattern: (st:isVoid (srl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (and:i8 CL:i8:$amt, 31:i8)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHR32mCL:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 55 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
@@ -33674,12 +33290,12 @@ SDNode *Select_ISD_STORE(SDNode *N) {
SDValue N111 = N11.getNode()->getOperand(1);
ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111.getNode());
if (Tmp0 &&
- CheckAndMask(N110, Tmp0, INT64_C(63))) {
+ CheckAndMask(N110, Tmp0, INT64_C(31))) {
SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
- N1.getValueType() == MVT::i64 &&
+ N1.getValueType() == MVT::i32 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_201(N, X86::SHR64mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_201(N, X86::SHR32mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -33688,21 +33304,22 @@ SDNode *Select_ISD_STORE(SDNode *N) {
}
}
}
+ }
+ if (N1.getNode()->getOpcode() == ISD::SRA &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
- // Pattern: (st:isVoid (sra:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (and:i8 CL:i8:$amt, 63:i8)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SAR64mCL:isVoid addr:iPTR:$dst)
- // Pattern complexity = 55 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::SRA &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi64(N10.getNode())) {
+ // Pattern: (st:isVoid (sra:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (and:i8 CL:i8:$amt, 31:i8)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SAR8mCL:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 55 cost = 1 size = 3
+ if (Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
@@ -33716,115 +33333,53 @@ SDNode *Select_ISD_STORE(SDNode *N) {
SDValue N111 = N11.getNode()->getOperand(1);
ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111.getNode());
if (Tmp0 &&
- CheckAndMask(N110, Tmp0, INT64_C(63))) {
+ CheckAndMask(N110, Tmp0, INT64_C(31))) {
SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
- N1.getValueType() == MVT::i64 &&
+ N1.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_201(N, X86::SAR64mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_201(N, X86::SAR8mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
}
}
}
- }
- }
- if (N1.getNode()->getOpcode() == ISD::SUB &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::LOAD &&
- N11.hasOneUse() &&
- IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N11.getNode() || IsChainCompatible(Chain.getNode(), N11.getNode()))) {
- SDValue Chain11 = N11.getNode()->getOperand(0);
- if (Predicate_unindexedload(N11.getNode())) {
-
- // Pattern: (st:isVoid (sub:i8 0:i8, (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (NEG8m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 2
- if (Predicate_load(N11.getNode()) &&
- Predicate_loadi8(N11.getNode())) {
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue CPTmpN111_0;
- SDValue CPTmpN111_1;
- SDValue CPTmpN111_2;
- SDValue CPTmpN111_3;
- SDValue CPTmpN111_4;
- if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
- SDValue N2 = N->getOperand(2);
- if (N111 == N2 &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_173(N, X86::NEG8m, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
- return Result;
- }
- }
- }
-
- // Pattern: (st:isVoid (sub:i16 0:i16, (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (NEG16m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 2
- if (Predicate_loadi16(N11.getNode())) {
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue CPTmpN111_0;
- SDValue CPTmpN111_1;
- SDValue CPTmpN111_2;
- SDValue CPTmpN111_3;
- SDValue CPTmpN111_4;
- if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
- SDValue N2 = N->getOperand(2);
- if (N111 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_173(N, X86::NEG16m, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
- return Result;
- }
- }
- }
- // Pattern: (st:isVoid (sub:i32 0:i32, (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (NEG32m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 2
- if (Predicate_loadi32(N11.getNode())) {
- SDValue N111 = N11.getNode()->getOperand(1);
- SDValue CPTmpN111_0;
- SDValue CPTmpN111_1;
- SDValue CPTmpN111_2;
- SDValue CPTmpN111_3;
- SDValue CPTmpN111_4;
- if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
- SDValue N2 = N->getOperand(2);
- if (N111 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_173(N, X86::NEG32m, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
- return Result;
- }
+ // Pattern: (st:isVoid (sra:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (and:i8 CL:i8:$amt, 31:i8)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SAR16mCL:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 55 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::AND) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111.getNode());
+ if (Tmp0 &&
+ CheckAndMask(N110, Tmp0, INT64_C(31))) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_201(N, X86::SAR16mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
}
- }
- }
- // Pattern: (st:isVoid (add:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (INC8m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 2
- if (N1.getNode()->getOpcode() == ISD::ADD &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
+ // Pattern: (st:isVoid (sra:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (and:i8 CL:i8:$amt, 31:i8)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SAR32mCL:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 55 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
@@ -33833,14 +33388,17 @@ SDNode *Select_ISD_STORE(SDNode *N) {
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1)) {
+ if (N11.getNode()->getOpcode() == ISD::AND) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111.getNode());
+ if (Tmp0 &&
+ CheckAndMask(N110, Tmp0, INT64_C(31))) {
SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_175(N, X86::INC8m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ N1.getValueType() == MVT::i32 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_201(N, X86::SAR32mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -33850,72 +33408,83 @@ SDNode *Select_ISD_STORE(SDNode *N) {
}
}
}
- }
- if ((!Subtarget->is64Bit())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedstore(N) &&
- Predicate_store(N)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::ADD &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (add:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 1:i16), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (INC16m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 2
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_175(N, X86::INC16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
+
+ // Pattern: (st:isVoid (shl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (and:i8 CL:i8:$amt, 63:i8)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHL64mCL:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 55 cost = 1 size = 3
+ if (N1.getNode()->getOpcode() == ISD::SHL &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::AND) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111.getNode());
+ if (Tmp0 &&
+ CheckAndMask(N110, Tmp0, INT64_C(63))) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_201(N, X86::SHL64mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
+ }
+ }
+ }
+ }
- // Pattern: (st:isVoid (add:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 1:i32), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (INC32m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 2
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_175(N, X86::INC32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
+ // Pattern: (st:isVoid (srl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (and:i8 CL:i8:$amt, 63:i8)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHR64mCL:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 55 cost = 1 size = 3
+ if (N1.getNode()->getOpcode() == ISD::SRL &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::AND) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111.getNode());
+ if (Tmp0 &&
+ CheckAndMask(N110, Tmp0, INT64_C(63))) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_201(N, X86::SHR64mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
@@ -33923,45 +33492,41 @@ SDNode *Select_ISD_STORE(SDNode *N) {
}
}
}
- }
- // Pattern: (st:isVoid (add:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, -1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (DEC8m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 2
- {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedstore(N) &&
- Predicate_store(N)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::ADD &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(-1)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_175(N, X86::DEC8m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (sra:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (and:i8 CL:i8:$amt, 63:i8)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SAR64mCL:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 55 cost = 1 size = 3
+ if (N1.getNode()->getOpcode() == ISD::SRA &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::AND) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111.getNode());
+ if (Tmp0 &&
+ CheckAndMask(N110, Tmp0, INT64_C(63))) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_201(N, X86::SAR64mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
@@ -33969,105 +33534,66 @@ SDNode *Select_ISD_STORE(SDNode *N) {
}
}
}
- }
- if ((!Subtarget->is64Bit())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedstore(N) &&
- Predicate_store(N)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::ADD &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (add:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, -1:i16), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (DEC16m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 2
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(-1)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_175(N, X86::DEC16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ if (N1.getNode()->getOpcode() == ISD::SUB &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::LOAD &&
+ N11.hasOneUse() &&
+ IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N11.getNode() || IsChainCompatible(Chain.getNode(), N11.getNode()))) {
+ SDValue Chain11 = N11.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N11.getNode())) {
+
+ // Pattern: (st:isVoid (sub:i8 0:i8, (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (NEG8m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 2
+ if (Predicate_load(N11.getNode()) &&
+ Predicate_loadi8(N11.getNode())) {
+ SDValue N111 = N11.getNode()->getOperand(1);
+ SDValue CPTmpN111_0;
+ SDValue CPTmpN111_1;
+ SDValue CPTmpN111_2;
+ SDValue CPTmpN111_3;
+ SDValue CPTmpN111_4;
+ if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N111 == N2 &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_173(N, X86::NEG8m, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ return Result;
}
}
}
- }
- // Pattern: (st:isVoid (add:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, -1:i32), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (DEC32m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 2
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(-1)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_175(N, X86::DEC32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (sub:i16 0:i16, (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (NEG16m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 2
+ if (Predicate_loadi16(N11.getNode())) {
+ SDValue N111 = N11.getNode()->getOperand(1);
+ SDValue CPTmpN111_0;
+ SDValue CPTmpN111_1;
+ SDValue CPTmpN111_2;
+ SDValue CPTmpN111_3;
+ SDValue CPTmpN111_4;
+ if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N111 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_173(N, X86::NEG16m, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ return Result;
}
}
}
- }
- }
- }
- }
- }
- }
- {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedstore(N) &&
- Predicate_store(N)) {
- SDValue N1 = N->getOperand(1);
- // Pattern: (st:isVoid (sub:i64 0:i64, (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (NEG64m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 2
- if (N1.getNode()->getOpcode() == ISD::SUB &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::LOAD &&
- N11.hasOneUse() &&
- IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N11.getNode() || IsChainCompatible(Chain.getNode(), N11.getNode()))) {
- SDValue Chain11 = N11.getNode()->getOperand(0);
- if (Predicate_unindexedload(N11.getNode()) &&
- Predicate_load(N11.getNode()) &&
- Predicate_loadi64(N11.getNode())) {
+ // Pattern: (st:isVoid (sub:i32 0:i32, (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (NEG32m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 2
+ if (Predicate_loadi32(N11.getNode())) {
SDValue N111 = N11.getNode()->getOperand(1);
SDValue CPTmpN111_0;
SDValue CPTmpN111_1;
@@ -34077,8 +33603,8 @@ SDNode *Select_ISD_STORE(SDNode *N) {
if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
SDValue N2 = N->getOperand(2);
if (N111 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_173(N, X86::NEG64m, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_173(N, X86::NEG32m, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
return Result;
}
}
@@ -34087,17 +33613,67 @@ SDNode *Select_ISD_STORE(SDNode *N) {
}
}
}
- if (N1.getNode()->getOpcode() == ISD::ADD &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi64(N10.getNode())) {
+ }
+
+ // Pattern: (st:isVoid (add:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (INC8m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 2
+ if (N1.getNode()->getOpcode() == ISD::ADD &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(1)) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_175(N, X86::INC8m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((!Subtarget->is64Bit())) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedstore(N) &&
+ Predicate_store(N)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::ADD &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
+
+ // Pattern: (st:isVoid (add:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 1:i16), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (INC16m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 2
+ if (Predicate_loadi16(N10.getNode())) {
SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
@@ -34109,27 +33685,38 @@ SDNode *Select_ISD_STORE(SDNode *N) {
ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (st:isVoid (add:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 1:i64), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (INC64m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 2
if (CN1 == INT64_C(1)) {
SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_175(N, X86::INC64m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_175(N, X86::INC16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
+ }
+ }
+ }
- // Pattern: (st:isVoid (add:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, -1:i64), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (DEC64m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 2
- if (CN1 == INT64_C(-1)) {
+ // Pattern: (st:isVoid (add:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 1:i32), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (INC32m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 2
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(1)) {
SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_175(N, X86::DEC64m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_175(N, X86::INC32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -34140,125 +33727,44 @@ SDNode *Select_ISD_STORE(SDNode *N) {
}
}
}
- if ((Subtarget->is64Bit())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedstore(N) &&
- Predicate_store(N)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::ADD &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (add:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 1:i16), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (INC64_16m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 2
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_175(N, X86::INC64_16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (add:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 1:i32), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (INC64_32m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 2
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_175(N, X86::INC64_32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (add:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, -1:i16), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (DEC64_16m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 2
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(-1)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_175(N, X86::DEC64_16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
+ }
- // Pattern: (st:isVoid (add:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, -1:i32), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (DEC64_32m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 2
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(-1)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_175(N, X86::DEC64_32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
+ // Pattern: (st:isVoid (add:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, -1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (DEC8m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 2
+ {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedstore(N) &&
+ Predicate_store(N)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::ADD &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(-1)) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_175(N, X86::DEC8m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
@@ -34267,101 +33773,70 @@ SDNode *Select_ISD_STORE(SDNode *N) {
}
}
}
- {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedstore(N) &&
- Predicate_store(N)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SHL &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (shl:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHL8m1:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 3
- if (Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_174(N, X86::SHL8m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
+ }
+ if ((!Subtarget->is64Bit())) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedstore(N) &&
+ Predicate_store(N)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::ADD &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
- // Pattern: (st:isVoid (shl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHL16m1:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_174(N, X86::SHL16m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (add:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, -1:i16), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (DEC16m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 2
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(-1)) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_175(N, X86::DEC16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (st:isVoid (shl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHL32m1:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_174(N, X86::SHL32m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (add:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, -1:i32), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (DEC32m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 2
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(-1)) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_175(N, X86::DEC32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
@@ -34369,387 +33844,223 @@ SDNode *Select_ISD_STORE(SDNode *N) {
}
}
}
- if (N1.getNode()->getOpcode() == ISD::SRL &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (srl:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHR8m1:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 3
- if (Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_174(N, X86::SHR8m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (srl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHR16m1:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_174(N, X86::SHR16m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
+ }
+ }
+ }
+ {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedstore(N) &&
+ Predicate_store(N)) {
+ SDValue N1 = N->getOperand(1);
- // Pattern: (st:isVoid (srl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHR32m1:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_174(N, X86::SHR32m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
+ // Pattern: (st:isVoid (sub:i64 0:i64, (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (NEG64m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 2
+ if (N1.getNode()->getOpcode() == ISD::SUB &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::LOAD &&
+ N11.hasOneUse() &&
+ IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N11.getNode() || IsChainCompatible(Chain.getNode(), N11.getNode()))) {
+ SDValue Chain11 = N11.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N11.getNode()) &&
+ Predicate_load(N11.getNode()) &&
+ Predicate_loadi64(N11.getNode())) {
+ SDValue N111 = N11.getNode()->getOperand(1);
+ SDValue CPTmpN111_0;
+ SDValue CPTmpN111_1;
+ SDValue CPTmpN111_2;
+ SDValue CPTmpN111_3;
+ SDValue CPTmpN111_4;
+ if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N111 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_173(N, X86::NEG64m, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ return Result;
}
}
}
}
}
}
- if (N1.getNode()->getOpcode() == ISD::SRA &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (sra:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SAR8m1:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 3
- if (Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_174(N, X86::SAR8m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
+ }
+ if (N1.getNode()->getOpcode() == ISD::ADD &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (st:isVoid (sra:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SAR16m1:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_174(N, X86::SAR16m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
+ // Pattern: (st:isVoid (add:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 1:i64), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (INC64m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 2
+ if (CN1 == INT64_C(1)) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_175(N, X86::INC64m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
- }
- // Pattern: (st:isVoid (sra:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SAR32m1:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_174(N, X86::SAR32m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
+ // Pattern: (st:isVoid (add:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, -1:i64), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (DEC64m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 2
+ if (CN1 == INT64_C(-1)) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_175(N, X86::DEC64m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
}
}
- if (N1.getNode()->getOpcode() == ISD::ROTL &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (rotl:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ROL8m1:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 3
- if (Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_174(N, X86::ROL8m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
+ }
+ }
+ }
+ if ((Subtarget->is64Bit())) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedstore(N) &&
+ Predicate_store(N)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::ADD &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
- // Pattern: (st:isVoid (rotl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ROL16m1:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_174(N, X86::ROL16m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (add:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 1:i16), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (INC64_16m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 2
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(1)) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_175(N, X86::INC64_16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (st:isVoid (rotl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ROL32m1:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_174(N, X86::ROL32m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (add:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 1:i32), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (INC64_32m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 2
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(1)) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_175(N, X86::INC64_32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
}
- }
- }
- if (N1.getNode()->getOpcode() == ISD::ROTR &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (rotr:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ROR8m1:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 3
- if (Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_174(N, X86::ROR8m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- // Pattern: (st:isVoid (rotr:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ROR16m1:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_174(N, X86::ROR16m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (add:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, -1:i16), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (DEC64_16m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 2
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(-1)) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_175(N, X86::DEC64_16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (st:isVoid (rotr:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ROR32m1:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_174(N, X86::ROR32m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (add:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, -1:i32), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (DEC64_32m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 2
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(-1)) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_175(N, X86::DEC64_32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
@@ -34757,21 +34068,29 @@ SDNode *Select_ISD_STORE(SDNode *N) {
}
}
}
+ }
+ }
+ }
+ {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedstore(N) &&
+ Predicate_store(N)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SHL &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
- // Pattern: (st:isVoid (shl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHL64m1:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::SHL &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi64(N10.getNode())) {
+ // Pattern: (st:isVoid (shl:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHL8m1:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 3
+ if (Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
@@ -34786,32 +34105,20 @@ SDNode *Select_ISD_STORE(SDNode *N) {
if (CN1 == INT64_C(1)) {
SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
- N1.getValueType() == MVT::i64 &&
+ N1.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_174(N, X86::SHL64m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_174(N, X86::SHL8m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
}
}
}
- }
- }
- // Pattern: (st:isVoid (srl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHR64m1:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::SRL &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi64(N10.getNode())) {
+ // Pattern: (st:isVoid (shl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHL16m1:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
@@ -34826,32 +34133,20 @@ SDNode *Select_ISD_STORE(SDNode *N) {
if (CN1 == INT64_C(1)) {
SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
- N1.getValueType() == MVT::i64 &&
+ N1.getValueType() == MVT::i16 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_174(N, X86::SHR64m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_174(N, X86::SHL16m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
}
}
}
- }
- }
- // Pattern: (st:isVoid (sra:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SAR64m1:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::SRA &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi64(N10.getNode())) {
+ // Pattern: (st:isVoid (shl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHL32m1:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
@@ -34866,9 +34161,9 @@ SDNode *Select_ISD_STORE(SDNode *N) {
if (CN1 == INT64_C(1)) {
SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
- N1.getValueType() == MVT::i64 &&
+ N1.getValueType() == MVT::i32 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_174(N, X86::SAR64m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_174(N, X86::SHL32m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -34877,21 +34172,22 @@ SDNode *Select_ISD_STORE(SDNode *N) {
}
}
}
+ }
+ if (N1.getNode()->getOpcode() == ISD::SRL &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
- // Pattern: (st:isVoid (rotl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ROL64m1:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::ROTL &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi64(N10.getNode())) {
+ // Pattern: (st:isVoid (srl:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHR8m1:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 3
+ if (Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
@@ -34906,32 +34202,20 @@ SDNode *Select_ISD_STORE(SDNode *N) {
if (CN1 == INT64_C(1)) {
SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
- N1.getValueType() == MVT::i64 &&
+ N1.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_174(N, X86::ROL64m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_174(N, X86::SHR8m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
}
}
}
- }
- }
- // Pattern: (st:isVoid (rotr:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ROR64m1:isVoid addr:iPTR:$dst)
- // Pattern complexity = 52 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::ROTR &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi64(N10.getNode())) {
+ // Pattern: (st:isVoid (srl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHR16m1:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
@@ -34946,116 +34230,38 @@ SDNode *Select_ISD_STORE(SDNode *N) {
if (CN1 == INT64_C(1)) {
SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
- N1.getValueType() == MVT::i64 &&
+ N1.getValueType() == MVT::i16 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_174(N, X86::ROR64m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_174(N, X86::SHR16m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
}
}
}
- }
- }
- if (N1.getNode()->getOpcode() == ISD::ADD &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (add:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 128:i16), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SUB16mi8:isVoid addr:iPTR:$dst, -128:i16)
- // Pattern complexity = 52 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(128)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_199(N, X86::SUB16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (add:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 128:i32), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SUB32mi8:isVoid addr:iPTR:$dst, -128:i32)
- // Pattern complexity = 52 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(128)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_200(N, X86::SUB32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- }
- if (Predicate_load(N10.getNode()) &&
- Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (st:isVoid (add:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 128:i64), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SUB64mi8:isVoid addr:iPTR:$dst, -128:i64)
- // Pattern complexity = 52 cost = 1 size = 3
- if (CN1 == INT64_C(128)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_208(N, X86::SUB64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- // Pattern: (st:isVoid (add:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 34359738368:i64), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SUB64mi32:isVoid addr:iPTR:$dst, -2147483648:i64)
- // Pattern complexity = 52 cost = 1 size = 3
- if (CN1 == INT64_C(34359738368)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_209(N, X86::SUB64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (srl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHR32m1:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(1)) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_174(N, X86::SHR32m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
@@ -35063,83 +34269,95 @@ SDNode *Select_ISD_STORE(SDNode *N) {
}
}
}
- if (N1.getNode()->getOpcode() == ISD::XOR &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (xor:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8)<<P:Predicate_immAllOnes>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (NOT8m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 51 cost = 1 size = 2
- if (Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_immAllOnes(N11.getNode())) {
+ }
+ if (N1.getNode()->getOpcode() == ISD::SRA &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
+
+ // Pattern: (st:isVoid (sra:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SAR8m1:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 3
+ if (Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(1)) {
SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_174(N, X86::NOT8m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ N1.getValueType() == MVT::i8 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_174(N, X86::SAR8m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
}
}
+ }
- // Pattern: (st:isVoid (xor:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16)<<P:Predicate_immAllOnes>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (NOT16m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 51 cost = 1 size = 2
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_immAllOnes(N11.getNode())) {
+ // Pattern: (st:isVoid (sra:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SAR16m1:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(1)) {
SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_174(N, X86::NOT16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ N1.getValueType() == MVT::i16 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_174(N, X86::SAR16m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
}
}
+ }
- // Pattern: (st:isVoid (xor:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32)<<P:Predicate_immAllOnes>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (NOT32m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 51 cost = 1 size = 2
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_immAllOnes(N11.getNode())) {
+ // Pattern: (st:isVoid (sra:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SAR32m1:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(1)) {
SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_174(N, X86::NOT32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ N1.getValueType() == MVT::i32 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_174(N, X86::SAR32m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35148,16 +34366,22 @@ SDNode *Select_ISD_STORE(SDNode *N) {
}
}
}
- if (N1.getNode()->getOpcode() == ISD::AND &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
+ }
+ if (N1.getNode()->getOpcode() == ISD::ROTL &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
+
+ // Pattern: (st:isVoid (rotl:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ROL8m1:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 3
+ if (Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
@@ -35166,46 +34390,26 @@ SDNode *Select_ISD_STORE(SDNode *N) {
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (st:isVoid (and:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (AND16mi8:isVoid addr:iPTR:$dst, (imm:i16):$src)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_i16immSExt8(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_178(N, X86::AND16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
-
- // Pattern: (st:isVoid (and:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i32)<<P:Predicate_i32immSExt8>>:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (AND32mi8:isVoid addr:iPTR:$dst, (imm:i32):$src)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_i32immSExt8(N11.getNode())) {
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(1)) {
SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::AND32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ N1.getValueType() == MVT::i8 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_174(N, X86::ROL8m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
}
}
}
- }
- }
- if (N1.getNode()->getOpcode() == ISD::OR &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
+
+ // Pattern: (st:isVoid (rotl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ROL16m1:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
@@ -35214,46 +34418,26 @@ SDNode *Select_ISD_STORE(SDNode *N) {
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (st:isVoid (or:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (OR16mi8:isVoid addr:iPTR:$dst, (imm:i16):$src)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_i16immSExt8(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_178(N, X86::OR16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
-
- // Pattern: (st:isVoid (or:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i32)<<P:Predicate_i32immSExt8>>:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (OR32mi8:isVoid addr:iPTR:$dst, (imm:i32):$src)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_i32immSExt8(N11.getNode())) {
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(1)) {
SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::OR32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ N1.getValueType() == MVT::i16 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_174(N, X86::ROL16m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
}
}
}
- }
- }
- if (N1.getNode()->getOpcode() == ISD::XOR &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
+
+ // Pattern: (st:isVoid (rotl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ROL32m1:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
@@ -35262,28 +34446,15 @@ SDNode *Select_ISD_STORE(SDNode *N) {
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (st:isVoid (xor:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (XOR16mi8:isVoid addr:iPTR:$dst, (imm:i16):$src)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_i16immSExt8(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_178(N, X86::XOR16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
-
- // Pattern: (st:isVoid (xor:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i32)<<P:Predicate_i32immSExt8>>:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (XOR32mi8:isVoid addr:iPTR:$dst, (imm:i32):$src)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_i32immSExt8(N11.getNode())) {
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(1)) {
SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::XOR32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ N1.getValueType() == MVT::i32 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_174(N, X86::ROL32m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35292,16 +34463,22 @@ SDNode *Select_ISD_STORE(SDNode *N) {
}
}
}
- if (N1.getNode()->getOpcode() == ISD::ADD &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
+ }
+ if (N1.getNode()->getOpcode() == ISD::ROTR &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
+
+ // Pattern: (st:isVoid (rotr:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ROR8m1:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 3
+ if (Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
@@ -35310,46 +34487,26 @@ SDNode *Select_ISD_STORE(SDNode *N) {
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (st:isVoid (add:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADD16mi8:isVoid addr:iPTR:$dst, (imm:i16):$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_i16immSExt8(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_178(N, X86::ADD16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
-
- // Pattern: (st:isVoid (add:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADD32mi8:isVoid addr:iPTR:$dst, (imm:i32):$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_i32immSExt8(N11.getNode())) {
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(1)) {
SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::ADD32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ N1.getValueType() == MVT::i8 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_174(N, X86::ROR8m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
}
}
}
- }
- }
- if (N1.getNode()->getOpcode() == ISD::ADDE &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
+
+ // Pattern: (st:isVoid (rotr:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ROR16m1:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
@@ -35358,46 +34515,26 @@ SDNode *Select_ISD_STORE(SDNode *N) {
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (st:isVoid (adde:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADC16mi8:isVoid addr:iPTR:$dst, (imm:i16):$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_i16immSExt8(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_186(N, X86::ADC16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
-
- // Pattern: (st:isVoid (adde:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADC32mi8:isVoid addr:iPTR:$dst, (imm:i32):$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_i32immSExt8(N11.getNode())) {
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(1)) {
SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_187(N, X86::ADC32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ N1.getValueType() == MVT::i16 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_174(N, X86::ROR16m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
}
}
}
- }
- }
- if (N1.getNode()->getOpcode() == ISD::SUB &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
+
+ // Pattern: (st:isVoid (rotr:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ROR32m1:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
@@ -35406,46 +34543,238 @@ SDNode *Select_ISD_STORE(SDNode *N) {
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (st:isVoid (sub:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SUB16mi8:isVoid addr:iPTR:$dst, (imm:i16):$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_i16immSExt8(N11.getNode())) {
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(1)) {
SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_178(N, X86::SUB16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ N1.getValueType() == MVT::i32 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_174(N, X86::ROR32m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
+ }
+ }
+ }
+ }
+ }
+ }
- // Pattern: (st:isVoid (sub:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SUB32mi8:isVoid addr:iPTR:$dst, (imm:i32):$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_i32immSExt8(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::SUB32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (shl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHL64m1:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 3
+ if (N1.getNode()->getOpcode() == ISD::SHL &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(1)) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_174(N, X86::SHL64m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
}
}
- if (N1.getNode()->getOpcode() == ISD::SUBE &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
+ }
+
+ // Pattern: (st:isVoid (srl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHR64m1:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 3
+ if (N1.getNode()->getOpcode() == ISD::SRL &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(1)) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_174(N, X86::SHR64m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (sra:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SAR64m1:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 3
+ if (N1.getNode()->getOpcode() == ISD::SRA &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(1)) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_174(N, X86::SAR64m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (rotl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ROL64m1:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 3
+ if (N1.getNode()->getOpcode() == ISD::ROTL &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(1)) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_174(N, X86::ROL64m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (rotr:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ROR64m1:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 52 cost = 1 size = 3
+ if (N1.getNode()->getOpcode() == ISD::ROTR &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(1)) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_174(N, X86::ROR64m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getNode()->getOpcode() == ISD::ADD &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
+
+ // Pattern: (st:isVoid (add:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 128:i16), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SUB16mi8:isVoid addr:iPTR:$dst, -128:i16)
+ // Pattern complexity = 52 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
@@ -35454,46 +34783,49 @@ SDNode *Select_ISD_STORE(SDNode *N) {
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (st:isVoid (sube:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SBB16mi8:isVoid addr:iPTR:$dst, (imm:i16):$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_i16immSExt8(N11.getNode())) {
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(128)) {
SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_186(N, X86::SBB16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_199(N, X86::SUB16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
+ }
+ }
+ }
- // Pattern: (st:isVoid (sube:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SBB32mi8:isVoid addr:iPTR:$dst, (imm:i32):$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_i32immSExt8(N11.getNode())) {
+ // Pattern: (st:isVoid (add:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 128:i32), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SUB32mi8:isVoid addr:iPTR:$dst, -128:i32)
+ // Pattern complexity = 52 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(128)) {
SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_187(N, X86::SBB32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_200(N, X86::SUB32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
}
}
}
- }
- }
- if (N1.getNode()->getOpcode() == ISD::ADD &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
+ if (Predicate_load(N10.getNode()) &&
+ Predicate_loadi64(N10.getNode())) {
SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
@@ -35502,28 +34834,30 @@ SDNode *Select_ISD_STORE(SDNode *N) {
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (st:isVoid (add:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADD64mi8:isVoid addr:iPTR:$dst, (imm:i64):$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_i64immSExt8(N11.getNode())) {
+ // Pattern: (st:isVoid (add:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 128:i64), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SUB64mi8:isVoid addr:iPTR:$dst, -128:i64)
+ // Pattern complexity = 52 cost = 1 size = 3
+ if (CN1 == INT64_C(128)) {
SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_190(N, X86::ADD64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_208(N, X86::SUB64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
- // Pattern: (st:isVoid (add:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADD64mi32:isVoid addr:iPTR:$dst, (imm:i64):$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_i64immSExt32(N11.getNode())) {
+ // Pattern: (st:isVoid (add:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 34359738368:i64), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SUB64mi32:isVoid addr:iPTR:$dst, -2147483648:i64)
+ // Pattern complexity = 52 cost = 1 size = 3
+ if (CN1 == INT64_C(34359738368)) {
SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_190(N, X86::ADD64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_209(N, X86::SUB64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35532,16 +34866,22 @@ SDNode *Select_ISD_STORE(SDNode *N) {
}
}
}
- if (N1.getNode()->getOpcode() == ISD::ADDE &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
+ }
+ if (N1.getNode()->getOpcode() == ISD::XOR &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
+
+ // Pattern: (st:isVoid (xor:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8)<<P:Predicate_immAllOnes>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (NOT8m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 51 cost = 1 size = 2
+ if (Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
@@ -35551,40 +34891,21 @@ SDNode *Select_ISD_STORE(SDNode *N) {
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N11 = N1.getNode()->getOperand(1);
if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_i64immSExt8(N11.getNode())) {
+ Predicate_immAllOnes(N11.getNode())) {
SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
-
- // Pattern: (st:isVoid (adde:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADC64mi8:isVoid addr:iPTR:$dst, (imm:i64):$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- {
- SDNode *Result = Emit_191(N, X86::ADC64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
-
- // Pattern: (st:isVoid (adde:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADC64mi32:isVoid addr:iPTR:$dst, (imm:i64):$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- SDNode *Result = Emit_191(N, X86::ADC64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_174(N, X86::NOT8m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
}
}
- }
- }
- if (N1.getNode()->getOpcode() == ISD::SUB &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
+
+ // Pattern: (st:isVoid (xor:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16)<<P:Predicate_immAllOnes>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (NOT16m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 51 cost = 1 size = 2
+ if (Predicate_loadi16(N10.getNode())) {
SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
@@ -35593,46 +34914,22 @@ SDNode *Select_ISD_STORE(SDNode *N) {
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (st:isVoid (sub:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SUB64mi8:isVoid addr:iPTR:$dst, (imm:i64):$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_i64immSExt8(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_190(N, X86::SUB64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
-
- // Pattern: (st:isVoid (sub:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SUB64mi32:isVoid addr:iPTR:$dst, (imm:i64):$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_i64immSExt32(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_190(N, X86::SUB64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
+ Predicate_immAllOnes(N11.getNode())) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_174(N, X86::NOT16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
- }
- }
- if (N1.getNode()->getOpcode() == ISD::SUBE &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
+
+ // Pattern: (st:isVoid (xor:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32)<<P:Predicate_immAllOnes>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (NOT32m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 51 cost = 1 size = 2
+ if (Predicate_loadi32(N10.getNode())) {
SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
@@ -35641,65 +34938,108 @@ SDNode *Select_ISD_STORE(SDNode *N) {
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
+ Predicate_immAllOnes(N11.getNode())) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_174(N, X86::NOT32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getNode()->getOpcode() == ISD::AND &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
- // Pattern: (st:isVoid (sube:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SBB64mi8:isVoid addr:iPTR:$dst, (imm:i64):$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_i64immSExt8(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_191(N, X86::SBB64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (and:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (AND16mi8:isVoid addr:iPTR:$dst, (imm:i16):$src)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_i16immSExt8(N11.getNode())) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_178(N, X86::AND16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
+ }
- // Pattern: (st:isVoid (sube:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SBB64mi32:isVoid addr:iPTR:$dst, (imm:i64):$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_i64immSExt32(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_191(N, X86::SBB64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (and:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i32)<<P:Predicate_i32immSExt8>>:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (AND32mi8:isVoid addr:iPTR:$dst, (imm:i32):$src)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_i32immSExt8(N11.getNode())) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_179(N, X86::AND32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
}
}
+ }
+ if (N1.getNode()->getOpcode() == ISD::OR &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
- // Pattern: (st:isVoid (xor:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_immAllOnes>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (NOT64m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 51 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::XOR &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_immAllOnes(N11.getNode())) {
+ // Pattern: (st:isVoid (or:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (OR16mi8:isVoid addr:iPTR:$dst, (imm:i16):$src)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_i16immSExt8(N11.getNode())) {
SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_174(N, X86::NOT64m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_178(N, X86::OR16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (st:isVoid (or:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i32)<<P:Predicate_i32immSExt8>>:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (OR32mi8:isVoid addr:iPTR:$dst, (imm:i32):$src)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_i32immSExt8(N11.getNode())) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_179(N, X86::OR32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35707,500 +35047,485 @@ SDNode *Select_ISD_STORE(SDNode *N) {
}
}
}
- if (N1.getNode()->getOpcode() == ISD::AND &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
+ }
+ if (N1.getNode()->getOpcode() == ISD::XOR &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
- // Pattern: (st:isVoid (and:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (AND64mi8:isVoid addr:iPTR:$dst, (imm:i64):$src)
- // Pattern complexity = 51 cost = 1 size = 3
- {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_i64immSExt8(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_190(N, X86::AND64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (xor:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (XOR16mi8:isVoid addr:iPTR:$dst, (imm:i16):$src)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_i16immSExt8(N11.getNode())) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_178(N, X86::XOR16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
- }
- // Pattern: (st:isVoid (and:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt32>>:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (AND64mi32:isVoid addr:iPTR:$dst, (imm:i64):$src)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_i64immSExt32(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_190(N, X86::AND64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (xor:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i32)<<P:Predicate_i32immSExt8>>:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (XOR32mi8:isVoid addr:iPTR:$dst, (imm:i32):$src)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_i32immSExt8(N11.getNode())) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_179(N, X86::XOR32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
}
}
- if (N1.getNode()->getOpcode() == ISD::OR &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
+ }
+ if (N1.getNode()->getOpcode() == ISD::ADD &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
- // Pattern: (st:isVoid (or:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (OR64mi8:isVoid addr:iPTR:$dst, (imm:i64):$src)
- // Pattern complexity = 51 cost = 1 size = 3
- {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_i64immSExt8(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_190(N, X86::OR64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (add:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADD16mi8:isVoid addr:iPTR:$dst, (imm:i16):$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_i16immSExt8(N11.getNode())) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_178(N, X86::ADD16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
- }
- // Pattern: (st:isVoid (or:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt32>>:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (OR64mi32:isVoid addr:iPTR:$dst, (imm:i64):$src)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_i64immSExt32(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_190(N, X86::OR64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (add:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADD32mi8:isVoid addr:iPTR:$dst, (imm:i32):$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_i32immSExt8(N11.getNode())) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_179(N, X86::ADD32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
}
}
- if (N1.getNode()->getOpcode() == ISD::XOR &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
+ }
+ if (N1.getNode()->getOpcode() == ISD::ADDE &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
- // Pattern: (st:isVoid (xor:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (XOR64mi8:isVoid addr:iPTR:$dst, (imm:i64):$src)
- // Pattern complexity = 51 cost = 1 size = 3
- {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_i64immSExt8(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_190(N, X86::XOR64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (adde:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADC16mi8:isVoid addr:iPTR:$dst, (imm:i16):$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_i16immSExt8(N11.getNode())) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_186(N, X86::ADC16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
- }
- // Pattern: (st:isVoid (xor:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt32>>:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (XOR64mi32:isVoid addr:iPTR:$dst, (imm:i64):$src)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_i64immSExt32(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_190(N, X86::XOR64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (adde:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADC32mi8:isVoid addr:iPTR:$dst, (imm:i32):$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_i32immSExt8(N11.getNode())) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_187(N, X86::ADC32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
}
}
- if (N1.getNode()->getOpcode() == X86ISD::ADD &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (X86add_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADD16mi8:isVoid addr:iPTR:$dst, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_i16immSExt8(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_178(N, X86::ADD16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ }
+ if (N1.getNode()->getOpcode() == ISD::SUB &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+
+ // Pattern: (st:isVoid (sub:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SUB16mi8:isVoid addr:iPTR:$dst, (imm:i16):$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_i16immSExt8(N11.getNode())) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_178(N, X86::SUB16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
- }
- // Pattern: (st:isVoid (X86add_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADD32mi8:isVoid addr:iPTR:$dst, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_i32immSExt8(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::ADD32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (sub:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SUB32mi8:isVoid addr:iPTR:$dst, (imm:i32):$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_i32immSExt8(N11.getNode())) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_179(N, X86::SUB32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
}
}
- if (N1.getNode()->getOpcode() == X86ISD::SUB &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (X86sub_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SUB16mi8:isVoid addr:iPTR:$dst, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_i16immSExt8(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_178(N, X86::SUB16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ }
+ if (N1.getNode()->getOpcode() == ISD::SUBE &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+
+ // Pattern: (st:isVoid (sube:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SBB16mi8:isVoid addr:iPTR:$dst, (imm:i16):$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_i16immSExt8(N11.getNode())) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_186(N, X86::SBB16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
- }
- // Pattern: (st:isVoid (X86sub_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SUB32mi8:isVoid addr:iPTR:$dst, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_i32immSExt8(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::SUB32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (sube:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SBB32mi8:isVoid addr:iPTR:$dst, (imm:i32):$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_i32immSExt8(N11.getNode())) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_187(N, X86::SBB32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
}
}
- if (N1.getNode()->getOpcode() == X86ISD::OR &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (X86or_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (OR16mi8:isVoid addr:iPTR:$dst, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_i16immSExt8(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_178(N, X86::OR16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ }
+ if (N1.getNode()->getOpcode() == ISD::ADD &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+
+ // Pattern: (st:isVoid (add:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADD64mi8:isVoid addr:iPTR:$dst, (imm:i64):$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_i64immSExt8(N11.getNode())) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_190(N, X86::ADD64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
- }
- // Pattern: (st:isVoid (X86or_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (OR32mi8:isVoid addr:iPTR:$dst, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_i32immSExt8(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::OR32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (add:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADD64mi32:isVoid addr:iPTR:$dst, (imm:i64):$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_i64immSExt32(N11.getNode())) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_190(N, X86::ADD64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
}
}
- if (N1.getNode()->getOpcode() == X86ISD::XOR &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (X86xor_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (XOR16mi8:isVoid addr:iPTR:$dst, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_i16immSExt8(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_178(N, X86::XOR16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ }
+ if (N1.getNode()->getOpcode() == ISD::ADDE &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
+ Predicate_i64immSExt8(N11.getNode())) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+
+ // Pattern: (st:isVoid (adde:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADC64mi8:isVoid addr:iPTR:$dst, (imm:i64):$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ {
+ SDNode *Result = Emit_191(N, X86::ADC64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
+
+ // Pattern: (st:isVoid (adde:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADC64mi32:isVoid addr:iPTR:$dst, (imm:i64):$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ SDNode *Result = Emit_191(N, X86::ADC64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
+ }
+ }
+ }
+ }
+ if (N1.getNode()->getOpcode() == ISD::SUB &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
- // Pattern: (st:isVoid (X86xor_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (XOR32mi8:isVoid addr:iPTR:$dst, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_i32immSExt8(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::XOR32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (sub:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SUB64mi8:isVoid addr:iPTR:$dst, (imm:i64):$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_i64immSExt8(N11.getNode())) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_190(N, X86::SUB64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (st:isVoid (sub:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SUB64mi32:isVoid addr:iPTR:$dst, (imm:i64):$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_i64immSExt32(N11.getNode())) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_190(N, X86::SUB64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
}
}
- if (N1.getNode()->getOpcode() == X86ISD::AND &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (X86and_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (AND16mi8:isVoid addr:iPTR:$dst, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_i16immSExt8(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_178(N, X86::AND16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ }
+ if (N1.getNode()->getOpcode() == ISD::SUBE &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+
+ // Pattern: (st:isVoid (sube:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SBB64mi8:isVoid addr:iPTR:$dst, (imm:i64):$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_i64immSExt8(N11.getNode())) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_191(N, X86::SBB64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
- }
- // Pattern: (st:isVoid (X86and_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (AND32mi8:isVoid addr:iPTR:$dst, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant &&
- Predicate_i32immSExt8(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::AND32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (sube:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SBB64mi32:isVoid addr:iPTR:$dst, (imm:i64):$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_i64immSExt32(N11.getNode())) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_191(N, X86::SBB64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
}
}
- if (N1.getNode()->getOpcode() == X86ISD::ADD &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi64(N10.getNode())) {
+ }
+
+ // Pattern: (st:isVoid (xor:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_immAllOnes>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (NOT64m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (N1.getNode()->getOpcode() == ISD::XOR &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
+ Predicate_immAllOnes(N11.getNode())) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_174(N, X86::NOT64m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getNode()->getOpcode() == ISD::AND &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+
+ // Pattern: (st:isVoid (and:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (AND64mi8:isVoid addr:iPTR:$dst, (imm:i64):$src)
+ // Pattern complexity = 51 cost = 1 size = 3
+ {
SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
@@ -36209,47 +35534,59 @@ SDNode *Select_ISD_STORE(SDNode *N) {
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (st:isVoid (X86add_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADD64mi8:isVoid addr:iPTR:$dst, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_i64immSExt8(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_190(N, X86::ADD64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
+ Predicate_i64immSExt8(N11.getNode())) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_190(N, X86::AND64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
+ }
+ }
+ }
- // Pattern: (st:isVoid (X86add_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADD64mi32:isVoid addr:iPTR:$dst, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_i64immSExt32(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_190(N, X86::ADD64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (and:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt32>>:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (AND64mi32:isVoid addr:iPTR:$dst, (imm:i64):$src)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
+ Predicate_i64immSExt32(N11.getNode())) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_190(N, X86::AND64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
}
}
- if (N1.getNode()->getOpcode() == X86ISD::SUB &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi64(N10.getNode())) {
+ }
+ if (N1.getNode()->getOpcode() == ISD::OR &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+
+ // Pattern: (st:isVoid (or:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (OR64mi8:isVoid addr:iPTR:$dst, (imm:i64):$src)
+ // Pattern complexity = 51 cost = 1 size = 3
+ {
SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
@@ -36258,47 +35595,59 @@ SDNode *Select_ISD_STORE(SDNode *N) {
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (st:isVoid (X86sub_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SUB64mi8:isVoid addr:iPTR:$dst, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_i64immSExt8(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_190(N, X86::SUB64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
+ Predicate_i64immSExt8(N11.getNode())) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_190(N, X86::OR64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
+ }
+ }
+ }
- // Pattern: (st:isVoid (X86sub_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SUB64mi32:isVoid addr:iPTR:$dst, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_i64immSExt32(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_190(N, X86::SUB64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (or:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt32>>:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (OR64mi32:isVoid addr:iPTR:$dst, (imm:i64):$src)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
+ Predicate_i64immSExt32(N11.getNode())) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_190(N, X86::OR64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
}
}
- if (N1.getNode()->getOpcode() == X86ISD::OR &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi64(N10.getNode())) {
+ }
+ if (N1.getNode()->getOpcode() == ISD::XOR &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+
+ // Pattern: (st:isVoid (xor:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (XOR64mi8:isVoid addr:iPTR:$dst, (imm:i64):$src)
+ // Pattern complexity = 51 cost = 1 size = 3
+ {
SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
@@ -36307,47 +35656,58 @@ SDNode *Select_ISD_STORE(SDNode *N) {
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (st:isVoid (X86or_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (OR64mi8:isVoid addr:iPTR:$dst, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_i64immSExt8(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_190(N, X86::OR64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
+ Predicate_i64immSExt8(N11.getNode())) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_190(N, X86::XOR64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
+ }
+ }
+ }
- // Pattern: (st:isVoid (X86or_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (OR64mi32:isVoid addr:iPTR:$dst, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_i64immSExt32(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_190(N, X86::OR64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (xor:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt32>>:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (XOR64mi32:isVoid addr:iPTR:$dst, (imm:i64):$src)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
+ Predicate_i64immSExt32(N11.getNode())) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_190(N, X86::XOR64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
}
}
- if (N1.getNode()->getOpcode() == X86ISD::XOR &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi64(N10.getNode())) {
+ }
+ if (N1.getNode()->getOpcode() == X86ISD::ADD &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
+
+ // Pattern: (st:isVoid (X86add_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADD16mi8:isVoid addr:iPTR:$dst, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
@@ -36356,47 +35716,58 @@ SDNode *Select_ISD_STORE(SDNode *N) {
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (st:isVoid (X86xor_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (XOR64mi8:isVoid addr:iPTR:$dst, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_i64immSExt8(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_190(N, X86::XOR64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
+ Predicate_i16immSExt8(N11.getNode())) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_178(N, X86::ADD16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
+ }
+ }
+ }
- // Pattern: (st:isVoid (X86xor_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (XOR64mi32:isVoid addr:iPTR:$dst, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_i64immSExt32(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_190(N, X86::XOR64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (X86add_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADD32mi8:isVoid addr:iPTR:$dst, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
+ Predicate_i32immSExt8(N11.getNode())) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_179(N, X86::ADD32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
}
}
- if (N1.getNode()->getOpcode() == X86ISD::AND &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi64(N10.getNode())) {
+ }
+ if (N1.getNode()->getOpcode() == X86ISD::SUB &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
+
+ // Pattern: (st:isVoid (X86sub_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SUB16mi8:isVoid addr:iPTR:$dst, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
@@ -36405,30 +35776,37 @@ SDNode *Select_ISD_STORE(SDNode *N) {
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (st:isVoid (X86and_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (AND64mi8:isVoid addr:iPTR:$dst, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_i64immSExt8(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_190(N, X86::AND64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
+ Predicate_i16immSExt8(N11.getNode())) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_178(N, X86::SUB16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
+ }
+ }
+ }
- // Pattern: (st:isVoid (X86and_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (AND64mi32:isVoid addr:iPTR:$dst, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if (Predicate_i64immSExt32(N11.getNode())) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_190(N, X86::AND64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (X86sub_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SUB32mi8:isVoid addr:iPTR:$dst, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
+ Predicate_i32immSExt8(N11.getNode())) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_179(N, X86::SUB32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
@@ -36436,43 +35814,58 @@ SDNode *Select_ISD_STORE(SDNode *N) {
}
}
}
- }
+ if (N1.getNode()->getOpcode() == X86ISD::OR &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
- // Pattern: (st:isVoid (vector_shuffle:v4i32 (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR128:v4i32:$src2)<<P:Predicate_movlp>>, addr:iPTR:$src1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (MOVLPSmr:isVoid addr:iPTR:$src1, VR128:v16i8:$src2)
- // Pattern complexity = 51 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedstore(N) &&
- Predicate_store(N)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::VECTOR_SHUFFLE &&
- N1.hasOneUse() &&
- Predicate_movlp(N1.getNode())) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::LOAD &&
- N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N) &&
- (Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
- SDValue Chain100 = N100.getNode()->getOperand(0);
- if (Predicate_unindexedload(N100.getNode()) &&
- Predicate_load(N100.getNode())) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue CPTmpN1001_0;
- SDValue CPTmpN1001_1;
- SDValue CPTmpN1001_2;
- SDValue CPTmpN1001_3;
- SDValue CPTmpN1001_4;
- if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
+ // Pattern: (st:isVoid (X86or_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (OR16mi8:isVoid addr:iPTR:$dst, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
+ Predicate_i16immSExt8(N11.getNode())) {
SDValue N2 = N->getOperand(2);
- if (N1001 == N2 &&
- N1.getValueType() == MVT::v4i32 &&
- N100.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_214(N, X86::MOVLPSmr, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_178(N, X86::OR16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86or_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (OR32mi8:isVoid addr:iPTR:$dst, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
+ Predicate_i32immSExt8(N11.getNode())) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_179(N, X86::OR32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36481,697 +35874,732 @@ SDNode *Select_ISD_STORE(SDNode *N) {
}
}
}
- }
- {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedstore(N) &&
- Predicate_store(N)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::AND &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (and:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (AND8mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_177(N, X86::AND8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ if (N1.getNode()->getOpcode() == X86ISD::XOR &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
+
+ // Pattern: (st:isVoid (X86xor_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (XOR16mi8:isVoid addr:iPTR:$dst, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
+ Predicate_i16immSExt8(N11.getNode())) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_178(N, X86::XOR16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
+ }
- // Pattern: (st:isVoid (and:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (AND16mi:isVoid addr:iPTR:$dst, (imm:i16):$src)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_178(N, X86::AND16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (X86xor_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (XOR32mi8:isVoid addr:iPTR:$dst, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
+ Predicate_i32immSExt8(N11.getNode())) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_179(N, X86::XOR32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
+ }
+ }
+ }
+ }
+ if (N1.getNode()->getOpcode() == X86ISD::AND &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
- // Pattern: (st:isVoid (and:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (AND32mi:isVoid addr:iPTR:$dst, (imm:i32):$src)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::AND32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (X86and_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (AND16mi8:isVoid addr:iPTR:$dst, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
+ Predicate_i16immSExt8(N11.getNode())) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_178(N, X86::AND16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86and_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (AND32mi8:isVoid addr:iPTR:$dst, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
+ Predicate_i32immSExt8(N11.getNode())) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_179(N, X86::AND32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
}
}
- if (N1.getNode()->getOpcode() == ISD::OR &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (or:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (OR8mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_177(N, X86::OR8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ }
+ if (N1.getNode()->getOpcode() == X86ISD::ADD &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+
+ // Pattern: (st:isVoid (X86add_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADD64mi8:isVoid addr:iPTR:$dst, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_i64immSExt8(N11.getNode())) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_190(N, X86::ADD64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
- }
- // Pattern: (st:isVoid (or:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (OR16mi:isVoid addr:iPTR:$dst, (imm:i16):$src)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_178(N, X86::OR16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (X86add_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADD64mi32:isVoid addr:iPTR:$dst, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_i64immSExt32(N11.getNode())) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_190(N, X86::ADD64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
+ }
+ }
+ }
+ }
+ if (N1.getNode()->getOpcode() == X86ISD::SUB &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
- // Pattern: (st:isVoid (or:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (OR32mi:isVoid addr:iPTR:$dst, (imm:i32):$src)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::OR32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (X86sub_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SUB64mi8:isVoid addr:iPTR:$dst, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_i64immSExt8(N11.getNode())) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_190(N, X86::SUB64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (st:isVoid (X86sub_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SUB64mi32:isVoid addr:iPTR:$dst, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_i64immSExt32(N11.getNode())) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_190(N, X86::SUB64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
}
}
- if (N1.getNode()->getOpcode() == ISD::XOR &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (xor:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (XOR8mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_177(N, X86::XOR8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ }
+ if (N1.getNode()->getOpcode() == X86ISD::OR &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+
+ // Pattern: (st:isVoid (X86or_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (OR64mi8:isVoid addr:iPTR:$dst, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_i64immSExt8(N11.getNode())) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_190(N, X86::OR64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
- }
- // Pattern: (st:isVoid (xor:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (XOR16mi:isVoid addr:iPTR:$dst, (imm:i16):$src)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_178(N, X86::XOR16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (X86or_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (OR64mi32:isVoid addr:iPTR:$dst, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_i64immSExt32(N11.getNode())) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_190(N, X86::OR64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
+ }
+ }
+ }
+ }
+ if (N1.getNode()->getOpcode() == X86ISD::XOR &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
- // Pattern: (st:isVoid (xor:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (XOR32mi:isVoid addr:iPTR:$dst, (imm:i32):$src)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::XOR32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (X86xor_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (XOR64mi8:isVoid addr:iPTR:$dst, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_i64immSExt8(N11.getNode())) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_190(N, X86::XOR64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (st:isVoid (X86xor_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (XOR64mi32:isVoid addr:iPTR:$dst, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_i64immSExt32(N11.getNode())) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_190(N, X86::XOR64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
}
}
- if (N1.getNode()->getOpcode() == ISD::SHL &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (shl:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHL8mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_181(N, X86::SHL8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ }
+ if (N1.getNode()->getOpcode() == X86ISD::AND &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+
+ // Pattern: (st:isVoid (X86and_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (AND64mi8:isVoid addr:iPTR:$dst, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_i64immSExt8(N11.getNode())) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_190(N, X86::AND64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
- }
- // Pattern: (st:isVoid (shl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHL16mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_181(N, X86::SHL16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (X86and_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (AND64mi32:isVoid addr:iPTR:$dst, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if (Predicate_i64immSExt32(N11.getNode())) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_190(N, X86::AND64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
+ }
+ }
+ }
+ }
+ }
+ }
- // Pattern: (st:isVoid (shl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHL32mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_181(N, X86::SHL32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
+ // Pattern: (st:isVoid (vector_shuffle:v4i32 (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR128:v4i32:$src2)<<P:Predicate_movlp>>, addr:iPTR:$src1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (MOVLPSmr:isVoid addr:iPTR:$src1, VR128:v16i8:$src2)
+ // Pattern complexity = 51 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedstore(N) &&
+ Predicate_store(N)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::VECTOR_SHUFFLE &&
+ N1.hasOneUse() &&
+ Predicate_movlp(N1.getNode())) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::LOAD &&
+ N100.hasOneUse() &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N) &&
+ (Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
+ SDValue Chain100 = N100.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N100.getNode()) &&
+ Predicate_load(N100.getNode())) {
+ SDValue N1001 = N100.getNode()->getOperand(1);
+ SDValue CPTmpN1001_0;
+ SDValue CPTmpN1001_1;
+ SDValue CPTmpN1001_2;
+ SDValue CPTmpN1001_3;
+ SDValue CPTmpN1001_4;
+ if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N1001 == N2 &&
+ N1.getValueType() == MVT::v4i32 &&
+ N100.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_214(N, X86::MOVLPSmr, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ return Result;
}
}
}
}
}
- if (N1.getNode()->getOpcode() == ISD::SRL &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (srl:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHR8mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_181(N, X86::SHR8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ }
+ }
+ }
+ {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedstore(N) &&
+ Predicate_store(N)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
+
+ // Pattern: (st:isVoid (and:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (AND8mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_177(N, X86::AND8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
+ }
- // Pattern: (st:isVoid (srl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHR16mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_181(N, X86::SHR16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (and:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (AND16mi:isVoid addr:iPTR:$dst, (imm:i16):$src)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_178(N, X86::AND16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
+ }
- // Pattern: (st:isVoid (srl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHR32mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_181(N, X86::SHR32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (and:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (AND32mi:isVoid addr:iPTR:$dst, (imm:i32):$src)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_179(N, X86::AND32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
}
}
- if (N1.getNode()->getOpcode() == ISD::SRA &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (sra:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SAR8mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_181(N, X86::SAR8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ }
+ if (N1.getNode()->getOpcode() == ISD::OR &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
+
+ // Pattern: (st:isVoid (or:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (OR8mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_177(N, X86::OR8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
+ }
- // Pattern: (st:isVoid (sra:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SAR16mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_181(N, X86::SAR16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (or:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (OR16mi:isVoid addr:iPTR:$dst, (imm:i16):$src)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_178(N, X86::OR16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
+ }
- // Pattern: (st:isVoid (sra:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SAR32mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_181(N, X86::SAR32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (or:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (OR32mi:isVoid addr:iPTR:$dst, (imm:i32):$src)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_179(N, X86::OR32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
}
}
- if (N1.getNode()->getOpcode() == ISD::ROTL &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (rotl:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ROL8mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_181(N, X86::ROL8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ }
+ if (N1.getNode()->getOpcode() == ISD::XOR &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
+
+ // Pattern: (st:isVoid (xor:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (XOR8mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_177(N, X86::XOR8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
+ }
- // Pattern: (st:isVoid (rotl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ROL16mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_181(N, X86::ROL16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (xor:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (XOR16mi:isVoid addr:iPTR:$dst, (imm:i16):$src)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_178(N, X86::XOR16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
+ }
- // Pattern: (st:isVoid (rotl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ROL32mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_181(N, X86::ROL32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (xor:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (XOR32mi:isVoid addr:iPTR:$dst, (imm:i32):$src)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_179(N, X86::XOR32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
}
}
- if (N1.getNode()->getOpcode() == ISD::ROTR &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (rotr:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ROR8mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_181(N, X86::ROR8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
+ }
+ if (N1.getNode()->getOpcode() == ISD::SHL &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
- // Pattern: (st:isVoid (rotr:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ROR16mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_181(N, X86::ROR16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (shl:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHL8mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i8 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_181(N, X86::SHL8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
+ }
- // Pattern: (st:isVoid (rotr:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ROR32mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_181(N, X86::ROR32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (shl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHL16mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_181(N, X86::SHL16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
- }
- }
- // Pattern: (st:isVoid (X86shld:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, (imm:i8):$src3), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHLD32mri8:isVoid addr:iPTR:$dst, GR32:i32:$src2, (imm:i8):$src3)
- // Pattern complexity = 50 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == X86ISD::SHLD &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_loadi32(N10.getNode())) {
+ // Pattern: (st:isVoid (shl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHL32mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
@@ -37180,13 +36608,12 @@ SDNode *Select_ISD_STORE(SDNode *N) {
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N12 = N1.getNode()->getOperand(2);
- if (N12.getNode()->getOpcode() == ISD::Constant) {
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32 &&
- N12.getValueType() == MVT::i8) {
- SDNode *Result = Emit_183(N, X86::SHLD32mri8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_181(N, X86::SHL32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37194,20 +36621,22 @@ SDNode *Select_ISD_STORE(SDNode *N) {
}
}
}
+ }
+ if (N1.getNode()->getOpcode() == ISD::SRL &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
- // Pattern: (st:isVoid (X86shrd:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, (imm:i8):$src3), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHRD32mri8:isVoid addr:iPTR:$dst, GR32:i32:$src2, (imm:i8):$src3)
- // Pattern complexity = 50 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == X86ISD::SHRD &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_loadi32(N10.getNode())) {
+ // Pattern: (st:isVoid (srl:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHR8mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
@@ -37216,34 +36645,22 @@ SDNode *Select_ISD_STORE(SDNode *N) {
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N12 = N1.getNode()->getOperand(2);
- if (N12.getNode()->getOpcode() == ISD::Constant) {
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N12.getValueType() == MVT::i8) {
- SDNode *Result = Emit_183(N, X86::SHRD32mri8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ N1.getValueType() == MVT::i8 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_181(N, X86::SHR8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
}
}
- }
- }
- // Pattern: (st:isVoid (X86shld:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, (imm:i8):$src3), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHLD16mri8:isVoid addr:iPTR:$dst, GR16:i16:$src2, (imm:i8):$src3)
- // Pattern complexity = 50 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == X86ISD::SHLD &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_loadi16(N10.getNode())) {
+ // Pattern: (st:isVoid (srl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHR16mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
@@ -37252,34 +36669,22 @@ SDNode *Select_ISD_STORE(SDNode *N) {
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N12 = N1.getNode()->getOperand(2);
- if (N12.getNode()->getOpcode() == ISD::Constant) {
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16 &&
- N12.getValueType() == MVT::i8) {
- SDNode *Result = Emit_183(N, X86::SHLD16mri8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_181(N, X86::SHR16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
}
}
- }
- }
- // Pattern: (st:isVoid (X86shrd:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, (imm:i8):$src3), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHRD16mri8:isVoid addr:iPTR:$dst, GR16:i16:$src2, (imm:i8):$src3)
- // Pattern complexity = 50 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == X86ISD::SHRD &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_loadi16(N10.getNode())) {
+ // Pattern: (st:isVoid (srl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHR32mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
@@ -37288,13 +36693,12 @@ SDNode *Select_ISD_STORE(SDNode *N) {
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N12 = N1.getNode()->getOperand(2);
- if (N12.getNode()->getOpcode() == ISD::Constant) {
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N12.getValueType() == MVT::i8) {
- SDNode *Result = Emit_183(N, X86::SHRD16mri8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ N1.getValueType() == MVT::i32 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_181(N, X86::SHR32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37302,349 +36706,421 @@ SDNode *Select_ISD_STORE(SDNode *N) {
}
}
}
- if (N1.getNode()->getOpcode() == ISD::ADD &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (add:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADD8mi:isVoid addr:iPTR:$dst, (imm:i8):$src2)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_177(N, X86::ADD8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ }
+ if (N1.getNode()->getOpcode() == ISD::SRA &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
+
+ // Pattern: (st:isVoid (sra:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SAR8mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i8 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_181(N, X86::SAR8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
+ }
- // Pattern: (st:isVoid (add:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADD16mi:isVoid addr:iPTR:$dst, (imm:i16):$src2)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_178(N, X86::ADD16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (sra:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SAR16mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_181(N, X86::SAR16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
+ }
- // Pattern: (st:isVoid (add:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADD32mi:isVoid addr:iPTR:$dst, (imm:i32):$src2)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::ADD32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (sra:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SAR32mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_181(N, X86::SAR32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
}
}
- if (N1.getNode()->getOpcode() == ISD::ADDE &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (adde:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADC8mi:isVoid addr:iPTR:$dst, (imm:i8):$src2)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_185(N, X86::ADC8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ }
+ if (N1.getNode()->getOpcode() == ISD::ROTL &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
+
+ // Pattern: (st:isVoid (rotl:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ROL8mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i8 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_181(N, X86::ROL8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
+ }
- // Pattern: (st:isVoid (adde:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADC16mi:isVoid addr:iPTR:$dst, (imm:i16):$src2)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_186(N, X86::ADC16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (rotl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ROL16mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_181(N, X86::ROL16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
+ }
- // Pattern: (st:isVoid (adde:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADC32mi:isVoid addr:iPTR:$dst, (imm:i32):$src2)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_187(N, X86::ADC32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (rotl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ROL32mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_181(N, X86::ROL32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
}
}
- if (N1.getNode()->getOpcode() == ISD::SUB &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (sub:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SUB8mi:isVoid addr:iPTR:$dst, (imm:i8):$src2)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_177(N, X86::SUB8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ }
+ if (N1.getNode()->getOpcode() == ISD::ROTR &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
+
+ // Pattern: (st:isVoid (rotr:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ROR8mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i8 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_181(N, X86::ROR8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
+ }
- // Pattern: (st:isVoid (sub:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SUB16mi:isVoid addr:iPTR:$dst, (imm:i16):$src2)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_178(N, X86::SUB16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (rotr:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ROR16mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_181(N, X86::ROR16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
+ }
- // Pattern: (st:isVoid (sub:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SUB32mi:isVoid addr:iPTR:$dst, (imm:i32):$src2)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::SUB32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (rotr:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ROR32mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_181(N, X86::ROR32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
}
}
- if (N1.getNode()->getOpcode() == ISD::SUBE &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (sube:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SBB8mi:isVoid addr:iPTR:$dst, (imm:i8):$src2)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_185(N, X86::SBB8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
+ }
+
+ // Pattern: (st:isVoid (X86shld:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, (imm:i8):$src3), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHLD32mri8:isVoid addr:iPTR:$dst, GR32:i32:$src2, (imm:i8):$src3)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (N1.getNode()->getOpcode() == X86ISD::SHLD &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N12 = N1.getNode()->getOperand(2);
+ if (N12.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32 &&
+ N12.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_183(N, X86::SHLD32mri8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
+ }
+ }
+ }
+ }
- // Pattern: (st:isVoid (sube:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SBB16mi:isVoid addr:iPTR:$dst, (imm:i16):$src2)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_186(N, X86::SBB16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
+ // Pattern: (st:isVoid (X86shrd:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, (imm:i8):$src3), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHRD32mri8:isVoid addr:iPTR:$dst, GR32:i32:$src2, (imm:i8):$src3)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (N1.getNode()->getOpcode() == X86ISD::SHRD &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N12 = N1.getNode()->getOperand(2);
+ if (N12.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32 &&
+ N12.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_183(N, X86::SHRD32mri8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
+ }
+ }
+ }
+ }
- // Pattern: (st:isVoid (sube:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SBB32mi:isVoid addr:iPTR:$dst, (imm:i32):$src2)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_187(N, X86::SBB32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
+ // Pattern: (st:isVoid (X86shld:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, (imm:i8):$src3), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHLD16mri8:isVoid addr:iPTR:$dst, GR16:i16:$src2, (imm:i8):$src3)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (N1.getNode()->getOpcode() == X86ISD::SHLD &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N12 = N1.getNode()->getOperand(2);
+ if (N12.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16 &&
+ N12.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_183(N, X86::SHLD16mri8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
}
+ }
- // Pattern: (st:isVoid (shl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHL64mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
- // Pattern complexity = 50 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::SHL &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi64(N10.getNode())) {
+ // Pattern: (st:isVoid (X86shrd:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, (imm:i8):$src3), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHRD16mri8:isVoid addr:iPTR:$dst, GR16:i16:$src2, (imm:i8):$src3)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (N1.getNode()->getOpcode() == X86ISD::SHRD &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N12 = N1.getNode()->getOperand(2);
+ if (N12.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16 &&
+ N12.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_183(N, X86::SHRD16mri8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getNode()->getOpcode() == ISD::ADD &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
+
+ // Pattern: (st:isVoid (add:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADD8mi:isVoid addr:iPTR:$dst, (imm:i8):$src2)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
@@ -37656,31 +37132,18 @@ SDNode *Select_ISD_STORE(SDNode *N) {
if (N11.getNode()->getOpcode() == ISD::Constant) {
SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
- N1.getValueType() == MVT::i64 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_181(N, X86::SHL64mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_177(N, X86::ADD8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
}
}
- }
- }
- // Pattern: (st:isVoid (srl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHR64mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
- // Pattern complexity = 50 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::SRL &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi64(N10.getNode())) {
+ // Pattern: (st:isVoid (add:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADD16mi:isVoid addr:iPTR:$dst, (imm:i16):$src2)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
@@ -37692,31 +37155,18 @@ SDNode *Select_ISD_STORE(SDNode *N) {
if (N11.getNode()->getOpcode() == ISD::Constant) {
SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
- N1.getValueType() == MVT::i64 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_181(N, X86::SHR64mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_178(N, X86::ADD16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
}
}
- }
- }
- // Pattern: (st:isVoid (sra:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SAR64mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
- // Pattern complexity = 50 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::SRA &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi64(N10.getNode())) {
+ // Pattern: (st:isVoid (add:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADD32mi:isVoid addr:iPTR:$dst, (imm:i32):$src2)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
@@ -37728,9 +37178,8 @@ SDNode *Select_ISD_STORE(SDNode *N) {
if (N11.getNode()->getOpcode() == ISD::Constant) {
SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
- N1.getValueType() == MVT::i64 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_181(N, X86::SAR64mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_179(N, X86::ADD32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37738,21 +37187,22 @@ SDNode *Select_ISD_STORE(SDNode *N) {
}
}
}
+ }
+ if (N1.getNode()->getOpcode() == ISD::ADDE &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
- // Pattern: (st:isVoid (rotl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ROL64mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
- // Pattern complexity = 50 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::ROTL &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi64(N10.getNode())) {
+ // Pattern: (st:isVoid (adde:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADC8mi:isVoid addr:iPTR:$dst, (imm:i8):$src2)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
@@ -37764,31 +37214,18 @@ SDNode *Select_ISD_STORE(SDNode *N) {
if (N11.getNode()->getOpcode() == ISD::Constant) {
SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
- N1.getValueType() == MVT::i64 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_181(N, X86::ROL64mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_185(N, X86::ADC8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
}
}
- }
- }
- // Pattern: (st:isVoid (rotr:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ROR64mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
- // Pattern complexity = 50 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == ISD::ROTR &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi64(N10.getNode())) {
+ // Pattern: (st:isVoid (adde:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADC16mi:isVoid addr:iPTR:$dst, (imm:i16):$src2)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
@@ -37800,31 +37237,18 @@ SDNode *Select_ISD_STORE(SDNode *N) {
if (N11.getNode()->getOpcode() == ISD::Constant) {
SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
- N1.getValueType() == MVT::i64 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_181(N, X86::ROR64mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_186(N, X86::ADC16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
}
}
- }
- }
- // Pattern: (st:isVoid (X86shld:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, (imm:i8):$src3), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHLD64mri8:isVoid addr:iPTR:$dst, GR64:i64:$src2, (imm:i8):$src3)
- // Pattern complexity = 50 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == X86ISD::SHLD &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi64(N10.getNode())) {
+ // Pattern: (st:isVoid (adde:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADC32mi:isVoid addr:iPTR:$dst, (imm:i32):$src2)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
@@ -37833,13 +37257,11 @@ SDNode *Select_ISD_STORE(SDNode *N) {
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N12 = N1.getNode()->getOperand(2);
- if (N12.getNode()->getOpcode() == ISD::Constant) {
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
- N1.getValueType() == MVT::i64 &&
- N12.getValueType() == MVT::i8) {
- SDNode *Result = Emit_183(N, X86::SHLD64mri8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_187(N, X86::ADC32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37847,21 +37269,22 @@ SDNode *Select_ISD_STORE(SDNode *N) {
}
}
}
+ }
+ if (N1.getNode()->getOpcode() == ISD::SUB &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
- // Pattern: (st:isVoid (X86shrd:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, (imm:i8):$src3), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHRD64mri8:isVoid addr:iPTR:$dst, GR64:i64:$src2, (imm:i8):$src3)
- // Pattern complexity = 50 cost = 1 size = 3
- if (N1.getNode()->getOpcode() == X86ISD::SHRD &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi64(N10.getNode())) {
+ // Pattern: (st:isVoid (sub:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SUB8mi:isVoid addr:iPTR:$dst, (imm:i8):$src2)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
@@ -37870,452 +37293,462 @@ SDNode *Select_ISD_STORE(SDNode *N) {
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N12 = N1.getNode()->getOperand(2);
- if (N12.getNode()->getOpcode() == ISD::Constant) {
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
- N1.getValueType() == MVT::i64 &&
- N12.getValueType() == MVT::i8) {
- SDNode *Result = Emit_183(N, X86::SHRD64mri8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_177(N, X86::SUB8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
}
}
- }
- }
- if (N1.getNode()->getOpcode() == X86ISD::ADD &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (X86add_flag:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADD8mi:isVoid addr:iPTR:$dst, (imm:i8):$src2)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_177(N, X86::ADD8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
- }
- }
- // Pattern: (st:isVoid (X86add_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADD16mi:isVoid addr:iPTR:$dst, (imm:i16):$src2)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_178(N, X86::ADD16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (sub:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SUB16mi:isVoid addr:iPTR:$dst, (imm:i16):$src2)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_178(N, X86::SUB16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
+ }
- // Pattern: (st:isVoid (X86add_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (ADD32mi:isVoid addr:iPTR:$dst, (imm:i32):$src2)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::ADD32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (sub:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SUB32mi:isVoid addr:iPTR:$dst, (imm:i32):$src2)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_179(N, X86::SUB32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
}
}
- if (N1.getNode()->getOpcode() == X86ISD::SUB &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (X86sub_flag:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SUB8mi:isVoid addr:iPTR:$dst, (imm:i8):$src2)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_177(N, X86::SUB8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ }
+ if (N1.getNode()->getOpcode() == ISD::SUBE &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
+
+ // Pattern: (st:isVoid (sube:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SBB8mi:isVoid addr:iPTR:$dst, (imm:i8):$src2)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_185(N, X86::SBB8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
+ }
- // Pattern: (st:isVoid (X86sub_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SUB16mi:isVoid addr:iPTR:$dst, (imm:i16):$src2)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_178(N, X86::SUB16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (sube:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SBB16mi:isVoid addr:iPTR:$dst, (imm:i16):$src2)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_186(N, X86::SBB16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
+ }
- // Pattern: (st:isVoid (X86sub_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SUB32mi:isVoid addr:iPTR:$dst, (imm:i32):$src2)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::SUB32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (sube:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SBB32mi:isVoid addr:iPTR:$dst, (imm:i32):$src2)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_187(N, X86::SBB32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
}
}
- if (N1.getNode()->getOpcode() == X86ISD::OR &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (X86or_flag:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (OR8mi:isVoid addr:iPTR:$dst, (imm:i8):$src2)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_177(N, X86::OR8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
+ }
+
+ // Pattern: (st:isVoid (shl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHL64mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (N1.getNode()->getOpcode() == ISD::SHL &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_181(N, X86::SHL64mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
+ }
+ }
+ }
+ }
- // Pattern: (st:isVoid (X86or_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (OR16mi:isVoid addr:iPTR:$dst, (imm:i16):$src2)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_178(N, X86::OR16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
+ // Pattern: (st:isVoid (srl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHR64mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (N1.getNode()->getOpcode() == ISD::SRL &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_181(N, X86::SHR64mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
+ }
+ }
+ }
+ }
- // Pattern: (st:isVoid (X86or_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (OR32mi:isVoid addr:iPTR:$dst, (imm:i32):$src2)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::OR32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
+ // Pattern: (st:isVoid (sra:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SAR64mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (N1.getNode()->getOpcode() == ISD::SRA &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_181(N, X86::SAR64mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
}
- if (N1.getNode()->getOpcode() == X86ISD::XOR &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (X86xor_flag:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (XOR8mi:isVoid addr:iPTR:$dst, (imm:i8):$src2)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_177(N, X86::XOR8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
+ }
+
+ // Pattern: (st:isVoid (rotl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ROL64mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (N1.getNode()->getOpcode() == ISD::ROTL &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_181(N, X86::ROL64mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
+ }
+ }
+ }
+ }
- // Pattern: (st:isVoid (X86xor_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (XOR16mi:isVoid addr:iPTR:$dst, (imm:i16):$src2)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_178(N, X86::XOR16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
+ // Pattern: (st:isVoid (rotr:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ROR64mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (N1.getNode()->getOpcode() == ISD::ROTR &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64 &&
+ N11.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_181(N, X86::ROR64mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
+ }
+ }
+ }
+ }
- // Pattern: (st:isVoid (X86xor_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (XOR32mi:isVoid addr:iPTR:$dst, (imm:i32):$src2)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::XOR32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
+ // Pattern: (st:isVoid (X86shld:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, (imm:i8):$src3), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHLD64mri8:isVoid addr:iPTR:$dst, GR64:i64:$src2, (imm:i8):$src3)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (N1.getNode()->getOpcode() == X86ISD::SHLD &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N12 = N1.getNode()->getOperand(2);
+ if (N12.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64 &&
+ N12.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_183(N, X86::SHLD64mri8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
}
- if (N1.getNode()->getOpcode() == X86ISD::AND &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode())) {
-
- // Pattern: (st:isVoid (X86and_flag:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (AND8mi:isVoid addr:iPTR:$dst, (imm:i8):$src2)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_177(N, X86::AND8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
- }
+ }
+
+ // Pattern: (st:isVoid (X86shrd:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, (imm:i8):$src3), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHRD64mri8:isVoid addr:iPTR:$dst, GR64:i64:$src2, (imm:i8):$src3)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (N1.getNode()->getOpcode() == X86ISD::SHRD &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi64(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N12 = N1.getNode()->getOperand(2);
+ if (N12.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i64 &&
+ N12.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_183(N, X86::SHRD64mri8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
+ }
+ }
+ }
+ }
+ if (N1.getNode()->getOpcode() == X86ISD::ADD &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
- // Pattern: (st:isVoid (X86and_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (AND16mi:isVoid addr:iPTR:$dst, (imm:i16):$src2)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_178(N, X86::AND16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (X86add_flag:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADD8mi:isVoid addr:iPTR:$dst, (imm:i8):$src2)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_177(N, X86::ADD8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
+ }
- // Pattern: (st:isVoid (X86and_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (AND32mi:isVoid addr:iPTR:$dst, (imm:i32):$src2)
- // Pattern complexity = 50 cost = 1 size = 3
- if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getNode()->getOperand(1);
- if (N11.getNode()->getOpcode() == ISD::Constant) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::AND32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (st:isVoid (X86add_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADD16mi:isVoid addr:iPTR:$dst, (imm:i16):$src2)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_178(N, X86::ADD16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
- }
- }
- }
- }
- // Pattern: (st:isVoid (vector_shuffle:v4f32 (ld:v4f32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>>, VR128:v4f32:$src2)<<P:Predicate_movlp>>, addr:iPTR:$src1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (MOVLPSmr:isVoid addr:iPTR:$src1, VR128:v16i8:$src2)
- // Pattern complexity = 48 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedstore(N) &&
- Predicate_store(N)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::VECTOR_SHUFFLE &&
- N1.hasOneUse() &&
- Predicate_movlp(N1.getNode())) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
+ // Pattern: (st:isVoid (X86add_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADD32mi:isVoid addr:iPTR:$dst, (imm:i32):$src2)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
@@ -38324,34 +37757,34 @@ SDNode *Select_ISD_STORE(SDNode *N) {
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_213(N, X86::MOVLPSmr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_179(N, X86::ADD32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
}
}
}
}
}
}
- }
- if ((Subtarget->hasSSE2())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedstore(N) &&
- Predicate_store(N)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::VECTOR_SHUFFLE &&
- N1.hasOneUse() &&
- Predicate_movlp(N1.getNode())) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
+ if (N1.getNode()->getOpcode() == X86ISD::SUB &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
+
+ // Pattern: (st:isVoid (X86sub_flag:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SUB8mi:isVoid addr:iPTR:$dst, (imm:i8):$src2)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
@@ -38360,51 +37793,44 @@ SDNode *Select_ISD_STORE(SDNode *N) {
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
SDValue N11 = N1.getNode()->getOperand(1);
- SDValue N2 = N->getOperand(2);
- if (N101 == N2) {
-
- // Pattern: (st:isVoid (vector_shuffle:v2f64 (ld:v2f64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>>, VR128:v2f64:$src2)<<P:Predicate_movlp>>, addr:iPTR:$src1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (MOVLPDmr:isVoid addr:iPTR:$src1, VR128:v16i8:$src2)
- // Pattern complexity = 48 cost = 1 size = 3
- if (N1.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_213(N, X86::MOVLPDmr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_177(N, X86::SUB8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
+ }
+ }
+ }
- // Pattern: (st:isVoid (vector_shuffle:v2i64 (ld:v2i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>>, VR128:v2i64:$src2)<<P:Predicate_movlp>>, addr:iPTR:$src1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (MOVLPDmr:isVoid addr:iPTR:$src1, VR128:v16i8:$src2)
- // Pattern complexity = 48 cost = 1 size = 3
- if (N1.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_213(N, X86::MOVLPDmr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ // Pattern: (st:isVoid (X86sub_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SUB16mi:isVoid addr:iPTR:$dst, (imm:i16):$src2)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_178(N, X86::SUB16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
}
}
- }
- }
- }
- }
- {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedstore(N) &&
- Predicate_store(N)) {
- SDValue N1 = N->getOperand(1);
- // Pattern: (st:isVoid (X86inc_flag:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (INC8m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 47 cost = 1 size = 2
- if (N1.getNode()->getOpcode() == X86ISD::INC &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadi8(N10.getNode())) {
+ // Pattern: (st:isVoid (X86sub_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SUB32mi:isVoid addr:iPTR:$dst, (imm:i32):$src2)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
@@ -38412,31 +37838,34 @@ SDNode *Select_ISD_STORE(SDNode *N) {
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8 &&
- N10.getValueType() == MVT::i8) {
- SDNode *Result = Emit_206(N, X86::INC8m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_179(N, X86::SUB32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
}
}
}
}
}
+ }
+ if (N1.getNode()->getOpcode() == X86ISD::OR &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
- // Pattern: (st:isVoid (X86dec_flag:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (DEC8m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 47 cost = 1 size = 2
- if (N1.getNode()->getOpcode() == X86ISD::DEC &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
+ // Pattern: (st:isVoid (X86or_flag:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (OR8mi:isVoid addr:iPTR:$dst, (imm:i8):$src2)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_load(N10.getNode()) &&
Predicate_loadi8(N10.getNode())) {
SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
@@ -38445,38 +37874,22 @@ SDNode *Select_ISD_STORE(SDNode *N) {
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i8 &&
- N10.getValueType() == MVT::i8) {
- SDNode *Result = Emit_206(N, X86::DEC8m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_177(N, X86::OR8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
}
}
}
- }
- }
- }
- }
- if ((!Subtarget->is64Bit())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedstore(N) &&
- Predicate_store(N)) {
- SDValue N1 = N->getOperand(1);
- // Pattern: (st:isVoid (X86inc_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (INC16m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 47 cost = 1 size = 2
- if (N1.getNode()->getOpcode() == X86ISD::INC &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_loadi16(N10.getNode())) {
+ // Pattern: (st:isVoid (X86or_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (OR16mi:isVoid addr:iPTR:$dst, (imm:i16):$src2)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
@@ -38484,31 +37897,22 @@ SDNode *Select_ISD_STORE(SDNode *N) {
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N10.getValueType() == MVT::i16) {
- SDNode *Result = Emit_206(N, X86::INC16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_178(N, X86::OR16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
}
}
}
- }
- }
- // Pattern: (st:isVoid (X86dec_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (DEC16m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 47 cost = 1 size = 2
- if (N1.getNode()->getOpcode() == X86ISD::DEC &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_loadi16(N10.getNode())) {
+ // Pattern: (st:isVoid (X86or_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (OR32mi:isVoid addr:iPTR:$dst, (imm:i32):$src2)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
@@ -38516,31 +37920,35 @@ SDNode *Select_ISD_STORE(SDNode *N) {
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N10.getValueType() == MVT::i16) {
- SDNode *Result = Emit_206(N, X86::DEC16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_179(N, X86::OR32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
}
}
}
}
}
+ }
+ if (N1.getNode()->getOpcode() == X86ISD::XOR &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
- // Pattern: (st:isVoid (X86inc_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (INC32m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 47 cost = 1 size = 2
- if (N1.getNode()->getOpcode() == X86ISD::INC &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_loadi32(N10.getNode())) {
+ // Pattern: (st:isVoid (X86xor_flag:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (XOR8mi:isVoid addr:iPTR:$dst, (imm:i8):$src2)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
@@ -38548,31 +37956,22 @@ SDNode *Select_ISD_STORE(SDNode *N) {
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N10.getValueType() == MVT::i32) {
- SDNode *Result = Emit_206(N, X86::INC32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_177(N, X86::XOR8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
}
}
}
- }
- }
- // Pattern: (st:isVoid (X86dec_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (DEC32m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 47 cost = 1 size = 2
- if (N1.getNode()->getOpcode() == X86ISD::DEC &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_loadi32(N10.getNode())) {
+ // Pattern: (st:isVoid (X86xor_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (XOR16mi:isVoid addr:iPTR:$dst, (imm:i16):$src2)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
@@ -38580,38 +37979,22 @@ SDNode *Select_ISD_STORE(SDNode *N) {
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N10.getValueType() == MVT::i32) {
- SDNode *Result = Emit_206(N, X86::DEC32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_178(N, X86::XOR16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
}
}
}
- }
- }
- }
- }
- if ((Subtarget->is64Bit())) {
- SDValue Chain = N->getOperand(0);
- if (Predicate_unindexedstore(N) &&
- Predicate_store(N)) {
- SDValue N1 = N->getOperand(1);
- // Pattern: (st:isVoid (X86inc_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (INC64_16m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 47 cost = 1 size = 2
- if (N1.getNode()->getOpcode() == X86ISD::INC &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_loadi16(N10.getNode())) {
+ // Pattern: (st:isVoid (X86xor_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (XOR32mi:isVoid addr:iPTR:$dst, (imm:i32):$src2)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
@@ -38619,31 +38002,35 @@ SDNode *Select_ISD_STORE(SDNode *N) {
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N10.getValueType() == MVT::i16) {
- SDNode *Result = Emit_206(N, X86::INC64_16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_179(N, X86::XOR32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
}
}
}
}
}
+ }
+ if (N1.getNode()->getOpcode() == X86ISD::AND &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode())) {
- // Pattern: (st:isVoid (X86dec_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (DEC64_16m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 47 cost = 1 size = 2
- if (N1.getNode()->getOpcode() == X86ISD::DEC &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_loadi16(N10.getNode())) {
+ // Pattern: (st:isVoid (X86and_flag:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (AND8mi:isVoid addr:iPTR:$dst, (imm:i8):$src2)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
@@ -38651,31 +38038,22 @@ SDNode *Select_ISD_STORE(SDNode *N) {
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N10.getValueType() == MVT::i16) {
- SDNode *Result = Emit_206(N, X86::DEC64_16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_177(N, X86::AND8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
}
}
}
- }
- }
- // Pattern: (st:isVoid (X86inc_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (INC64_32m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 47 cost = 1 size = 2
- if (N1.getNode()->getOpcode() == X86ISD::INC &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_loadi32(N10.getNode())) {
+ // Pattern: (st:isVoid (X86and_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (AND16mi:isVoid addr:iPTR:$dst, (imm:i16):$src2)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi16(N10.getNode())) {
SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
@@ -38683,31 +38061,22 @@ SDNode *Select_ISD_STORE(SDNode *N) {
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N10.getValueType() == MVT::i32) {
- SDNode *Result = Emit_206(N, X86::INC64_32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_178(N, X86::AND16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
}
}
}
- }
- }
- // Pattern: (st:isVoid (X86dec_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (DEC64_32m:isVoid addr:iPTR:$dst)
- // Pattern complexity = 47 cost = 1 size = 2
- if (N1.getNode()->getOpcode() == X86ISD::DEC &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
- (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_loadi32(N10.getNode())) {
+ // Pattern: (st:isVoid (X86and_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (AND32mi:isVoid addr:iPTR:$dst, (imm:i32):$src2)
+ // Pattern complexity = 50 cost = 1 size = 3
+ if (Predicate_loadi32(N10.getNode())) {
SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
@@ -38715,11 +38084,102 @@ SDNode *Select_ISD_STORE(SDNode *N) {
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N->getOperand(2);
- if (N101 == N2 &&
- N1.getValueType() == MVT::i32 &&
- N10.getValueType() == MVT::i32) {
- SDNode *Result = Emit_206(N, X86::DEC64_32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_179(N, X86::AND32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (vector_shuffle:v4f32 (ld:v4f32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>>, VR128:v4f32:$src2)<<P:Predicate_movlp>>, addr:iPTR:$src1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (MOVLPSmr:isVoid addr:iPTR:$src1, VR128:v16i8:$src2)
+ // Pattern complexity = 48 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedstore(N) &&
+ Predicate_store(N)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::VECTOR_SHUFFLE &&
+ N1.hasOneUse() &&
+ Predicate_movlp(N1.getNode())) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_213(N, X86::MOVLPSmr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedstore(N) &&
+ Predicate_store(N)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::VECTOR_SHUFFLE &&
+ N1.hasOneUse() &&
+ Predicate_movlp(N1.getNode())) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2) {
+
+ // Pattern: (st:isVoid (vector_shuffle:v2f64 (ld:v2f64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>>, VR128:v2f64:$src2)<<P:Predicate_movlp>>, addr:iPTR:$src1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (MOVLPDmr:isVoid addr:iPTR:$src1, VR128:v16i8:$src2)
+ // Pattern complexity = 48 cost = 1 size = 3
+ if (N1.getValueType() == MVT::v2f64) {
+ SDNode *Result = Emit_213(N, X86::MOVLPDmr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+
+ // Pattern: (st:isVoid (vector_shuffle:v2i64 (ld:v2i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>>, VR128:v2i64:$src2)<<P:Predicate_movlp>>, addr:iPTR:$src1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (MOVLPDmr:isVoid addr:iPTR:$src1, VR128:v16i8:$src2)
+ // Pattern complexity = 48 cost = 1 size = 3
+ if (N1.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_213(N, X86::MOVLPDmr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38728,6 +38188,351 @@ SDNode *Select_ISD_STORE(SDNode *N) {
}
}
}
+ }
+ {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedstore(N) &&
+ Predicate_store(N)) {
+ SDValue N1 = N->getOperand(1);
+
+ // Pattern: (st:isVoid (X86inc_flag:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (INC8m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 47 cost = 1 size = 2
+ if (N1.getNode()->getOpcode() == X86ISD::INC &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i8 &&
+ N10.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_206(N, X86::INC8m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86dec_flag:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (DEC8m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 47 cost = 1 size = 2
+ if (N1.getNode()->getOpcode() == X86ISD::DEC &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadi8(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i8 &&
+ N10.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_206(N, X86::DEC8m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((!Subtarget->is64Bit())) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedstore(N) &&
+ Predicate_store(N)) {
+ SDValue N1 = N->getOperand(1);
+
+ // Pattern: (st:isVoid (X86inc_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (INC16m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 47 cost = 1 size = 2
+ if (N1.getNode()->getOpcode() == X86ISD::INC &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16 &&
+ N10.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_206(N, X86::INC16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86dec_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (DEC16m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 47 cost = 1 size = 2
+ if (N1.getNode()->getOpcode() == X86ISD::DEC &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16 &&
+ N10.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_206(N, X86::DEC16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86inc_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (INC32m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 47 cost = 1 size = 2
+ if (N1.getNode()->getOpcode() == X86ISD::INC &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32 &&
+ N10.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_206(N, X86::INC32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86dec_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (DEC32m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 47 cost = 1 size = 2
+ if (N1.getNode()->getOpcode() == X86ISD::DEC &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32 &&
+ N10.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_206(N, X86::DEC32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ if ((Subtarget->is64Bit())) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedstore(N) &&
+ Predicate_store(N)) {
+ SDValue N1 = N->getOperand(1);
+
+ // Pattern: (st:isVoid (X86inc_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (INC64_16m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 47 cost = 1 size = 2
+ if (N1.getNode()->getOpcode() == X86ISD::INC &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16 &&
+ N10.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_206(N, X86::INC64_16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86dec_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (DEC64_16m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 47 cost = 1 size = 2
+ if (N1.getNode()->getOpcode() == X86ISD::DEC &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_loadi16(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i16 &&
+ N10.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_206(N, X86::DEC64_16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86inc_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (INC64_32m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 47 cost = 1 size = 2
+ if (N1.getNode()->getOpcode() == X86ISD::INC &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32 &&
+ N10.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_206(N, X86::INC64_32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86dec_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (DEC64_32m:isVoid addr:iPTR:$dst)
+ // Pattern complexity = 47 cost = 1 size = 2
+ if (N1.getNode()->getOpcode() == X86ISD::DEC &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_loadi32(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N101 == N2 &&
+ N1.getValueType() == MVT::i32 &&
+ N10.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_206(N, X86::DEC64_32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ {
SDValue Chain = N->getOperand(0);
if (Predicate_unindexedstore(N) &&
Predicate_store(N)) {
@@ -41630,7 +41435,7 @@ SDNode *Select_ISD_STORE(SDNode *N) {
N1.getValueType() == MVT::i8 &&
N10.getValueType() == MVT::i64 &&
N101.getValueType() == MVT::i8) {
- SDNode *Result = Emit_210(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOV8mr_NOREX, MVT::i64, MVT::i8, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_210(N, TargetOpcode::COPY_TO_REGCLASS, TargetOpcode::EXTRACT_SUBREG, X86::MOV8mr_NOREX, MVT::i64, MVT::i8, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -41669,7 +41474,7 @@ SDNode *Select_ISD_STORE(SDNode *N) {
// Pattern complexity = 35 cost = 3 size = 3
if (N10.getValueType() == MVT::i32 &&
N101.getValueType() == MVT::i8) {
- SDNode *Result = Emit_211(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOV8mr_NOREX, MVT::i32, MVT::i8, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_211(N, TargetOpcode::COPY_TO_REGCLASS, TargetOpcode::EXTRACT_SUBREG, X86::MOV8mr_NOREX, MVT::i32, MVT::i8, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -41678,7 +41483,7 @@ SDNode *Select_ISD_STORE(SDNode *N) {
// Pattern complexity = 35 cost = 3 size = 3
if (N10.getValueType() == MVT::i16 &&
N101.getValueType() == MVT::i8) {
- SDNode *Result = Emit_212(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOV8mr_NOREX, MVT::i16, MVT::i8, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_212(N, TargetOpcode::COPY_TO_REGCLASS, TargetOpcode::EXTRACT_SUBREG, X86::MOV8mr_NOREX, MVT::i16, MVT::i8, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42945,7 +42750,7 @@ SDNode *Select_ISD_STORE(SDNode *N) {
// Emits: (MOV16mr:isVoid addr:iPTR:$dst, (EXTRACT_SUBREG:i16 GR32:i32:$src, 3:i32))
// Pattern complexity = 22 cost = 2 size = 3
if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_207(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOV16mr, MVT::i16, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_207(N, TargetOpcode::EXTRACT_SUBREG, X86::MOV16mr, MVT::i16, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -42953,7 +42758,7 @@ SDNode *Select_ISD_STORE(SDNode *N) {
// Emits: (MOV16mr:isVoid addr:iPTR:$dst, (EXTRACT_SUBREG:i16 GR64:i64:$src, 3:i32))
// Pattern complexity = 22 cost = 2 size = 3
if (N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_207(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOV16mr, MVT::i16, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_207(N, TargetOpcode::EXTRACT_SUBREG, X86::MOV16mr, MVT::i16, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42970,34 +42775,33 @@ DISABLE_INLINE SDNode *Emit_222(SDNode *N, unsigned Opc0, MVT::SimpleValueType V
return CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::i32, N1);
}
SDNode *Select_ISD_SUB_i8(SDNode *N) {
-
- // Pattern: (sub:i8 GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (SUB8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::SUB8rm, MVT::i8, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
+
+ // Pattern: (sub:i8 GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (SUB8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::SUB8rm, MVT::i8, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
}
}
}
- }
- {
- SDValue N0 = N->getOperand(0);
// Pattern: (sub:i8 0:i8, GR8:i8:$src)
// Emits: (NEG8r:i8 GR8:i8:$src)
@@ -43031,34 +42835,33 @@ SDNode *Select_ISD_SUB_i8(SDNode *N) {
}
SDNode *Select_ISD_SUB_i16(SDNode *N) {
-
- // Pattern: (sub:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (SUB16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::SUB16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
+
+ // Pattern: (sub:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (SUB16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::SUB16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
}
}
}
- }
- {
- SDValue N0 = N->getOperand(0);
// Pattern: (sub:i16 0:i16, GR16:i16:$src)
// Emits: (NEG16r:i16 GR16:i16:$src)
@@ -43104,7 +42907,7 @@ SDNode *Select_ISD_SUB_i32(SDNode *N) {
// Pattern: (sub:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (SUB32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::LOAD &&
@@ -43201,7 +43004,7 @@ SDNode *Select_ISD_SUB_i64(SDNode *N) {
// Pattern: (sub:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (SUB64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::LOAD &&
@@ -43282,43 +43085,42 @@ SDNode *Select_ISD_SUB_i64(SDNode *N) {
}
SDNode *Select_ISD_SUB_v8i8(SDNode *N) {
+ if ((Subtarget->hasMMX())) {
- // Pattern: (sub:v8i8 VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PSUBBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasMMX())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_16(N, X86::MMX_PSUBBrm, MVT::v8i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
+ // Pattern: (sub:v8i8 VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PSUBBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_16(N, X86::MMX_PSUBBrm, MVT::v8i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
}
}
}
}
- }
- // Pattern: (sub:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
- // Emits: (MMX_PSUBBrr:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasMMX())) {
+ // Pattern: (sub:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Emits: (MMX_PSUBBrr:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
SDNode *Result = Emit_15(N, X86::MMX_PSUBBrr, MVT::v8i8);
return Result;
}
@@ -43328,44 +43130,43 @@ SDNode *Select_ISD_SUB_v8i8(SDNode *N) {
}
SDNode *Select_ISD_SUB_v16i8(SDNode *N) {
+ if ((Subtarget->hasSSE2())) {
- // Pattern: (sub:v16i8 VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PSUBBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_16(N, X86::PSUBBrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
+ // Pattern: (sub:v16i8 VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PSUBBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_16(N, X86::PSUBBrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
}
}
}
}
- }
- // Pattern: (sub:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Emits: (PSUBBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
+ // Pattern: (sub:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Emits: (PSUBBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
SDNode *Result = Emit_15(N, X86::PSUBBrr, MVT::v16i8);
return Result;
}
@@ -43375,43 +43176,42 @@ SDNode *Select_ISD_SUB_v16i8(SDNode *N) {
}
SDNode *Select_ISD_SUB_v4i16(SDNode *N) {
+ if ((Subtarget->hasMMX())) {
- // Pattern: (sub:v4i16 VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PSUBWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasMMX())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_16(N, X86::MMX_PSUBWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
+ // Pattern: (sub:v4i16 VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PSUBWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_16(N, X86::MMX_PSUBWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
}
}
}
}
- }
- // Pattern: (sub:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
- // Emits: (MMX_PSUBWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasMMX())) {
+ // Pattern: (sub:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Emits: (MMX_PSUBWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
SDNode *Result = Emit_15(N, X86::MMX_PSUBWrr, MVT::v4i16);
return Result;
}
@@ -43421,44 +43221,43 @@ SDNode *Select_ISD_SUB_v4i16(SDNode *N) {
}
SDNode *Select_ISD_SUB_v8i16(SDNode *N) {
+ if ((Subtarget->hasSSE2())) {
- // Pattern: (sub:v8i16 VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PSUBWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_16(N, X86::PSUBWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
+ // Pattern: (sub:v8i16 VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PSUBWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_16(N, X86::PSUBWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
}
}
}
}
- }
- // Pattern: (sub:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Emits: (PSUBWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
+ // Pattern: (sub:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Emits: (PSUBWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
SDNode *Result = Emit_15(N, X86::PSUBWrr, MVT::v8i16);
return Result;
}
@@ -43468,43 +43267,42 @@ SDNode *Select_ISD_SUB_v8i16(SDNode *N) {
}
SDNode *Select_ISD_SUB_v2i32(SDNode *N) {
+ if ((Subtarget->hasMMX())) {
- // Pattern: (sub:v2i32 VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PSUBDrm:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasMMX())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_16(N, X86::MMX_PSUBDrm, MVT::v2i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
+ // Pattern: (sub:v2i32 VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PSUBDrm:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_16(N, X86::MMX_PSUBDrm, MVT::v2i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
}
}
}
}
- }
- // Pattern: (sub:v2i32 VR64:v2i32:$src1, VR64:v2i32:$src2)
- // Emits: (MMX_PSUBDrr:v2i32 VR64:v2i32:$src1, VR64:v2i32:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasMMX())) {
+ // Pattern: (sub:v2i32 VR64:v2i32:$src1, VR64:v2i32:$src2)
+ // Emits: (MMX_PSUBDrr:v2i32 VR64:v2i32:$src1, VR64:v2i32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
SDNode *Result = Emit_15(N, X86::MMX_PSUBDrr, MVT::v2i32);
return Result;
}
@@ -43514,44 +43312,43 @@ SDNode *Select_ISD_SUB_v2i32(SDNode *N) {
}
SDNode *Select_ISD_SUB_v4i32(SDNode *N) {
+ if ((Subtarget->hasSSE2())) {
- // Pattern: (sub:v4i32 VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PSUBDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_16(N, X86::PSUBDrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
+ // Pattern: (sub:v4i32 VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PSUBDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_16(N, X86::PSUBDrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
}
}
}
}
- }
- // Pattern: (sub:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
- // Emits: (PSUBDrr:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
+ // Pattern: (sub:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Emits: (PSUBDrr:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
SDNode *Result = Emit_15(N, X86::PSUBDrr, MVT::v4i32);
return Result;
}
@@ -43561,43 +43358,42 @@ SDNode *Select_ISD_SUB_v4i32(SDNode *N) {
}
SDNode *Select_ISD_SUB_v1i64(SDNode *N) {
+ if ((Subtarget->hasMMX())) {
- // Pattern: (sub:v1i64 VR64:v1i64:$src1, (bitconvert:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_PSUBQrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasMMX())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_16(N, X86::MMX_PSUBQrm, MVT::v1i64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
+ // Pattern: (sub:v1i64 VR64:v1i64:$src1, (bitconvert:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_PSUBQrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v1i64) {
+ SDNode *Result = Emit_16(N, X86::MMX_PSUBQrm, MVT::v1i64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
}
}
}
}
- }
- // Pattern: (sub:v1i64 VR64:v1i64:$src1, VR64:v1i64:$src2)
- // Emits: (MMX_PSUBQrr:v1i64 VR64:v1i64:$src1, VR64:v1i64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasMMX())) {
+ // Pattern: (sub:v1i64 VR64:v1i64:$src1, VR64:v1i64:$src2)
+ // Emits: (MMX_PSUBQrr:v1i64 VR64:v1i64:$src1, VR64:v1i64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
SDNode *Result = Emit_15(N, X86::MMX_PSUBQrr, MVT::v1i64);
return Result;
}
@@ -43607,39 +43403,38 @@ SDNode *Select_ISD_SUB_v1i64(SDNode *N) {
}
SDNode *Select_ISD_SUB_v2i64(SDNode *N) {
+ if ((Subtarget->hasSSE2())) {
- // Pattern: (sub:v2i64 VR128:v2i64:$src1, (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (PSUBQrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::PSUBQrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
+ // Pattern: (sub:v2i64 VR128:v2i64:$src1, (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (PSUBQrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::PSUBQrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
}
}
}
- }
- // Pattern: (sub:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
- // Emits: (PSUBQrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
+ // Pattern: (sub:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
+ // Emits: (PSUBQrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
SDNode *Result = Emit_15(N, X86::PSUBQrr, MVT::v2i64);
return Result;
}
@@ -43649,13 +43444,13 @@ SDNode *Select_ISD_SUB_v2i64(SDNode *N) {
}
SDNode *Select_ISD_SUBC_i32(SDNode *N) {
-
- // Pattern: (subc:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (SUB32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
+
+ // Pattern: (subc:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (SUB32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
@@ -43674,10 +43469,6 @@ SDNode *Select_ISD_SUBC_i32(SDNode *N) {
}
}
}
- }
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (subc:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
@@ -43704,13 +43495,13 @@ SDNode *Select_ISD_SUBC_i32(SDNode *N) {
}
SDNode *Select_ISD_SUBC_i64(SDNode *N) {
-
- // Pattern: (subc:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (SUB64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
+
+ // Pattern: (subc:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (SUB64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
@@ -43729,10 +43520,6 @@ SDNode *Select_ISD_SUBC_i64(SDNode *N) {
}
}
}
- }
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (subc:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
@@ -43759,13 +43546,13 @@ SDNode *Select_ISD_SUBC_i64(SDNode *N) {
}
SDNode *Select_ISD_SUBE_i8(SDNode *N) {
-
- // Pattern: (sube:i8 GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (SBB8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
+
+ // Pattern: (sube:i8 GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (SBB8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
@@ -43784,14 +43571,10 @@ SDNode *Select_ISD_SUBE_i8(SDNode *N) {
}
}
}
- }
- // Pattern: (sube:i8 GR8:i8:$src1, (imm:i8):$src2)
- // Emits: (SBB8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
+ // Pattern: (sube:i8 GR8:i8:$src1, (imm:i8):$src2)
+ // Emits: (SBB8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_27(N, X86::SBB8ri, MVT::i8);
return Result;
@@ -43806,13 +43589,13 @@ SDNode *Select_ISD_SUBE_i8(SDNode *N) {
}
SDNode *Select_ISD_SUBE_i16(SDNode *N) {
-
- // Pattern: (sube:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (SBB16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
+
+ // Pattern: (sube:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (SBB16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
@@ -43831,10 +43614,6 @@ SDNode *Select_ISD_SUBE_i16(SDNode *N) {
}
}
}
- }
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (sube:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
@@ -43861,13 +43640,13 @@ SDNode *Select_ISD_SUBE_i16(SDNode *N) {
}
SDNode *Select_ISD_SUBE_i32(SDNode *N) {
-
- // Pattern: (sube:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (SBB32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
+
+ // Pattern: (sube:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (SBB32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
@@ -43886,10 +43665,6 @@ SDNode *Select_ISD_SUBE_i32(SDNode *N) {
}
}
}
- }
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (sube:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
@@ -43916,13 +43691,13 @@ SDNode *Select_ISD_SUBE_i32(SDNode *N) {
}
SDNode *Select_ISD_SUBE_i64(SDNode *N) {
-
- // Pattern: (sube:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (SBB64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
+
+ // Pattern: (sube:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (SBB64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
@@ -43941,10 +43716,6 @@ SDNode *Select_ISD_SUBE_i64(SDNode *N) {
}
}
}
- }
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (sube:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
@@ -44035,7 +43806,7 @@ SDNode *Select_ISD_TRUNCATE_i8(SDNode *N) {
// Pattern complexity = 12 cost = 2 size = 0
if (N0.getValueType() == MVT::i16 &&
N01.getValueType() == MVT::i8) {
- SDNode *Result = Emit_226(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, MVT::i32, MVT::i8);
+ SDNode *Result = Emit_226(N, TargetOpcode::COPY_TO_REGCLASS, TargetOpcode::EXTRACT_SUBREG, MVT::i32, MVT::i8);
return Result;
}
@@ -44044,7 +43815,7 @@ SDNode *Select_ISD_TRUNCATE_i8(SDNode *N) {
// Pattern complexity = 12 cost = 2 size = 0
if (N0.getValueType() == MVT::i32 &&
N01.getValueType() == MVT::i8) {
- SDNode *Result = Emit_227(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, MVT::i16, MVT::i8);
+ SDNode *Result = Emit_227(N, TargetOpcode::COPY_TO_REGCLASS, TargetOpcode::EXTRACT_SUBREG, MVT::i16, MVT::i8);
return Result;
}
}
@@ -44058,7 +43829,7 @@ SDNode *Select_ISD_TRUNCATE_i8(SDNode *N) {
{
SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_228(N, TargetInstrInfo::EXTRACT_SUBREG, MVT::i8);
+ SDNode *Result = Emit_228(N, TargetOpcode::EXTRACT_SUBREG, MVT::i8);
return Result;
}
}
@@ -44069,7 +43840,7 @@ SDNode *Select_ISD_TRUNCATE_i8(SDNode *N) {
// Emits: (EXTRACT_SUBREG:i8 GR32:i32:$src, 1:i32)
// Pattern complexity = 3 cost = 1 size = 0
if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_228(N, TargetInstrInfo::EXTRACT_SUBREG, MVT::i8);
+ SDNode *Result = Emit_228(N, TargetOpcode::EXTRACT_SUBREG, MVT::i8);
return Result;
}
@@ -44077,7 +43848,7 @@ SDNode *Select_ISD_TRUNCATE_i8(SDNode *N) {
// Emits: (EXTRACT_SUBREG:i8 GR16:i16:$src, 1:i32)
// Pattern complexity = 3 cost = 1 size = 0
if (N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_228(N, TargetInstrInfo::EXTRACT_SUBREG, MVT::i8);
+ SDNode *Result = Emit_228(N, TargetOpcode::EXTRACT_SUBREG, MVT::i8);
return Result;
}
}
@@ -44088,7 +43859,7 @@ SDNode *Select_ISD_TRUNCATE_i8(SDNode *N) {
// Emits: (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i32 GR32:i32:$src, GR32_ABCD:i32), 1:i32)
// Pattern complexity = 3 cost = 2 size = 0
if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_224(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, MVT::i32, MVT::i8);
+ SDNode *Result = Emit_224(N, TargetOpcode::COPY_TO_REGCLASS, TargetOpcode::EXTRACT_SUBREG, MVT::i32, MVT::i8);
return Result;
}
@@ -44096,7 +43867,7 @@ SDNode *Select_ISD_TRUNCATE_i8(SDNode *N) {
// Emits: (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i16 GR16:i16:$src, GR16_ABCD:i16), 1:i32)
// Pattern complexity = 3 cost = 2 size = 0
if (N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_225(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, MVT::i16, MVT::i8);
+ SDNode *Result = Emit_225(N, TargetOpcode::COPY_TO_REGCLASS, TargetOpcode::EXTRACT_SUBREG, MVT::i16, MVT::i8);
return Result;
}
}
@@ -44117,7 +43888,7 @@ SDNode *Select_ISD_TRUNCATE_i16(SDNode *N) {
// Emits: (EXTRACT_SUBREG:i16 GR32:i32:$src, 3:i32)
// Pattern complexity = 3 cost = 1 size = 0
if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_229(N, TargetInstrInfo::EXTRACT_SUBREG, MVT::i16);
+ SDNode *Result = Emit_229(N, TargetOpcode::EXTRACT_SUBREG, MVT::i16);
return Result;
}
@@ -44125,7 +43896,7 @@ SDNode *Select_ISD_TRUNCATE_i16(SDNode *N) {
// Emits: (EXTRACT_SUBREG:i16 GR64:i64:$src, 3:i32)
// Pattern complexity = 3 cost = 1 size = 0
if (N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_229(N, TargetInstrInfo::EXTRACT_SUBREG, MVT::i16);
+ SDNode *Result = Emit_229(N, TargetOpcode::EXTRACT_SUBREG, MVT::i16);
return Result;
}
@@ -44141,7 +43912,7 @@ DISABLE_INLINE SDNode *Emit_230(SDNode *N, unsigned Opc0, MVT::SimpleValueType V
SDNode *Select_ISD_TRUNCATE_i32(SDNode *N) {
SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_230(N, TargetInstrInfo::EXTRACT_SUBREG, MVT::i32);
+ SDNode *Result = Emit_230(N, TargetOpcode::EXTRACT_SUBREG, MVT::i32);
return Result;
}
@@ -44150,8 +43921,7 @@ SDNode *Select_ISD_TRUNCATE_i32(SDNode *N) {
}
SDNode *Select_ISD_VECTOR_SHUFFLE_v8i8(SDNode *N) {
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasMMX())) {
+ if ((Subtarget->hasMMX())) {
// Pattern: (vector_shuffle:v8i8 VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))<<P:Predicate_mmx_unpckh>>
// Emits: (MMX_PUNPCKHBWrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
@@ -44269,8 +44039,7 @@ DISABLE_INLINE SDNode *Emit_231(SDNode *N, unsigned Opc0, MVT::SimpleValueType V
return CurDAG->SelectNodeTo(N, Opc0, VT0, N1, N0, Tmp3);
}
SDNode *Select_ISD_VECTOR_SHUFFLE_v16i8(SDNode *N) {
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSE2())) {
+ if ((Subtarget->hasSSE2())) {
// Pattern: (vector_shuffle:v16i8 VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))<<P:Predicate_unpckl>>
// Emits: (PUNPCKLBWrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
@@ -44335,8 +44104,6 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v16i8(SDNode *N) {
}
}
}
- }
- if ((Subtarget->hasSSE2())) {
// Pattern: (vector_shuffle:v16i8 VR128:v16i8:$src, (undef:v16i8))<<P:Predicate_unpckl_undef>>
// Emits: (PUNPCKLBWrr:v16i8 VR128:v16i8:$src, VR128:v16i8:$src)
@@ -44416,8 +44183,7 @@ DISABLE_INLINE SDNode *Emit_233(SDNode *N, unsigned Opc0, MVT::SimpleValueType V
return ResNode;
}
SDNode *Select_ISD_VECTOR_SHUFFLE_v4i16(SDNode *N) {
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasMMX())) {
+ if ((Subtarget->hasMMX())) {
// Pattern: (vector_shuffle:v4i16 (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>>), (undef:v4i16))<<P:Predicate_mmx_pshufw>><<X:MMX_SHUFFLE_get_shuf_imm>>:$src2
// Emits: (MMX_PSHUFWmi:v4i16 addr:iPTR:$src1, (MMX_SHUFFLE_get_shuf_imm:i8 (vector_shuffle:v4i16 (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>>), (undef:v4i16)):$src2))
@@ -44616,8 +44382,7 @@ DISABLE_INLINE SDNode *Emit_237(SDNode *N, unsigned Opc0, MVT::SimpleValueType V
return ResNode;
}
SDNode *Select_ISD_VECTOR_SHUFFLE_v8i16(SDNode *N) {
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSE2())) {
+ if ((Subtarget->hasSSE2())) {
// Pattern: (vector_shuffle:v8i16 (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (undef:v8i16))<<P:Predicate_pshufhw>><<X:SHUFFLE_get_pshufhw_imm>>:$src2
// Emits: (PSHUFHWmi:v8i16 addr:iPTR:$src1, (SHUFFLE_get_pshufhw_imm:i8 (vector_shuffle:v8i16 (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (undef:v8i16)):$src2))
@@ -44750,8 +44515,6 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v8i16(SDNode *N) {
}
}
}
- }
- if ((Subtarget->hasSSE2())) {
// Pattern: (vector_shuffle:v8i16 VR128:v8i16:$src, (undef:v8i16))<<P:Predicate_unpckl_undef>>
// Emits: (PUNPCKLWDrr:v8i16 VR128:v16i8:$src, VR128:v16i8:$src)
@@ -44834,8 +44597,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v8i16(SDNode *N) {
}
SDNode *Select_ISD_VECTOR_SHUFFLE_v2i32(SDNode *N) {
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasMMX())) {
+ if ((Subtarget->hasMMX())) {
// Pattern: (vector_shuffle:v2i32 VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))<<P:Predicate_mmx_unpckh>>
// Emits: (MMX_PUNPCKHDQrm:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
@@ -44967,7 +44729,18 @@ DISABLE_INLINE SDNode *Emit_239(SDNode *N, unsigned Opc0, MVT::SimpleValueType V
ReplaceUses(SDValue(N00.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_240(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
+DISABLE_INLINE SDNode *Emit_240(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue Ops0[] = { N0, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Chain10 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
+ ReplaceUses(SDValue(N10.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_241(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
SDValue N0 = N->getOperand(0);
SDValue N00 = N0.getNode()->getOperand(0);
SDValue Chain00 = N00.getNode()->getOperand(0);
@@ -44981,13 +44754,13 @@ DISABLE_INLINE SDNode *Emit_240(SDNode *N, unsigned Opc0, MVT::SimpleValueType V
ReplaceUses(SDValue(N00.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_241(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_242(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
SDValue Tmp3 = Transform_SHUFFLE_get_shuf_imm(SDValue(N, 0).getNode());
return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, N1, Tmp3);
}
-DISABLE_INLINE SDNode *Emit_242(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+DISABLE_INLINE SDNode *Emit_243(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
SDValue N10 = N1.getNode()->getOperand(0);
@@ -45003,145 +44776,108 @@ DISABLE_INLINE SDNode *Emit_242(SDNode *N, unsigned Opc0, MVT::SimpleValueType V
return ResNode;
}
SDNode *Select_ISD_VECTOR_SHUFFLE_v4i32(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
- if ((Subtarget->hasSSE3())) {
+ if ((Subtarget->hasSSE3())) {
- // Pattern: (vector_shuffle:v4i32 (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (undef:v4i32))<<P:Predicate_movshdup>>
- // Emits: (MOVSHDUPrm:v4i32 addr:iPTR:$src)
- // Pattern complexity = 52 cost = 1 size = 3
- if (Predicate_movshdup(N)) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N0.hasOneUse()) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::LOAD &&
- N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
- SDValue Chain00 = N00.getNode()->getOperand(0);
- if (Predicate_unindexedload(N00.getNode()) &&
- Predicate_load(N00.getNode()) &&
- Predicate_memop(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF &&
- N00.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_240(N, X86::MOVSHDUPrm, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
- }
+ // Pattern: (vector_shuffle:v4i32 (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (undef:v4i32))<<P:Predicate_movshdup>>
+ // Emits: (MOVSHDUPrm:v4i32 addr:iPTR:$src)
+ // Pattern complexity = 52 cost = 1 size = 3
+ if (Predicate_movshdup(N)) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N0.hasOneUse()) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::LOAD &&
+ N00.hasOneUse() &&
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
+ SDValue Chain00 = N00.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N00.getNode()) &&
+ Predicate_load(N00.getNode()) &&
+ Predicate_memop(N00.getNode())) {
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF &&
+ N00.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_241(N, X86::MOVSHDUPrm, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
}
}
}
}
}
+ }
- // Pattern: (vector_shuffle:v4i32 (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (undef:v4i32))<<P:Predicate_movsldup>>
- // Emits: (MOVSLDUPrm:v4i32 addr:iPTR:$src)
- // Pattern complexity = 52 cost = 1 size = 3
- if (Predicate_movsldup(N)) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N0.hasOneUse()) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::LOAD &&
- N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
- SDValue Chain00 = N00.getNode()->getOperand(0);
- if (Predicate_unindexedload(N00.getNode()) &&
- Predicate_load(N00.getNode()) &&
- Predicate_memop(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF &&
- N00.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_240(N, X86::MOVSLDUPrm, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
- }
+ // Pattern: (vector_shuffle:v4i32 (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (undef:v4i32))<<P:Predicate_movsldup>>
+ // Emits: (MOVSLDUPrm:v4i32 addr:iPTR:$src)
+ // Pattern complexity = 52 cost = 1 size = 3
+ if (Predicate_movsldup(N)) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N0.hasOneUse()) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::LOAD &&
+ N00.hasOneUse() &&
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
+ SDValue Chain00 = N00.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N00.getNode()) &&
+ Predicate_load(N00.getNode()) &&
+ Predicate_memop(N00.getNode())) {
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF &&
+ N00.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_241(N, X86::MOVSLDUPrm, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
}
}
}
}
}
}
- if ((Subtarget->hasSSE2())) {
-
- // Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src1, (ld:v4i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)<<P:Predicate_movlp>>
- // Emits: (MOVLPSrm:v4i32 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 46 cost = 1 size = 3
- if (Predicate_movlp(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::MOVLPSrm, MVT::v4i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
+ }
+ if ((Subtarget->hasSSE2())) {
- // Pattern: (vector_shuffle:v4i32 (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (undef:v4i32))<<P:Predicate_pshufd>><<X:SHUFFLE_get_shuf_imm>>:$src2
- // Emits: (PSHUFDmi:v4i32 addr:iPTR:$src1, (SHUFFLE_get_shuf_imm:i8 (vector_shuffle:v4i32 (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (undef:v4i32)):$src2))
- // Pattern complexity = 37 cost = 1 size = 3
- if (Predicate_pshufd(N)) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N0.hasOneUse()) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::LOAD &&
- N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
- SDValue Chain00 = N00.getNode()->getOperand(0);
- if (Predicate_unindexedload(N00.getNode()) &&
- Predicate_load(N00.getNode()) &&
- Predicate_memop(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF &&
- N00.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_239(N, X86::PSHUFDmi, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
- }
- }
- }
+ // Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src1, (ld:v4i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)<<P:Predicate_movlp>>
+ // Emits: (MOVLPSrm:v4i32 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 46 cost = 1 size = 3
+ if (Predicate_movlp(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::MOVLPSrm, MVT::v4i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
}
}
}
}
- // Pattern: (vector_shuffle:v4i32 (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (undef:v4i32))<<P:Predicate_movddup>>
- // Emits: (MOVDDUPrm:v4i32 addr:iPTR:$src)
+ // Pattern: (vector_shuffle:v4i32 (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (undef:v4i32))<<P:Predicate_pshufd>><<X:SHUFFLE_get_shuf_imm>>:$src2
+ // Emits: (PSHUFDmi:v4i32 addr:iPTR:$src1, (SHUFFLE_get_shuf_imm:i8 (vector_shuffle:v4i32 (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (undef:v4i32)):$src2))
// Pattern complexity = 37 cost = 1 size = 3
- if ((Subtarget->hasSSE3()) &&
- Predicate_movddup(N)) {
+ if (Predicate_pshufd(N)) {
SDValue N0 = N->getOperand(0);
if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N0.hasOneUse()) {
@@ -45163,7 +44899,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4i32(SDNode *N) {
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::UNDEF &&
N00.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_240(N, X86::MOVDDUPrm, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_239(N, X86::PSHUFDmi, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
}
@@ -45171,133 +44907,168 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4i32(SDNode *N) {
}
}
}
- if ((Subtarget->hasSSE2())) {
+ }
- // Pattern: (vector_shuffle:v4i32 (bitconvert:v4i32 (ld:v4f32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (undef:v4i32))<<P:Predicate_pshufd>><<X:SHUFFLE_get_shuf_imm>>:$src2
- // Emits: (PSHUFDmi:v4i32 addr:iPTR:$src1, (SHUFFLE_get_shuf_imm:i8 VR128:i8:$src2))
- // Pattern complexity = 32 cost = 1 size = 3
- if (Predicate_pshufd(N)) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N0.hasOneUse()) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::LOAD &&
- N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
- SDValue Chain00 = N00.getNode()->getOperand(0);
- if (Predicate_unindexedload(N00.getNode()) &&
- Predicate_load(N00.getNode()) &&
- Predicate_memop(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF &&
- N00.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_239(N, X86::PSHUFDmi, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
- }
- }
+ // Pattern: (vector_shuffle:v4i32 (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (undef:v4i32))<<P:Predicate_movddup>>
+ // Emits: (MOVDDUPrm:v4i32 addr:iPTR:$src)
+ // Pattern complexity = 37 cost = 1 size = 3
+ if ((Subtarget->hasSSE3()) &&
+ Predicate_movddup(N)) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N0.hasOneUse()) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::LOAD &&
+ N00.hasOneUse() &&
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
+ SDValue Chain00 = N00.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N00.getNode()) &&
+ Predicate_load(N00.getNode()) &&
+ Predicate_memop(N00.getNode())) {
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF &&
+ N00.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_241(N, X86::MOVDDUPrm, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
}
}
}
}
+ }
+ }
+ if ((Subtarget->hasSSE2())) {
- // Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))<<P:Predicate_unpckl>>
- // Emits: (PUNPCKLDQrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 29 cost = 1 size = 3
- if (Predicate_unpckl(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_16(N, X86::PUNPCKLDQrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ // Pattern: (vector_shuffle:v4i32 (bitconvert:v4i32 (ld:v4f32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (undef:v4i32))<<P:Predicate_pshufd>><<X:SHUFFLE_get_shuf_imm>>:$src2
+ // Emits: (PSHUFDmi:v4i32 addr:iPTR:$src1, (SHUFFLE_get_shuf_imm:i8 VR128:i8:$src2))
+ // Pattern complexity = 32 cost = 1 size = 3
+ if (Predicate_pshufd(N)) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N0.hasOneUse()) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::LOAD &&
+ N00.hasOneUse() &&
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
+ SDValue Chain00 = N00.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N00.getNode()) &&
+ Predicate_load(N00.getNode()) &&
+ Predicate_memop(N00.getNode())) {
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF &&
+ N00.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_239(N, X86::PSHUFDmi, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
}
}
}
}
+ }
- // Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))<<P:Predicate_unpckh>>
- // Emits: (PUNPCKHDQrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 29 cost = 1 size = 3
- if (Predicate_unpckh(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_16(N, X86::PUNPCKHDQrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))<<P:Predicate_unpckl>>
+ // Emits: (PUNPCKLDQrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 29 cost = 1 size = 3
+ if (Predicate_unpckl(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_16(N, X86::PUNPCKLDQrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))<<P:Predicate_shufp>><<X:SHUFFLE_get_shuf_imm>>:$src3
- // Emits: (SHUFPSrmi:v4i32 VR128:v16i8:$src1, addr:iPTR:$src2, (SHUFFLE_get_shuf_imm:i8 VR128:i8:$src3))
- // Pattern complexity = 29 cost = 1 size = 3
- if (Predicate_shufp(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_242(N, X86::SHUFPSrmi, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))<<P:Predicate_unpckh>>
+ // Emits: (PUNPCKHDQrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 29 cost = 1 size = 3
+ if (Predicate_unpckh(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_16(N, X86::PUNPCKHDQrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))<<P:Predicate_shufp>><<X:SHUFFLE_get_shuf_imm>>:$src3
+ // Emits: (SHUFPSrmi:v4i32 VR128:v16i8:$src1, addr:iPTR:$src2, (SHUFFLE_get_shuf_imm:i8 VR128:i8:$src3))
+ // Pattern complexity = 29 cost = 1 size = 3
+ if (Predicate_shufp(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_243(N, X86::SHUFPSrmi, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
@@ -45305,6 +45076,34 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4i32(SDNode *N) {
}
}
+ // Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src1, (bitconvert:v4i32 (X86vzload:v2i64 addr:iPTR:$src2)))<<P:Predicate_movlhps>>
+ // Emits: (MOVHPSrm:v4i32 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if (Predicate_movlhps(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == X86ISD::VZEXT_LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_240(N, X86::MOVHPSrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
+ }
+ }
+ }
+
// Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src1, (undef:v4i32))<<P:Predicate_movhlps_undef>>
// Emits: (MOVHLPSrr:v4i32 VR128:v16i8:$src1, VR128:v16i8:$src1)
// Pattern complexity = 27 cost = 1 size = 3
@@ -45469,7 +45268,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4i32(SDNode *N) {
// Emits: (SHUFPSrri:v4i32 VR128:v16i8:$src1, VR128:v16i8:$src2, (SHUFFLE_get_shuf_imm:i8 VR128:i8:$src3))
// Pattern complexity = 4 cost = 1 size = 3
if (Predicate_shufp(N)) {
- SDNode *Result = Emit_241(N, X86::SHUFPSrri, MVT::v4i32);
+ SDNode *Result = Emit_242(N, X86::SHUFPSrri, MVT::v4i32);
return Result;
}
}
@@ -45478,14 +45277,14 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4i32(SDNode *N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_243(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_244(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
SDValue N10 = N1.getNode()->getOperand(0);
SDValue N100 = N10.getNode()->getOperand(0);
return CurDAG->SelectNodeTo(N, Opc0, VT0, N100);
}
-DISABLE_INLINE SDNode *Emit_244(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+DISABLE_INLINE SDNode *Emit_245(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
SDValue N0 = N->getOperand(0);
SDValue Chain0 = N0.getNode()->getOperand(0);
SDValue N01 = N0.getNode()->getOperand(1);
@@ -45498,67 +45297,65 @@ DISABLE_INLINE SDNode *Emit_244(SDNode *N, unsigned Opc0, MVT::SimpleValueType V
ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_245(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_246(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
SDValue Tmp3 = Transform_SHUFFLE_get_shuf_imm(SDValue(N, 0).getNode());
return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, N0, Tmp3);
}
SDNode *Select_ISD_VECTOR_SHUFFLE_v2i64(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
- // Pattern: (vector_shuffle:v2i64 VR128:v2i64:$src1, (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)<<P:Predicate_movlp>>
- // Emits: (MOVLPDrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 46 cost = 1 size = 3
- if ((Subtarget->hasSSE2()) &&
- Predicate_movlp(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::MOVLPDrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
+ // Pattern: (vector_shuffle:v2i64 VR128:v2i64:$src1, (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)<<P:Predicate_movlp>>
+ // Emits: (MOVLPDrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 46 cost = 1 size = 3
+ if ((Subtarget->hasSSE2()) &&
+ Predicate_movlp(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::MOVLPDrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
}
}
}
+ }
- // Pattern: (vector_shuffle:v2i64 (ld:v2i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (undef:v2i64))<<P:Predicate_movddup>>
- // Emits: (MOVDDUPrm:v2i64 addr:iPTR:$src)
- // Pattern complexity = 34 cost = 1 size = 3
- if ((Subtarget->hasSSE3()) &&
- Predicate_movddup(N)) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_244(N, X86::MOVDDUPrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
+ // Pattern: (vector_shuffle:v2i64 (ld:v2i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (undef:v2i64))<<P:Predicate_movddup>>
+ // Emits: (MOVDDUPrm:v2i64 addr:iPTR:$src)
+ // Pattern complexity = 34 cost = 1 size = 3
+ if ((Subtarget->hasSSE3()) &&
+ Predicate_movddup(N)) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_245(N, X86::MOVDDUPrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
}
}
}
@@ -45577,8 +45374,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2i64(SDNode *N) {
return Result;
}
}
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSE2())) {
+ if ((Subtarget->hasSSE2())) {
// Pattern: (vector_shuffle:v2i64 VR128:v2i64:$src1, (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)<<P:Predicate_unpckl>>
// Emits: (PUNPCKLQDQrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
@@ -45633,8 +45429,6 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2i64(SDNode *N) {
}
}
}
- }
- if ((Subtarget->hasSSE2())) {
// Pattern: (vector_shuffle:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)<<P:Predicate_movl>>
// Emits: (MOVLPDrr:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src2)
@@ -45682,7 +45476,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2i64(SDNode *N) {
SDValue N100 = N10.getNode()->getOperand(0);
if (N10.getValueType() == MVT::i64 &&
N100.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_243(N, X86::MMX_MOVQ2DQrr, MVT::v2i64);
+ SDNode *Result = Emit_244(N, X86::MMX_MOVQ2DQrr, MVT::v2i64);
return Result;
}
}
@@ -45697,7 +45491,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2i64(SDNode *N) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_245(N, X86::SHUFPDrri, MVT::v2i64);
+ SDNode *Result = Emit_246(N, X86::SHUFPDrri, MVT::v2i64);
return Result;
}
}
@@ -45722,7 +45516,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2i64(SDNode *N) {
// Emits: (SHUFPDrri:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src2, (SHUFFLE_get_shuf_imm:i8 VR128:i8:$src3))
// Pattern complexity = 4 cost = 1 size = 3
if (Predicate_shufp(N)) {
- SDNode *Result = Emit_241(N, X86::SHUFPDrri, MVT::v2i64);
+ SDNode *Result = Emit_242(N, X86::SHUFPDrri, MVT::v2i64);
return Result;
}
}
@@ -45731,7 +45525,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2i64(SDNode *N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_246(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1001_0, SDValue &CPTmpN1001_1, SDValue &CPTmpN1001_2, SDValue &CPTmpN1001_3, SDValue &CPTmpN1001_4) {
+DISABLE_INLINE SDNode *Emit_247(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1001_0, SDValue &CPTmpN1001_1, SDValue &CPTmpN1001_2, SDValue &CPTmpN1001_3, SDValue &CPTmpN1001_4) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
SDValue N10 = N1.getNode()->getOperand(0);
@@ -45746,7 +45540,7 @@ DISABLE_INLINE SDNode *Emit_246(SDNode *N, unsigned Opc0, MVT::SimpleValueType V
ReplaceUses(SDValue(N100.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_247(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
+DISABLE_INLINE SDNode *Emit_248(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
SDValue Chain1 = N1.getNode()->getOperand(0);
@@ -45760,262 +45554,260 @@ DISABLE_INLINE SDNode *Emit_247(SDNode *N, unsigned Opc0, MVT::SimpleValueType V
ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_248(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_249(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
SDValue Tmp3 = Transform_SHUFFLE_get_shuf_imm(SDValue(N, 0).getNode());
return CurDAG->SelectNodeTo(N, Opc0, VT0, N1, N0, Tmp3);
}
SDNode *Select_ISD_VECTOR_SHUFFLE_v4f32(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
- if ((Subtarget->hasSSE1())) {
+ if ((Subtarget->hasSSE1())) {
- // Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src1, (bitconvert:v4f32 (scalar_to_vector:v2f64 (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>)))<<P:Predicate_movlp>>
- // Emits: (MOVLPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 52 cost = 1 size = 3
- if (Predicate_movlp(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::LOAD &&
- N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N)) {
- SDValue Chain100 = N100.getNode()->getOperand(0);
- if (Predicate_unindexedload(N100.getNode()) &&
- Predicate_load(N100.getNode()) &&
- Predicate_loadf64(N100.getNode())) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue CPTmpN1001_0;
- SDValue CPTmpN1001_1;
- SDValue CPTmpN1001_2;
- SDValue CPTmpN1001_3;
- SDValue CPTmpN1001_4;
- if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
- N10.getValueType() == MVT::v2f64 &&
- N100.getValueType() == MVT::f64) {
- SDNode *Result = Emit_246(N, X86::MOVLPSrm, MVT::v4f32, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
- return Result;
- }
+ // Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src1, (bitconvert:v4f32 (scalar_to_vector:v2f64 (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>)))<<P:Predicate_movlp>>
+ // Emits: (MOVLPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 52 cost = 1 size = 3
+ if (Predicate_movlp(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::LOAD &&
+ N100.hasOneUse() &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N)) {
+ SDValue Chain100 = N100.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N100.getNode()) &&
+ Predicate_load(N100.getNode()) &&
+ Predicate_loadf64(N100.getNode())) {
+ SDValue N1001 = N100.getNode()->getOperand(1);
+ SDValue CPTmpN1001_0;
+ SDValue CPTmpN1001_1;
+ SDValue CPTmpN1001_2;
+ SDValue CPTmpN1001_3;
+ SDValue CPTmpN1001_4;
+ if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
+ N10.getValueType() == MVT::v2f64 &&
+ N100.getValueType() == MVT::f64) {
+ SDNode *Result = Emit_247(N, X86::MOVLPSrm, MVT::v4f32, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ return Result;
}
}
}
}
}
+ }
- // Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src1, (bitconvert:v4f32 (scalar_to_vector:v2f64 (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>)))<<P:Predicate_movlhps>>
- // Emits: (MOVHPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 52 cost = 1 size = 3
- if (Predicate_movlhps(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getNode()->getOperand(0);
- if (N100.getNode()->getOpcode() == ISD::LOAD &&
- N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N)) {
- SDValue Chain100 = N100.getNode()->getOperand(0);
- if (Predicate_unindexedload(N100.getNode()) &&
- Predicate_load(N100.getNode()) &&
- Predicate_loadf64(N100.getNode())) {
- SDValue N1001 = N100.getNode()->getOperand(1);
- SDValue CPTmpN1001_0;
- SDValue CPTmpN1001_1;
- SDValue CPTmpN1001_2;
- SDValue CPTmpN1001_3;
- SDValue CPTmpN1001_4;
- if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
- N10.getValueType() == MVT::v2f64 &&
- N100.getValueType() == MVT::f64) {
- SDNode *Result = Emit_246(N, X86::MOVHPSrm, MVT::v4f32, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
- return Result;
- }
+ // Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src1, (bitconvert:v4f32 (scalar_to_vector:v2f64 (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>)))<<P:Predicate_movlhps>>
+ // Emits: (MOVHPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 52 cost = 1 size = 3
+ if (Predicate_movlhps(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N10.hasOneUse()) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::LOAD &&
+ N100.hasOneUse() &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N)) {
+ SDValue Chain100 = N100.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N100.getNode()) &&
+ Predicate_load(N100.getNode()) &&
+ Predicate_loadf64(N100.getNode())) {
+ SDValue N1001 = N100.getNode()->getOperand(1);
+ SDValue CPTmpN1001_0;
+ SDValue CPTmpN1001_1;
+ SDValue CPTmpN1001_2;
+ SDValue CPTmpN1001_3;
+ SDValue CPTmpN1001_4;
+ if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
+ N10.getValueType() == MVT::v2f64 &&
+ N100.getValueType() == MVT::f64) {
+ SDNode *Result = Emit_247(N, X86::MOVHPSrm, MVT::v4f32, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ return Result;
}
}
}
}
}
+ }
- // Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)<<P:Predicate_movlp>>
- // Emits: (MOVLPSrm:v4f32 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 46 cost = 1 size = 3
- if (Predicate_movlp(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::MOVLPSrm, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
+ // Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)<<P:Predicate_movlp>>
+ // Emits: (MOVLPSrm:v4f32 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 46 cost = 1 size = 3
+ if (Predicate_movlp(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::MOVLPSrm, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (vector_shuffle:v4f32 (bitconvert:v4f32 (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (undef:v4f32))<<P:Predicate_movddup>>
- // Emits: (MOVDDUPrm:v4f32 addr:iPTR:$src)
- // Pattern complexity = 37 cost = 1 size = 3
- if ((Subtarget->hasSSE3()) &&
- Predicate_movddup(N)) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N0.hasOneUse()) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::LOAD &&
- N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
- SDValue Chain00 = N00.getNode()->getOperand(0);
- if (Predicate_unindexedload(N00.getNode()) &&
- Predicate_load(N00.getNode()) &&
- Predicate_memop(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF &&
- N00.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_240(N, X86::MOVDDUPrm, MVT::v4f32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
- }
+ // Pattern: (vector_shuffle:v4f32 (bitconvert:v4f32 (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (undef:v4f32))<<P:Predicate_movddup>>
+ // Emits: (MOVDDUPrm:v4f32 addr:iPTR:$src)
+ // Pattern complexity = 37 cost = 1 size = 3
+ if ((Subtarget->hasSSE3()) &&
+ Predicate_movddup(N)) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N0.hasOneUse()) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::LOAD &&
+ N00.hasOneUse() &&
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
+ SDValue Chain00 = N00.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N00.getNode()) &&
+ Predicate_load(N00.getNode()) &&
+ Predicate_memop(N00.getNode())) {
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF &&
+ N00.getValueType() == MVT::v2f64) {
+ SDNode *Result = Emit_241(N, X86::MOVDDUPrm, MVT::v4f32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
}
}
}
}
}
- if ((Subtarget->hasSSE1())) {
+ }
+ if ((Subtarget->hasSSE1())) {
- // Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)<<P:Predicate_unpckh>>
- // Emits: (UNPCKHPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 36 cost = 1 size = 3
- if (Predicate_unpckh(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::UNPCKHPSrm, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
+ // Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)<<P:Predicate_unpckh>>
+ // Emits: (UNPCKHPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 36 cost = 1 size = 3
+ if (Predicate_unpckh(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::UNPCKHPSrm, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
}
}
}
+ }
- // Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)<<P:Predicate_unpckl>>
- // Emits: (UNPCKLPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 36 cost = 1 size = 3
- if (Predicate_unpckl(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::UNPCKLPSrm, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
+ // Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)<<P:Predicate_unpckl>>
+ // Emits: (UNPCKLPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 36 cost = 1 size = 3
+ if (Predicate_unpckl(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::UNPCKLPSrm, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
}
}
}
}
- if ((Subtarget->hasSSE3())) {
+ }
+ if ((Subtarget->hasSSE3())) {
- // Pattern: (vector_shuffle:v4f32 (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (undef:v4f32))<<P:Predicate_movshdup>>
- // Emits: (MOVSHDUPrm:v4f32 addr:iPTR:$src)
- // Pattern complexity = 29 cost = 1 size = 3
- if (Predicate_movshdup(N)) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_244(N, X86::MOVSHDUPrm, MVT::v4f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
+ // Pattern: (vector_shuffle:v4f32 (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (undef:v4f32))<<P:Predicate_movshdup>>
+ // Emits: (MOVSHDUPrm:v4f32 addr:iPTR:$src)
+ // Pattern complexity = 29 cost = 1 size = 3
+ if (Predicate_movshdup(N)) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_245(N, X86::MOVSHDUPrm, MVT::v4f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (vector_shuffle:v4f32 (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (undef:v4f32))<<P:Predicate_movsldup>>
- // Emits: (MOVSLDUPrm:v4f32 addr:iPTR:$src)
- // Pattern complexity = 29 cost = 1 size = 3
- if (Predicate_movsldup(N)) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_244(N, X86::MOVSLDUPrm, MVT::v4f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
+ // Pattern: (vector_shuffle:v4f32 (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (undef:v4f32))<<P:Predicate_movsldup>>
+ // Emits: (MOVSLDUPrm:v4f32 addr:iPTR:$src)
+ // Pattern complexity = 29 cost = 1 size = 3
+ if (Predicate_movsldup(N)) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_245(N, X86::MOVSLDUPrm, MVT::v4f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
}
}
}
@@ -46047,36 +45839,34 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4f32(SDNode *N) {
return Result;
}
}
+ if ((Subtarget->hasSSE1())) {
- // Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)<<P:Predicate_shufp>><<X:SHUFFLE_get_shuf_imm>>:$src3
- // Emits: (SHUFPSrmi:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2, (SHUFFLE_get_shuf_imm:i8 (vector_shuffle:v4f32 VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>):$src3))
- // Pattern complexity = 26 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSE1()) &&
- Predicate_shufp(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_247(N, X86::SHUFPSrmi, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
+ // Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)<<P:Predicate_shufp>><<X:SHUFFLE_get_shuf_imm>>:$src3
+ // Emits: (SHUFPSrmi:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2, (SHUFFLE_get_shuf_imm:i8 (vector_shuffle:v4f32 VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>):$src3))
+ // Pattern complexity = 26 cost = 1 size = 3
+ if (Predicate_shufp(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_248(N, X86::SHUFPSrmi, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
}
}
}
- }
- if ((Subtarget->hasSSE1())) {
// Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)<<P:Predicate_movlhps>>
// Emits: (MOVLHPSrr:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
@@ -46237,7 +46027,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4f32(SDNode *N) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_245(N, X86::SHUFPSrri, MVT::v4f32);
+ SDNode *Result = Emit_246(N, X86::SHUFPSrri, MVT::v4f32);
return Result;
}
}
@@ -46246,7 +46036,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4f32(SDNode *N) {
// Emits: (SHUFPSrri:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2, (SHUFFLE_get_shuf_imm:i8 (vector_shuffle:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2):$src3))
// Pattern complexity = 4 cost = 1 size = 3
if (Predicate_shufp(N)) {
- SDNode *Result = Emit_241(N, X86::SHUFPSrri, MVT::v4f32);
+ SDNode *Result = Emit_242(N, X86::SHUFPSrri, MVT::v4f32);
return Result;
}
@@ -46254,7 +46044,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4f32(SDNode *N) {
// Emits: (SHUFPSrri:v4f32 VR128:v16i8:$src2, VR128:v16i8:$src1, (SHUFFLE_get_shuf_imm:i8 VR128:i8:$src3))
// Pattern complexity = 4 cost = 1 size = 3
if (Predicate_movlp(N)) {
- SDNode *Result = Emit_248(N, X86::SHUFPSrri, MVT::v4f32);
+ SDNode *Result = Emit_249(N, X86::SHUFPSrri, MVT::v4f32);
return Result;
}
}
@@ -46263,7 +46053,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4f32(SDNode *N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_249(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0001_0, SDValue &CPTmpN0001_1, SDValue &CPTmpN0001_2, SDValue &CPTmpN0001_3, SDValue &CPTmpN0001_4) {
+DISABLE_INLINE SDNode *Emit_250(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0001_0, SDValue &CPTmpN0001_1, SDValue &CPTmpN0001_2, SDValue &CPTmpN0001_3, SDValue &CPTmpN0001_4) {
SDValue N0 = N->getOperand(0);
SDValue N00 = N0.getNode()->getOperand(0);
SDValue N000 = N00.getNode()->getOperand(0);
@@ -46279,256 +46069,255 @@ DISABLE_INLINE SDNode *Emit_249(SDNode *N, unsigned Opc0, MVT::SimpleValueType V
return ResNode;
}
SDNode *Select_ISD_VECTOR_SHUFFLE_v2f64(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
- if ((Subtarget->hasSSE2())) {
+ if ((Subtarget->hasSSE2())) {
- // Pattern: (vector_shuffle:v2f64 VR128:v2f64:$src1, (scalar_to_vector:v2f64 (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>))<<P:Predicate_movlp>>
- // Emits: (MOVLPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 49 cost = 1 size = 3
- if (Predicate_movlp(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadf64(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::f64) {
- SDNode *Result = Emit_16(N, X86::MOVLPDrm, MVT::v2f64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (vector_shuffle:v2f64 VR128:v2f64:$src1, (scalar_to_vector:v2f64 (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>))<<P:Predicate_movlp>>
+ // Emits: (MOVLPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 49 cost = 1 size = 3
+ if (Predicate_movlp(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadf64(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::f64) {
+ SDNode *Result = Emit_16(N, X86::MOVLPDrm, MVT::v2f64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (vector_shuffle:v2f64 VR128:v2f64:$src1, (scalar_to_vector:v2f64 (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>))<<P:Predicate_movlhps>>
- // Emits: (MOVHPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 49 cost = 1 size = 3
- if (Predicate_movlhps(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_loadf64(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::f64) {
- SDNode *Result = Emit_16(N, X86::MOVHPDrm, MVT::v2f64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
- }
+ // Pattern: (vector_shuffle:v2f64 VR128:v2f64:$src1, (scalar_to_vector:v2f64 (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>))<<P:Predicate_movlhps>>
+ // Emits: (MOVHPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 49 cost = 1 size = 3
+ if (Predicate_movlhps(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_loadf64(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::f64) {
+ SDNode *Result = Emit_16(N, X86::MOVHPDrm, MVT::v2f64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (vector_shuffle:v2f64 VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)<<P:Predicate_movlp>>
- // Emits: (MOVLPDrm:v2f64 VR128:v16i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 46 cost = 1 size = 3
- if (Predicate_movlp(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::MOVLPDrm, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
+ // Pattern: (vector_shuffle:v2f64 VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)<<P:Predicate_movlp>>
+ // Emits: (MOVLPDrm:v2f64 VR128:v16i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 46 cost = 1 size = 3
+ if (Predicate_movlp(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::MOVLPDrm, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
}
}
}
+ }
- // Pattern: (vector_shuffle:v2f64 VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)<<P:Predicate_unpckh>>
- // Emits: (UNPCKHPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 36 cost = 1 size = 3
- if (Predicate_unpckh(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::UNPCKHPDrm, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
+ // Pattern: (vector_shuffle:v2f64 VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)<<P:Predicate_unpckh>>
+ // Emits: (UNPCKHPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 36 cost = 1 size = 3
+ if (Predicate_unpckh(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::UNPCKHPDrm, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
}
}
}
+ }
- // Pattern: (vector_shuffle:v2f64 VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)<<P:Predicate_unpckl>>
- // Emits: (UNPCKLPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 36 cost = 1 size = 3
- if (Predicate_unpckl(N)) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::UNPCKLPDrm, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
+ // Pattern: (vector_shuffle:v2f64 VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)<<P:Predicate_unpckl>>
+ // Emits: (UNPCKLPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 36 cost = 1 size = 3
+ if (Predicate_unpckl(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::UNPCKLPDrm, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
}
}
}
}
- if ((Subtarget->hasSSE3()) &&
- Predicate_movddup(N)) {
- SDValue N0 = N->getOperand(0);
+ }
+ if ((Subtarget->hasSSE3()) &&
+ Predicate_movddup(N)) {
+ SDValue N0 = N->getOperand(0);
- // Pattern: (vector_shuffle:v2f64 (bitconvert:v2f64 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)), (undef:v2f64))<<P:Predicate_movddup>>
- // Emits: (MOVDDUPrm:v2f64 addr:iPTR:$src)
- // Pattern complexity = 35 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N0.hasOneUse()) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N00.hasOneUse()) {
- SDValue N000 = N00.getNode()->getOperand(0);
- if (N000.getNode()->getOpcode() == ISD::LOAD &&
- N000.hasOneUse() &&
- IsLegalAndProfitableToFold(N000.getNode(), N00.getNode(), N)) {
- SDValue Chain000 = N000.getNode()->getOperand(0);
- if (Predicate_unindexedload(N000.getNode()) &&
- Predicate_load(N000.getNode()) &&
- Predicate_loadi64(N000.getNode())) {
- SDValue N0001 = N000.getNode()->getOperand(1);
- SDValue CPTmpN0001_0;
- SDValue CPTmpN0001_1;
- SDValue CPTmpN0001_2;
- SDValue CPTmpN0001_3;
- SDValue CPTmpN0001_4;
- if (SelectAddr(N, N0001, CPTmpN0001_0, CPTmpN0001_1, CPTmpN0001_2, CPTmpN0001_3, CPTmpN0001_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF &&
- N00.getValueType() == MVT::v2i64 &&
- N000.getValueType() == MVT::i64) {
- SDNode *Result = Emit_249(N, X86::MOVDDUPrm, MVT::v2f64, CPTmpN0001_0, CPTmpN0001_1, CPTmpN0001_2, CPTmpN0001_3, CPTmpN0001_4);
- return Result;
- }
+ // Pattern: (vector_shuffle:v2f64 (bitconvert:v2f64 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)), (undef:v2f64))<<P:Predicate_movddup>>
+ // Emits: (MOVDDUPrm:v2f64 addr:iPTR:$src)
+ // Pattern complexity = 35 cost = 1 size = 3
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N0.hasOneUse()) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N00.hasOneUse()) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ if (N000.getNode()->getOpcode() == ISD::LOAD &&
+ N000.hasOneUse() &&
+ IsLegalAndProfitableToFold(N000.getNode(), N00.getNode(), N)) {
+ SDValue Chain000 = N000.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N000.getNode()) &&
+ Predicate_load(N000.getNode()) &&
+ Predicate_loadi64(N000.getNode())) {
+ SDValue N0001 = N000.getNode()->getOperand(1);
+ SDValue CPTmpN0001_0;
+ SDValue CPTmpN0001_1;
+ SDValue CPTmpN0001_2;
+ SDValue CPTmpN0001_3;
+ SDValue CPTmpN0001_4;
+ if (SelectAddr(N, N0001, CPTmpN0001_0, CPTmpN0001_1, CPTmpN0001_2, CPTmpN0001_3, CPTmpN0001_4)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF &&
+ N00.getValueType() == MVT::v2i64 &&
+ N000.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_250(N, X86::MOVDDUPrm, MVT::v2f64, CPTmpN0001_0, CPTmpN0001_1, CPTmpN0001_2, CPTmpN0001_3, CPTmpN0001_4);
+ return Result;
}
}
}
}
}
+ }
- // Pattern: (vector_shuffle:v2f64 (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (undef:v2f64))<<P:Predicate_movddup>>
- // Emits: (MOVDDUPrm:v2f64 addr:iPTR:$src)
- // Pattern complexity = 34 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_244(N, X86::MOVDDUPrm, MVT::v2f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
+ // Pattern: (vector_shuffle:v2f64 (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (undef:v2f64))<<P:Predicate_movddup>>
+ // Emits: (MOVDDUPrm:v2f64 addr:iPTR:$src)
+ // Pattern complexity = 34 cost = 1 size = 3
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_245(N, X86::MOVDDUPrm, MVT::v2f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
}
}
}
+ }
- // Pattern: (vector_shuffle:v2f64 (scalar_to_vector:v2f64 (ld:f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>), (undef:v2f64))<<P:Predicate_movddup>>
- // Emits: (MOVDDUPrm:v2f64 addr:iPTR:$src)
- // Pattern complexity = 32 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N0.hasOneUse()) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::LOAD &&
- N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
- SDValue Chain00 = N00.getNode()->getOperand(0);
- if (Predicate_unindexedload(N00.getNode()) &&
- Predicate_load(N00.getNode()) &&
- Predicate_loadf64(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::UNDEF &&
- N00.getValueType() == MVT::f64) {
- SDNode *Result = Emit_240(N, X86::MOVDDUPrm, MVT::v2f64, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
- }
+ // Pattern: (vector_shuffle:v2f64 (scalar_to_vector:v2f64 (ld:f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>), (undef:v2f64))<<P:Predicate_movddup>>
+ // Emits: (MOVDDUPrm:v2f64 addr:iPTR:$src)
+ // Pattern complexity = 32 cost = 1 size = 3
+ if (N0.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N0.hasOneUse()) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::LOAD &&
+ N00.hasOneUse() &&
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
+ SDValue Chain00 = N00.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N00.getNode()) &&
+ Predicate_load(N00.getNode()) &&
+ Predicate_loadf64(N00.getNode())) {
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF &&
+ N00.getValueType() == MVT::f64) {
+ SDNode *Result = Emit_241(N, X86::MOVDDUPrm, MVT::v2f64, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
}
}
}
}
}
+ }
+ if ((Subtarget->hasSSE2())) {
// Pattern: (vector_shuffle:v2f64 VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)<<P:Predicate_shufp>><<X:SHUFFLE_get_shuf_imm>>:$src3
// Emits: (SHUFPDrmi:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2, (SHUFFLE_get_shuf_imm:i8 (vector_shuffle:v2f64 VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>):$src3))
// Pattern complexity = 26 cost = 1 size = 3
- if ((Subtarget->hasSSE2()) &&
- Predicate_shufp(N)) {
+ if (Predicate_shufp(N)) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::LOAD &&
@@ -46545,14 +46334,12 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2f64(SDNode *N) {
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_247(N, X86::SHUFPDrmi, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_248(N, X86::SHUFPDrmi, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
}
}
- }
- if ((Subtarget->hasSSE2())) {
if (Predicate_movl(N)) {
// Pattern: (vector_shuffle:v2f64 (bitconvert:v2f64)<<P:Predicate_immAllZerosV_bc>>, VR128:v2f64:$src)<<P:Predicate_movl>>
@@ -46636,7 +46423,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2f64(SDNode *N) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_245(N, X86::SHUFPDrri, MVT::v2f64);
+ SDNode *Result = Emit_246(N, X86::SHUFPDrri, MVT::v2f64);
return Result;
}
}
@@ -46645,7 +46432,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2f64(SDNode *N) {
// Emits: (SHUFPDrri:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2, (SHUFFLE_get_shuf_imm:i8 (vector_shuffle:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2):$src3))
// Pattern complexity = 4 cost = 1 size = 3
if (Predicate_shufp(N)) {
- SDNode *Result = Emit_241(N, X86::SHUFPDrri, MVT::v2f64);
+ SDNode *Result = Emit_242(N, X86::SHUFPDrri, MVT::v2f64);
return Result;
}
}
@@ -46655,7 +46442,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2f64(SDNode *N) {
}
SDNode *Select_ISD_XOR_i8(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
// Pattern: (xor:i8 GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
@@ -46704,9 +46491,6 @@ SDNode *Select_ISD_XOR_i8(SDNode *N) {
}
}
}
- }
- {
- SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::Constant) {
@@ -46734,7 +46518,7 @@ SDNode *Select_ISD_XOR_i8(SDNode *N) {
}
SDNode *Select_ISD_XOR_i16(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
// Pattern: (xor:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
@@ -46783,9 +46567,6 @@ SDNode *Select_ISD_XOR_i16(SDNode *N) {
}
}
}
- }
- {
- SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::Constant) {
@@ -46821,7 +46602,7 @@ SDNode *Select_ISD_XOR_i16(SDNode *N) {
}
SDNode *Select_ISD_XOR_i32(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
// Pattern: (xor:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
@@ -46870,9 +46651,6 @@ SDNode *Select_ISD_XOR_i32(SDNode *N) {
}
}
}
- }
- {
- SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::Constant) {
@@ -46908,7 +46686,7 @@ SDNode *Select_ISD_XOR_i32(SDNode *N) {
}
SDNode *Select_ISD_XOR_i64(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
// Pattern: (xor:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
@@ -46957,9 +46735,6 @@ SDNode *Select_ISD_XOR_i64(SDNode *N) {
}
}
}
- }
- {
- SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::Constant) {
@@ -46997,44 +46772,145 @@ SDNode *Select_ISD_XOR_i64(SDNode *N) {
}
SDNode *Select_ISD_XOR_v1i64(SDNode *N) {
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasMMX())) {
+ if ((Subtarget->hasMMX())) {
+ {
+ SDValue N0 = N->getOperand(0);
+
+ // Pattern: (xor:v1i64 VR64:v1i64:$src1, (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (MMX_PXORrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::MMX_PXORrm, MVT::v1i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (xor:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, VR64:v1i64:$src1)
+ // Emits: (MMX_PXORrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_19(N, X86::MMX_PXORrm, MVT::v1i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (xor:v1i64 VR64:v1i64:$src1, VR64:v1i64:$src2)
+ // Emits: (MMX_PXORrr:v1i64 VR64:v1i64:$src1, VR64:v1i64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_15(N, X86::MMX_PXORrr, MVT::v1i64);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+SDNode *Select_ISD_XOR_v2i64(SDNode *N) {
+
+ // Pattern: (xor:v2i64 (bitconvert:v2i64 VR128:v4f32:$src1), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (XORPSrm:v2i64 VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
+ N00.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_57(N, X86::XORPSrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
- // Pattern: (xor:v1i64 VR64:v1i64:$src1, (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (MMX_PXORrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
+ // Pattern: (xor:v2i64 (bitconvert:v2i64 VR128:v2f64:$src1), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (XORPDrm:v2i64 VR128:v2f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N00 = N0.getNode()->getOperand(0);
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::MMX_PXORrm, MVT::v1i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
+ N00.getValueType() == MVT::v2f64) {
+ SDNode *Result = Emit_57(N, X86::XORPDrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
}
}
+ }
- // Pattern: (xor:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, VR64:v1i64:$src1)
- // Emits: (MMX_PXORrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
+ // Pattern: (xor:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (bitconvert:v2i64 VR128:v4f32:$src1))
+ // Emits: (XORPSrm:v2i64 VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDValue N0 = N->getOperand(0);
if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode())) {
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
@@ -47042,83 +46918,43 @@ SDNode *Select_ISD_XOR_v1i64(SDNode *N) {
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_19(N, X86::MMX_PXORrm, MVT::v1i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (xor:v1i64 VR64:v1i64:$src1, VR64:v1i64:$src2)
- // Emits: (MMX_PXORrr:v1i64 VR64:v1i64:$src1, VR64:v1i64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasMMX())) {
- SDNode *Result = Emit_15(N, X86::MMX_PXORrr, MVT::v1i64);
- return Result;
- }
-
- CannotYetSelect(N);
- return NULL;
-}
-
-SDNode *Select_ISD_XOR_v2i64(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
-
- // Pattern: (xor:v2i64 (bitconvert:v2i64 VR128:v4f32:$src1), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (XORPSrm:v2i64 VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
- N00.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_57(N, X86::XORPSrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_62(N, X86::XORPSrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
}
}
}
+ }
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N->getOperand(0);
- // Pattern: (xor:v2i64 (bitconvert:v2i64 VR128:v2f64:$src1), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Pattern: (xor:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (bitconvert:v2i64 VR128:v2f64:$src1))
// Emits: (XORPDrm:v2i64 VR128:v2f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 28 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N00 = N0.getNode()->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
- N00.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_57(N, X86::XORPDrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getValueType() == MVT::v2f64) {
+ SDNode *Result = Emit_62(N, X86::XORPDrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -47126,125 +46962,58 @@ SDNode *Select_ISD_XOR_v2i64(SDNode *N) {
}
}
- // Pattern: (xor:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (bitconvert:v2i64 VR128:v4f32:$src1))
- // Emits: (XORPSrm:v2i64 VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_62(N, X86::XORPSrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
+ // Pattern: (xor:v2i64 VR128:v2i64:$src1, (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (PXORrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::PXORrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
}
}
}
}
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- // Pattern: (xor:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (bitconvert:v2i64 VR128:v2f64:$src1))
- // Emits: (XORPDrm:v2i64 VR128:v2f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_62(N, X86::XORPDrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (xor:v2i64 VR128:v2i64:$src1, (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (PXORrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::PXORrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (xor:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, VR128:v2i64:$src1)
- // Emits: (PXORrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_19(N, X86::PXORrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
+ // Pattern: (xor:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, VR128:v2i64:$src1)
+ // Emits: (PXORrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_19(N, X86::PXORrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
}
}
}
- }
- // Pattern: (xor:v2i64 (bitconvert:v2i64 VR128:v2f64:$src1), (bitconvert:v2i64 VR128:v2f64:$src2))
- // Emits: (XORPDrr:v2i64 VR128:v2f64:$src1, VR128:v2f64:$src2)
- // Pattern complexity = 9 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
+ // Pattern: (xor:v2i64 (bitconvert:v2i64 VR128:v2f64:$src1), (bitconvert:v2i64 VR128:v2f64:$src2))
+ // Emits: (XORPDrr:v2i64 VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Pattern complexity = 9 cost = 1 size = 3
if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT) {
SDValue N00 = N0.getNode()->getOperand(0);
SDValue N1 = N->getOperand(1);
@@ -47307,7 +47076,7 @@ SDNode *Select_ISD_ZERO_EXTEND_i32(SDNode *N) {
if (CN1 == INT64_C(8) &&
N0.getValueType() == MVT::i16 &&
N01.getValueType() == MVT::i8) {
- SDNode *Result = Emit_74(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX32rr8, MVT::i16, MVT::i8, MVT::i32);
+ SDNode *Result = Emit_74(N, TargetOpcode::COPY_TO_REGCLASS, TargetOpcode::EXTRACT_SUBREG, X86::MOVZX32rr8, MVT::i16, MVT::i8, MVT::i32);
return Result;
}
}
@@ -47329,7 +47098,7 @@ SDNode *Select_ISD_ZERO_EXTEND_i32(SDNode *N) {
if (CN1 == INT64_C(8) &&
N0.getValueType() == MVT::i16 &&
N01.getValueType() == MVT::i8) {
- SDNode *Result = Emit_74(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX32_NOREXrr8, MVT::i16, MVT::i8, MVT::i32);
+ SDNode *Result = Emit_74(N, TargetOpcode::COPY_TO_REGCLASS, TargetOpcode::EXTRACT_SUBREG, X86::MOVZX32_NOREXrr8, MVT::i16, MVT::i8, MVT::i32);
return Result;
}
}
@@ -47373,7 +47142,7 @@ SDNode *Select_ISD_ZERO_EXTEND_i64(SDNode *N) {
if (CN1 == INT64_C(8) &&
N0.getValueType() == MVT::i16 &&
N01.getValueType() == MVT::i8) {
- SDNode *Result = Emit_76(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX32_NOREXrr8, TargetInstrInfo::SUBREG_TO_REG, MVT::i16, MVT::i8, MVT::i32, MVT::i64);
+ SDNode *Result = Emit_76(N, TargetOpcode::COPY_TO_REGCLASS, TargetOpcode::EXTRACT_SUBREG, X86::MOVZX32_NOREXrr8, TargetOpcode::SUBREG_TO_REG, MVT::i16, MVT::i8, MVT::i32, MVT::i64);
return Result;
}
}
@@ -47384,7 +47153,7 @@ SDNode *Select_ISD_ZERO_EXTEND_i64(SDNode *N) {
// Pattern complexity = 4 cost = 1 size = 0
if (Predicate_def32(N0.getNode()) &&
N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_75(N, TargetInstrInfo::SUBREG_TO_REG, MVT::i64);
+ SDNode *Result = Emit_75(N, TargetOpcode::SUBREG_TO_REG, MVT::i64);
return Result;
}
@@ -47417,7 +47186,7 @@ SDNode *Select_ISD_ZERO_EXTEND_i64(SDNode *N) {
}
SDNode *Select_X86ISD_ADD_i8(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
// Pattern: (X86add_flag:i8 GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>)
@@ -47468,13 +47237,10 @@ SDNode *Select_X86ISD_ADD_i8(SDNode *N) {
}
}
}
- }
- // Pattern: (X86add_flag:i8 GR8:i8:$src1, (imm:i8):$src2)
- // Emits: (ADD8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- {
- SDValue N0 = N->getOperand(0);
+ // Pattern: (X86add_flag:i8 GR8:i8:$src1, (imm:i8):$src2)
+ // Emits: (ADD8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_3(N, X86::ADD8ri, MVT::i8);
@@ -47490,7 +47256,7 @@ SDNode *Select_X86ISD_ADD_i8(SDNode *N) {
}
SDNode *Select_X86ISD_ADD_i16(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
// Pattern: (X86add_flag:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>)
@@ -47539,9 +47305,6 @@ SDNode *Select_X86ISD_ADD_i16(SDNode *N) {
}
}
}
- }
- {
- SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::Constant) {
@@ -47569,7 +47332,7 @@ SDNode *Select_X86ISD_ADD_i16(SDNode *N) {
}
SDNode *Select_X86ISD_ADD_i32(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
// Pattern: (X86add_flag:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
@@ -47618,9 +47381,6 @@ SDNode *Select_X86ISD_ADD_i32(SDNode *N) {
}
}
}
- }
- {
- SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::Constant) {
@@ -47648,7 +47408,7 @@ SDNode *Select_X86ISD_ADD_i32(SDNode *N) {
}
SDNode *Select_X86ISD_ADD_i64(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
// Pattern: (X86add_flag:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
@@ -47699,9 +47459,6 @@ SDNode *Select_X86ISD_ADD_i64(SDNode *N) {
}
}
}
- }
- {
- SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::Constant) {
@@ -47731,7 +47488,7 @@ SDNode *Select_X86ISD_ADD_i64(SDNode *N) {
}
SDNode *Select_X86ISD_AND_i8(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
// Pattern: (X86and_flag:i8 GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>)
@@ -47782,13 +47539,10 @@ SDNode *Select_X86ISD_AND_i8(SDNode *N) {
}
}
}
- }
- // Pattern: (X86and_flag:i8 GR8:i8:$src1, (imm:i8):$src2)
- // Emits: (AND8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- {
- SDValue N0 = N->getOperand(0);
+ // Pattern: (X86and_flag:i8 GR8:i8:$src1, (imm:i8):$src2)
+ // Emits: (AND8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_3(N, X86::AND8ri, MVT::i8);
@@ -47804,7 +47558,7 @@ SDNode *Select_X86ISD_AND_i8(SDNode *N) {
}
SDNode *Select_X86ISD_AND_i16(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
// Pattern: (X86and_flag:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>)
@@ -47853,9 +47607,6 @@ SDNode *Select_X86ISD_AND_i16(SDNode *N) {
}
}
}
- }
- {
- SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::Constant) {
@@ -47883,7 +47634,7 @@ SDNode *Select_X86ISD_AND_i16(SDNode *N) {
}
SDNode *Select_X86ISD_AND_i32(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
// Pattern: (X86and_flag:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
@@ -47932,9 +47683,6 @@ SDNode *Select_X86ISD_AND_i32(SDNode *N) {
}
}
}
- }
- {
- SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::Constant) {
@@ -47962,7 +47710,7 @@ SDNode *Select_X86ISD_AND_i32(SDNode *N) {
}
SDNode *Select_X86ISD_AND_i64(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
// Pattern: (X86and_flag:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
@@ -48013,9 +47761,6 @@ SDNode *Select_X86ISD_AND_i64(SDNode *N) {
}
}
}
- }
- {
- SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::Constant) {
@@ -48044,7 +47789,7 @@ SDNode *Select_X86ISD_AND_i64(SDNode *N) {
return Result;
}
-DISABLE_INLINE SDNode *Emit_250(SDNode *N, unsigned Opc0) {
+DISABLE_INLINE SDNode *Emit_251(SDNode *N, unsigned Opc0) {
SDValue Chain = N->getOperand(0);
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
@@ -48064,131 +47809,131 @@ SDNode *Select_X86ISD_BRCOND(SDNode *N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (X86brcond:isVoid (bb:Other):$dst, 4:i8, EFLAGS:i32)
- // Emits: (JE:isVoid (bb:Other):$dst)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(4)) {
- SDNode *Result = Emit_250(N, X86::JE);
- return Result;
- }
-
- // Pattern: (X86brcond:isVoid (bb:Other):$dst, 9:i8, EFLAGS:i32)
- // Emits: (JNE:isVoid (bb:Other):$dst)
+ // Pattern: (X86brcond:isVoid (bb:Other):$dst, 13:i8, EFLAGS:i32)
+ // Emits: (JO_4:isVoid (bb:Other):$dst)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(9)) {
- SDNode *Result = Emit_250(N, X86::JNE);
+ if (CN1 == INT64_C(13)) {
+ SDNode *Result = Emit_251(N, X86::JO_4);
return Result;
}
- // Pattern: (X86brcond:isVoid (bb:Other):$dst, 7:i8, EFLAGS:i32)
- // Emits: (JL:isVoid (bb:Other):$dst)
+ // Pattern: (X86brcond:isVoid (bb:Other):$dst, 10:i8, EFLAGS:i32)
+ // Emits: (JNO_4:isVoid (bb:Other):$dst)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(7)) {
- SDNode *Result = Emit_250(N, X86::JL);
+ if (CN1 == INT64_C(10)) {
+ SDNode *Result = Emit_251(N, X86::JNO_4);
return Result;
}
- // Pattern: (X86brcond:isVoid (bb:Other):$dst, 8:i8, EFLAGS:i32)
- // Emits: (JLE:isVoid (bb:Other):$dst)
+ // Pattern: (X86brcond:isVoid (bb:Other):$dst, 2:i8, EFLAGS:i32)
+ // Emits: (JB_4:isVoid (bb:Other):$dst)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(8)) {
- SDNode *Result = Emit_250(N, X86::JLE);
+ if (CN1 == INT64_C(2)) {
+ SDNode *Result = Emit_251(N, X86::JB_4);
return Result;
}
- // Pattern: (X86brcond:isVoid (bb:Other):$dst, 5:i8, EFLAGS:i32)
- // Emits: (JG:isVoid (bb:Other):$dst)
+ // Pattern: (X86brcond:isVoid (bb:Other):$dst, 1:i8, EFLAGS:i32)
+ // Emits: (JAE_4:isVoid (bb:Other):$dst)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(5)) {
- SDNode *Result = Emit_250(N, X86::JG);
+ if (CN1 == INT64_C(1)) {
+ SDNode *Result = Emit_251(N, X86::JAE_4);
return Result;
}
- // Pattern: (X86brcond:isVoid (bb:Other):$dst, 6:i8, EFLAGS:i32)
- // Emits: (JGE:isVoid (bb:Other):$dst)
+ // Pattern: (X86brcond:isVoid (bb:Other):$dst, 4:i8, EFLAGS:i32)
+ // Emits: (JE_4:isVoid (bb:Other):$dst)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(6)) {
- SDNode *Result = Emit_250(N, X86::JGE);
+ if (CN1 == INT64_C(4)) {
+ SDNode *Result = Emit_251(N, X86::JE_4);
return Result;
}
- // Pattern: (X86brcond:isVoid (bb:Other):$dst, 2:i8, EFLAGS:i32)
- // Emits: (JB:isVoid (bb:Other):$dst)
+ // Pattern: (X86brcond:isVoid (bb:Other):$dst, 9:i8, EFLAGS:i32)
+ // Emits: (JNE_4:isVoid (bb:Other):$dst)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_250(N, X86::JB);
+ if (CN1 == INT64_C(9)) {
+ SDNode *Result = Emit_251(N, X86::JNE_4);
return Result;
}
// Pattern: (X86brcond:isVoid (bb:Other):$dst, 3:i8, EFLAGS:i32)
- // Emits: (JBE:isVoid (bb:Other):$dst)
+ // Emits: (JBE_4:isVoid (bb:Other):$dst)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(3)) {
- SDNode *Result = Emit_250(N, X86::JBE);
+ SDNode *Result = Emit_251(N, X86::JBE_4);
return Result;
}
// Pattern: (X86brcond:isVoid (bb:Other):$dst, 0:i8, EFLAGS:i32)
- // Emits: (JA:isVoid (bb:Other):$dst)
+ // Emits: (JA_4:isVoid (bb:Other):$dst)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_250(N, X86::JA);
- return Result;
- }
-
- // Pattern: (X86brcond:isVoid (bb:Other):$dst, 1:i8, EFLAGS:i32)
- // Emits: (JAE:isVoid (bb:Other):$dst)
- // Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(1)) {
- SDNode *Result = Emit_250(N, X86::JAE);
+ SDNode *Result = Emit_251(N, X86::JA_4);
return Result;
}
// Pattern: (X86brcond:isVoid (bb:Other):$dst, 15:i8, EFLAGS:i32)
- // Emits: (JS:isVoid (bb:Other):$dst)
+ // Emits: (JS_4:isVoid (bb:Other):$dst)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(15)) {
- SDNode *Result = Emit_250(N, X86::JS);
+ SDNode *Result = Emit_251(N, X86::JS_4);
return Result;
}
// Pattern: (X86brcond:isVoid (bb:Other):$dst, 12:i8, EFLAGS:i32)
- // Emits: (JNS:isVoid (bb:Other):$dst)
+ // Emits: (JNS_4:isVoid (bb:Other):$dst)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(12)) {
- SDNode *Result = Emit_250(N, X86::JNS);
+ SDNode *Result = Emit_251(N, X86::JNS_4);
return Result;
}
// Pattern: (X86brcond:isVoid (bb:Other):$dst, 14:i8, EFLAGS:i32)
- // Emits: (JP:isVoid (bb:Other):$dst)
+ // Emits: (JP_4:isVoid (bb:Other):$dst)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(14)) {
- SDNode *Result = Emit_250(N, X86::JP);
+ SDNode *Result = Emit_251(N, X86::JP_4);
return Result;
}
// Pattern: (X86brcond:isVoid (bb:Other):$dst, 11:i8, EFLAGS:i32)
- // Emits: (JNP:isVoid (bb:Other):$dst)
+ // Emits: (JNP_4:isVoid (bb:Other):$dst)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(11)) {
- SDNode *Result = Emit_250(N, X86::JNP);
+ SDNode *Result = Emit_251(N, X86::JNP_4);
return Result;
}
- // Pattern: (X86brcond:isVoid (bb:Other):$dst, 13:i8, EFLAGS:i32)
- // Emits: (JO:isVoid (bb:Other):$dst)
+ // Pattern: (X86brcond:isVoid (bb:Other):$dst, 7:i8, EFLAGS:i32)
+ // Emits: (JL_4:isVoid (bb:Other):$dst)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(13)) {
- SDNode *Result = Emit_250(N, X86::JO);
+ if (CN1 == INT64_C(7)) {
+ SDNode *Result = Emit_251(N, X86::JL_4);
return Result;
}
- // Pattern: (X86brcond:isVoid (bb:Other):$dst, 10:i8, EFLAGS:i32)
- // Emits: (JNO:isVoid (bb:Other):$dst)
+ // Pattern: (X86brcond:isVoid (bb:Other):$dst, 6:i8, EFLAGS:i32)
+ // Emits: (JGE_4:isVoid (bb:Other):$dst)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(10)) {
- SDNode *Result = Emit_250(N, X86::JNO);
+ if (CN1 == INT64_C(6)) {
+ SDNode *Result = Emit_251(N, X86::JGE_4);
+ return Result;
+ }
+
+ // Pattern: (X86brcond:isVoid (bb:Other):$dst, 8:i8, EFLAGS:i32)
+ // Emits: (JLE_4:isVoid (bb:Other):$dst)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(8)) {
+ SDNode *Result = Emit_251(N, X86::JLE_4);
+ return Result;
+ }
+
+ // Pattern: (X86brcond:isVoid (bb:Other):$dst, 5:i8, EFLAGS:i32)
+ // Emits: (JG_4:isVoid (bb:Other):$dst)
+ // Pattern complexity = 8 cost = 1 size = 3
+ if (CN1 == INT64_C(5)) {
+ SDNode *Result = Emit_251(N, X86::JG_4);
return Result;
}
}
@@ -48198,11 +47943,11 @@ SDNode *Select_X86ISD_BRCOND(SDNode *N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_251(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_252(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N->getOperand(0);
return CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::i32, N0);
}
-DISABLE_INLINE SDNode *Emit_252(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+DISABLE_INLINE SDNode *Emit_253(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
SDValue N0 = N->getOperand(0);
SDValue Chain0 = N0.getNode()->getOperand(0);
SDValue N01 = N0.getNode()->getOperand(1);
@@ -48219,7 +47964,7 @@ SDNode *Select_X86ISD_BSF_i16(SDNode *N) {
// Pattern: (X86bsf:i16 (ld:i16 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>)
// Emits: (BSF16rm:i16 addr:iPTR:$src)
// Pattern complexity = 25 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse()) {
@@ -48233,7 +47978,7 @@ SDNode *Select_X86ISD_BSF_i16(SDNode *N) {
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_252(N, X86::BSF16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_253(N, X86::BSF16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -48243,7 +47988,7 @@ SDNode *Select_X86ISD_BSF_i16(SDNode *N) {
// Pattern: (X86bsf:i16 GR16:i16:$src)
// Emits: (BSF16rr:i16 GR16:i16:$src)
// Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_251(N, X86::BSF16rr, MVT::i16);
+ SDNode *Result = Emit_252(N, X86::BSF16rr, MVT::i16);
return Result;
}
@@ -48252,7 +47997,7 @@ SDNode *Select_X86ISD_BSF_i32(SDNode *N) {
// Pattern: (X86bsf:i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
// Emits: (BSF32rm:i32 addr:iPTR:$src)
// Pattern complexity = 25 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse()) {
@@ -48266,7 +48011,7 @@ SDNode *Select_X86ISD_BSF_i32(SDNode *N) {
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_252(N, X86::BSF32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_253(N, X86::BSF32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -48276,7 +48021,7 @@ SDNode *Select_X86ISD_BSF_i32(SDNode *N) {
// Pattern: (X86bsf:i32 GR32:i32:$src)
// Emits: (BSF32rr:i32 GR32:i32:$src)
// Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_251(N, X86::BSF32rr, MVT::i32);
+ SDNode *Result = Emit_252(N, X86::BSF32rr, MVT::i32);
return Result;
}
@@ -48285,7 +48030,7 @@ SDNode *Select_X86ISD_BSF_i64(SDNode *N) {
// Pattern: (X86bsf:i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
// Emits: (BSF64rm:i64 addr:iPTR:$src)
// Pattern complexity = 25 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse()) {
@@ -48300,7 +48045,7 @@ SDNode *Select_X86ISD_BSF_i64(SDNode *N) {
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_252(N, X86::BSF64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_253(N, X86::BSF64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -48310,7 +48055,7 @@ SDNode *Select_X86ISD_BSF_i64(SDNode *N) {
// Pattern: (X86bsf:i64 GR64:i64:$src)
// Emits: (BSF64rr:i64 GR64:i64:$src)
// Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_251(N, X86::BSF64rr, MVT::i64);
+ SDNode *Result = Emit_252(N, X86::BSF64rr, MVT::i64);
return Result;
}
@@ -48319,7 +48064,7 @@ SDNode *Select_X86ISD_BSR_i16(SDNode *N) {
// Pattern: (X86bsr:i16 (ld:i16 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>)
// Emits: (BSR16rm:i16 addr:iPTR:$src)
// Pattern complexity = 25 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse()) {
@@ -48333,7 +48078,7 @@ SDNode *Select_X86ISD_BSR_i16(SDNode *N) {
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_252(N, X86::BSR16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_253(N, X86::BSR16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -48343,7 +48088,7 @@ SDNode *Select_X86ISD_BSR_i16(SDNode *N) {
// Pattern: (X86bsr:i16 GR16:i16:$src)
// Emits: (BSR16rr:i16 GR16:i16:$src)
// Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_251(N, X86::BSR16rr, MVT::i16);
+ SDNode *Result = Emit_252(N, X86::BSR16rr, MVT::i16);
return Result;
}
@@ -48352,7 +48097,7 @@ SDNode *Select_X86ISD_BSR_i32(SDNode *N) {
// Pattern: (X86bsr:i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
// Emits: (BSR32rm:i32 addr:iPTR:$src)
// Pattern complexity = 25 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse()) {
@@ -48366,7 +48111,7 @@ SDNode *Select_X86ISD_BSR_i32(SDNode *N) {
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_252(N, X86::BSR32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_253(N, X86::BSR32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -48376,7 +48121,7 @@ SDNode *Select_X86ISD_BSR_i32(SDNode *N) {
// Pattern: (X86bsr:i32 GR32:i32:$src)
// Emits: (BSR32rr:i32 GR32:i32:$src)
// Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_251(N, X86::BSR32rr, MVT::i32);
+ SDNode *Result = Emit_252(N, X86::BSR32rr, MVT::i32);
return Result;
}
@@ -48385,7 +48130,7 @@ SDNode *Select_X86ISD_BSR_i64(SDNode *N) {
// Pattern: (X86bsr:i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
// Emits: (BSR64rm:i64 addr:iPTR:$src)
// Pattern complexity = 25 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse()) {
@@ -48400,7 +48145,7 @@ SDNode *Select_X86ISD_BSR_i64(SDNode *N) {
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_252(N, X86::BSR64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_253(N, X86::BSR64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -48410,28 +48155,28 @@ SDNode *Select_X86ISD_BSR_i64(SDNode *N) {
// Pattern: (X86bsr:i64 GR64:i64:$src)
// Emits: (BSR64rr:i64 GR64:i64:$src)
// Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_251(N, X86::BSR64rr, MVT::i64);
+ SDNode *Result = Emit_252(N, X86::BSR64rr, MVT::i64);
return Result;
}
-DISABLE_INLINE SDNode *Emit_253(SDNode *N, unsigned Opc0) {
+DISABLE_INLINE SDNode *Emit_254(SDNode *N, unsigned Opc0) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
return CurDAG->SelectNodeTo(N, Opc0, MVT::i32, N0, N1);
}
-DISABLE_INLINE SDNode *Emit_254(SDNode *N, unsigned Opc0) {
+DISABLE_INLINE SDNode *Emit_255(SDNode *N, unsigned Opc0) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned short) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i16);
return CurDAG->SelectNodeTo(N, Opc0, MVT::i32, N0, Tmp1);
}
-DISABLE_INLINE SDNode *Emit_255(SDNode *N, unsigned Opc0) {
+DISABLE_INLINE SDNode *Emit_256(SDNode *N, unsigned Opc0) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
return CurDAG->SelectNodeTo(N, Opc0, MVT::i32, N0, Tmp1);
}
-DISABLE_INLINE SDNode *Emit_256(SDNode *N, unsigned Opc0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+DISABLE_INLINE SDNode *Emit_257(SDNode *N, unsigned Opc0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
SDValue N0 = N->getOperand(0);
SDValue Chain0 = N0.getNode()->getOperand(0);
SDValue N01 = N0.getNode()->getOperand(1);
@@ -48445,7 +48190,7 @@ DISABLE_INLINE SDNode *Emit_256(SDNode *N, unsigned Opc0, SDValue &CPTmpN01_0, S
ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_257(SDNode *N, unsigned Opc0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+DISABLE_INLINE SDNode *Emit_258(SDNode *N, unsigned Opc0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
SDValue N0 = N->getOperand(0);
SDValue Chain0 = N0.getNode()->getOperand(0);
SDValue N01 = N0.getNode()->getOperand(1);
@@ -48459,13 +48204,13 @@ DISABLE_INLINE SDNode *Emit_257(SDNode *N, unsigned Opc0, SDValue &CPTmpN01_0, S
ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_258(SDNode *N, unsigned Opc0) {
+DISABLE_INLINE SDNode *Emit_259(SDNode *N, unsigned Opc0) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i64);
return CurDAG->SelectNodeTo(N, Opc0, MVT::i32, N0, Tmp1);
}
-DISABLE_INLINE SDNode *Emit_259(SDNode *N, unsigned Opc0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+DISABLE_INLINE SDNode *Emit_260(SDNode *N, unsigned Opc0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
SDValue N0 = N->getOperand(0);
SDValue Chain0 = N0.getNode()->getOperand(0);
SDValue N01 = N0.getNode()->getOperand(1);
@@ -48480,81 +48225,78 @@ DISABLE_INLINE SDNode *Emit_259(SDNode *N, unsigned Opc0, SDValue &CPTmpN01_0, S
return ResNode;
}
SDNode *Select_X86ISD_BT(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode())) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode())) {
- // Pattern: (X86bt:isVoid (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
- // Emits: (BT16mi8:isVoid addr:iPTR:$src1, (imm:i16):$src2)
- // Pattern complexity = 29 cost = 1 size = 3
- if (Predicate_loadi16(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- Predicate_i16immSExt8(N1.getNode()) &&
- N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_256(N, X86::BT16mi8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
+ // Pattern: (X86bt:isVoid (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
+ // Emits: (BT16mi8:isVoid addr:iPTR:$src1, (imm:i16):$src2)
+ // Pattern complexity = 29 cost = 1 size = 3
+ if (Predicate_loadi16(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
+ Predicate_i16immSExt8(N1.getNode()) &&
+ N0.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_257(N, X86::BT16mi8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
}
}
+ }
- // Pattern: (X86bt:isVoid (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
- // Emits: (BT32mi8:isVoid addr:iPTR:$src1, (imm:i32):$src2)
- // Pattern complexity = 29 cost = 1 size = 3
- if (Predicate_loadi32(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- Predicate_i32immSExt8(N1.getNode()) &&
- N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_257(N, X86::BT32mi8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
+ // Pattern: (X86bt:isVoid (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
+ // Emits: (BT32mi8:isVoid addr:iPTR:$src1, (imm:i32):$src2)
+ // Pattern complexity = 29 cost = 1 size = 3
+ if (Predicate_loadi32(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
+ Predicate_i32immSExt8(N1.getNode()) &&
+ N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_258(N, X86::BT32mi8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
}
}
+ }
- // Pattern: (X86bt:isVoid (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
- // Emits: (BT64mi8:isVoid addr:iPTR:$src1, (imm:i64):$src2)
- // Pattern complexity = 29 cost = 1 size = 3
- if (Predicate_load(N0.getNode()) &&
- Predicate_loadi64(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- Predicate_i64immSExt8(N1.getNode()) &&
- N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_259(N, X86::BT64mi8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
+ // Pattern: (X86bt:isVoid (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
+ // Emits: (BT64mi8:isVoid addr:iPTR:$src1, (imm:i64):$src2)
+ // Pattern complexity = 29 cost = 1 size = 3
+ if (Predicate_load(N0.getNode()) &&
+ Predicate_loadi64(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
+ Predicate_i64immSExt8(N1.getNode()) &&
+ N0.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_260(N, X86::BT64mi8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
}
}
}
}
}
- SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::Constant) {
@@ -48563,7 +48305,7 @@ SDNode *Select_X86ISD_BT(SDNode *N) {
// Pattern complexity = 7 cost = 1 size = 3
if (Predicate_i16immSExt8(N1.getNode()) &&
N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_254(N, X86::BT16ri8);
+ SDNode *Result = Emit_255(N, X86::BT16ri8);
return Result;
}
@@ -48572,7 +48314,7 @@ SDNode *Select_X86ISD_BT(SDNode *N) {
// Pattern complexity = 7 cost = 1 size = 3
if (Predicate_i32immSExt8(N1.getNode()) &&
N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_255(N, X86::BT32ri8);
+ SDNode *Result = Emit_256(N, X86::BT32ri8);
return Result;
}
@@ -48581,7 +48323,7 @@ SDNode *Select_X86ISD_BT(SDNode *N) {
// Pattern complexity = 7 cost = 1 size = 3
if (Predicate_i64immSExt8(N1.getNode()) &&
N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_258(N, X86::BT64ri8);
+ SDNode *Result = Emit_259(N, X86::BT64ri8);
return Result;
}
}
@@ -48590,7 +48332,7 @@ SDNode *Select_X86ISD_BT(SDNode *N) {
// Emits: (BT16rr:isVoid GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 3 cost = 1 size = 3
if (N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_253(N, X86::BT16rr);
+ SDNode *Result = Emit_254(N, X86::BT16rr);
return Result;
}
@@ -48598,7 +48340,7 @@ SDNode *Select_X86ISD_BT(SDNode *N) {
// Emits: (BT32rr:isVoid GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 3 cost = 1 size = 3
if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_253(N, X86::BT32rr);
+ SDNode *Result = Emit_254(N, X86::BT32rr);
return Result;
}
@@ -48606,7 +48348,7 @@ SDNode *Select_X86ISD_BT(SDNode *N) {
// Emits: (BT64rr:isVoid GR64:i64:$src1, GR64:i64:$src2)
// Pattern complexity = 3 cost = 1 size = 3
if (N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_253(N, X86::BT64rr);
+ SDNode *Result = Emit_254(N, X86::BT64rr);
return Result;
}
@@ -48614,7 +48356,7 @@ SDNode *Select_X86ISD_BT(SDNode *N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_260(SDNode *N, unsigned Opc0, unsigned NumInputRootOps) {
+DISABLE_INLINE SDNode *Emit_261(SDNode *N, unsigned Opc0, unsigned NumInputRootOps) {
SDValue Chain = N->getOperand(0);
SDValue N1 = N->getOperand(1);
bool HasInFlag = (N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag);
@@ -48644,7 +48386,7 @@ DISABLE_INLINE SDNode *Emit_260(SDNode *N, unsigned Opc0, unsigned NumInputRootO
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_261(SDNode *N, unsigned Opc0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4, unsigned NumInputRootOps) {
+DISABLE_INLINE SDNode *Emit_262(SDNode *N, unsigned Opc0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4, unsigned NumInputRootOps) {
SDValue Chain = N->getOperand(0);
SDValue N1 = N->getOperand(1);
SDValue Chain1 = N1.getNode()->getOperand(0);
@@ -48691,7 +48433,7 @@ DISABLE_INLINE SDNode *Emit_261(SDNode *N, unsigned Opc0, SDValue &CPTmpN11_0, S
ReplaceUses(Froms, Tos, 3);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_262(SDNode *N, unsigned Opc0, unsigned NumInputRootOps) {
+DISABLE_INLINE SDNode *Emit_263(SDNode *N, unsigned Opc0, unsigned NumInputRootOps) {
SDValue Chain = N->getOperand(0);
SDValue N1 = N->getOperand(1);
bool HasInFlag = (N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag);
@@ -48745,7 +48487,7 @@ SDNode *Select_X86ISD_CALL(SDNode *N) {
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_261(N, X86::CALL32m, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, 1);
+ SDNode *Result = Emit_262(N, X86::CALL32m, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, 1);
return Result;
}
}
@@ -48774,7 +48516,7 @@ SDNode *Select_X86ISD_CALL(SDNode *N) {
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_261(N, X86::CALL64m, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, 1);
+ SDNode *Result = Emit_262(N, X86::CALL64m, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, 1);
return Result;
}
}
@@ -48803,7 +48545,7 @@ SDNode *Select_X86ISD_CALL(SDNode *N) {
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_261(N, X86::WINCALL64m, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, 1);
+ SDNode *Result = Emit_262(N, X86::WINCALL64m, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, 1);
return Result;
}
}
@@ -48818,7 +48560,7 @@ SDNode *Select_X86ISD_CALL(SDNode *N) {
// Pattern complexity = 6 cost = 1 size = 3
if (N1.getNode()->getOpcode() == ISD::TargetGlobalAddress &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_260(N, X86::CALL64pcrel32, 1);
+ SDNode *Result = Emit_261(N, X86::CALL64pcrel32, 1);
return Result;
}
@@ -48827,7 +48569,7 @@ SDNode *Select_X86ISD_CALL(SDNode *N) {
// Pattern complexity = 6 cost = 1 size = 3
if (N1.getNode()->getOpcode() == ISD::TargetExternalSymbol &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_260(N, X86::CALL64pcrel32, 1);
+ SDNode *Result = Emit_261(N, X86::CALL64pcrel32, 1);
return Result;
}
}
@@ -48840,7 +48582,7 @@ SDNode *Select_X86ISD_CALL(SDNode *N) {
// Pattern complexity = 6 cost = 1 size = 3
if (N1.getNode()->getOpcode() == ISD::TargetGlobalAddress &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_260(N, X86::WINCALL64pcrel32, 1);
+ SDNode *Result = Emit_261(N, X86::WINCALL64pcrel32, 1);
return Result;
}
@@ -48849,7 +48591,7 @@ SDNode *Select_X86ISD_CALL(SDNode *N) {
// Pattern complexity = 6 cost = 1 size = 3
if (N1.getNode()->getOpcode() == ISD::TargetExternalSymbol &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_260(N, X86::WINCALL64pcrel32, 1);
+ SDNode *Result = Emit_261(N, X86::WINCALL64pcrel32, 1);
return Result;
}
}
@@ -48862,7 +48604,7 @@ SDNode *Select_X86ISD_CALL(SDNode *N) {
// Pattern complexity = 6 cost = 1 size = 3
if (N1.getNode()->getOpcode() == ISD::TargetGlobalAddress &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_260(N, X86::CALLpcrel32, 1);
+ SDNode *Result = Emit_261(N, X86::CALLpcrel32, 1);
return Result;
}
@@ -48871,7 +48613,7 @@ SDNode *Select_X86ISD_CALL(SDNode *N) {
// Pattern complexity = 6 cost = 1 size = 3
if (N1.getNode()->getOpcode() == ISD::TargetExternalSymbol &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_260(N, X86::CALLpcrel32, 1);
+ SDNode *Result = Emit_261(N, X86::CALLpcrel32, 1);
return Result;
}
}
@@ -48884,7 +48626,7 @@ SDNode *Select_X86ISD_CALL(SDNode *N) {
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_262(N, X86::CALLpcrel32, 1);
+ SDNode *Result = Emit_263(N, X86::CALLpcrel32, 1);
return Result;
}
}
@@ -48896,7 +48638,7 @@ SDNode *Select_X86ISD_CALL(SDNode *N) {
SDValue Chain = N->getOperand(0);
SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_260(N, X86::CALL32r, 1);
+ SDNode *Result = Emit_261(N, X86::CALL32r, 1);
return Result;
}
}
@@ -48908,7 +48650,7 @@ SDNode *Select_X86ISD_CALL(SDNode *N) {
SDValue Chain = N->getOperand(0);
SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_260(N, X86::CALL64r, 1);
+ SDNode *Result = Emit_261(N, X86::CALL64r, 1);
return Result;
}
}
@@ -48920,7 +48662,7 @@ SDNode *Select_X86ISD_CALL(SDNode *N) {
SDValue Chain = N->getOperand(0);
SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_260(N, X86::WINCALL64r, 1);
+ SDNode *Result = Emit_261(N, X86::WINCALL64r, 1);
return Result;
}
}
@@ -48929,7 +48671,7 @@ SDNode *Select_X86ISD_CALL(SDNode *N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_263(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_264(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
@@ -48948,7 +48690,7 @@ SDNode *Select_X86ISD_CMOV_i8(SDNode *N) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_263(N, X86::CMOV_GR8, MVT::i8);
+ SDNode *Result = Emit_264(N, X86::CMOV_GR8, MVT::i8);
return Result;
}
@@ -48956,7 +48698,7 @@ SDNode *Select_X86ISD_CMOV_i8(SDNode *N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_264(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_265(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
@@ -48968,7 +48710,7 @@ DISABLE_INLINE SDNode *Emit_264(SDNode *N, unsigned Opc0, MVT::SimpleValueType V
InFlag = SDValue(ResNode, 1);
return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, N1, InFlag);
}
-DISABLE_INLINE SDNode *Emit_265(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
+DISABLE_INLINE SDNode *Emit_266(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
SDValue Chain1 = N1.getNode()->getOperand(0);
@@ -48987,7 +48729,7 @@ DISABLE_INLINE SDNode *Emit_265(SDNode *N, unsigned Opc0, MVT::SimpleValueType V
ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_266(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+DISABLE_INLINE SDNode *Emit_267(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
SDValue N0 = N->getOperand(0);
SDValue Chain0 = N0.getNode()->getOperand(0);
SDValue N01 = N0.getNode()->getOperand(1);
@@ -49007,304 +48749,152 @@ DISABLE_INLINE SDNode *Emit_266(SDNode *N, unsigned Opc0, MVT::SimpleValueType V
return ResNode;
}
SDNode *Select_X86ISD_CMOV_i16(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N->getOperand(0);
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_loadi16(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDValue N2 = N->getOperand(2);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (X86cmov:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 2:i8, EFLAGS:i32)
- // Emits: (CMOVB16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_265(N, X86::CMOVB16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 1:i8, EFLAGS:i32)
- // Emits: (CMOVAE16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(1)) {
- SDNode *Result = Emit_265(N, X86::CMOVAE16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 4:i8, EFLAGS:i32)
- // Emits: (CMOVE16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(4)) {
- SDNode *Result = Emit_265(N, X86::CMOVE16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 9:i8, EFLAGS:i32)
- // Emits: (CMOVNE16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(9)) {
- SDNode *Result = Emit_265(N, X86::CMOVNE16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 3:i8, EFLAGS:i32)
- // Emits: (CMOVBE16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(3)) {
- SDNode *Result = Emit_265(N, X86::CMOVBE16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 0:i8, EFLAGS:i32)
- // Emits: (CMOVA16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_265(N, X86::CMOVA16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 7:i8, EFLAGS:i32)
- // Emits: (CMOVL16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(7)) {
- SDNode *Result = Emit_265(N, X86::CMOVL16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 6:i8, EFLAGS:i32)
- // Emits: (CMOVGE16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(6)) {
- SDNode *Result = Emit_265(N, X86::CMOVGE16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 8:i8, EFLAGS:i32)
- // Emits: (CMOVLE16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(8)) {
- SDNode *Result = Emit_265(N, X86::CMOVLE16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 5:i8, EFLAGS:i32)
- // Emits: (CMOVG16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(5)) {
- SDNode *Result = Emit_265(N, X86::CMOVG16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 15:i8, EFLAGS:i32)
- // Emits: (CMOVS16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(15)) {
- SDNode *Result = Emit_265(N, X86::CMOVS16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 12:i8, EFLAGS:i32)
- // Emits: (CMOVNS16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(12)) {
- SDNode *Result = Emit_265(N, X86::CMOVNS16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 14:i8, EFLAGS:i32)
- // Emits: (CMOVP16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(14)) {
- SDNode *Result = Emit_265(N, X86::CMOVP16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 11:i8, EFLAGS:i32)
- // Emits: (CMOVNP16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(11)) {
- SDNode *Result = Emit_265(N, X86::CMOVNP16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 13:i8, EFLAGS:i32)
- // Emits: (CMOVO16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(13)) {
- SDNode *Result = Emit_265(N, X86::CMOVO16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 10:i8, EFLAGS:i32)
- // Emits: (CMOVNO16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(10)) {
- SDNode *Result = Emit_265(N, X86::CMOVNO16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_loadi16(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_loadi16(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
SDValue N2 = N->getOperand(2);
ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (X86cmov:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, 6:i8, EFLAGS:i32)
- // Emits: (CMOVL16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
+ // Pattern: (X86cmov:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 2:i8, EFLAGS:i32)
+ // Emits: (CMOVB16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(6)) {
- SDNode *Result = Emit_266(N, X86::CMOVL16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ if (CN1 == INT64_C(2)) {
+ SDNode *Result = Emit_266(N, X86::CMOVB16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
- // Pattern: (X86cmov:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, 8:i8, EFLAGS:i32)
- // Emits: (CMOVG16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
+ // Pattern: (X86cmov:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 1:i8, EFLAGS:i32)
+ // Emits: (CMOVAE16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(8)) {
- SDNode *Result = Emit_266(N, X86::CMOVG16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ if (CN1 == INT64_C(1)) {
+ SDNode *Result = Emit_266(N, X86::CMOVAE16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
- // Pattern: (X86cmov:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, 5:i8, EFLAGS:i32)
- // Emits: (CMOVLE16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
+ // Pattern: (X86cmov:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 4:i8, EFLAGS:i32)
+ // Emits: (CMOVE16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(5)) {
- SDNode *Result = Emit_266(N, X86::CMOVLE16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ if (CN1 == INT64_C(4)) {
+ SDNode *Result = Emit_266(N, X86::CMOVE16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
- // Pattern: (X86cmov:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, 14:i8, EFLAGS:i32)
- // Emits: (CMOVNP16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
+ // Pattern: (X86cmov:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 9:i8, EFLAGS:i32)
+ // Emits: (CMOVNE16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(14)) {
- SDNode *Result = Emit_266(N, X86::CMOVNP16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ if (CN1 == INT64_C(9)) {
+ SDNode *Result = Emit_266(N, X86::CMOVNE16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
- // Pattern: (X86cmov:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, 11:i8, EFLAGS:i32)
- // Emits: (CMOVP16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
+ // Pattern: (X86cmov:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 3:i8, EFLAGS:i32)
+ // Emits: (CMOVBE16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(11)) {
- SDNode *Result = Emit_266(N, X86::CMOVP16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ if (CN1 == INT64_C(3)) {
+ SDNode *Result = Emit_266(N, X86::CMOVBE16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
- // Pattern: (X86cmov:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, 15:i8, EFLAGS:i32)
- // Emits: (CMOVNS16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
+ // Pattern: (X86cmov:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 0:i8, EFLAGS:i32)
+ // Emits: (CMOVA16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(15)) {
- SDNode *Result = Emit_266(N, X86::CMOVNS16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_266(N, X86::CMOVA16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
- // Pattern: (X86cmov:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, 12:i8, EFLAGS:i32)
- // Emits: (CMOVS16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
+ // Pattern: (X86cmov:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 7:i8, EFLAGS:i32)
+ // Emits: (CMOVL16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(12)) {
- SDNode *Result = Emit_266(N, X86::CMOVS16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ if (CN1 == INT64_C(7)) {
+ SDNode *Result = Emit_266(N, X86::CMOVL16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
- // Pattern: (X86cmov:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, 13:i8, EFLAGS:i32)
- // Emits: (CMOVNO16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
+ // Pattern: (X86cmov:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 6:i8, EFLAGS:i32)
+ // Emits: (CMOVGE16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(13)) {
- SDNode *Result = Emit_266(N, X86::CMOVNO16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ if (CN1 == INT64_C(6)) {
+ SDNode *Result = Emit_266(N, X86::CMOVGE16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
- // Pattern: (X86cmov:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, 10:i8, EFLAGS:i32)
- // Emits: (CMOVO16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
+ // Pattern: (X86cmov:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 8:i8, EFLAGS:i32)
+ // Emits: (CMOVLE16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(10)) {
- SDNode *Result = Emit_266(N, X86::CMOVO16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ if (CN1 == INT64_C(8)) {
+ SDNode *Result = Emit_266(N, X86::CMOVLE16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
- // Pattern: (X86cmov:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, 2:i8, EFLAGS:i32)
- // Emits: (CMOVAE16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
+ // Pattern: (X86cmov:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 5:i8, EFLAGS:i32)
+ // Emits: (CMOVG16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_266(N, X86::CMOVAE16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ if (CN1 == INT64_C(5)) {
+ SDNode *Result = Emit_266(N, X86::CMOVG16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
- // Pattern: (X86cmov:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, 1:i8, EFLAGS:i32)
- // Emits: (CMOVB16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
+ // Pattern: (X86cmov:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 15:i8, EFLAGS:i32)
+ // Emits: (CMOVS16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(1)) {
- SDNode *Result = Emit_266(N, X86::CMOVB16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ if (CN1 == INT64_C(15)) {
+ SDNode *Result = Emit_266(N, X86::CMOVS16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
- // Pattern: (X86cmov:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, 4:i8, EFLAGS:i32)
- // Emits: (CMOVNE16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
+ // Pattern: (X86cmov:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 12:i8, EFLAGS:i32)
+ // Emits: (CMOVNS16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(4)) {
- SDNode *Result = Emit_266(N, X86::CMOVNE16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ if (CN1 == INT64_C(12)) {
+ SDNode *Result = Emit_266(N, X86::CMOVNS16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
- // Pattern: (X86cmov:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, 9:i8, EFLAGS:i32)
- // Emits: (CMOVE16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
+ // Pattern: (X86cmov:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 14:i8, EFLAGS:i32)
+ // Emits: (CMOVP16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(9)) {
- SDNode *Result = Emit_266(N, X86::CMOVE16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ if (CN1 == INT64_C(14)) {
+ SDNode *Result = Emit_266(N, X86::CMOVP16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
- // Pattern: (X86cmov:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, 3:i8, EFLAGS:i32)
- // Emits: (CMOVA16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
+ // Pattern: (X86cmov:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 11:i8, EFLAGS:i32)
+ // Emits: (CMOVNP16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(3)) {
- SDNode *Result = Emit_266(N, X86::CMOVA16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ if (CN1 == INT64_C(11)) {
+ SDNode *Result = Emit_266(N, X86::CMOVNP16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
- // Pattern: (X86cmov:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, 0:i8, EFLAGS:i32)
- // Emits: (CMOVBE16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
+ // Pattern: (X86cmov:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 13:i8, EFLAGS:i32)
+ // Emits: (CMOVO16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_266(N, X86::CMOVBE16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ if (CN1 == INT64_C(13)) {
+ SDNode *Result = Emit_266(N, X86::CMOVO16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
- // Pattern: (X86cmov:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, 7:i8, EFLAGS:i32)
- // Emits: (CMOVGE16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
+ // Pattern: (X86cmov:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 10:i8, EFLAGS:i32)
+ // Emits: (CMOVNO16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(7)) {
- SDNode *Result = Emit_266(N, X86::CMOVGE16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ if (CN1 == INT64_C(10)) {
+ SDNode *Result = Emit_266(N, X86::CMOVNO16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -49312,7 +48902,156 @@ SDNode *Select_X86ISD_CMOV_i16(SDNode *N) {
}
}
}
- SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_loadi16(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (X86cmov:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, 6:i8, EFLAGS:i32)
+ // Emits: (CMOVL16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(6)) {
+ SDNode *Result = Emit_267(N, X86::CMOVL16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, 8:i8, EFLAGS:i32)
+ // Emits: (CMOVG16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(8)) {
+ SDNode *Result = Emit_267(N, X86::CMOVG16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, 5:i8, EFLAGS:i32)
+ // Emits: (CMOVLE16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(5)) {
+ SDNode *Result = Emit_267(N, X86::CMOVLE16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, 14:i8, EFLAGS:i32)
+ // Emits: (CMOVNP16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(14)) {
+ SDNode *Result = Emit_267(N, X86::CMOVNP16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, 11:i8, EFLAGS:i32)
+ // Emits: (CMOVP16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(11)) {
+ SDNode *Result = Emit_267(N, X86::CMOVP16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, 15:i8, EFLAGS:i32)
+ // Emits: (CMOVNS16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(15)) {
+ SDNode *Result = Emit_267(N, X86::CMOVNS16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, 12:i8, EFLAGS:i32)
+ // Emits: (CMOVS16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(12)) {
+ SDNode *Result = Emit_267(N, X86::CMOVS16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, 13:i8, EFLAGS:i32)
+ // Emits: (CMOVNO16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(13)) {
+ SDNode *Result = Emit_267(N, X86::CMOVNO16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, 10:i8, EFLAGS:i32)
+ // Emits: (CMOVO16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(10)) {
+ SDNode *Result = Emit_267(N, X86::CMOVO16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, 2:i8, EFLAGS:i32)
+ // Emits: (CMOVAE16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(2)) {
+ SDNode *Result = Emit_267(N, X86::CMOVAE16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, 1:i8, EFLAGS:i32)
+ // Emits: (CMOVB16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(1)) {
+ SDNode *Result = Emit_267(N, X86::CMOVB16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, 4:i8, EFLAGS:i32)
+ // Emits: (CMOVNE16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(4)) {
+ SDNode *Result = Emit_267(N, X86::CMOVNE16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, 9:i8, EFLAGS:i32)
+ // Emits: (CMOVE16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(9)) {
+ SDNode *Result = Emit_267(N, X86::CMOVE16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, 3:i8, EFLAGS:i32)
+ // Emits: (CMOVA16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(3)) {
+ SDNode *Result = Emit_267(N, X86::CMOVA16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, 0:i8, EFLAGS:i32)
+ // Emits: (CMOVBE16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_267(N, X86::CMOVBE16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, 7:i8, EFLAGS:i32)
+ // Emits: (CMOVGE16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(7)) {
+ SDNode *Result = Emit_267(N, X86::CMOVGE16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2.getNode());
@@ -49323,7 +49062,7 @@ SDNode *Select_X86ISD_CMOV_i16(SDNode *N) {
// Emits: (CMOVB16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_264(N, X86::CMOVB16rr, MVT::i16);
+ SDNode *Result = Emit_265(N, X86::CMOVB16rr, MVT::i16);
return Result;
}
@@ -49331,7 +49070,7 @@ SDNode *Select_X86ISD_CMOV_i16(SDNode *N) {
// Emits: (CMOVAE16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(1)) {
- SDNode *Result = Emit_264(N, X86::CMOVAE16rr, MVT::i16);
+ SDNode *Result = Emit_265(N, X86::CMOVAE16rr, MVT::i16);
return Result;
}
@@ -49339,7 +49078,7 @@ SDNode *Select_X86ISD_CMOV_i16(SDNode *N) {
// Emits: (CMOVE16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(4)) {
- SDNode *Result = Emit_264(N, X86::CMOVE16rr, MVT::i16);
+ SDNode *Result = Emit_265(N, X86::CMOVE16rr, MVT::i16);
return Result;
}
@@ -49347,7 +49086,7 @@ SDNode *Select_X86ISD_CMOV_i16(SDNode *N) {
// Emits: (CMOVNE16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(9)) {
- SDNode *Result = Emit_264(N, X86::CMOVNE16rr, MVT::i16);
+ SDNode *Result = Emit_265(N, X86::CMOVNE16rr, MVT::i16);
return Result;
}
@@ -49355,7 +49094,7 @@ SDNode *Select_X86ISD_CMOV_i16(SDNode *N) {
// Emits: (CMOVBE16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(3)) {
- SDNode *Result = Emit_264(N, X86::CMOVBE16rr, MVT::i16);
+ SDNode *Result = Emit_265(N, X86::CMOVBE16rr, MVT::i16);
return Result;
}
@@ -49363,7 +49102,7 @@ SDNode *Select_X86ISD_CMOV_i16(SDNode *N) {
// Emits: (CMOVA16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_264(N, X86::CMOVA16rr, MVT::i16);
+ SDNode *Result = Emit_265(N, X86::CMOVA16rr, MVT::i16);
return Result;
}
@@ -49371,7 +49110,7 @@ SDNode *Select_X86ISD_CMOV_i16(SDNode *N) {
// Emits: (CMOVL16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(7)) {
- SDNode *Result = Emit_264(N, X86::CMOVL16rr, MVT::i16);
+ SDNode *Result = Emit_265(N, X86::CMOVL16rr, MVT::i16);
return Result;
}
@@ -49379,7 +49118,7 @@ SDNode *Select_X86ISD_CMOV_i16(SDNode *N) {
// Emits: (CMOVGE16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(6)) {
- SDNode *Result = Emit_264(N, X86::CMOVGE16rr, MVT::i16);
+ SDNode *Result = Emit_265(N, X86::CMOVGE16rr, MVT::i16);
return Result;
}
@@ -49387,7 +49126,7 @@ SDNode *Select_X86ISD_CMOV_i16(SDNode *N) {
// Emits: (CMOVLE16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(8)) {
- SDNode *Result = Emit_264(N, X86::CMOVLE16rr, MVT::i16);
+ SDNode *Result = Emit_265(N, X86::CMOVLE16rr, MVT::i16);
return Result;
}
@@ -49395,7 +49134,7 @@ SDNode *Select_X86ISD_CMOV_i16(SDNode *N) {
// Emits: (CMOVG16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(5)) {
- SDNode *Result = Emit_264(N, X86::CMOVG16rr, MVT::i16);
+ SDNode *Result = Emit_265(N, X86::CMOVG16rr, MVT::i16);
return Result;
}
@@ -49403,7 +49142,7 @@ SDNode *Select_X86ISD_CMOV_i16(SDNode *N) {
// Emits: (CMOVS16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(15)) {
- SDNode *Result = Emit_264(N, X86::CMOVS16rr, MVT::i16);
+ SDNode *Result = Emit_265(N, X86::CMOVS16rr, MVT::i16);
return Result;
}
@@ -49411,7 +49150,7 @@ SDNode *Select_X86ISD_CMOV_i16(SDNode *N) {
// Emits: (CMOVNS16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(12)) {
- SDNode *Result = Emit_264(N, X86::CMOVNS16rr, MVT::i16);
+ SDNode *Result = Emit_265(N, X86::CMOVNS16rr, MVT::i16);
return Result;
}
@@ -49419,7 +49158,7 @@ SDNode *Select_X86ISD_CMOV_i16(SDNode *N) {
// Emits: (CMOVP16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(14)) {
- SDNode *Result = Emit_264(N, X86::CMOVP16rr, MVT::i16);
+ SDNode *Result = Emit_265(N, X86::CMOVP16rr, MVT::i16);
return Result;
}
@@ -49427,7 +49166,7 @@ SDNode *Select_X86ISD_CMOV_i16(SDNode *N) {
// Emits: (CMOVNP16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(11)) {
- SDNode *Result = Emit_264(N, X86::CMOVNP16rr, MVT::i16);
+ SDNode *Result = Emit_265(N, X86::CMOVNP16rr, MVT::i16);
return Result;
}
@@ -49435,7 +49174,7 @@ SDNode *Select_X86ISD_CMOV_i16(SDNode *N) {
// Emits: (CMOVO16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(13)) {
- SDNode *Result = Emit_264(N, X86::CMOVO16rr, MVT::i16);
+ SDNode *Result = Emit_265(N, X86::CMOVO16rr, MVT::i16);
return Result;
}
@@ -49443,7 +49182,7 @@ SDNode *Select_X86ISD_CMOV_i16(SDNode *N) {
// Emits: (CMOVNO16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(10)) {
- SDNode *Result = Emit_264(N, X86::CMOVNO16rr, MVT::i16);
+ SDNode *Result = Emit_265(N, X86::CMOVNO16rr, MVT::i16);
return Result;
}
}
@@ -49453,304 +49192,152 @@ SDNode *Select_X86ISD_CMOV_i16(SDNode *N) {
}
SDNode *Select_X86ISD_CMOV_i32(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N->getOperand(0);
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_loadi32(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDValue N2 = N->getOperand(2);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (X86cmov:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 2:i8, EFLAGS:i32)
- // Emits: (CMOVB32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_265(N, X86::CMOVB32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 1:i8, EFLAGS:i32)
- // Emits: (CMOVAE32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(1)) {
- SDNode *Result = Emit_265(N, X86::CMOVAE32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 4:i8, EFLAGS:i32)
- // Emits: (CMOVE32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(4)) {
- SDNode *Result = Emit_265(N, X86::CMOVE32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 9:i8, EFLAGS:i32)
- // Emits: (CMOVNE32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(9)) {
- SDNode *Result = Emit_265(N, X86::CMOVNE32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 3:i8, EFLAGS:i32)
- // Emits: (CMOVBE32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(3)) {
- SDNode *Result = Emit_265(N, X86::CMOVBE32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 0:i8, EFLAGS:i32)
- // Emits: (CMOVA32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_265(N, X86::CMOVA32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 7:i8, EFLAGS:i32)
- // Emits: (CMOVL32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(7)) {
- SDNode *Result = Emit_265(N, X86::CMOVL32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 6:i8, EFLAGS:i32)
- // Emits: (CMOVGE32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(6)) {
- SDNode *Result = Emit_265(N, X86::CMOVGE32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 8:i8, EFLAGS:i32)
- // Emits: (CMOVLE32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(8)) {
- SDNode *Result = Emit_265(N, X86::CMOVLE32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 5:i8, EFLAGS:i32)
- // Emits: (CMOVG32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(5)) {
- SDNode *Result = Emit_265(N, X86::CMOVG32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 15:i8, EFLAGS:i32)
- // Emits: (CMOVS32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(15)) {
- SDNode *Result = Emit_265(N, X86::CMOVS32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 12:i8, EFLAGS:i32)
- // Emits: (CMOVNS32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(12)) {
- SDNode *Result = Emit_265(N, X86::CMOVNS32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 14:i8, EFLAGS:i32)
- // Emits: (CMOVP32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(14)) {
- SDNode *Result = Emit_265(N, X86::CMOVP32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 11:i8, EFLAGS:i32)
- // Emits: (CMOVNP32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(11)) {
- SDNode *Result = Emit_265(N, X86::CMOVNP32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 13:i8, EFLAGS:i32)
- // Emits: (CMOVO32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(13)) {
- SDNode *Result = Emit_265(N, X86::CMOVO32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 10:i8, EFLAGS:i32)
- // Emits: (CMOVNO32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(10)) {
- SDNode *Result = Emit_265(N, X86::CMOVNO32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_loadi32(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_loadi32(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
SDValue N2 = N->getOperand(2);
ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 6:i8, EFLAGS:i32)
- // Emits: (CMOVL32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
+ // Pattern: (X86cmov:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 2:i8, EFLAGS:i32)
+ // Emits: (CMOVB32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(6)) {
- SDNode *Result = Emit_266(N, X86::CMOVL32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ if (CN1 == INT64_C(2)) {
+ SDNode *Result = Emit_266(N, X86::CMOVB32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
- // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 8:i8, EFLAGS:i32)
- // Emits: (CMOVG32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
+ // Pattern: (X86cmov:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 1:i8, EFLAGS:i32)
+ // Emits: (CMOVAE32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(8)) {
- SDNode *Result = Emit_266(N, X86::CMOVG32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ if (CN1 == INT64_C(1)) {
+ SDNode *Result = Emit_266(N, X86::CMOVAE32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
- // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 5:i8, EFLAGS:i32)
- // Emits: (CMOVLE32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
+ // Pattern: (X86cmov:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 4:i8, EFLAGS:i32)
+ // Emits: (CMOVE32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(5)) {
- SDNode *Result = Emit_266(N, X86::CMOVLE32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ if (CN1 == INT64_C(4)) {
+ SDNode *Result = Emit_266(N, X86::CMOVE32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
- // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 14:i8, EFLAGS:i32)
- // Emits: (CMOVNP32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
+ // Pattern: (X86cmov:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 9:i8, EFLAGS:i32)
+ // Emits: (CMOVNE32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(14)) {
- SDNode *Result = Emit_266(N, X86::CMOVNP32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ if (CN1 == INT64_C(9)) {
+ SDNode *Result = Emit_266(N, X86::CMOVNE32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
- // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 11:i8, EFLAGS:i32)
- // Emits: (CMOVP32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
+ // Pattern: (X86cmov:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 3:i8, EFLAGS:i32)
+ // Emits: (CMOVBE32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(11)) {
- SDNode *Result = Emit_266(N, X86::CMOVP32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ if (CN1 == INT64_C(3)) {
+ SDNode *Result = Emit_266(N, X86::CMOVBE32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
- // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 15:i8, EFLAGS:i32)
- // Emits: (CMOVNS32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
+ // Pattern: (X86cmov:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 0:i8, EFLAGS:i32)
+ // Emits: (CMOVA32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(15)) {
- SDNode *Result = Emit_266(N, X86::CMOVNS32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_266(N, X86::CMOVA32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
- // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 12:i8, EFLAGS:i32)
- // Emits: (CMOVS32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
+ // Pattern: (X86cmov:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 7:i8, EFLAGS:i32)
+ // Emits: (CMOVL32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(12)) {
- SDNode *Result = Emit_266(N, X86::CMOVS32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ if (CN1 == INT64_C(7)) {
+ SDNode *Result = Emit_266(N, X86::CMOVL32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
- // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 13:i8, EFLAGS:i32)
- // Emits: (CMOVNO32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
+ // Pattern: (X86cmov:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 6:i8, EFLAGS:i32)
+ // Emits: (CMOVGE32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(13)) {
- SDNode *Result = Emit_266(N, X86::CMOVNO32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ if (CN1 == INT64_C(6)) {
+ SDNode *Result = Emit_266(N, X86::CMOVGE32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
- // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 10:i8, EFLAGS:i32)
- // Emits: (CMOVO32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
+ // Pattern: (X86cmov:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 8:i8, EFLAGS:i32)
+ // Emits: (CMOVLE32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(10)) {
- SDNode *Result = Emit_266(N, X86::CMOVO32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ if (CN1 == INT64_C(8)) {
+ SDNode *Result = Emit_266(N, X86::CMOVLE32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
- // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 2:i8, EFLAGS:i32)
- // Emits: (CMOVAE32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
+ // Pattern: (X86cmov:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 5:i8, EFLAGS:i32)
+ // Emits: (CMOVG32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_266(N, X86::CMOVAE32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ if (CN1 == INT64_C(5)) {
+ SDNode *Result = Emit_266(N, X86::CMOVG32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
- // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 1:i8, EFLAGS:i32)
- // Emits: (CMOVB32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
+ // Pattern: (X86cmov:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 15:i8, EFLAGS:i32)
+ // Emits: (CMOVS32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(1)) {
- SDNode *Result = Emit_266(N, X86::CMOVB32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ if (CN1 == INT64_C(15)) {
+ SDNode *Result = Emit_266(N, X86::CMOVS32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
- // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 4:i8, EFLAGS:i32)
- // Emits: (CMOVNE32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
+ // Pattern: (X86cmov:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 12:i8, EFLAGS:i32)
+ // Emits: (CMOVNS32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(4)) {
- SDNode *Result = Emit_266(N, X86::CMOVNE32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ if (CN1 == INT64_C(12)) {
+ SDNode *Result = Emit_266(N, X86::CMOVNS32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
- // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 9:i8, EFLAGS:i32)
- // Emits: (CMOVE32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
+ // Pattern: (X86cmov:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 14:i8, EFLAGS:i32)
+ // Emits: (CMOVP32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(9)) {
- SDNode *Result = Emit_266(N, X86::CMOVE32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ if (CN1 == INT64_C(14)) {
+ SDNode *Result = Emit_266(N, X86::CMOVP32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
- // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 3:i8, EFLAGS:i32)
- // Emits: (CMOVA32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
+ // Pattern: (X86cmov:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 11:i8, EFLAGS:i32)
+ // Emits: (CMOVNP32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(3)) {
- SDNode *Result = Emit_266(N, X86::CMOVA32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ if (CN1 == INT64_C(11)) {
+ SDNode *Result = Emit_266(N, X86::CMOVNP32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
- // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 0:i8, EFLAGS:i32)
- // Emits: (CMOVBE32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
+ // Pattern: (X86cmov:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 13:i8, EFLAGS:i32)
+ // Emits: (CMOVO32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_266(N, X86::CMOVBE32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ if (CN1 == INT64_C(13)) {
+ SDNode *Result = Emit_266(N, X86::CMOVO32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
- // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 7:i8, EFLAGS:i32)
- // Emits: (CMOVGE32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
+ // Pattern: (X86cmov:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, 10:i8, EFLAGS:i32)
+ // Emits: (CMOVNO32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(7)) {
- SDNode *Result = Emit_266(N, X86::CMOVGE32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ if (CN1 == INT64_C(10)) {
+ SDNode *Result = Emit_266(N, X86::CMOVNO32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -49758,7 +49345,156 @@ SDNode *Select_X86ISD_CMOV_i32(SDNode *N) {
}
}
}
- SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_loadi32(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 6:i8, EFLAGS:i32)
+ // Emits: (CMOVL32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(6)) {
+ SDNode *Result = Emit_267(N, X86::CMOVL32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 8:i8, EFLAGS:i32)
+ // Emits: (CMOVG32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(8)) {
+ SDNode *Result = Emit_267(N, X86::CMOVG32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 5:i8, EFLAGS:i32)
+ // Emits: (CMOVLE32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(5)) {
+ SDNode *Result = Emit_267(N, X86::CMOVLE32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 14:i8, EFLAGS:i32)
+ // Emits: (CMOVNP32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(14)) {
+ SDNode *Result = Emit_267(N, X86::CMOVNP32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 11:i8, EFLAGS:i32)
+ // Emits: (CMOVP32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(11)) {
+ SDNode *Result = Emit_267(N, X86::CMOVP32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 15:i8, EFLAGS:i32)
+ // Emits: (CMOVNS32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(15)) {
+ SDNode *Result = Emit_267(N, X86::CMOVNS32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 12:i8, EFLAGS:i32)
+ // Emits: (CMOVS32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(12)) {
+ SDNode *Result = Emit_267(N, X86::CMOVS32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 13:i8, EFLAGS:i32)
+ // Emits: (CMOVNO32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(13)) {
+ SDNode *Result = Emit_267(N, X86::CMOVNO32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 10:i8, EFLAGS:i32)
+ // Emits: (CMOVO32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(10)) {
+ SDNode *Result = Emit_267(N, X86::CMOVO32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 2:i8, EFLAGS:i32)
+ // Emits: (CMOVAE32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(2)) {
+ SDNode *Result = Emit_267(N, X86::CMOVAE32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 1:i8, EFLAGS:i32)
+ // Emits: (CMOVB32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(1)) {
+ SDNode *Result = Emit_267(N, X86::CMOVB32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 4:i8, EFLAGS:i32)
+ // Emits: (CMOVNE32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(4)) {
+ SDNode *Result = Emit_267(N, X86::CMOVNE32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 9:i8, EFLAGS:i32)
+ // Emits: (CMOVE32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(9)) {
+ SDNode *Result = Emit_267(N, X86::CMOVE32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 3:i8, EFLAGS:i32)
+ // Emits: (CMOVA32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(3)) {
+ SDNode *Result = Emit_267(N, X86::CMOVA32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 0:i8, EFLAGS:i32)
+ // Emits: (CMOVBE32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_267(N, X86::CMOVBE32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 7:i8, EFLAGS:i32)
+ // Emits: (CMOVGE32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(7)) {
+ SDNode *Result = Emit_267(N, X86::CMOVGE32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2.getNode());
@@ -49769,7 +49505,7 @@ SDNode *Select_X86ISD_CMOV_i32(SDNode *N) {
// Emits: (CMOVB32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_264(N, X86::CMOVB32rr, MVT::i32);
+ SDNode *Result = Emit_265(N, X86::CMOVB32rr, MVT::i32);
return Result;
}
@@ -49777,7 +49513,7 @@ SDNode *Select_X86ISD_CMOV_i32(SDNode *N) {
// Emits: (CMOVAE32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(1)) {
- SDNode *Result = Emit_264(N, X86::CMOVAE32rr, MVT::i32);
+ SDNode *Result = Emit_265(N, X86::CMOVAE32rr, MVT::i32);
return Result;
}
@@ -49785,7 +49521,7 @@ SDNode *Select_X86ISD_CMOV_i32(SDNode *N) {
// Emits: (CMOVE32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(4)) {
- SDNode *Result = Emit_264(N, X86::CMOVE32rr, MVT::i32);
+ SDNode *Result = Emit_265(N, X86::CMOVE32rr, MVT::i32);
return Result;
}
@@ -49793,7 +49529,7 @@ SDNode *Select_X86ISD_CMOV_i32(SDNode *N) {
// Emits: (CMOVNE32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(9)) {
- SDNode *Result = Emit_264(N, X86::CMOVNE32rr, MVT::i32);
+ SDNode *Result = Emit_265(N, X86::CMOVNE32rr, MVT::i32);
return Result;
}
@@ -49801,7 +49537,7 @@ SDNode *Select_X86ISD_CMOV_i32(SDNode *N) {
// Emits: (CMOVBE32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(3)) {
- SDNode *Result = Emit_264(N, X86::CMOVBE32rr, MVT::i32);
+ SDNode *Result = Emit_265(N, X86::CMOVBE32rr, MVT::i32);
return Result;
}
@@ -49809,7 +49545,7 @@ SDNode *Select_X86ISD_CMOV_i32(SDNode *N) {
// Emits: (CMOVA32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_264(N, X86::CMOVA32rr, MVT::i32);
+ SDNode *Result = Emit_265(N, X86::CMOVA32rr, MVT::i32);
return Result;
}
@@ -49817,7 +49553,7 @@ SDNode *Select_X86ISD_CMOV_i32(SDNode *N) {
// Emits: (CMOVL32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(7)) {
- SDNode *Result = Emit_264(N, X86::CMOVL32rr, MVT::i32);
+ SDNode *Result = Emit_265(N, X86::CMOVL32rr, MVT::i32);
return Result;
}
@@ -49825,7 +49561,7 @@ SDNode *Select_X86ISD_CMOV_i32(SDNode *N) {
// Emits: (CMOVGE32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(6)) {
- SDNode *Result = Emit_264(N, X86::CMOVGE32rr, MVT::i32);
+ SDNode *Result = Emit_265(N, X86::CMOVGE32rr, MVT::i32);
return Result;
}
@@ -49833,7 +49569,7 @@ SDNode *Select_X86ISD_CMOV_i32(SDNode *N) {
// Emits: (CMOVLE32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(8)) {
- SDNode *Result = Emit_264(N, X86::CMOVLE32rr, MVT::i32);
+ SDNode *Result = Emit_265(N, X86::CMOVLE32rr, MVT::i32);
return Result;
}
@@ -49841,7 +49577,7 @@ SDNode *Select_X86ISD_CMOV_i32(SDNode *N) {
// Emits: (CMOVG32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(5)) {
- SDNode *Result = Emit_264(N, X86::CMOVG32rr, MVT::i32);
+ SDNode *Result = Emit_265(N, X86::CMOVG32rr, MVT::i32);
return Result;
}
@@ -49849,7 +49585,7 @@ SDNode *Select_X86ISD_CMOV_i32(SDNode *N) {
// Emits: (CMOVS32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(15)) {
- SDNode *Result = Emit_264(N, X86::CMOVS32rr, MVT::i32);
+ SDNode *Result = Emit_265(N, X86::CMOVS32rr, MVT::i32);
return Result;
}
@@ -49857,7 +49593,7 @@ SDNode *Select_X86ISD_CMOV_i32(SDNode *N) {
// Emits: (CMOVNS32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(12)) {
- SDNode *Result = Emit_264(N, X86::CMOVNS32rr, MVT::i32);
+ SDNode *Result = Emit_265(N, X86::CMOVNS32rr, MVT::i32);
return Result;
}
@@ -49865,7 +49601,7 @@ SDNode *Select_X86ISD_CMOV_i32(SDNode *N) {
// Emits: (CMOVP32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(14)) {
- SDNode *Result = Emit_264(N, X86::CMOVP32rr, MVT::i32);
+ SDNode *Result = Emit_265(N, X86::CMOVP32rr, MVT::i32);
return Result;
}
@@ -49873,7 +49609,7 @@ SDNode *Select_X86ISD_CMOV_i32(SDNode *N) {
// Emits: (CMOVNP32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(11)) {
- SDNode *Result = Emit_264(N, X86::CMOVNP32rr, MVT::i32);
+ SDNode *Result = Emit_265(N, X86::CMOVNP32rr, MVT::i32);
return Result;
}
@@ -49881,7 +49617,7 @@ SDNode *Select_X86ISD_CMOV_i32(SDNode *N) {
// Emits: (CMOVO32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(13)) {
- SDNode *Result = Emit_264(N, X86::CMOVO32rr, MVT::i32);
+ SDNode *Result = Emit_265(N, X86::CMOVO32rr, MVT::i32);
return Result;
}
@@ -49889,7 +49625,7 @@ SDNode *Select_X86ISD_CMOV_i32(SDNode *N) {
// Emits: (CMOVNO32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(10)) {
- SDNode *Result = Emit_264(N, X86::CMOVNO32rr, MVT::i32);
+ SDNode *Result = Emit_265(N, X86::CMOVNO32rr, MVT::i32);
return Result;
}
}
@@ -49899,306 +49635,153 @@ SDNode *Select_X86ISD_CMOV_i32(SDNode *N) {
}
SDNode *Select_X86ISD_CMOV_i64(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N->getOperand(0);
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_loadi64(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDValue N2 = N->getOperand(2);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
-
- // Pattern: (X86cmov:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 2:i8, EFLAGS:i32)
- // Emits: (CMOVB64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_265(N, X86::CMOVB64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 1:i8, EFLAGS:i32)
- // Emits: (CMOVAE64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(1)) {
- SDNode *Result = Emit_265(N, X86::CMOVAE64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 4:i8, EFLAGS:i32)
- // Emits: (CMOVE64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(4)) {
- SDNode *Result = Emit_265(N, X86::CMOVE64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 9:i8, EFLAGS:i32)
- // Emits: (CMOVNE64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(9)) {
- SDNode *Result = Emit_265(N, X86::CMOVNE64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 3:i8, EFLAGS:i32)
- // Emits: (CMOVBE64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(3)) {
- SDNode *Result = Emit_265(N, X86::CMOVBE64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 0:i8, EFLAGS:i32)
- // Emits: (CMOVA64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_265(N, X86::CMOVA64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 7:i8, EFLAGS:i32)
- // Emits: (CMOVL64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(7)) {
- SDNode *Result = Emit_265(N, X86::CMOVL64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 6:i8, EFLAGS:i32)
- // Emits: (CMOVGE64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(6)) {
- SDNode *Result = Emit_265(N, X86::CMOVGE64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 8:i8, EFLAGS:i32)
- // Emits: (CMOVLE64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(8)) {
- SDNode *Result = Emit_265(N, X86::CMOVLE64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 5:i8, EFLAGS:i32)
- // Emits: (CMOVG64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(5)) {
- SDNode *Result = Emit_265(N, X86::CMOVG64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 15:i8, EFLAGS:i32)
- // Emits: (CMOVS64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(15)) {
- SDNode *Result = Emit_265(N, X86::CMOVS64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 12:i8, EFLAGS:i32)
- // Emits: (CMOVNS64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(12)) {
- SDNode *Result = Emit_265(N, X86::CMOVNS64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 14:i8, EFLAGS:i32)
- // Emits: (CMOVP64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(14)) {
- SDNode *Result = Emit_265(N, X86::CMOVP64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 11:i8, EFLAGS:i32)
- // Emits: (CMOVNP64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(11)) {
- SDNode *Result = Emit_265(N, X86::CMOVNP64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 13:i8, EFLAGS:i32)
- // Emits: (CMOVO64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(13)) {
- SDNode *Result = Emit_265(N, X86::CMOVO64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
-
- // Pattern: (X86cmov:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 10:i8, EFLAGS:i32)
- // Emits: (CMOVNO64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(10)) {
- SDNode *Result = Emit_265(N, X86::CMOVNO64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
- }
- }
- }
- }
- }
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_loadi64(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_loadi64(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
SDValue N2 = N->getOperand(2);
ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (X86cmov:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, 2:i8, EFLAGS:i32)
- // Emits: (CMOVAE64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
+ // Pattern: (X86cmov:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 2:i8, EFLAGS:i32)
+ // Emits: (CMOVB64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_266(N, X86::CMOVAE64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_266(N, X86::CMOVB64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
- // Pattern: (X86cmov:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, 1:i8, EFLAGS:i32)
- // Emits: (CMOVB64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
+ // Pattern: (X86cmov:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 1:i8, EFLAGS:i32)
+ // Emits: (CMOVAE64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(1)) {
- SDNode *Result = Emit_266(N, X86::CMOVB64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_266(N, X86::CMOVAE64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
- // Pattern: (X86cmov:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, 4:i8, EFLAGS:i32)
- // Emits: (CMOVNE64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
+ // Pattern: (X86cmov:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 4:i8, EFLAGS:i32)
+ // Emits: (CMOVE64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(4)) {
- SDNode *Result = Emit_266(N, X86::CMOVNE64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_266(N, X86::CMOVE64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
- // Pattern: (X86cmov:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, 9:i8, EFLAGS:i32)
- // Emits: (CMOVE64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
+ // Pattern: (X86cmov:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 9:i8, EFLAGS:i32)
+ // Emits: (CMOVNE64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(9)) {
- SDNode *Result = Emit_266(N, X86::CMOVE64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_266(N, X86::CMOVNE64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
- // Pattern: (X86cmov:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, 3:i8, EFLAGS:i32)
- // Emits: (CMOVA64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
+ // Pattern: (X86cmov:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 3:i8, EFLAGS:i32)
+ // Emits: (CMOVBE64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(3)) {
- SDNode *Result = Emit_266(N, X86::CMOVA64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_266(N, X86::CMOVBE64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
- // Pattern: (X86cmov:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, 0:i8, EFLAGS:i32)
- // Emits: (CMOVBE64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
+ // Pattern: (X86cmov:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 0:i8, EFLAGS:i32)
+ // Emits: (CMOVA64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_266(N, X86::CMOVBE64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_266(N, X86::CMOVA64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
- // Pattern: (X86cmov:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, 7:i8, EFLAGS:i32)
- // Emits: (CMOVGE64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
+ // Pattern: (X86cmov:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 7:i8, EFLAGS:i32)
+ // Emits: (CMOVL64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(7)) {
- SDNode *Result = Emit_266(N, X86::CMOVGE64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_266(N, X86::CMOVL64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
- // Pattern: (X86cmov:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, 6:i8, EFLAGS:i32)
- // Emits: (CMOVL64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
+ // Pattern: (X86cmov:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 6:i8, EFLAGS:i32)
+ // Emits: (CMOVGE64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(6)) {
- SDNode *Result = Emit_266(N, X86::CMOVL64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_266(N, X86::CMOVGE64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
- // Pattern: (X86cmov:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, 8:i8, EFLAGS:i32)
- // Emits: (CMOVG64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
+ // Pattern: (X86cmov:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 8:i8, EFLAGS:i32)
+ // Emits: (CMOVLE64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(8)) {
- SDNode *Result = Emit_266(N, X86::CMOVG64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_266(N, X86::CMOVLE64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
- // Pattern: (X86cmov:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, 5:i8, EFLAGS:i32)
- // Emits: (CMOVLE64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
+ // Pattern: (X86cmov:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 5:i8, EFLAGS:i32)
+ // Emits: (CMOVG64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(5)) {
- SDNode *Result = Emit_266(N, X86::CMOVLE64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_266(N, X86::CMOVG64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
- // Pattern: (X86cmov:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, 14:i8, EFLAGS:i32)
- // Emits: (CMOVNP64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
+ // Pattern: (X86cmov:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 15:i8, EFLAGS:i32)
+ // Emits: (CMOVS64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(14)) {
- SDNode *Result = Emit_266(N, X86::CMOVNP64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ if (CN1 == INT64_C(15)) {
+ SDNode *Result = Emit_266(N, X86::CMOVS64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
- // Pattern: (X86cmov:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, 11:i8, EFLAGS:i32)
- // Emits: (CMOVP64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
+ // Pattern: (X86cmov:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 12:i8, EFLAGS:i32)
+ // Emits: (CMOVNS64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(11)) {
- SDNode *Result = Emit_266(N, X86::CMOVP64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ if (CN1 == INT64_C(12)) {
+ SDNode *Result = Emit_266(N, X86::CMOVNS64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
- // Pattern: (X86cmov:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, 15:i8, EFLAGS:i32)
- // Emits: (CMOVNS64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
+ // Pattern: (X86cmov:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 14:i8, EFLAGS:i32)
+ // Emits: (CMOVP64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(15)) {
- SDNode *Result = Emit_266(N, X86::CMOVNS64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ if (CN1 == INT64_C(14)) {
+ SDNode *Result = Emit_266(N, X86::CMOVP64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
- // Pattern: (X86cmov:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, 12:i8, EFLAGS:i32)
- // Emits: (CMOVS64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
+ // Pattern: (X86cmov:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 11:i8, EFLAGS:i32)
+ // Emits: (CMOVNP64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(12)) {
- SDNode *Result = Emit_266(N, X86::CMOVS64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ if (CN1 == INT64_C(11)) {
+ SDNode *Result = Emit_266(N, X86::CMOVNP64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
- // Pattern: (X86cmov:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, 13:i8, EFLAGS:i32)
- // Emits: (CMOVNO64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
+ // Pattern: (X86cmov:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 13:i8, EFLAGS:i32)
+ // Emits: (CMOVO64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(13)) {
- SDNode *Result = Emit_266(N, X86::CMOVNO64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_266(N, X86::CMOVO64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
- // Pattern: (X86cmov:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, 10:i8, EFLAGS:i32)
- // Emits: (CMOVO64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
+ // Pattern: (X86cmov:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 10:i8, EFLAGS:i32)
+ // Emits: (CMOVNO64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(10)) {
- SDNode *Result = Emit_266(N, X86::CMOVO64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_266(N, X86::CMOVNO64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -50206,7 +49789,157 @@ SDNode *Select_X86ISD_CMOV_i64(SDNode *N) {
}
}
}
- SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_loadi64(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+
+ // Pattern: (X86cmov:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, 2:i8, EFLAGS:i32)
+ // Emits: (CMOVAE64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(2)) {
+ SDNode *Result = Emit_267(N, X86::CMOVAE64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, 1:i8, EFLAGS:i32)
+ // Emits: (CMOVB64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(1)) {
+ SDNode *Result = Emit_267(N, X86::CMOVB64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, 4:i8, EFLAGS:i32)
+ // Emits: (CMOVNE64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(4)) {
+ SDNode *Result = Emit_267(N, X86::CMOVNE64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, 9:i8, EFLAGS:i32)
+ // Emits: (CMOVE64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(9)) {
+ SDNode *Result = Emit_267(N, X86::CMOVE64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, 3:i8, EFLAGS:i32)
+ // Emits: (CMOVA64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(3)) {
+ SDNode *Result = Emit_267(N, X86::CMOVA64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, 0:i8, EFLAGS:i32)
+ // Emits: (CMOVBE64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(0)) {
+ SDNode *Result = Emit_267(N, X86::CMOVBE64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, 7:i8, EFLAGS:i32)
+ // Emits: (CMOVGE64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(7)) {
+ SDNode *Result = Emit_267(N, X86::CMOVGE64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, 6:i8, EFLAGS:i32)
+ // Emits: (CMOVL64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(6)) {
+ SDNode *Result = Emit_267(N, X86::CMOVL64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, 8:i8, EFLAGS:i32)
+ // Emits: (CMOVG64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(8)) {
+ SDNode *Result = Emit_267(N, X86::CMOVG64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, 5:i8, EFLAGS:i32)
+ // Emits: (CMOVLE64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(5)) {
+ SDNode *Result = Emit_267(N, X86::CMOVLE64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, 14:i8, EFLAGS:i32)
+ // Emits: (CMOVNP64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(14)) {
+ SDNode *Result = Emit_267(N, X86::CMOVNP64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, 11:i8, EFLAGS:i32)
+ // Emits: (CMOVP64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(11)) {
+ SDNode *Result = Emit_267(N, X86::CMOVP64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, 15:i8, EFLAGS:i32)
+ // Emits: (CMOVNS64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(15)) {
+ SDNode *Result = Emit_267(N, X86::CMOVNS64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, 12:i8, EFLAGS:i32)
+ // Emits: (CMOVS64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(12)) {
+ SDNode *Result = Emit_267(N, X86::CMOVS64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, 13:i8, EFLAGS:i32)
+ // Emits: (CMOVNO64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(13)) {
+ SDNode *Result = Emit_267(N, X86::CMOVNO64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, 10:i8, EFLAGS:i32)
+ // Emits: (CMOVO64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(10)) {
+ SDNode *Result = Emit_267(N, X86::CMOVO64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2.getNode());
@@ -50217,7 +49950,7 @@ SDNode *Select_X86ISD_CMOV_i64(SDNode *N) {
// Emits: (CMOVB64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_264(N, X86::CMOVB64rr, MVT::i64);
+ SDNode *Result = Emit_265(N, X86::CMOVB64rr, MVT::i64);
return Result;
}
@@ -50225,7 +49958,7 @@ SDNode *Select_X86ISD_CMOV_i64(SDNode *N) {
// Emits: (CMOVAE64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(1)) {
- SDNode *Result = Emit_264(N, X86::CMOVAE64rr, MVT::i64);
+ SDNode *Result = Emit_265(N, X86::CMOVAE64rr, MVT::i64);
return Result;
}
@@ -50233,7 +49966,7 @@ SDNode *Select_X86ISD_CMOV_i64(SDNode *N) {
// Emits: (CMOVE64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(4)) {
- SDNode *Result = Emit_264(N, X86::CMOVE64rr, MVT::i64);
+ SDNode *Result = Emit_265(N, X86::CMOVE64rr, MVT::i64);
return Result;
}
@@ -50241,7 +49974,7 @@ SDNode *Select_X86ISD_CMOV_i64(SDNode *N) {
// Emits: (CMOVNE64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(9)) {
- SDNode *Result = Emit_264(N, X86::CMOVNE64rr, MVT::i64);
+ SDNode *Result = Emit_265(N, X86::CMOVNE64rr, MVT::i64);
return Result;
}
@@ -50249,7 +49982,7 @@ SDNode *Select_X86ISD_CMOV_i64(SDNode *N) {
// Emits: (CMOVBE64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(3)) {
- SDNode *Result = Emit_264(N, X86::CMOVBE64rr, MVT::i64);
+ SDNode *Result = Emit_265(N, X86::CMOVBE64rr, MVT::i64);
return Result;
}
@@ -50257,7 +49990,7 @@ SDNode *Select_X86ISD_CMOV_i64(SDNode *N) {
// Emits: (CMOVA64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_264(N, X86::CMOVA64rr, MVT::i64);
+ SDNode *Result = Emit_265(N, X86::CMOVA64rr, MVT::i64);
return Result;
}
@@ -50265,7 +49998,7 @@ SDNode *Select_X86ISD_CMOV_i64(SDNode *N) {
// Emits: (CMOVL64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(7)) {
- SDNode *Result = Emit_264(N, X86::CMOVL64rr, MVT::i64);
+ SDNode *Result = Emit_265(N, X86::CMOVL64rr, MVT::i64);
return Result;
}
@@ -50273,7 +50006,7 @@ SDNode *Select_X86ISD_CMOV_i64(SDNode *N) {
// Emits: (CMOVGE64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(6)) {
- SDNode *Result = Emit_264(N, X86::CMOVGE64rr, MVT::i64);
+ SDNode *Result = Emit_265(N, X86::CMOVGE64rr, MVT::i64);
return Result;
}
@@ -50281,7 +50014,7 @@ SDNode *Select_X86ISD_CMOV_i64(SDNode *N) {
// Emits: (CMOVLE64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(8)) {
- SDNode *Result = Emit_264(N, X86::CMOVLE64rr, MVT::i64);
+ SDNode *Result = Emit_265(N, X86::CMOVLE64rr, MVT::i64);
return Result;
}
@@ -50289,7 +50022,7 @@ SDNode *Select_X86ISD_CMOV_i64(SDNode *N) {
// Emits: (CMOVG64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(5)) {
- SDNode *Result = Emit_264(N, X86::CMOVG64rr, MVT::i64);
+ SDNode *Result = Emit_265(N, X86::CMOVG64rr, MVT::i64);
return Result;
}
@@ -50297,7 +50030,7 @@ SDNode *Select_X86ISD_CMOV_i64(SDNode *N) {
// Emits: (CMOVS64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(15)) {
- SDNode *Result = Emit_264(N, X86::CMOVS64rr, MVT::i64);
+ SDNode *Result = Emit_265(N, X86::CMOVS64rr, MVT::i64);
return Result;
}
@@ -50305,7 +50038,7 @@ SDNode *Select_X86ISD_CMOV_i64(SDNode *N) {
// Emits: (CMOVNS64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(12)) {
- SDNode *Result = Emit_264(N, X86::CMOVNS64rr, MVT::i64);
+ SDNode *Result = Emit_265(N, X86::CMOVNS64rr, MVT::i64);
return Result;
}
@@ -50313,7 +50046,7 @@ SDNode *Select_X86ISD_CMOV_i64(SDNode *N) {
// Emits: (CMOVP64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(14)) {
- SDNode *Result = Emit_264(N, X86::CMOVP64rr, MVT::i64);
+ SDNode *Result = Emit_265(N, X86::CMOVP64rr, MVT::i64);
return Result;
}
@@ -50321,7 +50054,7 @@ SDNode *Select_X86ISD_CMOV_i64(SDNode *N) {
// Emits: (CMOVNP64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(11)) {
- SDNode *Result = Emit_264(N, X86::CMOVNP64rr, MVT::i64);
+ SDNode *Result = Emit_265(N, X86::CMOVNP64rr, MVT::i64);
return Result;
}
@@ -50329,7 +50062,7 @@ SDNode *Select_X86ISD_CMOV_i64(SDNode *N) {
// Emits: (CMOVO64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(13)) {
- SDNode *Result = Emit_264(N, X86::CMOVO64rr, MVT::i64);
+ SDNode *Result = Emit_265(N, X86::CMOVO64rr, MVT::i64);
return Result;
}
@@ -50337,7 +50070,7 @@ SDNode *Select_X86ISD_CMOV_i64(SDNode *N) {
// Emits: (CMOVNO64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(10)) {
- SDNode *Result = Emit_264(N, X86::CMOVNO64rr, MVT::i64);
+ SDNode *Result = Emit_265(N, X86::CMOVNO64rr, MVT::i64);
return Result;
}
}
@@ -50359,7 +50092,7 @@ SDNode *Select_X86ISD_CMOV_f32(SDNode *N) {
// Emits: (CMOVB_Fp32:f32 RFP32:f32:$src1, RFP32:f32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_264(N, X86::CMOVB_Fp32, MVT::f32);
+ SDNode *Result = Emit_265(N, X86::CMOVB_Fp32, MVT::f32);
return Result;
}
@@ -50367,7 +50100,7 @@ SDNode *Select_X86ISD_CMOV_f32(SDNode *N) {
// Emits: (CMOVBE_Fp32:f32 RFP32:f32:$src1, RFP32:f32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(3)) {
- SDNode *Result = Emit_264(N, X86::CMOVBE_Fp32, MVT::f32);
+ SDNode *Result = Emit_265(N, X86::CMOVBE_Fp32, MVT::f32);
return Result;
}
@@ -50375,7 +50108,7 @@ SDNode *Select_X86ISD_CMOV_f32(SDNode *N) {
// Emits: (CMOVE_Fp32:f32 RFP32:f32:$src1, RFP32:f32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(4)) {
- SDNode *Result = Emit_264(N, X86::CMOVE_Fp32, MVT::f32);
+ SDNode *Result = Emit_265(N, X86::CMOVE_Fp32, MVT::f32);
return Result;
}
@@ -50383,7 +50116,7 @@ SDNode *Select_X86ISD_CMOV_f32(SDNode *N) {
// Emits: (CMOVP_Fp32:f32 RFP32:f32:$src1, RFP32:f32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(14)) {
- SDNode *Result = Emit_264(N, X86::CMOVP_Fp32, MVT::f32);
+ SDNode *Result = Emit_265(N, X86::CMOVP_Fp32, MVT::f32);
return Result;
}
@@ -50391,7 +50124,7 @@ SDNode *Select_X86ISD_CMOV_f32(SDNode *N) {
// Emits: (CMOVNB_Fp32:f32 RFP32:f32:$src1, RFP32:f32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(1)) {
- SDNode *Result = Emit_264(N, X86::CMOVNB_Fp32, MVT::f32);
+ SDNode *Result = Emit_265(N, X86::CMOVNB_Fp32, MVT::f32);
return Result;
}
@@ -50399,7 +50132,7 @@ SDNode *Select_X86ISD_CMOV_f32(SDNode *N) {
// Emits: (CMOVNBE_Fp32:f32 RFP32:f32:$src1, RFP32:f32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_264(N, X86::CMOVNBE_Fp32, MVT::f32);
+ SDNode *Result = Emit_265(N, X86::CMOVNBE_Fp32, MVT::f32);
return Result;
}
@@ -50407,7 +50140,7 @@ SDNode *Select_X86ISD_CMOV_f32(SDNode *N) {
// Emits: (CMOVNE_Fp32:f32 RFP32:f32:$src1, RFP32:f32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(9)) {
- SDNode *Result = Emit_264(N, X86::CMOVNE_Fp32, MVT::f32);
+ SDNode *Result = Emit_265(N, X86::CMOVNE_Fp32, MVT::f32);
return Result;
}
@@ -50415,7 +50148,7 @@ SDNode *Select_X86ISD_CMOV_f32(SDNode *N) {
// Emits: (CMOVNP_Fp32:f32 RFP32:f32:$src1, RFP32:f32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(11)) {
- SDNode *Result = Emit_264(N, X86::CMOVNP_Fp32, MVT::f32);
+ SDNode *Result = Emit_265(N, X86::CMOVNP_Fp32, MVT::f32);
return Result;
}
}
@@ -50428,7 +50161,7 @@ SDNode *Select_X86ISD_CMOV_f32(SDNode *N) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_263(N, X86::CMOV_FR32, MVT::f32);
+ SDNode *Result = Emit_264(N, X86::CMOV_FR32, MVT::f32);
return Result;
}
@@ -50449,7 +50182,7 @@ SDNode *Select_X86ISD_CMOV_f64(SDNode *N) {
// Emits: (CMOVB_Fp64:f64 RFP64:f64:$src1, RFP64:f64:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_264(N, X86::CMOVB_Fp64, MVT::f64);
+ SDNode *Result = Emit_265(N, X86::CMOVB_Fp64, MVT::f64);
return Result;
}
@@ -50457,7 +50190,7 @@ SDNode *Select_X86ISD_CMOV_f64(SDNode *N) {
// Emits: (CMOVBE_Fp64:f64 RFP64:f64:$src1, RFP64:f64:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(3)) {
- SDNode *Result = Emit_264(N, X86::CMOVBE_Fp64, MVT::f64);
+ SDNode *Result = Emit_265(N, X86::CMOVBE_Fp64, MVT::f64);
return Result;
}
@@ -50465,7 +50198,7 @@ SDNode *Select_X86ISD_CMOV_f64(SDNode *N) {
// Emits: (CMOVE_Fp64:f64 RFP64:f64:$src1, RFP64:f64:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(4)) {
- SDNode *Result = Emit_264(N, X86::CMOVE_Fp64, MVT::f64);
+ SDNode *Result = Emit_265(N, X86::CMOVE_Fp64, MVT::f64);
return Result;
}
@@ -50473,7 +50206,7 @@ SDNode *Select_X86ISD_CMOV_f64(SDNode *N) {
// Emits: (CMOVP_Fp64:f64 RFP64:f64:$src1, RFP64:f64:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(14)) {
- SDNode *Result = Emit_264(N, X86::CMOVP_Fp64, MVT::f64);
+ SDNode *Result = Emit_265(N, X86::CMOVP_Fp64, MVT::f64);
return Result;
}
@@ -50481,7 +50214,7 @@ SDNode *Select_X86ISD_CMOV_f64(SDNode *N) {
// Emits: (CMOVNB_Fp64:f64 RFP64:f64:$src1, RFP64:f64:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(1)) {
- SDNode *Result = Emit_264(N, X86::CMOVNB_Fp64, MVT::f64);
+ SDNode *Result = Emit_265(N, X86::CMOVNB_Fp64, MVT::f64);
return Result;
}
@@ -50489,7 +50222,7 @@ SDNode *Select_X86ISD_CMOV_f64(SDNode *N) {
// Emits: (CMOVNBE_Fp64:f64 RFP64:f64:$src1, RFP64:f64:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_264(N, X86::CMOVNBE_Fp64, MVT::f64);
+ SDNode *Result = Emit_265(N, X86::CMOVNBE_Fp64, MVT::f64);
return Result;
}
@@ -50497,7 +50230,7 @@ SDNode *Select_X86ISD_CMOV_f64(SDNode *N) {
// Emits: (CMOVNE_Fp64:f64 RFP64:f64:$src1, RFP64:f64:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(9)) {
- SDNode *Result = Emit_264(N, X86::CMOVNE_Fp64, MVT::f64);
+ SDNode *Result = Emit_265(N, X86::CMOVNE_Fp64, MVT::f64);
return Result;
}
@@ -50505,7 +50238,7 @@ SDNode *Select_X86ISD_CMOV_f64(SDNode *N) {
// Emits: (CMOVNP_Fp64:f64 RFP64:f64:$src1, RFP64:f64:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(11)) {
- SDNode *Result = Emit_264(N, X86::CMOVNP_Fp64, MVT::f64);
+ SDNode *Result = Emit_265(N, X86::CMOVNP_Fp64, MVT::f64);
return Result;
}
}
@@ -50518,7 +50251,7 @@ SDNode *Select_X86ISD_CMOV_f64(SDNode *N) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_263(N, X86::CMOV_FR64, MVT::f64);
+ SDNode *Result = Emit_264(N, X86::CMOV_FR64, MVT::f64);
return Result;
}
@@ -50538,7 +50271,7 @@ SDNode *Select_X86ISD_CMOV_f80(SDNode *N) {
// Emits: (CMOVB_Fp80:f80 RFP80:f80:$src1, RFP80:f80:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_264(N, X86::CMOVB_Fp80, MVT::f80);
+ SDNode *Result = Emit_265(N, X86::CMOVB_Fp80, MVT::f80);
return Result;
}
@@ -50546,7 +50279,7 @@ SDNode *Select_X86ISD_CMOV_f80(SDNode *N) {
// Emits: (CMOVBE_Fp80:f80 RFP80:f80:$src1, RFP80:f80:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(3)) {
- SDNode *Result = Emit_264(N, X86::CMOVBE_Fp80, MVT::f80);
+ SDNode *Result = Emit_265(N, X86::CMOVBE_Fp80, MVT::f80);
return Result;
}
@@ -50554,7 +50287,7 @@ SDNode *Select_X86ISD_CMOV_f80(SDNode *N) {
// Emits: (CMOVE_Fp80:f80 RFP80:f80:$src1, RFP80:f80:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(4)) {
- SDNode *Result = Emit_264(N, X86::CMOVE_Fp80, MVT::f80);
+ SDNode *Result = Emit_265(N, X86::CMOVE_Fp80, MVT::f80);
return Result;
}
@@ -50562,7 +50295,7 @@ SDNode *Select_X86ISD_CMOV_f80(SDNode *N) {
// Emits: (CMOVP_Fp80:f80 RFP80:f80:$src1, RFP80:f80:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(14)) {
- SDNode *Result = Emit_264(N, X86::CMOVP_Fp80, MVT::f80);
+ SDNode *Result = Emit_265(N, X86::CMOVP_Fp80, MVT::f80);
return Result;
}
@@ -50570,7 +50303,7 @@ SDNode *Select_X86ISD_CMOV_f80(SDNode *N) {
// Emits: (CMOVNB_Fp80:f80 RFP80:f80:$src1, RFP80:f80:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(1)) {
- SDNode *Result = Emit_264(N, X86::CMOVNB_Fp80, MVT::f80);
+ SDNode *Result = Emit_265(N, X86::CMOVNB_Fp80, MVT::f80);
return Result;
}
@@ -50578,7 +50311,7 @@ SDNode *Select_X86ISD_CMOV_f80(SDNode *N) {
// Emits: (CMOVNBE_Fp80:f80 RFP80:f80:$src1, RFP80:f80:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_264(N, X86::CMOVNBE_Fp80, MVT::f80);
+ SDNode *Result = Emit_265(N, X86::CMOVNBE_Fp80, MVT::f80);
return Result;
}
@@ -50586,7 +50319,7 @@ SDNode *Select_X86ISD_CMOV_f80(SDNode *N) {
// Emits: (CMOVNE_Fp80:f80 RFP80:f80:$src1, RFP80:f80:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(9)) {
- SDNode *Result = Emit_264(N, X86::CMOVNE_Fp80, MVT::f80);
+ SDNode *Result = Emit_265(N, X86::CMOVNE_Fp80, MVT::f80);
return Result;
}
@@ -50594,7 +50327,7 @@ SDNode *Select_X86ISD_CMOV_f80(SDNode *N) {
// Emits: (CMOVNP_Fp80:f80 RFP80:f80:$src1, RFP80:f80:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(11)) {
- SDNode *Result = Emit_264(N, X86::CMOVNP_Fp80, MVT::f80);
+ SDNode *Result = Emit_265(N, X86::CMOVNP_Fp80, MVT::f80);
return Result;
}
}
@@ -50608,7 +50341,7 @@ SDNode *Select_X86ISD_CMOV_v1i64(SDNode *N) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_263(N, X86::CMOV_V1I64, MVT::v1i64);
+ SDNode *Result = Emit_264(N, X86::CMOV_V1I64, MVT::v1i64);
return Result;
}
@@ -50621,7 +50354,7 @@ SDNode *Select_X86ISD_CMOV_v2i64(SDNode *N) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_263(N, X86::CMOV_V2I64, MVT::v2i64);
+ SDNode *Result = Emit_264(N, X86::CMOV_V2I64, MVT::v2i64);
return Result;
}
@@ -50634,7 +50367,7 @@ SDNode *Select_X86ISD_CMOV_v4f32(SDNode *N) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_263(N, X86::CMOV_V4F32, MVT::v4f32);
+ SDNode *Result = Emit_264(N, X86::CMOV_V4F32, MVT::v4f32);
return Result;
}
@@ -50647,7 +50380,7 @@ SDNode *Select_X86ISD_CMOV_v2f64(SDNode *N) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
if (N2.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_263(N, X86::CMOV_V2F64, MVT::v2f64);
+ SDNode *Result = Emit_264(N, X86::CMOV_V2F64, MVT::v2f64);
return Result;
}
@@ -50655,14 +50388,14 @@ SDNode *Select_X86ISD_CMOV_v2f64(SDNode *N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_267(SDNode *N, unsigned Opc0) {
+DISABLE_INLINE SDNode *Emit_268(SDNode *N, unsigned Opc0) {
SDValue N0 = N->getOperand(0);
SDValue N00 = N0.getNode()->getOperand(0);
SDValue N01 = N0.getNode()->getOperand(1);
SDValue N1 = N->getOperand(1);
return CurDAG->SelectNodeTo(N, Opc0, MVT::i32, N00, N01);
}
-DISABLE_INLINE SDNode *Emit_268(SDNode *N, unsigned Opc0, SDValue &CPTmpN011_0, SDValue &CPTmpN011_1, SDValue &CPTmpN011_2, SDValue &CPTmpN011_3, SDValue &CPTmpN011_4) {
+DISABLE_INLINE SDNode *Emit_269(SDNode *N, unsigned Opc0, SDValue &CPTmpN011_0, SDValue &CPTmpN011_1, SDValue &CPTmpN011_2, SDValue &CPTmpN011_3, SDValue &CPTmpN011_4) {
SDValue N0 = N->getOperand(0);
SDValue N00 = N0.getNode()->getOperand(0);
SDValue N01 = N0.getNode()->getOperand(1);
@@ -50677,7 +50410,7 @@ DISABLE_INLINE SDNode *Emit_268(SDNode *N, unsigned Opc0, SDValue &CPTmpN011_0,
ReplaceUses(SDValue(N01.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_269(SDNode *N, unsigned Opc0) {
+DISABLE_INLINE SDNode *Emit_270(SDNode *N, unsigned Opc0) {
SDValue N0 = N->getOperand(0);
SDValue N00 = N0.getNode()->getOperand(0);
SDValue N01 = N0.getNode()->getOperand(1);
@@ -50685,7 +50418,7 @@ DISABLE_INLINE SDNode *Emit_269(SDNode *N, unsigned Opc0) {
SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N01)->getZExtValue()), MVT::i8);
return CurDAG->SelectNodeTo(N, Opc0, MVT::i32, N00, Tmp3);
}
-DISABLE_INLINE SDNode *Emit_270(SDNode *N, unsigned Opc0) {
+DISABLE_INLINE SDNode *Emit_271(SDNode *N, unsigned Opc0) {
SDValue N0 = N->getOperand(0);
SDValue N00 = N0.getNode()->getOperand(0);
SDValue N01 = N0.getNode()->getOperand(1);
@@ -50693,7 +50426,7 @@ DISABLE_INLINE SDNode *Emit_270(SDNode *N, unsigned Opc0) {
SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned short) cast<ConstantSDNode>(N01)->getZExtValue()), MVT::i16);
return CurDAG->SelectNodeTo(N, Opc0, MVT::i32, N00, Tmp3);
}
-DISABLE_INLINE SDNode *Emit_271(SDNode *N, unsigned Opc0) {
+DISABLE_INLINE SDNode *Emit_272(SDNode *N, unsigned Opc0) {
SDValue N0 = N->getOperand(0);
SDValue N00 = N0.getNode()->getOperand(0);
SDValue N01 = N0.getNode()->getOperand(1);
@@ -50701,7 +50434,7 @@ DISABLE_INLINE SDNode *Emit_271(SDNode *N, unsigned Opc0) {
SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N01)->getZExtValue()), MVT::i32);
return CurDAG->SelectNodeTo(N, Opc0, MVT::i32, N00, Tmp3);
}
-DISABLE_INLINE SDNode *Emit_272(SDNode *N, unsigned Opc0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
+DISABLE_INLINE SDNode *Emit_273(SDNode *N, unsigned Opc0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
SDValue N0 = N->getOperand(0);
SDValue N00 = N0.getNode()->getOperand(0);
SDValue Chain00 = N00.getNode()->getOperand(0);
@@ -50717,7 +50450,7 @@ DISABLE_INLINE SDNode *Emit_272(SDNode *N, unsigned Opc0, SDValue &CPTmpN001_0,
ReplaceUses(SDValue(N00.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_273(SDNode *N, unsigned Opc0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
+DISABLE_INLINE SDNode *Emit_274(SDNode *N, unsigned Opc0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
SDValue N0 = N->getOperand(0);
SDValue N00 = N0.getNode()->getOperand(0);
SDValue Chain00 = N00.getNode()->getOperand(0);
@@ -50733,7 +50466,7 @@ DISABLE_INLINE SDNode *Emit_273(SDNode *N, unsigned Opc0, SDValue &CPTmpN001_0,
ReplaceUses(SDValue(N00.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_274(SDNode *N, unsigned Opc0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
+DISABLE_INLINE SDNode *Emit_275(SDNode *N, unsigned Opc0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
SDValue N0 = N->getOperand(0);
SDValue N00 = N0.getNode()->getOperand(0);
SDValue Chain00 = N00.getNode()->getOperand(0);
@@ -50749,7 +50482,7 @@ DISABLE_INLINE SDNode *Emit_274(SDNode *N, unsigned Opc0, SDValue &CPTmpN001_0,
ReplaceUses(SDValue(N00.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_275(SDNode *N, unsigned Opc0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+DISABLE_INLINE SDNode *Emit_276(SDNode *N, unsigned Opc0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
SDValue N0 = N->getOperand(0);
SDValue Chain0 = N0.getNode()->getOperand(0);
SDValue N01 = N0.getNode()->getOperand(1);
@@ -50762,7 +50495,7 @@ DISABLE_INLINE SDNode *Emit_275(SDNode *N, unsigned Opc0, SDValue &CPTmpN01_0, S
ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_276(SDNode *N, unsigned Opc0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
+DISABLE_INLINE SDNode *Emit_277(SDNode *N, unsigned Opc0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
SDValue Chain1 = N1.getNode()->getOperand(0);
@@ -50775,13 +50508,13 @@ DISABLE_INLINE SDNode *Emit_276(SDNode *N, unsigned Opc0, SDValue &CPTmpN11_0, S
ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_277(SDNode *N, unsigned Opc0) {
+DISABLE_INLINE SDNode *Emit_278(SDNode *N, unsigned Opc0) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i8);
return CurDAG->SelectNodeTo(N, Opc0, MVT::i32, N0, Tmp1);
}
-DISABLE_INLINE SDNode *Emit_278(SDNode *N, unsigned Opc0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+DISABLE_INLINE SDNode *Emit_279(SDNode *N, unsigned Opc0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
SDValue N0 = N->getOperand(0);
SDValue Chain0 = N0.getNode()->getOperand(0);
SDValue N01 = N0.getNode()->getOperand(1);
@@ -50795,7 +50528,7 @@ DISABLE_INLINE SDNode *Emit_278(SDNode *N, unsigned Opc0, SDValue &CPTmpN01_0, S
ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_279(SDNode *N, unsigned Opc0) {
+DISABLE_INLINE SDNode *Emit_280(SDNode *N, unsigned Opc0) {
SDValue N0 = N->getOperand(0);
SDValue N00 = N0.getNode()->getOperand(0);
SDValue N01 = N0.getNode()->getOperand(1);
@@ -50803,7 +50536,7 @@ DISABLE_INLINE SDNode *Emit_279(SDNode *N, unsigned Opc0) {
SDValue Tmp3 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N01)->getZExtValue()), MVT::i64);
return CurDAG->SelectNodeTo(N, Opc0, MVT::i32, N00, Tmp3);
}
-DISABLE_INLINE SDNode *Emit_280(SDNode *N, unsigned Opc0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
+DISABLE_INLINE SDNode *Emit_281(SDNode *N, unsigned Opc0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
SDValue N0 = N->getOperand(0);
SDValue N00 = N0.getNode()->getOperand(0);
SDValue Chain00 = N00.getNode()->getOperand(0);
@@ -50819,12 +50552,12 @@ DISABLE_INLINE SDNode *Emit_280(SDNode *N, unsigned Opc0, SDValue &CPTmpN001_0,
ReplaceUses(SDValue(N00.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_281(SDNode *N, unsigned Opc0) {
+DISABLE_INLINE SDNode *Emit_282(SDNode *N, unsigned Opc0) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
return CurDAG->SelectNodeTo(N, Opc0, MVT::i32, N0, N0);
}
-DISABLE_INLINE SDNode *Emit_282(SDNode *N, unsigned Opc0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
+DISABLE_INLINE SDNode *Emit_283(SDNode *N, unsigned Opc0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
SDValue N0 = N->getOperand(0);
SDValue N00 = N0.getNode()->getOperand(0);
SDValue Chain00 = N00.getNode()->getOperand(0);
@@ -50840,79 +50573,22 @@ DISABLE_INLINE SDNode *Emit_282(SDNode *N, unsigned Opc0, SDValue &CPTmpN001_0,
return ResNode;
}
SDNode *Select_X86ISD_CMP(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
- {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::AND &&
- N0.hasOneUse()) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::LOAD &&
- N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
- SDValue Chain00 = N00.getNode()->getOperand(0);
- if (Predicate_unindexedload(N00.getNode())) {
- if (Predicate_load(N00.getNode())) {
-
- // Pattern: (X86cmp:isVoid (and:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2), 0:i64)
- // Emits: (TEST64mi32:isVoid addr:iPTR:$src1, (imm:i64):$src2)
- // Pattern complexity = 37 cost = 1 size = 3
- if (Predicate_loadi64(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant &&
- Predicate_i64immSExt32(N01.getNode())) {
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0) &&
- N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_280(N, X86::TEST64mi32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (X86cmp:isVoid (and:i8 (ld:i8 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src2), 0:i8)
- // Emits: (TEST8mi:isVoid addr:iPTR:$src1, (imm:i8):$src2)
- // Pattern complexity = 36 cost = 1 size = 3
- if (Predicate_loadi8(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant) {
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0) &&
- N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_272(N, X86::TEST8mi, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
- }
- }
- }
- }
- }
- }
+ {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::AND &&
+ N0.hasOneUse()) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::LOAD &&
+ N00.hasOneUse() &&
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
+ SDValue Chain00 = N00.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N00.getNode())) {
+ if (Predicate_load(N00.getNode())) {
- // Pattern: (X86cmp:isVoid (and:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16):$src2), 0:i16)
- // Emits: (TEST16mi:isVoid addr:iPTR:$src1, (imm:i16):$src2)
- // Pattern complexity = 36 cost = 1 size = 3
- if (Predicate_loadi16(N00.getNode())) {
+ // Pattern: (X86cmp:isVoid (and:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2), 0:i64)
+ // Emits: (TEST64mi32:isVoid addr:iPTR:$src1, (imm:i64):$src2)
+ // Pattern complexity = 37 cost = 1 size = 3
+ if (Predicate_loadi64(N00.getNode())) {
SDValue N001 = N00.getNode()->getOperand(1);
SDValue CPTmpN001_0;
SDValue CPTmpN001_1;
@@ -50921,14 +50597,15 @@ SDNode *Select_X86ISD_CMP(SDNode *N) {
SDValue CPTmpN001_4;
if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::Constant) {
+ if (N01.getNode()->getOpcode() == ISD::Constant &&
+ Predicate_i64immSExt32(N01.getNode())) {
SDValue N1 = N->getOperand(1);
ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
- N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_273(N, X86::TEST16mi, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ N0.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_281(N, X86::TEST64mi32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
}
@@ -50936,10 +50613,10 @@ SDNode *Select_X86ISD_CMP(SDNode *N) {
}
}
- // Pattern: (X86cmp:isVoid (and:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32):$src2), 0:i32)
- // Emits: (TEST32mi:isVoid addr:iPTR:$src1, (imm:i32):$src2)
+ // Pattern: (X86cmp:isVoid (and:i8 (ld:i8 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src2), 0:i8)
+ // Emits: (TEST8mi:isVoid addr:iPTR:$src1, (imm:i8):$src2)
// Pattern complexity = 36 cost = 1 size = 3
- if (Predicate_loadi32(N00.getNode())) {
+ if (Predicate_loadi8(N00.getNode())) {
SDValue N001 = N00.getNode()->getOperand(1);
SDValue CPTmpN001_0;
SDValue CPTmpN001_1;
@@ -50954,8 +50631,8 @@ SDNode *Select_X86ISD_CMP(SDNode *N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
- N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_274(N, X86::TEST32mi, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ N0.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_273(N, X86::TEST8mi, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
}
@@ -50963,217 +50640,162 @@ SDNode *Select_X86ISD_CMP(SDNode *N) {
}
}
}
- }
- {
- SDValue N01 = N0.getNode()->getOperand(1);
- if (N01.getNode()->getOpcode() == ISD::LOAD &&
- N01.hasOneUse() &&
- IsLegalAndProfitableToFold(N01.getNode(), N0.getNode(), N)) {
- SDValue Chain01 = N01.getNode()->getOperand(0);
- if (Predicate_unindexedload(N01.getNode())) {
-
- // Pattern: (X86cmp:isVoid (and:i8 GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>), 0:i8)
- // Emits: (TEST8rm:isVoid GR8:i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (Predicate_load(N01.getNode()) &&
- Predicate_loadi8(N01.getNode())) {
- SDValue N011 = N01.getNode()->getOperand(1);
- SDValue CPTmpN011_0;
- SDValue CPTmpN011_1;
- SDValue CPTmpN011_2;
- SDValue CPTmpN011_3;
- SDValue CPTmpN011_4;
- if (SelectAddr(N, N011, CPTmpN011_0, CPTmpN011_1, CPTmpN011_2, CPTmpN011_3, CPTmpN011_4)) {
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0) &&
- N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_268(N, X86::TEST8rm, CPTmpN011_0, CPTmpN011_1, CPTmpN011_2, CPTmpN011_3, CPTmpN011_4);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (X86cmp:isVoid (and:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>), 0:i16)
- // Emits: (TEST16rm:isVoid GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (Predicate_loadi16(N01.getNode())) {
- SDValue N011 = N01.getNode()->getOperand(1);
- SDValue CPTmpN011_0;
- SDValue CPTmpN011_1;
- SDValue CPTmpN011_2;
- SDValue CPTmpN011_3;
- SDValue CPTmpN011_4;
- if (SelectAddr(N, N011, CPTmpN011_0, CPTmpN011_1, CPTmpN011_2, CPTmpN011_3, CPTmpN011_4)) {
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0) &&
- N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_268(N, X86::TEST16rm, CPTmpN011_0, CPTmpN011_1, CPTmpN011_2, CPTmpN011_3, CPTmpN011_4);
- return Result;
- }
- }
- }
- }
- // Pattern: (X86cmp:isVoid (and:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>), 0:i32)
- // Emits: (TEST32rm:isVoid GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (Predicate_loadi32(N01.getNode())) {
- SDValue N011 = N01.getNode()->getOperand(1);
- SDValue CPTmpN011_0;
- SDValue CPTmpN011_1;
- SDValue CPTmpN011_2;
- SDValue CPTmpN011_3;
- SDValue CPTmpN011_4;
- if (SelectAddr(N, N011, CPTmpN011_0, CPTmpN011_1, CPTmpN011_2, CPTmpN011_3, CPTmpN011_4)) {
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0) &&
- N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_268(N, X86::TEST32rm, CPTmpN011_0, CPTmpN011_1, CPTmpN011_2, CPTmpN011_3, CPTmpN011_4);
- return Result;
- }
+ // Pattern: (X86cmp:isVoid (and:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16):$src2), 0:i16)
+ // Emits: (TEST16mi:isVoid addr:iPTR:$src1, (imm:i16):$src2)
+ // Pattern complexity = 36 cost = 1 size = 3
+ if (Predicate_loadi16(N00.getNode())) {
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0) &&
+ N0.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_274(N, X86::TEST16mi, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
}
}
}
+ }
+ }
- // Pattern: (X86cmp:isVoid (and:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>), 0:i64)
- // Emits: (TEST64rm:isVoid GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 33 cost = 1 size = 3
- if (Predicate_load(N01.getNode()) &&
- Predicate_loadi64(N01.getNode())) {
- SDValue N011 = N01.getNode()->getOperand(1);
- SDValue CPTmpN011_0;
- SDValue CPTmpN011_1;
- SDValue CPTmpN011_2;
- SDValue CPTmpN011_3;
- SDValue CPTmpN011_4;
- if (SelectAddr(N, N011, CPTmpN011_0, CPTmpN011_1, CPTmpN011_2, CPTmpN011_3, CPTmpN011_4)) {
- SDValue N1 = N->getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0) &&
- N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_268(N, X86::TEST64rm, CPTmpN011_0, CPTmpN011_1, CPTmpN011_2, CPTmpN011_3, CPTmpN011_4);
- return Result;
- }
+ // Pattern: (X86cmp:isVoid (and:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32):$src2), 0:i32)
+ // Emits: (TEST32mi:isVoid addr:iPTR:$src1, (imm:i32):$src2)
+ // Pattern complexity = 36 cost = 1 size = 3
+ if (Predicate_loadi32(N00.getNode())) {
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0) &&
+ N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_275(N, X86::TEST32mi, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
}
}
}
}
}
}
- if (N00.getNode()->getOpcode() == ISD::LOAD &&
- N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
- SDValue Chain00 = N00.getNode()->getOperand(0);
- if (Predicate_unindexedload(N00.getNode())) {
+ }
+ {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::LOAD &&
+ N01.hasOneUse() &&
+ IsLegalAndProfitableToFold(N01.getNode(), N0.getNode(), N)) {
+ SDValue Chain01 = N01.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N01.getNode())) {
- // Pattern: (X86cmp:isVoid (and:i8 (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, GR8:i8:$src1), 0:i8)
+ // Pattern: (X86cmp:isVoid (and:i8 GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>), 0:i8)
// Emits: (TEST8rm:isVoid GR8:i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (Predicate_load(N00.getNode()) &&
- Predicate_loadi8(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N01 = N0.getNode()->getOperand(1);
+ if (Predicate_load(N01.getNode()) &&
+ Predicate_loadi8(N01.getNode())) {
+ SDValue N011 = N01.getNode()->getOperand(1);
+ SDValue CPTmpN011_0;
+ SDValue CPTmpN011_1;
+ SDValue CPTmpN011_2;
+ SDValue CPTmpN011_3;
+ SDValue CPTmpN011_4;
+ if (SelectAddr(N, N011, CPTmpN011_0, CPTmpN011_1, CPTmpN011_2, CPTmpN011_3, CPTmpN011_4)) {
SDValue N1 = N->getOperand(1);
ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_282(N, X86::TEST8rm, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_269(N, X86::TEST8rm, CPTmpN011_0, CPTmpN011_1, CPTmpN011_2, CPTmpN011_3, CPTmpN011_4);
return Result;
}
}
}
}
- // Pattern: (X86cmp:isVoid (and:i16 (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src1), 0:i16)
+ // Pattern: (X86cmp:isVoid (and:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>), 0:i16)
// Emits: (TEST16rm:isVoid GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (Predicate_loadi16(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N01 = N0.getNode()->getOperand(1);
+ if (Predicate_loadi16(N01.getNode())) {
+ SDValue N011 = N01.getNode()->getOperand(1);
+ SDValue CPTmpN011_0;
+ SDValue CPTmpN011_1;
+ SDValue CPTmpN011_2;
+ SDValue CPTmpN011_3;
+ SDValue CPTmpN011_4;
+ if (SelectAddr(N, N011, CPTmpN011_0, CPTmpN011_1, CPTmpN011_2, CPTmpN011_3, CPTmpN011_4)) {
SDValue N1 = N->getOperand(1);
ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_282(N, X86::TEST16rm, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_269(N, X86::TEST16rm, CPTmpN011_0, CPTmpN011_1, CPTmpN011_2, CPTmpN011_3, CPTmpN011_4);
return Result;
}
}
}
}
- // Pattern: (X86cmp:isVoid (and:i32 (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src1), 0:i32)
+ // Pattern: (X86cmp:isVoid (and:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>), 0:i32)
// Emits: (TEST32rm:isVoid GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (Predicate_loadi32(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N01 = N0.getNode()->getOperand(1);
+ if (Predicate_loadi32(N01.getNode())) {
+ SDValue N011 = N01.getNode()->getOperand(1);
+ SDValue CPTmpN011_0;
+ SDValue CPTmpN011_1;
+ SDValue CPTmpN011_2;
+ SDValue CPTmpN011_3;
+ SDValue CPTmpN011_4;
+ if (SelectAddr(N, N011, CPTmpN011_0, CPTmpN011_1, CPTmpN011_2, CPTmpN011_3, CPTmpN011_4)) {
SDValue N1 = N->getOperand(1);
ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_282(N, X86::TEST32rm, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_269(N, X86::TEST32rm, CPTmpN011_0, CPTmpN011_1, CPTmpN011_2, CPTmpN011_3, CPTmpN011_4);
return Result;
}
}
}
}
- // Pattern: (X86cmp:isVoid (and:i64 (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src1), 0:i64)
+ // Pattern: (X86cmp:isVoid (and:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>), 0:i64)
// Emits: (TEST64rm:isVoid GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (Predicate_load(N00.getNode()) &&
- Predicate_loadi64(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N01 = N0.getNode()->getOperand(1);
+ if (Predicate_load(N01.getNode()) &&
+ Predicate_loadi64(N01.getNode())) {
+ SDValue N011 = N01.getNode()->getOperand(1);
+ SDValue CPTmpN011_0;
+ SDValue CPTmpN011_1;
+ SDValue CPTmpN011_2;
+ SDValue CPTmpN011_3;
+ SDValue CPTmpN011_4;
+ if (SelectAddr(N, N011, CPTmpN011_0, CPTmpN011_1, CPTmpN011_2, CPTmpN011_3, CPTmpN011_4)) {
SDValue N1 = N->getOperand(1);
ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_282(N, X86::TEST64rm, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_269(N, X86::TEST64rm, CPTmpN011_0, CPTmpN011_1, CPTmpN011_2, CPTmpN011_3, CPTmpN011_4);
return Result;
}
}
@@ -51182,152 +50804,165 @@ SDNode *Select_X86ISD_CMP(SDNode *N) {
}
}
}
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode())) {
+ if (N00.getNode()->getOpcode() == ISD::LOAD &&
+ N00.hasOneUse() &&
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
+ SDValue Chain00 = N00.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N00.getNode())) {
- // Pattern: (X86cmp:isVoid (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
- // Emits: (CMP16mi8:isVoid addr:iPTR:$src1, (imm:i16):$src2)
- // Pattern complexity = 29 cost = 1 size = 3
- if (Predicate_loadi16(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ // Pattern: (X86cmp:isVoid (and:i8 (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, GR8:i8:$src1), 0:i8)
+ // Emits: (TEST8rm:isVoid GR8:i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (Predicate_load(N00.getNode()) &&
+ Predicate_loadi8(N00.getNode())) {
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- Predicate_i16immSExt8(N1.getNode()) &&
- N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_256(N, X86::CMP16mi8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0) &&
+ N0.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_283(N, X86::TEST8rm, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
+ }
}
}
}
- // Pattern: (X86cmp:isVoid (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
- // Emits: (CMP32mi8:isVoid addr:iPTR:$src1, (imm:i32):$src2)
- // Pattern complexity = 29 cost = 1 size = 3
- if (Predicate_loadi32(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ // Pattern: (X86cmp:isVoid (and:i16 (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src1), 0:i16)
+ // Emits: (TEST16rm:isVoid GR16:i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (Predicate_loadi16(N00.getNode())) {
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- Predicate_i32immSExt8(N1.getNode()) &&
- N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_257(N, X86::CMP32mi8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0) &&
+ N0.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_283(N, X86::TEST16rm, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
+ }
}
}
}
- if (Predicate_load(N0.getNode())) {
- if (Predicate_loadi64(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant) {
-
- // Pattern: (X86cmp:isVoid (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
- // Emits: (CMP64mi8:isVoid addr:iPTR:$src1, (imm:i64):$src2)
- // Pattern complexity = 29 cost = 1 size = 3
- if (Predicate_i64immSExt8(N1.getNode()) &&
- N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_259(N, X86::CMP64mi8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
- // Pattern: (X86cmp:isVoid (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
- // Emits: (CMP64mi32:isVoid addr:iPTR:$src1, (imm:i64):$src2)
- // Pattern complexity = 29 cost = 1 size = 3
- if (Predicate_i64immSExt32(N1.getNode()) &&
- N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_259(N, X86::CMP64mi32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
+ // Pattern: (X86cmp:isVoid (and:i32 (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src1), 0:i32)
+ // Emits: (TEST32rm:isVoid GR32:i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (Predicate_loadi32(N00.getNode())) {
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0) &&
+ N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_283(N, X86::TEST32rm, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
}
}
}
+ }
- // Pattern: (X86cmp:isVoid (ld:i8 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src2)
- // Emits: (CMP8mi:isVoid addr:iPTR:$src1, (imm:i8):$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- if (Predicate_loadi8(N0.getNode())) {
+ // Pattern: (X86cmp:isVoid (and:i64 (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src1), 0:i64)
+ // Emits: (TEST64rm:isVoid GR64:i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 33 cost = 1 size = 3
+ if (Predicate_load(N00.getNode()) &&
+ Predicate_loadi64(N00.getNode())) {
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_278(N, X86::CMP8mi, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
+ if (Tmp0) {
+ int64_t CN1 = Tmp0->getSExtValue();
+ if (CN1 == INT64_C(0) &&
+ N0.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_283(N, X86::TEST64rm, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
}
}
}
+ }
+ }
+ }
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode())) {
- // Pattern: (X86cmp:isVoid (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16):$src2)
- // Emits: (CMP16mi:isVoid addr:iPTR:$src1, (imm:i16):$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- if (Predicate_loadi16(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_256(N, X86::CMP16mi, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
+ // Pattern: (X86cmp:isVoid (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
+ // Emits: (CMP16mi8:isVoid addr:iPTR:$src1, (imm:i16):$src2)
+ // Pattern complexity = 29 cost = 1 size = 3
+ if (Predicate_loadi16(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
+ Predicate_i16immSExt8(N1.getNode()) &&
+ N0.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_257(N, X86::CMP16mi8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
}
}
+ }
- // Pattern: (X86cmp:isVoid (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32):$src2)
- // Emits: (CMP32mi:isVoid addr:iPTR:$src1, (imm:i32):$src2)
- // Pattern complexity = 28 cost = 1 size = 3
- if (Predicate_loadi32(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_257(N, X86::CMP32mi, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
+ // Pattern: (X86cmp:isVoid (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
+ // Emits: (CMP32mi8:isVoid addr:iPTR:$src1, (imm:i32):$src2)
+ // Pattern complexity = 29 cost = 1 size = 3
+ if (Predicate_loadi32(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
+ Predicate_i32immSExt8(N1.getNode()) &&
+ N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_258(N, X86::CMP32mi8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
}
}
-
- // Pattern: (X86cmp:isVoid (ld:i8 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, GR8:i8:$src2)
- // Emits: (CMP8mr:isVoid addr:iPTR:$src1, GR8:i8:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (Predicate_load(N0.getNode()) &&
- Predicate_loadi8(N0.getNode())) {
+ }
+ if (Predicate_load(N0.getNode())) {
+ if (Predicate_loadi64(N0.getNode())) {
SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
@@ -51336,17 +50971,33 @@ SDNode *Select_X86ISD_CMP(SDNode *N) {
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
SDValue N1 = N->getOperand(1);
- if (N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_275(N, X86::CMP8mr, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
+
+ // Pattern: (X86cmp:isVoid (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
+ // Emits: (CMP64mi8:isVoid addr:iPTR:$src1, (imm:i64):$src2)
+ // Pattern complexity = 29 cost = 1 size = 3
+ if (Predicate_i64immSExt8(N1.getNode()) &&
+ N0.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_260(N, X86::CMP64mi8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmp:isVoid (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
+ // Emits: (CMP64mi32:isVoid addr:iPTR:$src1, (imm:i64):$src2)
+ // Pattern complexity = 29 cost = 1 size = 3
+ if (Predicate_i64immSExt32(N1.getNode()) &&
+ N0.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_260(N, X86::CMP64mi32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
}
}
}
- // Pattern: (X86cmp:isVoid (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2)
- // Emits: (CMP16mr:isVoid addr:iPTR:$src1, GR16:i16:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (Predicate_loadi16(N0.getNode())) {
+ // Pattern: (X86cmp:isVoid (ld:i8 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src2)
+ // Emits: (CMP8mi:isVoid addr:iPTR:$src1, (imm:i8):$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if (Predicate_loadi8(N0.getNode())) {
SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
@@ -51355,106 +51006,98 @@ SDNode *Select_X86ISD_CMP(SDNode *N) {
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
SDValue N1 = N->getOperand(1);
- if (N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_275(N, X86::CMP16mr, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_279(N, X86::CMP8mi, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
}
+ }
- // Pattern: (X86cmp:isVoid (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2)
- // Emits: (CMP32mr:isVoid addr:iPTR:$src1, GR32:i32:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (Predicate_loadi32(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N->getOperand(1);
- if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_275(N, X86::CMP32mr, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
+ // Pattern: (X86cmp:isVoid (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16):$src2)
+ // Emits: (CMP16mi:isVoid addr:iPTR:$src1, (imm:i16):$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if (Predicate_loadi16(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_257(N, X86::CMP16mi, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
}
}
}
- }
- {
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode())) {
- // Pattern: (X86cmp:isVoid GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>)
- // Emits: (CMP8rm:isVoid GR8:i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (Predicate_load(N1.getNode()) &&
- Predicate_loadi8(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
- N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_276(N, X86::CMP8rm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
+ // Pattern: (X86cmp:isVoid (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32):$src2)
+ // Emits: (CMP32mi:isVoid addr:iPTR:$src1, (imm:i32):$src2)
+ // Pattern complexity = 28 cost = 1 size = 3
+ if (Predicate_loadi32(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_258(N, X86::CMP32mi, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
}
+ }
+ }
- // Pattern: (X86cmp:isVoid GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>)
- // Emits: (CMP16rm:isVoid GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (Predicate_loadi16(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
- N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_276(N, X86::CMP16rm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
+ // Pattern: (X86cmp:isVoid (ld:i8 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, GR8:i8:$src2)
+ // Emits: (CMP8mr:isVoid addr:iPTR:$src1, GR8:i8:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (Predicate_load(N0.getNode()) &&
+ Predicate_loadi8(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N->getOperand(1);
+ if (N0.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_276(N, X86::CMP8mr, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
}
+ }
+ }
- // Pattern: (X86cmp:isVoid GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
- // Emits: (CMP32rm:isVoid GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (Predicate_loadi32(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
- N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_276(N, X86::CMP32rm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
+ // Pattern: (X86cmp:isVoid (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2)
+ // Emits: (CMP16mr:isVoid addr:iPTR:$src1, GR16:i16:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (Predicate_loadi16(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N->getOperand(1);
+ if (N0.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_276(N, X86::CMP16mr, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
}
}
}
- }
- // Pattern: (X86cmp:isVoid (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2)
- // Emits: (CMP64mr:isVoid addr:iPTR:$src1, GR64:i64:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_loadi64(N0.getNode())) {
+ // Pattern: (X86cmp:isVoid (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2)
+ // Emits: (CMP32mr:isVoid addr:iPTR:$src1, GR32:i32:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (Predicate_loadi32(N0.getNode())) {
SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
@@ -51463,92 +51106,180 @@ SDNode *Select_X86ISD_CMP(SDNode *N) {
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
SDValue N1 = N->getOperand(1);
- if (N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_275(N, X86::CMP64mr, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ if (N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_276(N, X86::CMP32mr, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
}
}
-
- // Pattern: (X86cmp:isVoid GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
- // Emits: (CMP64rm:isVoid GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
+ }
+ {
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_loadi64(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
- N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_276(N, X86::CMP64rm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
+ if (Predicate_unindexedload(N1.getNode())) {
+
+ // Pattern: (X86cmp:isVoid GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>)
+ // Emits: (CMP8rm:isVoid GR8:i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (Predicate_load(N1.getNode()) &&
+ Predicate_loadi8(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
+ N0.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_277(N, X86::CMP8rm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (X86cmp:isVoid GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>)
+ // Emits: (CMP16rm:isVoid GR16:i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (Predicate_loadi16(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
+ N0.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_277(N, X86::CMP16rm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+
+ // Pattern: (X86cmp:isVoid GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
+ // Emits: (CMP32rm:isVoid GR32:i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (Predicate_loadi32(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
+ N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_277(N, X86::CMP32rm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
}
}
}
}
- // Pattern: (X86cmp:isVoid FR32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>)
- // Emits: (UCOMISSrm:isVoid FR32:f32:$src1, addr:iPTR:$src2)
+ // Pattern: (X86cmp:isVoid (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2)
+ // Emits: (CMP64mr:isVoid addr:iPTR:$src1, GR64:i64:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_loadf32(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
- N0.getValueType() == MVT::f32) {
- SDNode *Result = Emit_276(N, X86::UCOMISSrm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_loadi64(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDValue N1 = N->getOperand(1);
+ if (N0.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_276(N, X86::CMP64mr, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
}
}
- // Pattern: (X86cmp:isVoid FR64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>)
- // Emits: (UCOMISDrm:isVoid FR64:f64:$src1, addr:iPTR:$src2)
+ // Pattern: (X86cmp:isVoid GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
+ // Emits: (CMP64rm:isVoid GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_loadf64(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
- N0.getValueType() == MVT::f64) {
- SDNode *Result = Emit_276(N, X86::UCOMISDrm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_loadi64(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
+ N0.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_277(N, X86::CMP64rm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86cmp:isVoid FR32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>)
+ // Emits: (UCOMISSrm:isVoid FR32:f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_loadf32(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
+ N0.getValueType() == MVT::f32) {
+ SDNode *Result = Emit_277(N, X86::UCOMISSrm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86cmp:isVoid FR64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>)
+ // Emits: (UCOMISDrm:isVoid FR64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_loadf64(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
+ N0.getValueType() == MVT::f64) {
+ SDNode *Result = Emit_277(N, X86::UCOMISDrm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
}
}
}
@@ -51570,7 +51301,7 @@ SDNode *Select_X86ISD_CMP(SDNode *N) {
// Emits: (TEST8ri:isVoid GR8:i8:$src1, (imm:i8):$src2)
// Pattern complexity = 15 cost = 1 size = 3
if (N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_269(N, X86::TEST8ri);
+ SDNode *Result = Emit_270(N, X86::TEST8ri);
return Result;
}
@@ -51578,7 +51309,7 @@ SDNode *Select_X86ISD_CMP(SDNode *N) {
// Emits: (TEST16ri:isVoid GR16:i16:$src1, (imm:i16):$src2)
// Pattern complexity = 15 cost = 1 size = 3
if (N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_270(N, X86::TEST16ri);
+ SDNode *Result = Emit_271(N, X86::TEST16ri);
return Result;
}
@@ -51586,7 +51317,7 @@ SDNode *Select_X86ISD_CMP(SDNode *N) {
// Emits: (TEST32ri:isVoid GR32:i32:$src1, (imm:i32):$src2)
// Pattern complexity = 15 cost = 1 size = 3
if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_271(N, X86::TEST32ri);
+ SDNode *Result = Emit_272(N, X86::TEST32ri);
return Result;
}
}
@@ -51608,7 +51339,7 @@ SDNode *Select_X86ISD_CMP(SDNode *N) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_279(N, X86::TEST64ri32);
+ SDNode *Result = Emit_280(N, X86::TEST64ri32);
return Result;
}
}
@@ -51627,7 +51358,7 @@ SDNode *Select_X86ISD_CMP(SDNode *N) {
// Emits: (TEST8rr:isVoid GR8:i8:$src1, GR8:i8:$src2)
// Pattern complexity = 12 cost = 1 size = 3
if (N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_267(N, X86::TEST8rr);
+ SDNode *Result = Emit_268(N, X86::TEST8rr);
return Result;
}
@@ -51635,7 +51366,7 @@ SDNode *Select_X86ISD_CMP(SDNode *N) {
// Emits: (TEST16rr:isVoid GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 12 cost = 1 size = 3
if (N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_267(N, X86::TEST16rr);
+ SDNode *Result = Emit_268(N, X86::TEST16rr);
return Result;
}
@@ -51643,7 +51374,7 @@ SDNode *Select_X86ISD_CMP(SDNode *N) {
// Emits: (TEST32rr:isVoid GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 12 cost = 1 size = 3
if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_267(N, X86::TEST32rr);
+ SDNode *Result = Emit_268(N, X86::TEST32rr);
return Result;
}
}
@@ -51661,7 +51392,7 @@ SDNode *Select_X86ISD_CMP(SDNode *N) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_267(N, X86::TEST64rr);
+ SDNode *Result = Emit_268(N, X86::TEST64rr);
return Result;
}
}
@@ -51677,7 +51408,7 @@ SDNode *Select_X86ISD_CMP(SDNode *N) {
// Emits: (TEST64rr:isVoid GR64:i64:$src1, GR64:i64:$src1)
// Pattern complexity = 8 cost = 1 size = 3
if (N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_281(N, X86::TEST64rr);
+ SDNode *Result = Emit_282(N, X86::TEST64rr);
return Result;
}
@@ -51685,7 +51416,7 @@ SDNode *Select_X86ISD_CMP(SDNode *N) {
// Emits: (TEST8rr:isVoid GR8:i8:$src1, GR8:i8:$src1)
// Pattern complexity = 8 cost = 1 size = 3
if (N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_281(N, X86::TEST8rr);
+ SDNode *Result = Emit_282(N, X86::TEST8rr);
return Result;
}
@@ -51693,7 +51424,7 @@ SDNode *Select_X86ISD_CMP(SDNode *N) {
// Emits: (TEST16rr:isVoid GR16:i16:$src1, GR16:i16:$src1)
// Pattern complexity = 8 cost = 1 size = 3
if (N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_281(N, X86::TEST16rr);
+ SDNode *Result = Emit_282(N, X86::TEST16rr);
return Result;
}
@@ -51701,7 +51432,7 @@ SDNode *Select_X86ISD_CMP(SDNode *N) {
// Emits: (TEST32rr:isVoid GR32:i32:$src1, GR32:i32:$src1)
// Pattern complexity = 8 cost = 1 size = 3
if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_281(N, X86::TEST32rr);
+ SDNode *Result = Emit_282(N, X86::TEST32rr);
return Result;
}
}
@@ -51714,7 +51445,7 @@ SDNode *Select_X86ISD_CMP(SDNode *N) {
// Pattern complexity = 7 cost = 1 size = 3
if (Predicate_i16immSExt8(N1.getNode()) &&
N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_254(N, X86::CMP16ri8);
+ SDNode *Result = Emit_255(N, X86::CMP16ri8);
return Result;
}
@@ -51723,7 +51454,7 @@ SDNode *Select_X86ISD_CMP(SDNode *N) {
// Pattern complexity = 7 cost = 1 size = 3
if (Predicate_i32immSExt8(N1.getNode()) &&
N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_255(N, X86::CMP32ri8);
+ SDNode *Result = Emit_256(N, X86::CMP32ri8);
return Result;
}
@@ -51732,7 +51463,7 @@ SDNode *Select_X86ISD_CMP(SDNode *N) {
// Pattern complexity = 7 cost = 1 size = 3
if (Predicate_i64immSExt8(N1.getNode()) &&
N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_258(N, X86::CMP64ri8);
+ SDNode *Result = Emit_259(N, X86::CMP64ri8);
return Result;
}
@@ -51741,7 +51472,7 @@ SDNode *Select_X86ISD_CMP(SDNode *N) {
// Pattern complexity = 7 cost = 1 size = 3
if (Predicate_i64immSExt32(N1.getNode()) &&
N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_258(N, X86::CMP64ri32);
+ SDNode *Result = Emit_259(N, X86::CMP64ri32);
return Result;
}
@@ -51749,7 +51480,7 @@ SDNode *Select_X86ISD_CMP(SDNode *N) {
// Emits: (CMP8ri:isVoid GR8:i8:$src1, (imm:i8):$src2)
// Pattern complexity = 6 cost = 1 size = 3
if (N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_277(N, X86::CMP8ri);
+ SDNode *Result = Emit_278(N, X86::CMP8ri);
return Result;
}
@@ -51757,7 +51488,7 @@ SDNode *Select_X86ISD_CMP(SDNode *N) {
// Emits: (CMP16ri:isVoid GR16:i16:$src1, (imm:i16):$src2)
// Pattern complexity = 6 cost = 1 size = 3
if (N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_254(N, X86::CMP16ri);
+ SDNode *Result = Emit_255(N, X86::CMP16ri);
return Result;
}
@@ -51765,7 +51496,7 @@ SDNode *Select_X86ISD_CMP(SDNode *N) {
// Emits: (CMP32ri:isVoid GR32:i32:$src1, (imm:i32):$src2)
// Pattern complexity = 6 cost = 1 size = 3
if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_255(N, X86::CMP32ri);
+ SDNode *Result = Emit_256(N, X86::CMP32ri);
return Result;
}
}
@@ -51778,7 +51509,7 @@ SDNode *Select_X86ISD_CMP(SDNode *N) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::f32) {
- SDNode *Result = Emit_253(N, X86::UCOM_FpIr32);
+ SDNode *Result = Emit_254(N, X86::UCOM_FpIr32);
return Result;
}
}
@@ -51790,7 +51521,7 @@ SDNode *Select_X86ISD_CMP(SDNode *N) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::f64) {
- SDNode *Result = Emit_253(N, X86::UCOM_FpIr64);
+ SDNode *Result = Emit_254(N, X86::UCOM_FpIr64);
return Result;
}
}
@@ -51802,7 +51533,7 @@ SDNode *Select_X86ISD_CMP(SDNode *N) {
// Emits: (UCOM_FpIr80:isVoid RFP80:f80:$lhs, RFP80:f80:$rhs)
// Pattern complexity = 3 cost = 1 size = 0
if (N0.getValueType() == MVT::f80) {
- SDNode *Result = Emit_253(N, X86::UCOM_FpIr80);
+ SDNode *Result = Emit_254(N, X86::UCOM_FpIr80);
return Result;
}
@@ -51810,7 +51541,7 @@ SDNode *Select_X86ISD_CMP(SDNode *N) {
// Emits: (CMP8rr:isVoid GR8:i8:$src1, GR8:i8:$src2)
// Pattern complexity = 3 cost = 1 size = 3
if (N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_253(N, X86::CMP8rr);
+ SDNode *Result = Emit_254(N, X86::CMP8rr);
return Result;
}
@@ -51818,7 +51549,7 @@ SDNode *Select_X86ISD_CMP(SDNode *N) {
// Emits: (CMP16rr:isVoid GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 3 cost = 1 size = 3
if (N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_253(N, X86::CMP16rr);
+ SDNode *Result = Emit_254(N, X86::CMP16rr);
return Result;
}
@@ -51826,7 +51557,7 @@ SDNode *Select_X86ISD_CMP(SDNode *N) {
// Emits: (CMP32rr:isVoid GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 3 cost = 1 size = 3
if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_253(N, X86::CMP32rr);
+ SDNode *Result = Emit_254(N, X86::CMP32rr);
return Result;
}
@@ -51834,7 +51565,7 @@ SDNode *Select_X86ISD_CMP(SDNode *N) {
// Emits: (CMP64rr:isVoid GR64:i64:$src1, GR64:i64:$src2)
// Pattern complexity = 3 cost = 1 size = 3
if (N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_253(N, X86::CMP64rr);
+ SDNode *Result = Emit_254(N, X86::CMP64rr);
return Result;
}
}
@@ -51846,7 +51577,7 @@ SDNode *Select_X86ISD_CMP(SDNode *N) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::f32) {
- SDNode *Result = Emit_253(N, X86::UCOMISSrr);
+ SDNode *Result = Emit_254(N, X86::UCOMISSrr);
return Result;
}
}
@@ -51858,7 +51589,7 @@ SDNode *Select_X86ISD_CMP(SDNode *N) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::f64) {
- SDNode *Result = Emit_253(N, X86::UCOMISDrr);
+ SDNode *Result = Emit_254(N, X86::UCOMISDrr);
return Result;
}
}
@@ -51867,14 +51598,14 @@ SDNode *Select_X86ISD_CMP(SDNode *N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_283(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_284(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i8);
return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, N1, Tmp2);
}
-DISABLE_INLINE SDNode *Emit_284(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
+DISABLE_INLINE SDNode *Emit_285(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
SDValue Chain1 = N1.getNode()->getOperand(0);
@@ -51890,33 +51621,31 @@ DISABLE_INLINE SDNode *Emit_284(SDNode *N, unsigned Opc0, MVT::SimpleValueType V
return ResNode;
}
SDNode *Select_X86ISD_CMPPD_v2i64(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (X86cmppd:v2i64 VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (imm:i8):$cc)
// Emits: (CMPPDrmi:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2, (imm:i8):$cc)
// Pattern complexity = 28 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_284(N, X86::CMPPDrmi, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::v2f64) {
+ SDNode *Result = Emit_285(N, X86::CMPPDrmi, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
}
}
}
@@ -51925,12 +51654,10 @@ SDNode *Select_X86ISD_CMPPD_v2i64(SDNode *N) {
// Pattern: (X86cmppd:v2i64 VR128:v2f64:$src1, VR128:v2f64:$src2, (imm:i8):$cc)
// Emits: (CMPPDrri:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$cc)
// Pattern complexity = 6 cost = 1 size = 3
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
if (N2.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_283(N, X86::CMPPDrri, MVT::v2i64);
+ SDNode *Result = Emit_284(N, X86::CMPPDrri, MVT::v2i64);
return Result;
}
@@ -51939,33 +51666,31 @@ SDNode *Select_X86ISD_CMPPD_v2i64(SDNode *N) {
}
SDNode *Select_X86ISD_CMPPS_v4i32(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (X86cmpps:v4i32 VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (imm:i8):$cc)
// Emits: (CMPPSrmi:v4i32 VR128:v16i8:$src1, addr:iPTR:$src2, (imm:i8):$cc)
// Pattern complexity = 28 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDValue N2 = N->getOperand(2);
- if (N2.getNode()->getOpcode() == ISD::Constant &&
- N0.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_284(N, X86::CMPPSrmi, MVT::v4i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant &&
+ N0.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_285(N, X86::CMPPSrmi, MVT::v4i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
}
}
}
@@ -51974,12 +51699,10 @@ SDNode *Select_X86ISD_CMPPS_v4i32(SDNode *N) {
// Pattern: (X86cmpps:v4i32 VR128:v4f32:$src1, VR128:v4f32:$src2, (imm:i8):$cc)
// Emits: (CMPPSrri:v4i32 VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$cc)
// Pattern complexity = 6 cost = 1 size = 3
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
if (N2.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_283(N, X86::CMPPSrri, MVT::v4i32);
+ SDNode *Result = Emit_284(N, X86::CMPPSrri, MVT::v4i32);
return Result;
}
@@ -51988,58 +51711,56 @@ SDNode *Select_X86ISD_CMPPS_v4i32(SDNode *N) {
}
SDNode *Select_X86ISD_COMI(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
- // Pattern: (X86comi:isVoid VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (Int_COMISSrm:isVoid VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
- N0.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_276(N, X86::Int_COMISSrm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
+ // Pattern: (X86comi:isVoid VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (Int_COMISSrm:isVoid VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
+ N0.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_277(N, X86::Int_COMISSrm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
}
}
}
+ }
- // Pattern: (X86comi:isVoid VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (Int_COMISDrm:isVoid VR128:v2f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
- N0.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_276(N, X86::Int_COMISDrm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
+ // Pattern: (X86comi:isVoid VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (Int_COMISDrm:isVoid VR128:v2f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
+ N0.getValueType() == MVT::v2f64) {
+ SDNode *Result = Emit_277(N, X86::Int_COMISDrm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
}
}
}
@@ -52052,7 +51773,7 @@ SDNode *Select_X86ISD_COMI(SDNode *N) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_253(N, X86::Int_COMISSrr);
+ SDNode *Result = Emit_254(N, X86::Int_COMISSrr);
return Result;
}
}
@@ -52064,7 +51785,7 @@ SDNode *Select_X86ISD_COMI(SDNode *N) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_253(N, X86::Int_COMISDrr);
+ SDNode *Result = Emit_254(N, X86::Int_COMISDrr);
return Result;
}
}
@@ -52076,7 +51797,7 @@ SDNode *Select_X86ISD_COMI(SDNode *N) {
SDNode *Select_X86ISD_DEC_i8(SDNode *N) {
SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_251(N, X86::DEC8r, MVT::i8);
+ SDNode *Result = Emit_252(N, X86::DEC8r, MVT::i8);
return Result;
}
@@ -52092,7 +51813,7 @@ SDNode *Select_X86ISD_DEC_i16(SDNode *N) {
if ((!Subtarget->is64Bit())) {
SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_251(N, X86::DEC16r, MVT::i16);
+ SDNode *Result = Emit_252(N, X86::DEC16r, MVT::i16);
return Result;
}
}
@@ -52103,7 +51824,7 @@ SDNode *Select_X86ISD_DEC_i16(SDNode *N) {
if ((Subtarget->is64Bit())) {
SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_251(N, X86::DEC64_16r, MVT::i16);
+ SDNode *Result = Emit_252(N, X86::DEC64_16r, MVT::i16);
return Result;
}
}
@@ -52120,7 +51841,7 @@ SDNode *Select_X86ISD_DEC_i32(SDNode *N) {
if ((!Subtarget->is64Bit())) {
SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_251(N, X86::DEC32r, MVT::i32);
+ SDNode *Result = Emit_252(N, X86::DEC32r, MVT::i32);
return Result;
}
}
@@ -52131,7 +51852,7 @@ SDNode *Select_X86ISD_DEC_i32(SDNode *N) {
if ((Subtarget->is64Bit())) {
SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_251(N, X86::DEC64_32r, MVT::i32);
+ SDNode *Result = Emit_252(N, X86::DEC64_32r, MVT::i32);
return Result;
}
}
@@ -52143,7 +51864,7 @@ SDNode *Select_X86ISD_DEC_i32(SDNode *N) {
SDNode *Select_X86ISD_DEC_i64(SDNode *N) {
SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_251(N, X86::DEC64r, MVT::i64);
+ SDNode *Result = Emit_252(N, X86::DEC64r, MVT::i64);
return Result;
}
@@ -52176,64 +51897,63 @@ SDNode *Select_X86ISD_EH_RETURN(SDNode *N) {
}
SDNode *Select_X86ISD_FAND_f32(SDNode *N) {
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (X86fand:f32 FR32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (FsANDPSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
{
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::FsANDPSrm, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
+ SDValue N0 = N->getOperand(0);
+
+ // Pattern: (X86fand:f32 FR32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (FsANDPSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::FsANDPSrm, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
}
}
}
- }
- // Pattern: (X86fand:f32 (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, FR32:f32:$src1)
- // Emits: (FsANDPSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_19(N, X86::FsANDPSrm, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
+ // Pattern: (X86fand:f32 (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, FR32:f32:$src1)
+ // Emits: (FsANDPSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_19(N, X86::FsANDPSrm, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
}
}
}
- }
- // Pattern: (X86fand:f32 FR32:f32:$src1, FR32:f32:$src2)
- // Emits: (FsANDPSrr:f32 FR32:f32:$src1, FR32:f32:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
+ // Pattern: (X86fand:f32 FR32:f32:$src1, FR32:f32:$src2)
+ // Emits: (FsANDPSrr:f32 FR32:f32:$src1, FR32:f32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
SDNode *Result = Emit_15(N, X86::FsANDPSrr, MVT::f32);
return Result;
}
@@ -52243,64 +51963,63 @@ SDNode *Select_X86ISD_FAND_f32(SDNode *N) {
}
SDNode *Select_X86ISD_FAND_f64(SDNode *N) {
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (X86fand:f64 FR64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (FsANDPDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
{
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::FsANDPDrm, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
+ SDValue N0 = N->getOperand(0);
+
+ // Pattern: (X86fand:f64 FR64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (FsANDPDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::FsANDPDrm, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
}
}
}
- }
- // Pattern: (X86fand:f64 (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, FR64:f64:$src1)
- // Emits: (FsANDPDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_19(N, X86::FsANDPDrm, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
+ // Pattern: (X86fand:f64 (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, FR64:f64:$src1)
+ // Emits: (FsANDPDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_19(N, X86::FsANDPDrm, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
}
}
}
- }
- // Pattern: (X86fand:f64 FR64:f64:$src1, FR64:f64:$src2)
- // Emits: (FsANDPDrr:f64 FR64:f64:$src1, FR64:f64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
+ // Pattern: (X86fand:f64 FR64:f64:$src1, FR64:f64:$src2)
+ // Emits: (FsANDPDrr:f64 FR64:f64:$src1, FR64:f64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
SDNode *Result = Emit_15(N, X86::FsANDPDrr, MVT::f64);
return Result;
}
@@ -52309,7 +52028,7 @@ SDNode *Select_X86ISD_FAND_f64(SDNode *N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_285(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
+DISABLE_INLINE SDNode *Emit_286(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
SDValue Chain = N->getOperand(0);
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
@@ -52332,7 +52051,7 @@ SDNode *Select_X86ISD_FILD_f32(SDNode *N) {
// Emits: (ILD_Fp16m32:f32 addr:iPTR:$src)
// Pattern complexity = 21 cost = 1 size = 0
if (cast<VTSDNode>(N2.getNode())->getVT() == MVT::i16) {
- SDNode *Result = Emit_285(N, X86::ILD_Fp16m32, MVT::f32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_286(N, X86::ILD_Fp16m32, MVT::f32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
@@ -52340,7 +52059,7 @@ SDNode *Select_X86ISD_FILD_f32(SDNode *N) {
// Emits: (ILD_Fp32m32:f32 addr:iPTR:$src)
// Pattern complexity = 21 cost = 1 size = 0
if (cast<VTSDNode>(N2.getNode())->getVT() == MVT::i32) {
- SDNode *Result = Emit_285(N, X86::ILD_Fp32m32, MVT::f32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_286(N, X86::ILD_Fp32m32, MVT::f32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
@@ -52348,7 +52067,7 @@ SDNode *Select_X86ISD_FILD_f32(SDNode *N) {
// Emits: (ILD_Fp64m32:f32 addr:iPTR:$src)
// Pattern complexity = 21 cost = 1 size = 0
if (cast<VTSDNode>(N2.getNode())->getVT() == MVT::i64) {
- SDNode *Result = Emit_285(N, X86::ILD_Fp64m32, MVT::f32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_286(N, X86::ILD_Fp64m32, MVT::f32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -52374,7 +52093,7 @@ SDNode *Select_X86ISD_FILD_f64(SDNode *N) {
// Emits: (ILD_Fp16m64:f64 addr:iPTR:$src)
// Pattern complexity = 21 cost = 1 size = 0
if (cast<VTSDNode>(N2.getNode())->getVT() == MVT::i16) {
- SDNode *Result = Emit_285(N, X86::ILD_Fp16m64, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_286(N, X86::ILD_Fp16m64, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
@@ -52382,7 +52101,7 @@ SDNode *Select_X86ISD_FILD_f64(SDNode *N) {
// Emits: (ILD_Fp32m64:f64 addr:iPTR:$src)
// Pattern complexity = 21 cost = 1 size = 0
if (cast<VTSDNode>(N2.getNode())->getVT() == MVT::i32) {
- SDNode *Result = Emit_285(N, X86::ILD_Fp32m64, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_286(N, X86::ILD_Fp32m64, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
@@ -52390,7 +52109,7 @@ SDNode *Select_X86ISD_FILD_f64(SDNode *N) {
// Emits: (ILD_Fp64m64:f64 addr:iPTR:$src)
// Pattern complexity = 21 cost = 1 size = 0
if (cast<VTSDNode>(N2.getNode())->getVT() == MVT::i64) {
- SDNode *Result = Emit_285(N, X86::ILD_Fp64m64, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_286(N, X86::ILD_Fp64m64, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -52415,7 +52134,7 @@ SDNode *Select_X86ISD_FILD_f80(SDNode *N) {
// Emits: (ILD_Fp16m80:f80 addr:iPTR:$src)
// Pattern complexity = 21 cost = 1 size = 0
if (cast<VTSDNode>(N2.getNode())->getVT() == MVT::i16) {
- SDNode *Result = Emit_285(N, X86::ILD_Fp16m80, MVT::f80, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_286(N, X86::ILD_Fp16m80, MVT::f80, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
@@ -52423,7 +52142,7 @@ SDNode *Select_X86ISD_FILD_f80(SDNode *N) {
// Emits: (ILD_Fp32m80:f80 addr:iPTR:$src)
// Pattern complexity = 21 cost = 1 size = 0
if (cast<VTSDNode>(N2.getNode())->getVT() == MVT::i32) {
- SDNode *Result = Emit_285(N, X86::ILD_Fp32m80, MVT::f80, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_286(N, X86::ILD_Fp32m80, MVT::f80, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
@@ -52431,7 +52150,7 @@ SDNode *Select_X86ISD_FILD_f80(SDNode *N) {
// Emits: (ILD_Fp64m80:f80 addr:iPTR:$src)
// Pattern complexity = 21 cost = 1 size = 0
if (cast<VTSDNode>(N2.getNode())->getVT() == MVT::i64) {
- SDNode *Result = Emit_285(N, X86::ILD_Fp64m80, MVT::f80, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_286(N, X86::ILD_Fp64m80, MVT::f80, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -52440,7 +52159,7 @@ SDNode *Select_X86ISD_FILD_f80(SDNode *N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_286(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
+DISABLE_INLINE SDNode *Emit_287(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
SDValue Chain = N->getOperand(0);
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
@@ -52470,7 +52189,7 @@ SDNode *Select_X86ISD_FILD_FLAG_f64(SDNode *N) {
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
SDValue N2 = N->getOperand(2);
if (cast<VTSDNode>(N2.getNode())->getVT() == MVT::i64) {
- SDNode *Result = Emit_286(N, X86::ILD_Fp64m64, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_287(N, X86::ILD_Fp64m64, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -52490,7 +52209,7 @@ SDNode *Select_X86ISD_FLD_f32(SDNode *N) {
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
SDValue N2 = N->getOperand(2);
if (cast<VTSDNode>(N2.getNode())->getVT() == MVT::f32) {
- SDNode *Result = Emit_285(N, X86::LD_Fp32m, MVT::f32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_286(N, X86::LD_Fp32m, MVT::f32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -52510,7 +52229,7 @@ SDNode *Select_X86ISD_FLD_f64(SDNode *N) {
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
SDValue N2 = N->getOperand(2);
if (cast<VTSDNode>(N2.getNode())->getVT() == MVT::f64) {
- SDNode *Result = Emit_285(N, X86::LD_Fp64m, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_286(N, X86::LD_Fp64m, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -52530,7 +52249,7 @@ SDNode *Select_X86ISD_FLD_f80(SDNode *N) {
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
SDValue N2 = N->getOperand(2);
if (cast<VTSDNode>(N2.getNode())->getVT() == MVT::f80) {
- SDNode *Result = Emit_285(N, X86::LD_Fp80m, MVT::f80, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_286(N, X86::LD_Fp80m, MVT::f80, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -52540,38 +52259,37 @@ SDNode *Select_X86ISD_FLD_f80(SDNode *N) {
}
SDNode *Select_X86ISD_FMAX_f32(SDNode *N) {
+ if ((Subtarget->hasSSE1())) {
- // Pattern: (X86fmax:f32 FR32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (MAXSSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::MAXSSrm, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
+ // Pattern: (X86fmax:f32 FR32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (MAXSSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::MAXSSrm, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
}
}
}
- }
- // Pattern: (X86fmax:f32 FR32:f32:$src1, FR32:f32:$src2)
- // Emits: (MAXSSrr:f32 FR32:f32:$src1, FR32:f32:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
+ // Pattern: (X86fmax:f32 FR32:f32:$src1, FR32:f32:$src2)
+ // Emits: (MAXSSrr:f32 FR32:f32:$src1, FR32:f32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
SDNode *Result = Emit_15(N, X86::MAXSSrr, MVT::f32);
return Result;
}
@@ -52581,38 +52299,37 @@ SDNode *Select_X86ISD_FMAX_f32(SDNode *N) {
}
SDNode *Select_X86ISD_FMAX_f64(SDNode *N) {
+ if ((Subtarget->hasSSE2())) {
- // Pattern: (X86fmax:f64 FR64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (MAXSDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::MAXSDrm, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
+ // Pattern: (X86fmax:f64 FR64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (MAXSDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::MAXSDrm, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
}
}
}
- }
- // Pattern: (X86fmax:f64 FR64:f64:$src1, FR64:f64:$src2)
- // Emits: (MAXSDrr:f64 FR64:f64:$src1, FR64:f64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
+ // Pattern: (X86fmax:f64 FR64:f64:$src1, FR64:f64:$src2)
+ // Emits: (MAXSDrr:f64 FR64:f64:$src1, FR64:f64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
SDNode *Result = Emit_15(N, X86::MAXSDrr, MVT::f64);
return Result;
}
@@ -52622,39 +52339,38 @@ SDNode *Select_X86ISD_FMAX_f64(SDNode *N) {
}
SDNode *Select_X86ISD_FMAX_v4f32(SDNode *N) {
+ if ((Subtarget->hasSSE1())) {
- // Pattern: (X86fmax:v4f32 VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (MAXPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::MAXPSrm, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
+ // Pattern: (X86fmax:v4f32 VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (MAXPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::MAXPSrm, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
}
}
}
- }
- // Pattern: (X86fmax:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
- // Emits: (MAXPSrr:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
+ // Pattern: (X86fmax:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Emits: (MAXPSrr:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
SDNode *Result = Emit_15(N, X86::MAXPSrr, MVT::v4f32);
return Result;
}
@@ -52664,39 +52380,38 @@ SDNode *Select_X86ISD_FMAX_v4f32(SDNode *N) {
}
SDNode *Select_X86ISD_FMAX_v2f64(SDNode *N) {
+ if ((Subtarget->hasSSE2())) {
- // Pattern: (X86fmax:v2f64 VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (MAXPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::MAXPDrm, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
+ // Pattern: (X86fmax:v2f64 VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (MAXPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::MAXPDrm, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
}
}
}
- }
- // Pattern: (X86fmax:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
- // Emits: (MAXPDrr:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
+ // Pattern: (X86fmax:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Emits: (MAXPDrr:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
SDNode *Result = Emit_15(N, X86::MAXPDrr, MVT::v2f64);
return Result;
}
@@ -52706,38 +52421,37 @@ SDNode *Select_X86ISD_FMAX_v2f64(SDNode *N) {
}
SDNode *Select_X86ISD_FMIN_f32(SDNode *N) {
+ if ((Subtarget->hasSSE1())) {
- // Pattern: (X86fmin:f32 FR32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (MINSSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::MINSSrm, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
+ // Pattern: (X86fmin:f32 FR32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (MINSSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::MINSSrm, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
}
}
}
- }
- // Pattern: (X86fmin:f32 FR32:f32:$src1, FR32:f32:$src2)
- // Emits: (MINSSrr:f32 FR32:f32:$src1, FR32:f32:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
+ // Pattern: (X86fmin:f32 FR32:f32:$src1, FR32:f32:$src2)
+ // Emits: (MINSSrr:f32 FR32:f32:$src1, FR32:f32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
SDNode *Result = Emit_15(N, X86::MINSSrr, MVT::f32);
return Result;
}
@@ -52747,38 +52461,37 @@ SDNode *Select_X86ISD_FMIN_f32(SDNode *N) {
}
SDNode *Select_X86ISD_FMIN_f64(SDNode *N) {
+ if ((Subtarget->hasSSE2())) {
- // Pattern: (X86fmin:f64 FR64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (MINSDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::MINSDrm, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
+ // Pattern: (X86fmin:f64 FR64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (MINSDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::MINSDrm, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
}
}
}
- }
- // Pattern: (X86fmin:f64 FR64:f64:$src1, FR64:f64:$src2)
- // Emits: (MINSDrr:f64 FR64:f64:$src1, FR64:f64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
+ // Pattern: (X86fmin:f64 FR64:f64:$src1, FR64:f64:$src2)
+ // Emits: (MINSDrr:f64 FR64:f64:$src1, FR64:f64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
SDNode *Result = Emit_15(N, X86::MINSDrr, MVT::f64);
return Result;
}
@@ -52788,39 +52501,38 @@ SDNode *Select_X86ISD_FMIN_f64(SDNode *N) {
}
SDNode *Select_X86ISD_FMIN_v4f32(SDNode *N) {
+ if ((Subtarget->hasSSE1())) {
- // Pattern: (X86fmin:v4f32 VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (MINPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::MINPSrm, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
+ // Pattern: (X86fmin:v4f32 VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (MINPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::MINPSrm, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
}
}
}
- }
- // Pattern: (X86fmin:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
- // Emits: (MINPSrr:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
+ // Pattern: (X86fmin:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Emits: (MINPSrr:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
SDNode *Result = Emit_15(N, X86::MINPSrr, MVT::v4f32);
return Result;
}
@@ -52830,39 +52542,38 @@ SDNode *Select_X86ISD_FMIN_v4f32(SDNode *N) {
}
SDNode *Select_X86ISD_FMIN_v2f64(SDNode *N) {
+ if ((Subtarget->hasSSE2())) {
- // Pattern: (X86fmin:v2f64 VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (MINPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::MINPDrm, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
+ // Pattern: (X86fmin:v2f64 VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (MINPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::MINPDrm, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
}
}
}
- }
- // Pattern: (X86fmin:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
- // Emits: (MINPDrr:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
+ // Pattern: (X86fmin:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Emits: (MINPDrr:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
SDNode *Result = Emit_15(N, X86::MINPDrr, MVT::v2f64);
return Result;
}
@@ -52871,7 +52582,7 @@ SDNode *Select_X86ISD_FMIN_v2f64(SDNode *N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_287(SDNode *N, unsigned Opc0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
+DISABLE_INLINE SDNode *Emit_288(SDNode *N, unsigned Opc0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
SDValue Chain = N->getOperand(0);
SDValue N1 = N->getOperand(1);
SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain };
@@ -52886,7 +52597,7 @@ SDNode *Select_X86ISD_FNSTCW16m(SDNode *N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_287(N, X86::FNSTCW16m, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_288(N, X86::FNSTCW16m, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
@@ -52895,64 +52606,63 @@ SDNode *Select_X86ISD_FNSTCW16m(SDNode *N) {
}
SDNode *Select_X86ISD_FOR_f32(SDNode *N) {
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (X86for:f32 FR32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (FsORPSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
{
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::FsORPSrm, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
+ SDValue N0 = N->getOperand(0);
+
+ // Pattern: (X86for:f32 FR32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (FsORPSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::FsORPSrm, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
}
}
}
- }
- // Pattern: (X86for:f32 (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, FR32:f32:$src1)
- // Emits: (FsORPSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_19(N, X86::FsORPSrm, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
+ // Pattern: (X86for:f32 (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, FR32:f32:$src1)
+ // Emits: (FsORPSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_19(N, X86::FsORPSrm, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
}
}
}
- }
- // Pattern: (X86for:f32 FR32:f32:$src1, FR32:f32:$src2)
- // Emits: (FsORPSrr:f32 FR32:f32:$src1, FR32:f32:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
+ // Pattern: (X86for:f32 FR32:f32:$src1, FR32:f32:$src2)
+ // Emits: (FsORPSrr:f32 FR32:f32:$src1, FR32:f32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
SDNode *Result = Emit_15(N, X86::FsORPSrr, MVT::f32);
return Result;
}
@@ -52962,64 +52672,63 @@ SDNode *Select_X86ISD_FOR_f32(SDNode *N) {
}
SDNode *Select_X86ISD_FOR_f64(SDNode *N) {
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (X86for:f64 FR64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (FsORPDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
{
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::FsORPDrm, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
+ SDValue N0 = N->getOperand(0);
+
+ // Pattern: (X86for:f64 FR64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (FsORPDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::FsORPDrm, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
}
}
}
- }
- // Pattern: (X86for:f64 (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, FR64:f64:$src1)
- // Emits: (FsORPDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_19(N, X86::FsORPDrm, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
+ // Pattern: (X86for:f64 (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, FR64:f64:$src1)
+ // Emits: (FsORPDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_19(N, X86::FsORPDrm, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
}
}
}
- }
- // Pattern: (X86for:f64 FR64:f64:$src1, FR64:f64:$src2)
- // Emits: (FsORPDrr:f64 FR64:f64:$src1, FR64:f64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
+ // Pattern: (X86for:f64 FR64:f64:$src1, FR64:f64:$src2)
+ // Emits: (FsORPDrr:f64 FR64:f64:$src1, FR64:f64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
SDNode *Result = Emit_15(N, X86::FsORPDrr, MVT::f64);
return Result;
}
@@ -53028,7 +52737,7 @@ SDNode *Select_X86ISD_FOR_f64(SDNode *N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_288(SDNode *N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+DISABLE_INLINE SDNode *Emit_289(SDNode *N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
SDValue Chain = N->getOperand(0);
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
@@ -53051,7 +52760,7 @@ SDNode *Select_X86ISD_FP_TO_INT16_IN_MEM(SDNode *N) {
// Emits: (ISTT_Fp16m32:isVoid addr:iPTR:$op, RFP32:f32:$src)
// Pattern complexity = 21 cost = 1 size = 0
if (N1.getValueType() == MVT::f32) {
- SDNode *Result = Emit_288(N, X86::ISTT_Fp16m32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_289(N, X86::ISTT_Fp16m32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -53059,7 +52768,7 @@ SDNode *Select_X86ISD_FP_TO_INT16_IN_MEM(SDNode *N) {
// Emits: (ISTT_Fp16m64:isVoid addr:iPTR:$op, RFP64:f64:$src)
// Pattern complexity = 21 cost = 1 size = 0
if (N1.getValueType() == MVT::f64) {
- SDNode *Result = Emit_288(N, X86::ISTT_Fp16m64, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_289(N, X86::ISTT_Fp16m64, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -53067,7 +52776,7 @@ SDNode *Select_X86ISD_FP_TO_INT16_IN_MEM(SDNode *N) {
// Emits: (ISTT_Fp16m80:isVoid addr:iPTR:$op, RFP80:f80:$src)
// Pattern complexity = 21 cost = 1 size = 0
if (N1.getValueType() == MVT::f80) {
- SDNode *Result = Emit_288(N, X86::ISTT_Fp16m80, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_289(N, X86::ISTT_Fp16m80, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -53086,7 +52795,7 @@ SDNode *Select_X86ISD_FP_TO_INT16_IN_MEM(SDNode *N) {
// Emits: (FP32_TO_INT16_IN_MEM:isVoid addr:iPTR:$dst, RFP32:f32:$src)
// Pattern complexity = 21 cost = 11 size = 3
if (N1.getValueType() == MVT::f32) {
- SDNode *Result = Emit_288(N, X86::FP32_TO_INT16_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_289(N, X86::FP32_TO_INT16_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -53094,7 +52803,7 @@ SDNode *Select_X86ISD_FP_TO_INT16_IN_MEM(SDNode *N) {
// Emits: (FP64_TO_INT16_IN_MEM:isVoid addr:iPTR:$dst, RFP64:f64:$src)
// Pattern complexity = 21 cost = 11 size = 3
if (N1.getValueType() == MVT::f64) {
- SDNode *Result = Emit_288(N, X86::FP64_TO_INT16_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_289(N, X86::FP64_TO_INT16_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -53102,7 +52811,7 @@ SDNode *Select_X86ISD_FP_TO_INT16_IN_MEM(SDNode *N) {
// Emits: (FP80_TO_INT16_IN_MEM:isVoid addr:iPTR:$dst, RFP80:f80:$src)
// Pattern complexity = 21 cost = 11 size = 3
if (N1.getValueType() == MVT::f80) {
- SDNode *Result = Emit_288(N, X86::FP80_TO_INT16_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_289(N, X86::FP80_TO_INT16_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -53127,7 +52836,7 @@ SDNode *Select_X86ISD_FP_TO_INT32_IN_MEM(SDNode *N) {
// Emits: (ISTT_Fp32m32:isVoid addr:iPTR:$op, RFP32:f32:$src)
// Pattern complexity = 21 cost = 1 size = 0
if (N1.getValueType() == MVT::f32) {
- SDNode *Result = Emit_288(N, X86::ISTT_Fp32m32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_289(N, X86::ISTT_Fp32m32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -53135,7 +52844,7 @@ SDNode *Select_X86ISD_FP_TO_INT32_IN_MEM(SDNode *N) {
// Emits: (ISTT_Fp32m64:isVoid addr:iPTR:$op, RFP64:f64:$src)
// Pattern complexity = 21 cost = 1 size = 0
if (N1.getValueType() == MVT::f64) {
- SDNode *Result = Emit_288(N, X86::ISTT_Fp32m64, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_289(N, X86::ISTT_Fp32m64, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -53143,7 +52852,7 @@ SDNode *Select_X86ISD_FP_TO_INT32_IN_MEM(SDNode *N) {
// Emits: (ISTT_Fp32m80:isVoid addr:iPTR:$op, RFP80:f80:$src)
// Pattern complexity = 21 cost = 1 size = 0
if (N1.getValueType() == MVT::f80) {
- SDNode *Result = Emit_288(N, X86::ISTT_Fp32m80, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_289(N, X86::ISTT_Fp32m80, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -53162,7 +52871,7 @@ SDNode *Select_X86ISD_FP_TO_INT32_IN_MEM(SDNode *N) {
// Emits: (FP32_TO_INT32_IN_MEM:isVoid addr:iPTR:$dst, RFP32:f32:$src)
// Pattern complexity = 21 cost = 11 size = 3
if (N1.getValueType() == MVT::f32) {
- SDNode *Result = Emit_288(N, X86::FP32_TO_INT32_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_289(N, X86::FP32_TO_INT32_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -53170,7 +52879,7 @@ SDNode *Select_X86ISD_FP_TO_INT32_IN_MEM(SDNode *N) {
// Emits: (FP64_TO_INT32_IN_MEM:isVoid addr:iPTR:$dst, RFP64:f64:$src)
// Pattern complexity = 21 cost = 11 size = 3
if (N1.getValueType() == MVT::f64) {
- SDNode *Result = Emit_288(N, X86::FP64_TO_INT32_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_289(N, X86::FP64_TO_INT32_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -53178,7 +52887,7 @@ SDNode *Select_X86ISD_FP_TO_INT32_IN_MEM(SDNode *N) {
// Emits: (FP80_TO_INT32_IN_MEM:isVoid addr:iPTR:$dst, RFP80:f80:$src)
// Pattern complexity = 21 cost = 11 size = 3
if (N1.getValueType() == MVT::f80) {
- SDNode *Result = Emit_288(N, X86::FP80_TO_INT32_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_289(N, X86::FP80_TO_INT32_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -53203,7 +52912,7 @@ SDNode *Select_X86ISD_FP_TO_INT64_IN_MEM(SDNode *N) {
// Emits: (ISTT_Fp64m32:isVoid addr:iPTR:$op, RFP32:f32:$src)
// Pattern complexity = 21 cost = 1 size = 0
if (N1.getValueType() == MVT::f32) {
- SDNode *Result = Emit_288(N, X86::ISTT_Fp64m32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_289(N, X86::ISTT_Fp64m32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -53211,7 +52920,7 @@ SDNode *Select_X86ISD_FP_TO_INT64_IN_MEM(SDNode *N) {
// Emits: (ISTT_Fp64m64:isVoid addr:iPTR:$op, RFP64:f64:$src)
// Pattern complexity = 21 cost = 1 size = 0
if (N1.getValueType() == MVT::f64) {
- SDNode *Result = Emit_288(N, X86::ISTT_Fp64m64, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_289(N, X86::ISTT_Fp64m64, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -53219,7 +52928,7 @@ SDNode *Select_X86ISD_FP_TO_INT64_IN_MEM(SDNode *N) {
// Emits: (ISTT_Fp64m80:isVoid addr:iPTR:$op, RFP80:f80:$src)
// Pattern complexity = 21 cost = 1 size = 0
if (N1.getValueType() == MVT::f80) {
- SDNode *Result = Emit_288(N, X86::ISTT_Fp64m80, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_289(N, X86::ISTT_Fp64m80, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -53238,7 +52947,7 @@ SDNode *Select_X86ISD_FP_TO_INT64_IN_MEM(SDNode *N) {
// Emits: (FP32_TO_INT64_IN_MEM:isVoid addr:iPTR:$dst, RFP32:f32:$src)
// Pattern complexity = 21 cost = 11 size = 3
if (N1.getValueType() == MVT::f32) {
- SDNode *Result = Emit_288(N, X86::FP32_TO_INT64_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_289(N, X86::FP32_TO_INT64_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -53246,7 +52955,7 @@ SDNode *Select_X86ISD_FP_TO_INT64_IN_MEM(SDNode *N) {
// Emits: (FP64_TO_INT64_IN_MEM:isVoid addr:iPTR:$dst, RFP64:f64:$src)
// Pattern complexity = 21 cost = 11 size = 3
if (N1.getValueType() == MVT::f64) {
- SDNode *Result = Emit_288(N, X86::FP64_TO_INT64_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_289(N, X86::FP64_TO_INT64_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -53254,7 +52963,7 @@ SDNode *Select_X86ISD_FP_TO_INT64_IN_MEM(SDNode *N) {
// Emits: (FP80_TO_INT64_IN_MEM:isVoid addr:iPTR:$dst, RFP80:f80:$src)
// Pattern complexity = 21 cost = 11 size = 3
if (N1.getValueType() == MVT::f80) {
- SDNode *Result = Emit_288(N, X86::FP80_TO_INT64_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_289(N, X86::FP80_TO_INT64_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -53268,8 +52977,7 @@ SDNode *Select_X86ISD_FRCP_f32(SDNode *N) {
// Pattern: (X86frcp:f32 (ld:f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (RCPSSm:f32 addr:iPTR:$src)
// Pattern complexity = 25 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSE1()) && (OptForSize)) {
+ if ((Subtarget->hasSSE1()) && (OptForSize)) {
SDValue N0 = N->getOperand(0);
if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse()) {
@@ -53303,37 +53011,36 @@ SDNode *Select_X86ISD_FRCP_f32(SDNode *N) {
}
SDNode *Select_X86ISD_FRCP_v4f32(SDNode *N) {
+ if ((Subtarget->hasSSE1())) {
- // Pattern: (X86frcp:v4f32 (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (RCPPSm:v4f32 addr:iPTR:$src)
- // Pattern complexity = 25 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse()) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_79(N, X86::RCPPSm, MVT::v4f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
+ // Pattern: (X86frcp:v4f32 (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (RCPPSm:v4f32 addr:iPTR:$src)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse()) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_79(N, X86::RCPPSm, MVT::v4f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
}
}
}
- }
- // Pattern: (X86frcp:v4f32 VR128:v4f32:$src)
- // Emits: (RCPPSr:v4f32 VR128:v4f32:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
+ // Pattern: (X86frcp:v4f32 VR128:v4f32:$src)
+ // Emits: (RCPPSr:v4f32 VR128:v4f32:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
SDNode *Result = Emit_72(N, X86::RCPPSr, MVT::v4f32);
return Result;
}
@@ -53347,8 +53054,7 @@ SDNode *Select_X86ISD_FRSQRT_f32(SDNode *N) {
// Pattern: (X86frsqrt:f32 (ld:f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (RSQRTSSm:f32 addr:iPTR:$src)
// Pattern complexity = 25 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSE1()) && (OptForSize)) {
+ if ((Subtarget->hasSSE1()) && (OptForSize)) {
SDValue N0 = N->getOperand(0);
if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse()) {
@@ -53382,37 +53088,36 @@ SDNode *Select_X86ISD_FRSQRT_f32(SDNode *N) {
}
SDNode *Select_X86ISD_FRSQRT_v4f32(SDNode *N) {
+ if ((Subtarget->hasSSE1())) {
- // Pattern: (X86frsqrt:v4f32 (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (RSQRTPSm:v4f32 addr:iPTR:$src)
- // Pattern complexity = 25 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse()) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_79(N, X86::RSQRTPSm, MVT::v4f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
+ // Pattern: (X86frsqrt:v4f32 (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (RSQRTPSm:v4f32 addr:iPTR:$src)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse()) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_79(N, X86::RSQRTPSm, MVT::v4f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
}
}
}
- }
- // Pattern: (X86frsqrt:v4f32 VR128:v4f32:$src)
- // Emits: (RSQRTPSr:v4f32 VR128:v4f32:$src)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
+ // Pattern: (X86frsqrt:v4f32 VR128:v4f32:$src)
+ // Emits: (RSQRTPSr:v4f32 VR128:v4f32:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
SDNode *Result = Emit_72(N, X86::RSQRTPSr, MVT::v4f32);
return Result;
}
@@ -53421,7 +53126,7 @@ SDNode *Select_X86ISD_FRSQRT_v4f32(SDNode *N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_289(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_290(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
@@ -53435,7 +53140,7 @@ SDNode *Select_X86ISD_FSRL_v2f64(SDNode *N) {
if (N1.getNode()->getOpcode() == ISD::Constant &&
Predicate_i32immSExt8(N1.getNode()) &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_289(N, X86::PSRLDQri, MVT::v2f64);
+ SDNode *Result = Emit_290(N, X86::PSRLDQri, MVT::v2f64);
return Result;
}
}
@@ -53444,7 +53149,7 @@ SDNode *Select_X86ISD_FSRL_v2f64(SDNode *N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_290(SDNode *N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+DISABLE_INLINE SDNode *Emit_291(SDNode *N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
SDValue Chain = N->getOperand(0);
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
@@ -53470,7 +53175,7 @@ SDNode *Select_X86ISD_FST(SDNode *N) {
// Emits: (ST_Fp32m:isVoid addr:iPTR:$op, RFP32:f32:$src)
// Pattern complexity = 21 cost = 1 size = 0
if (N1.getValueType() == MVT::f32) {
- SDNode *Result = Emit_290(N, X86::ST_Fp32m, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_291(N, X86::ST_Fp32m, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -53478,7 +53183,7 @@ SDNode *Select_X86ISD_FST(SDNode *N) {
// Emits: (ST_Fp64m32:isVoid addr:iPTR:$op, RFP64:f64:$src)
// Pattern complexity = 21 cost = 1 size = 0
if (N1.getValueType() == MVT::f64) {
- SDNode *Result = Emit_290(N, X86::ST_Fp64m32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_291(N, X86::ST_Fp64m32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -53488,7 +53193,7 @@ SDNode *Select_X86ISD_FST(SDNode *N) {
// Pattern complexity = 21 cost = 1 size = 0
if (cast<VTSDNode>(N3.getNode())->getVT() == MVT::f64 &&
N1.getValueType() == MVT::f64) {
- SDNode *Result = Emit_290(N, X86::ST_Fp64m, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_291(N, X86::ST_Fp64m, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -53497,7 +53202,7 @@ SDNode *Select_X86ISD_FST(SDNode *N) {
// Pattern complexity = 21 cost = 1 size = 0
if (cast<VTSDNode>(N3.getNode())->getVT() == MVT::f32 &&
N1.getValueType() == MVT::f80) {
- SDNode *Result = Emit_290(N, X86::ST_Fp80m32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_291(N, X86::ST_Fp80m32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -53506,7 +53211,7 @@ SDNode *Select_X86ISD_FST(SDNode *N) {
// Pattern complexity = 21 cost = 1 size = 0
if (cast<VTSDNode>(N3.getNode())->getVT() == MVT::f64 &&
N1.getValueType() == MVT::f80) {
- SDNode *Result = Emit_290(N, X86::ST_Fp80m64, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_291(N, X86::ST_Fp80m64, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -53515,7 +53220,7 @@ SDNode *Select_X86ISD_FST(SDNode *N) {
// Pattern complexity = 21 cost = 1 size = 0
if (cast<VTSDNode>(N3.getNode())->getVT() == MVT::f80 &&
N1.getValueType() == MVT::f80) {
- SDNode *Result = Emit_290(N, X86::ST_FpP80m, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_291(N, X86::ST_FpP80m, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -53525,64 +53230,63 @@ SDNode *Select_X86ISD_FST(SDNode *N) {
}
SDNode *Select_X86ISD_FXOR_f32(SDNode *N) {
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (X86fxor:f32 FR32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (FsXORPSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
{
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::FsXORPSrm, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
+ SDValue N0 = N->getOperand(0);
+
+ // Pattern: (X86fxor:f32 FR32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (FsXORPSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::FsXORPSrm, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
}
}
}
- }
- // Pattern: (X86fxor:f32 (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, FR32:f32:$src1)
- // Emits: (FsXORPSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_19(N, X86::FsXORPSrm, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
+ // Pattern: (X86fxor:f32 (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, FR32:f32:$src1)
+ // Emits: (FsXORPSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_19(N, X86::FsXORPSrm, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
}
}
}
- }
- // Pattern: (X86fxor:f32 FR32:f32:$src1, FR32:f32:$src2)
- // Emits: (FsXORPSrr:f32 FR32:f32:$src1, FR32:f32:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
+ // Pattern: (X86fxor:f32 FR32:f32:$src1, FR32:f32:$src2)
+ // Emits: (FsXORPSrr:f32 FR32:f32:$src1, FR32:f32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
SDNode *Result = Emit_15(N, X86::FsXORPSrr, MVT::f32);
return Result;
}
@@ -53592,64 +53296,63 @@ SDNode *Select_X86ISD_FXOR_f32(SDNode *N) {
}
SDNode *Select_X86ISD_FXOR_f64(SDNode *N) {
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
-
- // Pattern: (X86fxor:f64 FR64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
- // Emits: (FsXORPDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
{
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_18(N, X86::FsXORPDrm, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
+ SDValue N0 = N->getOperand(0);
+
+ // Pattern: (X86fxor:f64 FR64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Emits: (FsXORPDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_memop(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_18(N, X86::FsXORPDrm, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
}
}
}
- }
- // Pattern: (X86fxor:f64 (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, FR64:f64:$src1)
- // Emits: (FsXORPDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode()) &&
- Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_19(N, X86::FsXORPDrm, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
+ // Pattern: (X86fxor:f64 (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, FR64:f64:$src1)
+ // Emits: (FsXORPDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_memop(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_19(N, X86::FsXORPDrm, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
}
}
}
- }
- // Pattern: (X86fxor:f64 FR64:f64:$src1, FR64:f64:$src2)
- // Emits: (FsXORPDrr:f64 FR64:f64:$src1, FR64:f64:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
+ // Pattern: (X86fxor:f64 FR64:f64:$src1, FR64:f64:$src2)
+ // Emits: (FsXORPDrr:f64 FR64:f64:$src1, FR64:f64:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
SDNode *Result = Emit_15(N, X86::FsXORPDrr, MVT::f64);
return Result;
}
@@ -53661,7 +53364,7 @@ SDNode *Select_X86ISD_FXOR_f64(SDNode *N) {
SDNode *Select_X86ISD_INC_i8(SDNode *N) {
SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_251(N, X86::INC8r, MVT::i8);
+ SDNode *Result = Emit_252(N, X86::INC8r, MVT::i8);
return Result;
}
@@ -53677,7 +53380,7 @@ SDNode *Select_X86ISD_INC_i16(SDNode *N) {
if ((!Subtarget->is64Bit())) {
SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_251(N, X86::INC16r, MVT::i16);
+ SDNode *Result = Emit_252(N, X86::INC16r, MVT::i16);
return Result;
}
}
@@ -53688,7 +53391,7 @@ SDNode *Select_X86ISD_INC_i16(SDNode *N) {
if ((Subtarget->is64Bit())) {
SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_251(N, X86::INC64_16r, MVT::i16);
+ SDNode *Result = Emit_252(N, X86::INC64_16r, MVT::i16);
return Result;
}
}
@@ -53705,7 +53408,7 @@ SDNode *Select_X86ISD_INC_i32(SDNode *N) {
if ((!Subtarget->is64Bit())) {
SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_251(N, X86::INC32r, MVT::i32);
+ SDNode *Result = Emit_252(N, X86::INC32r, MVT::i32);
return Result;
}
}
@@ -53716,7 +53419,7 @@ SDNode *Select_X86ISD_INC_i32(SDNode *N) {
if ((Subtarget->is64Bit())) {
SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_251(N, X86::INC64_32r, MVT::i32);
+ SDNode *Result = Emit_252(N, X86::INC64_32r, MVT::i32);
return Result;
}
}
@@ -53728,7 +53431,7 @@ SDNode *Select_X86ISD_INC_i32(SDNode *N) {
SDNode *Select_X86ISD_INC_i64(SDNode *N) {
SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_251(N, X86::INC64r, MVT::i64);
+ SDNode *Result = Emit_252(N, X86::INC64r, MVT::i64);
return Result;
}
@@ -53736,7 +53439,7 @@ SDNode *Select_X86ISD_INC_i64(SDNode *N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_291(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+DISABLE_INLINE SDNode *Emit_292(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
SDValue N10 = N1.getNode()->getOperand(0);
@@ -53753,14 +53456,13 @@ DISABLE_INLINE SDNode *Emit_291(SDNode *N, unsigned Opc0, MVT::SimpleValueType V
return ResNode;
}
SDNode *Select_X86ISD_INSERTPS_v4f32(SDNode *N) {
-
- // Pattern: (X86insrtps:v4f32 VR128:v4f32:$src1, (scalar_to_vector:v4f32 (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>), (imm:iPTR):$src3)
- // Emits: (INSERTPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2, (imm:i32):$src3)
- // Pattern complexity = 31 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSE41())) {
+ if ((Subtarget->hasSSE41())) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
+
+ // Pattern: (X86insrtps:v4f32 VR128:v4f32:$src1, (scalar_to_vector:v4f32 (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>), (imm:iPTR):$src3)
+ // Emits: (INSERTPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2, (imm:i32):$src3)
+ // Pattern complexity = 31 cost = 1 size = 3
if (N1.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
N1.hasOneUse()) {
SDValue N10 = N1.getNode()->getOperand(0);
@@ -53781,21 +53483,17 @@ SDNode *Select_X86ISD_INSERTPS_v4f32(SDNode *N) {
SDValue N2 = N->getOperand(2);
if (N2.getNode()->getOpcode() == ISD::Constant &&
N10.getValueType() == MVT::f32) {
- SDNode *Result = Emit_291(N, X86::INSERTPSrm, MVT::v4f32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_292(N, X86::INSERTPSrm, MVT::v4f32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
}
}
}
- }
- // Pattern: (X86insrtps:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2, (imm:iPTR):$src3)
- // Emits: (INSERTPSrr:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2, (imm:i32):$src3)
- // Pattern complexity = 6 cost = 1 size = 3
- if ((Subtarget->hasSSE41())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
+ // Pattern: (X86insrtps:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2, (imm:iPTR):$src3)
+ // Emits: (INSERTPSrr:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2, (imm:i32):$src3)
+ // Pattern complexity = 6 cost = 1 size = 3
SDValue N2 = N->getOperand(2);
if (N2.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_98(N, X86::INSERTPSrr, MVT::v4f32);
@@ -53807,7 +53505,7 @@ SDNode *Select_X86ISD_INSERTPS_v4f32(SDNode *N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_292(SDNode *N, unsigned Opc0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
+DISABLE_INLINE SDNode *Emit_293(SDNode *N, unsigned Opc0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
SDValue Chain = N->getOperand(0);
SDValue N1 = N->getOperand(1);
SDValue InFlag = N->getOperand(2);
@@ -53835,7 +53533,7 @@ SDNode *Select_X86ISD_LCMPXCHG8_DAG(SDNode *N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_292(N, X86::LCMPXCHG8B, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_293(N, X86::LCMPXCHG8B, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
@@ -53843,7 +53541,7 @@ SDNode *Select_X86ISD_LCMPXCHG8_DAG(SDNode *N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_293(SDNode *N, unsigned Opc0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
+DISABLE_INLINE SDNode *Emit_294(SDNode *N, unsigned Opc0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
SDValue Chain = N->getOperand(0);
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
@@ -53884,7 +53582,7 @@ SDNode *Select_X86ISD_LCMPXCHG_DAG(SDNode *N) {
// Pattern complexity = 26 cost = 1 size = 3
if (CN1 == INT64_C(4) &&
N2.getValueType() == MVT::i32) {
- SDNode *Result = Emit_293(N, X86::LCMPXCHG32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_294(N, X86::LCMPXCHG32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
@@ -53893,7 +53591,7 @@ SDNode *Select_X86ISD_LCMPXCHG_DAG(SDNode *N) {
// Pattern complexity = 26 cost = 1 size = 3
if (CN1 == INT64_C(2) &&
N2.getValueType() == MVT::i16) {
- SDNode *Result = Emit_293(N, X86::LCMPXCHG16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_294(N, X86::LCMPXCHG16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
@@ -53902,7 +53600,7 @@ SDNode *Select_X86ISD_LCMPXCHG_DAG(SDNode *N) {
// Pattern complexity = 26 cost = 1 size = 3
if (CN1 == INT64_C(1) &&
N2.getValueType() == MVT::i8) {
- SDNode *Result = Emit_293(N, X86::LCMPXCHG8, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_294(N, X86::LCMPXCHG8, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
@@ -53911,7 +53609,7 @@ SDNode *Select_X86ISD_LCMPXCHG_DAG(SDNode *N) {
// Pattern complexity = 26 cost = 1 size = 3
if (CN1 == INT64_C(8) &&
N2.getValueType() == MVT::i64) {
- SDNode *Result = Emit_293(N, X86::LCMPXCHG64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_294(N, X86::LCMPXCHG64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -53921,7 +53619,7 @@ SDNode *Select_X86ISD_LCMPXCHG_DAG(SDNode *N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_294(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0001_0, SDValue &CPTmpN0001_1, SDValue &CPTmpN0001_2, SDValue &CPTmpN0001_3, SDValue &CPTmpN0001_4) {
+DISABLE_INLINE SDNode *Emit_295(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0001_0, SDValue &CPTmpN0001_1, SDValue &CPTmpN0001_2, SDValue &CPTmpN0001_3, SDValue &CPTmpN0001_4) {
SDValue N0 = N->getOperand(0);
SDValue N00 = N0.getNode()->getOperand(0);
SDValue N000 = N00.getNode()->getOperand(0);
@@ -53936,7 +53634,7 @@ DISABLE_INLINE SDNode *Emit_294(SDNode *N, unsigned Opc0, MVT::SimpleValueType V
return ResNode;
}
SDNode *Select_X86ISD_MOVQ2DQ_v2i64(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
// Pattern: (MMX_X86movq2dq:v2i64 (bitconvert:v1i64 (scalar_to_vector:v2i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)))
@@ -53963,7 +53661,7 @@ SDNode *Select_X86ISD_MOVQ2DQ_v2i64(SDNode *N) {
if (SelectAddr(N, N0001, CPTmpN0001_0, CPTmpN0001_1, CPTmpN0001_2, CPTmpN0001_3, CPTmpN0001_4) &&
N00.getValueType() == MVT::v2i32 &&
N000.getValueType() == MVT::i32) {
- SDNode *Result = Emit_294(N, X86::MOVDI2PDIrm, MVT::v2i64, CPTmpN0001_0, CPTmpN0001_1, CPTmpN0001_2, CPTmpN0001_3, CPTmpN0001_4);
+ SDNode *Result = Emit_295(N, X86::MOVDI2PDIrm, MVT::v2i64, CPTmpN0001_0, CPTmpN0001_1, CPTmpN0001_2, CPTmpN0001_3, CPTmpN0001_4);
return Result;
}
}
@@ -54049,7 +53747,7 @@ SDNode *Select_X86ISD_MUL_IMM_i64(SDNode *N) {
}
SDNode *Select_X86ISD_OR_i8(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
// Pattern: (X86or_flag:i8 GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>)
@@ -54100,13 +53798,10 @@ SDNode *Select_X86ISD_OR_i8(SDNode *N) {
}
}
}
- }
- // Pattern: (X86or_flag:i8 GR8:i8:$src1, (imm:i8):$src2)
- // Emits: (OR8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- {
- SDValue N0 = N->getOperand(0);
+ // Pattern: (X86or_flag:i8 GR8:i8:$src1, (imm:i8):$src2)
+ // Emits: (OR8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_3(N, X86::OR8ri, MVT::i8);
@@ -54122,7 +53817,7 @@ SDNode *Select_X86ISD_OR_i8(SDNode *N) {
}
SDNode *Select_X86ISD_OR_i16(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
// Pattern: (X86or_flag:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>)
@@ -54171,9 +53866,6 @@ SDNode *Select_X86ISD_OR_i16(SDNode *N) {
}
}
}
- }
- {
- SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::Constant) {
@@ -54201,7 +53893,7 @@ SDNode *Select_X86ISD_OR_i16(SDNode *N) {
}
SDNode *Select_X86ISD_OR_i32(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
// Pattern: (X86or_flag:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
@@ -54250,9 +53942,6 @@ SDNode *Select_X86ISD_OR_i32(SDNode *N) {
}
}
}
- }
- {
- SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::Constant) {
@@ -54280,7 +53969,7 @@ SDNode *Select_X86ISD_OR_i32(SDNode *N) {
}
SDNode *Select_X86ISD_OR_i64(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
// Pattern: (X86or_flag:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
@@ -54331,9 +54020,6 @@ SDNode *Select_X86ISD_OR_i64(SDNode *N) {
}
}
}
- }
- {
- SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::Constant) {
@@ -54363,7 +54049,7 @@ SDNode *Select_X86ISD_OR_i64(SDNode *N) {
}
SDNode *Select_X86ISD_PCMPEQB_v8i8(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
// Pattern: (X86pcmpeqb:v8i8 VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
@@ -54434,7 +54120,7 @@ SDNode *Select_X86ISD_PCMPEQB_v8i8(SDNode *N) {
}
SDNode *Select_X86ISD_PCMPEQB_v16i8(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
// Pattern: (X86pcmpeqb:v16i8 VR128:v16i8:$src1, (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
@@ -54495,7 +54181,7 @@ SDNode *Select_X86ISD_PCMPEQB_v16i8(SDNode *N) {
}
SDNode *Select_X86ISD_PCMPEQD_v2i32(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
// Pattern: (X86pcmpeqd:v2i32 VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
@@ -54566,7 +54252,7 @@ SDNode *Select_X86ISD_PCMPEQD_v2i32(SDNode *N) {
}
SDNode *Select_X86ISD_PCMPEQD_v4i32(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
// Pattern: (X86pcmpeqd:v4i32 VR128:v4i32:$src1, (ld:v4i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
@@ -54627,7 +54313,7 @@ SDNode *Select_X86ISD_PCMPEQD_v4i32(SDNode *N) {
}
SDNode *Select_X86ISD_PCMPEQQ_v2i64(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
// Pattern: (X86pcmpeqq:v2i64 VR128:v2i64:$src1, (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
@@ -54688,7 +54374,7 @@ SDNode *Select_X86ISD_PCMPEQQ_v2i64(SDNode *N) {
}
SDNode *Select_X86ISD_PCMPEQW_v4i16(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
// Pattern: (X86pcmpeqw:v4i16 VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
@@ -54759,7 +54445,7 @@ SDNode *Select_X86ISD_PCMPEQW_v4i16(SDNode *N) {
}
SDNode *Select_X86ISD_PCMPEQW_v8i16(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
// Pattern: (X86pcmpeqw:v8i16 VR128:v8i16:$src1, (ld:v8i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
@@ -54824,7 +54510,7 @@ SDNode *Select_X86ISD_PCMPGTB_v8i8(SDNode *N) {
// Pattern: (X86pcmpgtb:v8i8 VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
// Emits: (MMX_PCMPGTBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 28 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
@@ -54864,7 +54550,7 @@ SDNode *Select_X86ISD_PCMPGTB_v16i8(SDNode *N) {
// Pattern: (X86pcmpgtb:v16i8 VR128:v16i8:$src1, (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (PCMPGTBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::LOAD &&
@@ -54900,7 +54586,7 @@ SDNode *Select_X86ISD_PCMPGTD_v2i32(SDNode *N) {
// Pattern: (X86pcmpgtd:v2i32 VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
// Emits: (MMX_PCMPGTDrm:v2i32 VR64:v8i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 28 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
@@ -54940,7 +54626,7 @@ SDNode *Select_X86ISD_PCMPGTD_v4i32(SDNode *N) {
// Pattern: (X86pcmpgtd:v4i32 VR128:v4i32:$src1, (ld:v4i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (PCMPGTDrm:v4i32 VR128:v16i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::LOAD &&
@@ -54976,7 +54662,7 @@ SDNode *Select_X86ISD_PCMPGTQ_v2i64(SDNode *N) {
// Pattern: (X86pcmpgtq:v2i64 VR128:v2i64:$src1, (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (PCMPGTQrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::LOAD &&
@@ -55012,7 +54698,7 @@ SDNode *Select_X86ISD_PCMPGTW_v4i16(SDNode *N) {
// Pattern: (X86pcmpgtw:v4i16 VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
// Emits: (MMX_PCMPGTWrm:v4i16 VR64:v8i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 28 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
@@ -55052,7 +54738,7 @@ SDNode *Select_X86ISD_PCMPGTW_v8i16(SDNode *N) {
// Pattern: (X86pcmpgtw:v8i16 VR128:v8i16:$src1, (ld:v8i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (PCMPGTWrm:v8i16 VR128:v16i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::LOAD &&
@@ -55098,7 +54784,7 @@ SDNode *Select_X86ISD_PEXTRB_i32(SDNode *N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_295(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_296(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned short) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i16);
@@ -55128,7 +54814,7 @@ SDNode *Select_X86ISD_PEXTRW_i32(SDNode *N) {
if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v4i16 &&
N1.getValueType() == TLI.getPointerTy()) {
- SDNode *Result = Emit_295(N, X86::MMX_PEXTRWri, MVT::i32);
+ SDNode *Result = Emit_296(N, X86::MMX_PEXTRWri, MVT::i32);
return Result;
}
}
@@ -55138,14 +54824,13 @@ SDNode *Select_X86ISD_PEXTRW_i32(SDNode *N) {
}
SDNode *Select_X86ISD_PINSRB_v16i8(SDNode *N) {
-
- // Pattern: (X86pinsrb:v16i8 VR128:v16i8:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, (imm:iPTR):$src3)
- // Emits: (PINSRBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2, (imm:i32):$src3)
- // Pattern complexity = 28 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSE41())) {
+ if ((Subtarget->hasSSE41())) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
+
+ // Pattern: (X86pinsrb:v16i8 VR128:v16i8:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, (imm:iPTR):$src3)
+ // Emits: (PINSRBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2, (imm:i32):$src3)
+ // Pattern complexity = 28 cost = 1 size = 3
if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
@@ -55168,14 +54853,10 @@ SDNode *Select_X86ISD_PINSRB_v16i8(SDNode *N) {
}
}
}
- }
- // Pattern: (X86pinsrb:v16i8 VR128:v16i8:$src1, GR32:i32:$src2, (imm:iPTR):$src3)
- // Emits: (PINSRBrr:v16i8 VR128:v16i8:$src1, GR32:i32:$src2, (imm:i32):$src3)
- // Pattern complexity = 6 cost = 1 size = 3
- if ((Subtarget->hasSSE41())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
+ // Pattern: (X86pinsrb:v16i8 VR128:v16i8:$src1, GR32:i32:$src2, (imm:iPTR):$src3)
+ // Emits: (PINSRBrr:v16i8 VR128:v16i8:$src1, GR32:i32:$src2, (imm:i32):$src3)
+ // Pattern complexity = 6 cost = 1 size = 3
SDValue N2 = N->getOperand(2);
if (N2.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_98(N, X86::PINSRBrr, MVT::v16i8);
@@ -55187,14 +54868,14 @@ SDNode *Select_X86ISD_PINSRB_v16i8(SDNode *N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_296(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_297(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned short) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i16);
return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, N1, Tmp2);
}
-DISABLE_INLINE SDNode *Emit_297(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+DISABLE_INLINE SDNode *Emit_298(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
SDValue N10 = N1.getNode()->getOperand(0);
@@ -55211,14 +54892,13 @@ DISABLE_INLINE SDNode *Emit_297(SDNode *N, unsigned Opc0, MVT::SimpleValueType V
return ResNode;
}
SDNode *Select_X86ISD_PINSRW_v4i16(SDNode *N) {
-
- // Pattern: (MMX_X86pinsrw:v4i16 VR64:v4i16:$src1, (anyext:i32 (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>), (imm:iPTR):$src3)
- // Emits: (MMX_PINSRWrmi:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2, (imm:i16):$src3)
- // Pattern complexity = 31 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasMMX())) {
+ if ((Subtarget->hasMMX())) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
+
+ // Pattern: (MMX_X86pinsrw:v4i16 VR64:v4i16:$src1, (anyext:i32 (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>), (imm:iPTR):$src3)
+ // Emits: (MMX_PINSRWrmi:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2, (imm:i16):$src3)
+ // Pattern complexity = 31 cost = 1 size = 3
if (N1.getNode()->getOpcode() == ISD::ANY_EXTEND &&
N1.hasOneUse()) {
SDValue N10 = N1.getNode()->getOperand(0);
@@ -55241,27 +54921,23 @@ SDNode *Select_X86ISD_PINSRW_v4i16(SDNode *N) {
N1.getValueType() == MVT::i32 &&
N10.getValueType() == MVT::i16 &&
N2.getValueType() == TLI.getPointerTy()) {
- SDNode *Result = Emit_297(N, X86::MMX_PINSRWrmi, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_298(N, X86::MMX_PINSRWrmi, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
}
}
}
- }
- // Pattern: (MMX_X86pinsrw:v4i16 VR64:v4i16:$src1, GR32:i32:$src2, (imm:iPTR):$src3)
- // Emits: (MMX_PINSRWrri:v4i16 VR64:v4i16:$src1, GR32:i32:$src2, (imm:i16):$src3)
- // Pattern complexity = 6 cost = 1 size = 3
- if ((Subtarget->hasMMX())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
+ // Pattern: (MMX_X86pinsrw:v4i16 VR64:v4i16:$src1, GR32:i32:$src2, (imm:iPTR):$src3)
+ // Emits: (MMX_PINSRWrri:v4i16 VR64:v4i16:$src1, GR32:i32:$src2, (imm:i16):$src3)
+ // Pattern complexity = 6 cost = 1 size = 3
SDValue N2 = N->getOperand(2);
if (N2.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v4i16 &&
N1.getValueType() == MVT::i32 &&
N2.getValueType() == TLI.getPointerTy()) {
- SDNode *Result = Emit_296(N, X86::MMX_PINSRWrri, MVT::v4i16);
+ SDNode *Result = Emit_297(N, X86::MMX_PINSRWrri, MVT::v4i16);
return Result;
}
}
@@ -55271,14 +54947,13 @@ SDNode *Select_X86ISD_PINSRW_v4i16(SDNode *N) {
}
SDNode *Select_X86ISD_PINSRW_v8i16(SDNode *N) {
-
- // Pattern: (X86pinsrw:v8i16 VR128:v8i16:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, (imm:iPTR):$src3)
- // Emits: (PINSRWrmi:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2, (imm:i32):$src3)
- // Pattern complexity = 28 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSE2())) {
+ if ((Subtarget->hasSSE2())) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
+
+ // Pattern: (X86pinsrw:v8i16 VR128:v8i16:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, (imm:iPTR):$src3)
+ // Emits: (PINSRWrmi:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2, (imm:i32):$src3)
+ // Pattern complexity = 28 cost = 1 size = 3
if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
@@ -55301,14 +54976,10 @@ SDNode *Select_X86ISD_PINSRW_v8i16(SDNode *N) {
}
}
}
- }
- // Pattern: (X86pinsrw:v8i16 VR128:v8i16:$src1, GR32:i32:$src2, (imm:iPTR):$src3)
- // Emits: (PINSRWrri:v8i16 VR128:v8i16:$src1, GR32:i32:$src2, (imm:i32):$src3)
- // Pattern complexity = 6 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
+ // Pattern: (X86pinsrw:v8i16 VR128:v8i16:$src1, GR32:i32:$src2, (imm:iPTR):$src3)
+ // Emits: (PINSRWrri:v8i16 VR128:v8i16:$src1, GR32:i32:$src2, (imm:i32):$src3)
+ // Pattern complexity = 6 cost = 1 size = 3
SDValue N2 = N->getOperand(2);
if (N2.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_98(N, X86::PINSRWrri, MVT::v8i16);
@@ -55321,44 +54992,43 @@ SDNode *Select_X86ISD_PINSRW_v8i16(SDNode *N) {
}
SDNode *Select_X86ISD_PSHUFB_v16i8(SDNode *N) {
+ if ((Subtarget->hasSSSE3())) {
- // Pattern: (X86pshufb:v16i8 VR128:v16i8:$src, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$mask)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
- // Emits: (PSHUFBrm128:v16i8 VR128:v16i8:$src, addr:iPTR:$mask)
- // Pattern complexity = 28 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSSE3())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N1.hasOneUse()) {
- SDValue N10 = N1.getNode()->getOperand(0);
- if (N10.getNode()->getOpcode() == ISD::LOAD &&
- N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
- SDValue Chain10 = N10.getNode()->getOperand(0);
- if (Predicate_unindexedload(N10.getNode()) &&
- Predicate_load(N10.getNode()) &&
- Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getNode()->getOperand(1);
- SDValue CPTmpN101_0;
- SDValue CPTmpN101_1;
- SDValue CPTmpN101_2;
- SDValue CPTmpN101_3;
- SDValue CPTmpN101_4;
- if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
- N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_16(N, X86::PSHUFBrm128, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
- return Result;
+ // Pattern: (X86pshufb:v16i8 VR128:v16i8:$src, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$mask)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Emits: (PSHUFBrm128:v16i8 VR128:v16i8:$src, addr:iPTR:$mask)
+ // Pattern complexity = 28 cost = 1 size = 3
+ {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
+ N10.hasOneUse() &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N10.getNode()) &&
+ Predicate_load(N10.getNode()) &&
+ Predicate_memop(N10.getNode())) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue CPTmpN101_0;
+ SDValue CPTmpN101_1;
+ SDValue CPTmpN101_2;
+ SDValue CPTmpN101_3;
+ SDValue CPTmpN101_4;
+ if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
+ N10.getValueType() == MVT::v2i64) {
+ SDNode *Result = Emit_16(N, X86::PSHUFBrm128, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ return Result;
+ }
}
}
}
}
- }
- // Pattern: (X86pshufb:v16i8 VR128:v16i8:$src, VR128:v16i8:$mask)
- // Emits: (PSHUFBrr128:v16i8 VR128:v16i8:$src, VR128:v16i8:$mask)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSSE3())) {
+ // Pattern: (X86pshufb:v16i8 VR128:v16i8:$src, VR128:v16i8:$mask)
+ // Emits: (PSHUFBrr128:v16i8 VR128:v16i8:$src, VR128:v16i8:$mask)
+ // Pattern complexity = 3 cost = 1 size = 3
SDNode *Result = Emit_15(N, X86::PSHUFBrr128, MVT::v16i8);
return Result;
}
@@ -55368,39 +55038,38 @@ SDNode *Select_X86ISD_PSHUFB_v16i8(SDNode *N) {
}
SDNode *Select_X86ISD_PTEST(SDNode *N) {
+ if ((Subtarget->hasSSE41())) {
- // Pattern: (X86ptest:isVoid VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (PTESTrm:isVoid VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None &&
- (Subtarget->hasSSE41())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_276(N, X86::PTESTrm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
+ // Pattern: (X86ptest:isVoid VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (PTESTrm:isVoid VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_277(N, X86::PTESTrm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
}
}
}
- }
- // Pattern: (X86ptest:isVoid VR128:v4f32:$src1, VR128:v4f32:$src2)
- // Emits: (PTESTrr:isVoid VR128:v4f32:$src1, VR128:v4f32:$src2)
- // Pattern complexity = 3 cost = 1 size = 3
- if ((Subtarget->hasSSE41())) {
- SDNode *Result = Emit_253(N, X86::PTESTrr);
+ // Pattern: (X86ptest:isVoid VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Emits: (PTESTrr:isVoid VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_254(N, X86::PTESTrr);
return Result;
}
@@ -55408,7 +55077,7 @@ SDNode *Select_X86ISD_PTEST(SDNode *N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_298(SDNode *N, unsigned Opc0) {
+DISABLE_INLINE SDNode *Emit_299(SDNode *N, unsigned Opc0) {
SDValue Chain = N->getOperand(0);
SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, MVT::Flag, Chain);
Chain = SDValue(ResNode, 0);
@@ -55425,11 +55094,11 @@ DISABLE_INLINE SDNode *Emit_298(SDNode *N, unsigned Opc0) {
return ResNode;
}
SDNode *Select_X86ISD_RDTSC_DAG(SDNode *N) {
- SDNode *Result = Emit_298(N, X86::RDTSC);
+ SDNode *Result = Emit_299(N, X86::RDTSC);
return Result;
}
-DISABLE_INLINE SDNode *Emit_299(SDNode *N, unsigned Opc0) {
+DISABLE_INLINE SDNode *Emit_300(SDNode *N, unsigned Opc0) {
SDValue Chain = N->getOperand(0);
SDValue N1 = N->getOperand(1);
SDValue InFlag = N->getOperand(2);
@@ -55455,7 +55124,7 @@ SDNode *Select_X86ISD_REP_MOVS(SDNode *N) {
// Emits: (REP_MOVSB:isVoid)
// Pattern complexity = 3 cost = 1 size = 3
if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i8) {
- SDNode *Result = Emit_299(N, X86::REP_MOVSB);
+ SDNode *Result = Emit_300(N, X86::REP_MOVSB);
return Result;
}
@@ -55463,7 +55132,7 @@ SDNode *Select_X86ISD_REP_MOVS(SDNode *N) {
// Emits: (REP_MOVSW:isVoid)
// Pattern complexity = 3 cost = 1 size = 3
if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i16) {
- SDNode *Result = Emit_299(N, X86::REP_MOVSW);
+ SDNode *Result = Emit_300(N, X86::REP_MOVSW);
return Result;
}
@@ -55471,7 +55140,7 @@ SDNode *Select_X86ISD_REP_MOVS(SDNode *N) {
// Emits: (REP_MOVSD:isVoid)
// Pattern complexity = 3 cost = 1 size = 3
if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i32) {
- SDNode *Result = Emit_299(N, X86::REP_MOVSD);
+ SDNode *Result = Emit_300(N, X86::REP_MOVSD);
return Result;
}
@@ -55479,7 +55148,7 @@ SDNode *Select_X86ISD_REP_MOVS(SDNode *N) {
// Emits: (REP_MOVSQ:isVoid)
// Pattern complexity = 3 cost = 1 size = 3
if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i64) {
- SDNode *Result = Emit_299(N, X86::REP_MOVSQ);
+ SDNode *Result = Emit_300(N, X86::REP_MOVSQ);
return Result;
}
@@ -55495,7 +55164,7 @@ SDNode *Select_X86ISD_REP_STOS(SDNode *N) {
// Emits: (REP_STOSB:isVoid)
// Pattern complexity = 3 cost = 1 size = 3
if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i8) {
- SDNode *Result = Emit_299(N, X86::REP_STOSB);
+ SDNode *Result = Emit_300(N, X86::REP_STOSB);
return Result;
}
@@ -55503,7 +55172,7 @@ SDNode *Select_X86ISD_REP_STOS(SDNode *N) {
// Emits: (REP_STOSW:isVoid)
// Pattern complexity = 3 cost = 1 size = 3
if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i16) {
- SDNode *Result = Emit_299(N, X86::REP_STOSW);
+ SDNode *Result = Emit_300(N, X86::REP_STOSW);
return Result;
}
@@ -55511,7 +55180,7 @@ SDNode *Select_X86ISD_REP_STOS(SDNode *N) {
// Emits: (REP_STOSD:isVoid)
// Pattern complexity = 3 cost = 1 size = 3
if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i32) {
- SDNode *Result = Emit_299(N, X86::REP_STOSD);
+ SDNode *Result = Emit_300(N, X86::REP_STOSD);
return Result;
}
@@ -55519,7 +55188,7 @@ SDNode *Select_X86ISD_REP_STOS(SDNode *N) {
// Emits: (REP_STOSQ:isVoid)
// Pattern complexity = 3 cost = 1 size = 3
if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i64) {
- SDNode *Result = Emit_299(N, X86::REP_STOSQ);
+ SDNode *Result = Emit_300(N, X86::REP_STOSQ);
return Result;
}
@@ -55527,7 +55196,7 @@ SDNode *Select_X86ISD_REP_STOS(SDNode *N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_300(SDNode *N, unsigned Opc0, unsigned NumInputRootOps) {
+DISABLE_INLINE SDNode *Emit_301(SDNode *N, unsigned Opc0, unsigned NumInputRootOps) {
SDValue Chain = N->getOperand(0);
SDValue N1 = N->getOperand(1);
bool HasInFlag = (N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag);
@@ -55544,7 +55213,7 @@ DISABLE_INLINE SDNode *Emit_300(SDNode *N, unsigned Opc0, unsigned NumInputRootO
Ops0.push_back(InFlag);
return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, &Ops0[0], Ops0.size());
}
-DISABLE_INLINE SDNode *Emit_301(SDNode *N, unsigned Opc0, unsigned NumInputRootOps) {
+DISABLE_INLINE SDNode *Emit_302(SDNode *N, unsigned Opc0, unsigned NumInputRootOps) {
SDValue Chain = N->getOperand(0);
SDValue N1 = N->getOperand(1);
bool HasInFlag = (N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag);
@@ -55574,7 +55243,7 @@ SDNode *Select_X86ISD_RET_FLAG(SDNode *N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_300(N, X86::RET, 1);
+ SDNode *Result = Emit_301(N, X86::RET, 1);
return Result;
}
}
@@ -55584,7 +55253,7 @@ SDNode *Select_X86ISD_RET_FLAG(SDNode *N) {
// Emits: (RETI:isVoid (timm:i16):$amt)
// Pattern complexity = 6 cost = 1 size = 3
if (N1.getNode()->getOpcode() == ISD::TargetConstant) {
- SDNode *Result = Emit_301(N, X86::RETI, 1);
+ SDNode *Result = Emit_302(N, X86::RETI, 1);
return Result;
}
@@ -55592,7 +55261,7 @@ SDNode *Select_X86ISD_RET_FLAG(SDNode *N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_302(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_303(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
SDValue Chain = CurDAG->getEntryNode();
@@ -55612,7 +55281,7 @@ SDNode *Select_X86ISD_SETCC_i8(SDNode *N) {
// Emits: (SETEr:i8)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(4)) {
- SDNode *Result = Emit_302(N, X86::SETEr, MVT::i8);
+ SDNode *Result = Emit_303(N, X86::SETEr, MVT::i8);
return Result;
}
@@ -55620,7 +55289,7 @@ SDNode *Select_X86ISD_SETCC_i8(SDNode *N) {
// Emits: (SETNEr:i8)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(9)) {
- SDNode *Result = Emit_302(N, X86::SETNEr, MVT::i8);
+ SDNode *Result = Emit_303(N, X86::SETNEr, MVT::i8);
return Result;
}
@@ -55628,7 +55297,7 @@ SDNode *Select_X86ISD_SETCC_i8(SDNode *N) {
// Emits: (SETLr:i8)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(7)) {
- SDNode *Result = Emit_302(N, X86::SETLr, MVT::i8);
+ SDNode *Result = Emit_303(N, X86::SETLr, MVT::i8);
return Result;
}
@@ -55636,7 +55305,7 @@ SDNode *Select_X86ISD_SETCC_i8(SDNode *N) {
// Emits: (SETGEr:i8)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(6)) {
- SDNode *Result = Emit_302(N, X86::SETGEr, MVT::i8);
+ SDNode *Result = Emit_303(N, X86::SETGEr, MVT::i8);
return Result;
}
@@ -55644,7 +55313,7 @@ SDNode *Select_X86ISD_SETCC_i8(SDNode *N) {
// Emits: (SETLEr:i8)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(8)) {
- SDNode *Result = Emit_302(N, X86::SETLEr, MVT::i8);
+ SDNode *Result = Emit_303(N, X86::SETLEr, MVT::i8);
return Result;
}
@@ -55652,7 +55321,7 @@ SDNode *Select_X86ISD_SETCC_i8(SDNode *N) {
// Emits: (SETGr:i8)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(5)) {
- SDNode *Result = Emit_302(N, X86::SETGr, MVT::i8);
+ SDNode *Result = Emit_303(N, X86::SETGr, MVT::i8);
return Result;
}
@@ -55660,7 +55329,7 @@ SDNode *Select_X86ISD_SETCC_i8(SDNode *N) {
// Emits: (SETBr:i8)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_302(N, X86::SETBr, MVT::i8);
+ SDNode *Result = Emit_303(N, X86::SETBr, MVT::i8);
return Result;
}
@@ -55668,7 +55337,7 @@ SDNode *Select_X86ISD_SETCC_i8(SDNode *N) {
// Emits: (SETAEr:i8)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(1)) {
- SDNode *Result = Emit_302(N, X86::SETAEr, MVT::i8);
+ SDNode *Result = Emit_303(N, X86::SETAEr, MVT::i8);
return Result;
}
@@ -55676,7 +55345,7 @@ SDNode *Select_X86ISD_SETCC_i8(SDNode *N) {
// Emits: (SETBEr:i8)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(3)) {
- SDNode *Result = Emit_302(N, X86::SETBEr, MVT::i8);
+ SDNode *Result = Emit_303(N, X86::SETBEr, MVT::i8);
return Result;
}
@@ -55684,7 +55353,7 @@ SDNode *Select_X86ISD_SETCC_i8(SDNode *N) {
// Emits: (SETAr:i8)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_302(N, X86::SETAr, MVT::i8);
+ SDNode *Result = Emit_303(N, X86::SETAr, MVT::i8);
return Result;
}
@@ -55692,7 +55361,7 @@ SDNode *Select_X86ISD_SETCC_i8(SDNode *N) {
// Emits: (SETSr:i8)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(15)) {
- SDNode *Result = Emit_302(N, X86::SETSr, MVT::i8);
+ SDNode *Result = Emit_303(N, X86::SETSr, MVT::i8);
return Result;
}
@@ -55700,7 +55369,7 @@ SDNode *Select_X86ISD_SETCC_i8(SDNode *N) {
// Emits: (SETNSr:i8)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(12)) {
- SDNode *Result = Emit_302(N, X86::SETNSr, MVT::i8);
+ SDNode *Result = Emit_303(N, X86::SETNSr, MVT::i8);
return Result;
}
@@ -55708,7 +55377,7 @@ SDNode *Select_X86ISD_SETCC_i8(SDNode *N) {
// Emits: (SETPr:i8)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(14)) {
- SDNode *Result = Emit_302(N, X86::SETPr, MVT::i8);
+ SDNode *Result = Emit_303(N, X86::SETPr, MVT::i8);
return Result;
}
@@ -55716,7 +55385,7 @@ SDNode *Select_X86ISD_SETCC_i8(SDNode *N) {
// Emits: (SETNPr:i8)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(11)) {
- SDNode *Result = Emit_302(N, X86::SETNPr, MVT::i8);
+ SDNode *Result = Emit_303(N, X86::SETNPr, MVT::i8);
return Result;
}
@@ -55724,7 +55393,7 @@ SDNode *Select_X86ISD_SETCC_i8(SDNode *N) {
// Emits: (SETOr:i8)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(13)) {
- SDNode *Result = Emit_302(N, X86::SETOr, MVT::i8);
+ SDNode *Result = Emit_303(N, X86::SETOr, MVT::i8);
return Result;
}
@@ -55732,7 +55401,7 @@ SDNode *Select_X86ISD_SETCC_i8(SDNode *N) {
// Emits: (SETNOr:i8)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(10)) {
- SDNode *Result = Emit_302(N, X86::SETNOr, MVT::i8);
+ SDNode *Result = Emit_303(N, X86::SETNOr, MVT::i8);
return Result;
}
}
@@ -55747,7 +55416,7 @@ SDNode *Select_X86ISD_SETCC_CARRY_i8(SDNode *N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_302(N, X86::SETB_C8r, MVT::i8);
+ SDNode *Result = Emit_303(N, X86::SETB_C8r, MVT::i8);
return Result;
}
}
@@ -55762,7 +55431,7 @@ SDNode *Select_X86ISD_SETCC_CARRY_i16(SDNode *N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_302(N, X86::SETB_C16r, MVT::i16);
+ SDNode *Result = Emit_303(N, X86::SETB_C16r, MVT::i16);
return Result;
}
}
@@ -55777,7 +55446,7 @@ SDNode *Select_X86ISD_SETCC_CARRY_i32(SDNode *N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_302(N, X86::SETB_C32r, MVT::i32);
+ SDNode *Result = Emit_303(N, X86::SETB_C32r, MVT::i32);
return Result;
}
}
@@ -55792,7 +55461,7 @@ SDNode *Select_X86ISD_SETCC_CARRY_i64(SDNode *N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_302(N, X86::SETB_C64r, MVT::i64);
+ SDNode *Result = Emit_303(N, X86::SETB_C64r, MVT::i64);
return Result;
}
}
@@ -55801,7 +55470,7 @@ SDNode *Select_X86ISD_SETCC_CARRY_i64(SDNode *N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_303(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_304(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
@@ -55822,7 +55491,7 @@ SDNode *Select_X86ISD_SHLD_i16(SDNode *N) {
// Pattern complexity = 6 cost = 1 size = 3
if (N2.getNode()->getOpcode() == ISD::Constant &&
N2.getValueType() == MVT::i8) {
- SDNode *Result = Emit_283(N, X86::SHLD16rri8, MVT::i16);
+ SDNode *Result = Emit_284(N, X86::SHLD16rri8, MVT::i16);
return Result;
}
@@ -55830,7 +55499,7 @@ SDNode *Select_X86ISD_SHLD_i16(SDNode *N) {
// Emits: (SHLD16rrCL:i16 GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 3 cost = 1 size = 3
if (N2.getValueType() == MVT::i8) {
- SDNode *Result = Emit_303(N, X86::SHLD16rrCL, MVT::i16);
+ SDNode *Result = Emit_304(N, X86::SHLD16rrCL, MVT::i16);
return Result;
}
@@ -55848,7 +55517,7 @@ SDNode *Select_X86ISD_SHLD_i32(SDNode *N) {
// Pattern complexity = 6 cost = 1 size = 3
if (N2.getNode()->getOpcode() == ISD::Constant &&
N2.getValueType() == MVT::i8) {
- SDNode *Result = Emit_283(N, X86::SHLD32rri8, MVT::i32);
+ SDNode *Result = Emit_284(N, X86::SHLD32rri8, MVT::i32);
return Result;
}
@@ -55856,7 +55525,7 @@ SDNode *Select_X86ISD_SHLD_i32(SDNode *N) {
// Emits: (SHLD32rrCL:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 3 cost = 1 size = 3
if (N2.getValueType() == MVT::i8) {
- SDNode *Result = Emit_303(N, X86::SHLD32rrCL, MVT::i32);
+ SDNode *Result = Emit_304(N, X86::SHLD32rrCL, MVT::i32);
return Result;
}
@@ -55874,7 +55543,7 @@ SDNode *Select_X86ISD_SHLD_i64(SDNode *N) {
// Pattern complexity = 6 cost = 1 size = 3
if (N2.getNode()->getOpcode() == ISD::Constant &&
N2.getValueType() == MVT::i8) {
- SDNode *Result = Emit_283(N, X86::SHLD64rri8, MVT::i64);
+ SDNode *Result = Emit_284(N, X86::SHLD64rri8, MVT::i64);
return Result;
}
@@ -55882,7 +55551,7 @@ SDNode *Select_X86ISD_SHLD_i64(SDNode *N) {
// Emits: (SHLD64rrCL:i64 GR64:i64:$src1, GR64:i64:$src2)
// Pattern complexity = 3 cost = 1 size = 3
if (N2.getValueType() == MVT::i8) {
- SDNode *Result = Emit_303(N, X86::SHLD64rrCL, MVT::i64);
+ SDNode *Result = Emit_304(N, X86::SHLD64rrCL, MVT::i64);
return Result;
}
@@ -55900,7 +55569,7 @@ SDNode *Select_X86ISD_SHRD_i16(SDNode *N) {
// Pattern complexity = 6 cost = 1 size = 3
if (N2.getNode()->getOpcode() == ISD::Constant &&
N2.getValueType() == MVT::i8) {
- SDNode *Result = Emit_283(N, X86::SHRD16rri8, MVT::i16);
+ SDNode *Result = Emit_284(N, X86::SHRD16rri8, MVT::i16);
return Result;
}
@@ -55908,7 +55577,7 @@ SDNode *Select_X86ISD_SHRD_i16(SDNode *N) {
// Emits: (SHRD16rrCL:i16 GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 3 cost = 1 size = 3
if (N2.getValueType() == MVT::i8) {
- SDNode *Result = Emit_303(N, X86::SHRD16rrCL, MVT::i16);
+ SDNode *Result = Emit_304(N, X86::SHRD16rrCL, MVT::i16);
return Result;
}
@@ -55926,7 +55595,7 @@ SDNode *Select_X86ISD_SHRD_i32(SDNode *N) {
// Pattern complexity = 6 cost = 1 size = 3
if (N2.getNode()->getOpcode() == ISD::Constant &&
N2.getValueType() == MVT::i8) {
- SDNode *Result = Emit_283(N, X86::SHRD32rri8, MVT::i32);
+ SDNode *Result = Emit_284(N, X86::SHRD32rri8, MVT::i32);
return Result;
}
@@ -55934,7 +55603,7 @@ SDNode *Select_X86ISD_SHRD_i32(SDNode *N) {
// Emits: (SHRD32rrCL:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 3 cost = 1 size = 3
if (N2.getValueType() == MVT::i8) {
- SDNode *Result = Emit_303(N, X86::SHRD32rrCL, MVT::i32);
+ SDNode *Result = Emit_304(N, X86::SHRD32rrCL, MVT::i32);
return Result;
}
@@ -55952,7 +55621,7 @@ SDNode *Select_X86ISD_SHRD_i64(SDNode *N) {
// Pattern complexity = 6 cost = 1 size = 3
if (N2.getNode()->getOpcode() == ISD::Constant &&
N2.getValueType() == MVT::i8) {
- SDNode *Result = Emit_283(N, X86::SHRD64rri8, MVT::i64);
+ SDNode *Result = Emit_284(N, X86::SHRD64rri8, MVT::i64);
return Result;
}
@@ -55960,7 +55629,7 @@ SDNode *Select_X86ISD_SHRD_i64(SDNode *N) {
// Emits: (SHRD64rrCL:i64 GR64:i64:$src1, GR64:i64:$src2)
// Pattern complexity = 3 cost = 1 size = 3
if (N2.getValueType() == MVT::i8) {
- SDNode *Result = Emit_303(N, X86::SHRD64rrCL, MVT::i64);
+ SDNode *Result = Emit_304(N, X86::SHRD64rrCL, MVT::i64);
return Result;
}
@@ -55968,13 +55637,13 @@ SDNode *Select_X86ISD_SHRD_i64(SDNode *N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_304(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_305(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
return CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::i32, N0, N0);
}
SDNode *Select_X86ISD_SMUL_i16(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
@@ -56056,9 +55725,6 @@ SDNode *Select_X86ISD_SMUL_i16(SDNode *N) {
}
}
}
- }
- {
- SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
// Pattern: (X86smul_flag:i16 GR16:i16:$src1, 2:i16)
@@ -56069,7 +55735,7 @@ SDNode *Select_X86ISD_SMUL_i16(SDNode *N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_304(N, X86::ADD16rr, MVT::i16);
+ SDNode *Result = Emit_305(N, X86::ADD16rr, MVT::i16);
return Result;
}
}
@@ -56100,7 +55766,7 @@ SDNode *Select_X86ISD_SMUL_i16(SDNode *N) {
}
SDNode *Select_X86ISD_SMUL_i32(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
@@ -56182,9 +55848,6 @@ SDNode *Select_X86ISD_SMUL_i32(SDNode *N) {
}
}
}
- }
- {
- SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
// Pattern: (X86smul_flag:i32 GR32:i32:$src1, 2:i32)
@@ -56195,7 +55858,7 @@ SDNode *Select_X86ISD_SMUL_i32(SDNode *N) {
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_304(N, X86::ADD32rr, MVT::i32);
+ SDNode *Result = Emit_305(N, X86::ADD32rr, MVT::i32);
return Result;
}
}
@@ -56226,7 +55889,7 @@ SDNode *Select_X86ISD_SMUL_i32(SDNode *N) {
}
SDNode *Select_X86ISD_SMUL_i64(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
@@ -56313,9 +55976,6 @@ SDNode *Select_X86ISD_SMUL_i64(SDNode *N) {
}
}
}
- }
- {
- SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::Constant) {
@@ -56345,13 +56005,13 @@ SDNode *Select_X86ISD_SMUL_i64(SDNode *N) {
}
SDNode *Select_X86ISD_SUB_i8(SDNode *N) {
-
- // Pattern: (X86sub_flag:i8 GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>)
- // Emits: (SUB8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
+
+ // Pattern: (X86sub_flag:i8 GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>)
+ // Emits: (SUB8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
@@ -56371,14 +56031,10 @@ SDNode *Select_X86ISD_SUB_i8(SDNode *N) {
}
}
}
- }
- // Pattern: (X86sub_flag:i8 GR8:i8:$src1, (imm:i8):$src2)
- // Emits: (SUB8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
+ // Pattern: (X86sub_flag:i8 GR8:i8:$src1, (imm:i8):$src2)
+ // Emits: (SUB8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_3(N, X86::SUB8ri, MVT::i8);
return Result;
@@ -56393,13 +56049,13 @@ SDNode *Select_X86ISD_SUB_i8(SDNode *N) {
}
SDNode *Select_X86ISD_SUB_i16(SDNode *N) {
-
- // Pattern: (X86sub_flag:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>)
- // Emits: (SUB16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
+
+ // Pattern: (X86sub_flag:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>)
+ // Emits: (SUB16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
@@ -56418,10 +56074,6 @@ SDNode *Select_X86ISD_SUB_i16(SDNode *N) {
}
}
}
- }
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (X86sub_flag:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
@@ -56448,13 +56100,13 @@ SDNode *Select_X86ISD_SUB_i16(SDNode *N) {
}
SDNode *Select_X86ISD_SUB_i32(SDNode *N) {
-
- // Pattern: (X86sub_flag:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
- // Emits: (SUB32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
+
+ // Pattern: (X86sub_flag:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
+ // Emits: (SUB32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
@@ -56473,10 +56125,6 @@ SDNode *Select_X86ISD_SUB_i32(SDNode *N) {
}
}
}
- }
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (X86sub_flag:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
@@ -56503,13 +56151,13 @@ SDNode *Select_X86ISD_SUB_i32(SDNode *N) {
}
SDNode *Select_X86ISD_SUB_i64(SDNode *N) {
-
- // Pattern: (X86sub_flag:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
- // Emits: (SUB64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
+
+ // Pattern: (X86sub_flag:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
+ // Emits: (SUB64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
@@ -56529,10 +56177,6 @@ SDNode *Select_X86ISD_SUB_i64(SDNode *N) {
}
}
}
- }
- {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (X86sub_flag:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
@@ -56560,7 +56204,7 @@ SDNode *Select_X86ISD_SUB_i64(SDNode *N) {
return Result;
}
-DISABLE_INLINE SDNode *Emit_305(SDNode *N, unsigned Opc0, unsigned NumInputRootOps) {
+DISABLE_INLINE SDNode *Emit_306(SDNode *N, unsigned Opc0, unsigned NumInputRootOps) {
SDValue Chain = N->getOperand(0);
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
@@ -56592,7 +56236,7 @@ SDNode *Select_X86ISD_TC_RETURN(SDNode *N) {
SDValue N2 = N->getOperand(2);
if (N2.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_305(N, X86::TCRETURNdi64, 2);
+ SDNode *Result = Emit_306(N, X86::TCRETURNdi64, 2);
return Result;
}
}
@@ -56604,7 +56248,7 @@ SDNode *Select_X86ISD_TC_RETURN(SDNode *N) {
SDValue N2 = N->getOperand(2);
if (N2.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_305(N, X86::TCRETURNdi64, 2);
+ SDNode *Result = Emit_306(N, X86::TCRETURNdi64, 2);
return Result;
}
}
@@ -56616,7 +56260,7 @@ SDNode *Select_X86ISD_TC_RETURN(SDNode *N) {
SDValue N2 = N->getOperand(2);
if (N2.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_305(N, X86::TCRETURNdi, 2);
+ SDNode *Result = Emit_306(N, X86::TCRETURNdi, 2);
return Result;
}
}
@@ -56628,7 +56272,7 @@ SDNode *Select_X86ISD_TC_RETURN(SDNode *N) {
SDValue N2 = N->getOperand(2);
if (N2.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_305(N, X86::TCRETURNdi, 2);
+ SDNode *Result = Emit_306(N, X86::TCRETURNdi, 2);
return Result;
}
}
@@ -56639,7 +56283,7 @@ SDNode *Select_X86ISD_TC_RETURN(SDNode *N) {
// Emits: (TCRETURNri64:isVoid GR64:i64:$dst, (imm:i32):$off)
// Pattern complexity = 6 cost = 1 size = 3
if (N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_305(N, X86::TCRETURNri64, 2);
+ SDNode *Result = Emit_306(N, X86::TCRETURNri64, 2);
return Result;
}
@@ -56647,7 +56291,7 @@ SDNode *Select_X86ISD_TC_RETURN(SDNode *N) {
// Emits: (TCRETURNri:isVoid GR32:i32:$dst, (imm:i32):$off)
// Pattern complexity = 6 cost = 1 size = 3
if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_305(N, X86::TCRETURNri, 2);
+ SDNode *Result = Emit_306(N, X86::TCRETURNri, 2);
return Result;
}
}
@@ -56656,7 +56300,7 @@ SDNode *Select_X86ISD_TC_RETURN(SDNode *N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_306(SDNode *N, unsigned Opc0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3) {
+DISABLE_INLINE SDNode *Emit_307(SDNode *N, unsigned Opc0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3) {
SDValue Chain = N->getOperand(0);
SDValue N1 = N->getOperand(1);
bool HasInFlag = (N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag);
@@ -56693,7 +56337,7 @@ SDNode *Select_X86ISD_TLSADDR(SDNode *N) {
SDValue CPTmpN1_3;
if (SelectTLSADDRAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3) &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_306(N, X86::TLS_addr32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3);
+ SDNode *Result = Emit_307(N, X86::TLS_addr32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3);
return Result;
}
}
@@ -56710,7 +56354,7 @@ SDNode *Select_X86ISD_TLSADDR(SDNode *N) {
SDValue CPTmpN1_3;
if (SelectTLSADDRAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3) &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_306(N, X86::TLS_addr64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3);
+ SDNode *Result = Emit_307(N, X86::TLS_addr64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3);
return Result;
}
}
@@ -56720,58 +56364,56 @@ SDNode *Select_X86ISD_TLSADDR(SDNode *N) {
}
SDNode *Select_X86ISD_UCOMI(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
- // Pattern: (X86ucomi:isVoid VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (Int_UCOMISSrm:isVoid VR128:v4f32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
- N0.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_276(N, X86::Int_UCOMISSrm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
+ // Pattern: (X86ucomi:isVoid VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (Int_UCOMISSrm:isVoid VR128:v4f32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
+ N0.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_277(N, X86::Int_UCOMISSrm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
}
}
}
+ }
- // Pattern: (X86ucomi:isVoid VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (Int_UCOMISDrm:isVoid VR128:v2f64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- if (N1.getNode()->getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
- SDValue Chain1 = N1.getNode()->getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getNode()->getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
- N0.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_276(N, X86::Int_UCOMISDrm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
- return Result;
- }
+ // Pattern: (X86ucomi:isVoid VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (Int_UCOMISDrm:isVoid VR128:v2f64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
+ N0.getValueType() == MVT::v2f64) {
+ SDNode *Result = Emit_277(N, X86::Int_UCOMISDrm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
}
}
}
@@ -56784,7 +56426,7 @@ SDNode *Select_X86ISD_UCOMI(SDNode *N) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_253(N, X86::Int_UCOMISSrr);
+ SDNode *Result = Emit_254(N, X86::Int_UCOMISSrr);
return Result;
}
}
@@ -56796,7 +56438,7 @@ SDNode *Select_X86ISD_UCOMI(SDNode *N) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_253(N, X86::Int_UCOMISDrr);
+ SDNode *Result = Emit_254(N, X86::Int_UCOMISDrr);
return Result;
}
}
@@ -56805,7 +56447,7 @@ SDNode *Select_X86ISD_UCOMI(SDNode *N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_307(SDNode *N, unsigned Opc0, unsigned NumInputRootOps) {
+DISABLE_INLINE SDNode *Emit_308(SDNode *N, unsigned Opc0, unsigned NumInputRootOps) {
SDValue Chain = N->getOperand(0);
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
@@ -56829,7 +56471,7 @@ SDNode *Select_X86ISD_VASTART_SAVE_XMM_REGS(SDNode *N) {
if (N2.getNode()->getOpcode() == ISD::Constant) {
SDValue N3 = N->getOperand(3);
if (N3.getNode()->getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_307(N, X86::VASTART_SAVE_XMM_REGS, 3);
+ SDNode *Result = Emit_308(N, X86::VASTART_SAVE_XMM_REGS, 3);
return Result;
}
}
@@ -56857,7 +56499,7 @@ SDNode *Select_X86ISD_VSHL_v2i64(SDNode *N) {
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_289(N, X86::PSLLDQri, MVT::v2i64);
+ SDNode *Result = Emit_290(N, X86::PSLLDQri, MVT::v2i64);
return Result;
}
}
@@ -56885,7 +56527,7 @@ SDNode *Select_X86ISD_VSRL_v2i64(SDNode *N) {
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_289(N, X86::PSRLDQri, MVT::v2i64);
+ SDNode *Result = Emit_290(N, X86::PSRLDQri, MVT::v2i64);
return Result;
}
}
@@ -56894,7 +56536,7 @@ SDNode *Select_X86ISD_VSRL_v2i64(SDNode *N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_308(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
+DISABLE_INLINE SDNode *Emit_309(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
SDValue Chain = N->getOperand(0);
SDValue N1 = N->getOperand(1);
SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain };
@@ -56909,7 +56551,7 @@ SDNode *Select_X86ISD_VZEXT_LOAD_v2i64(SDNode *N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_308(N, X86::MOVZQI2PQIrm, MVT::v2i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_309(N, X86::MOVZQI2PQIrm, MVT::v2i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
@@ -56926,7 +56568,7 @@ SDNode *Select_X86ISD_VZEXT_LOAD_v2f64(SDNode *N) {
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_308(N, X86::MOVZSD2PDrm, MVT::v2f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_309(N, X86::MOVZSD2PDrm, MVT::v2f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
@@ -56934,7 +56576,7 @@ SDNode *Select_X86ISD_VZEXT_LOAD_v2f64(SDNode *N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_309(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
+DISABLE_INLINE SDNode *Emit_310(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
SDValue N0 = N->getOperand(0);
SDValue N00 = N0.getNode()->getOperand(0);
SDValue Chain00 = N00.getNode()->getOperand(0);
@@ -56947,47 +56589,47 @@ DISABLE_INLINE SDNode *Emit_309(SDNode *N, unsigned Opc0, MVT::SimpleValueType V
ReplaceUses(SDValue(N00.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_310(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+DISABLE_INLINE SDNode *Emit_311(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
SDValue N0 = N->getOperand(0);
SDValue Tmp1(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0), 0);
return CurDAG->SelectNodeTo(N, Opc1, VT1, N0, Tmp1);
}
SDNode *Select_X86ISD_VZEXT_MOVL_v2i32(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
- // Pattern: (X86vzmovl:v2i32 (scalar_to_vector:v2i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>))
- // Emits: (MMX_MOVZDI2PDIrm:v2i32 addr:iPTR:$src)
- // Pattern complexity = 48 cost = 1 size = 3
- if ((Subtarget->hasMMX())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N0.hasOneUse()) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::LOAD &&
- N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
- SDValue Chain00 = N00.getNode()->getOperand(0);
- if (Predicate_unindexedload(N00.getNode()) &&
- Predicate_loadi32(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4) &&
- N00.getValueType() == MVT::i32) {
- SDNode *Result = Emit_309(N, X86::MMX_MOVZDI2PDIrm, MVT::v2i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
- }
+ // Pattern: (X86vzmovl:v2i32 (scalar_to_vector:v2i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>))
+ // Emits: (MMX_MOVZDI2PDIrm:v2i32 addr:iPTR:$src)
+ // Pattern complexity = 48 cost = 1 size = 3
+ if ((Subtarget->hasMMX())) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N0.hasOneUse()) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::LOAD &&
+ N00.hasOneUse() &&
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
+ SDValue Chain00 = N00.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N00.getNode()) &&
+ Predicate_loadi32(N00.getNode())) {
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4) &&
+ N00.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_310(N, X86::MMX_MOVZDI2PDIrm, MVT::v2i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (X86vzmovl:v2i32 (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MMX_MOVZDI2PDIrm:v2i32 addr:iPTR:$src)
- // Pattern complexity = 48 cost = 1 size = 3
+ // Pattern: (X86vzmovl:v2i32 (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MMX_MOVZDI2PDIrm:v2i32 addr:iPTR:$src)
+ // Pattern complexity = 48 cost = 1 size = 3
+ {
SDValue N0 = N->getOperand(0);
if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N0.hasOneUse()) {
@@ -57006,7 +56648,7 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v2i32(SDNode *N) {
SDValue CPTmpN001_4;
if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4) &&
N00.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_309(N, X86::MMX_MOVZDI2PDIrm, MVT::v2i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_310(N, X86::MMX_MOVZDI2PDIrm, MVT::v2i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
}
@@ -57031,47 +56673,47 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v2i32(SDNode *N) {
// Pattern: (X86vzmovl:v2i32 VR64:v2i32:$src)
// Emits: (MMX_PUNPCKLDQrr:v2i32 VR64:v8i8:$src, (MMX_V_SET0:v8i8))
// Pattern complexity = 18 cost = 2 size = 6
- SDNode *Result = Emit_310(N, X86::MMX_V_SET0, X86::MMX_PUNPCKLDQrr, MVT::v8i8, MVT::v2i32);
+ SDNode *Result = Emit_311(N, X86::MMX_V_SET0, X86::MMX_PUNPCKLDQrr, MVT::v8i8, MVT::v2i32);
return Result;
}
-DISABLE_INLINE SDNode *Emit_311(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+DISABLE_INLINE SDNode *Emit_312(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
SDValue N0 = N->getOperand(0);
SDValue Tmp0(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0), 0);
return CurDAG->SelectNodeTo(N, Opc1, VT1, Tmp0, N0);
}
SDNode *Select_X86ISD_VZEXT_MOVL_v4i32(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
- // Pattern: (X86vzmovl:v4i32 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>))
- // Emits: (MOVZDI2PDIrm:v4i32 addr:iPTR:$src)
- // Pattern complexity = 48 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N0.hasOneUse()) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::LOAD &&
- N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
- SDValue Chain00 = N00.getNode()->getOperand(0);
- if (Predicate_unindexedload(N00.getNode()) &&
- Predicate_loadi32(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4) &&
- N00.getValueType() == MVT::i32) {
- SDNode *Result = Emit_309(N, X86::MOVZDI2PDIrm, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
- }
+ // Pattern: (X86vzmovl:v4i32 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>))
+ // Emits: (MOVZDI2PDIrm:v4i32 addr:iPTR:$src)
+ // Pattern complexity = 48 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N0.hasOneUse()) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::LOAD &&
+ N00.hasOneUse() &&
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
+ SDValue Chain00 = N00.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N00.getNode()) &&
+ Predicate_loadi32(N00.getNode())) {
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4) &&
+ N00.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_310(N, X86::MOVZDI2PDIrm, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
}
}
}
}
+ }
+ {
SDValue N0 = N->getOperand(0);
if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N0.hasOneUse()) {
@@ -57094,7 +56736,7 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v4i32(SDNode *N) {
// Emits: (MOVZDI2PDIrm:v4i32 addr:iPTR:$src)
// Pattern complexity = 48 cost = 1 size = 3
if (N00.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_309(N, X86::MOVZDI2PDIrm, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_310(N, X86::MOVZDI2PDIrm, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
@@ -57102,7 +56744,7 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v4i32(SDNode *N) {
// Emits: (MOVZDI2PDIrm:v4i32 addr:iPTR:$src)
// Pattern complexity = 48 cost = 1 size = 3
if (N00.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_309(N, X86::MOVZDI2PDIrm, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_310(N, X86::MOVZDI2PDIrm, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
}
@@ -57150,7 +56792,7 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v4i32(SDNode *N) {
// Emits: (MOVLPSrr:v4i32 (V_SET0:v16i8), VR128:v16i8:$src)
// Pattern complexity = 18 cost = 2 size = 6
if ((Subtarget->hasSSE1())) {
- SDNode *Result = Emit_311(N, X86::V_SET0, X86::MOVLPSrr, MVT::v16i8, MVT::v4i32);
+ SDNode *Result = Emit_312(N, X86::V_SET0, X86::MOVLPSrr, MVT::v16i8, MVT::v4i32);
return Result;
}
@@ -57159,105 +56801,105 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v4i32(SDNode *N) {
}
SDNode *Select_X86ISD_VZEXT_MOVL_v2i64(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
- // Pattern: (X86vzmovl:v2i64 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>))
- // Emits: (MOVZQI2PQIrm:v2i64 addr:iPTR:$src)
- // Pattern complexity = 48 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N0.hasOneUse()) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::LOAD &&
- N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
- SDValue Chain00 = N00.getNode()->getOperand(0);
- if (Predicate_unindexedload(N00.getNode()) &&
- Predicate_load(N00.getNode()) &&
- Predicate_loadi64(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4) &&
- N00.getValueType() == MVT::i64) {
- SDNode *Result = Emit_309(N, X86::MOVZQI2PQIrm, MVT::v2i64, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
- }
+ // Pattern: (X86vzmovl:v2i64 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>))
+ // Emits: (MOVZQI2PQIrm:v2i64 addr:iPTR:$src)
+ // Pattern complexity = 48 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N0.hasOneUse()) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::LOAD &&
+ N00.hasOneUse() &&
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
+ SDValue Chain00 = N00.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N00.getNode()) &&
+ Predicate_load(N00.getNode()) &&
+ Predicate_loadi64(N00.getNode())) {
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4) &&
+ N00.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_310(N, X86::MOVZQI2PQIrm, MVT::v2i64, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
}
}
}
}
- {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
- N0.hasOneUse()) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::LOAD &&
- N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
- SDValue Chain00 = N00.getNode()->getOperand(0);
- if (Predicate_unindexedload(N00.getNode()) &&
- Predicate_load(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
+ }
+ {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N0.hasOneUse()) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::LOAD &&
+ N00.hasOneUse() &&
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
+ SDValue Chain00 = N00.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N00.getNode()) &&
+ Predicate_load(N00.getNode())) {
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- // Pattern: (X86vzmovl:v2i64 (bitconvert:v2i64 (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MOVZQI2PQIrm:v2i64 addr:iPTR:$src)
- // Pattern complexity = 48 cost = 1 size = 3
- if (N00.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_309(N, X86::MOVZQI2PQIrm, MVT::v2i64, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
- }
+ // Pattern: (X86vzmovl:v2i64 (bitconvert:v2i64 (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MOVZQI2PQIrm:v2i64 addr:iPTR:$src)
+ // Pattern complexity = 48 cost = 1 size = 3
+ if (N00.getValueType() == MVT::v4f32) {
+ SDNode *Result = Emit_310(N, X86::MOVZQI2PQIrm, MVT::v2i64, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
+ }
- // Pattern: (X86vzmovl:v2i64 (bitconvert:v2i64 (ld:v4i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
- // Emits: (MOVZPQILo2PQIrm:v2i64 addr:iPTR:$src)
- // Pattern complexity = 48 cost = 1 size = 3
- if (N00.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_309(N, X86::MOVZPQILo2PQIrm, MVT::v2i64, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
- }
+ // Pattern: (X86vzmovl:v2i64 (bitconvert:v2i64 (ld:v4i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Emits: (MOVZPQILo2PQIrm:v2i64 addr:iPTR:$src)
+ // Pattern complexity = 48 cost = 1 size = 3
+ if (N00.getValueType() == MVT::v4i32) {
+ SDNode *Result = Emit_310(N, X86::MOVZPQILo2PQIrm, MVT::v2i64, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
}
}
}
}
}
+ }
- // Pattern: (X86vzmovl:v2i64 (ld:v2i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (MOVZPQILo2PQIrm:v2i64 addr:iPTR:$src)
- // Pattern complexity = 45 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::LOAD &&
- N0.hasOneUse()) {
- SDValue Chain0 = N0.getNode()->getOperand(0);
- if (Predicate_unindexedload(N0.getNode()) &&
- Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getNode()->getOperand(1);
- SDValue CPTmpN01_0;
- SDValue CPTmpN01_1;
- SDValue CPTmpN01_2;
- SDValue CPTmpN01_3;
- SDValue CPTmpN01_4;
- if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_79(N, X86::MOVZPQILo2PQIrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
+ // Pattern: (X86vzmovl:v2i64 (ld:v2i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (MOVZPQILo2PQIrm:v2i64 addr:iPTR:$src)
+ // Pattern complexity = 45 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse()) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_79(N, X86::MOVZPQILo2PQIrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
}
}
}
+ }
- // Pattern: (X86vzmovl:v2i64 (ld:v2i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (MOVZQI2PQIrm:v2i64 addr:iPTR:$src)
- // Pattern complexity = 45 cost = 1 size = 3
+ // Pattern: (X86vzmovl:v2i64 (ld:v2i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (MOVZQI2PQIrm:v2i64 addr:iPTR:$src)
+ // Pattern complexity = 45 cost = 1 size = 3
+ {
SDValue N0 = N->getOperand(0);
if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse()) {
@@ -57304,49 +56946,49 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v2i64(SDNode *N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_312(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+DISABLE_INLINE SDNode *Emit_313(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
SDValue N0 = N->getOperand(0);
SDValue N00 = N0.getNode()->getOperand(0);
SDValue Tmp0(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0), 0);
return CurDAG->SelectNodeTo(N, Opc1, VT1, Tmp0, N00);
}
SDNode *Select_X86ISD_VZEXT_MOVL_v4f32(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
- // Pattern: (X86vzmovl:v4f32 (scalar_to_vector:v4f32 (ld:f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>))
- // Emits: (MOVZSS2PSrm:v4f32 addr:iPTR:$src)
- // Pattern complexity = 48 cost = 1 size = 3
- if ((Subtarget->hasSSE1())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N0.hasOneUse()) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::LOAD &&
- N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
- SDValue Chain00 = N00.getNode()->getOperand(0);
- if (Predicate_unindexedload(N00.getNode()) &&
- Predicate_load(N00.getNode()) &&
- Predicate_loadf32(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4) &&
- N00.getValueType() == MVT::f32) {
- SDNode *Result = Emit_309(N, X86::MOVZSS2PSrm, MVT::v4f32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
- }
+ // Pattern: (X86vzmovl:v4f32 (scalar_to_vector:v4f32 (ld:f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>))
+ // Emits: (MOVZSS2PSrm:v4f32 addr:iPTR:$src)
+ // Pattern complexity = 48 cost = 1 size = 3
+ if ((Subtarget->hasSSE1())) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N0.hasOneUse()) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::LOAD &&
+ N00.hasOneUse() &&
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
+ SDValue Chain00 = N00.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N00.getNode()) &&
+ Predicate_load(N00.getNode()) &&
+ Predicate_loadf32(N00.getNode())) {
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4) &&
+ N00.getValueType() == MVT::f32) {
+ SDNode *Result = Emit_310(N, X86::MOVZSS2PSrm, MVT::v4f32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
}
}
}
}
+ }
- // Pattern: (X86vzmovl:v4f32 (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
- // Emits: (MOVZSS2PSrm:v4f32 addr:iPTR:$src)
- // Pattern complexity = 25 cost = 1 size = 3
+ // Pattern: (X86vzmovl:v4f32 (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (MOVZSS2PSrm:v4f32 addr:iPTR:$src)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
SDValue N0 = N->getOperand(0);
if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse()) {
@@ -57376,7 +57018,7 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v4f32(SDNode *N) {
if (N0.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR) {
SDValue N00 = N0.getNode()->getOperand(0);
if (N00.getValueType() == MVT::f32) {
- SDNode *Result = Emit_312(N, X86::V_SET0, X86::MOVLSS2PSrr, MVT::v16i8, MVT::v4f32);
+ SDNode *Result = Emit_313(N, X86::V_SET0, X86::MOVLSS2PSrr, MVT::v16i8, MVT::v4f32);
return Result;
}
}
@@ -57385,7 +57027,7 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v4f32(SDNode *N) {
// Pattern: (X86vzmovl:v4f32 VR128:v4f32:$src)
// Emits: (MOVLPSrr:v4f32 (V_SET0:v16i8), VR128:v16i8:$src)
// Pattern complexity = 18 cost = 2 size = 6
- SDNode *Result = Emit_311(N, X86::V_SET0, X86::MOVLPSrr, MVT::v16i8, MVT::v4f32);
+ SDNode *Result = Emit_312(N, X86::V_SET0, X86::MOVLPSrr, MVT::v16i8, MVT::v4f32);
return Result;
}
@@ -57394,38 +57036,38 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v4f32(SDNode *N) {
}
SDNode *Select_X86ISD_VZEXT_MOVL_v2f64(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
- // Pattern: (X86vzmovl:v2f64 (scalar_to_vector:v2f64 (ld:f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>))
- // Emits: (MOVZSD2PDrm:v2f64 addr:iPTR:$src)
- // Pattern complexity = 48 cost = 1 size = 3
- if ((Subtarget->hasSSE2())) {
- SDValue N0 = N->getOperand(0);
- if (N0.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
- N0.hasOneUse()) {
- SDValue N00 = N0.getNode()->getOperand(0);
- if (N00.getNode()->getOpcode() == ISD::LOAD &&
- N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
- SDValue Chain00 = N00.getNode()->getOperand(0);
- if (Predicate_unindexedload(N00.getNode()) &&
- Predicate_load(N00.getNode()) &&
- Predicate_loadf64(N00.getNode())) {
- SDValue N001 = N00.getNode()->getOperand(1);
- SDValue CPTmpN001_0;
- SDValue CPTmpN001_1;
- SDValue CPTmpN001_2;
- SDValue CPTmpN001_3;
- SDValue CPTmpN001_4;
- if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4) &&
- N00.getValueType() == MVT::f64) {
- SDNode *Result = Emit_309(N, X86::MOVZSD2PDrm, MVT::v2f64, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
- return Result;
- }
+ // Pattern: (X86vzmovl:v2f64 (scalar_to_vector:v2f64 (ld:f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>))
+ // Emits: (MOVZSD2PDrm:v2f64 addr:iPTR:$src)
+ // Pattern complexity = 48 cost = 1 size = 3
+ if ((Subtarget->hasSSE2())) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N0.hasOneUse()) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::LOAD &&
+ N00.hasOneUse() &&
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
+ SDValue Chain00 = N00.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N00.getNode()) &&
+ Predicate_load(N00.getNode()) &&
+ Predicate_loadf64(N00.getNode())) {
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue CPTmpN001_0;
+ SDValue CPTmpN001_1;
+ SDValue CPTmpN001_2;
+ SDValue CPTmpN001_3;
+ SDValue CPTmpN001_4;
+ if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4) &&
+ N00.getValueType() == MVT::f64) {
+ SDNode *Result = Emit_310(N, X86::MOVZSD2PDrm, MVT::v2f64, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ return Result;
}
}
}
}
+ }
+ {
SDValue N0 = N->getOperand(0);
// Pattern: (X86vzmovl:v2f64 (bitconvert:v2f64 (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
@@ -57448,7 +57090,7 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v2f64(SDNode *N) {
SDValue CPTmpN001_4;
if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4) &&
N00.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_309(N, X86::MOVZSD2PDrm, MVT::v2f64, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_310(N, X86::MOVZSD2PDrm, MVT::v2f64, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
}
@@ -57486,7 +57128,7 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v2f64(SDNode *N) {
if (N0.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR) {
SDValue N00 = N0.getNode()->getOperand(0);
if (N00.getValueType() == MVT::f64) {
- SDNode *Result = Emit_312(N, X86::V_SET0, X86::MOVLSD2PDrr, MVT::v16i8, MVT::v2f64);
+ SDNode *Result = Emit_313(N, X86::V_SET0, X86::MOVLSD2PDrr, MVT::v16i8, MVT::v2f64);
return Result;
}
}
@@ -57708,7 +57350,7 @@ SDNode *Select_X86ISD_WrapperRIP_i64(SDNode *N) {
}
SDNode *Select_X86ISD_XOR_i8(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
// Pattern: (X86xor_flag:i8 GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>)
@@ -57759,13 +57401,10 @@ SDNode *Select_X86ISD_XOR_i8(SDNode *N) {
}
}
}
- }
- // Pattern: (X86xor_flag:i8 GR8:i8:$src1, (imm:i8):$src2)
- // Emits: (XOR8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
- // Pattern complexity = 6 cost = 1 size = 3
- {
- SDValue N0 = N->getOperand(0);
+ // Pattern: (X86xor_flag:i8 GR8:i8:$src1, (imm:i8):$src2)
+ // Emits: (XOR8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
+ // Pattern complexity = 6 cost = 1 size = 3
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_3(N, X86::XOR8ri, MVT::i8);
@@ -57781,7 +57420,7 @@ SDNode *Select_X86ISD_XOR_i8(SDNode *N) {
}
SDNode *Select_X86ISD_XOR_i16(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
// Pattern: (X86xor_flag:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>)
@@ -57830,9 +57469,6 @@ SDNode *Select_X86ISD_XOR_i16(SDNode *N) {
}
}
}
- }
- {
- SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::Constant) {
@@ -57860,7 +57496,7 @@ SDNode *Select_X86ISD_XOR_i16(SDNode *N) {
}
SDNode *Select_X86ISD_XOR_i32(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
// Pattern: (X86xor_flag:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
@@ -57909,9 +57545,6 @@ SDNode *Select_X86ISD_XOR_i32(SDNode *N) {
}
}
}
- }
- {
- SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::Constant) {
@@ -57939,7 +57572,7 @@ SDNode *Select_X86ISD_XOR_i32(SDNode *N) {
}
SDNode *Select_X86ISD_XOR_i64(SDNode *N) {
- if (OptLevel != CodeGenOpt::None) {
+ {
SDValue N0 = N->getOperand(0);
// Pattern: (X86xor_flag:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
@@ -57990,9 +57623,6 @@ SDNode *Select_X86ISD_XOR_i64(SDNode *N) {
}
}
}
- }
- {
- SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::Constant) {
diff --git a/libclamav/c++/X86GenInstrInfo.inc b/libclamav/c++/X86GenInstrInfo.inc
index 85b6478..a352932 100644
--- a/libclamav/c++/X86GenInstrInfo.inc
+++ b/libclamav/c++/X86GenInstrInfo.inc
@@ -41,31 +41,38 @@ static const unsigned ImplicitList23[] = { X86::FP0, X86::FP1, X86::FP2, X86::FP
static const unsigned ImplicitList24[] = { X86::ST0, 0 };
static const unsigned ImplicitList25[] = { X86::ST1, 0 };
static const unsigned ImplicitList26[] = { X86::DX, 0 };
-static const unsigned ImplicitList27[] = { X86::AH, 0 };
-static const unsigned ImplicitList28[] = { X86::AX, X86::EFLAGS, 0 };
-static const unsigned ImplicitList29[] = { X86::EAX, X86::EFLAGS, 0 };
-static const unsigned ImplicitList30[] = { X86::RAX, X86::EFLAGS, 0 };
-static const unsigned ImplicitList31[] = { X86::AL, X86::EFLAGS, 0 };
-static const unsigned ImplicitList32[] = { X86::EBP, X86::ESP, 0 };
-static const unsigned ImplicitList33[] = { X86::RBP, X86::RSP, 0 };
-static const unsigned ImplicitList34[] = { X86::EDI, 0 };
-static const unsigned ImplicitList35[] = { X86::RDI, 0 };
-static const unsigned ImplicitList36[] = { X86::DX, X86::AX, 0 };
-static const unsigned ImplicitList37[] = { X86::DX, X86::EAX, 0 };
-static const unsigned ImplicitList38[] = { X86::DX, X86::AL, 0 };
-static const unsigned ImplicitList39[] = { X86::ECX, X86::EFLAGS, 0 };
-static const unsigned ImplicitList40[] = { X86::XMM0, X86::EFLAGS, 0 };
-static const unsigned ImplicitList41[] = { X86::CL, 0 };
-static const unsigned ImplicitList42[] = { X86::ECX, X86::EDI, X86::ESI, 0 };
-static const unsigned ImplicitList43[] = { X86::RCX, X86::RDI, X86::RSI, 0 };
-static const unsigned ImplicitList44[] = { X86::AL, X86::ECX, X86::EDI, 0 };
-static const unsigned ImplicitList45[] = { X86::ECX, X86::EDI, 0 };
-static const unsigned ImplicitList46[] = { X86::EAX, X86::ECX, X86::EDI, 0 };
-static const unsigned ImplicitList47[] = { X86::RAX, X86::RCX, X86::RDI, 0 };
-static const unsigned ImplicitList48[] = { X86::RCX, X86::RDI, 0 };
-static const unsigned ImplicitList49[] = { X86::AX, X86::ECX, X86::EDI, 0 };
+static const unsigned ImplicitList27[] = { X86::ECX, 0 };
+static const unsigned ImplicitList28[] = { X86::AH, 0 };
+static const unsigned ImplicitList29[] = { X86::AX, X86::EFLAGS, 0 };
+static const unsigned ImplicitList30[] = { X86::EAX, X86::EFLAGS, 0 };
+static const unsigned ImplicitList31[] = { X86::RAX, X86::EFLAGS, 0 };
+static const unsigned ImplicitList32[] = { X86::AL, X86::EFLAGS, 0 };
+static const unsigned ImplicitList33[] = { X86::EBP, X86::ESP, 0 };
+static const unsigned ImplicitList34[] = { X86::RBP, X86::RSP, 0 };
+static const unsigned ImplicitList35[] = { X86::EDI, 0 };
+static const unsigned ImplicitList36[] = { X86::RDI, 0 };
+static const unsigned ImplicitList37[] = { X86::EDI, X86::ESI, X86::EFLAGS, 0 };
+static const unsigned ImplicitList38[] = { X86::EDI, X86::ESI, 0 };
+static const unsigned ImplicitList39[] = { X86::DX, X86::AX, 0 };
+static const unsigned ImplicitList40[] = { X86::DX, X86::EAX, 0 };
+static const unsigned ImplicitList41[] = { X86::DX, X86::AL, 0 };
+static const unsigned ImplicitList42[] = { X86::ECX, X86::EFLAGS, 0 };
+static const unsigned ImplicitList43[] = { X86::XMM0, X86::EFLAGS, 0 };
+static const unsigned ImplicitList44[] = { X86::CL, 0 };
+static const unsigned ImplicitList45[] = { X86::RAX, X86::RCX, X86::RDX, 0 };
+static const unsigned ImplicitList46[] = { X86::ECX, X86::EDI, X86::ESI, 0 };
+static const unsigned ImplicitList47[] = { X86::RCX, X86::RDI, X86::RSI, 0 };
+static const unsigned ImplicitList48[] = { X86::AL, X86::ECX, X86::EDI, 0 };
+static const unsigned ImplicitList49[] = { X86::ECX, X86::EDI, 0 };
+static const unsigned ImplicitList50[] = { X86::EAX, X86::ECX, X86::EDI, 0 };
+static const unsigned ImplicitList51[] = { X86::RAX, X86::RCX, X86::RDI, 0 };
+static const unsigned ImplicitList52[] = { X86::RCX, X86::RDI, 0 };
+static const unsigned ImplicitList53[] = { X86::AX, X86::ECX, X86::EDI, 0 };
+static const unsigned ImplicitList54[] = { X86::AL, X86::EDI, X86::EFLAGS, 0 };
+static const unsigned ImplicitList55[] = { X86::EAX, X86::EDI, X86::EFLAGS, 0 };
+static const unsigned ImplicitList56[] = { X86::AX, X86::EDI, X86::EFLAGS, 0 };
static const TargetRegisterClass* Barriers8[] = { &X86::CCRRegClass, &X86::RFP32RegClass, &X86::RFP64RegClass, &X86::RFP80RegClass, &X86::VR64RegClass, NULL };
-static const unsigned ImplicitList50[] = { X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R10, X86::R11, X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, X86::ST0, X86::ST1, X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::EFLAGS, 0 };
+static const unsigned ImplicitList57[] = { X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R10, X86::R11, X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, X86::ST0, X86::ST1, X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::EFLAGS, 0 };
static const TargetOperandInfo OperandInfo2[] = { { X86::RFP32RegClassID, 0, 0 }, { X86::RFP32RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo3[] = { { X86::RFP64RegClassID, 0, 0 }, { X86::RFP64RegClassID, 0, 0 }, };
@@ -259,19 +266,17 @@ static const TargetOperandInfo OperandInfo190[] = { { X86::GR64RegClassID, 0, 0
static const TargetOperandInfo OperandInfo191[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR32RegClassID, 0, 0 }, { 0, 0, 0 }, };
static const TargetOperandInfo OperandInfo192[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR64RegClassID, 0, 0 }, { 0, 0, 0 }, };
static const TargetOperandInfo OperandInfo193[] = { { X86::VR128RegClassID, 0, 0 }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo194[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo195[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::LookupPtrRegClass), ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo196[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::GR16RegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo197[] = { { X86::GR16RegClassID, 0, 0 }, { X86::GR16RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR16RegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo198[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo199[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR32RegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo200[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::GR64RegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo201[] = { { X86::GR64RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR64RegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo202[] = { { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo203[] = { { X86::GR32RegClassID, 0, 0 }, { 0, 0, 0 }, { X86::GR32_NOSPRegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo204[] = { { X86::GR64RegClassID, 0, 0 }, { 0, 0, 0 }, { X86::GR64_NOSPRegClassID, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo205[] = { { X86::GR8RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo206[] = { { X86::VR128RegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo194[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::GR16RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo195[] = { { X86::GR16RegClassID, 0, 0 }, { X86::GR16RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR16RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo196[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::GR32RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo197[] = { { X86::GR32RegClassID, 0, 0 }, { X86::GR32RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR32RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo198[] = { { 0, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 1, 0|(1<<TOI::LookupPtrRegClass), 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { X86::GR64RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo199[] = { { X86::GR64RegClassID, 0, 0 }, { X86::GR64RegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { X86::GR64RegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo200[] = { { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo201[] = { { X86::GR32RegClassID, 0, 0 }, { 0, 0, 0 }, { X86::GR32_NOSPRegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo202[] = { { X86::GR64RegClassID, 0, 0 }, { 0, 0, 0 }, { X86::GR64_NOSPRegClassID, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo203[] = { { X86::GR8RegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo204[] = { { X86::VR128RegClassID, 0, 0 }, };
static const TargetInstrDesc X86Insts[] = {
{ 0, 0, 0, 0, "PHI", 0|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, 0 }, // Inst #0 = PHI
@@ -283,36 +288,36 @@ static const TargetInstrDesc X86Insts[] = {
{ 6, 3, 1, 0, "EXTRACT_SUBREG", 0, 0, NULL, NULL, NULL, OperandInfo76 }, // Inst #6 = EXTRACT_SUBREG
{ 7, 4, 1, 0, "INSERT_SUBREG", 0, 0, NULL, NULL, NULL, OperandInfo116 }, // Inst #7 = INSERT_SUBREG
{ 8, 1, 1, 0, "IMPLICIT_DEF", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0, NULL, NULL, NULL, OperandInfo5 }, // Inst #8 = IMPLICIT_DEF
- { 9, 4, 1, 0, "SUBREG_TO_REG", 0, 0, NULL, NULL, NULL, OperandInfo202 }, // Inst #9 = SUBREG_TO_REG
+ { 9, 4, 1, 0, "SUBREG_TO_REG", 0, 0, NULL, NULL, NULL, OperandInfo200 }, // Inst #9 = SUBREG_TO_REG
{ 10, 3, 1, 0, "COPY_TO_REGCLASS", 0|(1<<TID::CheapAsAMove), 0, NULL, NULL, NULL, OperandInfo76 }, // Inst #10 = COPY_TO_REGCLASS
- { 11, 0, 0, 0, "DEBUG_VALUE", 0|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::CheapAsAMove), 0, NULL, NULL, NULL, 0 }, // Inst #11 = DEBUG_VALUE
+ { 11, 0, 0, 0, "DBG_VALUE", 0|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::CheapAsAMove), 0, NULL, NULL, NULL, 0 }, // Inst #11 = DBG_VALUE
{ 12, 0, 0, 0, "ABS_F", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(225<<24), NULL, NULL, NULL, 0 }, // Inst #12 = ABS_F
{ 13, 2, 1, 0, "ABS_Fp32", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo2 }, // Inst #13 = ABS_Fp32
{ 14, 2, 1, 0, "ABS_Fp64", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo3 }, // Inst #14 = ABS_Fp64
{ 15, 2, 1, 0, "ABS_Fp80", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo4 }, // Inst #15 = ABS_Fp80
- { 16, 1, 0, 0, "ADC16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(2<<13)|(21<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #16 = ADC16i16
- { 17, 6, 0, 0, "ADC16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<6)|(2<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #17 = ADC16mi
+ { 16, 1, 0, 0, "ADC16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(3<<13)|(21<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #16 = ADC16i16
+ { 17, 6, 0, 0, "ADC16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<6)|(3<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #17 = ADC16mi
{ 18, 6, 0, 0, "ADC16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<6)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #18 = ADC16mi8
{ 19, 6, 0, 0, "ADC16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(17<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #19 = ADC16mr
- { 20, 3, 1, 0, "ADC16ri", 0, 0|18|(1<<6)|(2<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #20 = ADC16ri
+ { 20, 3, 1, 0, "ADC16ri", 0, 0|18|(1<<6)|(3<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #20 = ADC16ri
{ 21, 3, 1, 0, "ADC16ri8", 0, 0|18|(1<<6)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #21 = ADC16ri8
{ 22, 7, 1, 0, "ADC16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(19<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #22 = ADC16rm
{ 23, 3, 1, 0, "ADC16rr", 0|(1<<TID::Commutable), 0|3|(1<<6)|(17<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #23 = ADC16rr
{ 24, 3, 1, 0, "ADC16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(19<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #24 = ADC16rr_REV
- { 25, 1, 0, 0, "ADC32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(21<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #25 = ADC32i32
- { 26, 6, 0, 0, "ADC32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(3<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #26 = ADC32mi
+ { 25, 1, 0, 0, "ADC32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<13)|(21<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #25 = ADC32i32
+ { 26, 6, 0, 0, "ADC32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(4<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #26 = ADC32mi
{ 27, 6, 0, 0, "ADC32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #27 = ADC32mi8
{ 28, 6, 0, 0, "ADC32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(17<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #28 = ADC32mr
- { 29, 3, 1, 0, "ADC32ri", 0, 0|18|(3<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #29 = ADC32ri
+ { 29, 3, 1, 0, "ADC32ri", 0, 0|18|(4<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #29 = ADC32ri
{ 30, 3, 1, 0, "ADC32ri8", 0, 0|18|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #30 = ADC32ri8
{ 31, 7, 1, 0, "ADC32rm", 0|(1<<TID::MayLoad), 0|6|(19<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #31 = ADC32rm
{ 32, 3, 1, 0, "ADC32rr", 0|(1<<TID::Commutable), 0|3|(17<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #32 = ADC32rr
{ 33, 3, 1, 0, "ADC32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(19<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #33 = ADC32rr_REV
{ 34, 1, 0, 0, "ADC64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(21<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #34 = ADC64i32
- { 35, 6, 0, 0, "ADC64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<12)|(3<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #35 = ADC64mi32
+ { 35, 6, 0, 0, "ADC64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<12)|(4<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #35 = ADC64mi32
{ 36, 6, 0, 0, "ADC64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<12)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #36 = ADC64mi8
{ 37, 6, 0, 0, "ADC64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(17<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #37 = ADC64mr
- { 38, 3, 1, 0, "ADC64ri32", 0, 0|18|(1<<12)|(3<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #38 = ADC64ri32
+ { 38, 3, 1, 0, "ADC64ri32", 0, 0|18|(1<<12)|(4<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #38 = ADC64ri32
{ 39, 3, 1, 0, "ADC64ri8", 0, 0|18|(1<<12)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #39 = ADC64ri8
{ 40, 7, 1, 0, "ADC64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(19<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #40 = ADC64rm
{ 41, 3, 1, 0, "ADC64rr", 0|(1<<TID::Commutable), 0|3|(1<<12)|(17<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #41 = ADC64rr
@@ -324,30 +329,30 @@ static const TargetInstrDesc X86Insts[] = {
{ 47, 7, 1, 0, "ADC8rm", 0|(1<<TID::MayLoad), 0|6|(18<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #47 = ADC8rm
{ 48, 3, 1, 0, "ADC8rr", 0|(1<<TID::Commutable), 0|3|(16<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #48 = ADC8rr
{ 49, 3, 1, 0, "ADC8rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(18<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #49 = ADC8rr_REV
- { 50, 1, 0, 0, "ADD16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(2<<13)|(5<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #50 = ADD16i16
- { 51, 6, 0, 0, "ADD16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #51 = ADD16mi
+ { 50, 1, 0, 0, "ADD16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(3<<13)|(5<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #50 = ADD16i16
+ { 51, 6, 0, 0, "ADD16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #51 = ADD16mi
{ 52, 6, 0, 0, "ADD16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #52 = ADD16mi8
{ 53, 6, 0, 0, "ADD16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(1<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #53 = ADD16mr
{ 54, 3, 1, 0, "ADD16mrmrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(3<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #54 = ADD16mrmrr
- { 55, 3, 1, 0, "ADD16ri", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #55 = ADD16ri
+ { 55, 3, 1, 0, "ADD16ri", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(1<<6)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #55 = ADD16ri
{ 56, 3, 1, 0, "ADD16ri8", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #56 = ADD16ri8
{ 57, 7, 1, 0, "ADD16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(3<<24), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #57 = ADD16rm
{ 58, 3, 1, 0, "ADD16rr", 0|(1<<TID::ConvertibleTo3Addr)|(1<<TID::Commutable), 0|3|(1<<6)|(1<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #58 = ADD16rr
- { 59, 1, 0, 0, "ADD32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(5<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #59 = ADD32i32
- { 60, 6, 0, 0, "ADD32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #60 = ADD32mi
+ { 59, 1, 0, 0, "ADD32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<13)|(5<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #59 = ADD32i32
+ { 60, 6, 0, 0, "ADD32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #60 = ADD32mi
{ 61, 6, 0, 0, "ADD32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #61 = ADD32mi8
{ 62, 6, 0, 0, "ADD32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #62 = ADD32mr
{ 63, 3, 1, 0, "ADD32mrmrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(3<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #63 = ADD32mrmrr
- { 64, 3, 1, 0, "ADD32ri", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #64 = ADD32ri
+ { 64, 3, 1, 0, "ADD32ri", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #64 = ADD32ri
{ 65, 3, 1, 0, "ADD32ri8", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #65 = ADD32ri8
{ 66, 7, 1, 0, "ADD32rm", 0|(1<<TID::MayLoad), 0|6|(3<<24), NULL, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #66 = ADD32rm
{ 67, 3, 1, 0, "ADD32rr", 0|(1<<TID::ConvertibleTo3Addr)|(1<<TID::Commutable), 0|3|(1<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #67 = ADD32rr
{ 68, 1, 0, 0, "ADD64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(5<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #68 = ADD64i32
- { 69, 6, 0, 0, "ADD64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #69 = ADD64mi32
+ { 69, 6, 0, 0, "ADD64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<12)|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #69 = ADD64mi32
{ 70, 6, 0, 0, "ADD64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #70 = ADD64mi8
{ 71, 6, 0, 0, "ADD64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(1<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #71 = ADD64mr
{ 72, 3, 1, 0, "ADD64mrmrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(3<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #72 = ADD64mrmrr
- { 73, 3, 1, 0, "ADD64ri32", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #73 = ADD64ri32
+ { 73, 3, 1, 0, "ADD64ri32", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(1<<12)|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #73 = ADD64ri32
{ 74, 3, 1, 0, "ADD64ri8", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #74 = ADD64ri8
{ 75, 7, 1, 0, "ADD64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(3<<24), NULL, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #75 = ADD64rm
{ 76, 3, 1, 0, "ADD64rr", 0|(1<<TID::ConvertibleTo3Addr)|(1<<TID::Commutable), 0|3|(1<<12)|(1<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #76 = ADD64rr
@@ -399,29 +404,29 @@ static const TargetInstrDesc X86Insts[] = {
{ 122, 1, 0, 0, "ADJCALLSTACKDOWN64", 0, 0, ImplicitList4, ImplicitList5, Barriers1, OperandInfo5 }, // Inst #122 = ADJCALLSTACKDOWN64
{ 123, 2, 0, 0, "ADJCALLSTACKUP32", 0, 0, ImplicitList2, ImplicitList3, Barriers1, OperandInfo38 }, // Inst #123 = ADJCALLSTACKUP32
{ 124, 2, 0, 0, "ADJCALLSTACKUP64", 0, 0, ImplicitList4, ImplicitList5, Barriers1, OperandInfo38 }, // Inst #124 = ADJCALLSTACKUP64
- { 125, 1, 0, 0, "AND16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(2<<13)|(37<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #125 = AND16i16
- { 126, 6, 0, 0, "AND16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #126 = AND16mi
+ { 125, 1, 0, 0, "AND16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(3<<13)|(37<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #125 = AND16i16
+ { 126, 6, 0, 0, "AND16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<6)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #126 = AND16mi
{ 127, 6, 0, 0, "AND16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #127 = AND16mi8
{ 128, 6, 0, 0, "AND16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(33<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #128 = AND16mr
- { 129, 3, 1, 0, "AND16ri", 0, 0|20|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #129 = AND16ri
+ { 129, 3, 1, 0, "AND16ri", 0, 0|20|(1<<6)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #129 = AND16ri
{ 130, 3, 1, 0, "AND16ri8", 0, 0|20|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #130 = AND16ri8
{ 131, 7, 1, 0, "AND16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(35<<24), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #131 = AND16rm
{ 132, 3, 1, 0, "AND16rr", 0|(1<<TID::Commutable), 0|3|(1<<6)|(33<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #132 = AND16rr
{ 133, 3, 1, 0, "AND16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(35<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #133 = AND16rr_REV
- { 134, 1, 0, 0, "AND32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(37<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #134 = AND32i32
- { 135, 6, 0, 0, "AND32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #135 = AND32mi
+ { 134, 1, 0, 0, "AND32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<13)|(37<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #134 = AND32i32
+ { 135, 6, 0, 0, "AND32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #135 = AND32mi
{ 136, 6, 0, 0, "AND32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #136 = AND32mi8
{ 137, 6, 0, 0, "AND32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(33<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #137 = AND32mr
- { 138, 3, 1, 0, "AND32ri", 0, 0|20|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #138 = AND32ri
+ { 138, 3, 1, 0, "AND32ri", 0, 0|20|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #138 = AND32ri
{ 139, 3, 1, 0, "AND32ri8", 0, 0|20|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #139 = AND32ri8
{ 140, 7, 1, 0, "AND32rm", 0|(1<<TID::MayLoad), 0|6|(35<<24), NULL, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #140 = AND32rm
{ 141, 3, 1, 0, "AND32rr", 0|(1<<TID::Commutable), 0|3|(33<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #141 = AND32rr
{ 142, 3, 1, 0, "AND32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(35<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #142 = AND32rr_REV
{ 143, 1, 0, 0, "AND64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(37<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #143 = AND64i32
- { 144, 6, 0, 0, "AND64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #144 = AND64mi32
+ { 144, 6, 0, 0, "AND64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<12)|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #144 = AND64mi32
{ 145, 6, 0, 0, "AND64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #145 = AND64mi8
{ 146, 6, 0, 0, "AND64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(33<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #146 = AND64mr
- { 147, 3, 1, 0, "AND64ri32", 0, 0|20|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #147 = AND64ri32
+ { 147, 3, 1, 0, "AND64ri32", 0, 0|20|(1<<12)|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #147 = AND64ri32
{ 148, 3, 1, 0, "AND64ri8", 0, 0|20|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #148 = AND64ri8
{ 149, 7, 1, 0, "AND64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(35<<24), NULL, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #149 = AND64rm
{ 150, 3, 1, 0, "AND64rr", 0|(1<<TID::Commutable), 0|3|(1<<12)|(33<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #150 = AND64rr
@@ -549,9 +554,9 @@ static const TargetInstrDesc X86Insts[] = {
{ 272, 5, 0, 0, "CALL32m", 0|(1<<TID::Call)|(1<<TID::MayLoad)|(1<<TID::Variadic), 0|26|(255<<24), ImplicitList2, ImplicitList9, Barriers3, OperandInfo30 }, // Inst #272 = CALL32m
{ 273, 1, 0, 0, "CALL32r", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|18|(255<<24), ImplicitList2, ImplicitList9, Barriers3, OperandInfo57 }, // Inst #273 = CALL32r
{ 274, 5, 0, 0, "CALL64m", 0|(1<<TID::Call)|(1<<TID::MayLoad)|(1<<TID::Variadic), 0|26|(255<<24), ImplicitList4, ImplicitList10, Barriers4, OperandInfo30 }, // Inst #274 = CALL64m
- { 275, 1, 0, 0, "CALL64pcrel32", 0|(1<<TID::Call)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(232<<24), ImplicitList4, ImplicitList10, Barriers4, OperandInfo5 }, // Inst #275 = CALL64pcrel32
+ { 275, 1, 0, 0, "CALL64pcrel32", 0|(1<<TID::Call)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|1|(4<<13)|(232<<24), ImplicitList4, ImplicitList10, Barriers4, OperandInfo5 }, // Inst #275 = CALL64pcrel32
{ 276, 1, 0, 0, "CALL64r", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|18|(255<<24), ImplicitList4, ImplicitList10, Barriers4, OperandInfo58 }, // Inst #276 = CALL64r
- { 277, 1, 0, 0, "CALLpcrel32", 0|(1<<TID::Call)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(232<<24), ImplicitList2, ImplicitList9, Barriers3, OperandInfo5 }, // Inst #277 = CALLpcrel32
+ { 277, 1, 0, 0, "CALLpcrel32", 0|(1<<TID::Call)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|1|(5<<13)|(232<<24), ImplicitList2, ImplicitList9, Barriers3, OperandInfo5 }, // Inst #277 = CALLpcrel32
{ 278, 0, 0, 0, "CBW", 0, 0|1|(1<<6)|(152<<24), ImplicitList11, ImplicitList12, NULL, 0 }, // Inst #278 = CBW
{ 279, 0, 0, 0, "CDQ", 0, 0|1|(153<<24), ImplicitList13, ImplicitList14, Barriers5, 0 }, // Inst #279 = CDQ
{ 280, 0, 0, 0, "CDQE", 0, 0|1|(1<<12)|(152<<24), ImplicitList13, ImplicitList15, NULL, 0 }, // Inst #280 = CDQE
@@ -700,30 +705,30 @@ static const TargetInstrDesc X86Insts[] = {
{ 423, 4, 1, 0, "CMOV_V2F64", 0|(1<<TID::UsesCustomInserter), 0, ImplicitList1, NULL, NULL, OperandInfo66 }, // Inst #423 = CMOV_V2F64
{ 424, 4, 1, 0, "CMOV_V2I64", 0|(1<<TID::UsesCustomInserter), 0, ImplicitList1, NULL, NULL, OperandInfo66 }, // Inst #424 = CMOV_V2I64
{ 425, 4, 1, 0, "CMOV_V4F32", 0|(1<<TID::UsesCustomInserter), 0, ImplicitList1, NULL, NULL, OperandInfo66 }, // Inst #425 = CMOV_V4F32
- { 426, 1, 0, 0, "CMP16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(2<<13)|(61<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #426 = CMP16i16
- { 427, 6, 0, 0, "CMP16mi", 0|(1<<TID::MayLoad), 0|31|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #427 = CMP16mi
+ { 426, 1, 0, 0, "CMP16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(3<<13)|(61<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #426 = CMP16i16
+ { 427, 6, 0, 0, "CMP16mi", 0|(1<<TID::MayLoad), 0|31|(1<<6)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #427 = CMP16mi
{ 428, 6, 0, 0, "CMP16mi8", 0|(1<<TID::MayLoad), 0|31|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #428 = CMP16mi8
{ 429, 6, 0, 0, "CMP16mr", 0|(1<<TID::MayLoad), 0|4|(1<<6)|(57<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #429 = CMP16mr
{ 430, 2, 0, 0, "CMP16mrmrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(59<<24), NULL, ImplicitList1, Barriers1, OperandInfo47 }, // Inst #430 = CMP16mrmrr
- { 431, 2, 0, 0, "CMP16ri", 0, 0|23|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo54 }, // Inst #431 = CMP16ri
+ { 431, 2, 0, 0, "CMP16ri", 0, 0|23|(1<<6)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo54 }, // Inst #431 = CMP16ri
{ 432, 2, 0, 0, "CMP16ri8", 0, 0|23|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo54 }, // Inst #432 = CMP16ri8
{ 433, 6, 0, 0, "CMP16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(59<<24), NULL, ImplicitList1, Barriers1, OperandInfo46 }, // Inst #433 = CMP16rm
{ 434, 2, 0, 0, "CMP16rr", 0, 0|3|(1<<6)|(57<<24), NULL, ImplicitList1, Barriers1, OperandInfo47 }, // Inst #434 = CMP16rr
- { 435, 1, 0, 0, "CMP32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(61<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #435 = CMP32i32
- { 436, 6, 0, 0, "CMP32mi", 0|(1<<TID::MayLoad), 0|31|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #436 = CMP32mi
+ { 435, 1, 0, 0, "CMP32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<13)|(61<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #435 = CMP32i32
+ { 436, 6, 0, 0, "CMP32mi", 0|(1<<TID::MayLoad), 0|31|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #436 = CMP32mi
{ 437, 6, 0, 0, "CMP32mi8", 0|(1<<TID::MayLoad), 0|31|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #437 = CMP32mi8
{ 438, 6, 0, 0, "CMP32mr", 0|(1<<TID::MayLoad), 0|4|(57<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #438 = CMP32mr
{ 439, 2, 0, 0, "CMP32mrmrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(59<<24), NULL, ImplicitList1, Barriers1, OperandInfo49 }, // Inst #439 = CMP32mrmrr
- { 440, 2, 0, 0, "CMP32ri", 0, 0|23|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo55 }, // Inst #440 = CMP32ri
+ { 440, 2, 0, 0, "CMP32ri", 0, 0|23|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo55 }, // Inst #440 = CMP32ri
{ 441, 2, 0, 0, "CMP32ri8", 0, 0|23|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo55 }, // Inst #441 = CMP32ri8
{ 442, 6, 0, 0, "CMP32rm", 0|(1<<TID::MayLoad), 0|6|(59<<24), NULL, ImplicitList1, Barriers1, OperandInfo48 }, // Inst #442 = CMP32rm
{ 443, 2, 0, 0, "CMP32rr", 0, 0|3|(57<<24), NULL, ImplicitList1, Barriers1, OperandInfo49 }, // Inst #443 = CMP32rr
{ 444, 1, 0, 0, "CMP64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(61<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #444 = CMP64i32
- { 445, 6, 0, 0, "CMP64mi32", 0|(1<<TID::MayLoad), 0|31|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #445 = CMP64mi32
+ { 445, 6, 0, 0, "CMP64mi32", 0|(1<<TID::MayLoad), 0|31|(1<<12)|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #445 = CMP64mi32
{ 446, 6, 0, 0, "CMP64mi8", 0|(1<<TID::MayLoad), 0|31|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #446 = CMP64mi8
{ 447, 6, 0, 0, "CMP64mr", 0|(1<<TID::MayLoad), 0|4|(1<<12)|(57<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #447 = CMP64mr
{ 448, 2, 0, 0, "CMP64mrmrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(59<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #448 = CMP64mrmrr
- { 449, 2, 0, 0, "CMP64ri32", 0, 0|23|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo56 }, // Inst #449 = CMP64ri32
+ { 449, 2, 0, 0, "CMP64ri32", 0, 0|23|(1<<12)|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo56 }, // Inst #449 = CMP64ri32
{ 450, 2, 0, 0, "CMP64ri8", 0, 0|23|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo56 }, // Inst #450 = CMP64ri8
{ 451, 6, 0, 0, "CMP64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(59<<24), NULL, ImplicitList1, Barriers1, OperandInfo50 }, // Inst #451 = CMP64rm
{ 452, 2, 0, 0, "CMP64rr", 0, 0|3|(1<<12)|(57<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #452 = CMP64rr
@@ -778,2018 +783,2033 @@ static const TargetInstrDesc X86Insts[] = {
{ 501, 3, 1, 0, "CRC32r8", 0, 0|5|(1<<6)|(15<<8)|(240<<24), NULL, NULL, NULL, OperandInfo78 }, // Inst #501 = CRC32r8
{ 502, 7, 1, 0, "CRC64m64", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(15<<8)|(1<<12)|(240<<24), NULL, NULL, NULL, OperandInfo17 }, // Inst #502 = CRC64m64
{ 503, 3, 1, 0, "CRC64r64", 0, 0|5|(1<<6)|(15<<8)|(1<<12)|(240<<24), NULL, NULL, NULL, OperandInfo18 }, // Inst #503 = CRC64r64
- { 504, 6, 1, 0, "CVTDQ2PDrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(12<<8)|(230<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #504 = CVTDQ2PDrm
- { 505, 2, 1, 0, "CVTDQ2PDrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(12<<8)|(230<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #505 = CVTDQ2PDrr
- { 506, 6, 1, 0, "CVTDQ2PSrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(91<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #506 = CVTDQ2PSrm
- { 507, 2, 1, 0, "CVTDQ2PSrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(91<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #507 = CVTDQ2PSrr
- { 508, 6, 1, 0, "CVTPD2DQrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(11<<8)|(230<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #508 = CVTPD2DQrm
- { 509, 2, 1, 0, "CVTPD2DQrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(11<<8)|(230<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #509 = CVTPD2DQrr
- { 510, 6, 1, 0, "CVTPD2PSrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(90<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #510 = CVTPD2PSrm
- { 511, 2, 1, 0, "CVTPD2PSrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(90<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #511 = CVTPD2PSrr
- { 512, 6, 1, 0, "CVTPS2DQrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(91<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #512 = CVTPS2DQrm
- { 513, 2, 1, 0, "CVTPS2DQrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(91<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #513 = CVTPS2DQrr
- { 514, 6, 1, 0, "CVTPS2PDrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(90<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #514 = CVTPS2PDrm
- { 515, 2, 1, 0, "CVTPS2PDrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(90<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #515 = CVTPS2PDrr
- { 516, 6, 1, 0, "CVTSD2SI64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(11<<8)|(1<<12)|(45<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #516 = CVTSD2SI64rm
- { 517, 2, 1, 0, "CVTSD2SI64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(11<<8)|(1<<12)|(45<<24), NULL, NULL, NULL, OperandInfo79 }, // Inst #517 = CVTSD2SI64rr
- { 518, 6, 1, 0, "CVTSD2SSrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(90<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #518 = CVTSD2SSrm
- { 519, 2, 1, 0, "CVTSD2SSrr", 0, 0|5|(11<<8)|(90<<24), NULL, NULL, NULL, OperandInfo81 }, // Inst #519 = CVTSD2SSrr
- { 520, 6, 1, 0, "CVTSI2SD64rm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<12)|(42<<24), NULL, NULL, NULL, OperandInfo82 }, // Inst #520 = CVTSI2SD64rm
- { 521, 2, 1, 0, "CVTSI2SD64rr", 0, 0|5|(11<<8)|(1<<12)|(42<<24), NULL, NULL, NULL, OperandInfo83 }, // Inst #521 = CVTSI2SD64rr
- { 522, 6, 1, 0, "CVTSI2SDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(42<<24), NULL, NULL, NULL, OperandInfo82 }, // Inst #522 = CVTSI2SDrm
- { 523, 2, 1, 0, "CVTSI2SDrr", 0, 0|5|(11<<8)|(42<<24), NULL, NULL, NULL, OperandInfo84 }, // Inst #523 = CVTSI2SDrr
- { 524, 6, 1, 0, "CVTSI2SS64rm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<12)|(42<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #524 = CVTSI2SS64rm
- { 525, 2, 1, 0, "CVTSI2SS64rr", 0, 0|5|(12<<8)|(1<<12)|(42<<24), NULL, NULL, NULL, OperandInfo85 }, // Inst #525 = CVTSI2SS64rr
- { 526, 6, 1, 0, "CVTSI2SSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(42<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #526 = CVTSI2SSrm
- { 527, 2, 1, 0, "CVTSI2SSrr", 0, 0|5|(12<<8)|(42<<24), NULL, NULL, NULL, OperandInfo86 }, // Inst #527 = CVTSI2SSrr
- { 528, 6, 1, 0, "CVTSS2SDrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(90<<24), NULL, NULL, NULL, OperandInfo82 }, // Inst #528 = CVTSS2SDrm
- { 529, 2, 1, 0, "CVTSS2SDrr", 0, 0|5|(12<<8)|(90<<24), NULL, NULL, NULL, OperandInfo87 }, // Inst #529 = CVTSS2SDrr
- { 530, 6, 1, 0, "CVTSS2SI64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(12<<8)|(1<<12)|(45<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #530 = CVTSS2SI64rm
- { 531, 2, 1, 0, "CVTSS2SI64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(12<<8)|(1<<12)|(45<<24), NULL, NULL, NULL, OperandInfo88 }, // Inst #531 = CVTSS2SI64rr
- { 532, 6, 1, 0, "CVTSS2SIrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(12<<8)|(45<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #532 = CVTSS2SIrm
- { 533, 2, 1, 0, "CVTSS2SIrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(12<<8)|(45<<24), NULL, NULL, NULL, OperandInfo89 }, // Inst #533 = CVTSS2SIrr
- { 534, 6, 1, 0, "CVTTPS2DQrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(12<<8)|(91<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #534 = CVTTPS2DQrm
- { 535, 2, 1, 0, "CVTTPS2DQrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(12<<8)|(91<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #535 = CVTTPS2DQrr
- { 536, 6, 1, 0, "CVTTSD2SI64rm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<12)|(44<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #536 = CVTTSD2SI64rm
- { 537, 2, 1, 0, "CVTTSD2SI64rr", 0, 0|5|(11<<8)|(1<<12)|(44<<24), NULL, NULL, NULL, OperandInfo79 }, // Inst #537 = CVTTSD2SI64rr
- { 538, 6, 1, 0, "CVTTSD2SIrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(44<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #538 = CVTTSD2SIrm
- { 539, 2, 1, 0, "CVTTSD2SIrr", 0, 0|5|(11<<8)|(44<<24), NULL, NULL, NULL, OperandInfo90 }, // Inst #539 = CVTTSD2SIrr
- { 540, 6, 1, 0, "CVTTSS2SI64rm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<12)|(44<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #540 = CVTTSS2SI64rm
- { 541, 2, 1, 0, "CVTTSS2SI64rr", 0, 0|5|(12<<8)|(1<<12)|(44<<24), NULL, NULL, NULL, OperandInfo88 }, // Inst #541 = CVTTSS2SI64rr
- { 542, 6, 1, 0, "CVTTSS2SIrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(44<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #542 = CVTTSS2SIrm
- { 543, 2, 1, 0, "CVTTSS2SIrr", 0, 0|5|(12<<8)|(44<<24), NULL, NULL, NULL, OperandInfo89 }, // Inst #543 = CVTTSS2SIrr
- { 544, 0, 0, 0, "CWD", 0, 0|1|(1<<6)|(153<<24), ImplicitList12, ImplicitList20, NULL, 0 }, // Inst #544 = CWD
- { 545, 0, 0, 0, "CWDE", 0, 0|1|(152<<24), ImplicitList12, ImplicitList13, NULL, 0 }, // Inst #545 = CWDE
- { 546, 5, 0, 0, "DEC16m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #546 = DEC16m
- { 547, 2, 1, 0, "DEC16r", 0|(1<<TID::ConvertibleTo3Addr), 0|2|(1<<6)|(72<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #547 = DEC16r
- { 548, 5, 0, 0, "DEC32m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #548 = DEC32m
- { 549, 2, 1, 0, "DEC32r", 0|(1<<TID::ConvertibleTo3Addr), 0|2|(72<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #549 = DEC32r
- { 550, 5, 0, 0, "DEC64_16m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #550 = DEC64_16m
- { 551, 2, 1, 0, "DEC64_16r", 0|(1<<TID::ConvertibleTo3Addr), 0|17|(1<<6)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #551 = DEC64_16r
- { 552, 5, 0, 0, "DEC64_32m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #552 = DEC64_32m
- { 553, 2, 1, 0, "DEC64_32r", 0|(1<<TID::ConvertibleTo3Addr), 0|17|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #553 = DEC64_32r
- { 554, 5, 0, 0, "DEC64m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #554 = DEC64m
- { 555, 2, 1, 0, "DEC64r", 0|(1<<TID::ConvertibleTo3Addr), 0|17|(1<<12)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #555 = DEC64r
- { 556, 5, 0, 0, "DEC8m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(254<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #556 = DEC8m
- { 557, 2, 1, 0, "DEC8r", 0, 0|17|(254<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #557 = DEC8r
- { 558, 5, 0, 0, "DIV16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|30|(1<<6)|(247<<24), ImplicitList20, ImplicitList21, Barriers1, OperandInfo30 }, // Inst #558 = DIV16m
- { 559, 1, 0, 0, "DIV16r", 0|(1<<TID::UnmodeledSideEffects), 0|22|(1<<6)|(247<<24), ImplicitList20, ImplicitList21, Barriers1, OperandInfo93 }, // Inst #559 = DIV16r
- { 560, 5, 0, 0, "DIV32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|30|(247<<24), ImplicitList14, ImplicitList18, Barriers6, OperandInfo30 }, // Inst #560 = DIV32m
- { 561, 1, 0, 0, "DIV32r", 0|(1<<TID::UnmodeledSideEffects), 0|22|(247<<24), ImplicitList14, ImplicitList18, Barriers6, OperandInfo57 }, // Inst #561 = DIV32r
- { 562, 5, 0, 0, "DIV64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|30|(1<<12)|(247<<24), ImplicitList19, ImplicitList17, Barriers1, OperandInfo30 }, // Inst #562 = DIV64m
- { 563, 1, 0, 0, "DIV64r", 0|(1<<TID::UnmodeledSideEffects), 0|22|(1<<12)|(247<<24), ImplicitList19, ImplicitList17, Barriers1, OperandInfo58 }, // Inst #563 = DIV64r
- { 564, 5, 0, 0, "DIV8m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|30|(246<<24), ImplicitList12, ImplicitList22, Barriers1, OperandInfo30 }, // Inst #564 = DIV8m
- { 565, 1, 0, 0, "DIV8r", 0|(1<<TID::UnmodeledSideEffects), 0|22|(246<<24), ImplicitList12, ImplicitList22, Barriers1, OperandInfo94 }, // Inst #565 = DIV8r
- { 566, 7, 1, 0, "DIVPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(94<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #566 = DIVPDrm
- { 567, 3, 1, 0, "DIVPDrr", 0, 0|5|(1<<6)|(1<<8)|(94<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #567 = DIVPDrr
- { 568, 7, 1, 0, "DIVPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(94<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #568 = DIVPSrm
- { 569, 3, 1, 0, "DIVPSrr", 0, 0|5|(1<<8)|(94<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #569 = DIVPSrr
- { 570, 5, 0, 0, "DIVR_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|31|(216<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #570 = DIVR_F32m
- { 571, 5, 0, 0, "DIVR_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|31|(220<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #571 = DIVR_F64m
- { 572, 5, 0, 0, "DIVR_FI16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|31|(222<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #572 = DIVR_FI16m
- { 573, 5, 0, 0, "DIVR_FI32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|31|(218<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #573 = DIVR_FI32m
- { 574, 1, 0, 0, "DIVR_FPrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(9<<8)|(240<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #574 = DIVR_FPrST0
- { 575, 1, 0, 0, "DIVR_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(248<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #575 = DIVR_FST0r
- { 576, 7, 1, 0, "DIVR_Fp32m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #576 = DIVR_Fp32m
- { 577, 7, 1, 0, "DIVR_Fp64m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #577 = DIVR_Fp64m
- { 578, 7, 1, 0, "DIVR_Fp64m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #578 = DIVR_Fp64m32
- { 579, 7, 1, 0, "DIVR_Fp80m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #579 = DIVR_Fp80m32
- { 580, 7, 1, 0, "DIVR_Fp80m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #580 = DIVR_Fp80m64
- { 581, 7, 1, 0, "DIVR_FpI16m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #581 = DIVR_FpI16m32
- { 582, 7, 1, 0, "DIVR_FpI16m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #582 = DIVR_FpI16m64
- { 583, 7, 1, 0, "DIVR_FpI16m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #583 = DIVR_FpI16m80
- { 584, 7, 1, 0, "DIVR_FpI32m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #584 = DIVR_FpI32m32
- { 585, 7, 1, 0, "DIVR_FpI32m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #585 = DIVR_FpI32m64
- { 586, 7, 1, 0, "DIVR_FpI32m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #586 = DIVR_FpI32m80
- { 587, 1, 0, 0, "DIVR_FrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(7<<8)|(240<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #587 = DIVR_FrST0
- { 588, 7, 1, 0, "DIVSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(94<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #588 = DIVSDrm
- { 589, 7, 1, 0, "DIVSDrm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(94<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #589 = DIVSDrm_Int
- { 590, 3, 1, 0, "DIVSDrr", 0, 0|5|(11<<8)|(94<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #590 = DIVSDrr
- { 591, 3, 1, 0, "DIVSDrr_Int", 0, 0|5|(11<<8)|(94<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #591 = DIVSDrr_Int
- { 592, 7, 1, 0, "DIVSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(94<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #592 = DIVSSrm
- { 593, 7, 1, 0, "DIVSSrm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(94<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #593 = DIVSSrm_Int
- { 594, 3, 1, 0, "DIVSSrr", 0, 0|5|(12<<8)|(94<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #594 = DIVSSrr
- { 595, 3, 1, 0, "DIVSSrr_Int", 0, 0|5|(12<<8)|(94<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #595 = DIVSSrr_Int
- { 596, 5, 0, 0, "DIV_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|30|(216<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #596 = DIV_F32m
- { 597, 5, 0, 0, "DIV_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|30|(220<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #597 = DIV_F64m
- { 598, 5, 0, 0, "DIV_FI16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|30|(222<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #598 = DIV_FI16m
- { 599, 5, 0, 0, "DIV_FI32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|30|(218<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #599 = DIV_FI32m
- { 600, 1, 0, 0, "DIV_FPrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(9<<8)|(248<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #600 = DIV_FPrST0
- { 601, 1, 0, 0, "DIV_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(240<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #601 = DIV_FST0r
- { 602, 3, 1, 0, "DIV_Fp32", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #602 = DIV_Fp32
- { 603, 7, 1, 0, "DIV_Fp32m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #603 = DIV_Fp32m
- { 604, 3, 1, 0, "DIV_Fp64", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #604 = DIV_Fp64
- { 605, 7, 1, 0, "DIV_Fp64m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #605 = DIV_Fp64m
- { 606, 7, 1, 0, "DIV_Fp64m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #606 = DIV_Fp64m32
- { 607, 3, 1, 0, "DIV_Fp80", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #607 = DIV_Fp80
- { 608, 7, 1, 0, "DIV_Fp80m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #608 = DIV_Fp80m32
- { 609, 7, 1, 0, "DIV_Fp80m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #609 = DIV_Fp80m64
- { 610, 7, 1, 0, "DIV_FpI16m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #610 = DIV_FpI16m32
- { 611, 7, 1, 0, "DIV_FpI16m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #611 = DIV_FpI16m64
- { 612, 7, 1, 0, "DIV_FpI16m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #612 = DIV_FpI16m80
- { 613, 7, 1, 0, "DIV_FpI32m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #613 = DIV_FpI32m32
- { 614, 7, 1, 0, "DIV_FpI32m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #614 = DIV_FpI32m64
- { 615, 7, 1, 0, "DIV_FpI32m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #615 = DIV_FpI32m80
- { 616, 1, 0, 0, "DIV_FrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(7<<8)|(248<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #616 = DIV_FrST0
- { 617, 8, 1, 0, "DPPDrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(65<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #617 = DPPDrmi
- { 618, 4, 1, 0, "DPPDrri", 0|(1<<TID::Commutable), 0|5|(1<<6)|(14<<8)|(1<<13)|(65<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #618 = DPPDrri
- { 619, 8, 1, 0, "DPPSrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(64<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #619 = DPPSrmi
- { 620, 4, 1, 0, "DPPSrri", 0|(1<<TID::Commutable), 0|5|(1<<6)|(14<<8)|(1<<13)|(64<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #620 = DPPSrri
- { 621, 1, 0, 0, "EH_RETURN", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|1|(195<<24), NULL, NULL, NULL, OperandInfo57 }, // Inst #621 = EH_RETURN
- { 622, 1, 0, 0, "EH_RETURN64", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|1|(195<<24), NULL, NULL, NULL, OperandInfo58 }, // Inst #622 = EH_RETURN64
- { 623, 2, 0, 0, "ENTER", 0|(1<<TID::UnmodeledSideEffects), 0|1|(200<<24), NULL, NULL, NULL, OperandInfo38 }, // Inst #623 = ENTER
- { 624, 7, 0, 0, "EXTRACTPSmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(14<<8)|(1<<13)|(23<<24), NULL, NULL, NULL, OperandInfo95 }, // Inst #624 = EXTRACTPSmr
- { 625, 3, 1, 0, "EXTRACTPSrr", 0, 0|3|(1<<6)|(14<<8)|(1<<13)|(23<<24), NULL, NULL, NULL, OperandInfo96 }, // Inst #625 = EXTRACTPSrr
- { 626, 0, 0, 0, "F2XM1", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(240<<24), NULL, NULL, NULL, 0 }, // Inst #626 = F2XM1
- { 627, 2, 0, 0, "FARCALL16i", 0|(1<<TID::Call)|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(154<<24), ImplicitList2, ImplicitList9, Barriers3, OperandInfo38 }, // Inst #627 = FARCALL16i
- { 628, 5, 0, 0, "FARCALL16m", 0|(1<<TID::Call)|(1<<TID::UnmodeledSideEffects), 0|27|(1<<6)|(255<<24), ImplicitList2, ImplicitList9, Barriers3, OperandInfo30 }, // Inst #628 = FARCALL16m
- { 629, 2, 0, 0, "FARCALL32i", 0|(1<<TID::Call)|(1<<TID::UnmodeledSideEffects), 0|1|(154<<24), ImplicitList2, ImplicitList9, Barriers3, OperandInfo38 }, // Inst #629 = FARCALL32i
- { 630, 5, 0, 0, "FARCALL32m", 0|(1<<TID::Call)|(1<<TID::UnmodeledSideEffects), 0|27|(255<<24), ImplicitList2, ImplicitList9, Barriers3, OperandInfo30 }, // Inst #630 = FARCALL32m
- { 631, 5, 0, 0, "FARCALL64", 0|(1<<TID::Call)|(1<<TID::UnmodeledSideEffects), 0|27|(1<<12)|(255<<24), ImplicitList4, ImplicitList10, Barriers4, OperandInfo30 }, // Inst #631 = FARCALL64
- { 632, 2, 0, 0, "FARJMP16i", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(234<<24), NULL, NULL, NULL, OperandInfo38 }, // Inst #632 = FARJMP16i
- { 633, 5, 0, 0, "FARJMP16m", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|29|(1<<6)|(255<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #633 = FARJMP16m
- { 634, 2, 0, 0, "FARJMP32i", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(234<<24), NULL, NULL, NULL, OperandInfo38 }, // Inst #634 = FARJMP32i
- { 635, 5, 0, 0, "FARJMP32m", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|29|(255<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #635 = FARJMP32m
- { 636, 5, 0, 0, "FARJMP64", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|29|(1<<12)|(255<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #636 = FARJMP64
- { 637, 5, 0, 0, "FBLDm", 0|(1<<TID::UnmodeledSideEffects), 0|28|(223<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #637 = FBLDm
- { 638, 5, 1, 0, "FBSTPm", 0|(1<<TID::UnmodeledSideEffects), 0|30|(223<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #638 = FBSTPm
- { 639, 5, 0, 0, "FCOM32m", 0|(1<<TID::UnmodeledSideEffects), 0|26|(216<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #639 = FCOM32m
- { 640, 5, 0, 0, "FCOM64m", 0|(1<<TID::UnmodeledSideEffects), 0|26|(220<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #640 = FCOM64m
- { 641, 5, 0, 0, "FCOMP32m", 0|(1<<TID::UnmodeledSideEffects), 0|27|(216<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #641 = FCOMP32m
- { 642, 5, 0, 0, "FCOMP64m", 0|(1<<TID::UnmodeledSideEffects), 0|27|(220<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #642 = FCOMP64m
- { 643, 0, 0, 0, "FCOMPP", 0|(1<<TID::UnmodeledSideEffects), 0|1|(9<<8)|(217<<24), NULL, NULL, NULL, 0 }, // Inst #643 = FCOMPP
- { 644, 0, 0, 0, "FDECSTP", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(246<<24), NULL, NULL, NULL, 0 }, // Inst #644 = FDECSTP
- { 645, 1, 0, 0, "FFREE", 0|(1<<TID::UnmodeledSideEffects), 0|2|(8<<8)|(192<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #645 = FFREE
- { 646, 5, 0, 0, "FICOM16m", 0|(1<<TID::UnmodeledSideEffects), 0|26|(222<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #646 = FICOM16m
- { 647, 5, 0, 0, "FICOM32m", 0|(1<<TID::UnmodeledSideEffects), 0|26|(218<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #647 = FICOM32m
- { 648, 5, 0, 0, "FICOMP16m", 0|(1<<TID::UnmodeledSideEffects), 0|27|(222<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #648 = FICOMP16m
- { 649, 5, 0, 0, "FICOMP32m", 0|(1<<TID::UnmodeledSideEffects), 0|27|(218<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #649 = FICOMP32m
- { 650, 0, 0, 0, "FINCSTP", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(247<<24), NULL, NULL, NULL, 0 }, // Inst #650 = FINCSTP
- { 651, 5, 1, 0, "FISTTP32m", 0|(1<<TID::UnmodeledSideEffects), 0|25|(221<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #651 = FISTTP32m
- { 652, 5, 0, 0, "FLDCW16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(217<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #652 = FLDCW16m
- { 653, 5, 0, 0, "FLDENVm", 0|(1<<TID::UnmodeledSideEffects), 0|28|(217<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #653 = FLDENVm
- { 654, 0, 0, 0, "FLDL2E", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(234<<24), NULL, NULL, NULL, 0 }, // Inst #654 = FLDL2E
- { 655, 0, 0, 0, "FLDL2T", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(233<<24), NULL, NULL, NULL, 0 }, // Inst #655 = FLDL2T
- { 656, 0, 0, 0, "FLDLG2", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(236<<24), NULL, NULL, NULL, 0 }, // Inst #656 = FLDLG2
- { 657, 0, 0, 0, "FLDLN2", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(237<<24), NULL, NULL, NULL, 0 }, // Inst #657 = FLDLN2
- { 658, 0, 0, 0, "FLDPI", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(235<<24), NULL, NULL, NULL, 0 }, // Inst #658 = FLDPI
- { 659, 0, 0, 0, "FNCLEX", 0|(1<<TID::UnmodeledSideEffects), 0|1|(6<<8)|(226<<24), NULL, NULL, NULL, 0 }, // Inst #659 = FNCLEX
- { 660, 0, 0, 0, "FNINIT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(6<<8)|(227<<24), NULL, NULL, NULL, 0 }, // Inst #660 = FNINIT
- { 661, 0, 0, 0, "FNOP", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(208<<24), NULL, NULL, NULL, 0 }, // Inst #661 = FNOP
- { 662, 5, 0, 0, "FNSTCW16m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|31|(217<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #662 = FNSTCW16m
- { 663, 0, 0, 0, "FNSTSW8r", 0|(1<<TID::UnmodeledSideEffects), 0|1|(10<<8)|(224<<24), NULL, ImplicitList12, NULL, 0 }, // Inst #663 = FNSTSW8r
- { 664, 5, 1, 0, "FNSTSWm", 0|(1<<TID::UnmodeledSideEffects), 0|31|(221<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #664 = FNSTSWm
- { 665, 6, 0, 0, "FP32_TO_INT16_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo97 }, // Inst #665 = FP32_TO_INT16_IN_MEM
- { 666, 6, 0, 0, "FP32_TO_INT32_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo97 }, // Inst #666 = FP32_TO_INT32_IN_MEM
- { 667, 6, 0, 0, "FP32_TO_INT64_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo97 }, // Inst #667 = FP32_TO_INT64_IN_MEM
- { 668, 6, 0, 0, "FP64_TO_INT16_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo98 }, // Inst #668 = FP64_TO_INT16_IN_MEM
- { 669, 6, 0, 0, "FP64_TO_INT32_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo98 }, // Inst #669 = FP64_TO_INT32_IN_MEM
- { 670, 6, 0, 0, "FP64_TO_INT64_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo98 }, // Inst #670 = FP64_TO_INT64_IN_MEM
- { 671, 6, 0, 0, "FP80_TO_INT16_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo99 }, // Inst #671 = FP80_TO_INT16_IN_MEM
- { 672, 6, 0, 0, "FP80_TO_INT32_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo99 }, // Inst #672 = FP80_TO_INT32_IN_MEM
- { 673, 6, 0, 0, "FP80_TO_INT64_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo99 }, // Inst #673 = FP80_TO_INT64_IN_MEM
- { 674, 0, 0, 0, "FPATAN", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(243<<24), NULL, NULL, NULL, 0 }, // Inst #674 = FPATAN
- { 675, 0, 0, 0, "FPREM", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(248<<24), NULL, NULL, NULL, 0 }, // Inst #675 = FPREM
- { 676, 0, 0, 0, "FPREM1", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(245<<24), NULL, NULL, NULL, 0 }, // Inst #676 = FPREM1
- { 677, 0, 0, 0, "FPTAN", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(242<<24), NULL, NULL, NULL, 0 }, // Inst #677 = FPTAN
- { 678, 0, 0, 0, "FP_REG_KILL", 0|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0, NULL, ImplicitList23, Barriers7, 0 }, // Inst #678 = FP_REG_KILL
- { 679, 0, 0, 0, "FRNDINT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(252<<24), NULL, NULL, NULL, 0 }, // Inst #679 = FRNDINT
- { 680, 5, 1, 0, "FRSTORm", 0|(1<<TID::UnmodeledSideEffects), 0|28|(221<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #680 = FRSTORm
- { 681, 5, 1, 0, "FSAVEm", 0|(1<<TID::UnmodeledSideEffects), 0|30|(221<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #681 = FSAVEm
- { 682, 0, 0, 0, "FSCALE", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(253<<24), NULL, NULL, NULL, 0 }, // Inst #682 = FSCALE
- { 683, 0, 0, 0, "FSINCOS", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(251<<24), NULL, NULL, NULL, 0 }, // Inst #683 = FSINCOS
- { 684, 5, 1, 0, "FSTENVm", 0|(1<<TID::UnmodeledSideEffects), 0|30|(217<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #684 = FSTENVm
- { 685, 6, 1, 0, "FS_MOV32rm", 0|(1<<TID::MayLoad), 0|6|(1<<20)|(139<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #685 = FS_MOV32rm
- { 686, 0, 0, 0, "FXAM", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(229<<24), NULL, NULL, NULL, 0 }, // Inst #686 = FXAM
- { 687, 5, 0, 0, "FXRSTOR", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<8)|(174<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #687 = FXRSTOR
- { 688, 5, 1, 0, "FXSAVE", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<8)|(174<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #688 = FXSAVE
- { 689, 0, 0, 0, "FXTRACT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(244<<24), NULL, NULL, NULL, 0 }, // Inst #689 = FXTRACT
- { 690, 0, 0, 0, "FYL2X", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(241<<24), NULL, NULL, NULL, 0 }, // Inst #690 = FYL2X
- { 691, 0, 0, 0, "FYL2XP1", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(249<<24), NULL, NULL, NULL, 0 }, // Inst #691 = FYL2XP1
- { 692, 1, 1, 0, "FpGET_ST0_32", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, NULL, NULL, OperandInfo100 }, // Inst #692 = FpGET_ST0_32
- { 693, 1, 1, 0, "FpGET_ST0_64", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, NULL, NULL, OperandInfo101 }, // Inst #693 = FpGET_ST0_64
- { 694, 1, 1, 0, "FpGET_ST0_80", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, NULL, NULL, OperandInfo102 }, // Inst #694 = FpGET_ST0_80
- { 695, 1, 1, 0, "FpGET_ST1_32", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, NULL, NULL, OperandInfo100 }, // Inst #695 = FpGET_ST1_32
- { 696, 1, 1, 0, "FpGET_ST1_64", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, NULL, NULL, OperandInfo101 }, // Inst #696 = FpGET_ST1_64
- { 697, 1, 1, 0, "FpGET_ST1_80", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, NULL, NULL, OperandInfo102 }, // Inst #697 = FpGET_ST1_80
- { 698, 1, 0, 0, "FpSET_ST0_32", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, ImplicitList24, NULL, OperandInfo100 }, // Inst #698 = FpSET_ST0_32
- { 699, 1, 0, 0, "FpSET_ST0_64", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, ImplicitList24, NULL, OperandInfo101 }, // Inst #699 = FpSET_ST0_64
- { 700, 1, 0, 0, "FpSET_ST0_80", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, ImplicitList24, NULL, OperandInfo102 }, // Inst #700 = FpSET_ST0_80
- { 701, 1, 0, 0, "FpSET_ST1_32", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, ImplicitList25, NULL, OperandInfo100 }, // Inst #701 = FpSET_ST1_32
- { 702, 1, 0, 0, "FpSET_ST1_64", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, ImplicitList25, NULL, OperandInfo101 }, // Inst #702 = FpSET_ST1_64
- { 703, 1, 0, 0, "FpSET_ST1_80", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, ImplicitList25, NULL, OperandInfo102 }, // Inst #703 = FpSET_ST1_80
- { 704, 7, 1, 0, "FsANDNPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(85<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #704 = FsANDNPDrm
- { 705, 3, 1, 0, "FsANDNPDrr", 0, 0|5|(1<<6)|(1<<8)|(85<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #705 = FsANDNPDrr
- { 706, 7, 1, 0, "FsANDNPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(85<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #706 = FsANDNPSrm
- { 707, 3, 1, 0, "FsANDNPSrr", 0, 0|5|(1<<8)|(85<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #707 = FsANDNPSrr
- { 708, 7, 1, 0, "FsANDPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(84<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #708 = FsANDPDrm
- { 709, 3, 1, 0, "FsANDPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(84<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #709 = FsANDPDrr
- { 710, 7, 1, 0, "FsANDPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(84<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #710 = FsANDPSrm
- { 711, 3, 1, 0, "FsANDPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(84<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #711 = FsANDPSrr
- { 712, 1, 1, 0, "FsFLD0SD", 0|(1<<TID::FoldableAsLoad)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(1<<6)|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo103 }, // Inst #712 = FsFLD0SD
- { 713, 1, 1, 0, "FsFLD0SS", 0|(1<<TID::FoldableAsLoad)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(1<<6)|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo104 }, // Inst #713 = FsFLD0SS
- { 714, 6, 1, 0, "FsMOVAPDrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<6)|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo82 }, // Inst #714 = FsMOVAPDrm
- { 715, 2, 1, 0, "FsMOVAPDrr", 0, 0|5|(1<<6)|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo105 }, // Inst #715 = FsMOVAPDrr
- { 716, 6, 1, 0, "FsMOVAPSrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #716 = FsMOVAPSrm
- { 717, 2, 1, 0, "FsMOVAPSrr", 0, 0|5|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo106 }, // Inst #717 = FsMOVAPSrr
- { 718, 7, 1, 0, "FsORPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #718 = FsORPDrm
- { 719, 3, 1, 0, "FsORPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #719 = FsORPDrr
- { 720, 7, 1, 0, "FsORPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #720 = FsORPSrm
- { 721, 3, 1, 0, "FsORPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #721 = FsORPSrr
- { 722, 7, 1, 0, "FsXORPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #722 = FsXORPDrm
- { 723, 3, 1, 0, "FsXORPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #723 = FsXORPDrr
- { 724, 7, 1, 0, "FsXORPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #724 = FsXORPSrm
- { 725, 3, 1, 0, "FsXORPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #725 = FsXORPSrr
- { 726, 6, 1, 0, "GS_MOV32rm", 0|(1<<TID::MayLoad), 0|6|(2<<20)|(139<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #726 = GS_MOV32rm
- { 727, 7, 1, 0, "HADDPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(124<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #727 = HADDPDrm
- { 728, 3, 1, 0, "HADDPDrr", 0, 0|5|(1<<6)|(1<<8)|(124<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #728 = HADDPDrr
- { 729, 7, 1, 0, "HADDPSrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(124<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #729 = HADDPSrm
- { 730, 3, 1, 0, "HADDPSrr", 0, 0|5|(11<<8)|(124<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #730 = HADDPSrr
- { 731, 0, 0, 0, "HLT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(244<<24), NULL, NULL, NULL, 0 }, // Inst #731 = HLT
- { 732, 7, 1, 0, "HSUBPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(125<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #732 = HSUBPDrm
- { 733, 3, 1, 0, "HSUBPDrr", 0, 0|5|(1<<6)|(1<<8)|(125<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #733 = HSUBPDrr
- { 734, 7, 1, 0, "HSUBPSrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(125<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #734 = HSUBPSrm
- { 735, 3, 1, 0, "HSUBPSrr", 0, 0|5|(11<<8)|(125<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #735 = HSUBPSrr
- { 736, 5, 0, 0, "IDIV16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|31|(1<<6)|(247<<24), ImplicitList20, ImplicitList21, Barriers1, OperandInfo30 }, // Inst #736 = IDIV16m
- { 737, 1, 0, 0, "IDIV16r", 0|(1<<TID::UnmodeledSideEffects), 0|23|(1<<6)|(247<<24), ImplicitList20, ImplicitList21, Barriers1, OperandInfo93 }, // Inst #737 = IDIV16r
- { 738, 5, 0, 0, "IDIV32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|31|(247<<24), ImplicitList14, ImplicitList18, Barriers6, OperandInfo30 }, // Inst #738 = IDIV32m
- { 739, 1, 0, 0, "IDIV32r", 0|(1<<TID::UnmodeledSideEffects), 0|23|(247<<24), ImplicitList14, ImplicitList18, Barriers6, OperandInfo57 }, // Inst #739 = IDIV32r
- { 740, 5, 0, 0, "IDIV64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|31|(1<<12)|(247<<24), ImplicitList19, ImplicitList17, Barriers1, OperandInfo30 }, // Inst #740 = IDIV64m
- { 741, 1, 0, 0, "IDIV64r", 0|(1<<TID::UnmodeledSideEffects), 0|23|(1<<12)|(247<<24), ImplicitList19, ImplicitList17, Barriers1, OperandInfo58 }, // Inst #741 = IDIV64r
- { 742, 5, 0, 0, "IDIV8m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|31|(246<<24), ImplicitList12, ImplicitList22, Barriers1, OperandInfo30 }, // Inst #742 = IDIV8m
- { 743, 1, 0, 0, "IDIV8r", 0|(1<<TID::UnmodeledSideEffects), 0|23|(246<<24), ImplicitList12, ImplicitList22, Barriers1, OperandInfo94 }, // Inst #743 = IDIV8r
- { 744, 5, 0, 0, "ILD_F16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|24|(223<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #744 = ILD_F16m
- { 745, 5, 0, 0, "ILD_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|24|(219<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #745 = ILD_F32m
- { 746, 5, 0, 0, "ILD_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(223<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #746 = ILD_F64m
- { 747, 6, 1, 0, "ILD_Fp16m32", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo107 }, // Inst #747 = ILD_Fp16m32
- { 748, 6, 1, 0, "ILD_Fp16m64", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo108 }, // Inst #748 = ILD_Fp16m64
- { 749, 6, 1, 0, "ILD_Fp16m80", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo109 }, // Inst #749 = ILD_Fp16m80
- { 750, 6, 1, 0, "ILD_Fp32m32", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo107 }, // Inst #750 = ILD_Fp32m32
- { 751, 6, 1, 0, "ILD_Fp32m64", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo108 }, // Inst #751 = ILD_Fp32m64
- { 752, 6, 1, 0, "ILD_Fp32m80", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo109 }, // Inst #752 = ILD_Fp32m80
- { 753, 6, 1, 0, "ILD_Fp64m32", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo107 }, // Inst #753 = ILD_Fp64m32
- { 754, 6, 1, 0, "ILD_Fp64m64", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo108 }, // Inst #754 = ILD_Fp64m64
- { 755, 6, 1, 0, "ILD_Fp64m80", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo109 }, // Inst #755 = ILD_Fp64m80
- { 756, 5, 0, 0, "IMUL16m", 0|(1<<TID::MayLoad), 0|29|(1<<6)|(247<<24), ImplicitList12, ImplicitList21, Barriers1, OperandInfo30 }, // Inst #756 = IMUL16m
- { 757, 1, 0, 0, "IMUL16r", 0, 0|21|(1<<6)|(247<<24), ImplicitList12, ImplicitList21, Barriers1, OperandInfo93 }, // Inst #757 = IMUL16r
- { 758, 7, 1, 0, "IMUL16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(175<<24), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #758 = IMUL16rm
- { 759, 7, 1, 0, "IMUL16rmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(2<<13)|(105<<24), NULL, ImplicitList1, Barriers1, OperandInfo110 }, // Inst #759 = IMUL16rmi
- { 760, 7, 1, 0, "IMUL16rmi8", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<13)|(107<<24), NULL, ImplicitList1, Barriers1, OperandInfo110 }, // Inst #760 = IMUL16rmi8
- { 761, 3, 1, 0, "IMUL16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(175<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #761 = IMUL16rr
- { 762, 3, 1, 0, "IMUL16rri", 0, 0|5|(1<<6)|(2<<13)|(105<<24), NULL, ImplicitList1, Barriers1, OperandInfo111 }, // Inst #762 = IMUL16rri
- { 763, 3, 1, 0, "IMUL16rri8", 0, 0|5|(1<<6)|(1<<13)|(107<<24), NULL, ImplicitList1, Barriers1, OperandInfo111 }, // Inst #763 = IMUL16rri8
- { 764, 5, 0, 0, "IMUL32m", 0|(1<<TID::MayLoad), 0|29|(247<<24), ImplicitList13, ImplicitList18, Barriers6, OperandInfo30 }, // Inst #764 = IMUL32m
- { 765, 1, 0, 0, "IMUL32r", 0, 0|21|(247<<24), ImplicitList13, ImplicitList18, Barriers6, OperandInfo57 }, // Inst #765 = IMUL32r
- { 766, 7, 1, 0, "IMUL32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(175<<24), NULL, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #766 = IMUL32rm
- { 767, 7, 1, 0, "IMUL32rmi", 0|(1<<TID::MayLoad), 0|6|(3<<13)|(105<<24), NULL, ImplicitList1, Barriers1, OperandInfo112 }, // Inst #767 = IMUL32rmi
- { 768, 7, 1, 0, "IMUL32rmi8", 0|(1<<TID::MayLoad), 0|6|(1<<13)|(107<<24), NULL, ImplicitList1, Barriers1, OperandInfo112 }, // Inst #768 = IMUL32rmi8
- { 769, 3, 1, 0, "IMUL32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(175<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #769 = IMUL32rr
- { 770, 3, 1, 0, "IMUL32rri", 0, 0|5|(3<<13)|(105<<24), NULL, ImplicitList1, Barriers1, OperandInfo113 }, // Inst #770 = IMUL32rri
- { 771, 3, 1, 0, "IMUL32rri8", 0, 0|5|(1<<13)|(107<<24), NULL, ImplicitList1, Barriers1, OperandInfo113 }, // Inst #771 = IMUL32rri8
- { 772, 5, 0, 0, "IMUL64m", 0|(1<<TID::MayLoad), 0|29|(1<<12)|(247<<24), ImplicitList15, ImplicitList17, Barriers1, OperandInfo30 }, // Inst #772 = IMUL64m
- { 773, 1, 0, 0, "IMUL64r", 0, 0|21|(1<<12)|(247<<24), ImplicitList15, ImplicitList17, Barriers1, OperandInfo58 }, // Inst #773 = IMUL64r
- { 774, 7, 1, 0, "IMUL64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(175<<24), NULL, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #774 = IMUL64rm
- { 775, 7, 1, 0, "IMUL64rmi32", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(3<<13)|(105<<24), NULL, ImplicitList1, Barriers1, OperandInfo114 }, // Inst #775 = IMUL64rmi32
- { 776, 7, 1, 0, "IMUL64rmi8", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(1<<13)|(107<<24), NULL, ImplicitList1, Barriers1, OperandInfo114 }, // Inst #776 = IMUL64rmi8
- { 777, 3, 1, 0, "IMUL64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(175<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #777 = IMUL64rr
- { 778, 3, 1, 0, "IMUL64rri32", 0, 0|5|(1<<12)|(3<<13)|(105<<24), NULL, ImplicitList1, Barriers1, OperandInfo115 }, // Inst #778 = IMUL64rri32
- { 779, 3, 1, 0, "IMUL64rri8", 0, 0|5|(1<<12)|(1<<13)|(107<<24), NULL, ImplicitList1, Barriers1, OperandInfo115 }, // Inst #779 = IMUL64rri8
- { 780, 5, 0, 0, "IMUL8m", 0|(1<<TID::MayLoad), 0|29|(246<<24), ImplicitList11, ImplicitList22, Barriers1, OperandInfo30 }, // Inst #780 = IMUL8m
- { 781, 1, 0, 0, "IMUL8r", 0, 0|21|(246<<24), ImplicitList11, ImplicitList22, Barriers1, OperandInfo94 }, // Inst #781 = IMUL8r
- { 782, 0, 0, 0, "IN16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(109<<24), NULL, NULL, NULL, 0 }, // Inst #782 = IN16
- { 783, 1, 0, 0, "IN16ri", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<13)|(229<<24), NULL, ImplicitList12, NULL, OperandInfo5 }, // Inst #783 = IN16ri
- { 784, 0, 0, 0, "IN16rr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(237<<24), ImplicitList26, ImplicitList12, NULL, 0 }, // Inst #784 = IN16rr
- { 785, 0, 0, 0, "IN32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(109<<24), NULL, NULL, NULL, 0 }, // Inst #785 = IN32
- { 786, 1, 0, 0, "IN32ri", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(229<<24), NULL, ImplicitList13, NULL, OperandInfo5 }, // Inst #786 = IN32ri
- { 787, 0, 0, 0, "IN32rr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(237<<24), ImplicitList26, ImplicitList13, NULL, 0 }, // Inst #787 = IN32rr
- { 788, 0, 0, 0, "IN8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(108<<24), NULL, NULL, NULL, 0 }, // Inst #788 = IN8
- { 789, 1, 0, 0, "IN8ri", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(228<<24), NULL, ImplicitList11, NULL, OperandInfo5 }, // Inst #789 = IN8ri
- { 790, 0, 0, 0, "IN8rr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(236<<24), ImplicitList26, ImplicitList11, NULL, 0 }, // Inst #790 = IN8rr
- { 791, 5, 0, 0, "INC16m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #791 = INC16m
- { 792, 2, 1, 0, "INC16r", 0|(1<<TID::ConvertibleTo3Addr), 0|2|(1<<6)|(64<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #792 = INC16r
- { 793, 5, 0, 0, "INC32m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #793 = INC32m
- { 794, 2, 1, 0, "INC32r", 0|(1<<TID::ConvertibleTo3Addr), 0|2|(64<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #794 = INC32r
- { 795, 5, 0, 0, "INC64_16m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #795 = INC64_16m
- { 796, 2, 1, 0, "INC64_16r", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(1<<6)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #796 = INC64_16r
- { 797, 5, 0, 0, "INC64_32m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #797 = INC64_32m
- { 798, 2, 1, 0, "INC64_32r", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #798 = INC64_32r
- { 799, 5, 0, 0, "INC64m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<12)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #799 = INC64m
- { 800, 2, 1, 0, "INC64r", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(1<<12)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #800 = INC64r
- { 801, 5, 0, 0, "INC8m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(254<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #801 = INC8m
- { 802, 2, 1, 0, "INC8r", 0, 0|16|(254<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #802 = INC8r
- { 803, 8, 1, 0, "INSERTPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(33<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #803 = INSERTPSrm
- { 804, 4, 1, 0, "INSERTPSrr", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(33<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #804 = INSERTPSrr
- { 805, 1, 0, 0, "INT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(205<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #805 = INT
- { 806, 0, 0, 0, "INT3", 0|(1<<TID::UnmodeledSideEffects), 0|1|(204<<24), NULL, NULL, NULL, 0 }, // Inst #806 = INT3
- { 807, 0, 0, 0, "INVD", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(8<<24), NULL, NULL, NULL, 0 }, // Inst #807 = INVD
- { 808, 0, 0, 0, "INVEPT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<8)|(56<<24), NULL, NULL, NULL, 0 }, // Inst #808 = INVEPT
- { 809, 0, 0, 0, "INVLPG", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #809 = INVLPG
- { 810, 0, 0, 0, "INVVPID", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<8)|(56<<24), NULL, NULL, NULL, 0 }, // Inst #810 = INVVPID
- { 811, 0, 0, 0, "IRET16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(207<<24), NULL, NULL, NULL, 0 }, // Inst #811 = IRET16
- { 812, 0, 0, 0, "IRET32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(207<<24), NULL, NULL, NULL, 0 }, // Inst #812 = IRET32
- { 813, 0, 0, 0, "IRET64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(207<<24), NULL, NULL, NULL, 0 }, // Inst #813 = IRET64
- { 814, 5, 0, 0, "ISTT_FP16m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|25|(223<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #814 = ISTT_FP16m
- { 815, 5, 0, 0, "ISTT_FP32m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|25|(219<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #815 = ISTT_FP32m
- { 816, 5, 0, 0, "ISTT_FP64m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|25|(221<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #816 = ISTT_FP64m
- { 817, 6, 0, 0, "ISTT_Fp16m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #817 = ISTT_Fp16m32
- { 818, 6, 0, 0, "ISTT_Fp16m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #818 = ISTT_Fp16m64
- { 819, 6, 0, 0, "ISTT_Fp16m80", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #819 = ISTT_Fp16m80
- { 820, 6, 0, 0, "ISTT_Fp32m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #820 = ISTT_Fp32m32
- { 821, 6, 0, 0, "ISTT_Fp32m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #821 = ISTT_Fp32m64
- { 822, 6, 0, 0, "ISTT_Fp32m80", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #822 = ISTT_Fp32m80
- { 823, 6, 0, 0, "ISTT_Fp64m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #823 = ISTT_Fp64m32
- { 824, 6, 0, 0, "ISTT_Fp64m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #824 = ISTT_Fp64m64
- { 825, 6, 0, 0, "ISTT_Fp64m80", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #825 = ISTT_Fp64m80
- { 826, 5, 0, 0, "IST_F16m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|26|(223<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #826 = IST_F16m
- { 827, 5, 0, 0, "IST_F32m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|26|(219<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #827 = IST_F32m
- { 828, 5, 0, 0, "IST_FP16m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|27|(223<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #828 = IST_FP16m
- { 829, 5, 0, 0, "IST_FP32m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|27|(219<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #829 = IST_FP32m
- { 830, 5, 0, 0, "IST_FP64m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|31|(223<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #830 = IST_FP64m
- { 831, 6, 0, 0, "IST_Fp16m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #831 = IST_Fp16m32
- { 832, 6, 0, 0, "IST_Fp16m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #832 = IST_Fp16m64
- { 833, 6, 0, 0, "IST_Fp16m80", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #833 = IST_Fp16m80
- { 834, 6, 0, 0, "IST_Fp32m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #834 = IST_Fp32m32
- { 835, 6, 0, 0, "IST_Fp32m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #835 = IST_Fp32m64
- { 836, 6, 0, 0, "IST_Fp32m80", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #836 = IST_Fp32m80
- { 837, 6, 0, 0, "IST_Fp64m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #837 = IST_Fp64m32
- { 838, 6, 0, 0, "IST_Fp64m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #838 = IST_Fp64m64
- { 839, 6, 0, 0, "IST_Fp64m80", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #839 = IST_Fp64m80
- { 840, 8, 1, 0, "Int_CMPSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #840 = Int_CMPSDrm
- { 841, 4, 1, 0, "Int_CMPSDrr", 0, 0|5|(11<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #841 = Int_CMPSDrr
- { 842, 8, 1, 0, "Int_CMPSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #842 = Int_CMPSSrm
- { 843, 4, 1, 0, "Int_CMPSSrr", 0, 0|5|(12<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #843 = Int_CMPSSrr
- { 844, 6, 0, 0, "Int_COMISDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(47<<24), NULL, ImplicitList1, Barriers1, OperandInfo74 }, // Inst #844 = Int_COMISDrm
- { 845, 2, 0, 0, "Int_COMISDrr", 0, 0|5|(1<<6)|(1<<8)|(47<<24), NULL, ImplicitList1, Barriers1, OperandInfo75 }, // Inst #845 = Int_COMISDrr
- { 846, 6, 0, 0, "Int_COMISSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(47<<24), NULL, ImplicitList1, Barriers1, OperandInfo74 }, // Inst #846 = Int_COMISSrm
- { 847, 2, 0, 0, "Int_COMISSrr", 0, 0|5|(1<<8)|(47<<24), NULL, ImplicitList1, Barriers1, OperandInfo75 }, // Inst #847 = Int_COMISSrr
- { 848, 6, 1, 0, "Int_CVTDQ2PDrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(230<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #848 = Int_CVTDQ2PDrm
- { 849, 2, 1, 0, "Int_CVTDQ2PDrr", 0, 0|5|(12<<8)|(230<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #849 = Int_CVTDQ2PDrr
- { 850, 6, 1, 0, "Int_CVTDQ2PSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(91<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #850 = Int_CVTDQ2PSrm
- { 851, 2, 1, 0, "Int_CVTDQ2PSrr", 0, 0|5|(1<<8)|(91<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #851 = Int_CVTDQ2PSrr
- { 852, 6, 1, 0, "Int_CVTPD2DQrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(230<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #852 = Int_CVTPD2DQrm
- { 853, 2, 1, 0, "Int_CVTPD2DQrr", 0, 0|5|(11<<8)|(230<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #853 = Int_CVTPD2DQrr
- { 854, 6, 1, 0, "Int_CVTPD2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #854 = Int_CVTPD2PIrm
- { 855, 2, 1, 0, "Int_CVTPD2PIrr", 0, 0|5|(1<<6)|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #855 = Int_CVTPD2PIrr
- { 856, 6, 1, 0, "Int_CVTPD2PSrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(90<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #856 = Int_CVTPD2PSrm
- { 857, 2, 1, 0, "Int_CVTPD2PSrr", 0, 0|5|(1<<6)|(1<<8)|(90<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #857 = Int_CVTPD2PSrr
- { 858, 6, 1, 0, "Int_CVTPI2PDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #858 = Int_CVTPI2PDrm
- { 859, 2, 1, 0, "Int_CVTPI2PDrr", 0, 0|5|(1<<6)|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo119 }, // Inst #859 = Int_CVTPI2PDrr
- { 860, 7, 1, 0, "Int_CVTPI2PSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #860 = Int_CVTPI2PSrm
- { 861, 3, 1, 0, "Int_CVTPI2PSrr", 0, 0|5|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo120 }, // Inst #861 = Int_CVTPI2PSrr
- { 862, 6, 1, 0, "Int_CVTPS2DQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(91<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #862 = Int_CVTPS2DQrm
- { 863, 2, 1, 0, "Int_CVTPS2DQrr", 0, 0|5|(1<<6)|(1<<8)|(91<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #863 = Int_CVTPS2DQrr
- { 864, 6, 1, 0, "Int_CVTPS2PDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(90<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #864 = Int_CVTPS2PDrm
- { 865, 2, 1, 0, "Int_CVTPS2PDrr", 0, 0|5|(1<<8)|(90<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #865 = Int_CVTPS2PDrr
- { 866, 6, 1, 0, "Int_CVTPS2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #866 = Int_CVTPS2PIrm
- { 867, 2, 1, 0, "Int_CVTPS2PIrr", 0, 0|5|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #867 = Int_CVTPS2PIrr
- { 868, 6, 1, 0, "Int_CVTSD2SI64rm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<12)|(45<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #868 = Int_CVTSD2SI64rm
- { 869, 2, 1, 0, "Int_CVTSD2SI64rr", 0, 0|5|(11<<8)|(1<<12)|(45<<24), NULL, NULL, NULL, OperandInfo121 }, // Inst #869 = Int_CVTSD2SI64rr
- { 870, 6, 1, 0, "Int_CVTSD2SIrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(45<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #870 = Int_CVTSD2SIrm
- { 871, 2, 1, 0, "Int_CVTSD2SIrr", 0, 0|5|(11<<8)|(45<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #871 = Int_CVTSD2SIrr
- { 872, 7, 1, 0, "Int_CVTSD2SSrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(90<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #872 = Int_CVTSD2SSrm
- { 873, 3, 1, 0, "Int_CVTSD2SSrr", 0, 0|5|(11<<8)|(90<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #873 = Int_CVTSD2SSrr
- { 874, 7, 1, 0, "Int_CVTSI2SD64rm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<12)|(42<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #874 = Int_CVTSI2SD64rm
- { 875, 3, 1, 0, "Int_CVTSI2SD64rr", 0, 0|5|(11<<8)|(1<<12)|(42<<24), NULL, NULL, NULL, OperandInfo123 }, // Inst #875 = Int_CVTSI2SD64rr
- { 876, 7, 1, 0, "Int_CVTSI2SDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(42<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #876 = Int_CVTSI2SDrm
- { 877, 3, 1, 0, "Int_CVTSI2SDrr", 0, 0|5|(11<<8)|(42<<24), NULL, NULL, NULL, OperandInfo124 }, // Inst #877 = Int_CVTSI2SDrr
- { 878, 7, 1, 0, "Int_CVTSI2SS64rm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<12)|(42<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #878 = Int_CVTSI2SS64rm
- { 879, 3, 1, 0, "Int_CVTSI2SS64rr", 0, 0|5|(12<<8)|(1<<12)|(42<<24), NULL, NULL, NULL, OperandInfo123 }, // Inst #879 = Int_CVTSI2SS64rr
- { 880, 7, 1, 0, "Int_CVTSI2SSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(42<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #880 = Int_CVTSI2SSrm
- { 881, 3, 1, 0, "Int_CVTSI2SSrr", 0, 0|5|(12<<8)|(42<<24), NULL, NULL, NULL, OperandInfo124 }, // Inst #881 = Int_CVTSI2SSrr
- { 882, 7, 1, 0, "Int_CVTSS2SDrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(90<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #882 = Int_CVTSS2SDrm
- { 883, 3, 1, 0, "Int_CVTSS2SDrr", 0, 0|5|(12<<8)|(90<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #883 = Int_CVTSS2SDrr
- { 884, 6, 1, 0, "Int_CVTSS2SI64rm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<12)|(45<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #884 = Int_CVTSS2SI64rm
- { 885, 2, 1, 0, "Int_CVTSS2SI64rr", 0, 0|5|(12<<8)|(1<<12)|(45<<24), NULL, NULL, NULL, OperandInfo121 }, // Inst #885 = Int_CVTSS2SI64rr
- { 886, 6, 1, 0, "Int_CVTSS2SIrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(45<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #886 = Int_CVTSS2SIrm
- { 887, 2, 1, 0, "Int_CVTSS2SIrr", 0, 0|5|(12<<8)|(45<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #887 = Int_CVTSS2SIrr
- { 888, 6, 1, 0, "Int_CVTTPD2DQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(230<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #888 = Int_CVTTPD2DQrm
- { 889, 2, 1, 0, "Int_CVTTPD2DQrr", 0, 0|5|(1<<6)|(1<<8)|(230<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #889 = Int_CVTTPD2DQrr
- { 890, 6, 1, 0, "Int_CVTTPD2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #890 = Int_CVTTPD2PIrm
- { 891, 2, 1, 0, "Int_CVTTPD2PIrr", 0, 0|5|(1<<6)|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #891 = Int_CVTTPD2PIrr
- { 892, 6, 1, 0, "Int_CVTTPS2DQrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(91<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #892 = Int_CVTTPS2DQrm
- { 893, 2, 1, 0, "Int_CVTTPS2DQrr", 0, 0|5|(12<<8)|(91<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #893 = Int_CVTTPS2DQrr
- { 894, 6, 1, 0, "Int_CVTTPS2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #894 = Int_CVTTPS2PIrm
- { 895, 2, 1, 0, "Int_CVTTPS2PIrr", 0, 0|5|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #895 = Int_CVTTPS2PIrr
- { 896, 6, 1, 0, "Int_CVTTSD2SI64rm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<12)|(44<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #896 = Int_CVTTSD2SI64rm
- { 897, 2, 1, 0, "Int_CVTTSD2SI64rr", 0, 0|5|(11<<8)|(1<<12)|(44<<24), NULL, NULL, NULL, OperandInfo121 }, // Inst #897 = Int_CVTTSD2SI64rr
- { 898, 6, 1, 0, "Int_CVTTSD2SIrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(44<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #898 = Int_CVTTSD2SIrm
- { 899, 2, 1, 0, "Int_CVTTSD2SIrr", 0, 0|5|(11<<8)|(44<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #899 = Int_CVTTSD2SIrr
- { 900, 6, 1, 0, "Int_CVTTSS2SI64rm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<12)|(44<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #900 = Int_CVTTSS2SI64rm
- { 901, 2, 1, 0, "Int_CVTTSS2SI64rr", 0, 0|5|(12<<8)|(1<<12)|(44<<24), NULL, NULL, NULL, OperandInfo121 }, // Inst #901 = Int_CVTTSS2SI64rr
- { 902, 6, 1, 0, "Int_CVTTSS2SIrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(44<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #902 = Int_CVTTSS2SIrm
- { 903, 2, 1, 0, "Int_CVTTSS2SIrr", 0, 0|5|(12<<8)|(44<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #903 = Int_CVTTSS2SIrr
- { 904, 6, 0, 0, "Int_UCOMISDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo74 }, // Inst #904 = Int_UCOMISDrm
- { 905, 2, 0, 0, "Int_UCOMISDrr", 0, 0|5|(1<<6)|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo75 }, // Inst #905 = Int_UCOMISDrr
- { 906, 6, 0, 0, "Int_UCOMISSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo74 }, // Inst #906 = Int_UCOMISSrm
- { 907, 2, 0, 0, "Int_UCOMISSrr", 0, 0|5|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo75 }, // Inst #907 = Int_UCOMISSrr
- { 908, 1, 0, 0, "JA", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(135<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #908 = JA
- { 909, 1, 0, 0, "JA8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(119<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #909 = JA8
- { 910, 1, 0, 0, "JAE", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(131<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #910 = JAE
- { 911, 1, 0, 0, "JAE8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(115<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #911 = JAE8
- { 912, 1, 0, 0, "JB", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(130<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #912 = JB
- { 913, 1, 0, 0, "JB8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(114<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #913 = JB8
- { 914, 1, 0, 0, "JBE", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(134<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #914 = JBE
- { 915, 1, 0, 0, "JBE8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(118<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #915 = JBE8
- { 916, 1, 0, 0, "JCXZ8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(227<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #916 = JCXZ8
- { 917, 1, 0, 0, "JE", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(132<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #917 = JE
- { 918, 1, 0, 0, "JE8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(116<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #918 = JE8
- { 919, 1, 0, 0, "JG", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(143<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #919 = JG
- { 920, 1, 0, 0, "JG8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(127<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #920 = JG8
- { 921, 1, 0, 0, "JGE", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(141<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #921 = JGE
- { 922, 1, 0, 0, "JGE8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(125<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #922 = JGE8
- { 923, 1, 0, 0, "JL", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(140<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #923 = JL
- { 924, 1, 0, 0, "JL8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(124<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #924 = JL8
- { 925, 1, 0, 0, "JLE", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(142<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #925 = JLE
- { 926, 1, 0, 0, "JLE8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(126<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #926 = JLE8
- { 927, 1, 0, 0, "JMP", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|1|(233<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #927 = JMP
- { 928, 5, 0, 0, "JMP32m", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::Terminator), 0|28|(255<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #928 = JMP32m
- { 929, 1, 0, 0, "JMP32r", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|20|(255<<24), NULL, NULL, NULL, OperandInfo57 }, // Inst #929 = JMP32r
- { 930, 5, 0, 0, "JMP64m", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::Terminator), 0|28|(255<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #930 = JMP64m
- { 931, 1, 0, 0, "JMP64pcrel32", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(233<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #931 = JMP64pcrel32
- { 932, 1, 0, 0, "JMP64r", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|20|(255<<24), NULL, NULL, NULL, OperandInfo58 }, // Inst #932 = JMP64r
- { 933, 1, 0, 0, "JMP8", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(235<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #933 = JMP8
- { 934, 1, 0, 0, "JNE", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(133<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #934 = JNE
- { 935, 1, 0, 0, "JNE8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(117<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #935 = JNE8
- { 936, 1, 0, 0, "JNO", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(129<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #936 = JNO
- { 937, 1, 0, 0, "JNO8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(113<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #937 = JNO8
- { 938, 1, 0, 0, "JNP", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(139<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #938 = JNP
- { 939, 1, 0, 0, "JNP8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(123<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #939 = JNP8
- { 940, 1, 0, 0, "JNS", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(137<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #940 = JNS
- { 941, 1, 0, 0, "JNS8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(121<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #941 = JNS8
- { 942, 1, 0, 0, "JO", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(128<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #942 = JO
- { 943, 1, 0, 0, "JO8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(112<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #943 = JO8
- { 944, 1, 0, 0, "JP", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(138<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #944 = JP
- { 945, 1, 0, 0, "JP8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(122<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #945 = JP8
- { 946, 1, 0, 0, "JS", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(136<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #946 = JS
- { 947, 1, 0, 0, "JS8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(120<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #947 = JS8
- { 948, 0, 0, 0, "LAHF", 0, 0|1|(159<<24), ImplicitList1, ImplicitList27, NULL, 0 }, // Inst #948 = LAHF
- { 949, 6, 1, 0, "LAR16rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(2<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #949 = LAR16rm
- { 950, 2, 1, 0, "LAR16rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(2<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #950 = LAR16rr
- { 951, 6, 1, 0, "LAR32rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(2<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #951 = LAR32rm
- { 952, 2, 1, 0, "LAR32rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(2<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #952 = LAR32rr
- { 953, 6, 1, 0, "LAR64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(1<<12)|(2<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #953 = LAR64rm
- { 954, 2, 1, 0, "LAR64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(1<<12)|(2<<24), NULL, NULL, NULL, OperandInfo125 }, // Inst #954 = LAR64rr
- { 955, 6, 0, 0, "LCMPXCHG16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(1<<19)|(177<<24), ImplicitList12, ImplicitList28, Barriers1, OperandInfo7 }, // Inst #955 = LCMPXCHG16
- { 956, 6, 0, 0, "LCMPXCHG32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<19)|(177<<24), ImplicitList13, ImplicitList29, Barriers1, OperandInfo11 }, // Inst #956 = LCMPXCHG32
- { 957, 6, 0, 0, "LCMPXCHG64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<12)|(1<<19)|(177<<24), ImplicitList15, ImplicitList30, Barriers1, OperandInfo15 }, // Inst #957 = LCMPXCHG64
- { 958, 6, 0, 0, "LCMPXCHG8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<19)|(176<<24), ImplicitList11, ImplicitList31, Barriers1, OperandInfo20 }, // Inst #958 = LCMPXCHG8
- { 959, 5, 0, 0, "LCMPXCHG8B", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<8)|(1<<19)|(199<<24), ImplicitList6, ImplicitList18, Barriers6, OperandInfo30 }, // Inst #959 = LCMPXCHG8B
- { 960, 6, 1, 0, "LDDQUrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(240<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #960 = LDDQUrm
- { 961, 5, 0, 0, "LDMXCSR", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|26|(1<<8)|(174<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #961 = LDMXCSR
- { 962, 6, 1, 0, "LDS16rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(197<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #962 = LDS16rm
- { 963, 6, 1, 0, "LDS32rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(197<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #963 = LDS32rm
- { 964, 0, 0, 0, "LD_F0", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(238<<24), NULL, NULL, NULL, 0 }, // Inst #964 = LD_F0
- { 965, 0, 0, 0, "LD_F1", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(232<<24), NULL, NULL, NULL, 0 }, // Inst #965 = LD_F1
- { 966, 5, 0, 0, "LD_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|24|(217<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #966 = LD_F32m
- { 967, 5, 0, 0, "LD_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|24|(221<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #967 = LD_F64m
- { 968, 5, 0, 0, "LD_F80m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(219<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #968 = LD_F80m
- { 969, 1, 1, 0, "LD_Fp032", 0|(1<<TID::Rematerializable), 0|(1<<16), NULL, NULL, NULL, OperandInfo100 }, // Inst #969 = LD_Fp032
- { 970, 1, 1, 0, "LD_Fp064", 0|(1<<TID::Rematerializable), 0|(1<<16), NULL, NULL, NULL, OperandInfo101 }, // Inst #970 = LD_Fp064
- { 971, 1, 1, 0, "LD_Fp080", 0|(1<<TID::Rematerializable), 0|(1<<16), NULL, NULL, NULL, OperandInfo102 }, // Inst #971 = LD_Fp080
- { 972, 1, 1, 0, "LD_Fp132", 0|(1<<TID::Rematerializable), 0|(1<<16), NULL, NULL, NULL, OperandInfo100 }, // Inst #972 = LD_Fp132
- { 973, 1, 1, 0, "LD_Fp164", 0|(1<<TID::Rematerializable), 0|(1<<16), NULL, NULL, NULL, OperandInfo101 }, // Inst #973 = LD_Fp164
- { 974, 1, 1, 0, "LD_Fp180", 0|(1<<TID::Rematerializable), 0|(1<<16), NULL, NULL, NULL, OperandInfo102 }, // Inst #974 = LD_Fp180
- { 975, 6, 1, 0, "LD_Fp32m", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo107 }, // Inst #975 = LD_Fp32m
- { 976, 6, 1, 0, "LD_Fp32m64", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo108 }, // Inst #976 = LD_Fp32m64
- { 977, 6, 1, 0, "LD_Fp32m80", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo109 }, // Inst #977 = LD_Fp32m80
- { 978, 6, 1, 0, "LD_Fp64m", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|(1<<16), NULL, NULL, NULL, OperandInfo108 }, // Inst #978 = LD_Fp64m
- { 979, 6, 1, 0, "LD_Fp64m80", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo109 }, // Inst #979 = LD_Fp64m80
- { 980, 6, 1, 0, "LD_Fp80m", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo109 }, // Inst #980 = LD_Fp80m
- { 981, 1, 0, 0, "LD_Frr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(4<<8)|(192<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #981 = LD_Frr
- { 982, 5, 1, 0, "LEA16r", 0, 0|6|(1<<6)|(141<<24), NULL, NULL, NULL, OperandInfo126 }, // Inst #982 = LEA16r
- { 983, 5, 1, 0, "LEA32r", 0|(1<<TID::Rematerializable), 0|6|(141<<24), NULL, NULL, NULL, OperandInfo127 }, // Inst #983 = LEA32r
- { 984, 5, 1, 0, "LEA64_32r", 0, 0|6|(141<<24), NULL, NULL, NULL, OperandInfo127 }, // Inst #984 = LEA64_32r
- { 985, 5, 1, 0, "LEA64r", 0|(1<<TID::Rematerializable), 0|6|(1<<12)|(141<<24), NULL, NULL, NULL, OperandInfo128 }, // Inst #985 = LEA64r
- { 986, 0, 0, 0, "LEAVE", 0|(1<<TID::MayLoad), 0|1|(201<<24), ImplicitList32, ImplicitList32, NULL, 0 }, // Inst #986 = LEAVE
- { 987, 0, 0, 0, "LEAVE64", 0|(1<<TID::MayLoad), 0|1|(201<<24), ImplicitList33, ImplicitList33, NULL, 0 }, // Inst #987 = LEAVE64
- { 988, 6, 1, 0, "LES16rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(196<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #988 = LES16rm
- { 989, 6, 1, 0, "LES32rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(196<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #989 = LES32rm
- { 990, 0, 0, 0, "LFENCE", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|21|(1<<8)|(174<<24), NULL, NULL, NULL, 0 }, // Inst #990 = LFENCE
- { 991, 6, 1, 0, "LFS16rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(180<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #991 = LFS16rm
- { 992, 6, 1, 0, "LFS32rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(180<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #992 = LFS32rm
- { 993, 6, 1, 0, "LFS64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(1<<12)|(180<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #993 = LFS64rm
- { 994, 5, 0, 0, "LGDTm", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #994 = LGDTm
- { 995, 6, 1, 0, "LGS16rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(181<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #995 = LGS16rm
- { 996, 6, 1, 0, "LGS32rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(181<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #996 = LGS32rm
- { 997, 6, 1, 0, "LGS64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(1<<12)|(181<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #997 = LGS64rm
- { 998, 5, 0, 0, "LIDTm", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #998 = LIDTm
- { 999, 5, 0, 0, "LLDT16m", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<8), NULL, NULL, NULL, OperandInfo30 }, // Inst #999 = LLDT16m
- { 1000, 1, 0, 0, "LLDT16r", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<8), NULL, NULL, NULL, OperandInfo93 }, // Inst #1000 = LLDT16r
- { 1001, 5, 0, 0, "LMSW16m", 0|(1<<TID::UnmodeledSideEffects), 0|30|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1001 = LMSW16m
- { 1002, 1, 0, 0, "LMSW16r", 0|(1<<TID::UnmodeledSideEffects), 0|22|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo93 }, // Inst #1002 = LMSW16r
- { 1003, 6, 0, 0, "LOCK_ADD16mi", 0|(1<<TID::UnmodeledSideEffects), 0|24|(2<<13)|(1<<19)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1003 = LOCK_ADD16mi
- { 1004, 6, 0, 0, "LOCK_ADD16mi8", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<6)|(1<<13)|(1<<19)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1004 = LOCK_ADD16mi8
- { 1005, 6, 0, 0, "LOCK_ADD16mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<19)|(1<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #1005 = LOCK_ADD16mr
- { 1006, 6, 0, 0, "LOCK_ADD32mi", 0|(1<<TID::UnmodeledSideEffects), 0|24|(3<<13)|(1<<19)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1006 = LOCK_ADD32mi
- { 1007, 6, 0, 0, "LOCK_ADD32mi8", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<13)|(1<<19)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1007 = LOCK_ADD32mi8
- { 1008, 6, 0, 0, "LOCK_ADD32mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<19)|(1<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #1008 = LOCK_ADD32mr
- { 1009, 6, 0, 0, "LOCK_ADD64mi32", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<12)|(3<<13)|(1<<19)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1009 = LOCK_ADD64mi32
- { 1010, 6, 0, 0, "LOCK_ADD64mi8", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<12)|(1<<13)|(1<<19)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1010 = LOCK_ADD64mi8
- { 1011, 6, 0, 0, "LOCK_ADD64mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<12)|(1<<19)|(3<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #1011 = LOCK_ADD64mr
- { 1012, 6, 0, 0, "LOCK_ADD8mi", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<13)|(1<<19)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1012 = LOCK_ADD8mi
- { 1013, 6, 0, 0, "LOCK_ADD8mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<19), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #1013 = LOCK_ADD8mr
- { 1014, 5, 0, 0, "LOCK_DEC16m", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<6)|(1<<19)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1014 = LOCK_DEC16m
- { 1015, 5, 0, 0, "LOCK_DEC32m", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<19)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1015 = LOCK_DEC32m
- { 1016, 5, 0, 0, "LOCK_DEC64m", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<12)|(1<<19)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1016 = LOCK_DEC64m
- { 1017, 5, 0, 0, "LOCK_DEC8m", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<19)|(254<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1017 = LOCK_DEC8m
- { 1018, 5, 0, 0, "LOCK_INC16m", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<6)|(1<<19)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1018 = LOCK_INC16m
- { 1019, 5, 0, 0, "LOCK_INC32m", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<19)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1019 = LOCK_INC32m
- { 1020, 5, 0, 0, "LOCK_INC64m", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<12)|(1<<19)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1020 = LOCK_INC64m
- { 1021, 5, 0, 0, "LOCK_INC8m", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<19)|(254<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1021 = LOCK_INC8m
- { 1022, 6, 0, 0, "LOCK_SUB16mi", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<6)|(2<<13)|(1<<19)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1022 = LOCK_SUB16mi
- { 1023, 6, 0, 0, "LOCK_SUB16mi8", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<6)|(1<<13)|(1<<19)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1023 = LOCK_SUB16mi8
- { 1024, 6, 0, 0, "LOCK_SUB16mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<19)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #1024 = LOCK_SUB16mr
- { 1025, 6, 0, 0, "LOCK_SUB32mi", 0|(1<<TID::UnmodeledSideEffects), 0|29|(3<<13)|(1<<19)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1025 = LOCK_SUB32mi
- { 1026, 6, 0, 0, "LOCK_SUB32mi8", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<13)|(1<<19)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1026 = LOCK_SUB32mi8
- { 1027, 6, 0, 0, "LOCK_SUB32mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<19)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #1027 = LOCK_SUB32mr
- { 1028, 6, 0, 0, "LOCK_SUB64mi32", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<12)|(3<<13)|(1<<19)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1028 = LOCK_SUB64mi32
- { 1029, 6, 0, 0, "LOCK_SUB64mi8", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<12)|(1<<13)|(1<<19)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1029 = LOCK_SUB64mi8
- { 1030, 6, 0, 0, "LOCK_SUB64mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<12)|(1<<19)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #1030 = LOCK_SUB64mr
- { 1031, 6, 0, 0, "LOCK_SUB8mi", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<13)|(1<<19)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1031 = LOCK_SUB8mi
- { 1032, 6, 0, 0, "LOCK_SUB8mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<19)|(40<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #1032 = LOCK_SUB8mr
- { 1033, 0, 0, 0, "LODSB", 0|(1<<TID::UnmodeledSideEffects), 0|1|(172<<24), NULL, NULL, NULL, 0 }, // Inst #1033 = LODSB
- { 1034, 0, 0, 0, "LODSD", 0|(1<<TID::UnmodeledSideEffects), 0|1|(173<<24), NULL, NULL, NULL, 0 }, // Inst #1034 = LODSD
- { 1035, 0, 0, 0, "LODSQ", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(173<<24), NULL, NULL, NULL, 0 }, // Inst #1035 = LODSQ
- { 1036, 0, 0, 0, "LODSW", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(173<<24), NULL, NULL, NULL, 0 }, // Inst #1036 = LODSW
- { 1037, 1, 1, 0, "LOOP", 0|(1<<TID::UnmodeledSideEffects), 0|1|(226<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1037 = LOOP
- { 1038, 1, 1, 0, "LOOPE", 0|(1<<TID::UnmodeledSideEffects), 0|1|(225<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1038 = LOOPE
- { 1039, 1, 1, 0, "LOOPNE", 0|(1<<TID::UnmodeledSideEffects), 0|1|(224<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1039 = LOOPNE
- { 1040, 0, 0, 0, "LRET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(7<<16)|(203<<24), NULL, NULL, NULL, 0 }, // Inst #1040 = LRET
- { 1041, 1, 0, 0, "LRETI", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(2<<13)|(7<<16)|(202<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1041 = LRETI
- { 1042, 6, 1, 0, "LSL16rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(3<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1042 = LSL16rm
- { 1043, 2, 1, 0, "LSL16rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(3<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #1043 = LSL16rr
- { 1044, 6, 1, 0, "LSL32rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(3<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1044 = LSL32rm
- { 1045, 2, 1, 0, "LSL32rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(3<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #1045 = LSL32rr
- { 1046, 6, 1, 0, "LSL64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(1<<12)|(3<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1046 = LSL64rm
- { 1047, 2, 1, 0, "LSL64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(1<<12)|(3<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #1047 = LSL64rr
- { 1048, 6, 1, 0, "LSS16rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(178<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1048 = LSS16rm
- { 1049, 6, 1, 0, "LSS32rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(178<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1049 = LSS32rm
- { 1050, 6, 1, 0, "LSS64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(1<<12)|(178<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1050 = LSS64rm
- { 1051, 5, 0, 0, "LTRm", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<8), NULL, NULL, NULL, OperandInfo30 }, // Inst #1051 = LTRm
- { 1052, 1, 0, 0, "LTRr", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<8), NULL, NULL, NULL, OperandInfo93 }, // Inst #1052 = LTRr
- { 1053, 7, 1, 0, "LXADD16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(1<<6)|(1<<8)|(1<<19)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #1053 = LXADD16
- { 1054, 7, 1, 0, "LXADD32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(1<<8)|(1<<19)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #1054 = LXADD32
- { 1055, 7, 1, 0, "LXADD64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(1<<8)|(1<<12)|(1<<19)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #1055 = LXADD64
- { 1056, 7, 1, 0, "LXADD8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(1<<8)|(1<<19)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #1056 = LXADD8
- { 1057, 2, 0, 0, "MASKMOVDQU", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(247<<24), ImplicitList34, NULL, NULL, OperandInfo75 }, // Inst #1057 = MASKMOVDQU
- { 1058, 2, 0, 0, "MASKMOVDQU64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(247<<24), ImplicitList35, NULL, NULL, OperandInfo75 }, // Inst #1058 = MASKMOVDQU64
- { 1059, 7, 1, 0, "MAXPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(95<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1059 = MAXPDrm
- { 1060, 7, 1, 0, "MAXPDrm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(95<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1060 = MAXPDrm_Int
- { 1061, 3, 1, 0, "MAXPDrr", 0, 0|5|(1<<6)|(1<<8)|(95<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1061 = MAXPDrr
- { 1062, 3, 1, 0, "MAXPDrr_Int", 0, 0|5|(1<<6)|(1<<8)|(95<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1062 = MAXPDrr_Int
- { 1063, 7, 1, 0, "MAXPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(95<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1063 = MAXPSrm
- { 1064, 7, 1, 0, "MAXPSrm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(95<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1064 = MAXPSrm_Int
- { 1065, 3, 1, 0, "MAXPSrr", 0, 0|5|(1<<8)|(95<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1065 = MAXPSrr
- { 1066, 3, 1, 0, "MAXPSrr_Int", 0, 0|5|(1<<8)|(95<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1066 = MAXPSrr_Int
- { 1067, 7, 1, 0, "MAXSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(95<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #1067 = MAXSDrm
- { 1068, 7, 1, 0, "MAXSDrm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(95<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1068 = MAXSDrm_Int
- { 1069, 3, 1, 0, "MAXSDrr", 0, 0|5|(11<<8)|(95<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #1069 = MAXSDrr
- { 1070, 3, 1, 0, "MAXSDrr_Int", 0, 0|5|(11<<8)|(95<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1070 = MAXSDrr_Int
- { 1071, 7, 1, 0, "MAXSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(95<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #1071 = MAXSSrm
- { 1072, 7, 1, 0, "MAXSSrm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(95<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1072 = MAXSSrm_Int
- { 1073, 3, 1, 0, "MAXSSrr", 0, 0|5|(12<<8)|(95<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #1073 = MAXSSrr
- { 1074, 3, 1, 0, "MAXSSrr_Int", 0, 0|5|(12<<8)|(95<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1074 = MAXSSrr_Int
- { 1075, 0, 0, 0, "MFENCE", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|22|(1<<8)|(174<<24), NULL, NULL, NULL, 0 }, // Inst #1075 = MFENCE
- { 1076, 7, 1, 0, "MINPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1076 = MINPDrm
- { 1077, 7, 1, 0, "MINPDrm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1077 = MINPDrm_Int
- { 1078, 3, 1, 0, "MINPDrr", 0, 0|5|(1<<6)|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1078 = MINPDrr
- { 1079, 3, 1, 0, "MINPDrr_Int", 0, 0|5|(1<<6)|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1079 = MINPDrr_Int
- { 1080, 7, 1, 0, "MINPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1080 = MINPSrm
- { 1081, 7, 1, 0, "MINPSrm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1081 = MINPSrm_Int
- { 1082, 3, 1, 0, "MINPSrr", 0, 0|5|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1082 = MINPSrr
- { 1083, 3, 1, 0, "MINPSrr_Int", 0, 0|5|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1083 = MINPSrr_Int
- { 1084, 7, 1, 0, "MINSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(93<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #1084 = MINSDrm
- { 1085, 7, 1, 0, "MINSDrm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(93<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1085 = MINSDrm_Int
- { 1086, 3, 1, 0, "MINSDrr", 0, 0|5|(11<<8)|(93<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #1086 = MINSDrr
- { 1087, 3, 1, 0, "MINSDrr_Int", 0, 0|5|(11<<8)|(93<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1087 = MINSDrr_Int
- { 1088, 7, 1, 0, "MINSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(93<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #1088 = MINSSrm
- { 1089, 7, 1, 0, "MINSSrm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(93<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1089 = MINSSrm_Int
- { 1090, 3, 1, 0, "MINSSrr", 0, 0|5|(12<<8)|(93<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #1090 = MINSSrr
- { 1091, 3, 1, 0, "MINSSrr_Int", 0, 0|5|(12<<8)|(93<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1091 = MINSSrr_Int
- { 1092, 6, 1, 0, "MMX_CVTPD2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1092 = MMX_CVTPD2PIrm
- { 1093, 2, 1, 0, "MMX_CVTPD2PIrr", 0, 0|5|(1<<6)|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #1093 = MMX_CVTPD2PIrr
- { 1094, 6, 1, 0, "MMX_CVTPI2PDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1094 = MMX_CVTPI2PDrm
- { 1095, 2, 1, 0, "MMX_CVTPI2PDrr", 0, 0|5|(1<<6)|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo119 }, // Inst #1095 = MMX_CVTPI2PDrr
- { 1096, 6, 1, 0, "MMX_CVTPI2PSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1096 = MMX_CVTPI2PSrm
- { 1097, 2, 1, 0, "MMX_CVTPI2PSrr", 0, 0|5|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo119 }, // Inst #1097 = MMX_CVTPI2PSrr
- { 1098, 6, 1, 0, "MMX_CVTPS2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1098 = MMX_CVTPS2PIrm
- { 1099, 2, 1, 0, "MMX_CVTPS2PIrr", 0, 0|5|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #1099 = MMX_CVTPS2PIrr
- { 1100, 6, 1, 0, "MMX_CVTTPD2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1100 = MMX_CVTTPD2PIrm
- { 1101, 2, 1, 0, "MMX_CVTTPD2PIrr", 0, 0|5|(1<<6)|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #1101 = MMX_CVTTPD2PIrr
- { 1102, 6, 1, 0, "MMX_CVTTPS2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1102 = MMX_CVTTPS2PIrm
- { 1103, 2, 1, 0, "MMX_CVTTPS2PIrr", 0, 0|5|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #1103 = MMX_CVTTPS2PIrr
- { 1104, 0, 0, 0, "MMX_EMMS", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(119<<24), NULL, NULL, NULL, 0 }, // Inst #1104 = MMX_EMMS
- { 1105, 0, 0, 0, "MMX_FEMMS", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(14<<24), NULL, NULL, NULL, 0 }, // Inst #1105 = MMX_FEMMS
- { 1106, 2, 0, 0, "MMX_MASKMOVQ", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(247<<24), ImplicitList34, NULL, NULL, OperandInfo129 }, // Inst #1106 = MMX_MASKMOVQ
- { 1107, 2, 0, 0, "MMX_MASKMOVQ64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(247<<24), ImplicitList35, NULL, NULL, OperandInfo129 }, // Inst #1107 = MMX_MASKMOVQ64
- { 1108, 2, 1, 0, "MMX_MOVD64from64rr", 0, 0|3|(1<<8)|(1<<12)|(126<<24), NULL, NULL, NULL, OperandInfo130 }, // Inst #1108 = MMX_MOVD64from64rr
- { 1109, 2, 0, 0, "MMX_MOVD64grr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(126<<24), NULL, NULL, NULL, OperandInfo131 }, // Inst #1109 = MMX_MOVD64grr
- { 1110, 6, 0, 0, "MMX_MOVD64mr", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(126<<24), NULL, NULL, NULL, OperandInfo132 }, // Inst #1110 = MMX_MOVD64mr
- { 1111, 6, 1, 0, "MMX_MOVD64rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1111 = MMX_MOVD64rm
- { 1112, 2, 1, 0, "MMX_MOVD64rr", 0, 0|5|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo133 }, // Inst #1112 = MMX_MOVD64rr
- { 1113, 2, 1, 0, "MMX_MOVD64rrv164", 0, 0|5|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1113 = MMX_MOVD64rrv164
- { 1114, 2, 1, 0, "MMX_MOVD64to64rr", 0, 0|5|(1<<8)|(1<<12)|(110<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1114 = MMX_MOVD64to64rr
- { 1115, 2, 1, 0, "MMX_MOVDQ2Qrr", 0, 0|5|(11<<8)|(1<<13)|(214<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #1115 = MMX_MOVDQ2Qrr
- { 1116, 6, 0, 0, "MMX_MOVNTQmr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(231<<24), NULL, NULL, NULL, OperandInfo132 }, // Inst #1116 = MMX_MOVNTQmr
- { 1117, 2, 1, 0, "MMX_MOVQ2DQrr", 0, 0|5|(12<<8)|(1<<13)|(214<<24), NULL, NULL, NULL, OperandInfo119 }, // Inst #1117 = MMX_MOVQ2DQrr
- { 1118, 2, 1, 0, "MMX_MOVQ2FR64rr", 0, 0|5|(12<<8)|(1<<13)|(214<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1118 = MMX_MOVQ2FR64rr
- { 1119, 6, 0, 0, "MMX_MOVQ64gmr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(1<<12)|(126<<24), NULL, NULL, NULL, OperandInfo132 }, // Inst #1119 = MMX_MOVQ64gmr
- { 1120, 6, 0, 0, "MMX_MOVQ64mr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(127<<24), NULL, NULL, NULL, OperandInfo132 }, // Inst #1120 = MMX_MOVQ64mr
- { 1121, 6, 1, 0, "MMX_MOVQ64rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<8)|(111<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1121 = MMX_MOVQ64rm
- { 1122, 2, 1, 0, "MMX_MOVQ64rr", 0, 0|5|(1<<8)|(111<<24), NULL, NULL, NULL, OperandInfo129 }, // Inst #1122 = MMX_MOVQ64rr
- { 1123, 6, 1, 0, "MMX_MOVZDI2PDIrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1123 = MMX_MOVZDI2PDIrm
- { 1124, 2, 1, 0, "MMX_MOVZDI2PDIrr", 0, 0|5|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo133 }, // Inst #1124 = MMX_MOVZDI2PDIrr
- { 1125, 7, 1, 0, "MMX_PACKSSDWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(107<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1125 = MMX_PACKSSDWrm
- { 1126, 3, 1, 0, "MMX_PACKSSDWrr", 0, 0|5|(1<<8)|(107<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1126 = MMX_PACKSSDWrr
- { 1127, 7, 1, 0, "MMX_PACKSSWBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(99<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1127 = MMX_PACKSSWBrm
- { 1128, 3, 1, 0, "MMX_PACKSSWBrr", 0, 0|5|(1<<8)|(99<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1128 = MMX_PACKSSWBrr
- { 1129, 7, 1, 0, "MMX_PACKUSWBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(103<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1129 = MMX_PACKUSWBrm
- { 1130, 3, 1, 0, "MMX_PACKUSWBrr", 0, 0|5|(1<<8)|(103<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1130 = MMX_PACKUSWBrr
- { 1131, 7, 1, 0, "MMX_PADDBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(252<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1131 = MMX_PADDBrm
- { 1132, 3, 1, 0, "MMX_PADDBrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(252<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1132 = MMX_PADDBrr
- { 1133, 7, 1, 0, "MMX_PADDDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(254<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1133 = MMX_PADDDrm
- { 1134, 3, 1, 0, "MMX_PADDDrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(254<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1134 = MMX_PADDDrr
- { 1135, 7, 1, 0, "MMX_PADDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(212<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1135 = MMX_PADDQrm
- { 1136, 3, 1, 0, "MMX_PADDQrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(212<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1136 = MMX_PADDQrr
- { 1137, 7, 1, 0, "MMX_PADDSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(236<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1137 = MMX_PADDSBrm
- { 1138, 3, 1, 0, "MMX_PADDSBrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(236<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1138 = MMX_PADDSBrr
- { 1139, 7, 1, 0, "MMX_PADDSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(237<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1139 = MMX_PADDSWrm
- { 1140, 3, 1, 0, "MMX_PADDSWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(237<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1140 = MMX_PADDSWrr
- { 1141, 7, 1, 0, "MMX_PADDUSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(220<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1141 = MMX_PADDUSBrm
- { 1142, 3, 1, 0, "MMX_PADDUSBrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(220<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1142 = MMX_PADDUSBrr
- { 1143, 7, 1, 0, "MMX_PADDUSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(221<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1143 = MMX_PADDUSWrm
- { 1144, 3, 1, 0, "MMX_PADDUSWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(221<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1144 = MMX_PADDUSWrr
- { 1145, 7, 1, 0, "MMX_PADDWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(253<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1145 = MMX_PADDWrm
- { 1146, 3, 1, 0, "MMX_PADDWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(253<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1146 = MMX_PADDWrr
- { 1147, 7, 1, 0, "MMX_PANDNrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(223<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1147 = MMX_PANDNrm
- { 1148, 3, 1, 0, "MMX_PANDNrr", 0, 0|5|(1<<8)|(223<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1148 = MMX_PANDNrr
- { 1149, 7, 1, 0, "MMX_PANDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(219<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1149 = MMX_PANDrm
- { 1150, 3, 1, 0, "MMX_PANDrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(219<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1150 = MMX_PANDrr
- { 1151, 7, 1, 0, "MMX_PAVGBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(224<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1151 = MMX_PAVGBrm
- { 1152, 3, 1, 0, "MMX_PAVGBrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(224<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1152 = MMX_PAVGBrr
- { 1153, 7, 1, 0, "MMX_PAVGWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(227<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1153 = MMX_PAVGWrm
- { 1154, 3, 1, 0, "MMX_PAVGWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(227<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1154 = MMX_PAVGWrr
- { 1155, 7, 1, 0, "MMX_PCMPEQBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(116<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1155 = MMX_PCMPEQBrm
- { 1156, 3, 1, 0, "MMX_PCMPEQBrr", 0, 0|5|(1<<8)|(116<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1156 = MMX_PCMPEQBrr
- { 1157, 7, 1, 0, "MMX_PCMPEQDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1157 = MMX_PCMPEQDrm
- { 1158, 3, 1, 0, "MMX_PCMPEQDrr", 0, 0|5|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1158 = MMX_PCMPEQDrr
- { 1159, 7, 1, 0, "MMX_PCMPEQWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(117<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1159 = MMX_PCMPEQWrm
- { 1160, 3, 1, 0, "MMX_PCMPEQWrr", 0, 0|5|(1<<8)|(117<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1160 = MMX_PCMPEQWrr
- { 1161, 7, 1, 0, "MMX_PCMPGTBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(100<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1161 = MMX_PCMPGTBrm
- { 1162, 3, 1, 0, "MMX_PCMPGTBrr", 0, 0|5|(1<<8)|(100<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1162 = MMX_PCMPGTBrr
- { 1163, 7, 1, 0, "MMX_PCMPGTDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(102<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1163 = MMX_PCMPGTDrm
- { 1164, 3, 1, 0, "MMX_PCMPGTDrr", 0, 0|5|(1<<8)|(102<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1164 = MMX_PCMPGTDrr
- { 1165, 7, 1, 0, "MMX_PCMPGTWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(101<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1165 = MMX_PCMPGTWrm
- { 1166, 3, 1, 0, "MMX_PCMPGTWrr", 0, 0|5|(1<<8)|(101<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1166 = MMX_PCMPGTWrr
- { 1167, 3, 1, 0, "MMX_PEXTRWri", 0, 0|5|(1<<8)|(1<<13)|(197<<24), NULL, NULL, NULL, OperandInfo138 }, // Inst #1167 = MMX_PEXTRWri
- { 1168, 8, 1, 0, "MMX_PINSRWrmi", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<13)|(196<<24), NULL, NULL, NULL, OperandInfo139 }, // Inst #1168 = MMX_PINSRWrmi
- { 1169, 4, 1, 0, "MMX_PINSRWrri", 0, 0|5|(1<<8)|(1<<13)|(196<<24), NULL, NULL, NULL, OperandInfo140 }, // Inst #1169 = MMX_PINSRWrri
- { 1170, 7, 1, 0, "MMX_PMADDWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(245<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1170 = MMX_PMADDWDrm
- { 1171, 3, 1, 0, "MMX_PMADDWDrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(245<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1171 = MMX_PMADDWDrr
- { 1172, 7, 1, 0, "MMX_PMAXSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(238<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1172 = MMX_PMAXSWrm
- { 1173, 3, 1, 0, "MMX_PMAXSWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(238<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1173 = MMX_PMAXSWrr
- { 1174, 7, 1, 0, "MMX_PMAXUBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(222<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1174 = MMX_PMAXUBrm
- { 1175, 3, 1, 0, "MMX_PMAXUBrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(222<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1175 = MMX_PMAXUBrr
- { 1176, 7, 1, 0, "MMX_PMINSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(234<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1176 = MMX_PMINSWrm
- { 1177, 3, 1, 0, "MMX_PMINSWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(234<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1177 = MMX_PMINSWrr
- { 1178, 7, 1, 0, "MMX_PMINUBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(218<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1178 = MMX_PMINUBrm
- { 1179, 3, 1, 0, "MMX_PMINUBrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(218<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1179 = MMX_PMINUBrr
- { 1180, 2, 1, 0, "MMX_PMOVMSKBrr", 0, 0|5|(1<<8)|(215<<24), NULL, NULL, NULL, OperandInfo131 }, // Inst #1180 = MMX_PMOVMSKBrr
- { 1181, 7, 1, 0, "MMX_PMULHUWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(228<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1181 = MMX_PMULHUWrm
- { 1182, 3, 1, 0, "MMX_PMULHUWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(228<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1182 = MMX_PMULHUWrr
- { 1183, 7, 1, 0, "MMX_PMULHWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(229<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1183 = MMX_PMULHWrm
- { 1184, 3, 1, 0, "MMX_PMULHWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(229<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1184 = MMX_PMULHWrr
- { 1185, 7, 1, 0, "MMX_PMULLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(213<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1185 = MMX_PMULLWrm
- { 1186, 3, 1, 0, "MMX_PMULLWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(213<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1186 = MMX_PMULLWrr
- { 1187, 7, 1, 0, "MMX_PMULUDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(244<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1187 = MMX_PMULUDQrm
- { 1188, 3, 1, 0, "MMX_PMULUDQrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(244<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1188 = MMX_PMULUDQrr
- { 1189, 7, 1, 0, "MMX_PORrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(235<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1189 = MMX_PORrm
- { 1190, 3, 1, 0, "MMX_PORrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(235<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1190 = MMX_PORrr
- { 1191, 7, 1, 0, "MMX_PSADBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(246<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1191 = MMX_PSADBWrm
- { 1192, 3, 1, 0, "MMX_PSADBWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(246<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1192 = MMX_PSADBWrr
- { 1193, 7, 1, 0, "MMX_PSHUFWmi", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo141 }, // Inst #1193 = MMX_PSHUFWmi
- { 1194, 3, 1, 0, "MMX_PSHUFWri", 0, 0|5|(1<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo142 }, // Inst #1194 = MMX_PSHUFWri
- { 1195, 3, 1, 0, "MMX_PSLLDri", 0, 0|22|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1195 = MMX_PSLLDri
- { 1196, 7, 1, 0, "MMX_PSLLDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(242<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1196 = MMX_PSLLDrm
- { 1197, 3, 1, 0, "MMX_PSLLDrr", 0, 0|5|(1<<8)|(242<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1197 = MMX_PSLLDrr
- { 1198, 3, 1, 0, "MMX_PSLLQri", 0, 0|22|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1198 = MMX_PSLLQri
- { 1199, 7, 1, 0, "MMX_PSLLQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(243<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1199 = MMX_PSLLQrm
- { 1200, 3, 1, 0, "MMX_PSLLQrr", 0, 0|5|(1<<8)|(243<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1200 = MMX_PSLLQrr
- { 1201, 3, 1, 0, "MMX_PSLLWri", 0, 0|22|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1201 = MMX_PSLLWri
- { 1202, 7, 1, 0, "MMX_PSLLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(241<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1202 = MMX_PSLLWrm
- { 1203, 3, 1, 0, "MMX_PSLLWrr", 0, 0|5|(1<<8)|(241<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1203 = MMX_PSLLWrr
- { 1204, 3, 1, 0, "MMX_PSRADri", 0, 0|20|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1204 = MMX_PSRADri
- { 1205, 7, 1, 0, "MMX_PSRADrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(226<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1205 = MMX_PSRADrm
- { 1206, 3, 1, 0, "MMX_PSRADrr", 0, 0|5|(1<<8)|(226<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1206 = MMX_PSRADrr
- { 1207, 3, 1, 0, "MMX_PSRAWri", 0, 0|20|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1207 = MMX_PSRAWri
- { 1208, 7, 1, 0, "MMX_PSRAWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(225<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1208 = MMX_PSRAWrm
- { 1209, 3, 1, 0, "MMX_PSRAWrr", 0, 0|5|(1<<8)|(225<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1209 = MMX_PSRAWrr
- { 1210, 3, 1, 0, "MMX_PSRLDri", 0, 0|18|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1210 = MMX_PSRLDri
- { 1211, 7, 1, 0, "MMX_PSRLDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(210<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1211 = MMX_PSRLDrm
- { 1212, 3, 1, 0, "MMX_PSRLDrr", 0, 0|5|(1<<8)|(210<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1212 = MMX_PSRLDrr
- { 1213, 3, 1, 0, "MMX_PSRLQri", 0, 0|18|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1213 = MMX_PSRLQri
- { 1214, 7, 1, 0, "MMX_PSRLQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(211<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1214 = MMX_PSRLQrm
- { 1215, 3, 1, 0, "MMX_PSRLQrr", 0, 0|5|(1<<8)|(211<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1215 = MMX_PSRLQrr
- { 1216, 3, 1, 0, "MMX_PSRLWri", 0, 0|18|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1216 = MMX_PSRLWri
- { 1217, 7, 1, 0, "MMX_PSRLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(209<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1217 = MMX_PSRLWrm
- { 1218, 3, 1, 0, "MMX_PSRLWrr", 0, 0|5|(1<<8)|(209<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1218 = MMX_PSRLWrr
- { 1219, 7, 1, 0, "MMX_PSUBBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(248<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1219 = MMX_PSUBBrm
- { 1220, 3, 1, 0, "MMX_PSUBBrr", 0, 0|5|(1<<8)|(248<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1220 = MMX_PSUBBrr
- { 1221, 7, 1, 0, "MMX_PSUBDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(250<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1221 = MMX_PSUBDrm
- { 1222, 3, 1, 0, "MMX_PSUBDrr", 0, 0|5|(1<<8)|(250<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1222 = MMX_PSUBDrr
- { 1223, 7, 1, 0, "MMX_PSUBQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(251<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1223 = MMX_PSUBQrm
- { 1224, 3, 1, 0, "MMX_PSUBQrr", 0, 0|5|(1<<8)|(251<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1224 = MMX_PSUBQrr
- { 1225, 7, 1, 0, "MMX_PSUBSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(232<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1225 = MMX_PSUBSBrm
- { 1226, 3, 1, 0, "MMX_PSUBSBrr", 0, 0|5|(1<<8)|(232<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1226 = MMX_PSUBSBrr
- { 1227, 7, 1, 0, "MMX_PSUBSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(233<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1227 = MMX_PSUBSWrm
- { 1228, 3, 1, 0, "MMX_PSUBSWrr", 0, 0|5|(1<<8)|(233<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1228 = MMX_PSUBSWrr
- { 1229, 7, 1, 0, "MMX_PSUBUSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(216<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1229 = MMX_PSUBUSBrm
- { 1230, 3, 1, 0, "MMX_PSUBUSBrr", 0, 0|5|(1<<8)|(216<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1230 = MMX_PSUBUSBrr
- { 1231, 7, 1, 0, "MMX_PSUBUSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(217<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1231 = MMX_PSUBUSWrm
- { 1232, 3, 1, 0, "MMX_PSUBUSWrr", 0, 0|5|(1<<8)|(217<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1232 = MMX_PSUBUSWrr
- { 1233, 7, 1, 0, "MMX_PSUBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(249<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1233 = MMX_PSUBWrm
- { 1234, 3, 1, 0, "MMX_PSUBWrr", 0, 0|5|(1<<8)|(249<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1234 = MMX_PSUBWrr
- { 1235, 7, 1, 0, "MMX_PUNPCKHBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(104<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1235 = MMX_PUNPCKHBWrm
- { 1236, 3, 1, 0, "MMX_PUNPCKHBWrr", 0, 0|5|(1<<8)|(104<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1236 = MMX_PUNPCKHBWrr
- { 1237, 7, 1, 0, "MMX_PUNPCKHDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(106<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1237 = MMX_PUNPCKHDQrm
- { 1238, 3, 1, 0, "MMX_PUNPCKHDQrr", 0, 0|5|(1<<8)|(106<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1238 = MMX_PUNPCKHDQrr
- { 1239, 7, 1, 0, "MMX_PUNPCKHWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(105<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1239 = MMX_PUNPCKHWDrm
- { 1240, 3, 1, 0, "MMX_PUNPCKHWDrr", 0, 0|5|(1<<8)|(105<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1240 = MMX_PUNPCKHWDrr
- { 1241, 7, 1, 0, "MMX_PUNPCKLBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(96<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1241 = MMX_PUNPCKLBWrm
- { 1242, 3, 1, 0, "MMX_PUNPCKLBWrr", 0, 0|5|(1<<8)|(96<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1242 = MMX_PUNPCKLBWrr
- { 1243, 7, 1, 0, "MMX_PUNPCKLDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(98<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1243 = MMX_PUNPCKLDQrm
- { 1244, 3, 1, 0, "MMX_PUNPCKLDQrr", 0, 0|5|(1<<8)|(98<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1244 = MMX_PUNPCKLDQrr
- { 1245, 7, 1, 0, "MMX_PUNPCKLWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(97<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1245 = MMX_PUNPCKLWDrm
- { 1246, 3, 1, 0, "MMX_PUNPCKLWDrr", 0, 0|5|(1<<8)|(97<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1246 = MMX_PUNPCKLWDrr
- { 1247, 7, 1, 0, "MMX_PXORrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1247 = MMX_PXORrm
- { 1248, 3, 1, 0, "MMX_PXORrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1248 = MMX_PXORrr
- { 1249, 1, 1, 0, "MMX_V_SET0", 0|(1<<TID::Rematerializable), 0|32|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo144 }, // Inst #1249 = MMX_V_SET0
- { 1250, 1, 1, 0, "MMX_V_SETALLONES", 0|(1<<TID::Rematerializable), 0|32|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo144 }, // Inst #1250 = MMX_V_SETALLONES
- { 1251, 0, 0, 0, "MONITOR", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|17|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #1251 = MONITOR
- { 1252, 1, 1, 0, "MOV16ao16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(2<<13)|(163<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1252 = MOV16ao16
- { 1253, 6, 0, 0, "MOV16mi", 0|(1<<TID::MayStore), 0|24|(1<<6)|(2<<13)|(199<<24), NULL, NULL, NULL, OperandInfo6 }, // Inst #1253 = MOV16mi
- { 1254, 6, 0, 0, "MOV16mr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(137<<24), NULL, NULL, NULL, OperandInfo7 }, // Inst #1254 = MOV16mr
- { 1255, 6, 1, 0, "MOV16ms", 0|(1<<TID::UnmodeledSideEffects), 0|4|(140<<24), NULL, NULL, NULL, OperandInfo145 }, // Inst #1255 = MOV16ms
- { 1256, 1, 0, 0, "MOV16o16a", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(2<<13)|(161<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1256 = MOV16o16a
- { 1257, 1, 1, 0, "MOV16r0", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(1<<6)|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo93 }, // Inst #1257 = MOV16r0
- { 1258, 2, 1, 0, "MOV16ri", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|2|(1<<6)|(2<<13)|(184<<24), NULL, NULL, NULL, OperandInfo54 }, // Inst #1258 = MOV16ri
- { 1259, 6, 1, 0, "MOV16rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<6)|(139<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1259 = MOV16rm
- { 1260, 2, 1, 0, "MOV16rr", 0, 0|3|(1<<6)|(137<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #1260 = MOV16rr
- { 1261, 2, 1, 0, "MOV16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(139<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #1261 = MOV16rr_REV
- { 1262, 2, 1, 0, "MOV16rs", 0|(1<<TID::UnmodeledSideEffects), 0|3|(140<<24), NULL, NULL, NULL, OperandInfo146 }, // Inst #1262 = MOV16rs
- { 1263, 6, 1, 0, "MOV16sm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(142<<24), NULL, NULL, NULL, OperandInfo147 }, // Inst #1263 = MOV16sm
- { 1264, 2, 1, 0, "MOV16sr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(142<<24), NULL, NULL, NULL, OperandInfo148 }, // Inst #1264 = MOV16sr
- { 1265, 1, 1, 0, "MOV32ao32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(163<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1265 = MOV32ao32
- { 1266, 2, 1, 0, "MOV32cr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(34<<24), NULL, NULL, NULL, OperandInfo149 }, // Inst #1266 = MOV32cr
- { 1267, 2, 1, 0, "MOV32dr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(35<<24), NULL, NULL, NULL, OperandInfo150 }, // Inst #1267 = MOV32dr
- { 1268, 6, 0, 0, "MOV32mi", 0|(1<<TID::MayStore), 0|24|(3<<13)|(199<<24), NULL, NULL, NULL, OperandInfo6 }, // Inst #1268 = MOV32mi
- { 1269, 6, 0, 0, "MOV32mr", 0|(1<<TID::MayStore), 0|4|(137<<24), NULL, NULL, NULL, OperandInfo11 }, // Inst #1269 = MOV32mr
- { 1270, 1, 0, 0, "MOV32o32a", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(161<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1270 = MOV32o32a
- { 1271, 1, 1, 0, "MOV32r0", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo57 }, // Inst #1271 = MOV32r0
- { 1272, 2, 1, 0, "MOV32rc", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(32<<24), NULL, NULL, NULL, OperandInfo151 }, // Inst #1272 = MOV32rc
- { 1273, 2, 1, 0, "MOV32rd", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(33<<24), NULL, NULL, NULL, OperandInfo152 }, // Inst #1273 = MOV32rd
- { 1274, 2, 1, 0, "MOV32ri", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|2|(3<<13)|(184<<24), NULL, NULL, NULL, OperandInfo55 }, // Inst #1274 = MOV32ri
- { 1275, 6, 1, 0, "MOV32rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(139<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1275 = MOV32rm
- { 1276, 2, 1, 0, "MOV32rr", 0, 0|3|(137<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #1276 = MOV32rr
- { 1277, 2, 1, 0, "MOV32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(139<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #1277 = MOV32rr_REV
- { 1278, 6, 1, 0, "MOV64FSrm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(1<<20)|(139<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1278 = MOV64FSrm
- { 1279, 6, 1, 0, "MOV64GSrm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(2<<20)|(139<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1279 = MOV64GSrm
- { 1280, 1, 1, 0, "MOV64ao64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(3<<13)|(163<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1280 = MOV64ao64
- { 1281, 1, 1, 0, "MOV64ao8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(1<<13)|(162<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1281 = MOV64ao8
- { 1282, 2, 1, 0, "MOV64cr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(34<<24), NULL, NULL, NULL, OperandInfo153 }, // Inst #1282 = MOV64cr
- { 1283, 2, 1, 0, "MOV64dr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(35<<24), NULL, NULL, NULL, OperandInfo154 }, // Inst #1283 = MOV64dr
- { 1284, 6, 0, 0, "MOV64mi32", 0|(1<<TID::MayStore), 0|24|(1<<12)|(3<<13)|(199<<24), NULL, NULL, NULL, OperandInfo6 }, // Inst #1284 = MOV64mi32
- { 1285, 6, 0, 0, "MOV64mr", 0|(1<<TID::MayStore), 0|4|(1<<12)|(137<<24), NULL, NULL, NULL, OperandInfo15 }, // Inst #1285 = MOV64mr
- { 1286, 6, 1, 0, "MOV64ms", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<12)|(140<<24), NULL, NULL, NULL, OperandInfo145 }, // Inst #1286 = MOV64ms
- { 1287, 1, 0, 0, "MOV64o64a", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(3<<13)|(161<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1287 = MOV64o64a
- { 1288, 1, 0, 0, "MOV64o8a", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(1<<13)|(160<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1288 = MOV64o8a
- { 1289, 1, 1, 0, "MOV64r0", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo58 }, // Inst #1289 = MOV64r0
- { 1290, 2, 1, 0, "MOV64rc", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(32<<24), NULL, NULL, NULL, OperandInfo155 }, // Inst #1290 = MOV64rc
- { 1291, 2, 1, 0, "MOV64rd", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(33<<24), NULL, NULL, NULL, OperandInfo156 }, // Inst #1291 = MOV64rd
- { 1292, 2, 1, 0, "MOV64ri", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|2|(1<<12)|(4<<13)|(184<<24), NULL, NULL, NULL, OperandInfo56 }, // Inst #1292 = MOV64ri
- { 1293, 2, 1, 0, "MOV64ri32", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|16|(1<<12)|(3<<13)|(199<<24), NULL, NULL, NULL, OperandInfo56 }, // Inst #1293 = MOV64ri32
- { 1294, 2, 1, 0, "MOV64ri64i32", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|2|(3<<13)|(184<<24), NULL, NULL, NULL, OperandInfo56 }, // Inst #1294 = MOV64ri64i32
- { 1295, 6, 1, 0, "MOV64rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<12)|(139<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1295 = MOV64rm
- { 1296, 2, 1, 0, "MOV64rr", 0, 0|3|(1<<12)|(137<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #1296 = MOV64rr
- { 1297, 2, 1, 0, "MOV64rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(139<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #1297 = MOV64rr_REV
- { 1298, 2, 1, 0, "MOV64rs", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<12)|(140<<24), NULL, NULL, NULL, OperandInfo157 }, // Inst #1298 = MOV64rs
- { 1299, 6, 1, 0, "MOV64sm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<12)|(142<<24), NULL, NULL, NULL, OperandInfo147 }, // Inst #1299 = MOV64sm
- { 1300, 2, 1, 0, "MOV64sr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(142<<24), NULL, NULL, NULL, OperandInfo158 }, // Inst #1300 = MOV64sr
- { 1301, 2, 1, 0, "MOV64toPQIrr", 0, 0|5|(1<<6)|(1<<8)|(1<<12)|(110<<24), NULL, NULL, NULL, OperandInfo159 }, // Inst #1301 = MOV64toPQIrr
- { 1302, 6, 1, 0, "MOV64toSDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(1<<12)|(110<<24), NULL, NULL, NULL, OperandInfo82 }, // Inst #1302 = MOV64toSDrm
- { 1303, 2, 1, 0, "MOV64toSDrr", 0, 0|5|(1<<6)|(1<<8)|(1<<12)|(110<<24), NULL, NULL, NULL, OperandInfo83 }, // Inst #1303 = MOV64toSDrr
- { 1304, 1, 1, 0, "MOV8ao8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(162<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1304 = MOV8ao8
- { 1305, 6, 0, 0, "MOV8mi", 0|(1<<TID::MayStore), 0|24|(1<<13)|(198<<24), NULL, NULL, NULL, OperandInfo6 }, // Inst #1305 = MOV8mi
- { 1306, 6, 0, 0, "MOV8mr", 0|(1<<TID::MayStore), 0|4|(136<<24), NULL, NULL, NULL, OperandInfo20 }, // Inst #1306 = MOV8mr
- { 1307, 6, 0, 0, "MOV8mr_NOREX", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(136<<24), NULL, NULL, NULL, OperandInfo160 }, // Inst #1307 = MOV8mr_NOREX
- { 1308, 1, 0, 0, "MOV8o8a", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(160<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1308 = MOV8o8a
- { 1309, 1, 1, 0, "MOV8r0", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(48<<24), NULL, ImplicitList1, Barriers1, OperandInfo94 }, // Inst #1309 = MOV8r0
- { 1310, 2, 1, 0, "MOV8ri", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|2|(1<<13)|(176<<24), NULL, NULL, NULL, OperandInfo68 }, // Inst #1310 = MOV8ri
- { 1311, 6, 1, 0, "MOV8rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(138<<24), NULL, NULL, NULL, OperandInfo69 }, // Inst #1311 = MOV8rm
- { 1312, 6, 1, 0, "MOV8rm_NOREX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable)|(1<<TID::UnmodeledSideEffects), 0|6|(138<<24), NULL, NULL, NULL, OperandInfo161 }, // Inst #1312 = MOV8rm_NOREX
- { 1313, 2, 1, 0, "MOV8rr", 0, 0|3|(136<<24), NULL, NULL, NULL, OperandInfo67 }, // Inst #1313 = MOV8rr
- { 1314, 2, 1, 0, "MOV8rr_NOREX", 0, 0|3|(136<<24), NULL, NULL, NULL, OperandInfo162 }, // Inst #1314 = MOV8rr_NOREX
- { 1315, 2, 1, 0, "MOV8rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(138<<24), NULL, NULL, NULL, OperandInfo67 }, // Inst #1315 = MOV8rr_REV
- { 1316, 6, 0, 0, "MOVAPDmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(41<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1316 = MOVAPDmr
- { 1317, 6, 1, 0, "MOVAPDrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<6)|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1317 = MOVAPDrm
- { 1318, 2, 1, 0, "MOVAPDrr", 0, 0|5|(1<<6)|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1318 = MOVAPDrr
- { 1319, 6, 0, 0, "MOVAPSmr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(41<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1319 = MOVAPSmr
- { 1320, 6, 1, 0, "MOVAPSrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1320 = MOVAPSrm
- { 1321, 2, 1, 0, "MOVAPSrr", 0, 0|5|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1321 = MOVAPSrr
- { 1322, 6, 1, 0, "MOVDDUPrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(18<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1322 = MOVDDUPrm
- { 1323, 2, 1, 0, "MOVDDUPrr", 0, 0|5|(11<<8)|(18<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1323 = MOVDDUPrr
- { 1324, 6, 1, 0, "MOVDI2PDIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1324 = MOVDI2PDIrm
- { 1325, 2, 1, 0, "MOVDI2PDIrr", 0, 0|5|(1<<6)|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo164 }, // Inst #1325 = MOVDI2PDIrr
- { 1326, 6, 1, 0, "MOVDI2SSrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #1326 = MOVDI2SSrm
- { 1327, 2, 1, 0, "MOVDI2SSrr", 0, 0|5|(1<<6)|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo86 }, // Inst #1327 = MOVDI2SSrr
- { 1328, 6, 0, 0, "MOVDQAmr", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(127<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1328 = MOVDQAmr
- { 1329, 6, 1, 0, "MOVDQArm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(111<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1329 = MOVDQArm
- { 1330, 2, 1, 0, "MOVDQArr", 0, 0|5|(1<<6)|(1<<8)|(111<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1330 = MOVDQArr
- { 1331, 6, 0, 0, "MOVDQUmr", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(12<<8)|(127<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1331 = MOVDQUmr
- { 1332, 6, 0, 0, "MOVDQUmr_Int", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(12<<8)|(127<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1332 = MOVDQUmr_Int
- { 1333, 6, 1, 0, "MOVDQUrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|6|(12<<8)|(111<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1333 = MOVDQUrm
- { 1334, 6, 1, 0, "MOVDQUrm_Int", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|6|(12<<8)|(111<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1334 = MOVDQUrm_Int
- { 1335, 3, 1, 0, "MOVHLPSrr", 0, 0|5|(1<<8)|(18<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1335 = MOVHLPSrr
- { 1336, 6, 0, 0, "MOVHPDmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(23<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1336 = MOVHPDmr
- { 1337, 7, 1, 0, "MOVHPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(22<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1337 = MOVHPDrm
- { 1338, 6, 0, 0, "MOVHPSmr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(23<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1338 = MOVHPSmr
- { 1339, 7, 1, 0, "MOVHPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(22<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1339 = MOVHPSrm
- { 1340, 3, 1, 0, "MOVLHPSrr", 0, 0|5|(1<<8)|(22<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1340 = MOVLHPSrr
- { 1341, 6, 0, 0, "MOVLPDmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(19<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1341 = MOVLPDmr
- { 1342, 7, 1, 0, "MOVLPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(18<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1342 = MOVLPDrm
- { 1343, 3, 1, 0, "MOVLPDrr", 0, 0|5|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1343 = MOVLPDrr
- { 1344, 6, 0, 0, "MOVLPSmr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(19<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1344 = MOVLPSmr
- { 1345, 7, 1, 0, "MOVLPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(18<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1345 = MOVLPSrm
- { 1346, 3, 1, 0, "MOVLPSrr", 0, 0|5|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1346 = MOVLPSrr
- { 1347, 6, 0, 0, "MOVLQ128mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(214<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1347 = MOVLQ128mr
- { 1348, 3, 1, 0, "MOVLSD2PDrr", 0, 0|5|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo165 }, // Inst #1348 = MOVLSD2PDrr
- { 1349, 3, 1, 0, "MOVLSS2PSrr", 0, 0|5|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo166 }, // Inst #1349 = MOVLSS2PSrr
- { 1350, 2, 1, 0, "MOVMSKPDrr", 0, 0|5|(1<<6)|(1<<8)|(80<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #1350 = MOVMSKPDrr
- { 1351, 2, 1, 0, "MOVMSKPSrr", 0, 0|5|(1<<8)|(80<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #1351 = MOVMSKPSrr
- { 1352, 6, 1, 0, "MOVNTDQArm", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(42<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1352 = MOVNTDQArm
- { 1353, 6, 0, 0, "MOVNTDQmr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(231<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1353 = MOVNTDQmr
- { 1354, 6, 0, 0, "MOVNTImr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(195<<24), NULL, NULL, NULL, OperandInfo11 }, // Inst #1354 = MOVNTImr
- { 1355, 6, 0, 0, "MOVNTPDmr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(43<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1355 = MOVNTPDmr
- { 1356, 6, 0, 0, "MOVNTPSmr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(43<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1356 = MOVNTPSmr
- { 1357, 2, 1, 0, "MOVPC32r", 0|(1<<TID::NotDuplicable), 0|(3<<13)|(232<<24), ImplicitList2, NULL, NULL, OperandInfo55 }, // Inst #1357 = MOVPC32r
- { 1358, 6, 0, 0, "MOVPD2SDmr", 0|(1<<TID::MayStore), 0|4|(11<<8)|(17<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1358 = MOVPD2SDmr
- { 1359, 2, 1, 0, "MOVPD2SDrr", 0|(1<<TID::CheapAsAMove), 0|5|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo167 }, // Inst #1359 = MOVPD2SDrr
- { 1360, 6, 0, 0, "MOVPDI2DImr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(126<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1360 = MOVPDI2DImr
- { 1361, 2, 1, 0, "MOVPDI2DIrr", 0, 0|3|(1<<6)|(1<<8)|(126<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #1361 = MOVPDI2DIrr
- { 1362, 6, 0, 0, "MOVPQI2QImr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(214<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1362 = MOVPQI2QImr
- { 1363, 2, 1, 0, "MOVPQIto64rr", 0, 0|3|(1<<6)|(1<<8)|(1<<12)|(126<<24), NULL, NULL, NULL, OperandInfo121 }, // Inst #1363 = MOVPQIto64rr
- { 1364, 6, 0, 0, "MOVPS2SSmr", 0|(1<<TID::MayStore), 0|4|(12<<8)|(17<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1364 = MOVPS2SSmr
- { 1365, 2, 1, 0, "MOVPS2SSrr", 0|(1<<TID::CheapAsAMove), 0|5|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo168 }, // Inst #1365 = MOVPS2SSrr
- { 1366, 6, 1, 0, "MOVQI2PQIrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(126<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1366 = MOVQI2PQIrm
- { 1367, 2, 1, 0, "MOVQxrxr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(12<<8)|(126<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1367 = MOVQxrxr
- { 1368, 6, 1, 0, "MOVSD2PDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1368 = MOVSD2PDrm
- { 1369, 2, 1, 0, "MOVSD2PDrr", 0|(1<<TID::CheapAsAMove), 0|5|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo169 }, // Inst #1369 = MOVSD2PDrr
- { 1370, 6, 0, 0, "MOVSDmr", 0|(1<<TID::MayStore), 0|4|(11<<8)|(17<<24), NULL, NULL, NULL, OperandInfo170 }, // Inst #1370 = MOVSDmr
- { 1371, 6, 1, 0, "MOVSDrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo82 }, // Inst #1371 = MOVSDrm
- { 1372, 2, 1, 0, "MOVSDrr", 0, 0|5|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo105 }, // Inst #1372 = MOVSDrr
- { 1373, 6, 0, 0, "MOVSDto64mr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(1<<12)|(126<<24), NULL, NULL, NULL, OperandInfo170 }, // Inst #1373 = MOVSDto64mr
- { 1374, 2, 1, 0, "MOVSDto64rr", 0, 0|3|(1<<6)|(1<<8)|(1<<12)|(126<<24), NULL, NULL, NULL, OperandInfo79 }, // Inst #1374 = MOVSDto64rr
- { 1375, 6, 1, 0, "MOVSHDUPrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(22<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1375 = MOVSHDUPrm
- { 1376, 2, 1, 0, "MOVSHDUPrr", 0, 0|5|(12<<8)|(22<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1376 = MOVSHDUPrr
- { 1377, 6, 1, 0, "MOVSLDUPrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(18<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1377 = MOVSLDUPrm
- { 1378, 2, 1, 0, "MOVSLDUPrr", 0, 0|5|(12<<8)|(18<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1378 = MOVSLDUPrr
- { 1379, 6, 0, 0, "MOVSS2DImr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(126<<24), NULL, NULL, NULL, OperandInfo171 }, // Inst #1379 = MOVSS2DImr
- { 1380, 2, 1, 0, "MOVSS2DIrr", 0, 0|3|(1<<6)|(1<<8)|(126<<24), NULL, NULL, NULL, OperandInfo89 }, // Inst #1380 = MOVSS2DIrr
- { 1381, 6, 1, 0, "MOVSS2PSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1381 = MOVSS2PSrm
- { 1382, 2, 1, 0, "MOVSS2PSrr", 0|(1<<TID::CheapAsAMove), 0|5|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo172 }, // Inst #1382 = MOVSS2PSrr
- { 1383, 6, 0, 0, "MOVSSmr", 0|(1<<TID::MayStore), 0|4|(12<<8)|(17<<24), NULL, NULL, NULL, OperandInfo171 }, // Inst #1383 = MOVSSmr
- { 1384, 6, 1, 0, "MOVSSrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #1384 = MOVSSrm
- { 1385, 2, 1, 0, "MOVSSrr", 0, 0|5|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo106 }, // Inst #1385 = MOVSSrr
- { 1386, 6, 1, 0, "MOVSX16rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1386 = MOVSX16rm8
- { 1387, 6, 1, 0, "MOVSX16rm8W", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1387 = MOVSX16rm8W
- { 1388, 2, 1, 0, "MOVSX16rr8", 0, 0|5|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo173 }, // Inst #1388 = MOVSX16rr8
- { 1389, 2, 1, 0, "MOVSX16rr8W", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo173 }, // Inst #1389 = MOVSX16rr8W
- { 1390, 6, 1, 0, "MOVSX32rm16", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(191<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1390 = MOVSX32rm16
- { 1391, 6, 1, 0, "MOVSX32rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1391 = MOVSX32rm8
- { 1392, 2, 1, 0, "MOVSX32rr16", 0, 0|5|(1<<8)|(191<<24), NULL, NULL, NULL, OperandInfo174 }, // Inst #1392 = MOVSX32rr16
- { 1393, 2, 1, 0, "MOVSX32rr8", 0, 0|5|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo175 }, // Inst #1393 = MOVSX32rr8
- { 1394, 6, 1, 0, "MOVSX64rm16", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(191<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1394 = MOVSX64rm16
- { 1395, 6, 1, 0, "MOVSX64rm32", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(99<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1395 = MOVSX64rm32
- { 1396, 6, 1, 0, "MOVSX64rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(190<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1396 = MOVSX64rm8
- { 1397, 2, 1, 0, "MOVSX64rr16", 0, 0|5|(1<<8)|(1<<12)|(191<<24), NULL, NULL, NULL, OperandInfo176 }, // Inst #1397 = MOVSX64rr16
- { 1398, 2, 1, 0, "MOVSX64rr32", 0, 0|5|(1<<12)|(99<<24), NULL, NULL, NULL, OperandInfo125 }, // Inst #1398 = MOVSX64rr32
- { 1399, 2, 1, 0, "MOVSX64rr8", 0, 0|5|(1<<8)|(1<<12)|(190<<24), NULL, NULL, NULL, OperandInfo177 }, // Inst #1399 = MOVSX64rr8
- { 1400, 6, 0, 0, "MOVUPDmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(17<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1400 = MOVUPDmr
- { 1401, 6, 0, 0, "MOVUPDmr_Int", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(17<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1401 = MOVUPDmr_Int
- { 1402, 6, 1, 0, "MOVUPDrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1402 = MOVUPDrm
- { 1403, 6, 1, 0, "MOVUPDrm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1403 = MOVUPDrm_Int
- { 1404, 2, 1, 0, "MOVUPDrr", 0, 0|5|(1<<6)|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1404 = MOVUPDrr
- { 1405, 6, 0, 0, "MOVUPSmr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(17<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1405 = MOVUPSmr
- { 1406, 6, 0, 0, "MOVUPSmr_Int", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(17<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1406 = MOVUPSmr_Int
- { 1407, 6, 1, 0, "MOVUPSrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1407 = MOVUPSrm
- { 1408, 6, 1, 0, "MOVUPSrm_Int", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1408 = MOVUPSrm_Int
- { 1409, 2, 1, 0, "MOVUPSrr", 0, 0|5|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1409 = MOVUPSrr
- { 1410, 6, 1, 0, "MOVZDI2PDIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1410 = MOVZDI2PDIrm
- { 1411, 2, 1, 0, "MOVZDI2PDIrr", 0, 0|5|(1<<6)|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo164 }, // Inst #1411 = MOVZDI2PDIrr
- { 1412, 6, 1, 0, "MOVZPQILo2PQIrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(126<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1412 = MOVZPQILo2PQIrm
- { 1413, 2, 1, 0, "MOVZPQILo2PQIrr", 0, 0|5|(12<<8)|(126<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1413 = MOVZPQILo2PQIrr
- { 1414, 6, 1, 0, "MOVZQI2PQIrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(126<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1414 = MOVZQI2PQIrm
- { 1415, 2, 1, 0, "MOVZQI2PQIrr", 0, 0|5|(1<<6)|(1<<8)|(1<<12)|(110<<24), NULL, NULL, NULL, OperandInfo159 }, // Inst #1415 = MOVZQI2PQIrr
- { 1416, 6, 1, 0, "MOVZSD2PDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1416 = MOVZSD2PDrm
- { 1417, 6, 1, 0, "MOVZSS2PSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1417 = MOVZSS2PSrm
- { 1418, 6, 1, 0, "MOVZX16rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1418 = MOVZX16rm8
- { 1419, 6, 1, 0, "MOVZX16rm8W", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1419 = MOVZX16rm8W
- { 1420, 2, 1, 0, "MOVZX16rr8", 0, 0|5|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo173 }, // Inst #1420 = MOVZX16rr8
- { 1421, 2, 1, 0, "MOVZX16rr8W", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo173 }, // Inst #1421 = MOVZX16rr8W
- { 1422, 6, 1, 0, "MOVZX32_NOREXrm8", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo178 }, // Inst #1422 = MOVZX32_NOREXrm8
- { 1423, 2, 1, 0, "MOVZX32_NOREXrr8", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo179 }, // Inst #1423 = MOVZX32_NOREXrr8
- { 1424, 6, 1, 0, "MOVZX32rm16", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(183<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1424 = MOVZX32rm16
- { 1425, 6, 1, 0, "MOVZX32rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1425 = MOVZX32rm8
- { 1426, 2, 1, 0, "MOVZX32rr16", 0, 0|5|(1<<8)|(183<<24), NULL, NULL, NULL, OperandInfo174 }, // Inst #1426 = MOVZX32rr16
- { 1427, 2, 1, 0, "MOVZX32rr8", 0, 0|5|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo175 }, // Inst #1427 = MOVZX32rr8
- { 1428, 6, 1, 0, "MOVZX64rm16", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(183<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1428 = MOVZX64rm16
- { 1429, 6, 1, 0, "MOVZX64rm16_Q", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(1<<12)|(183<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1429 = MOVZX64rm16_Q
- { 1430, 6, 1, 0, "MOVZX64rm32", 0|(1<<TID::MayLoad), 0|6|(139<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1430 = MOVZX64rm32
- { 1431, 6, 1, 0, "MOVZX64rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1431 = MOVZX64rm8
- { 1432, 6, 1, 0, "MOVZX64rm8_Q", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(1<<12)|(182<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1432 = MOVZX64rm8_Q
- { 1433, 2, 1, 0, "MOVZX64rr16", 0, 0|5|(1<<8)|(183<<24), NULL, NULL, NULL, OperandInfo176 }, // Inst #1433 = MOVZX64rr16
- { 1434, 2, 1, 0, "MOVZX64rr16_Q", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(1<<12)|(183<<24), NULL, NULL, NULL, OperandInfo176 }, // Inst #1434 = MOVZX64rr16_Q
- { 1435, 2, 1, 0, "MOVZX64rr32", 0, 0|3|(137<<24), NULL, NULL, NULL, OperandInfo125 }, // Inst #1435 = MOVZX64rr32
- { 1436, 2, 1, 0, "MOVZX64rr8", 0, 0|5|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo177 }, // Inst #1436 = MOVZX64rr8
- { 1437, 2, 1, 0, "MOVZX64rr8_Q", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(1<<12)|(182<<24), NULL, NULL, NULL, OperandInfo177 }, // Inst #1437 = MOVZX64rr8_Q
- { 1438, 2, 1, 0, "MOV_Fp3232", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo2 }, // Inst #1438 = MOV_Fp3232
- { 1439, 2, 1, 0, "MOV_Fp3264", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo180 }, // Inst #1439 = MOV_Fp3264
- { 1440, 2, 1, 0, "MOV_Fp3280", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo181 }, // Inst #1440 = MOV_Fp3280
- { 1441, 2, 1, 0, "MOV_Fp6432", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo182 }, // Inst #1441 = MOV_Fp6432
- { 1442, 2, 1, 0, "MOV_Fp6464", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo3 }, // Inst #1442 = MOV_Fp6464
- { 1443, 2, 1, 0, "MOV_Fp6480", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo183 }, // Inst #1443 = MOV_Fp6480
- { 1444, 2, 1, 0, "MOV_Fp8032", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo184 }, // Inst #1444 = MOV_Fp8032
- { 1445, 2, 1, 0, "MOV_Fp8064", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo185 }, // Inst #1445 = MOV_Fp8064
- { 1446, 2, 1, 0, "MOV_Fp8080", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo4 }, // Inst #1446 = MOV_Fp8080
- { 1447, 8, 1, 0, "MPSADBWrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(66<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1447 = MPSADBWrmi
- { 1448, 4, 1, 0, "MPSADBWrri", 0|(1<<TID::Commutable), 0|5|(1<<6)|(14<<8)|(1<<13)|(66<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #1448 = MPSADBWrri
- { 1449, 5, 0, 0, "MUL16m", 0|(1<<TID::MayLoad), 0|28|(1<<6)|(247<<24), ImplicitList12, ImplicitList21, Barriers1, OperandInfo30 }, // Inst #1449 = MUL16m
- { 1450, 1, 0, 0, "MUL16r", 0, 0|20|(1<<6)|(247<<24), ImplicitList12, ImplicitList21, Barriers1, OperandInfo93 }, // Inst #1450 = MUL16r
- { 1451, 5, 0, 0, "MUL32m", 0|(1<<TID::MayLoad), 0|28|(247<<24), ImplicitList13, ImplicitList18, Barriers6, OperandInfo30 }, // Inst #1451 = MUL32m
- { 1452, 1, 0, 0, "MUL32r", 0, 0|20|(247<<24), ImplicitList13, ImplicitList18, Barriers6, OperandInfo57 }, // Inst #1452 = MUL32r
- { 1453, 5, 0, 0, "MUL64m", 0|(1<<TID::MayLoad), 0|28|(1<<12)|(247<<24), ImplicitList15, ImplicitList17, Barriers1, OperandInfo30 }, // Inst #1453 = MUL64m
- { 1454, 1, 0, 0, "MUL64r", 0, 0|20|(1<<12)|(247<<24), ImplicitList15, ImplicitList17, Barriers1, OperandInfo58 }, // Inst #1454 = MUL64r
- { 1455, 5, 0, 0, "MUL8m", 0|(1<<TID::MayLoad), 0|28|(246<<24), ImplicitList11, ImplicitList22, Barriers1, OperandInfo30 }, // Inst #1455 = MUL8m
- { 1456, 1, 0, 0, "MUL8r", 0, 0|20|(246<<24), ImplicitList11, ImplicitList22, Barriers1, OperandInfo94 }, // Inst #1456 = MUL8r
- { 1457, 7, 1, 0, "MULPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(89<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1457 = MULPDrm
- { 1458, 3, 1, 0, "MULPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(89<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1458 = MULPDrr
- { 1459, 7, 1, 0, "MULPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(89<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1459 = MULPSrm
- { 1460, 3, 1, 0, "MULPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(89<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1460 = MULPSrr
- { 1461, 7, 1, 0, "MULSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(89<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #1461 = MULSDrm
- { 1462, 7, 1, 0, "MULSDrm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(89<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1462 = MULSDrm_Int
- { 1463, 3, 1, 0, "MULSDrr", 0|(1<<TID::Commutable), 0|5|(11<<8)|(89<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #1463 = MULSDrr
- { 1464, 3, 1, 0, "MULSDrr_Int", 0, 0|5|(11<<8)|(89<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1464 = MULSDrr_Int
- { 1465, 7, 1, 0, "MULSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(89<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #1465 = MULSSrm
- { 1466, 7, 1, 0, "MULSSrm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(89<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1466 = MULSSrm_Int
- { 1467, 3, 1, 0, "MULSSrr", 0|(1<<TID::Commutable), 0|5|(12<<8)|(89<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #1467 = MULSSrr
- { 1468, 3, 1, 0, "MULSSrr_Int", 0, 0|5|(12<<8)|(89<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1468 = MULSSrr_Int
- { 1469, 5, 0, 0, "MUL_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|25|(216<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1469 = MUL_F32m
- { 1470, 5, 0, 0, "MUL_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|25|(220<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1470 = MUL_F64m
- { 1471, 5, 0, 0, "MUL_FI16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|25|(222<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1471 = MUL_FI16m
- { 1472, 5, 0, 0, "MUL_FI32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|25|(218<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1472 = MUL_FI32m
- { 1473, 1, 0, 0, "MUL_FPrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(9<<8)|(200<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #1473 = MUL_FPrST0
- { 1474, 1, 0, 0, "MUL_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(200<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #1474 = MUL_FST0r
- { 1475, 3, 1, 0, "MUL_Fp32", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #1475 = MUL_Fp32
- { 1476, 7, 1, 0, "MUL_Fp32m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #1476 = MUL_Fp32m
- { 1477, 3, 1, 0, "MUL_Fp64", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #1477 = MUL_Fp64
- { 1478, 7, 1, 0, "MUL_Fp64m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #1478 = MUL_Fp64m
- { 1479, 7, 1, 0, "MUL_Fp64m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #1479 = MUL_Fp64m32
- { 1480, 3, 1, 0, "MUL_Fp80", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #1480 = MUL_Fp80
- { 1481, 7, 1, 0, "MUL_Fp80m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #1481 = MUL_Fp80m32
- { 1482, 7, 1, 0, "MUL_Fp80m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #1482 = MUL_Fp80m64
- { 1483, 7, 1, 0, "MUL_FpI16m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #1483 = MUL_FpI16m32
- { 1484, 7, 1, 0, "MUL_FpI16m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #1484 = MUL_FpI16m64
- { 1485, 7, 1, 0, "MUL_FpI16m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #1485 = MUL_FpI16m80
- { 1486, 7, 1, 0, "MUL_FpI32m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #1486 = MUL_FpI32m32
- { 1487, 7, 1, 0, "MUL_FpI32m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #1487 = MUL_FpI32m64
- { 1488, 7, 1, 0, "MUL_FpI32m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #1488 = MUL_FpI32m80
- { 1489, 1, 0, 0, "MUL_FrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(7<<8)|(200<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #1489 = MUL_FrST0
- { 1490, 0, 0, 0, "MWAIT", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|17|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #1490 = MWAIT
- { 1491, 5, 0, 0, "NEG16m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<6)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1491 = NEG16m
- { 1492, 2, 1, 0, "NEG16r", 0, 0|19|(1<<6)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1492 = NEG16r
- { 1493, 5, 0, 0, "NEG32m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1493 = NEG32m
- { 1494, 2, 1, 0, "NEG32r", 0, 0|19|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1494 = NEG32r
- { 1495, 5, 0, 0, "NEG64m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<12)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1495 = NEG64m
- { 1496, 2, 1, 0, "NEG64r", 0, 0|19|(1<<12)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #1496 = NEG64r
- { 1497, 5, 0, 0, "NEG8m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(246<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1497 = NEG8m
- { 1498, 2, 1, 0, "NEG8r", 0, 0|19|(246<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #1498 = NEG8r
- { 1499, 0, 0, 0, "NOOP", 0, 0|1|(144<<24), NULL, NULL, NULL, 0 }, // Inst #1499 = NOOP
- { 1500, 5, 0, 0, "NOOPL", 0, 0|24|(1<<8)|(31<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1500 = NOOPL
- { 1501, 5, 0, 0, "NOOPW", 0, 0|24|(1<<6)|(1<<8)|(31<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1501 = NOOPW
- { 1502, 5, 0, 0, "NOT16m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<6)|(247<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1502 = NOT16m
- { 1503, 2, 1, 0, "NOT16r", 0, 0|18|(1<<6)|(247<<24), NULL, NULL, NULL, OperandInfo91 }, // Inst #1503 = NOT16r
- { 1504, 5, 0, 0, "NOT32m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(247<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1504 = NOT32m
- { 1505, 2, 1, 0, "NOT32r", 0, 0|18|(247<<24), NULL, NULL, NULL, OperandInfo52 }, // Inst #1505 = NOT32r
- { 1506, 5, 0, 0, "NOT64m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<12)|(247<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1506 = NOT64m
- { 1507, 2, 1, 0, "NOT64r", 0, 0|18|(1<<12)|(247<<24), NULL, NULL, NULL, OperandInfo53 }, // Inst #1507 = NOT64r
- { 1508, 5, 0, 0, "NOT8m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(246<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1508 = NOT8m
- { 1509, 2, 1, 0, "NOT8r", 0, 0|18|(246<<24), NULL, NULL, NULL, OperandInfo92 }, // Inst #1509 = NOT8r
- { 1510, 1, 0, 0, "OR16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(2<<13)|(13<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #1510 = OR16i16
- { 1511, 6, 0, 0, "OR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1511 = OR16mi
- { 1512, 6, 0, 0, "OR16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1512 = OR16mi8
- { 1513, 6, 0, 0, "OR16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #1513 = OR16mr
- { 1514, 3, 1, 0, "OR16ri", 0, 0|17|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1514 = OR16ri
- { 1515, 3, 1, 0, "OR16ri8", 0, 0|17|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1515 = OR16ri8
- { 1516, 7, 1, 0, "OR16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #1516 = OR16rm
- { 1517, 3, 1, 0, "OR16rr", 0|(1<<TID::Commutable), 0|3|(1<<6)|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #1517 = OR16rr
- { 1518, 3, 1, 0, "OR16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #1518 = OR16rr_REV
- { 1519, 1, 0, 0, "OR32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(13<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #1519 = OR32i32
- { 1520, 6, 0, 0, "OR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1520 = OR32mi
- { 1521, 6, 0, 0, "OR32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1521 = OR32mi8
- { 1522, 6, 0, 0, "OR32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #1522 = OR32mr
- { 1523, 3, 1, 0, "OR32ri", 0, 0|17|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1523 = OR32ri
- { 1524, 3, 1, 0, "OR32ri8", 0, 0|17|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1524 = OR32ri8
- { 1525, 7, 1, 0, "OR32rm", 0|(1<<TID::MayLoad), 0|6|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #1525 = OR32rm
- { 1526, 3, 1, 0, "OR32rr", 0|(1<<TID::Commutable), 0|3|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #1526 = OR32rr
- { 1527, 3, 1, 0, "OR32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #1527 = OR32rr_REV
- { 1528, 1, 0, 0, "OR64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(3<<13)|(13<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #1528 = OR64i32
- { 1529, 6, 0, 0, "OR64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1529 = OR64mi32
- { 1530, 6, 0, 0, "OR64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1530 = OR64mi8
- { 1531, 6, 0, 0, "OR64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #1531 = OR64mr
- { 1532, 3, 1, 0, "OR64ri32", 0, 0|17|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1532 = OR64ri32
- { 1533, 3, 1, 0, "OR64ri8", 0, 0|17|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1533 = OR64ri8
- { 1534, 7, 1, 0, "OR64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #1534 = OR64rm
- { 1535, 3, 1, 0, "OR64rr", 0|(1<<TID::Commutable), 0|3|(1<<12)|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #1535 = OR64rr
- { 1536, 3, 1, 0, "OR64rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #1536 = OR64rr_REV
- { 1537, 1, 0, 0, "OR8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(12<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #1537 = OR8i8
- { 1538, 6, 0, 0, "OR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1538 = OR8mi
- { 1539, 6, 0, 0, "OR8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(8<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #1539 = OR8mr
- { 1540, 3, 1, 0, "OR8ri", 0, 0|17|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1540 = OR8ri
- { 1541, 7, 1, 0, "OR8rm", 0|(1<<TID::MayLoad), 0|6|(10<<24), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #1541 = OR8rm
- { 1542, 3, 1, 0, "OR8rr", 0|(1<<TID::Commutable), 0|3|(8<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #1542 = OR8rr
- { 1543, 3, 1, 0, "OR8rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(10<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #1543 = OR8rr_REV
- { 1544, 7, 1, 0, "ORPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1544 = ORPDrm
- { 1545, 3, 1, 0, "ORPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1545 = ORPDrr
- { 1546, 7, 1, 0, "ORPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1546 = ORPSrm
- { 1547, 3, 1, 0, "ORPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1547 = ORPSrr
- { 1548, 1, 0, 0, "OUT16ir", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<13)|(231<<24), ImplicitList12, NULL, NULL, OperandInfo5 }, // Inst #1548 = OUT16ir
- { 1549, 0, 0, 0, "OUT16rr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(239<<24), ImplicitList36, NULL, NULL, 0 }, // Inst #1549 = OUT16rr
- { 1550, 1, 0, 0, "OUT32ir", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(231<<24), ImplicitList13, NULL, NULL, OperandInfo5 }, // Inst #1550 = OUT32ir
- { 1551, 0, 0, 0, "OUT32rr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(239<<24), ImplicitList37, NULL, NULL, 0 }, // Inst #1551 = OUT32rr
- { 1552, 1, 0, 0, "OUT8ir", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(230<<24), ImplicitList11, NULL, NULL, OperandInfo5 }, // Inst #1552 = OUT8ir
- { 1553, 0, 0, 0, "OUT8rr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(238<<24), ImplicitList38, NULL, NULL, 0 }, // Inst #1553 = OUT8rr
- { 1554, 0, 0, 0, "OUTSB", 0|(1<<TID::UnmodeledSideEffects), 0|1|(110<<24), NULL, NULL, NULL, 0 }, // Inst #1554 = OUTSB
- { 1555, 0, 0, 0, "OUTSD", 0|(1<<TID::UnmodeledSideEffects), 0|1|(111<<24), NULL, NULL, NULL, 0 }, // Inst #1555 = OUTSD
- { 1556, 0, 0, 0, "OUTSW", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(111<<24), NULL, NULL, NULL, 0 }, // Inst #1556 = OUTSW
- { 1557, 6, 1, 0, "PABSBrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(28<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1557 = PABSBrm128
- { 1558, 6, 1, 0, "PABSBrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(28<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1558 = PABSBrm64
- { 1559, 2, 1, 0, "PABSBrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(28<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1559 = PABSBrr128
- { 1560, 2, 1, 0, "PABSBrr64", 0, 0|5|(13<<8)|(1<<13)|(28<<24), NULL, NULL, NULL, OperandInfo129 }, // Inst #1560 = PABSBrr64
- { 1561, 6, 1, 0, "PABSDrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(30<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1561 = PABSDrm128
- { 1562, 6, 1, 0, "PABSDrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(30<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1562 = PABSDrm64
- { 1563, 2, 1, 0, "PABSDrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(30<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1563 = PABSDrr128
- { 1564, 2, 1, 0, "PABSDrr64", 0, 0|5|(13<<8)|(1<<13)|(30<<24), NULL, NULL, NULL, OperandInfo129 }, // Inst #1564 = PABSDrr64
- { 1565, 6, 1, 0, "PABSWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(29<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1565 = PABSWrm128
- { 1566, 6, 1, 0, "PABSWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(29<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1566 = PABSWrm64
- { 1567, 2, 1, 0, "PABSWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(29<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1567 = PABSWrr128
- { 1568, 2, 1, 0, "PABSWrr64", 0, 0|5|(13<<8)|(1<<13)|(29<<24), NULL, NULL, NULL, OperandInfo129 }, // Inst #1568 = PABSWrr64
- { 1569, 7, 1, 0, "PACKSSDWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(107<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1569 = PACKSSDWrm
- { 1570, 3, 1, 0, "PACKSSDWrr", 0, 0|5|(1<<6)|(1<<8)|(107<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1570 = PACKSSDWrr
- { 1571, 7, 1, 0, "PACKSSWBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(99<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1571 = PACKSSWBrm
- { 1572, 3, 1, 0, "PACKSSWBrr", 0, 0|5|(1<<6)|(1<<8)|(99<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1572 = PACKSSWBrr
- { 1573, 7, 1, 0, "PACKUSDWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(43<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1573 = PACKUSDWrm
- { 1574, 3, 1, 0, "PACKUSDWrr", 0, 0|5|(1<<6)|(13<<8)|(43<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1574 = PACKUSDWrr
- { 1575, 7, 1, 0, "PACKUSWBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(103<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1575 = PACKUSWBrm
- { 1576, 3, 1, 0, "PACKUSWBrr", 0, 0|5|(1<<6)|(1<<8)|(103<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1576 = PACKUSWBrr
- { 1577, 7, 1, 0, "PADDBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(252<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1577 = PADDBrm
- { 1578, 3, 1, 0, "PADDBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(252<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1578 = PADDBrr
- { 1579, 7, 1, 0, "PADDDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(254<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1579 = PADDDrm
- { 1580, 3, 1, 0, "PADDDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(254<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1580 = PADDDrr
- { 1581, 7, 1, 0, "PADDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(212<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1581 = PADDQrm
- { 1582, 3, 1, 0, "PADDQrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(212<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1582 = PADDQrr
- { 1583, 7, 1, 0, "PADDSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(236<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1583 = PADDSBrm
- { 1584, 3, 1, 0, "PADDSBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(236<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1584 = PADDSBrr
- { 1585, 7, 1, 0, "PADDSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(237<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1585 = PADDSWrm
- { 1586, 3, 1, 0, "PADDSWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(237<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1586 = PADDSWrr
- { 1587, 7, 1, 0, "PADDUSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(220<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1587 = PADDUSBrm
- { 1588, 3, 1, 0, "PADDUSBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(220<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1588 = PADDUSBrr
- { 1589, 7, 1, 0, "PADDUSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(221<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1589 = PADDUSWrm
- { 1590, 3, 1, 0, "PADDUSWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(221<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1590 = PADDUSWrr
- { 1591, 7, 1, 0, "PADDWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(253<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1591 = PADDWrm
- { 1592, 3, 1, 0, "PADDWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(253<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1592 = PADDWrr
- { 1593, 8, 1, 0, "PALIGNR128rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(14<<8)|(1<<13)|(15<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1593 = PALIGNR128rm
- { 1594, 4, 1, 0, "PALIGNR128rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(14<<8)|(1<<13)|(15<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #1594 = PALIGNR128rr
- { 1595, 8, 1, 0, "PALIGNR64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(14<<8)|(1<<13)|(15<<24), NULL, NULL, NULL, OperandInfo139 }, // Inst #1595 = PALIGNR64rm
- { 1596, 4, 1, 0, "PALIGNR64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(14<<8)|(1<<13)|(15<<24), NULL, NULL, NULL, OperandInfo186 }, // Inst #1596 = PALIGNR64rr
- { 1597, 7, 1, 0, "PANDNrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(223<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1597 = PANDNrm
- { 1598, 3, 1, 0, "PANDNrr", 0, 0|5|(1<<6)|(1<<8)|(223<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1598 = PANDNrr
- { 1599, 7, 1, 0, "PANDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(219<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1599 = PANDrm
- { 1600, 3, 1, 0, "PANDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(219<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1600 = PANDrr
- { 1601, 7, 1, 0, "PAVGBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(224<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1601 = PAVGBrm
- { 1602, 3, 1, 0, "PAVGBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(224<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1602 = PAVGBrr
- { 1603, 7, 1, 0, "PAVGWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(227<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1603 = PAVGWrm
- { 1604, 3, 1, 0, "PAVGWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(227<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1604 = PAVGWrr
- { 1605, 7, 1, 0, "PBLENDVBrm0", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(16<<24), ImplicitList8, NULL, NULL, OperandInfo24 }, // Inst #1605 = PBLENDVBrm0
- { 1606, 3, 1, 0, "PBLENDVBrr0", 0, 0|5|(1<<6)|(13<<8)|(16<<24), ImplicitList8, NULL, NULL, OperandInfo25 }, // Inst #1606 = PBLENDVBrr0
- { 1607, 8, 1, 0, "PBLENDWrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(14<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1607 = PBLENDWrmi
- { 1608, 4, 1, 0, "PBLENDWrri", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(14<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #1608 = PBLENDWrri
- { 1609, 7, 1, 0, "PCMPEQBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(116<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1609 = PCMPEQBrm
- { 1610, 3, 1, 0, "PCMPEQBrr", 0, 0|5|(1<<6)|(1<<8)|(116<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1610 = PCMPEQBrr
- { 1611, 7, 1, 0, "PCMPEQDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1611 = PCMPEQDrm
- { 1612, 3, 1, 0, "PCMPEQDrr", 0, 0|5|(1<<6)|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1612 = PCMPEQDrr
- { 1613, 7, 1, 0, "PCMPEQQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(41<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1613 = PCMPEQQrm
- { 1614, 3, 1, 0, "PCMPEQQrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(41<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1614 = PCMPEQQrr
- { 1615, 7, 1, 0, "PCMPEQWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(117<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1615 = PCMPEQWrm
- { 1616, 3, 1, 0, "PCMPEQWrr", 0, 0|5|(1<<6)|(1<<8)|(117<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1616 = PCMPEQWrr
- { 1617, 7, 0, 0, "PCMPESTRIArm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList39, Barriers1, OperandInfo187 }, // Inst #1617 = PCMPESTRIArm
- { 1618, 3, 0, 0, "PCMPESTRIArr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList39, Barriers1, OperandInfo188 }, // Inst #1618 = PCMPESTRIArr
- { 1619, 7, 0, 0, "PCMPESTRICrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList39, Barriers1, OperandInfo187 }, // Inst #1619 = PCMPESTRICrm
- { 1620, 3, 0, 0, "PCMPESTRICrr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList39, Barriers1, OperandInfo188 }, // Inst #1620 = PCMPESTRICrr
- { 1621, 7, 0, 0, "PCMPESTRIOrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList39, Barriers1, OperandInfo187 }, // Inst #1621 = PCMPESTRIOrm
- { 1622, 3, 0, 0, "PCMPESTRIOrr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList39, Barriers1, OperandInfo188 }, // Inst #1622 = PCMPESTRIOrr
- { 1623, 7, 0, 0, "PCMPESTRISrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList39, Barriers1, OperandInfo187 }, // Inst #1623 = PCMPESTRISrm
- { 1624, 3, 0, 0, "PCMPESTRISrr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList39, Barriers1, OperandInfo188 }, // Inst #1624 = PCMPESTRISrr
- { 1625, 7, 0, 0, "PCMPESTRIZrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList39, Barriers1, OperandInfo187 }, // Inst #1625 = PCMPESTRIZrm
- { 1626, 3, 0, 0, "PCMPESTRIZrr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList39, Barriers1, OperandInfo188 }, // Inst #1626 = PCMPESTRIZrr
- { 1627, 7, 0, 0, "PCMPESTRIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList39, Barriers1, OperandInfo187 }, // Inst #1627 = PCMPESTRIrm
- { 1628, 3, 0, 0, "PCMPESTRIrr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList39, Barriers1, OperandInfo188 }, // Inst #1628 = PCMPESTRIrr
- { 1629, 8, 1, 0, "PCMPESTRM128MEM", 0|(1<<TID::MayLoad)|(1<<TID::UsesCustomInserter), 0|(1<<6)|(14<<8), ImplicitList14, ImplicitList1, Barriers1, OperandInfo189 }, // Inst #1629 = PCMPESTRM128MEM
- { 1630, 4, 1, 0, "PCMPESTRM128REG", 0|(1<<TID::UsesCustomInserter), 0|(1<<6)|(14<<8), ImplicitList14, ImplicitList1, Barriers1, OperandInfo66 }, // Inst #1630 = PCMPESTRM128REG
- { 1631, 7, 0, 0, "PCMPESTRM128rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(14<<8)|(96<<24), ImplicitList14, ImplicitList40, Barriers1, OperandInfo187 }, // Inst #1631 = PCMPESTRM128rm
- { 1632, 3, 0, 0, "PCMPESTRM128rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(14<<8)|(96<<24), ImplicitList14, ImplicitList40, Barriers1, OperandInfo188 }, // Inst #1632 = PCMPESTRM128rr
- { 1633, 7, 1, 0, "PCMPGTBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(100<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1633 = PCMPGTBrm
- { 1634, 3, 1, 0, "PCMPGTBrr", 0, 0|5|(1<<6)|(1<<8)|(100<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1634 = PCMPGTBrr
- { 1635, 7, 1, 0, "PCMPGTDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(102<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1635 = PCMPGTDrm
- { 1636, 3, 1, 0, "PCMPGTDrr", 0, 0|5|(1<<6)|(1<<8)|(102<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1636 = PCMPGTDrr
- { 1637, 7, 1, 0, "PCMPGTQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(55<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1637 = PCMPGTQrm
- { 1638, 3, 1, 0, "PCMPGTQrr", 0, 0|5|(1<<6)|(13<<8)|(55<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1638 = PCMPGTQrr
- { 1639, 7, 1, 0, "PCMPGTWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(101<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1639 = PCMPGTWrm
- { 1640, 3, 1, 0, "PCMPGTWrr", 0, 0|5|(1<<6)|(1<<8)|(101<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1640 = PCMPGTWrr
- { 1641, 7, 0, 0, "PCMPISTRIArm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList39, Barriers1, OperandInfo187 }, // Inst #1641 = PCMPISTRIArm
- { 1642, 3, 0, 0, "PCMPISTRIArr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList39, Barriers1, OperandInfo188 }, // Inst #1642 = PCMPISTRIArr
- { 1643, 7, 0, 0, "PCMPISTRICrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList39, Barriers1, OperandInfo187 }, // Inst #1643 = PCMPISTRICrm
- { 1644, 3, 0, 0, "PCMPISTRICrr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList39, Barriers1, OperandInfo188 }, // Inst #1644 = PCMPISTRICrr
- { 1645, 7, 0, 0, "PCMPISTRIOrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList39, Barriers1, OperandInfo187 }, // Inst #1645 = PCMPISTRIOrm
- { 1646, 3, 0, 0, "PCMPISTRIOrr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList39, Barriers1, OperandInfo188 }, // Inst #1646 = PCMPISTRIOrr
- { 1647, 7, 0, 0, "PCMPISTRISrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList39, Barriers1, OperandInfo187 }, // Inst #1647 = PCMPISTRISrm
- { 1648, 3, 0, 0, "PCMPISTRISrr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList39, Barriers1, OperandInfo188 }, // Inst #1648 = PCMPISTRISrr
- { 1649, 7, 0, 0, "PCMPISTRIZrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList39, Barriers1, OperandInfo187 }, // Inst #1649 = PCMPISTRIZrm
- { 1650, 3, 0, 0, "PCMPISTRIZrr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList39, Barriers1, OperandInfo188 }, // Inst #1650 = PCMPISTRIZrr
- { 1651, 7, 0, 0, "PCMPISTRIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList39, Barriers1, OperandInfo187 }, // Inst #1651 = PCMPISTRIrm
- { 1652, 3, 0, 0, "PCMPISTRIrr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList39, Barriers1, OperandInfo188 }, // Inst #1652 = PCMPISTRIrr
- { 1653, 8, 1, 0, "PCMPISTRM128MEM", 0|(1<<TID::MayLoad)|(1<<TID::UsesCustomInserter), 0|(1<<6)|(14<<8), NULL, ImplicitList1, Barriers1, OperandInfo189 }, // Inst #1653 = PCMPISTRM128MEM
- { 1654, 4, 1, 0, "PCMPISTRM128REG", 0|(1<<TID::UsesCustomInserter), 0|(1<<6)|(14<<8), NULL, ImplicitList1, Barriers1, OperandInfo66 }, // Inst #1654 = PCMPISTRM128REG
- { 1655, 7, 0, 0, "PCMPISTRM128rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(14<<8)|(98<<24), NULL, ImplicitList40, Barriers1, OperandInfo187 }, // Inst #1655 = PCMPISTRM128rm
- { 1656, 3, 0, 0, "PCMPISTRM128rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(14<<8)|(98<<24), NULL, ImplicitList40, Barriers1, OperandInfo188 }, // Inst #1656 = PCMPISTRM128rr
- { 1657, 7, 0, 0, "PEXTRBmr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(14<<8)|(1<<13)|(20<<24), NULL, NULL, NULL, OperandInfo95 }, // Inst #1657 = PEXTRBmr
- { 1658, 3, 1, 0, "PEXTRBrr", 0, 0|3|(1<<6)|(14<<8)|(1<<13)|(20<<24), NULL, NULL, NULL, OperandInfo96 }, // Inst #1658 = PEXTRBrr
- { 1659, 7, 0, 0, "PEXTRDmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(14<<8)|(1<<13)|(22<<24), NULL, NULL, NULL, OperandInfo95 }, // Inst #1659 = PEXTRDmr
- { 1660, 3, 1, 0, "PEXTRDrr", 0, 0|3|(1<<6)|(14<<8)|(1<<13)|(22<<24), NULL, NULL, NULL, OperandInfo96 }, // Inst #1660 = PEXTRDrr
- { 1661, 7, 0, 0, "PEXTRQmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(14<<8)|(1<<12)|(1<<13)|(22<<24), NULL, NULL, NULL, OperandInfo95 }, // Inst #1661 = PEXTRQmr
- { 1662, 3, 1, 0, "PEXTRQrr", 0, 0|3|(1<<6)|(14<<8)|(1<<12)|(1<<13)|(22<<24), NULL, NULL, NULL, OperandInfo190 }, // Inst #1662 = PEXTRQrr
- { 1663, 7, 0, 0, "PEXTRWmr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(14<<8)|(1<<13)|(21<<24), NULL, NULL, NULL, OperandInfo95 }, // Inst #1663 = PEXTRWmr
- { 1664, 3, 1, 0, "PEXTRWri", 0, 0|5|(1<<6)|(1<<8)|(1<<13)|(197<<24), NULL, NULL, NULL, OperandInfo96 }, // Inst #1664 = PEXTRWri
- { 1665, 7, 1, 0, "PHADDDrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(2<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1665 = PHADDDrm128
- { 1666, 7, 1, 0, "PHADDDrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(2<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1666 = PHADDDrm64
- { 1667, 3, 1, 0, "PHADDDrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(2<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1667 = PHADDDrr128
- { 1668, 3, 1, 0, "PHADDDrr64", 0, 0|5|(13<<8)|(1<<13)|(2<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1668 = PHADDDrr64
- { 1669, 7, 1, 0, "PHADDSWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(3<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1669 = PHADDSWrm128
- { 1670, 7, 1, 0, "PHADDSWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(3<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1670 = PHADDSWrm64
- { 1671, 3, 1, 0, "PHADDSWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(3<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1671 = PHADDSWrr128
- { 1672, 3, 1, 0, "PHADDSWrr64", 0, 0|5|(13<<8)|(1<<13)|(3<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1672 = PHADDSWrr64
- { 1673, 7, 1, 0, "PHADDWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(1<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1673 = PHADDWrm128
- { 1674, 7, 1, 0, "PHADDWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(1<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1674 = PHADDWrm64
- { 1675, 3, 1, 0, "PHADDWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(1<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1675 = PHADDWrr128
- { 1676, 3, 1, 0, "PHADDWrr64", 0, 0|5|(13<<8)|(1<<13)|(1<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1676 = PHADDWrr64
- { 1677, 6, 1, 0, "PHMINPOSUWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(65<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1677 = PHMINPOSUWrm128
- { 1678, 2, 1, 0, "PHMINPOSUWrr128", 0, 0|5|(1<<6)|(13<<8)|(65<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1678 = PHMINPOSUWrr128
- { 1679, 7, 1, 0, "PHSUBDrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(6<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1679 = PHSUBDrm128
- { 1680, 7, 1, 0, "PHSUBDrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(6<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1680 = PHSUBDrm64
- { 1681, 3, 1, 0, "PHSUBDrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(6<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1681 = PHSUBDrr128
- { 1682, 3, 1, 0, "PHSUBDrr64", 0, 0|5|(13<<8)|(1<<13)|(6<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1682 = PHSUBDrr64
- { 1683, 7, 1, 0, "PHSUBSWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(7<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1683 = PHSUBSWrm128
- { 1684, 7, 1, 0, "PHSUBSWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(7<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1684 = PHSUBSWrm64
- { 1685, 3, 1, 0, "PHSUBSWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(7<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1685 = PHSUBSWrr128
- { 1686, 3, 1, 0, "PHSUBSWrr64", 0, 0|5|(13<<8)|(1<<13)|(7<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1686 = PHSUBSWrr64
- { 1687, 7, 1, 0, "PHSUBWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(5<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1687 = PHSUBWrm128
- { 1688, 7, 1, 0, "PHSUBWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(5<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1688 = PHSUBWrm64
- { 1689, 3, 1, 0, "PHSUBWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(5<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1689 = PHSUBWrr128
- { 1690, 3, 1, 0, "PHSUBWrr64", 0, 0|5|(13<<8)|(1<<13)|(5<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1690 = PHSUBWrr64
- { 1691, 8, 1, 0, "PINSRBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(32<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1691 = PINSRBrm
- { 1692, 4, 1, 0, "PINSRBrr", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(32<<24), NULL, NULL, NULL, OperandInfo191 }, // Inst #1692 = PINSRBrr
- { 1693, 8, 1, 0, "PINSRDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(34<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1693 = PINSRDrm
- { 1694, 4, 1, 0, "PINSRDrr", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(34<<24), NULL, NULL, NULL, OperandInfo191 }, // Inst #1694 = PINSRDrr
- { 1695, 8, 1, 0, "PINSRQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<12)|(1<<13)|(34<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1695 = PINSRQrm
- { 1696, 4, 1, 0, "PINSRQrr", 0, 0|5|(1<<6)|(14<<8)|(1<<12)|(1<<13)|(34<<24), NULL, NULL, NULL, OperandInfo192 }, // Inst #1696 = PINSRQrr
- { 1697, 8, 1, 0, "PINSRWrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(1<<13)|(196<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1697 = PINSRWrmi
- { 1698, 4, 1, 0, "PINSRWrri", 0, 0|5|(1<<6)|(1<<8)|(1<<13)|(196<<24), NULL, NULL, NULL, OperandInfo191 }, // Inst #1698 = PINSRWrri
- { 1699, 7, 1, 0, "PMADDUBSWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(4<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1699 = PMADDUBSWrm128
- { 1700, 7, 1, 0, "PMADDUBSWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(4<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1700 = PMADDUBSWrm64
- { 1701, 3, 1, 0, "PMADDUBSWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(4<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1701 = PMADDUBSWrr128
- { 1702, 3, 1, 0, "PMADDUBSWrr64", 0, 0|5|(13<<8)|(1<<13)|(4<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1702 = PMADDUBSWrr64
- { 1703, 7, 1, 0, "PMADDWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(245<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1703 = PMADDWDrm
- { 1704, 3, 1, 0, "PMADDWDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(245<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1704 = PMADDWDrr
- { 1705, 7, 1, 0, "PMAXSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(60<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1705 = PMAXSBrm
- { 1706, 3, 1, 0, "PMAXSBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(60<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1706 = PMAXSBrr
- { 1707, 7, 1, 0, "PMAXSDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(61<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1707 = PMAXSDrm
- { 1708, 3, 1, 0, "PMAXSDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(61<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1708 = PMAXSDrr
- { 1709, 7, 1, 0, "PMAXSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(238<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1709 = PMAXSWrm
- { 1710, 3, 1, 0, "PMAXSWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(238<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1710 = PMAXSWrr
- { 1711, 7, 1, 0, "PMAXUBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(222<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1711 = PMAXUBrm
- { 1712, 3, 1, 0, "PMAXUBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(222<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1712 = PMAXUBrr
- { 1713, 7, 1, 0, "PMAXUDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(63<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1713 = PMAXUDrm
- { 1714, 3, 1, 0, "PMAXUDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(63<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1714 = PMAXUDrr
- { 1715, 7, 1, 0, "PMAXUWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(62<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1715 = PMAXUWrm
- { 1716, 3, 1, 0, "PMAXUWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(62<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1716 = PMAXUWrr
- { 1717, 7, 1, 0, "PMINSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(56<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1717 = PMINSBrm
- { 1718, 3, 1, 0, "PMINSBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(56<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1718 = PMINSBrr
- { 1719, 7, 1, 0, "PMINSDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(57<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1719 = PMINSDrm
- { 1720, 3, 1, 0, "PMINSDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(57<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1720 = PMINSDrr
- { 1721, 7, 1, 0, "PMINSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(234<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1721 = PMINSWrm
- { 1722, 3, 1, 0, "PMINSWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(234<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1722 = PMINSWrr
- { 1723, 7, 1, 0, "PMINUBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(218<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1723 = PMINUBrm
- { 1724, 3, 1, 0, "PMINUBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(218<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1724 = PMINUBrr
- { 1725, 7, 1, 0, "PMINUDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(59<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1725 = PMINUDrm
- { 1726, 3, 1, 0, "PMINUDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(59<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1726 = PMINUDrr
- { 1727, 7, 1, 0, "PMINUWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(58<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1727 = PMINUWrm
- { 1728, 3, 1, 0, "PMINUWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(58<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1728 = PMINUWrr
- { 1729, 2, 1, 0, "PMOVMSKBrr", 0, 0|5|(1<<6)|(1<<8)|(215<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #1729 = PMOVMSKBrr
- { 1730, 6, 1, 0, "PMOVSXBDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(33<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1730 = PMOVSXBDrm
- { 1731, 2, 1, 0, "PMOVSXBDrr", 0, 0|5|(1<<6)|(13<<8)|(33<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1731 = PMOVSXBDrr
- { 1732, 6, 1, 0, "PMOVSXBQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(34<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1732 = PMOVSXBQrm
- { 1733, 2, 1, 0, "PMOVSXBQrr", 0, 0|5|(1<<6)|(13<<8)|(34<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1733 = PMOVSXBQrr
- { 1734, 6, 1, 0, "PMOVSXBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(32<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1734 = PMOVSXBWrm
- { 1735, 2, 1, 0, "PMOVSXBWrr", 0, 0|5|(1<<6)|(13<<8)|(32<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1735 = PMOVSXBWrr
- { 1736, 6, 1, 0, "PMOVSXDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(37<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1736 = PMOVSXDQrm
- { 1737, 2, 1, 0, "PMOVSXDQrr", 0, 0|5|(1<<6)|(13<<8)|(37<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1737 = PMOVSXDQrr
- { 1738, 6, 1, 0, "PMOVSXWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(35<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1738 = PMOVSXWDrm
- { 1739, 2, 1, 0, "PMOVSXWDrr", 0, 0|5|(1<<6)|(13<<8)|(35<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1739 = PMOVSXWDrr
- { 1740, 6, 1, 0, "PMOVSXWQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(36<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1740 = PMOVSXWQrm
- { 1741, 2, 1, 0, "PMOVSXWQrr", 0, 0|5|(1<<6)|(13<<8)|(36<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1741 = PMOVSXWQrr
- { 1742, 6, 1, 0, "PMOVZXBDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(49<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1742 = PMOVZXBDrm
- { 1743, 2, 1, 0, "PMOVZXBDrr", 0, 0|5|(1<<6)|(13<<8)|(49<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1743 = PMOVZXBDrr
- { 1744, 6, 1, 0, "PMOVZXBQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(50<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1744 = PMOVZXBQrm
- { 1745, 2, 1, 0, "PMOVZXBQrr", 0, 0|5|(1<<6)|(13<<8)|(50<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1745 = PMOVZXBQrr
- { 1746, 6, 1, 0, "PMOVZXBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(48<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1746 = PMOVZXBWrm
- { 1747, 2, 1, 0, "PMOVZXBWrr", 0, 0|5|(1<<6)|(13<<8)|(48<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1747 = PMOVZXBWrr
- { 1748, 6, 1, 0, "PMOVZXDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(53<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1748 = PMOVZXDQrm
- { 1749, 2, 1, 0, "PMOVZXDQrr", 0, 0|5|(1<<6)|(13<<8)|(53<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1749 = PMOVZXDQrr
- { 1750, 6, 1, 0, "PMOVZXWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(51<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1750 = PMOVZXWDrm
- { 1751, 2, 1, 0, "PMOVZXWDrr", 0, 0|5|(1<<6)|(13<<8)|(51<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1751 = PMOVZXWDrr
- { 1752, 6, 1, 0, "PMOVZXWQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(52<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1752 = PMOVZXWQrm
- { 1753, 2, 1, 0, "PMOVZXWQrr", 0, 0|5|(1<<6)|(13<<8)|(52<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1753 = PMOVZXWQrr
- { 1754, 7, 1, 0, "PMULDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(40<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1754 = PMULDQrm
- { 1755, 3, 1, 0, "PMULDQrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(40<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1755 = PMULDQrr
- { 1756, 7, 1, 0, "PMULHRSWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1756 = PMULHRSWrm128
- { 1757, 7, 1, 0, "PMULHRSWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1757 = PMULHRSWrm64
- { 1758, 3, 1, 0, "PMULHRSWrr128", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1758 = PMULHRSWrr128
- { 1759, 3, 1, 0, "PMULHRSWrr64", 0|(1<<TID::Commutable), 0|5|(13<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1759 = PMULHRSWrr64
- { 1760, 7, 1, 0, "PMULHUWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(228<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1760 = PMULHUWrm
- { 1761, 3, 1, 0, "PMULHUWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(228<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1761 = PMULHUWrr
- { 1762, 7, 1, 0, "PMULHWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(229<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1762 = PMULHWrm
- { 1763, 3, 1, 0, "PMULHWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(229<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1763 = PMULHWrr
- { 1764, 7, 1, 0, "PMULLDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(64<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1764 = PMULLDrm
- { 1765, 7, 1, 0, "PMULLDrm_int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(64<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1765 = PMULLDrm_int
- { 1766, 3, 1, 0, "PMULLDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(64<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1766 = PMULLDrr
- { 1767, 3, 1, 0, "PMULLDrr_int", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(64<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1767 = PMULLDrr_int
- { 1768, 7, 1, 0, "PMULLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(213<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1768 = PMULLWrm
- { 1769, 3, 1, 0, "PMULLWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(213<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1769 = PMULLWrr
- { 1770, 7, 1, 0, "PMULUDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(244<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1770 = PMULUDQrm
- { 1771, 3, 1, 0, "PMULUDQrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(244<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1771 = PMULUDQrr
- { 1772, 1, 1, 0, "POP16r", 0|(1<<TID::MayLoad), 0|2|(1<<6)|(88<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo93 }, // Inst #1772 = POP16r
- { 1773, 5, 1, 0, "POP16rmm", 0|(1<<TID::MayLoad), 0|24|(1<<6)|(143<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo30 }, // Inst #1773 = POP16rmm
- { 1774, 1, 1, 0, "POP16rmr", 0|(1<<TID::MayLoad), 0|16|(1<<6)|(143<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo93 }, // Inst #1774 = POP16rmr
- { 1775, 1, 1, 0, "POP32r", 0|(1<<TID::MayLoad), 0|2|(88<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo57 }, // Inst #1775 = POP32r
- { 1776, 5, 1, 0, "POP32rmm", 0|(1<<TID::MayLoad), 0|24|(143<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo30 }, // Inst #1776 = POP32rmm
- { 1777, 1, 1, 0, "POP32rmr", 0|(1<<TID::MayLoad), 0|16|(143<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo57 }, // Inst #1777 = POP32rmr
- { 1778, 1, 1, 0, "POP64r", 0|(1<<TID::MayLoad), 0|2|(88<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo58 }, // Inst #1778 = POP64r
- { 1779, 5, 1, 0, "POP64rmm", 0|(1<<TID::MayLoad), 0|24|(143<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo30 }, // Inst #1779 = POP64rmm
- { 1780, 1, 1, 0, "POP64rmr", 0|(1<<TID::MayLoad), 0|16|(143<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo58 }, // Inst #1780 = POP64rmr
- { 1781, 6, 1, 0, "POPCNT16rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(12<<8)|(184<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1781 = POPCNT16rm
- { 1782, 2, 1, 0, "POPCNT16rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(12<<8)|(184<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #1782 = POPCNT16rr
- { 1783, 6, 1, 0, "POPCNT32rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(12<<8)|(184<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1783 = POPCNT32rm
- { 1784, 2, 1, 0, "POPCNT32rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(12<<8)|(184<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #1784 = POPCNT32rr
- { 1785, 6, 1, 0, "POPCNT64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(12<<8)|(1<<12)|(184<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1785 = POPCNT64rm
- { 1786, 2, 1, 0, "POPCNT64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(12<<8)|(1<<12)|(184<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #1786 = POPCNT64rr
- { 1787, 0, 0, 0, "POPF", 0|(1<<TID::MayLoad), 0|1|(1<<6)|(157<<24), ImplicitList2, ImplicitList3, Barriers1, 0 }, // Inst #1787 = POPF
- { 1788, 0, 0, 0, "POPFD", 0|(1<<TID::MayLoad), 0|1|(157<<24), ImplicitList2, ImplicitList3, Barriers1, 0 }, // Inst #1788 = POPFD
- { 1789, 0, 0, 0, "POPFQ", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(157<<24), ImplicitList4, ImplicitList5, Barriers1, 0 }, // Inst #1789 = POPFQ
- { 1790, 0, 0, 0, "POPFS16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<8)|(161<<24), NULL, NULL, NULL, 0 }, // Inst #1790 = POPFS16
- { 1791, 0, 0, 0, "POPFS32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(161<<24), NULL, NULL, NULL, 0 }, // Inst #1791 = POPFS32
- { 1792, 0, 0, 0, "POPFS64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(161<<24), NULL, NULL, NULL, 0 }, // Inst #1792 = POPFS64
- { 1793, 0, 0, 0, "POPGS16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<8)|(169<<24), NULL, NULL, NULL, 0 }, // Inst #1793 = POPGS16
- { 1794, 0, 0, 0, "POPGS32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(169<<24), NULL, NULL, NULL, 0 }, // Inst #1794 = POPGS32
- { 1795, 0, 0, 0, "POPGS64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(169<<24), NULL, NULL, NULL, 0 }, // Inst #1795 = POPGS64
- { 1796, 7, 1, 0, "PORrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(235<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1796 = PORrm
- { 1797, 3, 1, 0, "PORrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(235<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1797 = PORrr
- { 1798, 5, 0, 0, "PREFETCHNTA", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<8)|(24<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1798 = PREFETCHNTA
- { 1799, 5, 0, 0, "PREFETCHT0", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<8)|(24<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1799 = PREFETCHT0
- { 1800, 5, 0, 0, "PREFETCHT1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<8)|(24<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1800 = PREFETCHT1
- { 1801, 5, 0, 0, "PREFETCHT2", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<8)|(24<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1801 = PREFETCHT2
- { 1802, 7, 1, 0, "PSADBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(246<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1802 = PSADBWrm
- { 1803, 3, 1, 0, "PSADBWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(246<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1803 = PSADBWrr
- { 1804, 7, 1, 0, "PSHUFBrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13), NULL, NULL, NULL, OperandInfo24 }, // Inst #1804 = PSHUFBrm128
- { 1805, 7, 1, 0, "PSHUFBrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13), NULL, NULL, NULL, OperandInfo136 }, // Inst #1805 = PSHUFBrm64
- { 1806, 3, 1, 0, "PSHUFBrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13), NULL, NULL, NULL, OperandInfo25 }, // Inst #1806 = PSHUFBrr128
- { 1807, 3, 1, 0, "PSHUFBrr64", 0, 0|5|(13<<8)|(1<<13), NULL, NULL, NULL, OperandInfo137 }, // Inst #1807 = PSHUFBrr64
- { 1808, 7, 1, 0, "PSHUFDmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo187 }, // Inst #1808 = PSHUFDmi
- { 1809, 3, 1, 0, "PSHUFDri", 0, 0|5|(1<<6)|(1<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo188 }, // Inst #1809 = PSHUFDri
- { 1810, 7, 1, 0, "PSHUFHWmi", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo187 }, // Inst #1810 = PSHUFHWmi
- { 1811, 3, 1, 0, "PSHUFHWri", 0, 0|5|(12<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo188 }, // Inst #1811 = PSHUFHWri
- { 1812, 7, 1, 0, "PSHUFLWmi", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo187 }, // Inst #1812 = PSHUFLWmi
- { 1813, 3, 1, 0, "PSHUFLWri", 0, 0|5|(11<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo188 }, // Inst #1813 = PSHUFLWri
- { 1814, 7, 1, 0, "PSIGNBrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1814 = PSIGNBrm128
- { 1815, 7, 1, 0, "PSIGNBrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1815 = PSIGNBrm64
- { 1816, 3, 1, 0, "PSIGNBrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1816 = PSIGNBrr128
- { 1817, 3, 1, 0, "PSIGNBrr64", 0, 0|5|(13<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1817 = PSIGNBrr64
- { 1818, 7, 1, 0, "PSIGNDrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1818 = PSIGNDrm128
- { 1819, 7, 1, 0, "PSIGNDrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1819 = PSIGNDrm64
- { 1820, 3, 1, 0, "PSIGNDrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1820 = PSIGNDrr128
- { 1821, 3, 1, 0, "PSIGNDrr64", 0, 0|5|(13<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1821 = PSIGNDrr64
- { 1822, 7, 1, 0, "PSIGNWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1822 = PSIGNWrm128
- { 1823, 7, 1, 0, "PSIGNWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1823 = PSIGNWrm64
- { 1824, 3, 1, 0, "PSIGNWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1824 = PSIGNWrr128
- { 1825, 3, 1, 0, "PSIGNWrr64", 0, 0|5|(13<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1825 = PSIGNWrr64
- { 1826, 3, 1, 0, "PSLLDQri", 0, 0|23|(1<<6)|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo193 }, // Inst #1826 = PSLLDQri
- { 1827, 3, 1, 0, "PSLLDri", 0, 0|22|(1<<6)|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo193 }, // Inst #1827 = PSLLDri
- { 1828, 7, 1, 0, "PSLLDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(242<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1828 = PSLLDrm
- { 1829, 3, 1, 0, "PSLLDrr", 0, 0|5|(1<<6)|(1<<8)|(242<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1829 = PSLLDrr
- { 1830, 3, 1, 0, "PSLLQri", 0, 0|22|(1<<6)|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo193 }, // Inst #1830 = PSLLQri
- { 1831, 7, 1, 0, "PSLLQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(243<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1831 = PSLLQrm
- { 1832, 3, 1, 0, "PSLLQrr", 0, 0|5|(1<<6)|(1<<8)|(243<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1832 = PSLLQrr
- { 1833, 3, 1, 0, "PSLLWri", 0, 0|22|(1<<6)|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo193 }, // Inst #1833 = PSLLWri
- { 1834, 7, 1, 0, "PSLLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(241<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1834 = PSLLWrm
- { 1835, 3, 1, 0, "PSLLWrr", 0, 0|5|(1<<6)|(1<<8)|(241<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1835 = PSLLWrr
- { 1836, 3, 1, 0, "PSRADri", 0, 0|20|(1<<6)|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo193 }, // Inst #1836 = PSRADri
- { 1837, 7, 1, 0, "PSRADrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(226<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1837 = PSRADrm
- { 1838, 3, 1, 0, "PSRADrr", 0, 0|5|(1<<6)|(1<<8)|(226<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1838 = PSRADrr
- { 1839, 3, 1, 0, "PSRAWri", 0, 0|20|(1<<6)|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo193 }, // Inst #1839 = PSRAWri
- { 1840, 7, 1, 0, "PSRAWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(225<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1840 = PSRAWrm
- { 1841, 3, 1, 0, "PSRAWrr", 0, 0|5|(1<<6)|(1<<8)|(225<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1841 = PSRAWrr
- { 1842, 3, 1, 0, "PSRLDQri", 0, 0|19|(1<<6)|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo193 }, // Inst #1842 = PSRLDQri
- { 1843, 3, 1, 0, "PSRLDri", 0, 0|18|(1<<6)|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo193 }, // Inst #1843 = PSRLDri
- { 1844, 7, 1, 0, "PSRLDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(210<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1844 = PSRLDrm
- { 1845, 3, 1, 0, "PSRLDrr", 0, 0|5|(1<<6)|(1<<8)|(210<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1845 = PSRLDrr
- { 1846, 3, 1, 0, "PSRLQri", 0, 0|18|(1<<6)|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo193 }, // Inst #1846 = PSRLQri
- { 1847, 7, 1, 0, "PSRLQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(211<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1847 = PSRLQrm
- { 1848, 3, 1, 0, "PSRLQrr", 0, 0|5|(1<<6)|(1<<8)|(211<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1848 = PSRLQrr
- { 1849, 3, 1, 0, "PSRLWri", 0, 0|18|(1<<6)|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo193 }, // Inst #1849 = PSRLWri
- { 1850, 7, 1, 0, "PSRLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(209<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1850 = PSRLWrm
- { 1851, 3, 1, 0, "PSRLWrr", 0, 0|5|(1<<6)|(1<<8)|(209<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1851 = PSRLWrr
- { 1852, 7, 1, 0, "PSUBBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(248<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1852 = PSUBBrm
- { 1853, 3, 1, 0, "PSUBBrr", 0, 0|5|(1<<6)|(1<<8)|(248<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1853 = PSUBBrr
- { 1854, 7, 1, 0, "PSUBDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(250<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1854 = PSUBDrm
- { 1855, 3, 1, 0, "PSUBDrr", 0, 0|5|(1<<6)|(1<<8)|(250<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1855 = PSUBDrr
- { 1856, 7, 1, 0, "PSUBQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(251<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1856 = PSUBQrm
- { 1857, 3, 1, 0, "PSUBQrr", 0, 0|5|(1<<6)|(1<<8)|(251<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1857 = PSUBQrr
- { 1858, 7, 1, 0, "PSUBSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(232<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1858 = PSUBSBrm
- { 1859, 3, 1, 0, "PSUBSBrr", 0, 0|5|(1<<6)|(1<<8)|(232<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1859 = PSUBSBrr
- { 1860, 7, 1, 0, "PSUBSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(233<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1860 = PSUBSWrm
- { 1861, 3, 1, 0, "PSUBSWrr", 0, 0|5|(1<<6)|(1<<8)|(233<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1861 = PSUBSWrr
- { 1862, 7, 1, 0, "PSUBUSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(216<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1862 = PSUBUSBrm
- { 1863, 3, 1, 0, "PSUBUSBrr", 0, 0|5|(1<<6)|(1<<8)|(216<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1863 = PSUBUSBrr
- { 1864, 7, 1, 0, "PSUBUSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(217<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1864 = PSUBUSWrm
- { 1865, 3, 1, 0, "PSUBUSWrr", 0, 0|5|(1<<6)|(1<<8)|(217<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1865 = PSUBUSWrr
- { 1866, 7, 1, 0, "PSUBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(249<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1866 = PSUBWrm
- { 1867, 3, 1, 0, "PSUBWrr", 0, 0|5|(1<<6)|(1<<8)|(249<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1867 = PSUBWrr
- { 1868, 6, 0, 0, "PTESTrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(23<<24), NULL, ImplicitList1, Barriers1, OperandInfo74 }, // Inst #1868 = PTESTrm
- { 1869, 2, 0, 0, "PTESTrr", 0, 0|5|(1<<6)|(13<<8)|(23<<24), NULL, ImplicitList1, Barriers1, OperandInfo75 }, // Inst #1869 = PTESTrr
- { 1870, 7, 1, 0, "PUNPCKHBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(104<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1870 = PUNPCKHBWrm
- { 1871, 3, 1, 0, "PUNPCKHBWrr", 0, 0|5|(1<<6)|(1<<8)|(104<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1871 = PUNPCKHBWrr
- { 1872, 7, 1, 0, "PUNPCKHDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(106<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1872 = PUNPCKHDQrm
- { 1873, 3, 1, 0, "PUNPCKHDQrr", 0, 0|5|(1<<6)|(1<<8)|(106<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1873 = PUNPCKHDQrr
- { 1874, 7, 1, 0, "PUNPCKHQDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(109<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1874 = PUNPCKHQDQrm
- { 1875, 3, 1, 0, "PUNPCKHQDQrr", 0, 0|5|(1<<6)|(1<<8)|(109<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1875 = PUNPCKHQDQrr
- { 1876, 7, 1, 0, "PUNPCKHWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(105<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1876 = PUNPCKHWDrm
- { 1877, 3, 1, 0, "PUNPCKHWDrr", 0, 0|5|(1<<6)|(1<<8)|(105<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1877 = PUNPCKHWDrr
- { 1878, 7, 1, 0, "PUNPCKLBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(96<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1878 = PUNPCKLBWrm
- { 1879, 3, 1, 0, "PUNPCKLBWrr", 0, 0|5|(1<<6)|(1<<8)|(96<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1879 = PUNPCKLBWrr
- { 1880, 7, 1, 0, "PUNPCKLDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(98<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1880 = PUNPCKLDQrm
- { 1881, 3, 1, 0, "PUNPCKLDQrr", 0, 0|5|(1<<6)|(1<<8)|(98<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1881 = PUNPCKLDQrr
- { 1882, 7, 1, 0, "PUNPCKLQDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(108<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1882 = PUNPCKLQDQrm
- { 1883, 3, 1, 0, "PUNPCKLQDQrr", 0, 0|5|(1<<6)|(1<<8)|(108<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1883 = PUNPCKLQDQrr
- { 1884, 7, 1, 0, "PUNPCKLWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(97<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1884 = PUNPCKLWDrm
- { 1885, 3, 1, 0, "PUNPCKLWDrr", 0, 0|5|(1<<6)|(1<<8)|(97<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1885 = PUNPCKLWDrr
- { 1886, 1, 0, 0, "PUSH16r", 0|(1<<TID::MayStore), 0|2|(1<<6)|(80<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo93 }, // Inst #1886 = PUSH16r
- { 1887, 5, 0, 0, "PUSH16rmm", 0|(1<<TID::MayStore), 0|30|(1<<6)|(255<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo30 }, // Inst #1887 = PUSH16rmm
- { 1888, 1, 0, 0, "PUSH16rmr", 0|(1<<TID::MayStore), 0|22|(1<<6)|(255<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo93 }, // Inst #1888 = PUSH16rmr
- { 1889, 1, 0, 0, "PUSH32i16", 0|(1<<TID::MayStore), 0|1|(2<<13)|(104<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo5 }, // Inst #1889 = PUSH32i16
- { 1890, 1, 0, 0, "PUSH32i32", 0|(1<<TID::MayStore), 0|1|(3<<13)|(104<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo5 }, // Inst #1890 = PUSH32i32
- { 1891, 1, 0, 0, "PUSH32i8", 0|(1<<TID::MayStore), 0|1|(1<<13)|(106<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo5 }, // Inst #1891 = PUSH32i8
- { 1892, 1, 0, 0, "PUSH32r", 0|(1<<TID::MayStore), 0|2|(80<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo57 }, // Inst #1892 = PUSH32r
- { 1893, 5, 0, 0, "PUSH32rmm", 0|(1<<TID::MayStore), 0|30|(255<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo30 }, // Inst #1893 = PUSH32rmm
- { 1894, 1, 0, 0, "PUSH32rmr", 0|(1<<TID::MayStore), 0|22|(255<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo57 }, // Inst #1894 = PUSH32rmr
- { 1895, 1, 0, 0, "PUSH64i16", 0|(1<<TID::MayStore), 0|1|(2<<13)|(104<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo5 }, // Inst #1895 = PUSH64i16
- { 1896, 1, 0, 0, "PUSH64i32", 0|(1<<TID::MayStore), 0|1|(3<<13)|(104<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo5 }, // Inst #1896 = PUSH64i32
- { 1897, 1, 0, 0, "PUSH64i8", 0|(1<<TID::MayStore), 0|1|(1<<13)|(106<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo5 }, // Inst #1897 = PUSH64i8
- { 1898, 1, 0, 0, "PUSH64r", 0|(1<<TID::MayStore), 0|2|(80<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo58 }, // Inst #1898 = PUSH64r
- { 1899, 5, 0, 0, "PUSH64rmm", 0|(1<<TID::MayStore), 0|30|(255<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo30 }, // Inst #1899 = PUSH64rmm
- { 1900, 1, 0, 0, "PUSH64rmr", 0|(1<<TID::MayStore), 0|22|(255<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo58 }, // Inst #1900 = PUSH64rmr
- { 1901, 0, 0, 0, "PUSHF", 0|(1<<TID::MayStore), 0|1|(1<<6)|(156<<24), ImplicitList3, ImplicitList2, NULL, 0 }, // Inst #1901 = PUSHF
- { 1902, 0, 0, 0, "PUSHFD", 0|(1<<TID::MayStore), 0|1|(156<<24), ImplicitList3, ImplicitList2, NULL, 0 }, // Inst #1902 = PUSHFD
- { 1903, 0, 0, 0, "PUSHFQ64", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|1|(156<<24), ImplicitList5, ImplicitList4, NULL, 0 }, // Inst #1903 = PUSHFQ64
- { 1904, 0, 0, 0, "PUSHFS16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<8)|(160<<24), NULL, NULL, NULL, 0 }, // Inst #1904 = PUSHFS16
- { 1905, 0, 0, 0, "PUSHFS32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(160<<24), NULL, NULL, NULL, 0 }, // Inst #1905 = PUSHFS32
- { 1906, 0, 0, 0, "PUSHFS64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(160<<24), NULL, NULL, NULL, 0 }, // Inst #1906 = PUSHFS64
- { 1907, 0, 0, 0, "PUSHGS16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<8)|(168<<24), NULL, NULL, NULL, 0 }, // Inst #1907 = PUSHGS16
- { 1908, 0, 0, 0, "PUSHGS32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(168<<24), NULL, NULL, NULL, 0 }, // Inst #1908 = PUSHGS32
- { 1909, 0, 0, 0, "PUSHGS64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(168<<24), NULL, NULL, NULL, 0 }, // Inst #1909 = PUSHGS64
- { 1910, 7, 1, 0, "PXORrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1910 = PXORrm
- { 1911, 3, 1, 0, "PXORrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1911 = PXORrr
- { 1912, 10, 1, 0, "RCL16m1", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #1912 = RCL16m1
- { 1913, 10, 1, 0, "RCL16mCL", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<6)|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #1913 = RCL16mCL
- { 1914, 11, 1, 0, "RCL16mi", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo195 }, // Inst #1914 = RCL16mi
- { 1915, 2, 1, 0, "RCL16r1", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1915 = RCL16r1
- { 1916, 2, 1, 0, "RCL16rCL", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<6)|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1916 = RCL16rCL
- { 1917, 3, 1, 0, "RCL16ri", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1917 = RCL16ri
- { 1918, 10, 1, 0, "RCL32m1", 0|(1<<TID::UnmodeledSideEffects), 0|26|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #1918 = RCL32m1
- { 1919, 10, 1, 0, "RCL32mCL", 0|(1<<TID::UnmodeledSideEffects), 0|26|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #1919 = RCL32mCL
- { 1920, 11, 1, 0, "RCL32mi", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo195 }, // Inst #1920 = RCL32mi
- { 1921, 2, 1, 0, "RCL32r1", 0|(1<<TID::UnmodeledSideEffects), 0|18|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1921 = RCL32r1
- { 1922, 2, 1, 0, "RCL32rCL", 0|(1<<TID::UnmodeledSideEffects), 0|18|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1922 = RCL32rCL
- { 1923, 3, 1, 0, "RCL32ri", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1923 = RCL32ri
- { 1924, 10, 1, 0, "RCL64m1", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #1924 = RCL64m1
- { 1925, 10, 1, 0, "RCL64mCL", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<12)|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #1925 = RCL64mCL
- { 1926, 11, 1, 0, "RCL64mi", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo195 }, // Inst #1926 = RCL64mi
- { 1927, 2, 1, 0, "RCL64r1", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #1927 = RCL64r1
- { 1928, 2, 1, 0, "RCL64rCL", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<12)|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #1928 = RCL64rCL
- { 1929, 3, 1, 0, "RCL64ri", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1929 = RCL64ri
- { 1930, 10, 1, 0, "RCL8m1", 0|(1<<TID::UnmodeledSideEffects), 0|26|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #1930 = RCL8m1
- { 1931, 10, 1, 0, "RCL8mCL", 0|(1<<TID::UnmodeledSideEffects), 0|26|(210<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #1931 = RCL8mCL
- { 1932, 11, 1, 0, "RCL8mi", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo195 }, // Inst #1932 = RCL8mi
- { 1933, 2, 1, 0, "RCL8r1", 0|(1<<TID::UnmodeledSideEffects), 0|18|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #1933 = RCL8r1
- { 1934, 2, 1, 0, "RCL8rCL", 0|(1<<TID::UnmodeledSideEffects), 0|18|(210<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #1934 = RCL8rCL
- { 1935, 3, 1, 0, "RCL8ri", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1935 = RCL8ri
- { 1936, 6, 1, 0, "RCPPSm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(83<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1936 = RCPPSm
- { 1937, 6, 1, 0, "RCPPSm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(83<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1937 = RCPPSm_Int
- { 1938, 2, 1, 0, "RCPPSr", 0, 0|5|(1<<8)|(83<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1938 = RCPPSr
- { 1939, 2, 1, 0, "RCPPSr_Int", 0, 0|5|(1<<8)|(83<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1939 = RCPPSr_Int
- { 1940, 6, 1, 0, "RCPSSm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(83<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #1940 = RCPSSm
- { 1941, 6, 1, 0, "RCPSSm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(83<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1941 = RCPSSm_Int
- { 1942, 2, 1, 0, "RCPSSr", 0, 0|5|(12<<8)|(83<<24), NULL, NULL, NULL, OperandInfo106 }, // Inst #1942 = RCPSSr
- { 1943, 2, 1, 0, "RCPSSr_Int", 0, 0|5|(12<<8)|(83<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1943 = RCPSSr_Int
- { 1944, 10, 1, 0, "RCR16m1", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #1944 = RCR16m1
- { 1945, 10, 1, 0, "RCR16mCL", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<6)|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #1945 = RCR16mCL
- { 1946, 11, 1, 0, "RCR16mi", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo195 }, // Inst #1946 = RCR16mi
- { 1947, 2, 1, 0, "RCR16r1", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1947 = RCR16r1
- { 1948, 2, 1, 0, "RCR16rCL", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<6)|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1948 = RCR16rCL
- { 1949, 3, 1, 0, "RCR16ri", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1949 = RCR16ri
- { 1950, 10, 1, 0, "RCR32m1", 0|(1<<TID::UnmodeledSideEffects), 0|27|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #1950 = RCR32m1
- { 1951, 10, 1, 0, "RCR32mCL", 0|(1<<TID::UnmodeledSideEffects), 0|27|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #1951 = RCR32mCL
- { 1952, 11, 1, 0, "RCR32mi", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo195 }, // Inst #1952 = RCR32mi
- { 1953, 2, 1, 0, "RCR32r1", 0|(1<<TID::UnmodeledSideEffects), 0|19|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1953 = RCR32r1
- { 1954, 2, 1, 0, "RCR32rCL", 0|(1<<TID::UnmodeledSideEffects), 0|19|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1954 = RCR32rCL
- { 1955, 3, 1, 0, "RCR32ri", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1955 = RCR32ri
- { 1956, 10, 1, 0, "RCR64m1", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #1956 = RCR64m1
- { 1957, 10, 1, 0, "RCR64mCL", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<12)|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #1957 = RCR64mCL
- { 1958, 11, 1, 0, "RCR64mi", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo195 }, // Inst #1958 = RCR64mi
- { 1959, 2, 1, 0, "RCR64r1", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #1959 = RCR64r1
- { 1960, 2, 1, 0, "RCR64rCL", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<12)|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #1960 = RCR64rCL
- { 1961, 3, 1, 0, "RCR64ri", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1961 = RCR64ri
- { 1962, 10, 1, 0, "RCR8m1", 0|(1<<TID::UnmodeledSideEffects), 0|27|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #1962 = RCR8m1
- { 1963, 10, 1, 0, "RCR8mCL", 0|(1<<TID::UnmodeledSideEffects), 0|27|(210<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #1963 = RCR8mCL
- { 1964, 11, 1, 0, "RCR8mi", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo195 }, // Inst #1964 = RCR8mi
- { 1965, 2, 1, 0, "RCR8r1", 0|(1<<TID::UnmodeledSideEffects), 0|19|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #1965 = RCR8r1
- { 1966, 2, 1, 0, "RCR8rCL", 0|(1<<TID::UnmodeledSideEffects), 0|19|(210<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #1966 = RCR8rCL
- { 1967, 3, 1, 0, "RCR8ri", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1967 = RCR8ri
- { 1968, 0, 0, 0, "RDMSR", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(50<<24), NULL, NULL, NULL, 0 }, // Inst #1968 = RDMSR
- { 1969, 0, 0, 0, "RDPMC", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(51<<24), NULL, NULL, NULL, 0 }, // Inst #1969 = RDPMC
- { 1970, 0, 0, 0, "RDTSC", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(49<<24), NULL, ImplicitList19, NULL, 0 }, // Inst #1970 = RDTSC
- { 1971, 0, 0, 0, "REP_MOVSB", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|1|(2<<8)|(164<<24), ImplicitList42, ImplicitList42, NULL, 0 }, // Inst #1971 = REP_MOVSB
- { 1972, 0, 0, 0, "REP_MOVSD", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|1|(2<<8)|(165<<24), ImplicitList42, ImplicitList42, NULL, 0 }, // Inst #1972 = REP_MOVSD
- { 1973, 0, 0, 0, "REP_MOVSQ", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|1|(2<<8)|(1<<12)|(165<<24), ImplicitList43, ImplicitList43, NULL, 0 }, // Inst #1973 = REP_MOVSQ
- { 1974, 0, 0, 0, "REP_MOVSW", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|1|(1<<6)|(2<<8)|(165<<24), ImplicitList42, ImplicitList42, NULL, 0 }, // Inst #1974 = REP_MOVSW
- { 1975, 0, 0, 0, "REP_STOSB", 0|(1<<TID::MayStore), 0|1|(2<<8)|(170<<24), ImplicitList44, ImplicitList45, NULL, 0 }, // Inst #1975 = REP_STOSB
- { 1976, 0, 0, 0, "REP_STOSD", 0|(1<<TID::MayStore), 0|1|(2<<8)|(171<<24), ImplicitList46, ImplicitList45, NULL, 0 }, // Inst #1976 = REP_STOSD
- { 1977, 0, 0, 0, "REP_STOSQ", 0|(1<<TID::MayStore), 0|1|(2<<8)|(1<<12)|(171<<24), ImplicitList47, ImplicitList48, NULL, 0 }, // Inst #1977 = REP_STOSQ
- { 1978, 0, 0, 0, "REP_STOSW", 0|(1<<TID::MayStore), 0|1|(1<<6)|(2<<8)|(171<<24), ImplicitList49, ImplicitList45, NULL, 0 }, // Inst #1978 = REP_STOSW
- { 1979, 0, 0, 0, "RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::Variadic), 0|1|(7<<16)|(195<<24), NULL, NULL, NULL, 0 }, // Inst #1979 = RET
- { 1980, 1, 0, 0, "RETI", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::Variadic), 0|1|(2<<13)|(7<<16)|(194<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1980 = RETI
- { 1981, 5, 0, 0, "ROL16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1981 = ROL16m1
- { 1982, 5, 0, 0, "ROL16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1982 = ROL16mCL
- { 1983, 6, 0, 0, "ROL16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1983 = ROL16mi
- { 1984, 2, 1, 0, "ROL16r1", 0, 0|16|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1984 = ROL16r1
- { 1985, 2, 1, 0, "ROL16rCL", 0, 0|16|(1<<6)|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1985 = ROL16rCL
- { 1986, 3, 1, 0, "ROL16ri", 0, 0|16|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1986 = ROL16ri
- { 1987, 5, 0, 0, "ROL32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1987 = ROL32m1
- { 1988, 5, 0, 0, "ROL32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1988 = ROL32mCL
- { 1989, 6, 0, 0, "ROL32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1989 = ROL32mi
- { 1990, 2, 1, 0, "ROL32r1", 0, 0|16|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1990 = ROL32r1
- { 1991, 2, 1, 0, "ROL32rCL", 0, 0|16|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1991 = ROL32rCL
- { 1992, 3, 1, 0, "ROL32ri", 0, 0|16|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1992 = ROL32ri
- { 1993, 5, 0, 0, "ROL64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1993 = ROL64m1
- { 1994, 5, 0, 0, "ROL64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<12)|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1994 = ROL64mCL
- { 1995, 6, 0, 0, "ROL64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1995 = ROL64mi
- { 1996, 2, 1, 0, "ROL64r1", 0, 0|16|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #1996 = ROL64r1
- { 1997, 2, 1, 0, "ROL64rCL", 0, 0|16|(1<<12)|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #1997 = ROL64rCL
- { 1998, 3, 1, 0, "ROL64ri", 0, 0|16|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1998 = ROL64ri
- { 1999, 5, 0, 0, "ROL8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1999 = ROL8m1
- { 2000, 5, 0, 0, "ROL8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(210<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2000 = ROL8mCL
- { 2001, 6, 0, 0, "ROL8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2001 = ROL8mi
- { 2002, 2, 1, 0, "ROL8r1", 0, 0|16|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2002 = ROL8r1
- { 2003, 2, 1, 0, "ROL8rCL", 0, 0|16|(210<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2003 = ROL8rCL
- { 2004, 3, 1, 0, "ROL8ri", 0, 0|16|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2004 = ROL8ri
- { 2005, 5, 0, 0, "ROR16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2005 = ROR16m1
- { 2006, 5, 0, 0, "ROR16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2006 = ROR16mCL
- { 2007, 6, 0, 0, "ROR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2007 = ROR16mi
- { 2008, 2, 1, 0, "ROR16r1", 0, 0|17|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2008 = ROR16r1
- { 2009, 2, 1, 0, "ROR16rCL", 0, 0|17|(1<<6)|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2009 = ROR16rCL
- { 2010, 3, 1, 0, "ROR16ri", 0, 0|17|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2010 = ROR16ri
- { 2011, 5, 0, 0, "ROR32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2011 = ROR32m1
- { 2012, 5, 0, 0, "ROR32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2012 = ROR32mCL
- { 2013, 6, 0, 0, "ROR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2013 = ROR32mi
- { 2014, 2, 1, 0, "ROR32r1", 0, 0|17|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2014 = ROR32r1
- { 2015, 2, 1, 0, "ROR32rCL", 0, 0|17|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2015 = ROR32rCL
- { 2016, 3, 1, 0, "ROR32ri", 0, 0|17|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2016 = ROR32ri
- { 2017, 5, 0, 0, "ROR64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2017 = ROR64m1
- { 2018, 5, 0, 0, "ROR64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2018 = ROR64mCL
- { 2019, 6, 0, 0, "ROR64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2019 = ROR64mi
- { 2020, 2, 1, 0, "ROR64r1", 0, 0|17|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2020 = ROR64r1
- { 2021, 2, 1, 0, "ROR64rCL", 0, 0|17|(1<<12)|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2021 = ROR64rCL
- { 2022, 3, 1, 0, "ROR64ri", 0, 0|17|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2022 = ROR64ri
- { 2023, 5, 0, 0, "ROR8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2023 = ROR8m1
- { 2024, 5, 0, 0, "ROR8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(210<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2024 = ROR8mCL
- { 2025, 6, 0, 0, "ROR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2025 = ROR8mi
- { 2026, 2, 1, 0, "ROR8r1", 0, 0|17|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2026 = ROR8r1
- { 2027, 2, 1, 0, "ROR8rCL", 0, 0|17|(210<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2027 = ROR8rCL
- { 2028, 3, 1, 0, "ROR8ri", 0, 0|17|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2028 = ROR8ri
- { 2029, 7, 1, 0, "ROUNDPDm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo187 }, // Inst #2029 = ROUNDPDm_Int
- { 2030, 3, 1, 0, "ROUNDPDr_Int", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo188 }, // Inst #2030 = ROUNDPDr_Int
- { 2031, 7, 1, 0, "ROUNDPSm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo187 }, // Inst #2031 = ROUNDPSm_Int
- { 2032, 3, 1, 0, "ROUNDPSr_Int", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo188 }, // Inst #2032 = ROUNDPSr_Int
- { 2033, 8, 1, 0, "ROUNDSDm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #2033 = ROUNDSDm_Int
- { 2034, 4, 1, 0, "ROUNDSDr_Int", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #2034 = ROUNDSDr_Int
- { 2035, 8, 1, 0, "ROUNDSSm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #2035 = ROUNDSSm_Int
- { 2036, 4, 1, 0, "ROUNDSSr_Int", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #2036 = ROUNDSSr_Int
- { 2037, 0, 0, 0, "RSM", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(170<<24), NULL, NULL, NULL, 0 }, // Inst #2037 = RSM
- { 2038, 6, 1, 0, "RSQRTPSm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(82<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2038 = RSQRTPSm
- { 2039, 6, 1, 0, "RSQRTPSm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(82<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2039 = RSQRTPSm_Int
- { 2040, 2, 1, 0, "RSQRTPSr", 0, 0|5|(1<<8)|(82<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2040 = RSQRTPSr
- { 2041, 2, 1, 0, "RSQRTPSr_Int", 0, 0|5|(1<<8)|(82<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2041 = RSQRTPSr_Int
- { 2042, 6, 1, 0, "RSQRTSSm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(82<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #2042 = RSQRTSSm
- { 2043, 6, 1, 0, "RSQRTSSm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(82<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2043 = RSQRTSSm_Int
- { 2044, 2, 1, 0, "RSQRTSSr", 0, 0|5|(12<<8)|(82<<24), NULL, NULL, NULL, OperandInfo106 }, // Inst #2044 = RSQRTSSr
- { 2045, 2, 1, 0, "RSQRTSSr_Int", 0, 0|5|(12<<8)|(82<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2045 = RSQRTSSr_Int
- { 2046, 0, 0, 0, "SAHF", 0, 0|1|(158<<24), ImplicitList27, ImplicitList1, Barriers1, 0 }, // Inst #2046 = SAHF
- { 2047, 5, 0, 0, "SAR16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2047 = SAR16m1
- { 2048, 5, 0, 0, "SAR16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<6)|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2048 = SAR16mCL
- { 2049, 6, 0, 0, "SAR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2049 = SAR16mi
- { 2050, 2, 1, 0, "SAR16r1", 0, 0|23|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2050 = SAR16r1
- { 2051, 2, 1, 0, "SAR16rCL", 0, 0|23|(1<<6)|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2051 = SAR16rCL
- { 2052, 3, 1, 0, "SAR16ri", 0, 0|23|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2052 = SAR16ri
- { 2053, 5, 0, 0, "SAR32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2053 = SAR32m1
- { 2054, 5, 0, 0, "SAR32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2054 = SAR32mCL
- { 2055, 6, 0, 0, "SAR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2055 = SAR32mi
- { 2056, 2, 1, 0, "SAR32r1", 0, 0|23|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2056 = SAR32r1
- { 2057, 2, 1, 0, "SAR32rCL", 0, 0|23|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2057 = SAR32rCL
- { 2058, 3, 1, 0, "SAR32ri", 0, 0|23|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2058 = SAR32ri
- { 2059, 5, 0, 0, "SAR64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2059 = SAR64m1
- { 2060, 5, 0, 0, "SAR64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<12)|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2060 = SAR64mCL
- { 2061, 6, 0, 0, "SAR64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2061 = SAR64mi
- { 2062, 2, 1, 0, "SAR64r1", 0, 0|23|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2062 = SAR64r1
- { 2063, 2, 1, 0, "SAR64rCL", 0, 0|23|(1<<12)|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2063 = SAR64rCL
- { 2064, 3, 1, 0, "SAR64ri", 0, 0|23|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2064 = SAR64ri
- { 2065, 5, 0, 0, "SAR8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2065 = SAR8m1
- { 2066, 5, 0, 0, "SAR8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(210<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2066 = SAR8mCL
- { 2067, 6, 0, 0, "SAR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2067 = SAR8mi
- { 2068, 2, 1, 0, "SAR8r1", 0, 0|23|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2068 = SAR8r1
- { 2069, 2, 1, 0, "SAR8rCL", 0, 0|23|(210<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2069 = SAR8rCL
- { 2070, 3, 1, 0, "SAR8ri", 0, 0|23|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2070 = SAR8ri
- { 2071, 1, 0, 0, "SBB16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(2<<13)|(29<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2071 = SBB16i16
- { 2072, 6, 0, 0, "SBB16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<6)|(2<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2072 = SBB16mi
- { 2073, 6, 0, 0, "SBB16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<6)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2073 = SBB16mi8
- { 2074, 6, 0, 0, "SBB16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #2074 = SBB16mr
- { 2075, 3, 1, 0, "SBB16ri", 0, 0|19|(1<<6)|(2<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2075 = SBB16ri
- { 2076, 3, 1, 0, "SBB16ri8", 0, 0|19|(1<<6)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2076 = SBB16ri8
- { 2077, 7, 1, 0, "SBB16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #2077 = SBB16rm
- { 2078, 3, 1, 0, "SBB16rr", 0, 0|3|(1<<6)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2078 = SBB16rr
- { 2079, 3, 1, 0, "SBB16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2079 = SBB16rr_REV
- { 2080, 1, 0, 0, "SBB32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(29<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2080 = SBB32i32
- { 2081, 6, 0, 0, "SBB32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(3<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2081 = SBB32mi
- { 2082, 6, 0, 0, "SBB32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2082 = SBB32mi8
- { 2083, 6, 0, 0, "SBB32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #2083 = SBB32mr
- { 2084, 3, 1, 0, "SBB32ri", 0, 0|19|(3<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2084 = SBB32ri
- { 2085, 3, 1, 0, "SBB32ri8", 0, 0|19|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2085 = SBB32ri8
- { 2086, 7, 1, 0, "SBB32rm", 0|(1<<TID::MayLoad), 0|6|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #2086 = SBB32rm
- { 2087, 3, 1, 0, "SBB32rr", 0, 0|3|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2087 = SBB32rr
- { 2088, 3, 1, 0, "SBB32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2088 = SBB32rr_REV
- { 2089, 1, 0, 0, "SBB64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(29<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2089 = SBB64i32
- { 2090, 6, 0, 0, "SBB64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<12)|(3<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2090 = SBB64mi32
- { 2091, 6, 0, 0, "SBB64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<12)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2091 = SBB64mi8
- { 2092, 6, 0, 0, "SBB64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #2092 = SBB64mr
- { 2093, 3, 1, 0, "SBB64ri32", 0, 0|19|(1<<12)|(3<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2093 = SBB64ri32
- { 2094, 3, 1, 0, "SBB64ri8", 0, 0|19|(1<<12)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2094 = SBB64ri8
- { 2095, 7, 1, 0, "SBB64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #2095 = SBB64rm
- { 2096, 3, 1, 0, "SBB64rr", 0, 0|3|(1<<12)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2096 = SBB64rr
- { 2097, 3, 1, 0, "SBB64rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2097 = SBB64rr_REV
- { 2098, 1, 0, 0, "SBB8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(28<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2098 = SBB8i8
- { 2099, 6, 0, 0, "SBB8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(3<<13)|(128<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2099 = SBB8mi
- { 2100, 6, 0, 0, "SBB8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(24<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #2100 = SBB8mr
- { 2101, 3, 1, 0, "SBB8ri", 0, 0|19|(1<<13)|(128<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2101 = SBB8ri
- { 2102, 7, 1, 0, "SBB8rm", 0|(1<<TID::MayLoad), 0|6|(26<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #2102 = SBB8rm
- { 2103, 3, 1, 0, "SBB8rr", 0, 0|3|(24<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #2103 = SBB8rr
- { 2104, 3, 1, 0, "SBB8rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(26<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #2104 = SBB8rr_REV
- { 2105, 0, 0, 0, "SCAS16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(175<<24), NULL, NULL, NULL, 0 }, // Inst #2105 = SCAS16
- { 2106, 0, 0, 0, "SCAS32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(175<<24), NULL, NULL, NULL, 0 }, // Inst #2106 = SCAS32
- { 2107, 0, 0, 0, "SCAS64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(175<<24), NULL, NULL, NULL, 0 }, // Inst #2107 = SCAS64
- { 2108, 0, 0, 0, "SCAS8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(174<<24), NULL, NULL, NULL, 0 }, // Inst #2108 = SCAS8
- { 2109, 5, 0, 0, "SETAEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(147<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2109 = SETAEm
- { 2110, 1, 1, 0, "SETAEr", 0, 0|16|(1<<8)|(147<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2110 = SETAEr
- { 2111, 5, 0, 0, "SETAm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(151<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2111 = SETAm
- { 2112, 1, 1, 0, "SETAr", 0, 0|16|(1<<8)|(151<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2112 = SETAr
- { 2113, 5, 0, 0, "SETBEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(150<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2113 = SETBEm
- { 2114, 1, 1, 0, "SETBEr", 0, 0|16|(1<<8)|(150<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2114 = SETBEr
- { 2115, 1, 1, 0, "SETB_C16r", 0, 0|32|(1<<6)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo93 }, // Inst #2115 = SETB_C16r
- { 2116, 1, 1, 0, "SETB_C32r", 0, 0|32|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo57 }, // Inst #2116 = SETB_C32r
- { 2117, 1, 1, 0, "SETB_C64r", 0, 0|32|(1<<12)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo58 }, // Inst #2117 = SETB_C64r
- { 2118, 1, 1, 0, "SETB_C8r", 0, 0|32|(24<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo94 }, // Inst #2118 = SETB_C8r
- { 2119, 5, 0, 0, "SETBm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(146<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2119 = SETBm
- { 2120, 1, 1, 0, "SETBr", 0, 0|16|(1<<8)|(146<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2120 = SETBr
- { 2121, 5, 0, 0, "SETEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(148<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2121 = SETEm
- { 2122, 1, 1, 0, "SETEr", 0, 0|16|(1<<8)|(148<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2122 = SETEr
- { 2123, 5, 0, 0, "SETGEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(157<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2123 = SETGEm
- { 2124, 1, 1, 0, "SETGEr", 0, 0|16|(1<<8)|(157<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2124 = SETGEr
- { 2125, 5, 0, 0, "SETGm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(159<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2125 = SETGm
- { 2126, 1, 1, 0, "SETGr", 0, 0|16|(1<<8)|(159<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2126 = SETGr
- { 2127, 5, 0, 0, "SETLEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(158<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2127 = SETLEm
- { 2128, 1, 1, 0, "SETLEr", 0, 0|16|(1<<8)|(158<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2128 = SETLEr
- { 2129, 5, 0, 0, "SETLm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(156<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2129 = SETLm
- { 2130, 1, 1, 0, "SETLr", 0, 0|16|(1<<8)|(156<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2130 = SETLr
- { 2131, 5, 0, 0, "SETNEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(149<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2131 = SETNEm
- { 2132, 1, 1, 0, "SETNEr", 0, 0|16|(1<<8)|(149<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2132 = SETNEr
- { 2133, 5, 0, 0, "SETNOm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(145<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2133 = SETNOm
- { 2134, 1, 1, 0, "SETNOr", 0, 0|16|(1<<8)|(145<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2134 = SETNOr
- { 2135, 5, 0, 0, "SETNPm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(155<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2135 = SETNPm
- { 2136, 1, 1, 0, "SETNPr", 0, 0|16|(1<<8)|(155<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2136 = SETNPr
- { 2137, 5, 0, 0, "SETNSm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(153<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2137 = SETNSm
- { 2138, 1, 1, 0, "SETNSr", 0, 0|16|(1<<8)|(153<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2138 = SETNSr
- { 2139, 5, 0, 0, "SETOm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(144<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2139 = SETOm
- { 2140, 1, 1, 0, "SETOr", 0, 0|16|(1<<8)|(144<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2140 = SETOr
- { 2141, 5, 0, 0, "SETPm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(154<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2141 = SETPm
- { 2142, 1, 1, 0, "SETPr", 0, 0|16|(1<<8)|(154<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2142 = SETPr
- { 2143, 5, 0, 0, "SETSm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(152<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2143 = SETSm
- { 2144, 1, 1, 0, "SETSr", 0, 0|16|(1<<8)|(152<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2144 = SETSr
- { 2145, 0, 0, 0, "SFENCE", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|23|(1<<8)|(174<<24), NULL, NULL, NULL, 0 }, // Inst #2145 = SFENCE
- { 2146, 5, 1, 0, "SGDTm", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2146 = SGDTm
- { 2147, 5, 0, 0, "SHL16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2147 = SHL16m1
- { 2148, 5, 0, 0, "SHL16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<6)|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2148 = SHL16mCL
- { 2149, 6, 0, 0, "SHL16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2149 = SHL16mi
- { 2150, 2, 1, 0, "SHL16r1", 0|(1<<TID::ConvertibleTo3Addr)|(1<<TID::UnmodeledSideEffects), 0|20|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2150 = SHL16r1
- { 2151, 2, 1, 0, "SHL16rCL", 0, 0|20|(1<<6)|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2151 = SHL16rCL
- { 2152, 3, 1, 0, "SHL16ri", 0|(1<<TID::ConvertibleTo3Addr), 0|20|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2152 = SHL16ri
- { 2153, 5, 0, 0, "SHL32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2153 = SHL32m1
- { 2154, 5, 0, 0, "SHL32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2154 = SHL32mCL
- { 2155, 6, 0, 0, "SHL32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2155 = SHL32mi
- { 2156, 2, 1, 0, "SHL32r1", 0|(1<<TID::ConvertibleTo3Addr)|(1<<TID::UnmodeledSideEffects), 0|20|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2156 = SHL32r1
- { 2157, 2, 1, 0, "SHL32rCL", 0, 0|20|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2157 = SHL32rCL
- { 2158, 3, 1, 0, "SHL32ri", 0|(1<<TID::ConvertibleTo3Addr), 0|20|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2158 = SHL32ri
- { 2159, 5, 0, 0, "SHL64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2159 = SHL64m1
- { 2160, 5, 0, 0, "SHL64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<12)|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2160 = SHL64mCL
- { 2161, 6, 0, 0, "SHL64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2161 = SHL64mi
- { 2162, 2, 1, 0, "SHL64r1", 0|(1<<TID::UnmodeledSideEffects), 0|20|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2162 = SHL64r1
- { 2163, 2, 1, 0, "SHL64rCL", 0, 0|20|(1<<12)|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2163 = SHL64rCL
- { 2164, 3, 1, 0, "SHL64ri", 0|(1<<TID::ConvertibleTo3Addr), 0|20|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2164 = SHL64ri
- { 2165, 5, 0, 0, "SHL8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2165 = SHL8m1
- { 2166, 5, 0, 0, "SHL8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(210<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2166 = SHL8mCL
- { 2167, 6, 0, 0, "SHL8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2167 = SHL8mi
- { 2168, 2, 1, 0, "SHL8r1", 0|(1<<TID::ConvertibleTo3Addr)|(1<<TID::UnmodeledSideEffects), 0|20|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2168 = SHL8r1
- { 2169, 2, 1, 0, "SHL8rCL", 0, 0|20|(210<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2169 = SHL8rCL
- { 2170, 3, 1, 0, "SHL8ri", 0, 0|20|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2170 = SHL8ri
- { 2171, 6, 0, 0, "SHLD16mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(165<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #2171 = SHLD16mrCL
- { 2172, 7, 0, 0, "SHLD16mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo196 }, // Inst #2172 = SHLD16mri8
- { 2173, 3, 1, 0, "SHLD16rrCL", 0, 0|3|(1<<6)|(1<<8)|(165<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2173 = SHLD16rrCL
- { 2174, 4, 1, 0, "SHLD16rri8", 0|(1<<TID::Commutable), 0|3|(1<<6)|(1<<8)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo197 }, // Inst #2174 = SHLD16rri8
- { 2175, 6, 0, 0, "SHLD32mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(165<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #2175 = SHLD32mrCL
- { 2176, 7, 0, 0, "SHLD32mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo198 }, // Inst #2176 = SHLD32mri8
- { 2177, 3, 1, 0, "SHLD32rrCL", 0, 0|3|(1<<8)|(165<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2177 = SHLD32rrCL
- { 2178, 4, 1, 0, "SHLD32rri8", 0|(1<<TID::Commutable), 0|3|(1<<8)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo199 }, // Inst #2178 = SHLD32rri8
- { 2179, 6, 0, 0, "SHLD64mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<12)|(165<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #2179 = SHLD64mrCL
- { 2180, 7, 0, 0, "SHLD64mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<12)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo200 }, // Inst #2180 = SHLD64mri8
- { 2181, 3, 1, 0, "SHLD64rrCL", 0, 0|3|(1<<8)|(1<<12)|(165<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2181 = SHLD64rrCL
- { 2182, 4, 1, 0, "SHLD64rri8", 0|(1<<TID::Commutable), 0|3|(1<<8)|(1<<12)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo201 }, // Inst #2182 = SHLD64rri8
- { 2183, 5, 0, 0, "SHR16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2183 = SHR16m1
- { 2184, 5, 0, 0, "SHR16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<6)|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2184 = SHR16mCL
- { 2185, 6, 0, 0, "SHR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2185 = SHR16mi
- { 2186, 2, 1, 0, "SHR16r1", 0, 0|21|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2186 = SHR16r1
- { 2187, 2, 1, 0, "SHR16rCL", 0, 0|21|(1<<6)|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2187 = SHR16rCL
- { 2188, 3, 1, 0, "SHR16ri", 0, 0|21|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2188 = SHR16ri
- { 2189, 5, 0, 0, "SHR32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2189 = SHR32m1
- { 2190, 5, 0, 0, "SHR32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2190 = SHR32mCL
- { 2191, 6, 0, 0, "SHR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2191 = SHR32mi
- { 2192, 2, 1, 0, "SHR32r1", 0, 0|21|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2192 = SHR32r1
- { 2193, 2, 1, 0, "SHR32rCL", 0, 0|21|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2193 = SHR32rCL
- { 2194, 3, 1, 0, "SHR32ri", 0, 0|21|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2194 = SHR32ri
- { 2195, 5, 0, 0, "SHR64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2195 = SHR64m1
- { 2196, 5, 0, 0, "SHR64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<12)|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2196 = SHR64mCL
- { 2197, 6, 0, 0, "SHR64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2197 = SHR64mi
- { 2198, 2, 1, 0, "SHR64r1", 0, 0|21|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2198 = SHR64r1
- { 2199, 2, 1, 0, "SHR64rCL", 0, 0|21|(1<<12)|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2199 = SHR64rCL
- { 2200, 3, 1, 0, "SHR64ri", 0, 0|21|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2200 = SHR64ri
- { 2201, 5, 0, 0, "SHR8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2201 = SHR8m1
- { 2202, 5, 0, 0, "SHR8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(210<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2202 = SHR8mCL
- { 2203, 6, 0, 0, "SHR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2203 = SHR8mi
- { 2204, 2, 1, 0, "SHR8r1", 0, 0|21|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2204 = SHR8r1
- { 2205, 2, 1, 0, "SHR8rCL", 0, 0|21|(210<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2205 = SHR8rCL
- { 2206, 3, 1, 0, "SHR8ri", 0, 0|21|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2206 = SHR8ri
- { 2207, 6, 0, 0, "SHRD16mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(173<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #2207 = SHRD16mrCL
- { 2208, 7, 0, 0, "SHRD16mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo196 }, // Inst #2208 = SHRD16mri8
- { 2209, 3, 1, 0, "SHRD16rrCL", 0, 0|3|(1<<6)|(1<<8)|(173<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2209 = SHRD16rrCL
- { 2210, 4, 1, 0, "SHRD16rri8", 0|(1<<TID::Commutable), 0|3|(1<<6)|(1<<8)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo197 }, // Inst #2210 = SHRD16rri8
- { 2211, 6, 0, 0, "SHRD32mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(173<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #2211 = SHRD32mrCL
- { 2212, 7, 0, 0, "SHRD32mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo198 }, // Inst #2212 = SHRD32mri8
- { 2213, 3, 1, 0, "SHRD32rrCL", 0, 0|3|(1<<8)|(173<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2213 = SHRD32rrCL
- { 2214, 4, 1, 0, "SHRD32rri8", 0|(1<<TID::Commutable), 0|3|(1<<8)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo199 }, // Inst #2214 = SHRD32rri8
- { 2215, 6, 0, 0, "SHRD64mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<12)|(173<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #2215 = SHRD64mrCL
- { 2216, 7, 0, 0, "SHRD64mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<12)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo200 }, // Inst #2216 = SHRD64mri8
- { 2217, 3, 1, 0, "SHRD64rrCL", 0, 0|3|(1<<8)|(1<<12)|(173<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2217 = SHRD64rrCL
- { 2218, 4, 1, 0, "SHRD64rri8", 0|(1<<TID::Commutable), 0|3|(1<<8)|(1<<12)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo201 }, // Inst #2218 = SHRD64rri8
- { 2219, 8, 1, 0, "SHUFPDrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(1<<13)|(198<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #2219 = SHUFPDrmi
- { 2220, 4, 1, 0, "SHUFPDrri", 0, 0|5|(1<<6)|(1<<8)|(1<<13)|(198<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #2220 = SHUFPDrri
- { 2221, 8, 1, 0, "SHUFPSrmi", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<13)|(198<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #2221 = SHUFPSrmi
- { 2222, 4, 1, 0, "SHUFPSrri", 0|(1<<TID::ConvertibleTo3Addr), 0|5|(1<<8)|(1<<13)|(198<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #2222 = SHUFPSrri
- { 2223, 5, 1, 0, "SIDTm", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2223 = SIDTm
- { 2224, 0, 0, 0, "SIN_F", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(254<<24), NULL, NULL, NULL, 0 }, // Inst #2224 = SIN_F
- { 2225, 2, 1, 0, "SIN_Fp32", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo2 }, // Inst #2225 = SIN_Fp32
- { 2226, 2, 1, 0, "SIN_Fp64", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo3 }, // Inst #2226 = SIN_Fp64
- { 2227, 2, 1, 0, "SIN_Fp80", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo4 }, // Inst #2227 = SIN_Fp80
- { 2228, 5, 1, 0, "SLDT16m", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<8), NULL, NULL, NULL, OperandInfo30 }, // Inst #2228 = SLDT16m
- { 2229, 1, 1, 0, "SLDT16r", 0|(1<<TID::UnmodeledSideEffects), 0|16|(1<<8), NULL, NULL, NULL, OperandInfo93 }, // Inst #2229 = SLDT16r
- { 2230, 5, 1, 0, "SLDT64m", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<8)|(1<<12), NULL, NULL, NULL, OperandInfo30 }, // Inst #2230 = SLDT64m
- { 2231, 1, 1, 0, "SLDT64r", 0|(1<<TID::UnmodeledSideEffects), 0|16|(1<<8)|(1<<12), NULL, NULL, NULL, OperandInfo58 }, // Inst #2231 = SLDT64r
- { 2232, 5, 1, 0, "SMSW16m", 0|(1<<TID::UnmodeledSideEffects), 0|28|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2232 = SMSW16m
- { 2233, 1, 1, 0, "SMSW16r", 0|(1<<TID::UnmodeledSideEffects), 0|20|(1<<6)|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo93 }, // Inst #2233 = SMSW16r
- { 2234, 1, 1, 0, "SMSW32r", 0|(1<<TID::UnmodeledSideEffects), 0|20|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo57 }, // Inst #2234 = SMSW32r
- { 2235, 1, 1, 0, "SMSW64r", 0|(1<<TID::UnmodeledSideEffects), 0|20|(1<<8)|(1<<12)|(1<<24), NULL, NULL, NULL, OperandInfo58 }, // Inst #2235 = SMSW64r
- { 2236, 6, 1, 0, "SQRTPDm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2236 = SQRTPDm
- { 2237, 6, 1, 0, "SQRTPDm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2237 = SQRTPDm_Int
- { 2238, 2, 1, 0, "SQRTPDr", 0, 0|5|(1<<6)|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2238 = SQRTPDr
- { 2239, 2, 1, 0, "SQRTPDr_Int", 0, 0|5|(1<<6)|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2239 = SQRTPDr_Int
- { 2240, 6, 1, 0, "SQRTPSm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2240 = SQRTPSm
- { 2241, 6, 1, 0, "SQRTPSm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2241 = SQRTPSm_Int
- { 2242, 2, 1, 0, "SQRTPSr", 0, 0|5|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2242 = SQRTPSr
- { 2243, 2, 1, 0, "SQRTPSr_Int", 0, 0|5|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2243 = SQRTPSr_Int
- { 2244, 6, 1, 0, "SQRTSDm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(81<<24), NULL, NULL, NULL, OperandInfo82 }, // Inst #2244 = SQRTSDm
- { 2245, 6, 1, 0, "SQRTSDm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2245 = SQRTSDm_Int
- { 2246, 2, 1, 0, "SQRTSDr", 0, 0|5|(11<<8)|(81<<24), NULL, NULL, NULL, OperandInfo105 }, // Inst #2246 = SQRTSDr
- { 2247, 2, 1, 0, "SQRTSDr_Int", 0, 0|5|(11<<8)|(81<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2247 = SQRTSDr_Int
- { 2248, 6, 1, 0, "SQRTSSm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(81<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #2248 = SQRTSSm
- { 2249, 6, 1, 0, "SQRTSSm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2249 = SQRTSSm_Int
- { 2250, 2, 1, 0, "SQRTSSr", 0, 0|5|(12<<8)|(81<<24), NULL, NULL, NULL, OperandInfo106 }, // Inst #2250 = SQRTSSr
- { 2251, 2, 1, 0, "SQRTSSr_Int", 0, 0|5|(12<<8)|(81<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2251 = SQRTSSr_Int
- { 2252, 0, 0, 0, "SQRT_F", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(250<<24), NULL, NULL, NULL, 0 }, // Inst #2252 = SQRT_F
- { 2253, 2, 1, 0, "SQRT_Fp32", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo2 }, // Inst #2253 = SQRT_Fp32
- { 2254, 2, 1, 0, "SQRT_Fp64", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo3 }, // Inst #2254 = SQRT_Fp64
- { 2255, 2, 1, 0, "SQRT_Fp80", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo4 }, // Inst #2255 = SQRT_Fp80
- { 2256, 0, 0, 0, "STC", 0|(1<<TID::UnmodeledSideEffects), 0|1|(249<<24), NULL, NULL, NULL, 0 }, // Inst #2256 = STC
- { 2257, 0, 0, 0, "STD", 0|(1<<TID::UnmodeledSideEffects), 0|1|(253<<24), NULL, NULL, NULL, 0 }, // Inst #2257 = STD
- { 2258, 0, 0, 0, "STI", 0|(1<<TID::UnmodeledSideEffects), 0|1|(251<<24), NULL, NULL, NULL, 0 }, // Inst #2258 = STI
- { 2259, 5, 0, 0, "STMXCSR", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|27|(1<<8)|(174<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2259 = STMXCSR
- { 2260, 5, 1, 0, "STRm", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<8), NULL, NULL, NULL, OperandInfo30 }, // Inst #2260 = STRm
- { 2261, 1, 1, 0, "STRr", 0|(1<<TID::UnmodeledSideEffects), 0|17|(1<<8), NULL, NULL, NULL, OperandInfo93 }, // Inst #2261 = STRr
- { 2262, 5, 0, 0, "ST_F32m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|26|(217<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2262 = ST_F32m
- { 2263, 5, 0, 0, "ST_F64m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|26|(221<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2263 = ST_F64m
- { 2264, 5, 0, 0, "ST_FP32m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|27|(217<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2264 = ST_FP32m
- { 2265, 5, 0, 0, "ST_FP64m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|27|(221<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2265 = ST_FP64m
- { 2266, 5, 0, 0, "ST_FP80m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|31|(219<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2266 = ST_FP80m
- { 2267, 1, 0, 0, "ST_FPrr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(8<<8)|(216<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2267 = ST_FPrr
- { 2268, 6, 0, 0, "ST_Fp32m", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #2268 = ST_Fp32m
- { 2269, 6, 0, 0, "ST_Fp64m", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #2269 = ST_Fp64m
- { 2270, 6, 0, 0, "ST_Fp64m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #2270 = ST_Fp64m32
- { 2271, 6, 0, 0, "ST_Fp80m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #2271 = ST_Fp80m32
- { 2272, 6, 0, 0, "ST_Fp80m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #2272 = ST_Fp80m64
- { 2273, 6, 0, 0, "ST_FpP32m", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #2273 = ST_FpP32m
- { 2274, 6, 0, 0, "ST_FpP64m", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #2274 = ST_FpP64m
- { 2275, 6, 0, 0, "ST_FpP64m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #2275 = ST_FpP64m32
- { 2276, 6, 0, 0, "ST_FpP80m", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #2276 = ST_FpP80m
- { 2277, 6, 0, 0, "ST_FpP80m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #2277 = ST_FpP80m32
- { 2278, 6, 0, 0, "ST_FpP80m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #2278 = ST_FpP80m64
- { 2279, 1, 0, 0, "ST_Frr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(8<<8)|(208<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2279 = ST_Frr
- { 2280, 1, 0, 0, "SUB16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(2<<13)|(45<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2280 = SUB16i16
- { 2281, 6, 0, 0, "SUB16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2281 = SUB16mi
- { 2282, 6, 0, 0, "SUB16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2282 = SUB16mi8
- { 2283, 6, 0, 0, "SUB16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #2283 = SUB16mr
- { 2284, 3, 1, 0, "SUB16ri", 0, 0|21|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2284 = SUB16ri
- { 2285, 3, 1, 0, "SUB16ri8", 0, 0|21|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2285 = SUB16ri8
- { 2286, 7, 1, 0, "SUB16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #2286 = SUB16rm
- { 2287, 3, 1, 0, "SUB16rr", 0, 0|3|(1<<6)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2287 = SUB16rr
- { 2288, 3, 1, 0, "SUB16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2288 = SUB16rr_REV
- { 2289, 1, 0, 0, "SUB32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(45<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2289 = SUB32i32
- { 2290, 6, 0, 0, "SUB32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2290 = SUB32mi
- { 2291, 6, 0, 0, "SUB32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2291 = SUB32mi8
- { 2292, 6, 0, 0, "SUB32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #2292 = SUB32mr
- { 2293, 3, 1, 0, "SUB32ri", 0, 0|21|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2293 = SUB32ri
- { 2294, 3, 1, 0, "SUB32ri8", 0, 0|21|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2294 = SUB32ri8
- { 2295, 7, 1, 0, "SUB32rm", 0|(1<<TID::MayLoad), 0|6|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #2295 = SUB32rm
- { 2296, 3, 1, 0, "SUB32rr", 0, 0|3|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2296 = SUB32rr
- { 2297, 3, 1, 0, "SUB32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2297 = SUB32rr_REV
- { 2298, 1, 0, 0, "SUB64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(45<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2298 = SUB64i32
- { 2299, 6, 0, 0, "SUB64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2299 = SUB64mi32
- { 2300, 6, 0, 0, "SUB64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2300 = SUB64mi8
- { 2301, 6, 0, 0, "SUB64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #2301 = SUB64mr
- { 2302, 3, 1, 0, "SUB64ri32", 0, 0|21|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2302 = SUB64ri32
- { 2303, 3, 1, 0, "SUB64ri8", 0, 0|21|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2303 = SUB64ri8
- { 2304, 7, 1, 0, "SUB64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #2304 = SUB64rm
- { 2305, 3, 1, 0, "SUB64rr", 0, 0|3|(1<<12)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2305 = SUB64rr
- { 2306, 3, 1, 0, "SUB64rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2306 = SUB64rr_REV
- { 2307, 1, 0, 0, "SUB8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(44<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2307 = SUB8i8
- { 2308, 6, 0, 0, "SUB8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2308 = SUB8mi
- { 2309, 6, 0, 0, "SUB8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(40<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #2309 = SUB8mr
- { 2310, 3, 1, 0, "SUB8ri", 0, 0|21|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2310 = SUB8ri
- { 2311, 7, 1, 0, "SUB8rm", 0|(1<<TID::MayLoad), 0|6|(42<<24), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #2311 = SUB8rm
- { 2312, 3, 1, 0, "SUB8rr", 0, 0|3|(40<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #2312 = SUB8rr
- { 2313, 3, 1, 0, "SUB8rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(42<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #2313 = SUB8rr_REV
- { 2314, 7, 1, 0, "SUBPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(92<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2314 = SUBPDrm
- { 2315, 3, 1, 0, "SUBPDrr", 0, 0|5|(1<<6)|(1<<8)|(92<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2315 = SUBPDrr
- { 2316, 7, 1, 0, "SUBPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(92<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2316 = SUBPSrm
- { 2317, 3, 1, 0, "SUBPSrr", 0, 0|5|(1<<8)|(92<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2317 = SUBPSrr
- { 2318, 5, 0, 0, "SUBR_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(216<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2318 = SUBR_F32m
- { 2319, 5, 0, 0, "SUBR_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(220<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2319 = SUBR_F64m
- { 2320, 5, 0, 0, "SUBR_FI16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(222<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2320 = SUBR_FI16m
- { 2321, 5, 0, 0, "SUBR_FI32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(218<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2321 = SUBR_FI32m
- { 2322, 1, 0, 0, "SUBR_FPrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(9<<8)|(224<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2322 = SUBR_FPrST0
- { 2323, 1, 0, 0, "SUBR_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(232<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2323 = SUBR_FST0r
- { 2324, 7, 1, 0, "SUBR_Fp32m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #2324 = SUBR_Fp32m
- { 2325, 7, 1, 0, "SUBR_Fp64m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2325 = SUBR_Fp64m
- { 2326, 7, 1, 0, "SUBR_Fp64m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2326 = SUBR_Fp64m32
- { 2327, 7, 1, 0, "SUBR_Fp80m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2327 = SUBR_Fp80m32
- { 2328, 7, 1, 0, "SUBR_Fp80m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2328 = SUBR_Fp80m64
- { 2329, 7, 1, 0, "SUBR_FpI16m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #2329 = SUBR_FpI16m32
- { 2330, 7, 1, 0, "SUBR_FpI16m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2330 = SUBR_FpI16m64
- { 2331, 7, 1, 0, "SUBR_FpI16m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2331 = SUBR_FpI16m80
- { 2332, 7, 1, 0, "SUBR_FpI32m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #2332 = SUBR_FpI32m32
- { 2333, 7, 1, 0, "SUBR_FpI32m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2333 = SUBR_FpI32m64
- { 2334, 7, 1, 0, "SUBR_FpI32m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2334 = SUBR_FpI32m80
- { 2335, 1, 0, 0, "SUBR_FrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(7<<8)|(224<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2335 = SUBR_FrST0
- { 2336, 7, 1, 0, "SUBSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(92<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #2336 = SUBSDrm
- { 2337, 7, 1, 0, "SUBSDrm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(92<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2337 = SUBSDrm_Int
- { 2338, 3, 1, 0, "SUBSDrr", 0, 0|5|(11<<8)|(92<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #2338 = SUBSDrr
- { 2339, 3, 1, 0, "SUBSDrr_Int", 0, 0|5|(11<<8)|(92<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2339 = SUBSDrr_Int
- { 2340, 7, 1, 0, "SUBSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(92<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #2340 = SUBSSrm
- { 2341, 7, 1, 0, "SUBSSrm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(92<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2341 = SUBSSrm_Int
- { 2342, 3, 1, 0, "SUBSSrr", 0, 0|5|(12<<8)|(92<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #2342 = SUBSSrr
- { 2343, 3, 1, 0, "SUBSSrr_Int", 0, 0|5|(12<<8)|(92<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2343 = SUBSSrr_Int
- { 2344, 5, 0, 0, "SUB_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|28|(216<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2344 = SUB_F32m
- { 2345, 5, 0, 0, "SUB_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|28|(220<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2345 = SUB_F64m
- { 2346, 5, 0, 0, "SUB_FI16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|28|(222<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2346 = SUB_FI16m
- { 2347, 5, 0, 0, "SUB_FI32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|28|(218<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2347 = SUB_FI32m
- { 2348, 1, 0, 0, "SUB_FPrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(9<<8)|(232<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2348 = SUB_FPrST0
- { 2349, 1, 0, 0, "SUB_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(224<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2349 = SUB_FST0r
- { 2350, 3, 1, 0, "SUB_Fp32", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #2350 = SUB_Fp32
- { 2351, 7, 1, 0, "SUB_Fp32m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #2351 = SUB_Fp32m
- { 2352, 3, 1, 0, "SUB_Fp64", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #2352 = SUB_Fp64
- { 2353, 7, 1, 0, "SUB_Fp64m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2353 = SUB_Fp64m
- { 2354, 7, 1, 0, "SUB_Fp64m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2354 = SUB_Fp64m32
- { 2355, 3, 1, 0, "SUB_Fp80", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #2355 = SUB_Fp80
- { 2356, 7, 1, 0, "SUB_Fp80m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2356 = SUB_Fp80m32
- { 2357, 7, 1, 0, "SUB_Fp80m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2357 = SUB_Fp80m64
- { 2358, 7, 1, 0, "SUB_FpI16m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #2358 = SUB_FpI16m32
- { 2359, 7, 1, 0, "SUB_FpI16m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2359 = SUB_FpI16m64
- { 2360, 7, 1, 0, "SUB_FpI16m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2360 = SUB_FpI16m80
- { 2361, 7, 1, 0, "SUB_FpI32m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #2361 = SUB_FpI32m32
- { 2362, 7, 1, 0, "SUB_FpI32m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2362 = SUB_FpI32m64
- { 2363, 7, 1, 0, "SUB_FpI32m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2363 = SUB_FpI32m80
- { 2364, 1, 0, 0, "SUB_FrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(7<<8)|(232<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2364 = SUB_FrST0
- { 2365, 0, 0, 0, "SWPGS", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #2365 = SWPGS
- { 2366, 0, 0, 0, "SYSCALL", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(5<<24), NULL, NULL, NULL, 0 }, // Inst #2366 = SYSCALL
- { 2367, 0, 0, 0, "SYSENTER", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(52<<24), NULL, NULL, NULL, 0 }, // Inst #2367 = SYSENTER
- { 2368, 0, 0, 0, "SYSEXIT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(53<<24), NULL, NULL, NULL, 0 }, // Inst #2368 = SYSEXIT
- { 2369, 0, 0, 0, "SYSEXIT64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(1<<12)|(53<<24), NULL, NULL, NULL, 0 }, // Inst #2369 = SYSEXIT64
- { 2370, 0, 0, 0, "SYSRET", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(7<<24), NULL, NULL, NULL, 0 }, // Inst #2370 = SYSRET
- { 2371, 1, 0, 0, "TAILJMPd", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(233<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #2371 = TAILJMPd
- { 2372, 5, 0, 0, "TAILJMPm", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|28|(255<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2372 = TAILJMPm
- { 2373, 1, 0, 0, "TAILJMPr", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|20|(255<<24), NULL, NULL, NULL, OperandInfo57 }, // Inst #2373 = TAILJMPr
- { 2374, 1, 0, 0, "TAILJMPr64", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|20|(255<<24), NULL, NULL, NULL, OperandInfo58 }, // Inst #2374 = TAILJMPr64
- { 2375, 2, 0, 0, "TCRETURNdi", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo38 }, // Inst #2375 = TCRETURNdi
- { 2376, 2, 0, 0, "TCRETURNdi64", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo38 }, // Inst #2376 = TCRETURNdi64
- { 2377, 2, 0, 0, "TCRETURNri", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo55 }, // Inst #2377 = TCRETURNri
- { 2378, 2, 0, 0, "TCRETURNri64", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo56 }, // Inst #2378 = TCRETURNri64
- { 2379, 1, 0, 0, "TEST16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(2<<13)|(169<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2379 = TEST16i16
- { 2380, 6, 0, 0, "TEST16mi", 0|(1<<TID::MayLoad), 0|24|(1<<6)|(2<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2380 = TEST16mi
- { 2381, 2, 0, 0, "TEST16ri", 0, 0|16|(1<<6)|(2<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo54 }, // Inst #2381 = TEST16ri
- { 2382, 6, 0, 0, "TEST16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo46 }, // Inst #2382 = TEST16rm
- { 2383, 2, 0, 0, "TEST16rr", 0|(1<<TID::Commutable), 0|3|(1<<6)|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo47 }, // Inst #2383 = TEST16rr
- { 2384, 1, 0, 0, "TEST32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(169<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2384 = TEST32i32
- { 2385, 6, 0, 0, "TEST32mi", 0|(1<<TID::MayLoad), 0|24|(3<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2385 = TEST32mi
- { 2386, 2, 0, 0, "TEST32ri", 0, 0|16|(3<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo55 }, // Inst #2386 = TEST32ri
- { 2387, 6, 0, 0, "TEST32rm", 0|(1<<TID::MayLoad), 0|6|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo48 }, // Inst #2387 = TEST32rm
- { 2388, 2, 0, 0, "TEST32rr", 0|(1<<TID::Commutable), 0|3|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo49 }, // Inst #2388 = TEST32rr
- { 2389, 1, 0, 0, "TEST64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(169<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2389 = TEST64i32
- { 2390, 6, 0, 0, "TEST64mi32", 0|(1<<TID::MayLoad), 0|24|(1<<12)|(3<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2390 = TEST64mi32
- { 2391, 2, 0, 0, "TEST64ri32", 0, 0|16|(1<<12)|(3<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo56 }, // Inst #2391 = TEST64ri32
- { 2392, 6, 0, 0, "TEST64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo50 }, // Inst #2392 = TEST64rm
- { 2393, 2, 0, 0, "TEST64rr", 0|(1<<TID::Commutable), 0|3|(1<<12)|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #2393 = TEST64rr
- { 2394, 1, 0, 0, "TEST8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(168<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2394 = TEST8i8
- { 2395, 6, 0, 0, "TEST8mi", 0|(1<<TID::MayLoad), 0|24|(1<<13)|(246<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2395 = TEST8mi
- { 2396, 2, 0, 0, "TEST8ri", 0, 0|16|(1<<13)|(246<<24), NULL, ImplicitList1, Barriers1, OperandInfo68 }, // Inst #2396 = TEST8ri
- { 2397, 6, 0, 0, "TEST8rm", 0|(1<<TID::MayLoad), 0|6|(132<<24), NULL, ImplicitList1, Barriers1, OperandInfo69 }, // Inst #2397 = TEST8rm
- { 2398, 2, 0, 0, "TEST8rr", 0|(1<<TID::Commutable), 0|3|(132<<24), NULL, ImplicitList1, Barriers1, OperandInfo67 }, // Inst #2398 = TEST8rr
- { 2399, 4, 0, 0, "TLS_addr32", 0, 0, ImplicitList2, ImplicitList9, Barriers3, OperandInfo203 }, // Inst #2399 = TLS_addr32
- { 2400, 4, 0, 0, "TLS_addr64", 0, 0, ImplicitList4, ImplicitList10, Barriers4, OperandInfo204 }, // Inst #2400 = TLS_addr64
- { 2401, 0, 0, 0, "TRAP", 0|(1<<TID::Barrier)|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(11<<24), NULL, NULL, NULL, 0 }, // Inst #2401 = TRAP
- { 2402, 0, 0, 0, "TST_F", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(228<<24), NULL, NULL, NULL, 0 }, // Inst #2402 = TST_F
- { 2403, 1, 0, 0, "TST_Fp32", 0, 0|(2<<16), NULL, NULL, NULL, OperandInfo100 }, // Inst #2403 = TST_Fp32
- { 2404, 1, 0, 0, "TST_Fp64", 0, 0|(2<<16), NULL, NULL, NULL, OperandInfo101 }, // Inst #2404 = TST_Fp64
- { 2405, 1, 0, 0, "TST_Fp80", 0, 0|(2<<16), NULL, NULL, NULL, OperandInfo102 }, // Inst #2405 = TST_Fp80
- { 2406, 6, 0, 0, "UCOMISDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo82 }, // Inst #2406 = UCOMISDrm
- { 2407, 2, 0, 0, "UCOMISDrr", 0, 0|5|(1<<6)|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo105 }, // Inst #2407 = UCOMISDrr
- { 2408, 6, 0, 0, "UCOMISSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo80 }, // Inst #2408 = UCOMISSrm
- { 2409, 2, 0, 0, "UCOMISSrr", 0, 0|5|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo106 }, // Inst #2409 = UCOMISSrr
- { 2410, 1, 0, 0, "UCOM_FIPr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(10<<8)|(232<<24), ImplicitList24, ImplicitList1, Barriers1, OperandInfo31 }, // Inst #2410 = UCOM_FIPr
- { 2411, 1, 0, 0, "UCOM_FIr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(6<<8)|(232<<24), ImplicitList24, ImplicitList1, Barriers1, OperandInfo31 }, // Inst #2411 = UCOM_FIr
- { 2412, 0, 0, 0, "UCOM_FPPr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(5<<8)|(233<<24), ImplicitList24, ImplicitList1, Barriers1, 0 }, // Inst #2412 = UCOM_FPPr
- { 2413, 1, 0, 0, "UCOM_FPr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(8<<8)|(232<<24), ImplicitList24, ImplicitList1, Barriers1, OperandInfo31 }, // Inst #2413 = UCOM_FPr
- { 2414, 2, 0, 0, "UCOM_FpIr32", 0, 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #2414 = UCOM_FpIr32
- { 2415, 2, 0, 0, "UCOM_FpIr64", 0, 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #2415 = UCOM_FpIr64
- { 2416, 2, 0, 0, "UCOM_FpIr80", 0, 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #2416 = UCOM_FpIr80
- { 2417, 2, 0, 0, "UCOM_Fpr32", 0|(1<<TID::UnmodeledSideEffects), 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #2417 = UCOM_Fpr32
- { 2418, 2, 0, 0, "UCOM_Fpr64", 0|(1<<TID::UnmodeledSideEffects), 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #2418 = UCOM_Fpr64
- { 2419, 2, 0, 0, "UCOM_Fpr80", 0|(1<<TID::UnmodeledSideEffects), 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #2419 = UCOM_Fpr80
- { 2420, 1, 0, 0, "UCOM_Fr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(8<<8)|(224<<24), ImplicitList24, ImplicitList1, Barriers1, OperandInfo31 }, // Inst #2420 = UCOM_Fr
- { 2421, 7, 1, 0, "UNPCKHPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(21<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2421 = UNPCKHPDrm
- { 2422, 3, 1, 0, "UNPCKHPDrr", 0, 0|5|(1<<6)|(1<<8)|(21<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2422 = UNPCKHPDrr
- { 2423, 7, 1, 0, "UNPCKHPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(21<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2423 = UNPCKHPSrm
- { 2424, 3, 1, 0, "UNPCKHPSrr", 0, 0|5|(1<<8)|(21<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2424 = UNPCKHPSrr
- { 2425, 7, 1, 0, "UNPCKLPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(20<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2425 = UNPCKLPDrm
- { 2426, 3, 1, 0, "UNPCKLPDrr", 0, 0|5|(1<<6)|(1<<8)|(20<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2426 = UNPCKLPDrr
- { 2427, 7, 1, 0, "UNPCKLPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(20<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2427 = UNPCKLPSrm
- { 2428, 3, 1, 0, "UNPCKLPSrr", 0, 0|5|(1<<8)|(20<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2428 = UNPCKLPSrr
- { 2429, 3, 0, 0, "VASTART_SAVE_XMM_REGS", 0|(1<<TID::UsesCustomInserter)|(1<<TID::Variadic), 0, NULL, NULL, NULL, OperandInfo205 }, // Inst #2429 = VASTART_SAVE_XMM_REGS
- { 2430, 5, 0, 0, "VERRm", 0|(1<<TID::UnmodeledSideEffects), 0|28|(1<<8), NULL, NULL, NULL, OperandInfo30 }, // Inst #2430 = VERRm
- { 2431, 1, 0, 0, "VERRr", 0|(1<<TID::UnmodeledSideEffects), 0|20|(1<<8), NULL, NULL, NULL, OperandInfo93 }, // Inst #2431 = VERRr
- { 2432, 5, 0, 0, "VERWm", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<8), NULL, NULL, NULL, OperandInfo30 }, // Inst #2432 = VERWm
- { 2433, 1, 0, 0, "VERWr", 0|(1<<TID::UnmodeledSideEffects), 0|21|(1<<8), NULL, NULL, NULL, OperandInfo93 }, // Inst #2433 = VERWr
- { 2434, 0, 0, 0, "VMCALL", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #2434 = VMCALL
- { 2435, 5, 0, 0, "VMCLEARm", 0|(1<<TID::UnmodeledSideEffects), 0|30|(1<<6)|(1<<8)|(199<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2435 = VMCLEARm
- { 2436, 0, 0, 0, "VMLAUNCH", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #2436 = VMLAUNCH
- { 2437, 5, 0, 0, "VMPTRLDm", 0|(1<<TID::UnmodeledSideEffects), 0|30|(1<<8)|(199<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2437 = VMPTRLDm
- { 2438, 5, 1, 0, "VMPTRSTm", 0|(1<<TID::UnmodeledSideEffects), 0|31|(1<<8)|(199<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2438 = VMPTRSTm
- { 2439, 6, 1, 0, "VMREAD32rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(120<<24), NULL, NULL, NULL, OperandInfo11 }, // Inst #2439 = VMREAD32rm
- { 2440, 2, 1, 0, "VMREAD32rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(120<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #2440 = VMREAD32rr
- { 2441, 6, 1, 0, "VMREAD64rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(120<<24), NULL, NULL, NULL, OperandInfo15 }, // Inst #2441 = VMREAD64rm
- { 2442, 2, 1, 0, "VMREAD64rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(120<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #2442 = VMREAD64rr
- { 2443, 0, 0, 0, "VMRESUME", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #2443 = VMRESUME
- { 2444, 6, 1, 0, "VMWRITE32rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(121<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #2444 = VMWRITE32rm
- { 2445, 2, 1, 0, "VMWRITE32rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(121<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #2445 = VMWRITE32rr
- { 2446, 6, 1, 0, "VMWRITE64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(121<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #2446 = VMWRITE64rm
- { 2447, 2, 1, 0, "VMWRITE64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(121<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #2447 = VMWRITE64rr
- { 2448, 0, 0, 0, "VMXOFF", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #2448 = VMXOFF
- { 2449, 5, 0, 0, "VMXON", 0|(1<<TID::UnmodeledSideEffects), 0|30|(11<<8)|(199<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2449 = VMXON
- { 2450, 1, 1, 0, "V_SET0", 0|(1<<TID::FoldableAsLoad)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo206 }, // Inst #2450 = V_SET0
- { 2451, 1, 1, 0, "V_SETALLONES", 0|(1<<TID::FoldableAsLoad)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(1<<6)|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo206 }, // Inst #2451 = V_SETALLONES
- { 2452, 0, 0, 0, "WAIT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(155<<24), NULL, NULL, NULL, 0 }, // Inst #2452 = WAIT
- { 2453, 0, 0, 0, "WBINVD", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(9<<24), NULL, NULL, NULL, 0 }, // Inst #2453 = WBINVD
- { 2454, 5, 0, 0, "WINCALL64m", 0|(1<<TID::Call)|(1<<TID::MayLoad)|(1<<TID::Variadic), 0|26|(255<<24), ImplicitList4, ImplicitList50, Barriers8, OperandInfo30 }, // Inst #2454 = WINCALL64m
- { 2455, 1, 0, 0, "WINCALL64pcrel32", 0|(1<<TID::Call)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|1|(232<<24), ImplicitList4, ImplicitList50, Barriers8, OperandInfo5 }, // Inst #2455 = WINCALL64pcrel32
- { 2456, 1, 0, 0, "WINCALL64r", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|18|(255<<24), ImplicitList4, ImplicitList50, Barriers8, OperandInfo58 }, // Inst #2456 = WINCALL64r
- { 2457, 0, 0, 0, "WRMSR", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(48<<24), NULL, NULL, NULL, 0 }, // Inst #2457 = WRMSR
- { 2458, 6, 0, 0, "XADD16rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(193<<24), NULL, NULL, NULL, OperandInfo7 }, // Inst #2458 = XADD16rm
- { 2459, 2, 1, 0, "XADD16rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<6)|(1<<8)|(193<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #2459 = XADD16rr
- { 2460, 6, 0, 0, "XADD32rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(193<<24), NULL, NULL, NULL, OperandInfo11 }, // Inst #2460 = XADD32rm
- { 2461, 2, 1, 0, "XADD32rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(193<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #2461 = XADD32rr
- { 2462, 6, 0, 0, "XADD64rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(1<<12)|(193<<24), NULL, NULL, NULL, OperandInfo15 }, // Inst #2462 = XADD64rm
- { 2463, 2, 1, 0, "XADD64rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(1<<12)|(193<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #2463 = XADD64rr
- { 2464, 6, 0, 0, "XADD8rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(192<<24), NULL, NULL, NULL, OperandInfo20 }, // Inst #2464 = XADD8rm
- { 2465, 2, 1, 0, "XADD8rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(192<<24), NULL, NULL, NULL, OperandInfo67 }, // Inst #2465 = XADD8rr
- { 2466, 1, 0, 0, "XCHG16ar", 0|(1<<TID::UnmodeledSideEffects), 0|2|(1<<6)|(144<<24), NULL, NULL, NULL, OperandInfo93 }, // Inst #2466 = XCHG16ar
- { 2467, 7, 1, 0, "XCHG16rm", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(1<<6)|(135<<24), NULL, NULL, NULL, OperandInfo9 }, // Inst #2467 = XCHG16rm
- { 2468, 3, 1, 0, "XCHG16rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(135<<24), NULL, NULL, NULL, OperandInfo10 }, // Inst #2468 = XCHG16rr
- { 2469, 1, 0, 0, "XCHG32ar", 0|(1<<TID::UnmodeledSideEffects), 0|2|(144<<24), NULL, NULL, NULL, OperandInfo57 }, // Inst #2469 = XCHG32ar
- { 2470, 7, 1, 0, "XCHG32rm", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(135<<24), NULL, NULL, NULL, OperandInfo13 }, // Inst #2470 = XCHG32rm
- { 2471, 3, 1, 0, "XCHG32rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(135<<24), NULL, NULL, NULL, OperandInfo14 }, // Inst #2471 = XCHG32rr
- { 2472, 1, 0, 0, "XCHG64ar", 0|(1<<TID::UnmodeledSideEffects), 0|2|(1<<12)|(144<<24), NULL, NULL, NULL, OperandInfo58 }, // Inst #2472 = XCHG64ar
- { 2473, 7, 1, 0, "XCHG64rm", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(1<<12)|(135<<24), NULL, NULL, NULL, OperandInfo17 }, // Inst #2473 = XCHG64rm
- { 2474, 3, 1, 0, "XCHG64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(135<<24), NULL, NULL, NULL, OperandInfo18 }, // Inst #2474 = XCHG64rr
- { 2475, 7, 1, 0, "XCHG8rm", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(134<<24), NULL, NULL, NULL, OperandInfo22 }, // Inst #2475 = XCHG8rm
- { 2476, 3, 1, 0, "XCHG8rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(134<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #2476 = XCHG8rr
- { 2477, 1, 0, 0, "XCH_F", 0|(1<<TID::UnmodeledSideEffects), 0|2|(4<<8)|(200<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2477 = XCH_F
- { 2478, 0, 0, 0, "XLAT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(215<<24), NULL, NULL, NULL, 0 }, // Inst #2478 = XLAT
- { 2479, 1, 0, 0, "XOR16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(2<<13)|(53<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2479 = XOR16i16
- { 2480, 6, 0, 0, "XOR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2480 = XOR16mi
- { 2481, 6, 0, 0, "XOR16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2481 = XOR16mi8
- { 2482, 6, 0, 0, "XOR16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #2482 = XOR16mr
- { 2483, 3, 1, 0, "XOR16ri", 0, 0|22|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2483 = XOR16ri
- { 2484, 3, 1, 0, "XOR16ri8", 0, 0|22|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2484 = XOR16ri8
- { 2485, 7, 1, 0, "XOR16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #2485 = XOR16rm
- { 2486, 3, 1, 0, "XOR16rr", 0|(1<<TID::Commutable), 0|3|(1<<6)|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2486 = XOR16rr
- { 2487, 3, 1, 0, "XOR16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2487 = XOR16rr_REV
- { 2488, 1, 0, 0, "XOR32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(53<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2488 = XOR32i32
- { 2489, 6, 0, 0, "XOR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2489 = XOR32mi
- { 2490, 6, 0, 0, "XOR32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2490 = XOR32mi8
- { 2491, 6, 0, 0, "XOR32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #2491 = XOR32mr
- { 2492, 3, 1, 0, "XOR32ri", 0, 0|22|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2492 = XOR32ri
- { 2493, 3, 1, 0, "XOR32ri8", 0, 0|22|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2493 = XOR32ri8
- { 2494, 7, 1, 0, "XOR32rm", 0|(1<<TID::MayLoad), 0|6|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #2494 = XOR32rm
- { 2495, 3, 1, 0, "XOR32rr", 0|(1<<TID::Commutable), 0|3|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2495 = XOR32rr
- { 2496, 3, 1, 0, "XOR32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2496 = XOR32rr_REV
- { 2497, 1, 0, 0, "XOR64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(3<<13)|(53<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2497 = XOR64i32
- { 2498, 6, 0, 0, "XOR64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2498 = XOR64mi32
- { 2499, 6, 0, 0, "XOR64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2499 = XOR64mi8
- { 2500, 6, 0, 0, "XOR64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #2500 = XOR64mr
- { 2501, 3, 1, 0, "XOR64ri32", 0, 0|22|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2501 = XOR64ri32
- { 2502, 3, 1, 0, "XOR64ri8", 0, 0|22|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2502 = XOR64ri8
- { 2503, 7, 1, 0, "XOR64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #2503 = XOR64rm
- { 2504, 3, 1, 0, "XOR64rr", 0|(1<<TID::Commutable), 0|3|(1<<12)|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2504 = XOR64rr
- { 2505, 3, 1, 0, "XOR64rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2505 = XOR64rr_REV
- { 2506, 1, 0, 0, "XOR8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(52<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2506 = XOR8i8
- { 2507, 6, 0, 0, "XOR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2507 = XOR8mi
- { 2508, 6, 0, 0, "XOR8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(48<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #2508 = XOR8mr
- { 2509, 3, 1, 0, "XOR8ri", 0, 0|22|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2509 = XOR8ri
- { 2510, 7, 1, 0, "XOR8rm", 0|(1<<TID::MayLoad), 0|6|(50<<24), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #2510 = XOR8rm
- { 2511, 3, 1, 0, "XOR8rr", 0|(1<<TID::Commutable), 0|3|(48<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #2511 = XOR8rr
- { 2512, 3, 1, 0, "XOR8rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(50<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #2512 = XOR8rr_REV
- { 2513, 7, 1, 0, "XORPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2513 = XORPDrm
- { 2514, 3, 1, 0, "XORPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2514 = XORPDrr
- { 2515, 7, 1, 0, "XORPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2515 = XORPSrm
- { 2516, 3, 1, 0, "XORPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2516 = XORPSrr
+ { 504, 0, 0, 0, "CS_PREFIX", 0|(1<<TID::UnmodeledSideEffects), 0|1|(46<<24), NULL, NULL, NULL, 0 }, // Inst #504 = CS_PREFIX
+ { 505, 6, 1, 0, "CVTDQ2PDrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(12<<8)|(230<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #505 = CVTDQ2PDrm
+ { 506, 2, 1, 0, "CVTDQ2PDrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(12<<8)|(230<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #506 = CVTDQ2PDrr
+ { 507, 6, 1, 0, "CVTDQ2PSrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(91<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #507 = CVTDQ2PSrm
+ { 508, 2, 1, 0, "CVTDQ2PSrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(91<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #508 = CVTDQ2PSrr
+ { 509, 6, 1, 0, "CVTPD2DQrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(11<<8)|(230<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #509 = CVTPD2DQrm
+ { 510, 2, 1, 0, "CVTPD2DQrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(11<<8)|(230<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #510 = CVTPD2DQrr
+ { 511, 6, 1, 0, "CVTPD2PSrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(90<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #511 = CVTPD2PSrm
+ { 512, 2, 1, 0, "CVTPD2PSrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(90<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #512 = CVTPD2PSrr
+ { 513, 6, 1, 0, "CVTPS2DQrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(91<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #513 = CVTPS2DQrm
+ { 514, 2, 1, 0, "CVTPS2DQrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(91<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #514 = CVTPS2DQrr
+ { 515, 6, 1, 0, "CVTPS2PDrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(90<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #515 = CVTPS2PDrm
+ { 516, 2, 1, 0, "CVTPS2PDrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(90<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #516 = CVTPS2PDrr
+ { 517, 6, 1, 0, "CVTSD2SI64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(11<<8)|(1<<12)|(45<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #517 = CVTSD2SI64rm
+ { 518, 2, 1, 0, "CVTSD2SI64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(11<<8)|(1<<12)|(45<<24), NULL, NULL, NULL, OperandInfo79 }, // Inst #518 = CVTSD2SI64rr
+ { 519, 6, 1, 0, "CVTSD2SSrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(90<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #519 = CVTSD2SSrm
+ { 520, 2, 1, 0, "CVTSD2SSrr", 0, 0|5|(11<<8)|(90<<24), NULL, NULL, NULL, OperandInfo81 }, // Inst #520 = CVTSD2SSrr
+ { 521, 6, 1, 0, "CVTSI2SD64rm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<12)|(42<<24), NULL, NULL, NULL, OperandInfo82 }, // Inst #521 = CVTSI2SD64rm
+ { 522, 2, 1, 0, "CVTSI2SD64rr", 0, 0|5|(11<<8)|(1<<12)|(42<<24), NULL, NULL, NULL, OperandInfo83 }, // Inst #522 = CVTSI2SD64rr
+ { 523, 6, 1, 0, "CVTSI2SDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(42<<24), NULL, NULL, NULL, OperandInfo82 }, // Inst #523 = CVTSI2SDrm
+ { 524, 2, 1, 0, "CVTSI2SDrr", 0, 0|5|(11<<8)|(42<<24), NULL, NULL, NULL, OperandInfo84 }, // Inst #524 = CVTSI2SDrr
+ { 525, 6, 1, 0, "CVTSI2SS64rm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<12)|(42<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #525 = CVTSI2SS64rm
+ { 526, 2, 1, 0, "CVTSI2SS64rr", 0, 0|5|(12<<8)|(1<<12)|(42<<24), NULL, NULL, NULL, OperandInfo85 }, // Inst #526 = CVTSI2SS64rr
+ { 527, 6, 1, 0, "CVTSI2SSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(42<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #527 = CVTSI2SSrm
+ { 528, 2, 1, 0, "CVTSI2SSrr", 0, 0|5|(12<<8)|(42<<24), NULL, NULL, NULL, OperandInfo86 }, // Inst #528 = CVTSI2SSrr
+ { 529, 6, 1, 0, "CVTSS2SDrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(90<<24), NULL, NULL, NULL, OperandInfo82 }, // Inst #529 = CVTSS2SDrm
+ { 530, 2, 1, 0, "CVTSS2SDrr", 0, 0|5|(12<<8)|(90<<24), NULL, NULL, NULL, OperandInfo87 }, // Inst #530 = CVTSS2SDrr
+ { 531, 6, 1, 0, "CVTSS2SI64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(12<<8)|(1<<12)|(45<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #531 = CVTSS2SI64rm
+ { 532, 2, 1, 0, "CVTSS2SI64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(12<<8)|(1<<12)|(45<<24), NULL, NULL, NULL, OperandInfo88 }, // Inst #532 = CVTSS2SI64rr
+ { 533, 6, 1, 0, "CVTSS2SIrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(12<<8)|(45<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #533 = CVTSS2SIrm
+ { 534, 2, 1, 0, "CVTSS2SIrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(12<<8)|(45<<24), NULL, NULL, NULL, OperandInfo89 }, // Inst #534 = CVTSS2SIrr
+ { 535, 6, 1, 0, "CVTTPS2DQrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(12<<8)|(91<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #535 = CVTTPS2DQrm
+ { 536, 2, 1, 0, "CVTTPS2DQrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(12<<8)|(91<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #536 = CVTTPS2DQrr
+ { 537, 6, 1, 0, "CVTTSD2SI64rm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<12)|(44<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #537 = CVTTSD2SI64rm
+ { 538, 2, 1, 0, "CVTTSD2SI64rr", 0, 0|5|(11<<8)|(1<<12)|(44<<24), NULL, NULL, NULL, OperandInfo79 }, // Inst #538 = CVTTSD2SI64rr
+ { 539, 6, 1, 0, "CVTTSD2SIrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(44<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #539 = CVTTSD2SIrm
+ { 540, 2, 1, 0, "CVTTSD2SIrr", 0, 0|5|(11<<8)|(44<<24), NULL, NULL, NULL, OperandInfo90 }, // Inst #540 = CVTTSD2SIrr
+ { 541, 6, 1, 0, "CVTTSS2SI64rm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<12)|(44<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #541 = CVTTSS2SI64rm
+ { 542, 2, 1, 0, "CVTTSS2SI64rr", 0, 0|5|(12<<8)|(1<<12)|(44<<24), NULL, NULL, NULL, OperandInfo88 }, // Inst #542 = CVTTSS2SI64rr
+ { 543, 6, 1, 0, "CVTTSS2SIrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(44<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #543 = CVTTSS2SIrm
+ { 544, 2, 1, 0, "CVTTSS2SIrr", 0, 0|5|(12<<8)|(44<<24), NULL, NULL, NULL, OperandInfo89 }, // Inst #544 = CVTTSS2SIrr
+ { 545, 0, 0, 0, "CWD", 0, 0|1|(1<<6)|(153<<24), ImplicitList12, ImplicitList20, NULL, 0 }, // Inst #545 = CWD
+ { 546, 0, 0, 0, "CWDE", 0, 0|1|(152<<24), ImplicitList12, ImplicitList13, NULL, 0 }, // Inst #546 = CWDE
+ { 547, 5, 0, 0, "DEC16m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #547 = DEC16m
+ { 548, 2, 1, 0, "DEC16r", 0|(1<<TID::ConvertibleTo3Addr), 0|2|(1<<6)|(72<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #548 = DEC16r
+ { 549, 5, 0, 0, "DEC32m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #549 = DEC32m
+ { 550, 2, 1, 0, "DEC32r", 0|(1<<TID::ConvertibleTo3Addr), 0|2|(72<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #550 = DEC32r
+ { 551, 5, 0, 0, "DEC64_16m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #551 = DEC64_16m
+ { 552, 2, 1, 0, "DEC64_16r", 0|(1<<TID::ConvertibleTo3Addr), 0|17|(1<<6)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #552 = DEC64_16r
+ { 553, 5, 0, 0, "DEC64_32m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #553 = DEC64_32m
+ { 554, 2, 1, 0, "DEC64_32r", 0|(1<<TID::ConvertibleTo3Addr), 0|17|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #554 = DEC64_32r
+ { 555, 5, 0, 0, "DEC64m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #555 = DEC64m
+ { 556, 2, 1, 0, "DEC64r", 0|(1<<TID::ConvertibleTo3Addr), 0|17|(1<<12)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #556 = DEC64r
+ { 557, 5, 0, 0, "DEC8m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(254<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #557 = DEC8m
+ { 558, 2, 1, 0, "DEC8r", 0, 0|17|(254<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #558 = DEC8r
+ { 559, 5, 0, 0, "DIV16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|30|(1<<6)|(247<<24), ImplicitList20, ImplicitList21, Barriers1, OperandInfo30 }, // Inst #559 = DIV16m
+ { 560, 1, 0, 0, "DIV16r", 0|(1<<TID::UnmodeledSideEffects), 0|22|(1<<6)|(247<<24), ImplicitList20, ImplicitList21, Barriers1, OperandInfo93 }, // Inst #560 = DIV16r
+ { 561, 5, 0, 0, "DIV32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|30|(247<<24), ImplicitList14, ImplicitList18, Barriers6, OperandInfo30 }, // Inst #561 = DIV32m
+ { 562, 1, 0, 0, "DIV32r", 0|(1<<TID::UnmodeledSideEffects), 0|22|(247<<24), ImplicitList14, ImplicitList18, Barriers6, OperandInfo57 }, // Inst #562 = DIV32r
+ { 563, 5, 0, 0, "DIV64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|30|(1<<12)|(247<<24), ImplicitList19, ImplicitList17, Barriers1, OperandInfo30 }, // Inst #563 = DIV64m
+ { 564, 1, 0, 0, "DIV64r", 0|(1<<TID::UnmodeledSideEffects), 0|22|(1<<12)|(247<<24), ImplicitList19, ImplicitList17, Barriers1, OperandInfo58 }, // Inst #564 = DIV64r
+ { 565, 5, 0, 0, "DIV8m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|30|(246<<24), ImplicitList12, ImplicitList22, Barriers1, OperandInfo30 }, // Inst #565 = DIV8m
+ { 566, 1, 0, 0, "DIV8r", 0|(1<<TID::UnmodeledSideEffects), 0|22|(246<<24), ImplicitList12, ImplicitList22, Barriers1, OperandInfo94 }, // Inst #566 = DIV8r
+ { 567, 7, 1, 0, "DIVPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(94<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #567 = DIVPDrm
+ { 568, 3, 1, 0, "DIVPDrr", 0, 0|5|(1<<6)|(1<<8)|(94<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #568 = DIVPDrr
+ { 569, 7, 1, 0, "DIVPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(94<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #569 = DIVPSrm
+ { 570, 3, 1, 0, "DIVPSrr", 0, 0|5|(1<<8)|(94<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #570 = DIVPSrr
+ { 571, 5, 0, 0, "DIVR_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|31|(216<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #571 = DIVR_F32m
+ { 572, 5, 0, 0, "DIVR_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|31|(220<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #572 = DIVR_F64m
+ { 573, 5, 0, 0, "DIVR_FI16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|31|(222<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #573 = DIVR_FI16m
+ { 574, 5, 0, 0, "DIVR_FI32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|31|(218<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #574 = DIVR_FI32m
+ { 575, 1, 0, 0, "DIVR_FPrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(9<<8)|(240<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #575 = DIVR_FPrST0
+ { 576, 1, 0, 0, "DIVR_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(248<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #576 = DIVR_FST0r
+ { 577, 7, 1, 0, "DIVR_Fp32m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #577 = DIVR_Fp32m
+ { 578, 7, 1, 0, "DIVR_Fp64m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #578 = DIVR_Fp64m
+ { 579, 7, 1, 0, "DIVR_Fp64m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #579 = DIVR_Fp64m32
+ { 580, 7, 1, 0, "DIVR_Fp80m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #580 = DIVR_Fp80m32
+ { 581, 7, 1, 0, "DIVR_Fp80m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #581 = DIVR_Fp80m64
+ { 582, 7, 1, 0, "DIVR_FpI16m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #582 = DIVR_FpI16m32
+ { 583, 7, 1, 0, "DIVR_FpI16m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #583 = DIVR_FpI16m64
+ { 584, 7, 1, 0, "DIVR_FpI16m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #584 = DIVR_FpI16m80
+ { 585, 7, 1, 0, "DIVR_FpI32m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #585 = DIVR_FpI32m32
+ { 586, 7, 1, 0, "DIVR_FpI32m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #586 = DIVR_FpI32m64
+ { 587, 7, 1, 0, "DIVR_FpI32m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #587 = DIVR_FpI32m80
+ { 588, 1, 0, 0, "DIVR_FrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(7<<8)|(240<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #588 = DIVR_FrST0
+ { 589, 7, 1, 0, "DIVSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(94<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #589 = DIVSDrm
+ { 590, 7, 1, 0, "DIVSDrm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(94<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #590 = DIVSDrm_Int
+ { 591, 3, 1, 0, "DIVSDrr", 0, 0|5|(11<<8)|(94<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #591 = DIVSDrr
+ { 592, 3, 1, 0, "DIVSDrr_Int", 0, 0|5|(11<<8)|(94<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #592 = DIVSDrr_Int
+ { 593, 7, 1, 0, "DIVSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(94<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #593 = DIVSSrm
+ { 594, 7, 1, 0, "DIVSSrm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(94<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #594 = DIVSSrm_Int
+ { 595, 3, 1, 0, "DIVSSrr", 0, 0|5|(12<<8)|(94<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #595 = DIVSSrr
+ { 596, 3, 1, 0, "DIVSSrr_Int", 0, 0|5|(12<<8)|(94<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #596 = DIVSSrr_Int
+ { 597, 5, 0, 0, "DIV_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|30|(216<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #597 = DIV_F32m
+ { 598, 5, 0, 0, "DIV_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|30|(220<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #598 = DIV_F64m
+ { 599, 5, 0, 0, "DIV_FI16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|30|(222<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #599 = DIV_FI16m
+ { 600, 5, 0, 0, "DIV_FI32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|30|(218<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #600 = DIV_FI32m
+ { 601, 1, 0, 0, "DIV_FPrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(9<<8)|(248<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #601 = DIV_FPrST0
+ { 602, 1, 0, 0, "DIV_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(240<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #602 = DIV_FST0r
+ { 603, 3, 1, 0, "DIV_Fp32", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #603 = DIV_Fp32
+ { 604, 7, 1, 0, "DIV_Fp32m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #604 = DIV_Fp32m
+ { 605, 3, 1, 0, "DIV_Fp64", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #605 = DIV_Fp64
+ { 606, 7, 1, 0, "DIV_Fp64m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #606 = DIV_Fp64m
+ { 607, 7, 1, 0, "DIV_Fp64m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #607 = DIV_Fp64m32
+ { 608, 3, 1, 0, "DIV_Fp80", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #608 = DIV_Fp80
+ { 609, 7, 1, 0, "DIV_Fp80m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #609 = DIV_Fp80m32
+ { 610, 7, 1, 0, "DIV_Fp80m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #610 = DIV_Fp80m64
+ { 611, 7, 1, 0, "DIV_FpI16m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #611 = DIV_FpI16m32
+ { 612, 7, 1, 0, "DIV_FpI16m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #612 = DIV_FpI16m64
+ { 613, 7, 1, 0, "DIV_FpI16m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #613 = DIV_FpI16m80
+ { 614, 7, 1, 0, "DIV_FpI32m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #614 = DIV_FpI32m32
+ { 615, 7, 1, 0, "DIV_FpI32m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #615 = DIV_FpI32m64
+ { 616, 7, 1, 0, "DIV_FpI32m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #616 = DIV_FpI32m80
+ { 617, 1, 0, 0, "DIV_FrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(7<<8)|(248<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #617 = DIV_FrST0
+ { 618, 8, 1, 0, "DPPDrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(65<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #618 = DPPDrmi
+ { 619, 4, 1, 0, "DPPDrri", 0|(1<<TID::Commutable), 0|5|(1<<6)|(14<<8)|(1<<13)|(65<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #619 = DPPDrri
+ { 620, 8, 1, 0, "DPPSrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(64<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #620 = DPPSrmi
+ { 621, 4, 1, 0, "DPPSrri", 0|(1<<TID::Commutable), 0|5|(1<<6)|(14<<8)|(1<<13)|(64<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #621 = DPPSrri
+ { 622, 0, 0, 0, "DS_PREFIX", 0|(1<<TID::UnmodeledSideEffects), 0|1|(62<<24), NULL, NULL, NULL, 0 }, // Inst #622 = DS_PREFIX
+ { 623, 1, 0, 0, "EH_RETURN", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|1|(195<<24), NULL, NULL, NULL, OperandInfo57 }, // Inst #623 = EH_RETURN
+ { 624, 1, 0, 0, "EH_RETURN64", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|1|(195<<24), NULL, NULL, NULL, OperandInfo58 }, // Inst #624 = EH_RETURN64
+ { 625, 2, 0, 0, "ENTER", 0|(1<<TID::UnmodeledSideEffects), 0|1|(200<<24), NULL, NULL, NULL, OperandInfo38 }, // Inst #625 = ENTER
+ { 626, 0, 0, 0, "ES_PREFIX", 0|(1<<TID::UnmodeledSideEffects), 0|1|(38<<24), NULL, NULL, NULL, 0 }, // Inst #626 = ES_PREFIX
+ { 627, 7, 0, 0, "EXTRACTPSmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(14<<8)|(1<<13)|(23<<24), NULL, NULL, NULL, OperandInfo95 }, // Inst #627 = EXTRACTPSmr
+ { 628, 3, 1, 0, "EXTRACTPSrr", 0, 0|3|(1<<6)|(14<<8)|(1<<13)|(23<<24), NULL, NULL, NULL, OperandInfo96 }, // Inst #628 = EXTRACTPSrr
+ { 629, 0, 0, 0, "F2XM1", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(240<<24), NULL, NULL, NULL, 0 }, // Inst #629 = F2XM1
+ { 630, 2, 0, 0, "FARCALL16i", 0|(1<<TID::Call)|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(154<<24), ImplicitList2, ImplicitList9, Barriers3, OperandInfo38 }, // Inst #630 = FARCALL16i
+ { 631, 5, 0, 0, "FARCALL16m", 0|(1<<TID::Call)|(1<<TID::UnmodeledSideEffects), 0|27|(1<<6)|(255<<24), ImplicitList2, ImplicitList9, Barriers3, OperandInfo30 }, // Inst #631 = FARCALL16m
+ { 632, 2, 0, 0, "FARCALL32i", 0|(1<<TID::Call)|(1<<TID::UnmodeledSideEffects), 0|1|(154<<24), ImplicitList2, ImplicitList9, Barriers3, OperandInfo38 }, // Inst #632 = FARCALL32i
+ { 633, 5, 0, 0, "FARCALL32m", 0|(1<<TID::Call)|(1<<TID::UnmodeledSideEffects), 0|27|(255<<24), ImplicitList2, ImplicitList9, Barriers3, OperandInfo30 }, // Inst #633 = FARCALL32m
+ { 634, 5, 0, 0, "FARCALL64", 0|(1<<TID::Call)|(1<<TID::UnmodeledSideEffects), 0|27|(1<<12)|(255<<24), ImplicitList4, ImplicitList10, Barriers4, OperandInfo30 }, // Inst #634 = FARCALL64
+ { 635, 2, 0, 0, "FARJMP16i", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(234<<24), NULL, NULL, NULL, OperandInfo38 }, // Inst #635 = FARJMP16i
+ { 636, 5, 0, 0, "FARJMP16m", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|29|(1<<6)|(255<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #636 = FARJMP16m
+ { 637, 2, 0, 0, "FARJMP32i", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(234<<24), NULL, NULL, NULL, OperandInfo38 }, // Inst #637 = FARJMP32i
+ { 638, 5, 0, 0, "FARJMP32m", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|29|(255<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #638 = FARJMP32m
+ { 639, 5, 0, 0, "FARJMP64", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|29|(1<<12)|(255<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #639 = FARJMP64
+ { 640, 5, 0, 0, "FBLDm", 0|(1<<TID::UnmodeledSideEffects), 0|28|(223<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #640 = FBLDm
+ { 641, 5, 1, 0, "FBSTPm", 0|(1<<TID::UnmodeledSideEffects), 0|30|(223<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #641 = FBSTPm
+ { 642, 5, 0, 0, "FCOM32m", 0|(1<<TID::UnmodeledSideEffects), 0|26|(216<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #642 = FCOM32m
+ { 643, 5, 0, 0, "FCOM64m", 0|(1<<TID::UnmodeledSideEffects), 0|26|(220<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #643 = FCOM64m
+ { 644, 5, 0, 0, "FCOMP32m", 0|(1<<TID::UnmodeledSideEffects), 0|27|(216<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #644 = FCOMP32m
+ { 645, 5, 0, 0, "FCOMP64m", 0|(1<<TID::UnmodeledSideEffects), 0|27|(220<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #645 = FCOMP64m
+ { 646, 0, 0, 0, "FCOMPP", 0|(1<<TID::UnmodeledSideEffects), 0|1|(9<<8)|(217<<24), NULL, NULL, NULL, 0 }, // Inst #646 = FCOMPP
+ { 647, 0, 0, 0, "FDECSTP", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(246<<24), NULL, NULL, NULL, 0 }, // Inst #647 = FDECSTP
+ { 648, 1, 0, 0, "FFREE", 0|(1<<TID::UnmodeledSideEffects), 0|2|(8<<8)|(192<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #648 = FFREE
+ { 649, 5, 0, 0, "FICOM16m", 0|(1<<TID::UnmodeledSideEffects), 0|26|(222<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #649 = FICOM16m
+ { 650, 5, 0, 0, "FICOM32m", 0|(1<<TID::UnmodeledSideEffects), 0|26|(218<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #650 = FICOM32m
+ { 651, 5, 0, 0, "FICOMP16m", 0|(1<<TID::UnmodeledSideEffects), 0|27|(222<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #651 = FICOMP16m
+ { 652, 5, 0, 0, "FICOMP32m", 0|(1<<TID::UnmodeledSideEffects), 0|27|(218<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #652 = FICOMP32m
+ { 653, 0, 0, 0, "FINCSTP", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(247<<24), NULL, NULL, NULL, 0 }, // Inst #653 = FINCSTP
+ { 654, 5, 0, 0, "FLDCW16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(217<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #654 = FLDCW16m
+ { 655, 5, 0, 0, "FLDENVm", 0|(1<<TID::UnmodeledSideEffects), 0|28|(217<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #655 = FLDENVm
+ { 656, 0, 0, 0, "FLDL2E", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(234<<24), NULL, NULL, NULL, 0 }, // Inst #656 = FLDL2E
+ { 657, 0, 0, 0, "FLDL2T", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(233<<24), NULL, NULL, NULL, 0 }, // Inst #657 = FLDL2T
+ { 658, 0, 0, 0, "FLDLG2", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(236<<24), NULL, NULL, NULL, 0 }, // Inst #658 = FLDLG2
+ { 659, 0, 0, 0, "FLDLN2", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(237<<24), NULL, NULL, NULL, 0 }, // Inst #659 = FLDLN2
+ { 660, 0, 0, 0, "FLDPI", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(235<<24), NULL, NULL, NULL, 0 }, // Inst #660 = FLDPI
+ { 661, 0, 0, 0, "FNCLEX", 0|(1<<TID::UnmodeledSideEffects), 0|1|(6<<8)|(226<<24), NULL, NULL, NULL, 0 }, // Inst #661 = FNCLEX
+ { 662, 0, 0, 0, "FNINIT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(6<<8)|(227<<24), NULL, NULL, NULL, 0 }, // Inst #662 = FNINIT
+ { 663, 0, 0, 0, "FNOP", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(208<<24), NULL, NULL, NULL, 0 }, // Inst #663 = FNOP
+ { 664, 5, 0, 0, "FNSTCW16m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|31|(217<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #664 = FNSTCW16m
+ { 665, 0, 0, 0, "FNSTSW8r", 0|(1<<TID::UnmodeledSideEffects), 0|1|(10<<8)|(224<<24), NULL, ImplicitList12, NULL, 0 }, // Inst #665 = FNSTSW8r
+ { 666, 5, 1, 0, "FNSTSWm", 0|(1<<TID::UnmodeledSideEffects), 0|31|(221<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #666 = FNSTSWm
+ { 667, 6, 0, 0, "FP32_TO_INT16_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo97 }, // Inst #667 = FP32_TO_INT16_IN_MEM
+ { 668, 6, 0, 0, "FP32_TO_INT32_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo97 }, // Inst #668 = FP32_TO_INT32_IN_MEM
+ { 669, 6, 0, 0, "FP32_TO_INT64_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo97 }, // Inst #669 = FP32_TO_INT64_IN_MEM
+ { 670, 6, 0, 0, "FP64_TO_INT16_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo98 }, // Inst #670 = FP64_TO_INT16_IN_MEM
+ { 671, 6, 0, 0, "FP64_TO_INT32_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo98 }, // Inst #671 = FP64_TO_INT32_IN_MEM
+ { 672, 6, 0, 0, "FP64_TO_INT64_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo98 }, // Inst #672 = FP64_TO_INT64_IN_MEM
+ { 673, 6, 0, 0, "FP80_TO_INT16_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo99 }, // Inst #673 = FP80_TO_INT16_IN_MEM
+ { 674, 6, 0, 0, "FP80_TO_INT32_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo99 }, // Inst #674 = FP80_TO_INT32_IN_MEM
+ { 675, 6, 0, 0, "FP80_TO_INT64_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo99 }, // Inst #675 = FP80_TO_INT64_IN_MEM
+ { 676, 0, 0, 0, "FPATAN", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(243<<24), NULL, NULL, NULL, 0 }, // Inst #676 = FPATAN
+ { 677, 0, 0, 0, "FPREM", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(248<<24), NULL, NULL, NULL, 0 }, // Inst #677 = FPREM
+ { 678, 0, 0, 0, "FPREM1", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(245<<24), NULL, NULL, NULL, 0 }, // Inst #678 = FPREM1
+ { 679, 0, 0, 0, "FPTAN", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(242<<24), NULL, NULL, NULL, 0 }, // Inst #679 = FPTAN
+ { 680, 0, 0, 0, "FP_REG_KILL", 0|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0, NULL, ImplicitList23, Barriers7, 0 }, // Inst #680 = FP_REG_KILL
+ { 681, 0, 0, 0, "FRNDINT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(252<<24), NULL, NULL, NULL, 0 }, // Inst #681 = FRNDINT
+ { 682, 5, 1, 0, "FRSTORm", 0|(1<<TID::UnmodeledSideEffects), 0|28|(221<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #682 = FRSTORm
+ { 683, 5, 1, 0, "FSAVEm", 0|(1<<TID::UnmodeledSideEffects), 0|30|(221<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #683 = FSAVEm
+ { 684, 0, 0, 0, "FSCALE", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(253<<24), NULL, NULL, NULL, 0 }, // Inst #684 = FSCALE
+ { 685, 0, 0, 0, "FSINCOS", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(251<<24), NULL, NULL, NULL, 0 }, // Inst #685 = FSINCOS
+ { 686, 5, 1, 0, "FSTENVm", 0|(1<<TID::UnmodeledSideEffects), 0|30|(217<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #686 = FSTENVm
+ { 687, 6, 1, 0, "FS_MOV32rm", 0|(1<<TID::MayLoad), 0|6|(1<<20)|(139<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #687 = FS_MOV32rm
+ { 688, 0, 0, 0, "FS_PREFIX", 0|(1<<TID::UnmodeledSideEffects), 0|1|(100<<24), NULL, NULL, NULL, 0 }, // Inst #688 = FS_PREFIX
+ { 689, 0, 0, 0, "FXAM", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(229<<24), NULL, NULL, NULL, 0 }, // Inst #689 = FXAM
+ { 690, 5, 0, 0, "FXRSTOR", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<8)|(174<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #690 = FXRSTOR
+ { 691, 5, 1, 0, "FXSAVE", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<8)|(174<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #691 = FXSAVE
+ { 692, 0, 0, 0, "FXTRACT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(244<<24), NULL, NULL, NULL, 0 }, // Inst #692 = FXTRACT
+ { 693, 0, 0, 0, "FYL2X", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(241<<24), NULL, NULL, NULL, 0 }, // Inst #693 = FYL2X
+ { 694, 0, 0, 0, "FYL2XP1", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(249<<24), NULL, NULL, NULL, 0 }, // Inst #694 = FYL2XP1
+ { 695, 1, 1, 0, "FpGET_ST0_32", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, NULL, NULL, OperandInfo100 }, // Inst #695 = FpGET_ST0_32
+ { 696, 1, 1, 0, "FpGET_ST0_64", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, NULL, NULL, OperandInfo101 }, // Inst #696 = FpGET_ST0_64
+ { 697, 1, 1, 0, "FpGET_ST0_80", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, NULL, NULL, OperandInfo102 }, // Inst #697 = FpGET_ST0_80
+ { 698, 1, 1, 0, "FpGET_ST1_32", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, NULL, NULL, OperandInfo100 }, // Inst #698 = FpGET_ST1_32
+ { 699, 1, 1, 0, "FpGET_ST1_64", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, NULL, NULL, OperandInfo101 }, // Inst #699 = FpGET_ST1_64
+ { 700, 1, 1, 0, "FpGET_ST1_80", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, NULL, NULL, OperandInfo102 }, // Inst #700 = FpGET_ST1_80
+ { 701, 1, 0, 0, "FpSET_ST0_32", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, ImplicitList24, NULL, OperandInfo100 }, // Inst #701 = FpSET_ST0_32
+ { 702, 1, 0, 0, "FpSET_ST0_64", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, ImplicitList24, NULL, OperandInfo101 }, // Inst #702 = FpSET_ST0_64
+ { 703, 1, 0, 0, "FpSET_ST0_80", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, ImplicitList24, NULL, OperandInfo102 }, // Inst #703 = FpSET_ST0_80
+ { 704, 1, 0, 0, "FpSET_ST1_32", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, ImplicitList25, NULL, OperandInfo100 }, // Inst #704 = FpSET_ST1_32
+ { 705, 1, 0, 0, "FpSET_ST1_64", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, ImplicitList25, NULL, OperandInfo101 }, // Inst #705 = FpSET_ST1_64
+ { 706, 1, 0, 0, "FpSET_ST1_80", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, ImplicitList25, NULL, OperandInfo102 }, // Inst #706 = FpSET_ST1_80
+ { 707, 7, 1, 0, "FsANDNPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(85<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #707 = FsANDNPDrm
+ { 708, 3, 1, 0, "FsANDNPDrr", 0, 0|5|(1<<6)|(1<<8)|(85<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #708 = FsANDNPDrr
+ { 709, 7, 1, 0, "FsANDNPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(85<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #709 = FsANDNPSrm
+ { 710, 3, 1, 0, "FsANDNPSrr", 0, 0|5|(1<<8)|(85<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #710 = FsANDNPSrr
+ { 711, 7, 1, 0, "FsANDPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(84<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #711 = FsANDPDrm
+ { 712, 3, 1, 0, "FsANDPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(84<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #712 = FsANDPDrr
+ { 713, 7, 1, 0, "FsANDPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(84<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #713 = FsANDPSrm
+ { 714, 3, 1, 0, "FsANDPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(84<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #714 = FsANDPSrr
+ { 715, 1, 1, 0, "FsFLD0SD", 0|(1<<TID::FoldableAsLoad)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(1<<6)|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo103 }, // Inst #715 = FsFLD0SD
+ { 716, 1, 1, 0, "FsFLD0SS", 0|(1<<TID::FoldableAsLoad)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(1<<6)|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo104 }, // Inst #716 = FsFLD0SS
+ { 717, 6, 1, 0, "FsMOVAPDrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<6)|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo82 }, // Inst #717 = FsMOVAPDrm
+ { 718, 2, 1, 0, "FsMOVAPDrr", 0, 0|5|(1<<6)|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo105 }, // Inst #718 = FsMOVAPDrr
+ { 719, 6, 1, 0, "FsMOVAPSrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #719 = FsMOVAPSrm
+ { 720, 2, 1, 0, "FsMOVAPSrr", 0, 0|5|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo106 }, // Inst #720 = FsMOVAPSrr
+ { 721, 7, 1, 0, "FsORPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #721 = FsORPDrm
+ { 722, 3, 1, 0, "FsORPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #722 = FsORPDrr
+ { 723, 7, 1, 0, "FsORPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #723 = FsORPSrm
+ { 724, 3, 1, 0, "FsORPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #724 = FsORPSrr
+ { 725, 7, 1, 0, "FsXORPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #725 = FsXORPDrm
+ { 726, 3, 1, 0, "FsXORPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #726 = FsXORPDrr
+ { 727, 7, 1, 0, "FsXORPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #727 = FsXORPSrm
+ { 728, 3, 1, 0, "FsXORPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #728 = FsXORPSrr
+ { 729, 6, 1, 0, "GS_MOV32rm", 0|(1<<TID::MayLoad), 0|6|(2<<20)|(139<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #729 = GS_MOV32rm
+ { 730, 0, 0, 0, "GS_PREFIX", 0|(1<<TID::UnmodeledSideEffects), 0|1|(101<<24), NULL, NULL, NULL, 0 }, // Inst #730 = GS_PREFIX
+ { 731, 7, 1, 0, "HADDPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(124<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #731 = HADDPDrm
+ { 732, 3, 1, 0, "HADDPDrr", 0, 0|5|(1<<6)|(1<<8)|(124<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #732 = HADDPDrr
+ { 733, 7, 1, 0, "HADDPSrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(124<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #733 = HADDPSrm
+ { 734, 3, 1, 0, "HADDPSrr", 0, 0|5|(11<<8)|(124<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #734 = HADDPSrr
+ { 735, 0, 0, 0, "HLT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(244<<24), NULL, NULL, NULL, 0 }, // Inst #735 = HLT
+ { 736, 7, 1, 0, "HSUBPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(125<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #736 = HSUBPDrm
+ { 737, 3, 1, 0, "HSUBPDrr", 0, 0|5|(1<<6)|(1<<8)|(125<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #737 = HSUBPDrr
+ { 738, 7, 1, 0, "HSUBPSrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(125<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #738 = HSUBPSrm
+ { 739, 3, 1, 0, "HSUBPSrr", 0, 0|5|(11<<8)|(125<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #739 = HSUBPSrr
+ { 740, 5, 0, 0, "IDIV16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|31|(1<<6)|(247<<24), ImplicitList20, ImplicitList21, Barriers1, OperandInfo30 }, // Inst #740 = IDIV16m
+ { 741, 1, 0, 0, "IDIV16r", 0|(1<<TID::UnmodeledSideEffects), 0|23|(1<<6)|(247<<24), ImplicitList20, ImplicitList21, Barriers1, OperandInfo93 }, // Inst #741 = IDIV16r
+ { 742, 5, 0, 0, "IDIV32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|31|(247<<24), ImplicitList14, ImplicitList18, Barriers6, OperandInfo30 }, // Inst #742 = IDIV32m
+ { 743, 1, 0, 0, "IDIV32r", 0|(1<<TID::UnmodeledSideEffects), 0|23|(247<<24), ImplicitList14, ImplicitList18, Barriers6, OperandInfo57 }, // Inst #743 = IDIV32r
+ { 744, 5, 0, 0, "IDIV64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|31|(1<<12)|(247<<24), ImplicitList19, ImplicitList17, Barriers1, OperandInfo30 }, // Inst #744 = IDIV64m
+ { 745, 1, 0, 0, "IDIV64r", 0|(1<<TID::UnmodeledSideEffects), 0|23|(1<<12)|(247<<24), ImplicitList19, ImplicitList17, Barriers1, OperandInfo58 }, // Inst #745 = IDIV64r
+ { 746, 5, 0, 0, "IDIV8m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|31|(246<<24), ImplicitList12, ImplicitList22, Barriers1, OperandInfo30 }, // Inst #746 = IDIV8m
+ { 747, 1, 0, 0, "IDIV8r", 0|(1<<TID::UnmodeledSideEffects), 0|23|(246<<24), ImplicitList12, ImplicitList22, Barriers1, OperandInfo94 }, // Inst #747 = IDIV8r
+ { 748, 5, 0, 0, "ILD_F16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|24|(223<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #748 = ILD_F16m
+ { 749, 5, 0, 0, "ILD_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|24|(219<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #749 = ILD_F32m
+ { 750, 5, 0, 0, "ILD_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(223<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #750 = ILD_F64m
+ { 751, 6, 1, 0, "ILD_Fp16m32", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo107 }, // Inst #751 = ILD_Fp16m32
+ { 752, 6, 1, 0, "ILD_Fp16m64", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo108 }, // Inst #752 = ILD_Fp16m64
+ { 753, 6, 1, 0, "ILD_Fp16m80", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo109 }, // Inst #753 = ILD_Fp16m80
+ { 754, 6, 1, 0, "ILD_Fp32m32", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo107 }, // Inst #754 = ILD_Fp32m32
+ { 755, 6, 1, 0, "ILD_Fp32m64", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo108 }, // Inst #755 = ILD_Fp32m64
+ { 756, 6, 1, 0, "ILD_Fp32m80", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo109 }, // Inst #756 = ILD_Fp32m80
+ { 757, 6, 1, 0, "ILD_Fp64m32", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo107 }, // Inst #757 = ILD_Fp64m32
+ { 758, 6, 1, 0, "ILD_Fp64m64", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo108 }, // Inst #758 = ILD_Fp64m64
+ { 759, 6, 1, 0, "ILD_Fp64m80", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo109 }, // Inst #759 = ILD_Fp64m80
+ { 760, 5, 0, 0, "IMUL16m", 0|(1<<TID::MayLoad), 0|29|(1<<6)|(247<<24), ImplicitList12, ImplicitList21, Barriers1, OperandInfo30 }, // Inst #760 = IMUL16m
+ { 761, 1, 0, 0, "IMUL16r", 0, 0|21|(1<<6)|(247<<24), ImplicitList12, ImplicitList21, Barriers1, OperandInfo93 }, // Inst #761 = IMUL16r
+ { 762, 7, 1, 0, "IMUL16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(175<<24), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #762 = IMUL16rm
+ { 763, 7, 1, 0, "IMUL16rmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(3<<13)|(105<<24), NULL, ImplicitList1, Barriers1, OperandInfo110 }, // Inst #763 = IMUL16rmi
+ { 764, 7, 1, 0, "IMUL16rmi8", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<13)|(107<<24), NULL, ImplicitList1, Barriers1, OperandInfo110 }, // Inst #764 = IMUL16rmi8
+ { 765, 3, 1, 0, "IMUL16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(175<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #765 = IMUL16rr
+ { 766, 3, 1, 0, "IMUL16rri", 0, 0|5|(1<<6)|(3<<13)|(105<<24), NULL, ImplicitList1, Barriers1, OperandInfo111 }, // Inst #766 = IMUL16rri
+ { 767, 3, 1, 0, "IMUL16rri8", 0, 0|5|(1<<6)|(1<<13)|(107<<24), NULL, ImplicitList1, Barriers1, OperandInfo111 }, // Inst #767 = IMUL16rri8
+ { 768, 5, 0, 0, "IMUL32m", 0|(1<<TID::MayLoad), 0|29|(247<<24), ImplicitList13, ImplicitList18, Barriers6, OperandInfo30 }, // Inst #768 = IMUL32m
+ { 769, 1, 0, 0, "IMUL32r", 0, 0|21|(247<<24), ImplicitList13, ImplicitList18, Barriers6, OperandInfo57 }, // Inst #769 = IMUL32r
+ { 770, 7, 1, 0, "IMUL32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(175<<24), NULL, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #770 = IMUL32rm
+ { 771, 7, 1, 0, "IMUL32rmi", 0|(1<<TID::MayLoad), 0|6|(4<<13)|(105<<24), NULL, ImplicitList1, Barriers1, OperandInfo112 }, // Inst #771 = IMUL32rmi
+ { 772, 7, 1, 0, "IMUL32rmi8", 0|(1<<TID::MayLoad), 0|6|(1<<13)|(107<<24), NULL, ImplicitList1, Barriers1, OperandInfo112 }, // Inst #772 = IMUL32rmi8
+ { 773, 3, 1, 0, "IMUL32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(175<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #773 = IMUL32rr
+ { 774, 3, 1, 0, "IMUL32rri", 0, 0|5|(4<<13)|(105<<24), NULL, ImplicitList1, Barriers1, OperandInfo113 }, // Inst #774 = IMUL32rri
+ { 775, 3, 1, 0, "IMUL32rri8", 0, 0|5|(1<<13)|(107<<24), NULL, ImplicitList1, Barriers1, OperandInfo113 }, // Inst #775 = IMUL32rri8
+ { 776, 5, 0, 0, "IMUL64m", 0|(1<<TID::MayLoad), 0|29|(1<<12)|(247<<24), ImplicitList15, ImplicitList17, Barriers1, OperandInfo30 }, // Inst #776 = IMUL64m
+ { 777, 1, 0, 0, "IMUL64r", 0, 0|21|(1<<12)|(247<<24), ImplicitList15, ImplicitList17, Barriers1, OperandInfo58 }, // Inst #777 = IMUL64r
+ { 778, 7, 1, 0, "IMUL64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(175<<24), NULL, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #778 = IMUL64rm
+ { 779, 7, 1, 0, "IMUL64rmi32", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(4<<13)|(105<<24), NULL, ImplicitList1, Barriers1, OperandInfo114 }, // Inst #779 = IMUL64rmi32
+ { 780, 7, 1, 0, "IMUL64rmi8", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(1<<13)|(107<<24), NULL, ImplicitList1, Barriers1, OperandInfo114 }, // Inst #780 = IMUL64rmi8
+ { 781, 3, 1, 0, "IMUL64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(175<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #781 = IMUL64rr
+ { 782, 3, 1, 0, "IMUL64rri32", 0, 0|5|(1<<12)|(4<<13)|(105<<24), NULL, ImplicitList1, Barriers1, OperandInfo115 }, // Inst #782 = IMUL64rri32
+ { 783, 3, 1, 0, "IMUL64rri8", 0, 0|5|(1<<12)|(1<<13)|(107<<24), NULL, ImplicitList1, Barriers1, OperandInfo115 }, // Inst #783 = IMUL64rri8
+ { 784, 5, 0, 0, "IMUL8m", 0|(1<<TID::MayLoad), 0|29|(246<<24), ImplicitList11, ImplicitList22, Barriers1, OperandInfo30 }, // Inst #784 = IMUL8m
+ { 785, 1, 0, 0, "IMUL8r", 0, 0|21|(246<<24), ImplicitList11, ImplicitList22, Barriers1, OperandInfo94 }, // Inst #785 = IMUL8r
+ { 786, 0, 0, 0, "IN16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(109<<24), NULL, NULL, NULL, 0 }, // Inst #786 = IN16
+ { 787, 1, 0, 0, "IN16ri", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<13)|(229<<24), NULL, ImplicitList12, NULL, OperandInfo5 }, // Inst #787 = IN16ri
+ { 788, 0, 0, 0, "IN16rr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(237<<24), ImplicitList26, ImplicitList12, NULL, 0 }, // Inst #788 = IN16rr
+ { 789, 0, 0, 0, "IN32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(109<<24), NULL, NULL, NULL, 0 }, // Inst #789 = IN32
+ { 790, 1, 0, 0, "IN32ri", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(229<<24), NULL, ImplicitList13, NULL, OperandInfo5 }, // Inst #790 = IN32ri
+ { 791, 0, 0, 0, "IN32rr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(237<<24), ImplicitList26, ImplicitList13, NULL, 0 }, // Inst #791 = IN32rr
+ { 792, 0, 0, 0, "IN8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(108<<24), NULL, NULL, NULL, 0 }, // Inst #792 = IN8
+ { 793, 1, 0, 0, "IN8ri", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(228<<24), NULL, ImplicitList11, NULL, OperandInfo5 }, // Inst #793 = IN8ri
+ { 794, 0, 0, 0, "IN8rr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(236<<24), ImplicitList26, ImplicitList11, NULL, 0 }, // Inst #794 = IN8rr
+ { 795, 5, 0, 0, "INC16m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #795 = INC16m
+ { 796, 2, 1, 0, "INC16r", 0|(1<<TID::ConvertibleTo3Addr), 0|2|(1<<6)|(64<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #796 = INC16r
+ { 797, 5, 0, 0, "INC32m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #797 = INC32m
+ { 798, 2, 1, 0, "INC32r", 0|(1<<TID::ConvertibleTo3Addr), 0|2|(64<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #798 = INC32r
+ { 799, 5, 0, 0, "INC64_16m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #799 = INC64_16m
+ { 800, 2, 1, 0, "INC64_16r", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(1<<6)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #800 = INC64_16r
+ { 801, 5, 0, 0, "INC64_32m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #801 = INC64_32m
+ { 802, 2, 1, 0, "INC64_32r", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #802 = INC64_32r
+ { 803, 5, 0, 0, "INC64m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<12)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #803 = INC64m
+ { 804, 2, 1, 0, "INC64r", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(1<<12)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #804 = INC64r
+ { 805, 5, 0, 0, "INC8m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(254<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #805 = INC8m
+ { 806, 2, 1, 0, "INC8r", 0, 0|16|(254<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #806 = INC8r
+ { 807, 8, 1, 0, "INSERTPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(33<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #807 = INSERTPSrm
+ { 808, 4, 1, 0, "INSERTPSrr", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(33<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #808 = INSERTPSrr
+ { 809, 1, 0, 0, "INT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(205<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #809 = INT
+ { 810, 0, 0, 0, "INT3", 0|(1<<TID::UnmodeledSideEffects), 0|1|(204<<24), NULL, NULL, NULL, 0 }, // Inst #810 = INT3
+ { 811, 0, 0, 0, "INVD", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(8<<24), NULL, NULL, NULL, 0 }, // Inst #811 = INVD
+ { 812, 0, 0, 0, "INVEPT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(13<<8)|(128<<24), NULL, NULL, NULL, 0 }, // Inst #812 = INVEPT
+ { 813, 5, 0, 0, "INVLPG", 0|(1<<TID::UnmodeledSideEffects), 0|31|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #813 = INVLPG
+ { 814, 0, 0, 0, "INVVPID", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(13<<8)|(129<<24), NULL, NULL, NULL, 0 }, // Inst #814 = INVVPID
+ { 815, 0, 0, 0, "IRET16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(207<<24), NULL, NULL, NULL, 0 }, // Inst #815 = IRET16
+ { 816, 0, 0, 0, "IRET32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(207<<24), NULL, NULL, NULL, 0 }, // Inst #816 = IRET32
+ { 817, 0, 0, 0, "IRET64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(207<<24), NULL, NULL, NULL, 0 }, // Inst #817 = IRET64
+ { 818, 5, 0, 0, "ISTT_FP16m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|25|(223<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #818 = ISTT_FP16m
+ { 819, 5, 0, 0, "ISTT_FP32m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|25|(219<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #819 = ISTT_FP32m
+ { 820, 5, 0, 0, "ISTT_FP64m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|25|(221<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #820 = ISTT_FP64m
+ { 821, 6, 0, 0, "ISTT_Fp16m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #821 = ISTT_Fp16m32
+ { 822, 6, 0, 0, "ISTT_Fp16m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #822 = ISTT_Fp16m64
+ { 823, 6, 0, 0, "ISTT_Fp16m80", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #823 = ISTT_Fp16m80
+ { 824, 6, 0, 0, "ISTT_Fp32m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #824 = ISTT_Fp32m32
+ { 825, 6, 0, 0, "ISTT_Fp32m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #825 = ISTT_Fp32m64
+ { 826, 6, 0, 0, "ISTT_Fp32m80", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #826 = ISTT_Fp32m80
+ { 827, 6, 0, 0, "ISTT_Fp64m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #827 = ISTT_Fp64m32
+ { 828, 6, 0, 0, "ISTT_Fp64m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #828 = ISTT_Fp64m64
+ { 829, 6, 0, 0, "ISTT_Fp64m80", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #829 = ISTT_Fp64m80
+ { 830, 5, 0, 0, "IST_F16m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|26|(223<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #830 = IST_F16m
+ { 831, 5, 0, 0, "IST_F32m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|26|(219<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #831 = IST_F32m
+ { 832, 5, 0, 0, "IST_FP16m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|27|(223<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #832 = IST_FP16m
+ { 833, 5, 0, 0, "IST_FP32m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|27|(219<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #833 = IST_FP32m
+ { 834, 5, 0, 0, "IST_FP64m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|31|(223<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #834 = IST_FP64m
+ { 835, 6, 0, 0, "IST_Fp16m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #835 = IST_Fp16m32
+ { 836, 6, 0, 0, "IST_Fp16m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #836 = IST_Fp16m64
+ { 837, 6, 0, 0, "IST_Fp16m80", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #837 = IST_Fp16m80
+ { 838, 6, 0, 0, "IST_Fp32m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #838 = IST_Fp32m32
+ { 839, 6, 0, 0, "IST_Fp32m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #839 = IST_Fp32m64
+ { 840, 6, 0, 0, "IST_Fp32m80", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #840 = IST_Fp32m80
+ { 841, 6, 0, 0, "IST_Fp64m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #841 = IST_Fp64m32
+ { 842, 6, 0, 0, "IST_Fp64m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #842 = IST_Fp64m64
+ { 843, 6, 0, 0, "IST_Fp64m80", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #843 = IST_Fp64m80
+ { 844, 8, 1, 0, "Int_CMPSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #844 = Int_CMPSDrm
+ { 845, 4, 1, 0, "Int_CMPSDrr", 0, 0|5|(11<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #845 = Int_CMPSDrr
+ { 846, 8, 1, 0, "Int_CMPSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #846 = Int_CMPSSrm
+ { 847, 4, 1, 0, "Int_CMPSSrr", 0, 0|5|(12<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #847 = Int_CMPSSrr
+ { 848, 6, 0, 0, "Int_COMISDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(47<<24), NULL, ImplicitList1, Barriers1, OperandInfo74 }, // Inst #848 = Int_COMISDrm
+ { 849, 2, 0, 0, "Int_COMISDrr", 0, 0|5|(1<<6)|(1<<8)|(47<<24), NULL, ImplicitList1, Barriers1, OperandInfo75 }, // Inst #849 = Int_COMISDrr
+ { 850, 6, 0, 0, "Int_COMISSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(47<<24), NULL, ImplicitList1, Barriers1, OperandInfo74 }, // Inst #850 = Int_COMISSrm
+ { 851, 2, 0, 0, "Int_COMISSrr", 0, 0|5|(1<<8)|(47<<24), NULL, ImplicitList1, Barriers1, OperandInfo75 }, // Inst #851 = Int_COMISSrr
+ { 852, 6, 1, 0, "Int_CVTDQ2PDrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(230<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #852 = Int_CVTDQ2PDrm
+ { 853, 2, 1, 0, "Int_CVTDQ2PDrr", 0, 0|5|(12<<8)|(230<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #853 = Int_CVTDQ2PDrr
+ { 854, 6, 1, 0, "Int_CVTDQ2PSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(91<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #854 = Int_CVTDQ2PSrm
+ { 855, 2, 1, 0, "Int_CVTDQ2PSrr", 0, 0|5|(1<<8)|(91<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #855 = Int_CVTDQ2PSrr
+ { 856, 6, 1, 0, "Int_CVTPD2DQrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(230<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #856 = Int_CVTPD2DQrm
+ { 857, 2, 1, 0, "Int_CVTPD2DQrr", 0, 0|5|(11<<8)|(230<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #857 = Int_CVTPD2DQrr
+ { 858, 6, 1, 0, "Int_CVTPD2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #858 = Int_CVTPD2PIrm
+ { 859, 2, 1, 0, "Int_CVTPD2PIrr", 0, 0|5|(1<<6)|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #859 = Int_CVTPD2PIrr
+ { 860, 6, 1, 0, "Int_CVTPD2PSrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(90<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #860 = Int_CVTPD2PSrm
+ { 861, 2, 1, 0, "Int_CVTPD2PSrr", 0, 0|5|(1<<6)|(1<<8)|(90<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #861 = Int_CVTPD2PSrr
+ { 862, 6, 1, 0, "Int_CVTPI2PDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #862 = Int_CVTPI2PDrm
+ { 863, 2, 1, 0, "Int_CVTPI2PDrr", 0, 0|5|(1<<6)|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo119 }, // Inst #863 = Int_CVTPI2PDrr
+ { 864, 7, 1, 0, "Int_CVTPI2PSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #864 = Int_CVTPI2PSrm
+ { 865, 3, 1, 0, "Int_CVTPI2PSrr", 0, 0|5|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo120 }, // Inst #865 = Int_CVTPI2PSrr
+ { 866, 6, 1, 0, "Int_CVTPS2DQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(91<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #866 = Int_CVTPS2DQrm
+ { 867, 2, 1, 0, "Int_CVTPS2DQrr", 0, 0|5|(1<<6)|(1<<8)|(91<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #867 = Int_CVTPS2DQrr
+ { 868, 6, 1, 0, "Int_CVTPS2PDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(90<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #868 = Int_CVTPS2PDrm
+ { 869, 2, 1, 0, "Int_CVTPS2PDrr", 0, 0|5|(1<<8)|(90<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #869 = Int_CVTPS2PDrr
+ { 870, 6, 1, 0, "Int_CVTPS2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #870 = Int_CVTPS2PIrm
+ { 871, 2, 1, 0, "Int_CVTPS2PIrr", 0, 0|5|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #871 = Int_CVTPS2PIrr
+ { 872, 6, 1, 0, "Int_CVTSD2SI64rm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<12)|(45<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #872 = Int_CVTSD2SI64rm
+ { 873, 2, 1, 0, "Int_CVTSD2SI64rr", 0, 0|5|(11<<8)|(1<<12)|(45<<24), NULL, NULL, NULL, OperandInfo121 }, // Inst #873 = Int_CVTSD2SI64rr
+ { 874, 6, 1, 0, "Int_CVTSD2SIrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(45<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #874 = Int_CVTSD2SIrm
+ { 875, 2, 1, 0, "Int_CVTSD2SIrr", 0, 0|5|(11<<8)|(45<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #875 = Int_CVTSD2SIrr
+ { 876, 7, 1, 0, "Int_CVTSD2SSrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(90<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #876 = Int_CVTSD2SSrm
+ { 877, 3, 1, 0, "Int_CVTSD2SSrr", 0, 0|5|(11<<8)|(90<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #877 = Int_CVTSD2SSrr
+ { 878, 7, 1, 0, "Int_CVTSI2SD64rm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<12)|(42<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #878 = Int_CVTSI2SD64rm
+ { 879, 3, 1, 0, "Int_CVTSI2SD64rr", 0, 0|5|(11<<8)|(1<<12)|(42<<24), NULL, NULL, NULL, OperandInfo123 }, // Inst #879 = Int_CVTSI2SD64rr
+ { 880, 7, 1, 0, "Int_CVTSI2SDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(42<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #880 = Int_CVTSI2SDrm
+ { 881, 3, 1, 0, "Int_CVTSI2SDrr", 0, 0|5|(11<<8)|(42<<24), NULL, NULL, NULL, OperandInfo124 }, // Inst #881 = Int_CVTSI2SDrr
+ { 882, 7, 1, 0, "Int_CVTSI2SS64rm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<12)|(42<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #882 = Int_CVTSI2SS64rm
+ { 883, 3, 1, 0, "Int_CVTSI2SS64rr", 0, 0|5|(12<<8)|(1<<12)|(42<<24), NULL, NULL, NULL, OperandInfo123 }, // Inst #883 = Int_CVTSI2SS64rr
+ { 884, 7, 1, 0, "Int_CVTSI2SSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(42<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #884 = Int_CVTSI2SSrm
+ { 885, 3, 1, 0, "Int_CVTSI2SSrr", 0, 0|5|(12<<8)|(42<<24), NULL, NULL, NULL, OperandInfo124 }, // Inst #885 = Int_CVTSI2SSrr
+ { 886, 7, 1, 0, "Int_CVTSS2SDrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(90<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #886 = Int_CVTSS2SDrm
+ { 887, 3, 1, 0, "Int_CVTSS2SDrr", 0, 0|5|(12<<8)|(90<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #887 = Int_CVTSS2SDrr
+ { 888, 6, 1, 0, "Int_CVTSS2SI64rm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<12)|(45<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #888 = Int_CVTSS2SI64rm
+ { 889, 2, 1, 0, "Int_CVTSS2SI64rr", 0, 0|5|(12<<8)|(1<<12)|(45<<24), NULL, NULL, NULL, OperandInfo121 }, // Inst #889 = Int_CVTSS2SI64rr
+ { 890, 6, 1, 0, "Int_CVTSS2SIrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(45<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #890 = Int_CVTSS2SIrm
+ { 891, 2, 1, 0, "Int_CVTSS2SIrr", 0, 0|5|(12<<8)|(45<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #891 = Int_CVTSS2SIrr
+ { 892, 6, 1, 0, "Int_CVTTPD2DQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(230<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #892 = Int_CVTTPD2DQrm
+ { 893, 2, 1, 0, "Int_CVTTPD2DQrr", 0, 0|5|(1<<6)|(1<<8)|(230<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #893 = Int_CVTTPD2DQrr
+ { 894, 6, 1, 0, "Int_CVTTPD2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #894 = Int_CVTTPD2PIrm
+ { 895, 2, 1, 0, "Int_CVTTPD2PIrr", 0, 0|5|(1<<6)|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #895 = Int_CVTTPD2PIrr
+ { 896, 6, 1, 0, "Int_CVTTPS2DQrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(91<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #896 = Int_CVTTPS2DQrm
+ { 897, 2, 1, 0, "Int_CVTTPS2DQrr", 0, 0|5|(12<<8)|(91<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #897 = Int_CVTTPS2DQrr
+ { 898, 6, 1, 0, "Int_CVTTPS2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #898 = Int_CVTTPS2PIrm
+ { 899, 2, 1, 0, "Int_CVTTPS2PIrr", 0, 0|5|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #899 = Int_CVTTPS2PIrr
+ { 900, 6, 1, 0, "Int_CVTTSD2SI64rm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<12)|(44<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #900 = Int_CVTTSD2SI64rm
+ { 901, 2, 1, 0, "Int_CVTTSD2SI64rr", 0, 0|5|(11<<8)|(1<<12)|(44<<24), NULL, NULL, NULL, OperandInfo121 }, // Inst #901 = Int_CVTTSD2SI64rr
+ { 902, 6, 1, 0, "Int_CVTTSD2SIrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(44<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #902 = Int_CVTTSD2SIrm
+ { 903, 2, 1, 0, "Int_CVTTSD2SIrr", 0, 0|5|(11<<8)|(44<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #903 = Int_CVTTSD2SIrr
+ { 904, 6, 1, 0, "Int_CVTTSS2SI64rm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<12)|(44<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #904 = Int_CVTTSS2SI64rm
+ { 905, 2, 1, 0, "Int_CVTTSS2SI64rr", 0, 0|5|(12<<8)|(1<<12)|(44<<24), NULL, NULL, NULL, OperandInfo121 }, // Inst #905 = Int_CVTTSS2SI64rr
+ { 906, 6, 1, 0, "Int_CVTTSS2SIrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(44<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #906 = Int_CVTTSS2SIrm
+ { 907, 2, 1, 0, "Int_CVTTSS2SIrr", 0, 0|5|(12<<8)|(44<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #907 = Int_CVTTSS2SIrr
+ { 908, 6, 0, 0, "Int_UCOMISDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo74 }, // Inst #908 = Int_UCOMISDrm
+ { 909, 2, 0, 0, "Int_UCOMISDrr", 0, 0|5|(1<<6)|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo75 }, // Inst #909 = Int_UCOMISDrr
+ { 910, 6, 0, 0, "Int_UCOMISSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo74 }, // Inst #910 = Int_UCOMISSrm
+ { 911, 2, 0, 0, "Int_UCOMISSrr", 0, 0|5|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo75 }, // Inst #911 = Int_UCOMISSrr
+ { 912, 1, 0, 0, "JAE_1", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(2<<13)|(115<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #912 = JAE_1
+ { 913, 1, 0, 0, "JAE_4", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(5<<13)|(131<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #913 = JAE_4
+ { 914, 1, 0, 0, "JA_1", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(2<<13)|(119<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #914 = JA_1
+ { 915, 1, 0, 0, "JA_4", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(5<<13)|(135<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #915 = JA_4
+ { 916, 1, 0, 0, "JBE_1", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(2<<13)|(118<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #916 = JBE_1
+ { 917, 1, 0, 0, "JBE_4", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(5<<13)|(134<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #917 = JBE_4
+ { 918, 1, 0, 0, "JB_1", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(2<<13)|(114<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #918 = JB_1
+ { 919, 1, 0, 0, "JB_4", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(5<<13)|(130<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #919 = JB_4
+ { 920, 1, 0, 0, "JCXZ8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(2<<13)|(227<<24), ImplicitList27, NULL, NULL, OperandInfo5 }, // Inst #920 = JCXZ8
+ { 921, 1, 0, 0, "JE_1", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(2<<13)|(116<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #921 = JE_1
+ { 922, 1, 0, 0, "JE_4", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(5<<13)|(132<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #922 = JE_4
+ { 923, 1, 0, 0, "JGE_1", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(2<<13)|(125<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #923 = JGE_1
+ { 924, 1, 0, 0, "JGE_4", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(5<<13)|(141<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #924 = JGE_4
+ { 925, 1, 0, 0, "JG_1", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(2<<13)|(127<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #925 = JG_1
+ { 926, 1, 0, 0, "JG_4", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(5<<13)|(143<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #926 = JG_4
+ { 927, 1, 0, 0, "JLE_1", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(2<<13)|(126<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #927 = JLE_1
+ { 928, 1, 0, 0, "JLE_4", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(5<<13)|(142<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #928 = JLE_4
+ { 929, 1, 0, 0, "JL_1", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(2<<13)|(124<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #929 = JL_1
+ { 930, 1, 0, 0, "JL_4", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(5<<13)|(140<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #930 = JL_4
+ { 931, 5, 0, 0, "JMP32m", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::Terminator), 0|28|(255<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #931 = JMP32m
+ { 932, 1, 0, 0, "JMP32r", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|20|(255<<24), NULL, NULL, NULL, OperandInfo57 }, // Inst #932 = JMP32r
+ { 933, 5, 0, 0, "JMP64m", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::Terminator), 0|28|(255<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #933 = JMP64m
+ { 934, 1, 0, 0, "JMP64pcrel32", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(233<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #934 = JMP64pcrel32
+ { 935, 1, 0, 0, "JMP64r", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|20|(255<<24), NULL, NULL, NULL, OperandInfo58 }, // Inst #935 = JMP64r
+ { 936, 1, 0, 0, "JMP_1", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(2<<13)|(235<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #936 = JMP_1
+ { 937, 1, 0, 0, "JMP_4", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|1|(5<<13)|(233<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #937 = JMP_4
+ { 938, 1, 0, 0, "JNE_1", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(2<<13)|(117<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #938 = JNE_1
+ { 939, 1, 0, 0, "JNE_4", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(5<<13)|(133<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #939 = JNE_4
+ { 940, 1, 0, 0, "JNO_1", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(2<<13)|(113<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #940 = JNO_1
+ { 941, 1, 0, 0, "JNO_4", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(5<<13)|(129<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #941 = JNO_4
+ { 942, 1, 0, 0, "JNP_1", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(2<<13)|(123<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #942 = JNP_1
+ { 943, 1, 0, 0, "JNP_4", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(5<<13)|(139<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #943 = JNP_4
+ { 944, 1, 0, 0, "JNS_1", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(2<<13)|(121<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #944 = JNS_1
+ { 945, 1, 0, 0, "JNS_4", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(5<<13)|(137<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #945 = JNS_4
+ { 946, 1, 0, 0, "JO_1", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(2<<13)|(112<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #946 = JO_1
+ { 947, 1, 0, 0, "JO_4", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(5<<13)|(128<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #947 = JO_4
+ { 948, 1, 0, 0, "JP_1", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(2<<13)|(122<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #948 = JP_1
+ { 949, 1, 0, 0, "JP_4", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(5<<13)|(138<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #949 = JP_4
+ { 950, 1, 0, 0, "JS_1", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(2<<13)|(120<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #950 = JS_1
+ { 951, 1, 0, 0, "JS_4", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(5<<13)|(136<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #951 = JS_4
+ { 952, 0, 0, 0, "LAHF", 0, 0|1|(159<<24), ImplicitList1, ImplicitList28, NULL, 0 }, // Inst #952 = LAHF
+ { 953, 6, 1, 0, "LAR16rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(2<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #953 = LAR16rm
+ { 954, 2, 1, 0, "LAR16rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(2<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #954 = LAR16rr
+ { 955, 6, 1, 0, "LAR32rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(2<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #955 = LAR32rm
+ { 956, 2, 1, 0, "LAR32rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(2<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #956 = LAR32rr
+ { 957, 6, 1, 0, "LAR64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(1<<12)|(2<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #957 = LAR64rm
+ { 958, 2, 1, 0, "LAR64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(1<<12)|(2<<24), NULL, NULL, NULL, OperandInfo125 }, // Inst #958 = LAR64rr
+ { 959, 6, 0, 0, "LCMPXCHG16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(1<<19)|(177<<24), ImplicitList12, ImplicitList29, Barriers1, OperandInfo7 }, // Inst #959 = LCMPXCHG16
+ { 960, 6, 0, 0, "LCMPXCHG32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<19)|(177<<24), ImplicitList13, ImplicitList30, Barriers1, OperandInfo11 }, // Inst #960 = LCMPXCHG32
+ { 961, 6, 0, 0, "LCMPXCHG64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<12)|(1<<19)|(177<<24), ImplicitList15, ImplicitList31, Barriers1, OperandInfo15 }, // Inst #961 = LCMPXCHG64
+ { 962, 6, 0, 0, "LCMPXCHG8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<19)|(176<<24), ImplicitList11, ImplicitList32, Barriers1, OperandInfo20 }, // Inst #962 = LCMPXCHG8
+ { 963, 5, 0, 0, "LCMPXCHG8B", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<8)|(1<<19)|(199<<24), ImplicitList6, ImplicitList18, Barriers6, OperandInfo30 }, // Inst #963 = LCMPXCHG8B
+ { 964, 6, 1, 0, "LDDQUrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(240<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #964 = LDDQUrm
+ { 965, 5, 0, 0, "LDMXCSR", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|26|(1<<8)|(174<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #965 = LDMXCSR
+ { 966, 6, 1, 0, "LDS16rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(197<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #966 = LDS16rm
+ { 967, 6, 1, 0, "LDS32rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(197<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #967 = LDS32rm
+ { 968, 0, 0, 0, "LD_F0", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(238<<24), NULL, NULL, NULL, 0 }, // Inst #968 = LD_F0
+ { 969, 0, 0, 0, "LD_F1", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(232<<24), NULL, NULL, NULL, 0 }, // Inst #969 = LD_F1
+ { 970, 5, 0, 0, "LD_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|24|(217<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #970 = LD_F32m
+ { 971, 5, 0, 0, "LD_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|24|(221<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #971 = LD_F64m
+ { 972, 5, 0, 0, "LD_F80m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(219<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #972 = LD_F80m
+ { 973, 1, 1, 0, "LD_Fp032", 0|(1<<TID::Rematerializable), 0|(1<<16), NULL, NULL, NULL, OperandInfo100 }, // Inst #973 = LD_Fp032
+ { 974, 1, 1, 0, "LD_Fp064", 0|(1<<TID::Rematerializable), 0|(1<<16), NULL, NULL, NULL, OperandInfo101 }, // Inst #974 = LD_Fp064
+ { 975, 1, 1, 0, "LD_Fp080", 0|(1<<TID::Rematerializable), 0|(1<<16), NULL, NULL, NULL, OperandInfo102 }, // Inst #975 = LD_Fp080
+ { 976, 1, 1, 0, "LD_Fp132", 0|(1<<TID::Rematerializable), 0|(1<<16), NULL, NULL, NULL, OperandInfo100 }, // Inst #976 = LD_Fp132
+ { 977, 1, 1, 0, "LD_Fp164", 0|(1<<TID::Rematerializable), 0|(1<<16), NULL, NULL, NULL, OperandInfo101 }, // Inst #977 = LD_Fp164
+ { 978, 1, 1, 0, "LD_Fp180", 0|(1<<TID::Rematerializable), 0|(1<<16), NULL, NULL, NULL, OperandInfo102 }, // Inst #978 = LD_Fp180
+ { 979, 6, 1, 0, "LD_Fp32m", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo107 }, // Inst #979 = LD_Fp32m
+ { 980, 6, 1, 0, "LD_Fp32m64", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo108 }, // Inst #980 = LD_Fp32m64
+ { 981, 6, 1, 0, "LD_Fp32m80", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo109 }, // Inst #981 = LD_Fp32m80
+ { 982, 6, 1, 0, "LD_Fp64m", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|(1<<16), NULL, NULL, NULL, OperandInfo108 }, // Inst #982 = LD_Fp64m
+ { 983, 6, 1, 0, "LD_Fp64m80", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo109 }, // Inst #983 = LD_Fp64m80
+ { 984, 6, 1, 0, "LD_Fp80m", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo109 }, // Inst #984 = LD_Fp80m
+ { 985, 1, 0, 0, "LD_Frr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(4<<8)|(192<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #985 = LD_Frr
+ { 986, 5, 1, 0, "LEA16r", 0, 0|6|(1<<6)|(141<<24), NULL, NULL, NULL, OperandInfo126 }, // Inst #986 = LEA16r
+ { 987, 5, 1, 0, "LEA32r", 0|(1<<TID::Rematerializable), 0|6|(141<<24), NULL, NULL, NULL, OperandInfo127 }, // Inst #987 = LEA32r
+ { 988, 5, 1, 0, "LEA64_32r", 0, 0|6|(141<<24), NULL, NULL, NULL, OperandInfo127 }, // Inst #988 = LEA64_32r
+ { 989, 5, 1, 0, "LEA64r", 0|(1<<TID::Rematerializable), 0|6|(1<<12)|(141<<24), NULL, NULL, NULL, OperandInfo128 }, // Inst #989 = LEA64r
+ { 990, 0, 0, 0, "LEAVE", 0|(1<<TID::MayLoad), 0|1|(201<<24), ImplicitList33, ImplicitList33, NULL, 0 }, // Inst #990 = LEAVE
+ { 991, 0, 0, 0, "LEAVE64", 0|(1<<TID::MayLoad), 0|1|(201<<24), ImplicitList34, ImplicitList34, NULL, 0 }, // Inst #991 = LEAVE64
+ { 992, 6, 1, 0, "LES16rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(196<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #992 = LES16rm
+ { 993, 6, 1, 0, "LES32rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(196<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #993 = LES32rm
+ { 994, 0, 0, 0, "LFENCE", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|39|(1<<8)|(174<<24), NULL, NULL, NULL, 0 }, // Inst #994 = LFENCE
+ { 995, 6, 1, 0, "LFS16rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(180<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #995 = LFS16rm
+ { 996, 6, 1, 0, "LFS32rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(180<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #996 = LFS32rm
+ { 997, 6, 1, 0, "LFS64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(1<<12)|(180<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #997 = LFS64rm
+ { 998, 5, 0, 0, "LGDTm", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #998 = LGDTm
+ { 999, 6, 1, 0, "LGS16rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(181<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #999 = LGS16rm
+ { 1000, 6, 1, 0, "LGS32rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(181<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1000 = LGS32rm
+ { 1001, 6, 1, 0, "LGS64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(1<<12)|(181<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1001 = LGS64rm
+ { 1002, 5, 0, 0, "LIDTm", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1002 = LIDTm
+ { 1003, 5, 0, 0, "LLDT16m", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<8), NULL, NULL, NULL, OperandInfo30 }, // Inst #1003 = LLDT16m
+ { 1004, 1, 0, 0, "LLDT16r", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<8), NULL, NULL, NULL, OperandInfo93 }, // Inst #1004 = LLDT16r
+ { 1005, 5, 0, 0, "LMSW16m", 0|(1<<TID::UnmodeledSideEffects), 0|30|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1005 = LMSW16m
+ { 1006, 1, 0, 0, "LMSW16r", 0|(1<<TID::UnmodeledSideEffects), 0|22|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo93 }, // Inst #1006 = LMSW16r
+ { 1007, 6, 0, 0, "LOCK_ADD16mi", 0|(1<<TID::UnmodeledSideEffects), 0|24|(3<<13)|(1<<19)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1007 = LOCK_ADD16mi
+ { 1008, 6, 0, 0, "LOCK_ADD16mi8", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<6)|(1<<13)|(1<<19)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1008 = LOCK_ADD16mi8
+ { 1009, 6, 0, 0, "LOCK_ADD16mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<19)|(1<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #1009 = LOCK_ADD16mr
+ { 1010, 6, 0, 0, "LOCK_ADD32mi", 0|(1<<TID::UnmodeledSideEffects), 0|24|(4<<13)|(1<<19)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1010 = LOCK_ADD32mi
+ { 1011, 6, 0, 0, "LOCK_ADD32mi8", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<13)|(1<<19)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1011 = LOCK_ADD32mi8
+ { 1012, 6, 0, 0, "LOCK_ADD32mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<19)|(1<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #1012 = LOCK_ADD32mr
+ { 1013, 6, 0, 0, "LOCK_ADD64mi32", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<12)|(4<<13)|(1<<19)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1013 = LOCK_ADD64mi32
+ { 1014, 6, 0, 0, "LOCK_ADD64mi8", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<12)|(1<<13)|(1<<19)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1014 = LOCK_ADD64mi8
+ { 1015, 6, 0, 0, "LOCK_ADD64mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<12)|(1<<19)|(3<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #1015 = LOCK_ADD64mr
+ { 1016, 6, 0, 0, "LOCK_ADD8mi", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<13)|(1<<19)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1016 = LOCK_ADD8mi
+ { 1017, 6, 0, 0, "LOCK_ADD8mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<19), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #1017 = LOCK_ADD8mr
+ { 1018, 5, 0, 0, "LOCK_DEC16m", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<6)|(1<<19)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1018 = LOCK_DEC16m
+ { 1019, 5, 0, 0, "LOCK_DEC32m", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<19)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1019 = LOCK_DEC32m
+ { 1020, 5, 0, 0, "LOCK_DEC64m", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<12)|(1<<19)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1020 = LOCK_DEC64m
+ { 1021, 5, 0, 0, "LOCK_DEC8m", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<19)|(254<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1021 = LOCK_DEC8m
+ { 1022, 5, 0, 0, "LOCK_INC16m", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<6)|(1<<19)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1022 = LOCK_INC16m
+ { 1023, 5, 0, 0, "LOCK_INC32m", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<19)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1023 = LOCK_INC32m
+ { 1024, 5, 0, 0, "LOCK_INC64m", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<12)|(1<<19)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1024 = LOCK_INC64m
+ { 1025, 5, 0, 0, "LOCK_INC8m", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<19)|(254<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1025 = LOCK_INC8m
+ { 1026, 0, 0, 0, "LOCK_PREFIX", 0|(1<<TID::UnmodeledSideEffects), 0|1|(240<<24), NULL, NULL, NULL, 0 }, // Inst #1026 = LOCK_PREFIX
+ { 1027, 6, 0, 0, "LOCK_SUB16mi", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<6)|(3<<13)|(1<<19)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1027 = LOCK_SUB16mi
+ { 1028, 6, 0, 0, "LOCK_SUB16mi8", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<6)|(1<<13)|(1<<19)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1028 = LOCK_SUB16mi8
+ { 1029, 6, 0, 0, "LOCK_SUB16mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<19)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #1029 = LOCK_SUB16mr
+ { 1030, 6, 0, 0, "LOCK_SUB32mi", 0|(1<<TID::UnmodeledSideEffects), 0|29|(4<<13)|(1<<19)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1030 = LOCK_SUB32mi
+ { 1031, 6, 0, 0, "LOCK_SUB32mi8", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<13)|(1<<19)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1031 = LOCK_SUB32mi8
+ { 1032, 6, 0, 0, "LOCK_SUB32mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<19)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #1032 = LOCK_SUB32mr
+ { 1033, 6, 0, 0, "LOCK_SUB64mi32", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<12)|(4<<13)|(1<<19)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1033 = LOCK_SUB64mi32
+ { 1034, 6, 0, 0, "LOCK_SUB64mi8", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<12)|(1<<13)|(1<<19)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1034 = LOCK_SUB64mi8
+ { 1035, 6, 0, 0, "LOCK_SUB64mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<12)|(1<<19)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #1035 = LOCK_SUB64mr
+ { 1036, 6, 0, 0, "LOCK_SUB8mi", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<13)|(1<<19)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1036 = LOCK_SUB8mi
+ { 1037, 6, 0, 0, "LOCK_SUB8mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<19)|(40<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #1037 = LOCK_SUB8mr
+ { 1038, 0, 0, 0, "LODSB", 0|(1<<TID::UnmodeledSideEffects), 0|1|(172<<24), NULL, NULL, NULL, 0 }, // Inst #1038 = LODSB
+ { 1039, 0, 0, 0, "LODSD", 0|(1<<TID::UnmodeledSideEffects), 0|1|(173<<24), NULL, NULL, NULL, 0 }, // Inst #1039 = LODSD
+ { 1040, 0, 0, 0, "LODSQ", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(173<<24), NULL, NULL, NULL, 0 }, // Inst #1040 = LODSQ
+ { 1041, 0, 0, 0, "LODSW", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(173<<24), NULL, NULL, NULL, 0 }, // Inst #1041 = LODSW
+ { 1042, 1, 1, 0, "LOOP", 0|(1<<TID::UnmodeledSideEffects), 0|1|(226<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1042 = LOOP
+ { 1043, 1, 1, 0, "LOOPE", 0|(1<<TID::UnmodeledSideEffects), 0|1|(225<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1043 = LOOPE
+ { 1044, 1, 1, 0, "LOOPNE", 0|(1<<TID::UnmodeledSideEffects), 0|1|(224<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1044 = LOOPNE
+ { 1045, 0, 0, 0, "LRET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(7<<16)|(203<<24), NULL, NULL, NULL, 0 }, // Inst #1045 = LRET
+ { 1046, 1, 0, 0, "LRETI", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(7<<16)|(202<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1046 = LRETI
+ { 1047, 6, 1, 0, "LSL16rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(3<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1047 = LSL16rm
+ { 1048, 2, 1, 0, "LSL16rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(3<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #1048 = LSL16rr
+ { 1049, 6, 1, 0, "LSL32rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(3<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1049 = LSL32rm
+ { 1050, 2, 1, 0, "LSL32rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(3<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #1050 = LSL32rr
+ { 1051, 6, 1, 0, "LSL64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(1<<12)|(3<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1051 = LSL64rm
+ { 1052, 2, 1, 0, "LSL64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(1<<12)|(3<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #1052 = LSL64rr
+ { 1053, 6, 1, 0, "LSS16rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(178<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1053 = LSS16rm
+ { 1054, 6, 1, 0, "LSS32rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(178<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1054 = LSS32rm
+ { 1055, 6, 1, 0, "LSS64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(1<<12)|(178<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1055 = LSS64rm
+ { 1056, 5, 0, 0, "LTRm", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<8), NULL, NULL, NULL, OperandInfo30 }, // Inst #1056 = LTRm
+ { 1057, 1, 0, 0, "LTRr", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<8), NULL, NULL, NULL, OperandInfo93 }, // Inst #1057 = LTRr
+ { 1058, 7, 1, 0, "LXADD16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(1<<6)|(1<<8)|(1<<19)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #1058 = LXADD16
+ { 1059, 7, 1, 0, "LXADD32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(1<<8)|(1<<19)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #1059 = LXADD32
+ { 1060, 7, 1, 0, "LXADD64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(1<<8)|(1<<12)|(1<<19)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #1060 = LXADD64
+ { 1061, 7, 1, 0, "LXADD8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(1<<8)|(1<<19)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #1061 = LXADD8
+ { 1062, 2, 0, 0, "MASKMOVDQU", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(247<<24), ImplicitList35, NULL, NULL, OperandInfo75 }, // Inst #1062 = MASKMOVDQU
+ { 1063, 2, 0, 0, "MASKMOVDQU64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(247<<24), ImplicitList36, NULL, NULL, OperandInfo75 }, // Inst #1063 = MASKMOVDQU64
+ { 1064, 7, 1, 0, "MAXPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(95<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1064 = MAXPDrm
+ { 1065, 7, 1, 0, "MAXPDrm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(95<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1065 = MAXPDrm_Int
+ { 1066, 3, 1, 0, "MAXPDrr", 0, 0|5|(1<<6)|(1<<8)|(95<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1066 = MAXPDrr
+ { 1067, 3, 1, 0, "MAXPDrr_Int", 0, 0|5|(1<<6)|(1<<8)|(95<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1067 = MAXPDrr_Int
+ { 1068, 7, 1, 0, "MAXPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(95<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1068 = MAXPSrm
+ { 1069, 7, 1, 0, "MAXPSrm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(95<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1069 = MAXPSrm_Int
+ { 1070, 3, 1, 0, "MAXPSrr", 0, 0|5|(1<<8)|(95<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1070 = MAXPSrr
+ { 1071, 3, 1, 0, "MAXPSrr_Int", 0, 0|5|(1<<8)|(95<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1071 = MAXPSrr_Int
+ { 1072, 7, 1, 0, "MAXSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(95<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #1072 = MAXSDrm
+ { 1073, 7, 1, 0, "MAXSDrm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(95<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1073 = MAXSDrm_Int
+ { 1074, 3, 1, 0, "MAXSDrr", 0, 0|5|(11<<8)|(95<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #1074 = MAXSDrr
+ { 1075, 3, 1, 0, "MAXSDrr_Int", 0, 0|5|(11<<8)|(95<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1075 = MAXSDrr_Int
+ { 1076, 7, 1, 0, "MAXSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(95<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #1076 = MAXSSrm
+ { 1077, 7, 1, 0, "MAXSSrm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(95<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1077 = MAXSSrm_Int
+ { 1078, 3, 1, 0, "MAXSSrr", 0, 0|5|(12<<8)|(95<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #1078 = MAXSSrr
+ { 1079, 3, 1, 0, "MAXSSrr_Int", 0, 0|5|(12<<8)|(95<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1079 = MAXSSrr_Int
+ { 1080, 0, 0, 0, "MFENCE", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|40|(1<<8)|(174<<24), NULL, NULL, NULL, 0 }, // Inst #1080 = MFENCE
+ { 1081, 7, 1, 0, "MINPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1081 = MINPDrm
+ { 1082, 7, 1, 0, "MINPDrm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1082 = MINPDrm_Int
+ { 1083, 3, 1, 0, "MINPDrr", 0, 0|5|(1<<6)|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1083 = MINPDrr
+ { 1084, 3, 1, 0, "MINPDrr_Int", 0, 0|5|(1<<6)|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1084 = MINPDrr_Int
+ { 1085, 7, 1, 0, "MINPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1085 = MINPSrm
+ { 1086, 7, 1, 0, "MINPSrm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1086 = MINPSrm_Int
+ { 1087, 3, 1, 0, "MINPSrr", 0, 0|5|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1087 = MINPSrr
+ { 1088, 3, 1, 0, "MINPSrr_Int", 0, 0|5|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1088 = MINPSrr_Int
+ { 1089, 7, 1, 0, "MINSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(93<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #1089 = MINSDrm
+ { 1090, 7, 1, 0, "MINSDrm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(93<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1090 = MINSDrm_Int
+ { 1091, 3, 1, 0, "MINSDrr", 0, 0|5|(11<<8)|(93<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #1091 = MINSDrr
+ { 1092, 3, 1, 0, "MINSDrr_Int", 0, 0|5|(11<<8)|(93<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1092 = MINSDrr_Int
+ { 1093, 7, 1, 0, "MINSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(93<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #1093 = MINSSrm
+ { 1094, 7, 1, 0, "MINSSrm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(93<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1094 = MINSSrm_Int
+ { 1095, 3, 1, 0, "MINSSrr", 0, 0|5|(12<<8)|(93<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #1095 = MINSSrr
+ { 1096, 3, 1, 0, "MINSSrr_Int", 0, 0|5|(12<<8)|(93<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1096 = MINSSrr_Int
+ { 1097, 6, 1, 0, "MMX_CVTPD2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1097 = MMX_CVTPD2PIrm
+ { 1098, 2, 1, 0, "MMX_CVTPD2PIrr", 0, 0|5|(1<<6)|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #1098 = MMX_CVTPD2PIrr
+ { 1099, 6, 1, 0, "MMX_CVTPI2PDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1099 = MMX_CVTPI2PDrm
+ { 1100, 2, 1, 0, "MMX_CVTPI2PDrr", 0, 0|5|(1<<6)|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo119 }, // Inst #1100 = MMX_CVTPI2PDrr
+ { 1101, 6, 1, 0, "MMX_CVTPI2PSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1101 = MMX_CVTPI2PSrm
+ { 1102, 2, 1, 0, "MMX_CVTPI2PSrr", 0, 0|5|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo119 }, // Inst #1102 = MMX_CVTPI2PSrr
+ { 1103, 6, 1, 0, "MMX_CVTPS2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1103 = MMX_CVTPS2PIrm
+ { 1104, 2, 1, 0, "MMX_CVTPS2PIrr", 0, 0|5|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #1104 = MMX_CVTPS2PIrr
+ { 1105, 6, 1, 0, "MMX_CVTTPD2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1105 = MMX_CVTTPD2PIrm
+ { 1106, 2, 1, 0, "MMX_CVTTPD2PIrr", 0, 0|5|(1<<6)|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #1106 = MMX_CVTTPD2PIrr
+ { 1107, 6, 1, 0, "MMX_CVTTPS2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1107 = MMX_CVTTPS2PIrm
+ { 1108, 2, 1, 0, "MMX_CVTTPS2PIrr", 0, 0|5|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #1108 = MMX_CVTTPS2PIrr
+ { 1109, 0, 0, 0, "MMX_EMMS", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(119<<24), NULL, NULL, NULL, 0 }, // Inst #1109 = MMX_EMMS
+ { 1110, 0, 0, 0, "MMX_FEMMS", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(14<<24), NULL, NULL, NULL, 0 }, // Inst #1110 = MMX_FEMMS
+ { 1111, 2, 0, 0, "MMX_MASKMOVQ", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(247<<24), ImplicitList35, NULL, NULL, OperandInfo129 }, // Inst #1111 = MMX_MASKMOVQ
+ { 1112, 2, 0, 0, "MMX_MASKMOVQ64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(247<<24), ImplicitList36, NULL, NULL, OperandInfo129 }, // Inst #1112 = MMX_MASKMOVQ64
+ { 1113, 2, 1, 0, "MMX_MOVD64from64rr", 0, 0|3|(1<<8)|(1<<12)|(126<<24), NULL, NULL, NULL, OperandInfo130 }, // Inst #1113 = MMX_MOVD64from64rr
+ { 1114, 2, 0, 0, "MMX_MOVD64grr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(126<<24), NULL, NULL, NULL, OperandInfo131 }, // Inst #1114 = MMX_MOVD64grr
+ { 1115, 6, 0, 0, "MMX_MOVD64mr", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(126<<24), NULL, NULL, NULL, OperandInfo132 }, // Inst #1115 = MMX_MOVD64mr
+ { 1116, 6, 1, 0, "MMX_MOVD64rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1116 = MMX_MOVD64rm
+ { 1117, 2, 1, 0, "MMX_MOVD64rr", 0, 0|5|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo133 }, // Inst #1117 = MMX_MOVD64rr
+ { 1118, 2, 1, 0, "MMX_MOVD64rrv164", 0, 0|5|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1118 = MMX_MOVD64rrv164
+ { 1119, 2, 1, 0, "MMX_MOVD64to64rr", 0, 0|5|(1<<8)|(1<<12)|(110<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1119 = MMX_MOVD64to64rr
+ { 1120, 2, 1, 0, "MMX_MOVDQ2Qrr", 0, 0|5|(11<<8)|(1<<13)|(214<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #1120 = MMX_MOVDQ2Qrr
+ { 1121, 6, 0, 0, "MMX_MOVNTQmr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(231<<24), NULL, NULL, NULL, OperandInfo132 }, // Inst #1121 = MMX_MOVNTQmr
+ { 1122, 2, 1, 0, "MMX_MOVQ2DQrr", 0, 0|5|(12<<8)|(1<<13)|(214<<24), NULL, NULL, NULL, OperandInfo119 }, // Inst #1122 = MMX_MOVQ2DQrr
+ { 1123, 2, 1, 0, "MMX_MOVQ2FR64rr", 0, 0|5|(12<<8)|(1<<13)|(214<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1123 = MMX_MOVQ2FR64rr
+ { 1124, 6, 0, 0, "MMX_MOVQ64gmr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(1<<12)|(126<<24), NULL, NULL, NULL, OperandInfo132 }, // Inst #1124 = MMX_MOVQ64gmr
+ { 1125, 6, 0, 0, "MMX_MOVQ64mr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(127<<24), NULL, NULL, NULL, OperandInfo132 }, // Inst #1125 = MMX_MOVQ64mr
+ { 1126, 6, 1, 0, "MMX_MOVQ64rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<8)|(111<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1126 = MMX_MOVQ64rm
+ { 1127, 2, 1, 0, "MMX_MOVQ64rr", 0, 0|5|(1<<8)|(111<<24), NULL, NULL, NULL, OperandInfo129 }, // Inst #1127 = MMX_MOVQ64rr
+ { 1128, 6, 1, 0, "MMX_MOVZDI2PDIrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1128 = MMX_MOVZDI2PDIrm
+ { 1129, 2, 1, 0, "MMX_MOVZDI2PDIrr", 0, 0|5|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo133 }, // Inst #1129 = MMX_MOVZDI2PDIrr
+ { 1130, 7, 1, 0, "MMX_PACKSSDWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(107<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1130 = MMX_PACKSSDWrm
+ { 1131, 3, 1, 0, "MMX_PACKSSDWrr", 0, 0|5|(1<<8)|(107<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1131 = MMX_PACKSSDWrr
+ { 1132, 7, 1, 0, "MMX_PACKSSWBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(99<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1132 = MMX_PACKSSWBrm
+ { 1133, 3, 1, 0, "MMX_PACKSSWBrr", 0, 0|5|(1<<8)|(99<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1133 = MMX_PACKSSWBrr
+ { 1134, 7, 1, 0, "MMX_PACKUSWBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(103<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1134 = MMX_PACKUSWBrm
+ { 1135, 3, 1, 0, "MMX_PACKUSWBrr", 0, 0|5|(1<<8)|(103<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1135 = MMX_PACKUSWBrr
+ { 1136, 7, 1, 0, "MMX_PADDBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(252<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1136 = MMX_PADDBrm
+ { 1137, 3, 1, 0, "MMX_PADDBrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(252<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1137 = MMX_PADDBrr
+ { 1138, 7, 1, 0, "MMX_PADDDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(254<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1138 = MMX_PADDDrm
+ { 1139, 3, 1, 0, "MMX_PADDDrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(254<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1139 = MMX_PADDDrr
+ { 1140, 7, 1, 0, "MMX_PADDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(212<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1140 = MMX_PADDQrm
+ { 1141, 3, 1, 0, "MMX_PADDQrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(212<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1141 = MMX_PADDQrr
+ { 1142, 7, 1, 0, "MMX_PADDSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(236<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1142 = MMX_PADDSBrm
+ { 1143, 3, 1, 0, "MMX_PADDSBrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(236<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1143 = MMX_PADDSBrr
+ { 1144, 7, 1, 0, "MMX_PADDSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(237<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1144 = MMX_PADDSWrm
+ { 1145, 3, 1, 0, "MMX_PADDSWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(237<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1145 = MMX_PADDSWrr
+ { 1146, 7, 1, 0, "MMX_PADDUSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(220<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1146 = MMX_PADDUSBrm
+ { 1147, 3, 1, 0, "MMX_PADDUSBrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(220<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1147 = MMX_PADDUSBrr
+ { 1148, 7, 1, 0, "MMX_PADDUSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(221<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1148 = MMX_PADDUSWrm
+ { 1149, 3, 1, 0, "MMX_PADDUSWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(221<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1149 = MMX_PADDUSWrr
+ { 1150, 7, 1, 0, "MMX_PADDWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(253<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1150 = MMX_PADDWrm
+ { 1151, 3, 1, 0, "MMX_PADDWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(253<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1151 = MMX_PADDWrr
+ { 1152, 7, 1, 0, "MMX_PANDNrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(223<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1152 = MMX_PANDNrm
+ { 1153, 3, 1, 0, "MMX_PANDNrr", 0, 0|5|(1<<8)|(223<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1153 = MMX_PANDNrr
+ { 1154, 7, 1, 0, "MMX_PANDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(219<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1154 = MMX_PANDrm
+ { 1155, 3, 1, 0, "MMX_PANDrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(219<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1155 = MMX_PANDrr
+ { 1156, 7, 1, 0, "MMX_PAVGBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(224<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1156 = MMX_PAVGBrm
+ { 1157, 3, 1, 0, "MMX_PAVGBrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(224<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1157 = MMX_PAVGBrr
+ { 1158, 7, 1, 0, "MMX_PAVGWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(227<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1158 = MMX_PAVGWrm
+ { 1159, 3, 1, 0, "MMX_PAVGWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(227<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1159 = MMX_PAVGWrr
+ { 1160, 7, 1, 0, "MMX_PCMPEQBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(116<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1160 = MMX_PCMPEQBrm
+ { 1161, 3, 1, 0, "MMX_PCMPEQBrr", 0, 0|5|(1<<8)|(116<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1161 = MMX_PCMPEQBrr
+ { 1162, 7, 1, 0, "MMX_PCMPEQDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1162 = MMX_PCMPEQDrm
+ { 1163, 3, 1, 0, "MMX_PCMPEQDrr", 0, 0|5|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1163 = MMX_PCMPEQDrr
+ { 1164, 7, 1, 0, "MMX_PCMPEQWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(117<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1164 = MMX_PCMPEQWrm
+ { 1165, 3, 1, 0, "MMX_PCMPEQWrr", 0, 0|5|(1<<8)|(117<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1165 = MMX_PCMPEQWrr
+ { 1166, 7, 1, 0, "MMX_PCMPGTBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(100<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1166 = MMX_PCMPGTBrm
+ { 1167, 3, 1, 0, "MMX_PCMPGTBrr", 0, 0|5|(1<<8)|(100<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1167 = MMX_PCMPGTBrr
+ { 1168, 7, 1, 0, "MMX_PCMPGTDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(102<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1168 = MMX_PCMPGTDrm
+ { 1169, 3, 1, 0, "MMX_PCMPGTDrr", 0, 0|5|(1<<8)|(102<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1169 = MMX_PCMPGTDrr
+ { 1170, 7, 1, 0, "MMX_PCMPGTWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(101<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1170 = MMX_PCMPGTWrm
+ { 1171, 3, 1, 0, "MMX_PCMPGTWrr", 0, 0|5|(1<<8)|(101<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1171 = MMX_PCMPGTWrr
+ { 1172, 3, 1, 0, "MMX_PEXTRWri", 0, 0|5|(1<<8)|(1<<13)|(197<<24), NULL, NULL, NULL, OperandInfo138 }, // Inst #1172 = MMX_PEXTRWri
+ { 1173, 8, 1, 0, "MMX_PINSRWrmi", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<13)|(196<<24), NULL, NULL, NULL, OperandInfo139 }, // Inst #1173 = MMX_PINSRWrmi
+ { 1174, 4, 1, 0, "MMX_PINSRWrri", 0, 0|5|(1<<8)|(1<<13)|(196<<24), NULL, NULL, NULL, OperandInfo140 }, // Inst #1174 = MMX_PINSRWrri
+ { 1175, 7, 1, 0, "MMX_PMADDWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(245<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1175 = MMX_PMADDWDrm
+ { 1176, 3, 1, 0, "MMX_PMADDWDrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(245<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1176 = MMX_PMADDWDrr
+ { 1177, 7, 1, 0, "MMX_PMAXSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(238<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1177 = MMX_PMAXSWrm
+ { 1178, 3, 1, 0, "MMX_PMAXSWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(238<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1178 = MMX_PMAXSWrr
+ { 1179, 7, 1, 0, "MMX_PMAXUBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(222<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1179 = MMX_PMAXUBrm
+ { 1180, 3, 1, 0, "MMX_PMAXUBrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(222<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1180 = MMX_PMAXUBrr
+ { 1181, 7, 1, 0, "MMX_PMINSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(234<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1181 = MMX_PMINSWrm
+ { 1182, 3, 1, 0, "MMX_PMINSWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(234<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1182 = MMX_PMINSWrr
+ { 1183, 7, 1, 0, "MMX_PMINUBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(218<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1183 = MMX_PMINUBrm
+ { 1184, 3, 1, 0, "MMX_PMINUBrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(218<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1184 = MMX_PMINUBrr
+ { 1185, 2, 1, 0, "MMX_PMOVMSKBrr", 0, 0|5|(1<<8)|(215<<24), NULL, NULL, NULL, OperandInfo131 }, // Inst #1185 = MMX_PMOVMSKBrr
+ { 1186, 7, 1, 0, "MMX_PMULHUWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(228<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1186 = MMX_PMULHUWrm
+ { 1187, 3, 1, 0, "MMX_PMULHUWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(228<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1187 = MMX_PMULHUWrr
+ { 1188, 7, 1, 0, "MMX_PMULHWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(229<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1188 = MMX_PMULHWrm
+ { 1189, 3, 1, 0, "MMX_PMULHWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(229<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1189 = MMX_PMULHWrr
+ { 1190, 7, 1, 0, "MMX_PMULLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(213<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1190 = MMX_PMULLWrm
+ { 1191, 3, 1, 0, "MMX_PMULLWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(213<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1191 = MMX_PMULLWrr
+ { 1192, 7, 1, 0, "MMX_PMULUDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(244<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1192 = MMX_PMULUDQrm
+ { 1193, 3, 1, 0, "MMX_PMULUDQrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(244<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1193 = MMX_PMULUDQrr
+ { 1194, 7, 1, 0, "MMX_PORrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(235<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1194 = MMX_PORrm
+ { 1195, 3, 1, 0, "MMX_PORrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(235<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1195 = MMX_PORrr
+ { 1196, 7, 1, 0, "MMX_PSADBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(246<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1196 = MMX_PSADBWrm
+ { 1197, 3, 1, 0, "MMX_PSADBWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(246<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1197 = MMX_PSADBWrr
+ { 1198, 7, 1, 0, "MMX_PSHUFWmi", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo141 }, // Inst #1198 = MMX_PSHUFWmi
+ { 1199, 3, 1, 0, "MMX_PSHUFWri", 0, 0|5|(1<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo142 }, // Inst #1199 = MMX_PSHUFWri
+ { 1200, 3, 1, 0, "MMX_PSLLDri", 0, 0|22|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1200 = MMX_PSLLDri
+ { 1201, 7, 1, 0, "MMX_PSLLDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(242<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1201 = MMX_PSLLDrm
+ { 1202, 3, 1, 0, "MMX_PSLLDrr", 0, 0|5|(1<<8)|(242<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1202 = MMX_PSLLDrr
+ { 1203, 3, 1, 0, "MMX_PSLLQri", 0, 0|22|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1203 = MMX_PSLLQri
+ { 1204, 7, 1, 0, "MMX_PSLLQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(243<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1204 = MMX_PSLLQrm
+ { 1205, 3, 1, 0, "MMX_PSLLQrr", 0, 0|5|(1<<8)|(243<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1205 = MMX_PSLLQrr
+ { 1206, 3, 1, 0, "MMX_PSLLWri", 0, 0|22|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1206 = MMX_PSLLWri
+ { 1207, 7, 1, 0, "MMX_PSLLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(241<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1207 = MMX_PSLLWrm
+ { 1208, 3, 1, 0, "MMX_PSLLWrr", 0, 0|5|(1<<8)|(241<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1208 = MMX_PSLLWrr
+ { 1209, 3, 1, 0, "MMX_PSRADri", 0, 0|20|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1209 = MMX_PSRADri
+ { 1210, 7, 1, 0, "MMX_PSRADrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(226<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1210 = MMX_PSRADrm
+ { 1211, 3, 1, 0, "MMX_PSRADrr", 0, 0|5|(1<<8)|(226<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1211 = MMX_PSRADrr
+ { 1212, 3, 1, 0, "MMX_PSRAWri", 0, 0|20|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1212 = MMX_PSRAWri
+ { 1213, 7, 1, 0, "MMX_PSRAWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(225<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1213 = MMX_PSRAWrm
+ { 1214, 3, 1, 0, "MMX_PSRAWrr", 0, 0|5|(1<<8)|(225<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1214 = MMX_PSRAWrr
+ { 1215, 3, 1, 0, "MMX_PSRLDri", 0, 0|18|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1215 = MMX_PSRLDri
+ { 1216, 7, 1, 0, "MMX_PSRLDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(210<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1216 = MMX_PSRLDrm
+ { 1217, 3, 1, 0, "MMX_PSRLDrr", 0, 0|5|(1<<8)|(210<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1217 = MMX_PSRLDrr
+ { 1218, 3, 1, 0, "MMX_PSRLQri", 0, 0|18|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1218 = MMX_PSRLQri
+ { 1219, 7, 1, 0, "MMX_PSRLQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(211<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1219 = MMX_PSRLQrm
+ { 1220, 3, 1, 0, "MMX_PSRLQrr", 0, 0|5|(1<<8)|(211<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1220 = MMX_PSRLQrr
+ { 1221, 3, 1, 0, "MMX_PSRLWri", 0, 0|18|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1221 = MMX_PSRLWri
+ { 1222, 7, 1, 0, "MMX_PSRLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(209<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1222 = MMX_PSRLWrm
+ { 1223, 3, 1, 0, "MMX_PSRLWrr", 0, 0|5|(1<<8)|(209<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1223 = MMX_PSRLWrr
+ { 1224, 7, 1, 0, "MMX_PSUBBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(248<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1224 = MMX_PSUBBrm
+ { 1225, 3, 1, 0, "MMX_PSUBBrr", 0, 0|5|(1<<8)|(248<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1225 = MMX_PSUBBrr
+ { 1226, 7, 1, 0, "MMX_PSUBDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(250<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1226 = MMX_PSUBDrm
+ { 1227, 3, 1, 0, "MMX_PSUBDrr", 0, 0|5|(1<<8)|(250<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1227 = MMX_PSUBDrr
+ { 1228, 7, 1, 0, "MMX_PSUBQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(251<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1228 = MMX_PSUBQrm
+ { 1229, 3, 1, 0, "MMX_PSUBQrr", 0, 0|5|(1<<8)|(251<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1229 = MMX_PSUBQrr
+ { 1230, 7, 1, 0, "MMX_PSUBSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(232<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1230 = MMX_PSUBSBrm
+ { 1231, 3, 1, 0, "MMX_PSUBSBrr", 0, 0|5|(1<<8)|(232<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1231 = MMX_PSUBSBrr
+ { 1232, 7, 1, 0, "MMX_PSUBSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(233<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1232 = MMX_PSUBSWrm
+ { 1233, 3, 1, 0, "MMX_PSUBSWrr", 0, 0|5|(1<<8)|(233<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1233 = MMX_PSUBSWrr
+ { 1234, 7, 1, 0, "MMX_PSUBUSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(216<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1234 = MMX_PSUBUSBrm
+ { 1235, 3, 1, 0, "MMX_PSUBUSBrr", 0, 0|5|(1<<8)|(216<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1235 = MMX_PSUBUSBrr
+ { 1236, 7, 1, 0, "MMX_PSUBUSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(217<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1236 = MMX_PSUBUSWrm
+ { 1237, 3, 1, 0, "MMX_PSUBUSWrr", 0, 0|5|(1<<8)|(217<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1237 = MMX_PSUBUSWrr
+ { 1238, 7, 1, 0, "MMX_PSUBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(249<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1238 = MMX_PSUBWrm
+ { 1239, 3, 1, 0, "MMX_PSUBWrr", 0, 0|5|(1<<8)|(249<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1239 = MMX_PSUBWrr
+ { 1240, 7, 1, 0, "MMX_PUNPCKHBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(104<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1240 = MMX_PUNPCKHBWrm
+ { 1241, 3, 1, 0, "MMX_PUNPCKHBWrr", 0, 0|5|(1<<8)|(104<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1241 = MMX_PUNPCKHBWrr
+ { 1242, 7, 1, 0, "MMX_PUNPCKHDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(106<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1242 = MMX_PUNPCKHDQrm
+ { 1243, 3, 1, 0, "MMX_PUNPCKHDQrr", 0, 0|5|(1<<8)|(106<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1243 = MMX_PUNPCKHDQrr
+ { 1244, 7, 1, 0, "MMX_PUNPCKHWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(105<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1244 = MMX_PUNPCKHWDrm
+ { 1245, 3, 1, 0, "MMX_PUNPCKHWDrr", 0, 0|5|(1<<8)|(105<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1245 = MMX_PUNPCKHWDrr
+ { 1246, 7, 1, 0, "MMX_PUNPCKLBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(96<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1246 = MMX_PUNPCKLBWrm
+ { 1247, 3, 1, 0, "MMX_PUNPCKLBWrr", 0, 0|5|(1<<8)|(96<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1247 = MMX_PUNPCKLBWrr
+ { 1248, 7, 1, 0, "MMX_PUNPCKLDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(98<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1248 = MMX_PUNPCKLDQrm
+ { 1249, 3, 1, 0, "MMX_PUNPCKLDQrr", 0, 0|5|(1<<8)|(98<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1249 = MMX_PUNPCKLDQrr
+ { 1250, 7, 1, 0, "MMX_PUNPCKLWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(97<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1250 = MMX_PUNPCKLWDrm
+ { 1251, 3, 1, 0, "MMX_PUNPCKLWDrr", 0, 0|5|(1<<8)|(97<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1251 = MMX_PUNPCKLWDrr
+ { 1252, 7, 1, 0, "MMX_PXORrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1252 = MMX_PXORrm
+ { 1253, 3, 1, 0, "MMX_PXORrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1253 = MMX_PXORrr
+ { 1254, 1, 1, 0, "MMX_V_SET0", 0|(1<<TID::Rematerializable), 0|32|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo144 }, // Inst #1254 = MMX_V_SET0
+ { 1255, 1, 1, 0, "MMX_V_SETALLONES", 0|(1<<TID::Rematerializable), 0|32|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo144 }, // Inst #1255 = MMX_V_SETALLONES
+ { 1256, 0, 0, 0, "MONITOR", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|37|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #1256 = MONITOR
+ { 1257, 1, 1, 0, "MOV16ao16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(3<<13)|(163<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1257 = MOV16ao16
+ { 1258, 6, 0, 0, "MOV16mi", 0|(1<<TID::MayStore), 0|24|(1<<6)|(3<<13)|(199<<24), NULL, NULL, NULL, OperandInfo6 }, // Inst #1258 = MOV16mi
+ { 1259, 6, 0, 0, "MOV16mr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(137<<24), NULL, NULL, NULL, OperandInfo7 }, // Inst #1259 = MOV16mr
+ { 1260, 6, 1, 0, "MOV16ms", 0|(1<<TID::UnmodeledSideEffects), 0|4|(140<<24), NULL, NULL, NULL, OperandInfo145 }, // Inst #1260 = MOV16ms
+ { 1261, 1, 0, 0, "MOV16o16a", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(3<<13)|(161<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1261 = MOV16o16a
+ { 1262, 1, 1, 0, "MOV16r0", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(1<<6)|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo93 }, // Inst #1262 = MOV16r0
+ { 1263, 2, 1, 0, "MOV16ri", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|2|(1<<6)|(3<<13)|(184<<24), NULL, NULL, NULL, OperandInfo54 }, // Inst #1263 = MOV16ri
+ { 1264, 6, 1, 0, "MOV16rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<6)|(139<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1264 = MOV16rm
+ { 1265, 2, 1, 0, "MOV16rr", 0, 0|3|(1<<6)|(137<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #1265 = MOV16rr
+ { 1266, 2, 1, 0, "MOV16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(139<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #1266 = MOV16rr_REV
+ { 1267, 2, 1, 0, "MOV16rs", 0|(1<<TID::UnmodeledSideEffects), 0|3|(140<<24), NULL, NULL, NULL, OperandInfo146 }, // Inst #1267 = MOV16rs
+ { 1268, 6, 1, 0, "MOV16sm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(142<<24), NULL, NULL, NULL, OperandInfo147 }, // Inst #1268 = MOV16sm
+ { 1269, 2, 1, 0, "MOV16sr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(142<<24), NULL, NULL, NULL, OperandInfo148 }, // Inst #1269 = MOV16sr
+ { 1270, 1, 1, 0, "MOV32ao32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<13)|(163<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1270 = MOV32ao32
+ { 1271, 2, 1, 0, "MOV32cr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(34<<24), NULL, NULL, NULL, OperandInfo149 }, // Inst #1271 = MOV32cr
+ { 1272, 2, 1, 0, "MOV32dr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(35<<24), NULL, NULL, NULL, OperandInfo150 }, // Inst #1272 = MOV32dr
+ { 1273, 6, 0, 0, "MOV32mi", 0|(1<<TID::MayStore), 0|24|(4<<13)|(199<<24), NULL, NULL, NULL, OperandInfo6 }, // Inst #1273 = MOV32mi
+ { 1274, 6, 0, 0, "MOV32mr", 0|(1<<TID::MayStore), 0|4|(137<<24), NULL, NULL, NULL, OperandInfo11 }, // Inst #1274 = MOV32mr
+ { 1275, 1, 0, 0, "MOV32o32a", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<13)|(161<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1275 = MOV32o32a
+ { 1276, 1, 1, 0, "MOV32r0", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo57 }, // Inst #1276 = MOV32r0
+ { 1277, 2, 1, 0, "MOV32rc", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(32<<24), NULL, NULL, NULL, OperandInfo151 }, // Inst #1277 = MOV32rc
+ { 1278, 2, 1, 0, "MOV32rd", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(33<<24), NULL, NULL, NULL, OperandInfo152 }, // Inst #1278 = MOV32rd
+ { 1279, 2, 1, 0, "MOV32ri", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|2|(4<<13)|(184<<24), NULL, NULL, NULL, OperandInfo55 }, // Inst #1279 = MOV32ri
+ { 1280, 6, 1, 0, "MOV32rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(139<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1280 = MOV32rm
+ { 1281, 2, 1, 0, "MOV32rr", 0, 0|3|(137<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #1281 = MOV32rr
+ { 1282, 2, 1, 0, "MOV32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(139<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #1282 = MOV32rr_REV
+ { 1283, 6, 1, 0, "MOV64FSrm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(1<<20)|(139<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1283 = MOV64FSrm
+ { 1284, 6, 1, 0, "MOV64GSrm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(2<<20)|(139<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1284 = MOV64GSrm
+ { 1285, 1, 1, 0, "MOV64ao64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(4<<13)|(163<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1285 = MOV64ao64
+ { 1286, 1, 1, 0, "MOV64ao8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(1<<13)|(162<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1286 = MOV64ao8
+ { 1287, 2, 1, 0, "MOV64cr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(34<<24), NULL, NULL, NULL, OperandInfo153 }, // Inst #1287 = MOV64cr
+ { 1288, 2, 1, 0, "MOV64dr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(35<<24), NULL, NULL, NULL, OperandInfo154 }, // Inst #1288 = MOV64dr
+ { 1289, 6, 0, 0, "MOV64mi32", 0|(1<<TID::MayStore), 0|24|(1<<12)|(4<<13)|(199<<24), NULL, NULL, NULL, OperandInfo6 }, // Inst #1289 = MOV64mi32
+ { 1290, 6, 0, 0, "MOV64mr", 0|(1<<TID::MayStore), 0|4|(1<<12)|(137<<24), NULL, NULL, NULL, OperandInfo15 }, // Inst #1290 = MOV64mr
+ { 1291, 6, 1, 0, "MOV64ms", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<12)|(140<<24), NULL, NULL, NULL, OperandInfo145 }, // Inst #1291 = MOV64ms
+ { 1292, 1, 0, 0, "MOV64o64a", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(4<<13)|(161<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1292 = MOV64o64a
+ { 1293, 1, 0, 0, "MOV64o8a", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(1<<13)|(160<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1293 = MOV64o8a
+ { 1294, 1, 1, 0, "MOV64r0", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo58 }, // Inst #1294 = MOV64r0
+ { 1295, 2, 1, 0, "MOV64rc", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(32<<24), NULL, NULL, NULL, OperandInfo155 }, // Inst #1295 = MOV64rc
+ { 1296, 2, 1, 0, "MOV64rd", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(33<<24), NULL, NULL, NULL, OperandInfo156 }, // Inst #1296 = MOV64rd
+ { 1297, 2, 1, 0, "MOV64ri", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|2|(1<<12)|(6<<13)|(184<<24), NULL, NULL, NULL, OperandInfo56 }, // Inst #1297 = MOV64ri
+ { 1298, 2, 1, 0, "MOV64ri32", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|16|(1<<12)|(4<<13)|(199<<24), NULL, NULL, NULL, OperandInfo56 }, // Inst #1298 = MOV64ri32
+ { 1299, 2, 1, 0, "MOV64ri64i32", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|2|(4<<13)|(184<<24), NULL, NULL, NULL, OperandInfo56 }, // Inst #1299 = MOV64ri64i32
+ { 1300, 6, 1, 0, "MOV64rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<12)|(139<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1300 = MOV64rm
+ { 1301, 2, 1, 0, "MOV64rr", 0, 0|3|(1<<12)|(137<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #1301 = MOV64rr
+ { 1302, 2, 1, 0, "MOV64rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(139<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #1302 = MOV64rr_REV
+ { 1303, 2, 1, 0, "MOV64rs", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<12)|(140<<24), NULL, NULL, NULL, OperandInfo157 }, // Inst #1303 = MOV64rs
+ { 1304, 6, 1, 0, "MOV64sm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<12)|(142<<24), NULL, NULL, NULL, OperandInfo147 }, // Inst #1304 = MOV64sm
+ { 1305, 2, 1, 0, "MOV64sr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(142<<24), NULL, NULL, NULL, OperandInfo158 }, // Inst #1305 = MOV64sr
+ { 1306, 2, 1, 0, "MOV64toPQIrr", 0, 0|5|(1<<6)|(1<<8)|(1<<12)|(110<<24), NULL, NULL, NULL, OperandInfo159 }, // Inst #1306 = MOV64toPQIrr
+ { 1307, 6, 1, 0, "MOV64toSDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(1<<12)|(110<<24), NULL, NULL, NULL, OperandInfo82 }, // Inst #1307 = MOV64toSDrm
+ { 1308, 2, 1, 0, "MOV64toSDrr", 0, 0|5|(1<<6)|(1<<8)|(1<<12)|(110<<24), NULL, NULL, NULL, OperandInfo83 }, // Inst #1308 = MOV64toSDrr
+ { 1309, 1, 1, 0, "MOV8ao8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(162<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1309 = MOV8ao8
+ { 1310, 6, 0, 0, "MOV8mi", 0|(1<<TID::MayStore), 0|24|(1<<13)|(198<<24), NULL, NULL, NULL, OperandInfo6 }, // Inst #1310 = MOV8mi
+ { 1311, 6, 0, 0, "MOV8mr", 0|(1<<TID::MayStore), 0|4|(136<<24), NULL, NULL, NULL, OperandInfo20 }, // Inst #1311 = MOV8mr
+ { 1312, 6, 0, 0, "MOV8mr_NOREX", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(136<<24), NULL, NULL, NULL, OperandInfo160 }, // Inst #1312 = MOV8mr_NOREX
+ { 1313, 1, 0, 0, "MOV8o8a", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(160<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1313 = MOV8o8a
+ { 1314, 1, 1, 0, "MOV8r0", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(48<<24), NULL, ImplicitList1, Barriers1, OperandInfo94 }, // Inst #1314 = MOV8r0
+ { 1315, 2, 1, 0, "MOV8ri", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|2|(1<<13)|(176<<24), NULL, NULL, NULL, OperandInfo68 }, // Inst #1315 = MOV8ri
+ { 1316, 6, 1, 0, "MOV8rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(138<<24), NULL, NULL, NULL, OperandInfo69 }, // Inst #1316 = MOV8rm
+ { 1317, 6, 1, 0, "MOV8rm_NOREX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable)|(1<<TID::UnmodeledSideEffects), 0|6|(138<<24), NULL, NULL, NULL, OperandInfo161 }, // Inst #1317 = MOV8rm_NOREX
+ { 1318, 2, 1, 0, "MOV8rr", 0, 0|3|(136<<24), NULL, NULL, NULL, OperandInfo67 }, // Inst #1318 = MOV8rr
+ { 1319, 2, 1, 0, "MOV8rr_NOREX", 0, 0|3|(136<<24), NULL, NULL, NULL, OperandInfo162 }, // Inst #1319 = MOV8rr_NOREX
+ { 1320, 2, 1, 0, "MOV8rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(138<<24), NULL, NULL, NULL, OperandInfo67 }, // Inst #1320 = MOV8rr_REV
+ { 1321, 6, 0, 0, "MOVAPDmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(41<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1321 = MOVAPDmr
+ { 1322, 6, 1, 0, "MOVAPDrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<6)|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1322 = MOVAPDrm
+ { 1323, 2, 1, 0, "MOVAPDrr", 0, 0|5|(1<<6)|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1323 = MOVAPDrr
+ { 1324, 6, 0, 0, "MOVAPSmr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(41<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1324 = MOVAPSmr
+ { 1325, 6, 1, 0, "MOVAPSrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1325 = MOVAPSrm
+ { 1326, 2, 1, 0, "MOVAPSrr", 0, 0|5|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1326 = MOVAPSrr
+ { 1327, 6, 1, 0, "MOVDDUPrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(18<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1327 = MOVDDUPrm
+ { 1328, 2, 1, 0, "MOVDDUPrr", 0, 0|5|(11<<8)|(18<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1328 = MOVDDUPrr
+ { 1329, 6, 1, 0, "MOVDI2PDIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1329 = MOVDI2PDIrm
+ { 1330, 2, 1, 0, "MOVDI2PDIrr", 0, 0|5|(1<<6)|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo164 }, // Inst #1330 = MOVDI2PDIrr
+ { 1331, 6, 1, 0, "MOVDI2SSrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #1331 = MOVDI2SSrm
+ { 1332, 2, 1, 0, "MOVDI2SSrr", 0, 0|5|(1<<6)|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo86 }, // Inst #1332 = MOVDI2SSrr
+ { 1333, 6, 0, 0, "MOVDQAmr", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(127<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1333 = MOVDQAmr
+ { 1334, 6, 1, 0, "MOVDQArm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(111<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1334 = MOVDQArm
+ { 1335, 2, 1, 0, "MOVDQArr", 0, 0|5|(1<<6)|(1<<8)|(111<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1335 = MOVDQArr
+ { 1336, 6, 0, 0, "MOVDQUmr", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(12<<8)|(127<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1336 = MOVDQUmr
+ { 1337, 6, 0, 0, "MOVDQUmr_Int", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(12<<8)|(127<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1337 = MOVDQUmr_Int
+ { 1338, 6, 1, 0, "MOVDQUrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|6|(12<<8)|(111<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1338 = MOVDQUrm
+ { 1339, 6, 1, 0, "MOVDQUrm_Int", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|6|(12<<8)|(111<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1339 = MOVDQUrm_Int
+ { 1340, 3, 1, 0, "MOVHLPSrr", 0, 0|5|(1<<8)|(18<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1340 = MOVHLPSrr
+ { 1341, 6, 0, 0, "MOVHPDmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(23<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1341 = MOVHPDmr
+ { 1342, 7, 1, 0, "MOVHPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(22<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1342 = MOVHPDrm
+ { 1343, 6, 0, 0, "MOVHPSmr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(23<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1343 = MOVHPSmr
+ { 1344, 7, 1, 0, "MOVHPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(22<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1344 = MOVHPSrm
+ { 1345, 3, 1, 0, "MOVLHPSrr", 0, 0|5|(1<<8)|(22<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1345 = MOVLHPSrr
+ { 1346, 6, 0, 0, "MOVLPDmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(19<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1346 = MOVLPDmr
+ { 1347, 7, 1, 0, "MOVLPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(18<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1347 = MOVLPDrm
+ { 1348, 3, 1, 0, "MOVLPDrr", 0, 0|5|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1348 = MOVLPDrr
+ { 1349, 6, 0, 0, "MOVLPSmr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(19<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1349 = MOVLPSmr
+ { 1350, 7, 1, 0, "MOVLPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(18<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1350 = MOVLPSrm
+ { 1351, 3, 1, 0, "MOVLPSrr", 0, 0|5|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1351 = MOVLPSrr
+ { 1352, 6, 0, 0, "MOVLQ128mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(214<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1352 = MOVLQ128mr
+ { 1353, 3, 1, 0, "MOVLSD2PDrr", 0, 0|5|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo165 }, // Inst #1353 = MOVLSD2PDrr
+ { 1354, 3, 1, 0, "MOVLSS2PSrr", 0, 0|5|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo166 }, // Inst #1354 = MOVLSS2PSrr
+ { 1355, 2, 1, 0, "MOVMSKPDrr", 0, 0|5|(1<<6)|(1<<8)|(80<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #1355 = MOVMSKPDrr
+ { 1356, 2, 1, 0, "MOVMSKPSrr", 0, 0|5|(1<<8)|(80<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #1356 = MOVMSKPSrr
+ { 1357, 6, 1, 0, "MOVNTDQArm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(42<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1357 = MOVNTDQArm
+ { 1358, 6, 0, 0, "MOVNTDQmr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(231<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1358 = MOVNTDQmr
+ { 1359, 6, 0, 0, "MOVNTImr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(195<<24), NULL, NULL, NULL, OperandInfo11 }, // Inst #1359 = MOVNTImr
+ { 1360, 6, 0, 0, "MOVNTPDmr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(43<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1360 = MOVNTPDmr
+ { 1361, 6, 0, 0, "MOVNTPSmr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(43<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1361 = MOVNTPSmr
+ { 1362, 2, 1, 0, "MOVPC32r", 0|(1<<TID::NotDuplicable), 0|(4<<13)|(232<<24), ImplicitList2, NULL, NULL, OperandInfo55 }, // Inst #1362 = MOVPC32r
+ { 1363, 6, 0, 0, "MOVPD2SDmr", 0|(1<<TID::MayStore), 0|4|(11<<8)|(17<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1363 = MOVPD2SDmr
+ { 1364, 2, 1, 0, "MOVPD2SDrr", 0|(1<<TID::CheapAsAMove), 0|5|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo167 }, // Inst #1364 = MOVPD2SDrr
+ { 1365, 6, 0, 0, "MOVPDI2DImr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(126<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1365 = MOVPDI2DImr
+ { 1366, 2, 1, 0, "MOVPDI2DIrr", 0, 0|3|(1<<6)|(1<<8)|(126<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #1366 = MOVPDI2DIrr
+ { 1367, 6, 0, 0, "MOVPQI2QImr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(214<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1367 = MOVPQI2QImr
+ { 1368, 2, 1, 0, "MOVPQIto64rr", 0, 0|3|(1<<6)|(1<<8)|(1<<12)|(126<<24), NULL, NULL, NULL, OperandInfo121 }, // Inst #1368 = MOVPQIto64rr
+ { 1369, 6, 0, 0, "MOVPS2SSmr", 0|(1<<TID::MayStore), 0|4|(12<<8)|(17<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1369 = MOVPS2SSmr
+ { 1370, 2, 1, 0, "MOVPS2SSrr", 0|(1<<TID::CheapAsAMove), 0|5|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo168 }, // Inst #1370 = MOVPS2SSrr
+ { 1371, 6, 1, 0, "MOVQI2PQIrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(126<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1371 = MOVQI2PQIrm
+ { 1372, 2, 1, 0, "MOVQxrxr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(12<<8)|(126<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1372 = MOVQxrxr
+ { 1373, 0, 0, 0, "MOVSB", 0|(1<<TID::UnmodeledSideEffects), 0|1|(164<<24), ImplicitList37, ImplicitList38, NULL, 0 }, // Inst #1373 = MOVSB
+ { 1374, 0, 0, 0, "MOVSD", 0|(1<<TID::UnmodeledSideEffects), 0|1|(165<<24), ImplicitList37, ImplicitList38, NULL, 0 }, // Inst #1374 = MOVSD
+ { 1375, 6, 1, 0, "MOVSD2PDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1375 = MOVSD2PDrm
+ { 1376, 2, 1, 0, "MOVSD2PDrr", 0|(1<<TID::CheapAsAMove), 0|5|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo169 }, // Inst #1376 = MOVSD2PDrr
+ { 1377, 6, 0, 0, "MOVSDmr", 0|(1<<TID::MayStore), 0|4|(11<<8)|(17<<24), NULL, NULL, NULL, OperandInfo170 }, // Inst #1377 = MOVSDmr
+ { 1378, 6, 1, 0, "MOVSDrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo82 }, // Inst #1378 = MOVSDrm
+ { 1379, 2, 1, 0, "MOVSDrr", 0, 0|5|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo105 }, // Inst #1379 = MOVSDrr
+ { 1380, 6, 0, 0, "MOVSDto64mr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(1<<12)|(126<<24), NULL, NULL, NULL, OperandInfo170 }, // Inst #1380 = MOVSDto64mr
+ { 1381, 2, 1, 0, "MOVSDto64rr", 0, 0|3|(1<<6)|(1<<8)|(1<<12)|(126<<24), NULL, NULL, NULL, OperandInfo79 }, // Inst #1381 = MOVSDto64rr
+ { 1382, 6, 1, 0, "MOVSHDUPrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(22<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1382 = MOVSHDUPrm
+ { 1383, 2, 1, 0, "MOVSHDUPrr", 0, 0|5|(12<<8)|(22<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1383 = MOVSHDUPrr
+ { 1384, 6, 1, 0, "MOVSLDUPrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(18<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1384 = MOVSLDUPrm
+ { 1385, 2, 1, 0, "MOVSLDUPrr", 0, 0|5|(12<<8)|(18<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1385 = MOVSLDUPrr
+ { 1386, 6, 0, 0, "MOVSS2DImr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(126<<24), NULL, NULL, NULL, OperandInfo171 }, // Inst #1386 = MOVSS2DImr
+ { 1387, 2, 1, 0, "MOVSS2DIrr", 0, 0|3|(1<<6)|(1<<8)|(126<<24), NULL, NULL, NULL, OperandInfo89 }, // Inst #1387 = MOVSS2DIrr
+ { 1388, 6, 1, 0, "MOVSS2PSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1388 = MOVSS2PSrm
+ { 1389, 2, 1, 0, "MOVSS2PSrr", 0|(1<<TID::CheapAsAMove), 0|5|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo172 }, // Inst #1389 = MOVSS2PSrr
+ { 1390, 6, 0, 0, "MOVSSmr", 0|(1<<TID::MayStore), 0|4|(12<<8)|(17<<24), NULL, NULL, NULL, OperandInfo171 }, // Inst #1390 = MOVSSmr
+ { 1391, 6, 1, 0, "MOVSSrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #1391 = MOVSSrm
+ { 1392, 2, 1, 0, "MOVSSrr", 0, 0|5|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo106 }, // Inst #1392 = MOVSSrr
+ { 1393, 0, 0, 0, "MOVSW", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(165<<24), ImplicitList37, ImplicitList38, NULL, 0 }, // Inst #1393 = MOVSW
+ { 1394, 6, 1, 0, "MOVSX16rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1394 = MOVSX16rm8
+ { 1395, 6, 1, 0, "MOVSX16rm8W", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1395 = MOVSX16rm8W
+ { 1396, 2, 1, 0, "MOVSX16rr8", 0, 0|5|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo173 }, // Inst #1396 = MOVSX16rr8
+ { 1397, 2, 1, 0, "MOVSX16rr8W", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo173 }, // Inst #1397 = MOVSX16rr8W
+ { 1398, 6, 1, 0, "MOVSX32rm16", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(191<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1398 = MOVSX32rm16
+ { 1399, 6, 1, 0, "MOVSX32rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1399 = MOVSX32rm8
+ { 1400, 2, 1, 0, "MOVSX32rr16", 0, 0|5|(1<<8)|(191<<24), NULL, NULL, NULL, OperandInfo174 }, // Inst #1400 = MOVSX32rr16
+ { 1401, 2, 1, 0, "MOVSX32rr8", 0, 0|5|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo175 }, // Inst #1401 = MOVSX32rr8
+ { 1402, 6, 1, 0, "MOVSX64rm16", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(191<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1402 = MOVSX64rm16
+ { 1403, 6, 1, 0, "MOVSX64rm32", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(99<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1403 = MOVSX64rm32
+ { 1404, 6, 1, 0, "MOVSX64rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(190<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1404 = MOVSX64rm8
+ { 1405, 2, 1, 0, "MOVSX64rr16", 0, 0|5|(1<<8)|(1<<12)|(191<<24), NULL, NULL, NULL, OperandInfo176 }, // Inst #1405 = MOVSX64rr16
+ { 1406, 2, 1, 0, "MOVSX64rr32", 0, 0|5|(1<<12)|(99<<24), NULL, NULL, NULL, OperandInfo125 }, // Inst #1406 = MOVSX64rr32
+ { 1407, 2, 1, 0, "MOVSX64rr8", 0, 0|5|(1<<8)|(1<<12)|(190<<24), NULL, NULL, NULL, OperandInfo177 }, // Inst #1407 = MOVSX64rr8
+ { 1408, 6, 0, 0, "MOVUPDmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(17<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1408 = MOVUPDmr
+ { 1409, 6, 0, 0, "MOVUPDmr_Int", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(17<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1409 = MOVUPDmr_Int
+ { 1410, 6, 1, 0, "MOVUPDrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1410 = MOVUPDrm
+ { 1411, 6, 1, 0, "MOVUPDrm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1411 = MOVUPDrm_Int
+ { 1412, 2, 1, 0, "MOVUPDrr", 0, 0|5|(1<<6)|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1412 = MOVUPDrr
+ { 1413, 6, 0, 0, "MOVUPSmr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(17<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1413 = MOVUPSmr
+ { 1414, 6, 0, 0, "MOVUPSmr_Int", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(17<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1414 = MOVUPSmr_Int
+ { 1415, 6, 1, 0, "MOVUPSrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1415 = MOVUPSrm
+ { 1416, 6, 1, 0, "MOVUPSrm_Int", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1416 = MOVUPSrm_Int
+ { 1417, 2, 1, 0, "MOVUPSrr", 0, 0|5|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1417 = MOVUPSrr
+ { 1418, 6, 1, 0, "MOVZDI2PDIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1418 = MOVZDI2PDIrm
+ { 1419, 2, 1, 0, "MOVZDI2PDIrr", 0, 0|5|(1<<6)|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo164 }, // Inst #1419 = MOVZDI2PDIrr
+ { 1420, 6, 1, 0, "MOVZPQILo2PQIrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(126<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1420 = MOVZPQILo2PQIrm
+ { 1421, 2, 1, 0, "MOVZPQILo2PQIrr", 0, 0|5|(12<<8)|(126<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1421 = MOVZPQILo2PQIrr
+ { 1422, 6, 1, 0, "MOVZQI2PQIrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(126<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1422 = MOVZQI2PQIrm
+ { 1423, 2, 1, 0, "MOVZQI2PQIrr", 0, 0|5|(1<<6)|(1<<8)|(1<<12)|(110<<24), NULL, NULL, NULL, OperandInfo159 }, // Inst #1423 = MOVZQI2PQIrr
+ { 1424, 6, 1, 0, "MOVZSD2PDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1424 = MOVZSD2PDrm
+ { 1425, 6, 1, 0, "MOVZSS2PSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1425 = MOVZSS2PSrm
+ { 1426, 6, 1, 0, "MOVZX16rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1426 = MOVZX16rm8
+ { 1427, 6, 1, 0, "MOVZX16rm8W", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1427 = MOVZX16rm8W
+ { 1428, 2, 1, 0, "MOVZX16rr8", 0, 0|5|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo173 }, // Inst #1428 = MOVZX16rr8
+ { 1429, 2, 1, 0, "MOVZX16rr8W", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo173 }, // Inst #1429 = MOVZX16rr8W
+ { 1430, 6, 1, 0, "MOVZX32_NOREXrm8", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo178 }, // Inst #1430 = MOVZX32_NOREXrm8
+ { 1431, 2, 1, 0, "MOVZX32_NOREXrr8", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo179 }, // Inst #1431 = MOVZX32_NOREXrr8
+ { 1432, 6, 1, 0, "MOVZX32rm16", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(183<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1432 = MOVZX32rm16
+ { 1433, 6, 1, 0, "MOVZX32rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1433 = MOVZX32rm8
+ { 1434, 2, 1, 0, "MOVZX32rr16", 0, 0|5|(1<<8)|(183<<24), NULL, NULL, NULL, OperandInfo174 }, // Inst #1434 = MOVZX32rr16
+ { 1435, 2, 1, 0, "MOVZX32rr8", 0, 0|5|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo175 }, // Inst #1435 = MOVZX32rr8
+ { 1436, 6, 1, 0, "MOVZX64rm16", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(183<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1436 = MOVZX64rm16
+ { 1437, 6, 1, 0, "MOVZX64rm16_Q", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(1<<12)|(183<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1437 = MOVZX64rm16_Q
+ { 1438, 6, 1, 0, "MOVZX64rm32", 0|(1<<TID::MayLoad), 0|6|(139<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1438 = MOVZX64rm32
+ { 1439, 6, 1, 0, "MOVZX64rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1439 = MOVZX64rm8
+ { 1440, 6, 1, 0, "MOVZX64rm8_Q", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(1<<12)|(182<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1440 = MOVZX64rm8_Q
+ { 1441, 2, 1, 0, "MOVZX64rr16", 0, 0|5|(1<<8)|(183<<24), NULL, NULL, NULL, OperandInfo176 }, // Inst #1441 = MOVZX64rr16
+ { 1442, 2, 1, 0, "MOVZX64rr16_Q", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(1<<12)|(183<<24), NULL, NULL, NULL, OperandInfo176 }, // Inst #1442 = MOVZX64rr16_Q
+ { 1443, 2, 1, 0, "MOVZX64rr32", 0, 0|3|(137<<24), NULL, NULL, NULL, OperandInfo125 }, // Inst #1443 = MOVZX64rr32
+ { 1444, 2, 1, 0, "MOVZX64rr8", 0, 0|5|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo177 }, // Inst #1444 = MOVZX64rr8
+ { 1445, 2, 1, 0, "MOVZX64rr8_Q", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(1<<12)|(182<<24), NULL, NULL, NULL, OperandInfo177 }, // Inst #1445 = MOVZX64rr8_Q
+ { 1446, 2, 1, 0, "MOV_Fp3232", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo2 }, // Inst #1446 = MOV_Fp3232
+ { 1447, 2, 1, 0, "MOV_Fp3264", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo180 }, // Inst #1447 = MOV_Fp3264
+ { 1448, 2, 1, 0, "MOV_Fp3280", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo181 }, // Inst #1448 = MOV_Fp3280
+ { 1449, 2, 1, 0, "MOV_Fp6432", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo182 }, // Inst #1449 = MOV_Fp6432
+ { 1450, 2, 1, 0, "MOV_Fp6464", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo3 }, // Inst #1450 = MOV_Fp6464
+ { 1451, 2, 1, 0, "MOV_Fp6480", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo183 }, // Inst #1451 = MOV_Fp6480
+ { 1452, 2, 1, 0, "MOV_Fp8032", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo184 }, // Inst #1452 = MOV_Fp8032
+ { 1453, 2, 1, 0, "MOV_Fp8064", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo185 }, // Inst #1453 = MOV_Fp8064
+ { 1454, 2, 1, 0, "MOV_Fp8080", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo4 }, // Inst #1454 = MOV_Fp8080
+ { 1455, 8, 1, 0, "MPSADBWrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(66<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1455 = MPSADBWrmi
+ { 1456, 4, 1, 0, "MPSADBWrri", 0|(1<<TID::Commutable), 0|5|(1<<6)|(14<<8)|(1<<13)|(66<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #1456 = MPSADBWrri
+ { 1457, 5, 0, 0, "MUL16m", 0|(1<<TID::MayLoad), 0|28|(1<<6)|(247<<24), ImplicitList12, ImplicitList21, Barriers1, OperandInfo30 }, // Inst #1457 = MUL16m
+ { 1458, 1, 0, 0, "MUL16r", 0, 0|20|(1<<6)|(247<<24), ImplicitList12, ImplicitList21, Barriers1, OperandInfo93 }, // Inst #1458 = MUL16r
+ { 1459, 5, 0, 0, "MUL32m", 0|(1<<TID::MayLoad), 0|28|(247<<24), ImplicitList13, ImplicitList18, Barriers6, OperandInfo30 }, // Inst #1459 = MUL32m
+ { 1460, 1, 0, 0, "MUL32r", 0, 0|20|(247<<24), ImplicitList13, ImplicitList18, Barriers6, OperandInfo57 }, // Inst #1460 = MUL32r
+ { 1461, 5, 0, 0, "MUL64m", 0|(1<<TID::MayLoad), 0|28|(1<<12)|(247<<24), ImplicitList15, ImplicitList17, Barriers1, OperandInfo30 }, // Inst #1461 = MUL64m
+ { 1462, 1, 0, 0, "MUL64r", 0, 0|20|(1<<12)|(247<<24), ImplicitList15, ImplicitList17, Barriers1, OperandInfo58 }, // Inst #1462 = MUL64r
+ { 1463, 5, 0, 0, "MUL8m", 0|(1<<TID::MayLoad), 0|28|(246<<24), ImplicitList11, ImplicitList22, Barriers1, OperandInfo30 }, // Inst #1463 = MUL8m
+ { 1464, 1, 0, 0, "MUL8r", 0, 0|20|(246<<24), ImplicitList11, ImplicitList22, Barriers1, OperandInfo94 }, // Inst #1464 = MUL8r
+ { 1465, 7, 1, 0, "MULPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(89<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1465 = MULPDrm
+ { 1466, 3, 1, 0, "MULPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(89<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1466 = MULPDrr
+ { 1467, 7, 1, 0, "MULPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(89<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1467 = MULPSrm
+ { 1468, 3, 1, 0, "MULPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(89<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1468 = MULPSrr
+ { 1469, 7, 1, 0, "MULSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(89<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #1469 = MULSDrm
+ { 1470, 7, 1, 0, "MULSDrm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(89<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1470 = MULSDrm_Int
+ { 1471, 3, 1, 0, "MULSDrr", 0|(1<<TID::Commutable), 0|5|(11<<8)|(89<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #1471 = MULSDrr
+ { 1472, 3, 1, 0, "MULSDrr_Int", 0, 0|5|(11<<8)|(89<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1472 = MULSDrr_Int
+ { 1473, 7, 1, 0, "MULSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(89<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #1473 = MULSSrm
+ { 1474, 7, 1, 0, "MULSSrm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(89<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1474 = MULSSrm_Int
+ { 1475, 3, 1, 0, "MULSSrr", 0|(1<<TID::Commutable), 0|5|(12<<8)|(89<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #1475 = MULSSrr
+ { 1476, 3, 1, 0, "MULSSrr_Int", 0, 0|5|(12<<8)|(89<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1476 = MULSSrr_Int
+ { 1477, 5, 0, 0, "MUL_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|25|(216<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1477 = MUL_F32m
+ { 1478, 5, 0, 0, "MUL_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|25|(220<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1478 = MUL_F64m
+ { 1479, 5, 0, 0, "MUL_FI16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|25|(222<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1479 = MUL_FI16m
+ { 1480, 5, 0, 0, "MUL_FI32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|25|(218<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1480 = MUL_FI32m
+ { 1481, 1, 0, 0, "MUL_FPrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(9<<8)|(200<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #1481 = MUL_FPrST0
+ { 1482, 1, 0, 0, "MUL_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(200<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #1482 = MUL_FST0r
+ { 1483, 3, 1, 0, "MUL_Fp32", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #1483 = MUL_Fp32
+ { 1484, 7, 1, 0, "MUL_Fp32m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #1484 = MUL_Fp32m
+ { 1485, 3, 1, 0, "MUL_Fp64", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #1485 = MUL_Fp64
+ { 1486, 7, 1, 0, "MUL_Fp64m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #1486 = MUL_Fp64m
+ { 1487, 7, 1, 0, "MUL_Fp64m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #1487 = MUL_Fp64m32
+ { 1488, 3, 1, 0, "MUL_Fp80", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #1488 = MUL_Fp80
+ { 1489, 7, 1, 0, "MUL_Fp80m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #1489 = MUL_Fp80m32
+ { 1490, 7, 1, 0, "MUL_Fp80m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #1490 = MUL_Fp80m64
+ { 1491, 7, 1, 0, "MUL_FpI16m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #1491 = MUL_FpI16m32
+ { 1492, 7, 1, 0, "MUL_FpI16m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #1492 = MUL_FpI16m64
+ { 1493, 7, 1, 0, "MUL_FpI16m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #1493 = MUL_FpI16m80
+ { 1494, 7, 1, 0, "MUL_FpI32m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #1494 = MUL_FpI32m32
+ { 1495, 7, 1, 0, "MUL_FpI32m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #1495 = MUL_FpI32m64
+ { 1496, 7, 1, 0, "MUL_FpI32m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #1496 = MUL_FpI32m80
+ { 1497, 1, 0, 0, "MUL_FrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(7<<8)|(200<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #1497 = MUL_FrST0
+ { 1498, 0, 0, 0, "MWAIT", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|38|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #1498 = MWAIT
+ { 1499, 5, 0, 0, "NEG16m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<6)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1499 = NEG16m
+ { 1500, 2, 1, 0, "NEG16r", 0, 0|19|(1<<6)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1500 = NEG16r
+ { 1501, 5, 0, 0, "NEG32m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1501 = NEG32m
+ { 1502, 2, 1, 0, "NEG32r", 0, 0|19|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1502 = NEG32r
+ { 1503, 5, 0, 0, "NEG64m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<12)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1503 = NEG64m
+ { 1504, 2, 1, 0, "NEG64r", 0, 0|19|(1<<12)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #1504 = NEG64r
+ { 1505, 5, 0, 0, "NEG8m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(246<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1505 = NEG8m
+ { 1506, 2, 1, 0, "NEG8r", 0, 0|19|(246<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #1506 = NEG8r
+ { 1507, 0, 0, 0, "NOOP", 0, 0|1|(144<<24), NULL, NULL, NULL, 0 }, // Inst #1507 = NOOP
+ { 1508, 5, 0, 0, "NOOPL", 0, 0|24|(1<<8)|(31<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1508 = NOOPL
+ { 1509, 5, 0, 0, "NOOPW", 0, 0|24|(1<<6)|(1<<8)|(31<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1509 = NOOPW
+ { 1510, 5, 0, 0, "NOT16m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<6)|(247<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1510 = NOT16m
+ { 1511, 2, 1, 0, "NOT16r", 0, 0|18|(1<<6)|(247<<24), NULL, NULL, NULL, OperandInfo91 }, // Inst #1511 = NOT16r
+ { 1512, 5, 0, 0, "NOT32m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(247<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1512 = NOT32m
+ { 1513, 2, 1, 0, "NOT32r", 0, 0|18|(247<<24), NULL, NULL, NULL, OperandInfo52 }, // Inst #1513 = NOT32r
+ { 1514, 5, 0, 0, "NOT64m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<12)|(247<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1514 = NOT64m
+ { 1515, 2, 1, 0, "NOT64r", 0, 0|18|(1<<12)|(247<<24), NULL, NULL, NULL, OperandInfo53 }, // Inst #1515 = NOT64r
+ { 1516, 5, 0, 0, "NOT8m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(246<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1516 = NOT8m
+ { 1517, 2, 1, 0, "NOT8r", 0, 0|18|(246<<24), NULL, NULL, NULL, OperandInfo92 }, // Inst #1517 = NOT8r
+ { 1518, 1, 0, 0, "OR16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(3<<13)|(13<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #1518 = OR16i16
+ { 1519, 6, 0, 0, "OR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1519 = OR16mi
+ { 1520, 6, 0, 0, "OR16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1520 = OR16mi8
+ { 1521, 6, 0, 0, "OR16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #1521 = OR16mr
+ { 1522, 3, 1, 0, "OR16ri", 0, 0|17|(1<<6)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1522 = OR16ri
+ { 1523, 3, 1, 0, "OR16ri8", 0, 0|17|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1523 = OR16ri8
+ { 1524, 7, 1, 0, "OR16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #1524 = OR16rm
+ { 1525, 3, 1, 0, "OR16rr", 0|(1<<TID::Commutable), 0|3|(1<<6)|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #1525 = OR16rr
+ { 1526, 3, 1, 0, "OR16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #1526 = OR16rr_REV
+ { 1527, 1, 0, 0, "OR32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<13)|(13<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #1527 = OR32i32
+ { 1528, 6, 0, 0, "OR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1528 = OR32mi
+ { 1529, 6, 0, 0, "OR32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1529 = OR32mi8
+ { 1530, 6, 0, 0, "OR32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #1530 = OR32mr
+ { 1531, 3, 1, 0, "OR32ri", 0, 0|17|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1531 = OR32ri
+ { 1532, 3, 1, 0, "OR32ri8", 0, 0|17|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1532 = OR32ri8
+ { 1533, 7, 1, 0, "OR32rm", 0|(1<<TID::MayLoad), 0|6|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #1533 = OR32rm
+ { 1534, 3, 1, 0, "OR32rr", 0|(1<<TID::Commutable), 0|3|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #1534 = OR32rr
+ { 1535, 3, 1, 0, "OR32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #1535 = OR32rr_REV
+ { 1536, 1, 0, 0, "OR64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(4<<13)|(13<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #1536 = OR64i32
+ { 1537, 6, 0, 0, "OR64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1537 = OR64mi32
+ { 1538, 6, 0, 0, "OR64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1538 = OR64mi8
+ { 1539, 6, 0, 0, "OR64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #1539 = OR64mr
+ { 1540, 3, 1, 0, "OR64ri32", 0, 0|17|(1<<12)|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1540 = OR64ri32
+ { 1541, 3, 1, 0, "OR64ri8", 0, 0|17|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1541 = OR64ri8
+ { 1542, 7, 1, 0, "OR64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #1542 = OR64rm
+ { 1543, 3, 1, 0, "OR64rr", 0|(1<<TID::Commutable), 0|3|(1<<12)|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #1543 = OR64rr
+ { 1544, 3, 1, 0, "OR64rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #1544 = OR64rr_REV
+ { 1545, 1, 0, 0, "OR8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(12<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #1545 = OR8i8
+ { 1546, 6, 0, 0, "OR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1546 = OR8mi
+ { 1547, 6, 0, 0, "OR8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(8<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #1547 = OR8mr
+ { 1548, 3, 1, 0, "OR8ri", 0, 0|17|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1548 = OR8ri
+ { 1549, 7, 1, 0, "OR8rm", 0|(1<<TID::MayLoad), 0|6|(10<<24), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #1549 = OR8rm
+ { 1550, 3, 1, 0, "OR8rr", 0|(1<<TID::Commutable), 0|3|(8<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #1550 = OR8rr
+ { 1551, 3, 1, 0, "OR8rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(10<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #1551 = OR8rr_REV
+ { 1552, 7, 1, 0, "ORPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1552 = ORPDrm
+ { 1553, 3, 1, 0, "ORPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1553 = ORPDrr
+ { 1554, 7, 1, 0, "ORPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1554 = ORPSrm
+ { 1555, 3, 1, 0, "ORPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1555 = ORPSrr
+ { 1556, 1, 0, 0, "OUT16ir", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<13)|(231<<24), ImplicitList12, NULL, NULL, OperandInfo5 }, // Inst #1556 = OUT16ir
+ { 1557, 0, 0, 0, "OUT16rr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(239<<24), ImplicitList39, NULL, NULL, 0 }, // Inst #1557 = OUT16rr
+ { 1558, 1, 0, 0, "OUT32ir", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(231<<24), ImplicitList13, NULL, NULL, OperandInfo5 }, // Inst #1558 = OUT32ir
+ { 1559, 0, 0, 0, "OUT32rr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(239<<24), ImplicitList40, NULL, NULL, 0 }, // Inst #1559 = OUT32rr
+ { 1560, 1, 0, 0, "OUT8ir", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(230<<24), ImplicitList11, NULL, NULL, OperandInfo5 }, // Inst #1560 = OUT8ir
+ { 1561, 0, 0, 0, "OUT8rr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(238<<24), ImplicitList41, NULL, NULL, 0 }, // Inst #1561 = OUT8rr
+ { 1562, 0, 0, 0, "OUTSB", 0|(1<<TID::UnmodeledSideEffects), 0|1|(110<<24), NULL, NULL, NULL, 0 }, // Inst #1562 = OUTSB
+ { 1563, 0, 0, 0, "OUTSD", 0|(1<<TID::UnmodeledSideEffects), 0|1|(111<<24), NULL, NULL, NULL, 0 }, // Inst #1563 = OUTSD
+ { 1564, 0, 0, 0, "OUTSW", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(111<<24), NULL, NULL, NULL, 0 }, // Inst #1564 = OUTSW
+ { 1565, 6, 1, 0, "PABSBrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(28<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1565 = PABSBrm128
+ { 1566, 6, 1, 0, "PABSBrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(28<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1566 = PABSBrm64
+ { 1567, 2, 1, 0, "PABSBrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(28<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1567 = PABSBrr128
+ { 1568, 2, 1, 0, "PABSBrr64", 0, 0|5|(13<<8)|(1<<13)|(28<<24), NULL, NULL, NULL, OperandInfo129 }, // Inst #1568 = PABSBrr64
+ { 1569, 6, 1, 0, "PABSDrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(30<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1569 = PABSDrm128
+ { 1570, 6, 1, 0, "PABSDrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(30<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1570 = PABSDrm64
+ { 1571, 2, 1, 0, "PABSDrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(30<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1571 = PABSDrr128
+ { 1572, 2, 1, 0, "PABSDrr64", 0, 0|5|(13<<8)|(1<<13)|(30<<24), NULL, NULL, NULL, OperandInfo129 }, // Inst #1572 = PABSDrr64
+ { 1573, 6, 1, 0, "PABSWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(29<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1573 = PABSWrm128
+ { 1574, 6, 1, 0, "PABSWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(29<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1574 = PABSWrm64
+ { 1575, 2, 1, 0, "PABSWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(29<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1575 = PABSWrr128
+ { 1576, 2, 1, 0, "PABSWrr64", 0, 0|5|(13<<8)|(1<<13)|(29<<24), NULL, NULL, NULL, OperandInfo129 }, // Inst #1576 = PABSWrr64
+ { 1577, 7, 1, 0, "PACKSSDWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(107<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1577 = PACKSSDWrm
+ { 1578, 3, 1, 0, "PACKSSDWrr", 0, 0|5|(1<<6)|(1<<8)|(107<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1578 = PACKSSDWrr
+ { 1579, 7, 1, 0, "PACKSSWBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(99<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1579 = PACKSSWBrm
+ { 1580, 3, 1, 0, "PACKSSWBrr", 0, 0|5|(1<<6)|(1<<8)|(99<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1580 = PACKSSWBrr
+ { 1581, 7, 1, 0, "PACKUSDWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(43<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1581 = PACKUSDWrm
+ { 1582, 3, 1, 0, "PACKUSDWrr", 0, 0|5|(1<<6)|(13<<8)|(43<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1582 = PACKUSDWrr
+ { 1583, 7, 1, 0, "PACKUSWBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(103<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1583 = PACKUSWBrm
+ { 1584, 3, 1, 0, "PACKUSWBrr", 0, 0|5|(1<<6)|(1<<8)|(103<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1584 = PACKUSWBrr
+ { 1585, 7, 1, 0, "PADDBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(252<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1585 = PADDBrm
+ { 1586, 3, 1, 0, "PADDBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(252<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1586 = PADDBrr
+ { 1587, 7, 1, 0, "PADDDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(254<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1587 = PADDDrm
+ { 1588, 3, 1, 0, "PADDDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(254<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1588 = PADDDrr
+ { 1589, 7, 1, 0, "PADDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(212<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1589 = PADDQrm
+ { 1590, 3, 1, 0, "PADDQrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(212<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1590 = PADDQrr
+ { 1591, 7, 1, 0, "PADDSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(236<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1591 = PADDSBrm
+ { 1592, 3, 1, 0, "PADDSBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(236<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1592 = PADDSBrr
+ { 1593, 7, 1, 0, "PADDSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(237<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1593 = PADDSWrm
+ { 1594, 3, 1, 0, "PADDSWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(237<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1594 = PADDSWrr
+ { 1595, 7, 1, 0, "PADDUSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(220<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1595 = PADDUSBrm
+ { 1596, 3, 1, 0, "PADDUSBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(220<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1596 = PADDUSBrr
+ { 1597, 7, 1, 0, "PADDUSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(221<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1597 = PADDUSWrm
+ { 1598, 3, 1, 0, "PADDUSWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(221<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1598 = PADDUSWrr
+ { 1599, 7, 1, 0, "PADDWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(253<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1599 = PADDWrm
+ { 1600, 3, 1, 0, "PADDWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(253<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1600 = PADDWrr
+ { 1601, 8, 1, 0, "PALIGNR128rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(14<<8)|(1<<13)|(15<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1601 = PALIGNR128rm
+ { 1602, 4, 1, 0, "PALIGNR128rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(14<<8)|(1<<13)|(15<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #1602 = PALIGNR128rr
+ { 1603, 8, 1, 0, "PALIGNR64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(14<<8)|(1<<13)|(15<<24), NULL, NULL, NULL, OperandInfo139 }, // Inst #1603 = PALIGNR64rm
+ { 1604, 4, 1, 0, "PALIGNR64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(14<<8)|(1<<13)|(15<<24), NULL, NULL, NULL, OperandInfo186 }, // Inst #1604 = PALIGNR64rr
+ { 1605, 7, 1, 0, "PANDNrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(223<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1605 = PANDNrm
+ { 1606, 3, 1, 0, "PANDNrr", 0, 0|5|(1<<6)|(1<<8)|(223<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1606 = PANDNrr
+ { 1607, 7, 1, 0, "PANDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(219<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1607 = PANDrm
+ { 1608, 3, 1, 0, "PANDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(219<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1608 = PANDrr
+ { 1609, 7, 1, 0, "PAVGBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(224<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1609 = PAVGBrm
+ { 1610, 3, 1, 0, "PAVGBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(224<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1610 = PAVGBrr
+ { 1611, 7, 1, 0, "PAVGWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(227<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1611 = PAVGWrm
+ { 1612, 3, 1, 0, "PAVGWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(227<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1612 = PAVGWrr
+ { 1613, 7, 1, 0, "PBLENDVBrm0", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(16<<24), ImplicitList8, NULL, NULL, OperandInfo24 }, // Inst #1613 = PBLENDVBrm0
+ { 1614, 3, 1, 0, "PBLENDVBrr0", 0, 0|5|(1<<6)|(13<<8)|(16<<24), ImplicitList8, NULL, NULL, OperandInfo25 }, // Inst #1614 = PBLENDVBrr0
+ { 1615, 8, 1, 0, "PBLENDWrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(14<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1615 = PBLENDWrmi
+ { 1616, 4, 1, 0, "PBLENDWrri", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(14<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #1616 = PBLENDWrri
+ { 1617, 7, 1, 0, "PCMPEQBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(116<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1617 = PCMPEQBrm
+ { 1618, 3, 1, 0, "PCMPEQBrr", 0, 0|5|(1<<6)|(1<<8)|(116<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1618 = PCMPEQBrr
+ { 1619, 7, 1, 0, "PCMPEQDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1619 = PCMPEQDrm
+ { 1620, 3, 1, 0, "PCMPEQDrr", 0, 0|5|(1<<6)|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1620 = PCMPEQDrr
+ { 1621, 7, 1, 0, "PCMPEQQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(41<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1621 = PCMPEQQrm
+ { 1622, 3, 1, 0, "PCMPEQQrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(41<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1622 = PCMPEQQrr
+ { 1623, 7, 1, 0, "PCMPEQWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(117<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1623 = PCMPEQWrm
+ { 1624, 3, 1, 0, "PCMPEQWrr", 0, 0|5|(1<<6)|(1<<8)|(117<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1624 = PCMPEQWrr
+ { 1625, 7, 0, 0, "PCMPESTRIArm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo187 }, // Inst #1625 = PCMPESTRIArm
+ { 1626, 3, 0, 0, "PCMPESTRIArr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo188 }, // Inst #1626 = PCMPESTRIArr
+ { 1627, 7, 0, 0, "PCMPESTRICrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo187 }, // Inst #1627 = PCMPESTRICrm
+ { 1628, 3, 0, 0, "PCMPESTRICrr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo188 }, // Inst #1628 = PCMPESTRICrr
+ { 1629, 7, 0, 0, "PCMPESTRIOrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo187 }, // Inst #1629 = PCMPESTRIOrm
+ { 1630, 3, 0, 0, "PCMPESTRIOrr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo188 }, // Inst #1630 = PCMPESTRIOrr
+ { 1631, 7, 0, 0, "PCMPESTRISrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo187 }, // Inst #1631 = PCMPESTRISrm
+ { 1632, 3, 0, 0, "PCMPESTRISrr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo188 }, // Inst #1632 = PCMPESTRISrr
+ { 1633, 7, 0, 0, "PCMPESTRIZrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo187 }, // Inst #1633 = PCMPESTRIZrm
+ { 1634, 3, 0, 0, "PCMPESTRIZrr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo188 }, // Inst #1634 = PCMPESTRIZrr
+ { 1635, 7, 0, 0, "PCMPESTRIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo187 }, // Inst #1635 = PCMPESTRIrm
+ { 1636, 3, 0, 0, "PCMPESTRIrr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo188 }, // Inst #1636 = PCMPESTRIrr
+ { 1637, 8, 1, 0, "PCMPESTRM128MEM", 0|(1<<TID::MayLoad)|(1<<TID::UsesCustomInserter), 0|(1<<6)|(14<<8), ImplicitList14, ImplicitList1, Barriers1, OperandInfo189 }, // Inst #1637 = PCMPESTRM128MEM
+ { 1638, 4, 1, 0, "PCMPESTRM128REG", 0|(1<<TID::UsesCustomInserter), 0|(1<<6)|(14<<8), ImplicitList14, ImplicitList1, Barriers1, OperandInfo66 }, // Inst #1638 = PCMPESTRM128REG
+ { 1639, 7, 0, 0, "PCMPESTRM128rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(14<<8)|(96<<24), ImplicitList14, ImplicitList43, Barriers1, OperandInfo187 }, // Inst #1639 = PCMPESTRM128rm
+ { 1640, 3, 0, 0, "PCMPESTRM128rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(14<<8)|(96<<24), ImplicitList14, ImplicitList43, Barriers1, OperandInfo188 }, // Inst #1640 = PCMPESTRM128rr
+ { 1641, 7, 1, 0, "PCMPGTBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(100<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1641 = PCMPGTBrm
+ { 1642, 3, 1, 0, "PCMPGTBrr", 0, 0|5|(1<<6)|(1<<8)|(100<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1642 = PCMPGTBrr
+ { 1643, 7, 1, 0, "PCMPGTDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(102<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1643 = PCMPGTDrm
+ { 1644, 3, 1, 0, "PCMPGTDrr", 0, 0|5|(1<<6)|(1<<8)|(102<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1644 = PCMPGTDrr
+ { 1645, 7, 1, 0, "PCMPGTQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(55<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1645 = PCMPGTQrm
+ { 1646, 3, 1, 0, "PCMPGTQrr", 0, 0|5|(1<<6)|(13<<8)|(55<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1646 = PCMPGTQrr
+ { 1647, 7, 1, 0, "PCMPGTWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(101<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1647 = PCMPGTWrm
+ { 1648, 3, 1, 0, "PCMPGTWrr", 0, 0|5|(1<<6)|(1<<8)|(101<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1648 = PCMPGTWrr
+ { 1649, 7, 0, 0, "PCMPISTRIArm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo187 }, // Inst #1649 = PCMPISTRIArm
+ { 1650, 3, 0, 0, "PCMPISTRIArr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo188 }, // Inst #1650 = PCMPISTRIArr
+ { 1651, 7, 0, 0, "PCMPISTRICrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo187 }, // Inst #1651 = PCMPISTRICrm
+ { 1652, 3, 0, 0, "PCMPISTRICrr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo188 }, // Inst #1652 = PCMPISTRICrr
+ { 1653, 7, 0, 0, "PCMPISTRIOrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo187 }, // Inst #1653 = PCMPISTRIOrm
+ { 1654, 3, 0, 0, "PCMPISTRIOrr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo188 }, // Inst #1654 = PCMPISTRIOrr
+ { 1655, 7, 0, 0, "PCMPISTRISrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo187 }, // Inst #1655 = PCMPISTRISrm
+ { 1656, 3, 0, 0, "PCMPISTRISrr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo188 }, // Inst #1656 = PCMPISTRISrr
+ { 1657, 7, 0, 0, "PCMPISTRIZrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo187 }, // Inst #1657 = PCMPISTRIZrm
+ { 1658, 3, 0, 0, "PCMPISTRIZrr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo188 }, // Inst #1658 = PCMPISTRIZrr
+ { 1659, 7, 0, 0, "PCMPISTRIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo187 }, // Inst #1659 = PCMPISTRIrm
+ { 1660, 3, 0, 0, "PCMPISTRIrr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo188 }, // Inst #1660 = PCMPISTRIrr
+ { 1661, 8, 1, 0, "PCMPISTRM128MEM", 0|(1<<TID::MayLoad)|(1<<TID::UsesCustomInserter), 0|(1<<6)|(14<<8), NULL, ImplicitList1, Barriers1, OperandInfo189 }, // Inst #1661 = PCMPISTRM128MEM
+ { 1662, 4, 1, 0, "PCMPISTRM128REG", 0|(1<<TID::UsesCustomInserter), 0|(1<<6)|(14<<8), NULL, ImplicitList1, Barriers1, OperandInfo66 }, // Inst #1662 = PCMPISTRM128REG
+ { 1663, 7, 0, 0, "PCMPISTRM128rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(14<<8)|(98<<24), NULL, ImplicitList43, Barriers1, OperandInfo187 }, // Inst #1663 = PCMPISTRM128rm
+ { 1664, 3, 0, 0, "PCMPISTRM128rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(14<<8)|(98<<24), NULL, ImplicitList43, Barriers1, OperandInfo188 }, // Inst #1664 = PCMPISTRM128rr
+ { 1665, 7, 0, 0, "PEXTRBmr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(14<<8)|(1<<13)|(20<<24), NULL, NULL, NULL, OperandInfo95 }, // Inst #1665 = PEXTRBmr
+ { 1666, 3, 1, 0, "PEXTRBrr", 0, 0|3|(1<<6)|(14<<8)|(1<<13)|(20<<24), NULL, NULL, NULL, OperandInfo96 }, // Inst #1666 = PEXTRBrr
+ { 1667, 7, 0, 0, "PEXTRDmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(14<<8)|(1<<13)|(22<<24), NULL, NULL, NULL, OperandInfo95 }, // Inst #1667 = PEXTRDmr
+ { 1668, 3, 1, 0, "PEXTRDrr", 0, 0|3|(1<<6)|(14<<8)|(1<<13)|(22<<24), NULL, NULL, NULL, OperandInfo96 }, // Inst #1668 = PEXTRDrr
+ { 1669, 7, 0, 0, "PEXTRQmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(14<<8)|(1<<12)|(1<<13)|(22<<24), NULL, NULL, NULL, OperandInfo95 }, // Inst #1669 = PEXTRQmr
+ { 1670, 3, 1, 0, "PEXTRQrr", 0, 0|3|(1<<6)|(14<<8)|(1<<12)|(1<<13)|(22<<24), NULL, NULL, NULL, OperandInfo190 }, // Inst #1670 = PEXTRQrr
+ { 1671, 7, 0, 0, "PEXTRWmr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(14<<8)|(1<<13)|(21<<24), NULL, NULL, NULL, OperandInfo95 }, // Inst #1671 = PEXTRWmr
+ { 1672, 3, 1, 0, "PEXTRWri", 0, 0|5|(1<<6)|(1<<8)|(1<<13)|(197<<24), NULL, NULL, NULL, OperandInfo96 }, // Inst #1672 = PEXTRWri
+ { 1673, 7, 1, 0, "PHADDDrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(2<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1673 = PHADDDrm128
+ { 1674, 7, 1, 0, "PHADDDrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(2<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1674 = PHADDDrm64
+ { 1675, 3, 1, 0, "PHADDDrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(2<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1675 = PHADDDrr128
+ { 1676, 3, 1, 0, "PHADDDrr64", 0, 0|5|(13<<8)|(1<<13)|(2<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1676 = PHADDDrr64
+ { 1677, 7, 1, 0, "PHADDSWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(3<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1677 = PHADDSWrm128
+ { 1678, 7, 1, 0, "PHADDSWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(3<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1678 = PHADDSWrm64
+ { 1679, 3, 1, 0, "PHADDSWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(3<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1679 = PHADDSWrr128
+ { 1680, 3, 1, 0, "PHADDSWrr64", 0, 0|5|(13<<8)|(1<<13)|(3<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1680 = PHADDSWrr64
+ { 1681, 7, 1, 0, "PHADDWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(1<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1681 = PHADDWrm128
+ { 1682, 7, 1, 0, "PHADDWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(1<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1682 = PHADDWrm64
+ { 1683, 3, 1, 0, "PHADDWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(1<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1683 = PHADDWrr128
+ { 1684, 3, 1, 0, "PHADDWrr64", 0, 0|5|(13<<8)|(1<<13)|(1<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1684 = PHADDWrr64
+ { 1685, 6, 1, 0, "PHMINPOSUWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(65<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1685 = PHMINPOSUWrm128
+ { 1686, 2, 1, 0, "PHMINPOSUWrr128", 0, 0|5|(1<<6)|(13<<8)|(65<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1686 = PHMINPOSUWrr128
+ { 1687, 7, 1, 0, "PHSUBDrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(6<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1687 = PHSUBDrm128
+ { 1688, 7, 1, 0, "PHSUBDrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(6<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1688 = PHSUBDrm64
+ { 1689, 3, 1, 0, "PHSUBDrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(6<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1689 = PHSUBDrr128
+ { 1690, 3, 1, 0, "PHSUBDrr64", 0, 0|5|(13<<8)|(1<<13)|(6<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1690 = PHSUBDrr64
+ { 1691, 7, 1, 0, "PHSUBSWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(7<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1691 = PHSUBSWrm128
+ { 1692, 7, 1, 0, "PHSUBSWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(7<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1692 = PHSUBSWrm64
+ { 1693, 3, 1, 0, "PHSUBSWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(7<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1693 = PHSUBSWrr128
+ { 1694, 3, 1, 0, "PHSUBSWrr64", 0, 0|5|(13<<8)|(1<<13)|(7<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1694 = PHSUBSWrr64
+ { 1695, 7, 1, 0, "PHSUBWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(5<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1695 = PHSUBWrm128
+ { 1696, 7, 1, 0, "PHSUBWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(5<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1696 = PHSUBWrm64
+ { 1697, 3, 1, 0, "PHSUBWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(5<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1697 = PHSUBWrr128
+ { 1698, 3, 1, 0, "PHSUBWrr64", 0, 0|5|(13<<8)|(1<<13)|(5<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1698 = PHSUBWrr64
+ { 1699, 8, 1, 0, "PINSRBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(32<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1699 = PINSRBrm
+ { 1700, 4, 1, 0, "PINSRBrr", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(32<<24), NULL, NULL, NULL, OperandInfo191 }, // Inst #1700 = PINSRBrr
+ { 1701, 8, 1, 0, "PINSRDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(34<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1701 = PINSRDrm
+ { 1702, 4, 1, 0, "PINSRDrr", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(34<<24), NULL, NULL, NULL, OperandInfo191 }, // Inst #1702 = PINSRDrr
+ { 1703, 8, 1, 0, "PINSRQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<12)|(1<<13)|(34<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1703 = PINSRQrm
+ { 1704, 4, 1, 0, "PINSRQrr", 0, 0|5|(1<<6)|(14<<8)|(1<<12)|(1<<13)|(34<<24), NULL, NULL, NULL, OperandInfo192 }, // Inst #1704 = PINSRQrr
+ { 1705, 8, 1, 0, "PINSRWrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(1<<13)|(196<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1705 = PINSRWrmi
+ { 1706, 4, 1, 0, "PINSRWrri", 0, 0|5|(1<<6)|(1<<8)|(1<<13)|(196<<24), NULL, NULL, NULL, OperandInfo191 }, // Inst #1706 = PINSRWrri
+ { 1707, 7, 1, 0, "PMADDUBSWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(4<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1707 = PMADDUBSWrm128
+ { 1708, 7, 1, 0, "PMADDUBSWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(4<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1708 = PMADDUBSWrm64
+ { 1709, 3, 1, 0, "PMADDUBSWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(4<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1709 = PMADDUBSWrr128
+ { 1710, 3, 1, 0, "PMADDUBSWrr64", 0, 0|5|(13<<8)|(1<<13)|(4<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1710 = PMADDUBSWrr64
+ { 1711, 7, 1, 0, "PMADDWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(245<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1711 = PMADDWDrm
+ { 1712, 3, 1, 0, "PMADDWDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(245<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1712 = PMADDWDrr
+ { 1713, 7, 1, 0, "PMAXSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(60<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1713 = PMAXSBrm
+ { 1714, 3, 1, 0, "PMAXSBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(60<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1714 = PMAXSBrr
+ { 1715, 7, 1, 0, "PMAXSDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(61<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1715 = PMAXSDrm
+ { 1716, 3, 1, 0, "PMAXSDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(61<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1716 = PMAXSDrr
+ { 1717, 7, 1, 0, "PMAXSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(238<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1717 = PMAXSWrm
+ { 1718, 3, 1, 0, "PMAXSWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(238<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1718 = PMAXSWrr
+ { 1719, 7, 1, 0, "PMAXUBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(222<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1719 = PMAXUBrm
+ { 1720, 3, 1, 0, "PMAXUBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(222<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1720 = PMAXUBrr
+ { 1721, 7, 1, 0, "PMAXUDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(63<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1721 = PMAXUDrm
+ { 1722, 3, 1, 0, "PMAXUDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(63<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1722 = PMAXUDrr
+ { 1723, 7, 1, 0, "PMAXUWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(62<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1723 = PMAXUWrm
+ { 1724, 3, 1, 0, "PMAXUWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(62<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1724 = PMAXUWrr
+ { 1725, 7, 1, 0, "PMINSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(56<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1725 = PMINSBrm
+ { 1726, 3, 1, 0, "PMINSBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(56<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1726 = PMINSBrr
+ { 1727, 7, 1, 0, "PMINSDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(57<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1727 = PMINSDrm
+ { 1728, 3, 1, 0, "PMINSDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(57<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1728 = PMINSDrr
+ { 1729, 7, 1, 0, "PMINSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(234<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1729 = PMINSWrm
+ { 1730, 3, 1, 0, "PMINSWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(234<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1730 = PMINSWrr
+ { 1731, 7, 1, 0, "PMINUBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(218<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1731 = PMINUBrm
+ { 1732, 3, 1, 0, "PMINUBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(218<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1732 = PMINUBrr
+ { 1733, 7, 1, 0, "PMINUDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(59<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1733 = PMINUDrm
+ { 1734, 3, 1, 0, "PMINUDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(59<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1734 = PMINUDrr
+ { 1735, 7, 1, 0, "PMINUWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(58<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1735 = PMINUWrm
+ { 1736, 3, 1, 0, "PMINUWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(58<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1736 = PMINUWrr
+ { 1737, 2, 1, 0, "PMOVMSKBrr", 0, 0|5|(1<<6)|(1<<8)|(215<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #1737 = PMOVMSKBrr
+ { 1738, 6, 1, 0, "PMOVSXBDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(33<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1738 = PMOVSXBDrm
+ { 1739, 2, 1, 0, "PMOVSXBDrr", 0, 0|5|(1<<6)|(13<<8)|(33<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1739 = PMOVSXBDrr
+ { 1740, 6, 1, 0, "PMOVSXBQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(34<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1740 = PMOVSXBQrm
+ { 1741, 2, 1, 0, "PMOVSXBQrr", 0, 0|5|(1<<6)|(13<<8)|(34<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1741 = PMOVSXBQrr
+ { 1742, 6, 1, 0, "PMOVSXBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(32<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1742 = PMOVSXBWrm
+ { 1743, 2, 1, 0, "PMOVSXBWrr", 0, 0|5|(1<<6)|(13<<8)|(32<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1743 = PMOVSXBWrr
+ { 1744, 6, 1, 0, "PMOVSXDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(37<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1744 = PMOVSXDQrm
+ { 1745, 2, 1, 0, "PMOVSXDQrr", 0, 0|5|(1<<6)|(13<<8)|(37<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1745 = PMOVSXDQrr
+ { 1746, 6, 1, 0, "PMOVSXWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(35<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1746 = PMOVSXWDrm
+ { 1747, 2, 1, 0, "PMOVSXWDrr", 0, 0|5|(1<<6)|(13<<8)|(35<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1747 = PMOVSXWDrr
+ { 1748, 6, 1, 0, "PMOVSXWQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(36<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1748 = PMOVSXWQrm
+ { 1749, 2, 1, 0, "PMOVSXWQrr", 0, 0|5|(1<<6)|(13<<8)|(36<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1749 = PMOVSXWQrr
+ { 1750, 6, 1, 0, "PMOVZXBDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(49<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1750 = PMOVZXBDrm
+ { 1751, 2, 1, 0, "PMOVZXBDrr", 0, 0|5|(1<<6)|(13<<8)|(49<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1751 = PMOVZXBDrr
+ { 1752, 6, 1, 0, "PMOVZXBQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(50<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1752 = PMOVZXBQrm
+ { 1753, 2, 1, 0, "PMOVZXBQrr", 0, 0|5|(1<<6)|(13<<8)|(50<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1753 = PMOVZXBQrr
+ { 1754, 6, 1, 0, "PMOVZXBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(48<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1754 = PMOVZXBWrm
+ { 1755, 2, 1, 0, "PMOVZXBWrr", 0, 0|5|(1<<6)|(13<<8)|(48<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1755 = PMOVZXBWrr
+ { 1756, 6, 1, 0, "PMOVZXDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(53<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1756 = PMOVZXDQrm
+ { 1757, 2, 1, 0, "PMOVZXDQrr", 0, 0|5|(1<<6)|(13<<8)|(53<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1757 = PMOVZXDQrr
+ { 1758, 6, 1, 0, "PMOVZXWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(51<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1758 = PMOVZXWDrm
+ { 1759, 2, 1, 0, "PMOVZXWDrr", 0, 0|5|(1<<6)|(13<<8)|(51<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1759 = PMOVZXWDrr
+ { 1760, 6, 1, 0, "PMOVZXWQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(52<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1760 = PMOVZXWQrm
+ { 1761, 2, 1, 0, "PMOVZXWQrr", 0, 0|5|(1<<6)|(13<<8)|(52<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1761 = PMOVZXWQrr
+ { 1762, 7, 1, 0, "PMULDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(40<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1762 = PMULDQrm
+ { 1763, 3, 1, 0, "PMULDQrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(40<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1763 = PMULDQrr
+ { 1764, 7, 1, 0, "PMULHRSWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1764 = PMULHRSWrm128
+ { 1765, 7, 1, 0, "PMULHRSWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1765 = PMULHRSWrm64
+ { 1766, 3, 1, 0, "PMULHRSWrr128", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1766 = PMULHRSWrr128
+ { 1767, 3, 1, 0, "PMULHRSWrr64", 0|(1<<TID::Commutable), 0|5|(13<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1767 = PMULHRSWrr64
+ { 1768, 7, 1, 0, "PMULHUWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(228<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1768 = PMULHUWrm
+ { 1769, 3, 1, 0, "PMULHUWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(228<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1769 = PMULHUWrr
+ { 1770, 7, 1, 0, "PMULHWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(229<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1770 = PMULHWrm
+ { 1771, 3, 1, 0, "PMULHWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(229<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1771 = PMULHWrr
+ { 1772, 7, 1, 0, "PMULLDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(64<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1772 = PMULLDrm
+ { 1773, 7, 1, 0, "PMULLDrm_int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(64<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1773 = PMULLDrm_int
+ { 1774, 3, 1, 0, "PMULLDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(64<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1774 = PMULLDrr
+ { 1775, 3, 1, 0, "PMULLDrr_int", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(64<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1775 = PMULLDrr_int
+ { 1776, 7, 1, 0, "PMULLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(213<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1776 = PMULLWrm
+ { 1777, 3, 1, 0, "PMULLWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(213<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1777 = PMULLWrr
+ { 1778, 7, 1, 0, "PMULUDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(244<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1778 = PMULUDQrm
+ { 1779, 3, 1, 0, "PMULUDQrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(244<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1779 = PMULUDQrr
+ { 1780, 1, 1, 0, "POP16r", 0|(1<<TID::MayLoad), 0|2|(1<<6)|(88<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo93 }, // Inst #1780 = POP16r
+ { 1781, 5, 1, 0, "POP16rmm", 0|(1<<TID::MayLoad), 0|24|(1<<6)|(143<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo30 }, // Inst #1781 = POP16rmm
+ { 1782, 1, 1, 0, "POP16rmr", 0|(1<<TID::MayLoad), 0|16|(1<<6)|(143<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo93 }, // Inst #1782 = POP16rmr
+ { 1783, 1, 1, 0, "POP32r", 0|(1<<TID::MayLoad), 0|2|(88<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo57 }, // Inst #1783 = POP32r
+ { 1784, 5, 1, 0, "POP32rmm", 0|(1<<TID::MayLoad), 0|24|(143<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo30 }, // Inst #1784 = POP32rmm
+ { 1785, 1, 1, 0, "POP32rmr", 0|(1<<TID::MayLoad), 0|16|(143<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo57 }, // Inst #1785 = POP32rmr
+ { 1786, 1, 1, 0, "POP64r", 0|(1<<TID::MayLoad), 0|2|(88<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo58 }, // Inst #1786 = POP64r
+ { 1787, 5, 1, 0, "POP64rmm", 0|(1<<TID::MayLoad), 0|24|(143<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo30 }, // Inst #1787 = POP64rmm
+ { 1788, 1, 1, 0, "POP64rmr", 0|(1<<TID::MayLoad), 0|16|(143<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo58 }, // Inst #1788 = POP64rmr
+ { 1789, 6, 1, 0, "POPCNT16rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(12<<8)|(184<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1789 = POPCNT16rm
+ { 1790, 2, 1, 0, "POPCNT16rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(12<<8)|(184<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #1790 = POPCNT16rr
+ { 1791, 6, 1, 0, "POPCNT32rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(12<<8)|(184<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1791 = POPCNT32rm
+ { 1792, 2, 1, 0, "POPCNT32rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(12<<8)|(184<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #1792 = POPCNT32rr
+ { 1793, 6, 1, 0, "POPCNT64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(12<<8)|(1<<12)|(184<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1793 = POPCNT64rm
+ { 1794, 2, 1, 0, "POPCNT64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(12<<8)|(1<<12)|(184<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #1794 = POPCNT64rr
+ { 1795, 0, 0, 0, "POPF", 0|(1<<TID::MayLoad), 0|1|(1<<6)|(157<<24), ImplicitList2, ImplicitList3, Barriers1, 0 }, // Inst #1795 = POPF
+ { 1796, 0, 0, 0, "POPFD", 0|(1<<TID::MayLoad), 0|1|(157<<24), ImplicitList2, ImplicitList3, Barriers1, 0 }, // Inst #1796 = POPFD
+ { 1797, 0, 0, 0, "POPFQ", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(157<<24), ImplicitList4, ImplicitList5, Barriers1, 0 }, // Inst #1797 = POPFQ
+ { 1798, 0, 0, 0, "POPFS16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<8)|(161<<24), NULL, NULL, NULL, 0 }, // Inst #1798 = POPFS16
+ { 1799, 0, 0, 0, "POPFS32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(161<<24), NULL, NULL, NULL, 0 }, // Inst #1799 = POPFS32
+ { 1800, 0, 0, 0, "POPFS64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(161<<24), NULL, NULL, NULL, 0 }, // Inst #1800 = POPFS64
+ { 1801, 0, 0, 0, "POPGS16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<8)|(169<<24), NULL, NULL, NULL, 0 }, // Inst #1801 = POPGS16
+ { 1802, 0, 0, 0, "POPGS32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(169<<24), NULL, NULL, NULL, 0 }, // Inst #1802 = POPGS32
+ { 1803, 0, 0, 0, "POPGS64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(169<<24), NULL, NULL, NULL, 0 }, // Inst #1803 = POPGS64
+ { 1804, 7, 1, 0, "PORrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(235<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1804 = PORrm
+ { 1805, 3, 1, 0, "PORrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(235<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1805 = PORrr
+ { 1806, 5, 0, 0, "PREFETCHNTA", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<8)|(24<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1806 = PREFETCHNTA
+ { 1807, 5, 0, 0, "PREFETCHT0", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<8)|(24<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1807 = PREFETCHT0
+ { 1808, 5, 0, 0, "PREFETCHT1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<8)|(24<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1808 = PREFETCHT1
+ { 1809, 5, 0, 0, "PREFETCHT2", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<8)|(24<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1809 = PREFETCHT2
+ { 1810, 7, 1, 0, "PSADBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(246<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1810 = PSADBWrm
+ { 1811, 3, 1, 0, "PSADBWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(246<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1811 = PSADBWrr
+ { 1812, 7, 1, 0, "PSHUFBrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13), NULL, NULL, NULL, OperandInfo24 }, // Inst #1812 = PSHUFBrm128
+ { 1813, 7, 1, 0, "PSHUFBrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13), NULL, NULL, NULL, OperandInfo136 }, // Inst #1813 = PSHUFBrm64
+ { 1814, 3, 1, 0, "PSHUFBrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13), NULL, NULL, NULL, OperandInfo25 }, // Inst #1814 = PSHUFBrr128
+ { 1815, 3, 1, 0, "PSHUFBrr64", 0, 0|5|(13<<8)|(1<<13), NULL, NULL, NULL, OperandInfo137 }, // Inst #1815 = PSHUFBrr64
+ { 1816, 7, 1, 0, "PSHUFDmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo187 }, // Inst #1816 = PSHUFDmi
+ { 1817, 3, 1, 0, "PSHUFDri", 0, 0|5|(1<<6)|(1<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo188 }, // Inst #1817 = PSHUFDri
+ { 1818, 7, 1, 0, "PSHUFHWmi", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo187 }, // Inst #1818 = PSHUFHWmi
+ { 1819, 3, 1, 0, "PSHUFHWri", 0, 0|5|(12<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo188 }, // Inst #1819 = PSHUFHWri
+ { 1820, 7, 1, 0, "PSHUFLWmi", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo187 }, // Inst #1820 = PSHUFLWmi
+ { 1821, 3, 1, 0, "PSHUFLWri", 0, 0|5|(11<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo188 }, // Inst #1821 = PSHUFLWri
+ { 1822, 7, 1, 0, "PSIGNBrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1822 = PSIGNBrm128
+ { 1823, 7, 1, 0, "PSIGNBrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1823 = PSIGNBrm64
+ { 1824, 3, 1, 0, "PSIGNBrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1824 = PSIGNBrr128
+ { 1825, 3, 1, 0, "PSIGNBrr64", 0, 0|5|(13<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1825 = PSIGNBrr64
+ { 1826, 7, 1, 0, "PSIGNDrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1826 = PSIGNDrm128
+ { 1827, 7, 1, 0, "PSIGNDrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1827 = PSIGNDrm64
+ { 1828, 3, 1, 0, "PSIGNDrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1828 = PSIGNDrr128
+ { 1829, 3, 1, 0, "PSIGNDrr64", 0, 0|5|(13<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1829 = PSIGNDrr64
+ { 1830, 7, 1, 0, "PSIGNWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1830 = PSIGNWrm128
+ { 1831, 7, 1, 0, "PSIGNWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1831 = PSIGNWrm64
+ { 1832, 3, 1, 0, "PSIGNWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1832 = PSIGNWrr128
+ { 1833, 3, 1, 0, "PSIGNWrr64", 0, 0|5|(13<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1833 = PSIGNWrr64
+ { 1834, 3, 1, 0, "PSLLDQri", 0, 0|23|(1<<6)|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo193 }, // Inst #1834 = PSLLDQri
+ { 1835, 3, 1, 0, "PSLLDri", 0, 0|22|(1<<6)|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo193 }, // Inst #1835 = PSLLDri
+ { 1836, 7, 1, 0, "PSLLDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(242<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1836 = PSLLDrm
+ { 1837, 3, 1, 0, "PSLLDrr", 0, 0|5|(1<<6)|(1<<8)|(242<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1837 = PSLLDrr
+ { 1838, 3, 1, 0, "PSLLQri", 0, 0|22|(1<<6)|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo193 }, // Inst #1838 = PSLLQri
+ { 1839, 7, 1, 0, "PSLLQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(243<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1839 = PSLLQrm
+ { 1840, 3, 1, 0, "PSLLQrr", 0, 0|5|(1<<6)|(1<<8)|(243<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1840 = PSLLQrr
+ { 1841, 3, 1, 0, "PSLLWri", 0, 0|22|(1<<6)|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo193 }, // Inst #1841 = PSLLWri
+ { 1842, 7, 1, 0, "PSLLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(241<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1842 = PSLLWrm
+ { 1843, 3, 1, 0, "PSLLWrr", 0, 0|5|(1<<6)|(1<<8)|(241<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1843 = PSLLWrr
+ { 1844, 3, 1, 0, "PSRADri", 0, 0|20|(1<<6)|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo193 }, // Inst #1844 = PSRADri
+ { 1845, 7, 1, 0, "PSRADrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(226<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1845 = PSRADrm
+ { 1846, 3, 1, 0, "PSRADrr", 0, 0|5|(1<<6)|(1<<8)|(226<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1846 = PSRADrr
+ { 1847, 3, 1, 0, "PSRAWri", 0, 0|20|(1<<6)|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo193 }, // Inst #1847 = PSRAWri
+ { 1848, 7, 1, 0, "PSRAWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(225<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1848 = PSRAWrm
+ { 1849, 3, 1, 0, "PSRAWrr", 0, 0|5|(1<<6)|(1<<8)|(225<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1849 = PSRAWrr
+ { 1850, 3, 1, 0, "PSRLDQri", 0, 0|19|(1<<6)|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo193 }, // Inst #1850 = PSRLDQri
+ { 1851, 3, 1, 0, "PSRLDri", 0, 0|18|(1<<6)|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo193 }, // Inst #1851 = PSRLDri
+ { 1852, 7, 1, 0, "PSRLDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(210<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1852 = PSRLDrm
+ { 1853, 3, 1, 0, "PSRLDrr", 0, 0|5|(1<<6)|(1<<8)|(210<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1853 = PSRLDrr
+ { 1854, 3, 1, 0, "PSRLQri", 0, 0|18|(1<<6)|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo193 }, // Inst #1854 = PSRLQri
+ { 1855, 7, 1, 0, "PSRLQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(211<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1855 = PSRLQrm
+ { 1856, 3, 1, 0, "PSRLQrr", 0, 0|5|(1<<6)|(1<<8)|(211<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1856 = PSRLQrr
+ { 1857, 3, 1, 0, "PSRLWri", 0, 0|18|(1<<6)|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo193 }, // Inst #1857 = PSRLWri
+ { 1858, 7, 1, 0, "PSRLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(209<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1858 = PSRLWrm
+ { 1859, 3, 1, 0, "PSRLWrr", 0, 0|5|(1<<6)|(1<<8)|(209<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1859 = PSRLWrr
+ { 1860, 7, 1, 0, "PSUBBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(248<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1860 = PSUBBrm
+ { 1861, 3, 1, 0, "PSUBBrr", 0, 0|5|(1<<6)|(1<<8)|(248<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1861 = PSUBBrr
+ { 1862, 7, 1, 0, "PSUBDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(250<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1862 = PSUBDrm
+ { 1863, 3, 1, 0, "PSUBDrr", 0, 0|5|(1<<6)|(1<<8)|(250<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1863 = PSUBDrr
+ { 1864, 7, 1, 0, "PSUBQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(251<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1864 = PSUBQrm
+ { 1865, 3, 1, 0, "PSUBQrr", 0, 0|5|(1<<6)|(1<<8)|(251<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1865 = PSUBQrr
+ { 1866, 7, 1, 0, "PSUBSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(232<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1866 = PSUBSBrm
+ { 1867, 3, 1, 0, "PSUBSBrr", 0, 0|5|(1<<6)|(1<<8)|(232<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1867 = PSUBSBrr
+ { 1868, 7, 1, 0, "PSUBSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(233<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1868 = PSUBSWrm
+ { 1869, 3, 1, 0, "PSUBSWrr", 0, 0|5|(1<<6)|(1<<8)|(233<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1869 = PSUBSWrr
+ { 1870, 7, 1, 0, "PSUBUSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(216<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1870 = PSUBUSBrm
+ { 1871, 3, 1, 0, "PSUBUSBrr", 0, 0|5|(1<<6)|(1<<8)|(216<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1871 = PSUBUSBrr
+ { 1872, 7, 1, 0, "PSUBUSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(217<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1872 = PSUBUSWrm
+ { 1873, 3, 1, 0, "PSUBUSWrr", 0, 0|5|(1<<6)|(1<<8)|(217<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1873 = PSUBUSWrr
+ { 1874, 7, 1, 0, "PSUBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(249<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1874 = PSUBWrm
+ { 1875, 3, 1, 0, "PSUBWrr", 0, 0|5|(1<<6)|(1<<8)|(249<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1875 = PSUBWrr
+ { 1876, 6, 0, 0, "PTESTrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(23<<24), NULL, ImplicitList1, Barriers1, OperandInfo74 }, // Inst #1876 = PTESTrm
+ { 1877, 2, 0, 0, "PTESTrr", 0, 0|5|(1<<6)|(13<<8)|(23<<24), NULL, ImplicitList1, Barriers1, OperandInfo75 }, // Inst #1877 = PTESTrr
+ { 1878, 7, 1, 0, "PUNPCKHBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(104<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1878 = PUNPCKHBWrm
+ { 1879, 3, 1, 0, "PUNPCKHBWrr", 0, 0|5|(1<<6)|(1<<8)|(104<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1879 = PUNPCKHBWrr
+ { 1880, 7, 1, 0, "PUNPCKHDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(106<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1880 = PUNPCKHDQrm
+ { 1881, 3, 1, 0, "PUNPCKHDQrr", 0, 0|5|(1<<6)|(1<<8)|(106<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1881 = PUNPCKHDQrr
+ { 1882, 7, 1, 0, "PUNPCKHQDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(109<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1882 = PUNPCKHQDQrm
+ { 1883, 3, 1, 0, "PUNPCKHQDQrr", 0, 0|5|(1<<6)|(1<<8)|(109<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1883 = PUNPCKHQDQrr
+ { 1884, 7, 1, 0, "PUNPCKHWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(105<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1884 = PUNPCKHWDrm
+ { 1885, 3, 1, 0, "PUNPCKHWDrr", 0, 0|5|(1<<6)|(1<<8)|(105<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1885 = PUNPCKHWDrr
+ { 1886, 7, 1, 0, "PUNPCKLBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(96<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1886 = PUNPCKLBWrm
+ { 1887, 3, 1, 0, "PUNPCKLBWrr", 0, 0|5|(1<<6)|(1<<8)|(96<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1887 = PUNPCKLBWrr
+ { 1888, 7, 1, 0, "PUNPCKLDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(98<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1888 = PUNPCKLDQrm
+ { 1889, 3, 1, 0, "PUNPCKLDQrr", 0, 0|5|(1<<6)|(1<<8)|(98<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1889 = PUNPCKLDQrr
+ { 1890, 7, 1, 0, "PUNPCKLQDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(108<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1890 = PUNPCKLQDQrm
+ { 1891, 3, 1, 0, "PUNPCKLQDQrr", 0, 0|5|(1<<6)|(1<<8)|(108<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1891 = PUNPCKLQDQrr
+ { 1892, 7, 1, 0, "PUNPCKLWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(97<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1892 = PUNPCKLWDrm
+ { 1893, 3, 1, 0, "PUNPCKLWDrr", 0, 0|5|(1<<6)|(1<<8)|(97<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1893 = PUNPCKLWDrr
+ { 1894, 1, 0, 0, "PUSH16r", 0|(1<<TID::MayStore), 0|2|(1<<6)|(80<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo93 }, // Inst #1894 = PUSH16r
+ { 1895, 5, 0, 0, "PUSH16rmm", 0|(1<<TID::MayStore), 0|30|(1<<6)|(255<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo30 }, // Inst #1895 = PUSH16rmm
+ { 1896, 1, 0, 0, "PUSH16rmr", 0|(1<<TID::MayStore), 0|22|(1<<6)|(255<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo93 }, // Inst #1896 = PUSH16rmr
+ { 1897, 1, 0, 0, "PUSH32i16", 0|(1<<TID::MayStore), 0|1|(3<<13)|(104<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo5 }, // Inst #1897 = PUSH32i16
+ { 1898, 1, 0, 0, "PUSH32i32", 0|(1<<TID::MayStore), 0|1|(4<<13)|(104<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo5 }, // Inst #1898 = PUSH32i32
+ { 1899, 1, 0, 0, "PUSH32i8", 0|(1<<TID::MayStore), 0|1|(1<<13)|(106<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo5 }, // Inst #1899 = PUSH32i8
+ { 1900, 1, 0, 0, "PUSH32r", 0|(1<<TID::MayStore), 0|2|(80<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo57 }, // Inst #1900 = PUSH32r
+ { 1901, 5, 0, 0, "PUSH32rmm", 0|(1<<TID::MayStore), 0|30|(255<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo30 }, // Inst #1901 = PUSH32rmm
+ { 1902, 1, 0, 0, "PUSH32rmr", 0|(1<<TID::MayStore), 0|22|(255<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo57 }, // Inst #1902 = PUSH32rmr
+ { 1903, 1, 0, 0, "PUSH64i16", 0|(1<<TID::MayStore), 0|1|(3<<13)|(104<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo5 }, // Inst #1903 = PUSH64i16
+ { 1904, 1, 0, 0, "PUSH64i32", 0|(1<<TID::MayStore), 0|1|(4<<13)|(104<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo5 }, // Inst #1904 = PUSH64i32
+ { 1905, 1, 0, 0, "PUSH64i8", 0|(1<<TID::MayStore), 0|1|(1<<13)|(106<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo5 }, // Inst #1905 = PUSH64i8
+ { 1906, 1, 0, 0, "PUSH64r", 0|(1<<TID::MayStore), 0|2|(80<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo58 }, // Inst #1906 = PUSH64r
+ { 1907, 5, 0, 0, "PUSH64rmm", 0|(1<<TID::MayStore), 0|30|(255<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo30 }, // Inst #1907 = PUSH64rmm
+ { 1908, 1, 0, 0, "PUSH64rmr", 0|(1<<TID::MayStore), 0|22|(255<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo58 }, // Inst #1908 = PUSH64rmr
+ { 1909, 0, 0, 0, "PUSHF", 0|(1<<TID::MayStore), 0|1|(1<<6)|(156<<24), ImplicitList3, ImplicitList2, NULL, 0 }, // Inst #1909 = PUSHF
+ { 1910, 0, 0, 0, "PUSHFD", 0|(1<<TID::MayStore), 0|1|(156<<24), ImplicitList3, ImplicitList2, NULL, 0 }, // Inst #1910 = PUSHFD
+ { 1911, 0, 0, 0, "PUSHFQ64", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|1|(156<<24), ImplicitList5, ImplicitList4, NULL, 0 }, // Inst #1911 = PUSHFQ64
+ { 1912, 0, 0, 0, "PUSHFS16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<8)|(160<<24), NULL, NULL, NULL, 0 }, // Inst #1912 = PUSHFS16
+ { 1913, 0, 0, 0, "PUSHFS32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(160<<24), NULL, NULL, NULL, 0 }, // Inst #1913 = PUSHFS32
+ { 1914, 0, 0, 0, "PUSHFS64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(160<<24), NULL, NULL, NULL, 0 }, // Inst #1914 = PUSHFS64
+ { 1915, 0, 0, 0, "PUSHGS16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<8)|(168<<24), NULL, NULL, NULL, 0 }, // Inst #1915 = PUSHGS16
+ { 1916, 0, 0, 0, "PUSHGS32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(168<<24), NULL, NULL, NULL, 0 }, // Inst #1916 = PUSHGS32
+ { 1917, 0, 0, 0, "PUSHGS64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(168<<24), NULL, NULL, NULL, 0 }, // Inst #1917 = PUSHGS64
+ { 1918, 7, 1, 0, "PXORrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1918 = PXORrm
+ { 1919, 3, 1, 0, "PXORrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1919 = PXORrr
+ { 1920, 5, 0, 0, "RCL16m1", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1920 = RCL16m1
+ { 1921, 5, 0, 0, "RCL16mCL", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1921 = RCL16mCL
+ { 1922, 6, 0, 0, "RCL16mi", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1922 = RCL16mi
+ { 1923, 2, 1, 0, "RCL16r1", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1923 = RCL16r1
+ { 1924, 2, 1, 0, "RCL16rCL", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1924 = RCL16rCL
+ { 1925, 3, 1, 0, "RCL16ri", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1925 = RCL16ri
+ { 1926, 5, 0, 0, "RCL32m1", 0|(1<<TID::UnmodeledSideEffects), 0|26|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1926 = RCL32m1
+ { 1927, 5, 0, 0, "RCL32mCL", 0|(1<<TID::UnmodeledSideEffects), 0|26|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1927 = RCL32mCL
+ { 1928, 6, 0, 0, "RCL32mi", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1928 = RCL32mi
+ { 1929, 2, 1, 0, "RCL32r1", 0|(1<<TID::UnmodeledSideEffects), 0|18|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1929 = RCL32r1
+ { 1930, 2, 1, 0, "RCL32rCL", 0|(1<<TID::UnmodeledSideEffects), 0|18|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1930 = RCL32rCL
+ { 1931, 3, 1, 0, "RCL32ri", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1931 = RCL32ri
+ { 1932, 5, 0, 0, "RCL64m1", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1932 = RCL64m1
+ { 1933, 5, 0, 0, "RCL64mCL", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1933 = RCL64mCL
+ { 1934, 6, 0, 0, "RCL64mi", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1934 = RCL64mi
+ { 1935, 2, 1, 0, "RCL64r1", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #1935 = RCL64r1
+ { 1936, 2, 1, 0, "RCL64rCL", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #1936 = RCL64rCL
+ { 1937, 3, 1, 0, "RCL64ri", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1937 = RCL64ri
+ { 1938, 5, 0, 0, "RCL8m1", 0|(1<<TID::UnmodeledSideEffects), 0|26|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1938 = RCL8m1
+ { 1939, 5, 0, 0, "RCL8mCL", 0|(1<<TID::UnmodeledSideEffects), 0|26|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1939 = RCL8mCL
+ { 1940, 6, 0, 0, "RCL8mi", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1940 = RCL8mi
+ { 1941, 2, 1, 0, "RCL8r1", 0|(1<<TID::UnmodeledSideEffects), 0|18|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #1941 = RCL8r1
+ { 1942, 2, 1, 0, "RCL8rCL", 0|(1<<TID::UnmodeledSideEffects), 0|18|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #1942 = RCL8rCL
+ { 1943, 3, 1, 0, "RCL8ri", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1943 = RCL8ri
+ { 1944, 6, 1, 0, "RCPPSm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(83<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1944 = RCPPSm
+ { 1945, 6, 1, 0, "RCPPSm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(83<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1945 = RCPPSm_Int
+ { 1946, 2, 1, 0, "RCPPSr", 0, 0|5|(1<<8)|(83<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1946 = RCPPSr
+ { 1947, 2, 1, 0, "RCPPSr_Int", 0, 0|5|(1<<8)|(83<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1947 = RCPPSr_Int
+ { 1948, 6, 1, 0, "RCPSSm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(83<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #1948 = RCPSSm
+ { 1949, 6, 1, 0, "RCPSSm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(83<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1949 = RCPSSm_Int
+ { 1950, 2, 1, 0, "RCPSSr", 0, 0|5|(12<<8)|(83<<24), NULL, NULL, NULL, OperandInfo106 }, // Inst #1950 = RCPSSr
+ { 1951, 2, 1, 0, "RCPSSr_Int", 0, 0|5|(12<<8)|(83<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1951 = RCPSSr_Int
+ { 1952, 5, 0, 0, "RCR16m1", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1952 = RCR16m1
+ { 1953, 5, 0, 0, "RCR16mCL", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1953 = RCR16mCL
+ { 1954, 6, 0, 0, "RCR16mi", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1954 = RCR16mi
+ { 1955, 2, 1, 0, "RCR16r1", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1955 = RCR16r1
+ { 1956, 2, 1, 0, "RCR16rCL", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1956 = RCR16rCL
+ { 1957, 3, 1, 0, "RCR16ri", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1957 = RCR16ri
+ { 1958, 5, 0, 0, "RCR32m1", 0|(1<<TID::UnmodeledSideEffects), 0|27|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1958 = RCR32m1
+ { 1959, 5, 0, 0, "RCR32mCL", 0|(1<<TID::UnmodeledSideEffects), 0|27|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1959 = RCR32mCL
+ { 1960, 6, 0, 0, "RCR32mi", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1960 = RCR32mi
+ { 1961, 2, 1, 0, "RCR32r1", 0|(1<<TID::UnmodeledSideEffects), 0|19|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1961 = RCR32r1
+ { 1962, 2, 1, 0, "RCR32rCL", 0|(1<<TID::UnmodeledSideEffects), 0|19|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1962 = RCR32rCL
+ { 1963, 3, 1, 0, "RCR32ri", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1963 = RCR32ri
+ { 1964, 5, 0, 0, "RCR64m1", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1964 = RCR64m1
+ { 1965, 5, 0, 0, "RCR64mCL", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1965 = RCR64mCL
+ { 1966, 6, 0, 0, "RCR64mi", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1966 = RCR64mi
+ { 1967, 2, 1, 0, "RCR64r1", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #1967 = RCR64r1
+ { 1968, 2, 1, 0, "RCR64rCL", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #1968 = RCR64rCL
+ { 1969, 3, 1, 0, "RCR64ri", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1969 = RCR64ri
+ { 1970, 5, 0, 0, "RCR8m1", 0|(1<<TID::UnmodeledSideEffects), 0|27|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1970 = RCR8m1
+ { 1971, 5, 0, 0, "RCR8mCL", 0|(1<<TID::UnmodeledSideEffects), 0|27|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1971 = RCR8mCL
+ { 1972, 6, 0, 0, "RCR8mi", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1972 = RCR8mi
+ { 1973, 2, 1, 0, "RCR8r1", 0|(1<<TID::UnmodeledSideEffects), 0|19|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #1973 = RCR8r1
+ { 1974, 2, 1, 0, "RCR8rCL", 0|(1<<TID::UnmodeledSideEffects), 0|19|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #1974 = RCR8rCL
+ { 1975, 3, 1, 0, "RCR8ri", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1975 = RCR8ri
+ { 1976, 0, 0, 0, "RDMSR", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(50<<24), NULL, NULL, NULL, 0 }, // Inst #1976 = RDMSR
+ { 1977, 0, 0, 0, "RDPMC", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(51<<24), NULL, NULL, NULL, 0 }, // Inst #1977 = RDPMC
+ { 1978, 0, 0, 0, "RDTSC", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(49<<24), NULL, ImplicitList19, NULL, 0 }, // Inst #1978 = RDTSC
+ { 1979, 0, 0, 0, "RDTSCP", 0|(1<<TID::UnmodeledSideEffects), 0|42|(1<<8)|(1<<24), NULL, ImplicitList45, NULL, 0 }, // Inst #1979 = RDTSCP
+ { 1980, 0, 0, 0, "REPNE_PREFIX", 0|(1<<TID::UnmodeledSideEffects), 0|1|(242<<24), ImplicitList42, ImplicitList27, NULL, 0 }, // Inst #1980 = REPNE_PREFIX
+ { 1981, 0, 0, 0, "REP_MOVSB", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|1|(2<<8)|(164<<24), ImplicitList46, ImplicitList46, NULL, 0 }, // Inst #1981 = REP_MOVSB
+ { 1982, 0, 0, 0, "REP_MOVSD", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|1|(2<<8)|(165<<24), ImplicitList46, ImplicitList46, NULL, 0 }, // Inst #1982 = REP_MOVSD
+ { 1983, 0, 0, 0, "REP_MOVSQ", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|1|(2<<8)|(1<<12)|(165<<24), ImplicitList47, ImplicitList47, NULL, 0 }, // Inst #1983 = REP_MOVSQ
+ { 1984, 0, 0, 0, "REP_MOVSW", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|1|(1<<6)|(2<<8)|(165<<24), ImplicitList46, ImplicitList46, NULL, 0 }, // Inst #1984 = REP_MOVSW
+ { 1985, 0, 0, 0, "REP_PREFIX", 0|(1<<TID::UnmodeledSideEffects), 0|1|(243<<24), ImplicitList42, ImplicitList27, NULL, 0 }, // Inst #1985 = REP_PREFIX
+ { 1986, 0, 0, 0, "REP_STOSB", 0|(1<<TID::MayStore), 0|1|(2<<8)|(170<<24), ImplicitList48, ImplicitList49, NULL, 0 }, // Inst #1986 = REP_STOSB
+ { 1987, 0, 0, 0, "REP_STOSD", 0|(1<<TID::MayStore), 0|1|(2<<8)|(171<<24), ImplicitList50, ImplicitList49, NULL, 0 }, // Inst #1987 = REP_STOSD
+ { 1988, 0, 0, 0, "REP_STOSQ", 0|(1<<TID::MayStore), 0|1|(2<<8)|(1<<12)|(171<<24), ImplicitList51, ImplicitList52, NULL, 0 }, // Inst #1988 = REP_STOSQ
+ { 1989, 0, 0, 0, "REP_STOSW", 0|(1<<TID::MayStore), 0|1|(1<<6)|(2<<8)|(171<<24), ImplicitList53, ImplicitList49, NULL, 0 }, // Inst #1989 = REP_STOSW
+ { 1990, 0, 0, 0, "RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::Variadic), 0|1|(7<<16)|(195<<24), NULL, NULL, NULL, 0 }, // Inst #1990 = RET
+ { 1991, 1, 0, 0, "RETI", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::Variadic), 0|1|(3<<13)|(7<<16)|(194<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1991 = RETI
+ { 1992, 5, 0, 0, "ROL16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1992 = ROL16m1
+ { 1993, 5, 0, 0, "ROL16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1993 = ROL16mCL
+ { 1994, 6, 0, 0, "ROL16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1994 = ROL16mi
+ { 1995, 2, 1, 0, "ROL16r1", 0, 0|16|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1995 = ROL16r1
+ { 1996, 2, 1, 0, "ROL16rCL", 0, 0|16|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1996 = ROL16rCL
+ { 1997, 3, 1, 0, "ROL16ri", 0, 0|16|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1997 = ROL16ri
+ { 1998, 5, 0, 0, "ROL32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1998 = ROL32m1
+ { 1999, 5, 0, 0, "ROL32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1999 = ROL32mCL
+ { 2000, 6, 0, 0, "ROL32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2000 = ROL32mi
+ { 2001, 2, 1, 0, "ROL32r1", 0, 0|16|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2001 = ROL32r1
+ { 2002, 2, 1, 0, "ROL32rCL", 0, 0|16|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2002 = ROL32rCL
+ { 2003, 3, 1, 0, "ROL32ri", 0, 0|16|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2003 = ROL32ri
+ { 2004, 5, 0, 0, "ROL64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2004 = ROL64m1
+ { 2005, 5, 0, 0, "ROL64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2005 = ROL64mCL
+ { 2006, 6, 0, 0, "ROL64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2006 = ROL64mi
+ { 2007, 2, 1, 0, "ROL64r1", 0, 0|16|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2007 = ROL64r1
+ { 2008, 2, 1, 0, "ROL64rCL", 0, 0|16|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2008 = ROL64rCL
+ { 2009, 3, 1, 0, "ROL64ri", 0, 0|16|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2009 = ROL64ri
+ { 2010, 5, 0, 0, "ROL8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2010 = ROL8m1
+ { 2011, 5, 0, 0, "ROL8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2011 = ROL8mCL
+ { 2012, 6, 0, 0, "ROL8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2012 = ROL8mi
+ { 2013, 2, 1, 0, "ROL8r1", 0, 0|16|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2013 = ROL8r1
+ { 2014, 2, 1, 0, "ROL8rCL", 0, 0|16|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2014 = ROL8rCL
+ { 2015, 3, 1, 0, "ROL8ri", 0, 0|16|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2015 = ROL8ri
+ { 2016, 5, 0, 0, "ROR16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2016 = ROR16m1
+ { 2017, 5, 0, 0, "ROR16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2017 = ROR16mCL
+ { 2018, 6, 0, 0, "ROR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2018 = ROR16mi
+ { 2019, 2, 1, 0, "ROR16r1", 0, 0|17|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2019 = ROR16r1
+ { 2020, 2, 1, 0, "ROR16rCL", 0, 0|17|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2020 = ROR16rCL
+ { 2021, 3, 1, 0, "ROR16ri", 0, 0|17|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2021 = ROR16ri
+ { 2022, 5, 0, 0, "ROR32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2022 = ROR32m1
+ { 2023, 5, 0, 0, "ROR32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2023 = ROR32mCL
+ { 2024, 6, 0, 0, "ROR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2024 = ROR32mi
+ { 2025, 2, 1, 0, "ROR32r1", 0, 0|17|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2025 = ROR32r1
+ { 2026, 2, 1, 0, "ROR32rCL", 0, 0|17|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2026 = ROR32rCL
+ { 2027, 3, 1, 0, "ROR32ri", 0, 0|17|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2027 = ROR32ri
+ { 2028, 5, 0, 0, "ROR64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2028 = ROR64m1
+ { 2029, 5, 0, 0, "ROR64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2029 = ROR64mCL
+ { 2030, 6, 0, 0, "ROR64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2030 = ROR64mi
+ { 2031, 2, 1, 0, "ROR64r1", 0, 0|17|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2031 = ROR64r1
+ { 2032, 2, 1, 0, "ROR64rCL", 0, 0|17|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2032 = ROR64rCL
+ { 2033, 3, 1, 0, "ROR64ri", 0, 0|17|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2033 = ROR64ri
+ { 2034, 5, 0, 0, "ROR8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2034 = ROR8m1
+ { 2035, 5, 0, 0, "ROR8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2035 = ROR8mCL
+ { 2036, 6, 0, 0, "ROR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2036 = ROR8mi
+ { 2037, 2, 1, 0, "ROR8r1", 0, 0|17|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2037 = ROR8r1
+ { 2038, 2, 1, 0, "ROR8rCL", 0, 0|17|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2038 = ROR8rCL
+ { 2039, 3, 1, 0, "ROR8ri", 0, 0|17|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2039 = ROR8ri
+ { 2040, 7, 1, 0, "ROUNDPDm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo187 }, // Inst #2040 = ROUNDPDm_Int
+ { 2041, 3, 1, 0, "ROUNDPDr_Int", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo188 }, // Inst #2041 = ROUNDPDr_Int
+ { 2042, 7, 1, 0, "ROUNDPSm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo187 }, // Inst #2042 = ROUNDPSm_Int
+ { 2043, 3, 1, 0, "ROUNDPSr_Int", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo188 }, // Inst #2043 = ROUNDPSr_Int
+ { 2044, 8, 1, 0, "ROUNDSDm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #2044 = ROUNDSDm_Int
+ { 2045, 4, 1, 0, "ROUNDSDr_Int", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #2045 = ROUNDSDr_Int
+ { 2046, 8, 1, 0, "ROUNDSSm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #2046 = ROUNDSSm_Int
+ { 2047, 4, 1, 0, "ROUNDSSr_Int", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #2047 = ROUNDSSr_Int
+ { 2048, 0, 0, 0, "RSM", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(170<<24), NULL, NULL, NULL, 0 }, // Inst #2048 = RSM
+ { 2049, 6, 1, 0, "RSQRTPSm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(82<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2049 = RSQRTPSm
+ { 2050, 6, 1, 0, "RSQRTPSm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(82<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2050 = RSQRTPSm_Int
+ { 2051, 2, 1, 0, "RSQRTPSr", 0, 0|5|(1<<8)|(82<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2051 = RSQRTPSr
+ { 2052, 2, 1, 0, "RSQRTPSr_Int", 0, 0|5|(1<<8)|(82<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2052 = RSQRTPSr_Int
+ { 2053, 6, 1, 0, "RSQRTSSm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(82<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #2053 = RSQRTSSm
+ { 2054, 6, 1, 0, "RSQRTSSm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(82<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2054 = RSQRTSSm_Int
+ { 2055, 2, 1, 0, "RSQRTSSr", 0, 0|5|(12<<8)|(82<<24), NULL, NULL, NULL, OperandInfo106 }, // Inst #2055 = RSQRTSSr
+ { 2056, 2, 1, 0, "RSQRTSSr_Int", 0, 0|5|(12<<8)|(82<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2056 = RSQRTSSr_Int
+ { 2057, 0, 0, 0, "SAHF", 0, 0|1|(158<<24), ImplicitList28, ImplicitList1, Barriers1, 0 }, // Inst #2057 = SAHF
+ { 2058, 5, 0, 0, "SAR16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2058 = SAR16m1
+ { 2059, 5, 0, 0, "SAR16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2059 = SAR16mCL
+ { 2060, 6, 0, 0, "SAR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2060 = SAR16mi
+ { 2061, 2, 1, 0, "SAR16r1", 0, 0|23|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2061 = SAR16r1
+ { 2062, 2, 1, 0, "SAR16rCL", 0, 0|23|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2062 = SAR16rCL
+ { 2063, 3, 1, 0, "SAR16ri", 0, 0|23|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2063 = SAR16ri
+ { 2064, 5, 0, 0, "SAR32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2064 = SAR32m1
+ { 2065, 5, 0, 0, "SAR32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2065 = SAR32mCL
+ { 2066, 6, 0, 0, "SAR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2066 = SAR32mi
+ { 2067, 2, 1, 0, "SAR32r1", 0, 0|23|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2067 = SAR32r1
+ { 2068, 2, 1, 0, "SAR32rCL", 0, 0|23|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2068 = SAR32rCL
+ { 2069, 3, 1, 0, "SAR32ri", 0, 0|23|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2069 = SAR32ri
+ { 2070, 5, 0, 0, "SAR64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2070 = SAR64m1
+ { 2071, 5, 0, 0, "SAR64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2071 = SAR64mCL
+ { 2072, 6, 0, 0, "SAR64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2072 = SAR64mi
+ { 2073, 2, 1, 0, "SAR64r1", 0, 0|23|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2073 = SAR64r1
+ { 2074, 2, 1, 0, "SAR64rCL", 0, 0|23|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2074 = SAR64rCL
+ { 2075, 3, 1, 0, "SAR64ri", 0, 0|23|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2075 = SAR64ri
+ { 2076, 5, 0, 0, "SAR8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2076 = SAR8m1
+ { 2077, 5, 0, 0, "SAR8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2077 = SAR8mCL
+ { 2078, 6, 0, 0, "SAR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2078 = SAR8mi
+ { 2079, 2, 1, 0, "SAR8r1", 0, 0|23|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2079 = SAR8r1
+ { 2080, 2, 1, 0, "SAR8rCL", 0, 0|23|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2080 = SAR8rCL
+ { 2081, 3, 1, 0, "SAR8ri", 0, 0|23|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2081 = SAR8ri
+ { 2082, 1, 0, 0, "SBB16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(3<<13)|(29<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2082 = SBB16i16
+ { 2083, 6, 0, 0, "SBB16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<6)|(3<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2083 = SBB16mi
+ { 2084, 6, 0, 0, "SBB16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<6)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2084 = SBB16mi8
+ { 2085, 6, 0, 0, "SBB16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #2085 = SBB16mr
+ { 2086, 3, 1, 0, "SBB16ri", 0, 0|19|(1<<6)|(3<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2086 = SBB16ri
+ { 2087, 3, 1, 0, "SBB16ri8", 0, 0|19|(1<<6)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2087 = SBB16ri8
+ { 2088, 7, 1, 0, "SBB16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #2088 = SBB16rm
+ { 2089, 3, 1, 0, "SBB16rr", 0, 0|3|(1<<6)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2089 = SBB16rr
+ { 2090, 3, 1, 0, "SBB16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2090 = SBB16rr_REV
+ { 2091, 1, 0, 0, "SBB32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<13)|(29<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2091 = SBB32i32
+ { 2092, 6, 0, 0, "SBB32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(4<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2092 = SBB32mi
+ { 2093, 6, 0, 0, "SBB32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2093 = SBB32mi8
+ { 2094, 6, 0, 0, "SBB32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #2094 = SBB32mr
+ { 2095, 3, 1, 0, "SBB32ri", 0, 0|19|(4<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2095 = SBB32ri
+ { 2096, 3, 1, 0, "SBB32ri8", 0, 0|19|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2096 = SBB32ri8
+ { 2097, 7, 1, 0, "SBB32rm", 0|(1<<TID::MayLoad), 0|6|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #2097 = SBB32rm
+ { 2098, 3, 1, 0, "SBB32rr", 0, 0|3|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2098 = SBB32rr
+ { 2099, 3, 1, 0, "SBB32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2099 = SBB32rr_REV
+ { 2100, 1, 0, 0, "SBB64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(29<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2100 = SBB64i32
+ { 2101, 6, 0, 0, "SBB64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<12)|(4<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2101 = SBB64mi32
+ { 2102, 6, 0, 0, "SBB64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<12)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2102 = SBB64mi8
+ { 2103, 6, 0, 0, "SBB64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #2103 = SBB64mr
+ { 2104, 3, 1, 0, "SBB64ri32", 0, 0|19|(1<<12)|(4<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2104 = SBB64ri32
+ { 2105, 3, 1, 0, "SBB64ri8", 0, 0|19|(1<<12)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2105 = SBB64ri8
+ { 2106, 7, 1, 0, "SBB64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #2106 = SBB64rm
+ { 2107, 3, 1, 0, "SBB64rr", 0, 0|3|(1<<12)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2107 = SBB64rr
+ { 2108, 3, 1, 0, "SBB64rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2108 = SBB64rr_REV
+ { 2109, 1, 0, 0, "SBB8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(28<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2109 = SBB8i8
+ { 2110, 6, 0, 0, "SBB8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<13)|(128<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2110 = SBB8mi
+ { 2111, 6, 0, 0, "SBB8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(24<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #2111 = SBB8mr
+ { 2112, 3, 1, 0, "SBB8ri", 0, 0|19|(1<<13)|(128<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2112 = SBB8ri
+ { 2113, 7, 1, 0, "SBB8rm", 0|(1<<TID::MayLoad), 0|6|(26<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #2113 = SBB8rm
+ { 2114, 3, 1, 0, "SBB8rr", 0, 0|3|(24<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #2114 = SBB8rr
+ { 2115, 3, 1, 0, "SBB8rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(26<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #2115 = SBB8rr_REV
+ { 2116, 0, 0, 0, "SCAS16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(175<<24), NULL, NULL, NULL, 0 }, // Inst #2116 = SCAS16
+ { 2117, 0, 0, 0, "SCAS32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(175<<24), NULL, NULL, NULL, 0 }, // Inst #2117 = SCAS32
+ { 2118, 0, 0, 0, "SCAS64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(175<<24), NULL, NULL, NULL, 0 }, // Inst #2118 = SCAS64
+ { 2119, 0, 0, 0, "SCAS8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(174<<24), NULL, NULL, NULL, 0 }, // Inst #2119 = SCAS8
+ { 2120, 5, 0, 0, "SETAEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(147<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2120 = SETAEm
+ { 2121, 1, 1, 0, "SETAEr", 0, 0|16|(1<<8)|(147<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2121 = SETAEr
+ { 2122, 5, 0, 0, "SETAm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(151<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2122 = SETAm
+ { 2123, 1, 1, 0, "SETAr", 0, 0|16|(1<<8)|(151<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2123 = SETAr
+ { 2124, 5, 0, 0, "SETBEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(150<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2124 = SETBEm
+ { 2125, 1, 1, 0, "SETBEr", 0, 0|16|(1<<8)|(150<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2125 = SETBEr
+ { 2126, 1, 1, 0, "SETB_C16r", 0, 0|32|(1<<6)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo93 }, // Inst #2126 = SETB_C16r
+ { 2127, 1, 1, 0, "SETB_C32r", 0, 0|32|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo57 }, // Inst #2127 = SETB_C32r
+ { 2128, 1, 1, 0, "SETB_C64r", 0, 0|32|(1<<12)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo58 }, // Inst #2128 = SETB_C64r
+ { 2129, 1, 1, 0, "SETB_C8r", 0, 0|32|(24<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo94 }, // Inst #2129 = SETB_C8r
+ { 2130, 5, 0, 0, "SETBm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(146<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2130 = SETBm
+ { 2131, 1, 1, 0, "SETBr", 0, 0|16|(1<<8)|(146<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2131 = SETBr
+ { 2132, 5, 0, 0, "SETEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(148<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2132 = SETEm
+ { 2133, 1, 1, 0, "SETEr", 0, 0|16|(1<<8)|(148<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2133 = SETEr
+ { 2134, 5, 0, 0, "SETGEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(157<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2134 = SETGEm
+ { 2135, 1, 1, 0, "SETGEr", 0, 0|16|(1<<8)|(157<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2135 = SETGEr
+ { 2136, 5, 0, 0, "SETGm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(159<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2136 = SETGm
+ { 2137, 1, 1, 0, "SETGr", 0, 0|16|(1<<8)|(159<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2137 = SETGr
+ { 2138, 5, 0, 0, "SETLEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(158<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2138 = SETLEm
+ { 2139, 1, 1, 0, "SETLEr", 0, 0|16|(1<<8)|(158<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2139 = SETLEr
+ { 2140, 5, 0, 0, "SETLm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(156<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2140 = SETLm
+ { 2141, 1, 1, 0, "SETLr", 0, 0|16|(1<<8)|(156<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2141 = SETLr
+ { 2142, 5, 0, 0, "SETNEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(149<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2142 = SETNEm
+ { 2143, 1, 1, 0, "SETNEr", 0, 0|16|(1<<8)|(149<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2143 = SETNEr
+ { 2144, 5, 0, 0, "SETNOm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(145<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2144 = SETNOm
+ { 2145, 1, 1, 0, "SETNOr", 0, 0|16|(1<<8)|(145<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2145 = SETNOr
+ { 2146, 5, 0, 0, "SETNPm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(155<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2146 = SETNPm
+ { 2147, 1, 1, 0, "SETNPr", 0, 0|16|(1<<8)|(155<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2147 = SETNPr
+ { 2148, 5, 0, 0, "SETNSm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(153<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2148 = SETNSm
+ { 2149, 1, 1, 0, "SETNSr", 0, 0|16|(1<<8)|(153<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2149 = SETNSr
+ { 2150, 5, 0, 0, "SETOm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(144<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2150 = SETOm
+ { 2151, 1, 1, 0, "SETOr", 0, 0|16|(1<<8)|(144<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2151 = SETOr
+ { 2152, 5, 0, 0, "SETPm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(154<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2152 = SETPm
+ { 2153, 1, 1, 0, "SETPr", 0, 0|16|(1<<8)|(154<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2153 = SETPr
+ { 2154, 5, 0, 0, "SETSm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(152<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2154 = SETSm
+ { 2155, 1, 1, 0, "SETSr", 0, 0|16|(1<<8)|(152<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2155 = SETSr
+ { 2156, 0, 0, 0, "SFENCE", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|23|(1<<8)|(174<<24), NULL, NULL, NULL, 0 }, // Inst #2156 = SFENCE
+ { 2157, 5, 1, 0, "SGDTm", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2157 = SGDTm
+ { 2158, 5, 0, 0, "SHL16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2158 = SHL16m1
+ { 2159, 5, 0, 0, "SHL16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2159 = SHL16mCL
+ { 2160, 6, 0, 0, "SHL16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2160 = SHL16mi
+ { 2161, 2, 1, 0, "SHL16r1", 0|(1<<TID::ConvertibleTo3Addr)|(1<<TID::UnmodeledSideEffects), 0|20|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2161 = SHL16r1
+ { 2162, 2, 1, 0, "SHL16rCL", 0, 0|20|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2162 = SHL16rCL
+ { 2163, 3, 1, 0, "SHL16ri", 0|(1<<TID::ConvertibleTo3Addr), 0|20|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2163 = SHL16ri
+ { 2164, 5, 0, 0, "SHL32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2164 = SHL32m1
+ { 2165, 5, 0, 0, "SHL32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2165 = SHL32mCL
+ { 2166, 6, 0, 0, "SHL32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2166 = SHL32mi
+ { 2167, 2, 1, 0, "SHL32r1", 0|(1<<TID::ConvertibleTo3Addr)|(1<<TID::UnmodeledSideEffects), 0|20|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2167 = SHL32r1
+ { 2168, 2, 1, 0, "SHL32rCL", 0, 0|20|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2168 = SHL32rCL
+ { 2169, 3, 1, 0, "SHL32ri", 0|(1<<TID::ConvertibleTo3Addr), 0|20|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2169 = SHL32ri
+ { 2170, 5, 0, 0, "SHL64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2170 = SHL64m1
+ { 2171, 5, 0, 0, "SHL64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2171 = SHL64mCL
+ { 2172, 6, 0, 0, "SHL64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2172 = SHL64mi
+ { 2173, 2, 1, 0, "SHL64r1", 0|(1<<TID::UnmodeledSideEffects), 0|20|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2173 = SHL64r1
+ { 2174, 2, 1, 0, "SHL64rCL", 0, 0|20|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2174 = SHL64rCL
+ { 2175, 3, 1, 0, "SHL64ri", 0|(1<<TID::ConvertibleTo3Addr), 0|20|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2175 = SHL64ri
+ { 2176, 5, 0, 0, "SHL8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2176 = SHL8m1
+ { 2177, 5, 0, 0, "SHL8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2177 = SHL8mCL
+ { 2178, 6, 0, 0, "SHL8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2178 = SHL8mi
+ { 2179, 2, 1, 0, "SHL8r1", 0|(1<<TID::ConvertibleTo3Addr)|(1<<TID::UnmodeledSideEffects), 0|20|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2179 = SHL8r1
+ { 2180, 2, 1, 0, "SHL8rCL", 0, 0|20|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2180 = SHL8rCL
+ { 2181, 3, 1, 0, "SHL8ri", 0, 0|20|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2181 = SHL8ri
+ { 2182, 6, 0, 0, "SHLD16mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(165<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #2182 = SHLD16mrCL
+ { 2183, 7, 0, 0, "SHLD16mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #2183 = SHLD16mri8
+ { 2184, 3, 1, 0, "SHLD16rrCL", 0, 0|3|(1<<6)|(1<<8)|(165<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2184 = SHLD16rrCL
+ { 2185, 4, 1, 0, "SHLD16rri8", 0|(1<<TID::Commutable), 0|3|(1<<6)|(1<<8)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo195 }, // Inst #2185 = SHLD16rri8
+ { 2186, 6, 0, 0, "SHLD32mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(165<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #2186 = SHLD32mrCL
+ { 2187, 7, 0, 0, "SHLD32mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo196 }, // Inst #2187 = SHLD32mri8
+ { 2188, 3, 1, 0, "SHLD32rrCL", 0, 0|3|(1<<8)|(165<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2188 = SHLD32rrCL
+ { 2189, 4, 1, 0, "SHLD32rri8", 0|(1<<TID::Commutable), 0|3|(1<<8)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo197 }, // Inst #2189 = SHLD32rri8
+ { 2190, 6, 0, 0, "SHLD64mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<12)|(165<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #2190 = SHLD64mrCL
+ { 2191, 7, 0, 0, "SHLD64mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<12)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo198 }, // Inst #2191 = SHLD64mri8
+ { 2192, 3, 1, 0, "SHLD64rrCL", 0, 0|3|(1<<8)|(1<<12)|(165<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2192 = SHLD64rrCL
+ { 2193, 4, 1, 0, "SHLD64rri8", 0|(1<<TID::Commutable), 0|3|(1<<8)|(1<<12)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo199 }, // Inst #2193 = SHLD64rri8
+ { 2194, 5, 0, 0, "SHR16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2194 = SHR16m1
+ { 2195, 5, 0, 0, "SHR16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2195 = SHR16mCL
+ { 2196, 6, 0, 0, "SHR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2196 = SHR16mi
+ { 2197, 2, 1, 0, "SHR16r1", 0, 0|21|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2197 = SHR16r1
+ { 2198, 2, 1, 0, "SHR16rCL", 0, 0|21|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2198 = SHR16rCL
+ { 2199, 3, 1, 0, "SHR16ri", 0, 0|21|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2199 = SHR16ri
+ { 2200, 5, 0, 0, "SHR32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2200 = SHR32m1
+ { 2201, 5, 0, 0, "SHR32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2201 = SHR32mCL
+ { 2202, 6, 0, 0, "SHR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2202 = SHR32mi
+ { 2203, 2, 1, 0, "SHR32r1", 0, 0|21|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2203 = SHR32r1
+ { 2204, 2, 1, 0, "SHR32rCL", 0, 0|21|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2204 = SHR32rCL
+ { 2205, 3, 1, 0, "SHR32ri", 0, 0|21|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2205 = SHR32ri
+ { 2206, 5, 0, 0, "SHR64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2206 = SHR64m1
+ { 2207, 5, 0, 0, "SHR64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2207 = SHR64mCL
+ { 2208, 6, 0, 0, "SHR64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2208 = SHR64mi
+ { 2209, 2, 1, 0, "SHR64r1", 0, 0|21|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2209 = SHR64r1
+ { 2210, 2, 1, 0, "SHR64rCL", 0, 0|21|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2210 = SHR64rCL
+ { 2211, 3, 1, 0, "SHR64ri", 0, 0|21|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2211 = SHR64ri
+ { 2212, 5, 0, 0, "SHR8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2212 = SHR8m1
+ { 2213, 5, 0, 0, "SHR8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2213 = SHR8mCL
+ { 2214, 6, 0, 0, "SHR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2214 = SHR8mi
+ { 2215, 2, 1, 0, "SHR8r1", 0, 0|21|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2215 = SHR8r1
+ { 2216, 2, 1, 0, "SHR8rCL", 0, 0|21|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2216 = SHR8rCL
+ { 2217, 3, 1, 0, "SHR8ri", 0, 0|21|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2217 = SHR8ri
+ { 2218, 6, 0, 0, "SHRD16mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(173<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #2218 = SHRD16mrCL
+ { 2219, 7, 0, 0, "SHRD16mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #2219 = SHRD16mri8
+ { 2220, 3, 1, 0, "SHRD16rrCL", 0, 0|3|(1<<6)|(1<<8)|(173<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2220 = SHRD16rrCL
+ { 2221, 4, 1, 0, "SHRD16rri8", 0|(1<<TID::Commutable), 0|3|(1<<6)|(1<<8)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo195 }, // Inst #2221 = SHRD16rri8
+ { 2222, 6, 0, 0, "SHRD32mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(173<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #2222 = SHRD32mrCL
+ { 2223, 7, 0, 0, "SHRD32mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo196 }, // Inst #2223 = SHRD32mri8
+ { 2224, 3, 1, 0, "SHRD32rrCL", 0, 0|3|(1<<8)|(173<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2224 = SHRD32rrCL
+ { 2225, 4, 1, 0, "SHRD32rri8", 0|(1<<TID::Commutable), 0|3|(1<<8)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo197 }, // Inst #2225 = SHRD32rri8
+ { 2226, 6, 0, 0, "SHRD64mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<12)|(173<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #2226 = SHRD64mrCL
+ { 2227, 7, 0, 0, "SHRD64mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<12)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo198 }, // Inst #2227 = SHRD64mri8
+ { 2228, 3, 1, 0, "SHRD64rrCL", 0, 0|3|(1<<8)|(1<<12)|(173<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2228 = SHRD64rrCL
+ { 2229, 4, 1, 0, "SHRD64rri8", 0|(1<<TID::Commutable), 0|3|(1<<8)|(1<<12)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo199 }, // Inst #2229 = SHRD64rri8
+ { 2230, 8, 1, 0, "SHUFPDrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(1<<13)|(198<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #2230 = SHUFPDrmi
+ { 2231, 4, 1, 0, "SHUFPDrri", 0, 0|5|(1<<6)|(1<<8)|(1<<13)|(198<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #2231 = SHUFPDrri
+ { 2232, 8, 1, 0, "SHUFPSrmi", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<13)|(198<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #2232 = SHUFPSrmi
+ { 2233, 4, 1, 0, "SHUFPSrri", 0|(1<<TID::ConvertibleTo3Addr), 0|5|(1<<8)|(1<<13)|(198<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #2233 = SHUFPSrri
+ { 2234, 5, 1, 0, "SIDTm", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2234 = SIDTm
+ { 2235, 0, 0, 0, "SIN_F", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(254<<24), NULL, NULL, NULL, 0 }, // Inst #2235 = SIN_F
+ { 2236, 2, 1, 0, "SIN_Fp32", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo2 }, // Inst #2236 = SIN_Fp32
+ { 2237, 2, 1, 0, "SIN_Fp64", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo3 }, // Inst #2237 = SIN_Fp64
+ { 2238, 2, 1, 0, "SIN_Fp80", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo4 }, // Inst #2238 = SIN_Fp80
+ { 2239, 5, 1, 0, "SLDT16m", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<8), NULL, NULL, NULL, OperandInfo30 }, // Inst #2239 = SLDT16m
+ { 2240, 1, 1, 0, "SLDT16r", 0|(1<<TID::UnmodeledSideEffects), 0|16|(1<<8), NULL, NULL, NULL, OperandInfo93 }, // Inst #2240 = SLDT16r
+ { 2241, 5, 1, 0, "SLDT64m", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<8)|(1<<12), NULL, NULL, NULL, OperandInfo30 }, // Inst #2241 = SLDT64m
+ { 2242, 1, 1, 0, "SLDT64r", 0|(1<<TID::UnmodeledSideEffects), 0|16|(1<<8)|(1<<12), NULL, NULL, NULL, OperandInfo58 }, // Inst #2242 = SLDT64r
+ { 2243, 5, 1, 0, "SMSW16m", 0|(1<<TID::UnmodeledSideEffects), 0|28|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2243 = SMSW16m
+ { 2244, 1, 1, 0, "SMSW16r", 0|(1<<TID::UnmodeledSideEffects), 0|20|(1<<6)|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo93 }, // Inst #2244 = SMSW16r
+ { 2245, 1, 1, 0, "SMSW32r", 0|(1<<TID::UnmodeledSideEffects), 0|20|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo57 }, // Inst #2245 = SMSW32r
+ { 2246, 1, 1, 0, "SMSW64r", 0|(1<<TID::UnmodeledSideEffects), 0|20|(1<<8)|(1<<12)|(1<<24), NULL, NULL, NULL, OperandInfo58 }, // Inst #2246 = SMSW64r
+ { 2247, 6, 1, 0, "SQRTPDm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2247 = SQRTPDm
+ { 2248, 6, 1, 0, "SQRTPDm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2248 = SQRTPDm_Int
+ { 2249, 2, 1, 0, "SQRTPDr", 0, 0|5|(1<<6)|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2249 = SQRTPDr
+ { 2250, 2, 1, 0, "SQRTPDr_Int", 0, 0|5|(1<<6)|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2250 = SQRTPDr_Int
+ { 2251, 6, 1, 0, "SQRTPSm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2251 = SQRTPSm
+ { 2252, 6, 1, 0, "SQRTPSm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2252 = SQRTPSm_Int
+ { 2253, 2, 1, 0, "SQRTPSr", 0, 0|5|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2253 = SQRTPSr
+ { 2254, 2, 1, 0, "SQRTPSr_Int", 0, 0|5|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2254 = SQRTPSr_Int
+ { 2255, 6, 1, 0, "SQRTSDm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(81<<24), NULL, NULL, NULL, OperandInfo82 }, // Inst #2255 = SQRTSDm
+ { 2256, 6, 1, 0, "SQRTSDm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2256 = SQRTSDm_Int
+ { 2257, 2, 1, 0, "SQRTSDr", 0, 0|5|(11<<8)|(81<<24), NULL, NULL, NULL, OperandInfo105 }, // Inst #2257 = SQRTSDr
+ { 2258, 2, 1, 0, "SQRTSDr_Int", 0, 0|5|(11<<8)|(81<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2258 = SQRTSDr_Int
+ { 2259, 6, 1, 0, "SQRTSSm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(81<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #2259 = SQRTSSm
+ { 2260, 6, 1, 0, "SQRTSSm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2260 = SQRTSSm_Int
+ { 2261, 2, 1, 0, "SQRTSSr", 0, 0|5|(12<<8)|(81<<24), NULL, NULL, NULL, OperandInfo106 }, // Inst #2261 = SQRTSSr
+ { 2262, 2, 1, 0, "SQRTSSr_Int", 0, 0|5|(12<<8)|(81<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2262 = SQRTSSr_Int
+ { 2263, 0, 0, 0, "SQRT_F", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(250<<24), NULL, NULL, NULL, 0 }, // Inst #2263 = SQRT_F
+ { 2264, 2, 1, 0, "SQRT_Fp32", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo2 }, // Inst #2264 = SQRT_Fp32
+ { 2265, 2, 1, 0, "SQRT_Fp64", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo3 }, // Inst #2265 = SQRT_Fp64
+ { 2266, 2, 1, 0, "SQRT_Fp80", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo4 }, // Inst #2266 = SQRT_Fp80
+ { 2267, 0, 0, 0, "SS_PREFIX", 0|(1<<TID::UnmodeledSideEffects), 0|1|(54<<24), NULL, NULL, NULL, 0 }, // Inst #2267 = SS_PREFIX
+ { 2268, 0, 0, 0, "STC", 0|(1<<TID::UnmodeledSideEffects), 0|1|(249<<24), NULL, NULL, NULL, 0 }, // Inst #2268 = STC
+ { 2269, 0, 0, 0, "STD", 0|(1<<TID::UnmodeledSideEffects), 0|1|(253<<24), NULL, NULL, NULL, 0 }, // Inst #2269 = STD
+ { 2270, 0, 0, 0, "STI", 0|(1<<TID::UnmodeledSideEffects), 0|1|(251<<24), NULL, NULL, NULL, 0 }, // Inst #2270 = STI
+ { 2271, 5, 0, 0, "STMXCSR", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|27|(1<<8)|(174<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2271 = STMXCSR
+ { 2272, 0, 0, 0, "STOSB", 0|(1<<TID::UnmodeledSideEffects), 0|1|(170<<24), ImplicitList54, ImplicitList35, NULL, 0 }, // Inst #2272 = STOSB
+ { 2273, 0, 0, 0, "STOSD", 0|(1<<TID::UnmodeledSideEffects), 0|1|(171<<24), ImplicitList55, ImplicitList35, NULL, 0 }, // Inst #2273 = STOSD
+ { 2274, 0, 0, 0, "STOSW", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(171<<24), ImplicitList56, ImplicitList35, NULL, 0 }, // Inst #2274 = STOSW
+ { 2275, 5, 1, 0, "STRm", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<8), NULL, NULL, NULL, OperandInfo30 }, // Inst #2275 = STRm
+ { 2276, 1, 1, 0, "STRr", 0|(1<<TID::UnmodeledSideEffects), 0|17|(1<<8), NULL, NULL, NULL, OperandInfo93 }, // Inst #2276 = STRr
+ { 2277, 5, 0, 0, "ST_F32m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|26|(217<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2277 = ST_F32m
+ { 2278, 5, 0, 0, "ST_F64m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|26|(221<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2278 = ST_F64m
+ { 2279, 5, 0, 0, "ST_FP32m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|27|(217<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2279 = ST_FP32m
+ { 2280, 5, 0, 0, "ST_FP64m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|27|(221<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2280 = ST_FP64m
+ { 2281, 5, 0, 0, "ST_FP80m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|31|(219<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2281 = ST_FP80m
+ { 2282, 1, 0, 0, "ST_FPrr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(8<<8)|(216<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2282 = ST_FPrr
+ { 2283, 6, 0, 0, "ST_Fp32m", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #2283 = ST_Fp32m
+ { 2284, 6, 0, 0, "ST_Fp64m", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #2284 = ST_Fp64m
+ { 2285, 6, 0, 0, "ST_Fp64m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #2285 = ST_Fp64m32
+ { 2286, 6, 0, 0, "ST_Fp80m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #2286 = ST_Fp80m32
+ { 2287, 6, 0, 0, "ST_Fp80m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #2287 = ST_Fp80m64
+ { 2288, 6, 0, 0, "ST_FpP32m", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #2288 = ST_FpP32m
+ { 2289, 6, 0, 0, "ST_FpP64m", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #2289 = ST_FpP64m
+ { 2290, 6, 0, 0, "ST_FpP64m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #2290 = ST_FpP64m32
+ { 2291, 6, 0, 0, "ST_FpP80m", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #2291 = ST_FpP80m
+ { 2292, 6, 0, 0, "ST_FpP80m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #2292 = ST_FpP80m32
+ { 2293, 6, 0, 0, "ST_FpP80m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #2293 = ST_FpP80m64
+ { 2294, 1, 0, 0, "ST_Frr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(8<<8)|(208<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2294 = ST_Frr
+ { 2295, 1, 0, 0, "SUB16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(3<<13)|(45<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2295 = SUB16i16
+ { 2296, 6, 0, 0, "SUB16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<6)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2296 = SUB16mi
+ { 2297, 6, 0, 0, "SUB16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2297 = SUB16mi8
+ { 2298, 6, 0, 0, "SUB16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #2298 = SUB16mr
+ { 2299, 3, 1, 0, "SUB16ri", 0, 0|21|(1<<6)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2299 = SUB16ri
+ { 2300, 3, 1, 0, "SUB16ri8", 0, 0|21|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2300 = SUB16ri8
+ { 2301, 7, 1, 0, "SUB16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #2301 = SUB16rm
+ { 2302, 3, 1, 0, "SUB16rr", 0, 0|3|(1<<6)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2302 = SUB16rr
+ { 2303, 3, 1, 0, "SUB16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2303 = SUB16rr_REV
+ { 2304, 1, 0, 0, "SUB32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<13)|(45<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2304 = SUB32i32
+ { 2305, 6, 0, 0, "SUB32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2305 = SUB32mi
+ { 2306, 6, 0, 0, "SUB32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2306 = SUB32mi8
+ { 2307, 6, 0, 0, "SUB32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #2307 = SUB32mr
+ { 2308, 3, 1, 0, "SUB32ri", 0, 0|21|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2308 = SUB32ri
+ { 2309, 3, 1, 0, "SUB32ri8", 0, 0|21|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2309 = SUB32ri8
+ { 2310, 7, 1, 0, "SUB32rm", 0|(1<<TID::MayLoad), 0|6|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #2310 = SUB32rm
+ { 2311, 3, 1, 0, "SUB32rr", 0, 0|3|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2311 = SUB32rr
+ { 2312, 3, 1, 0, "SUB32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2312 = SUB32rr_REV
+ { 2313, 1, 0, 0, "SUB64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(45<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2313 = SUB64i32
+ { 2314, 6, 0, 0, "SUB64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<12)|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2314 = SUB64mi32
+ { 2315, 6, 0, 0, "SUB64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2315 = SUB64mi8
+ { 2316, 6, 0, 0, "SUB64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #2316 = SUB64mr
+ { 2317, 3, 1, 0, "SUB64ri32", 0, 0|21|(1<<12)|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2317 = SUB64ri32
+ { 2318, 3, 1, 0, "SUB64ri8", 0, 0|21|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2318 = SUB64ri8
+ { 2319, 7, 1, 0, "SUB64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #2319 = SUB64rm
+ { 2320, 3, 1, 0, "SUB64rr", 0, 0|3|(1<<12)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2320 = SUB64rr
+ { 2321, 3, 1, 0, "SUB64rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2321 = SUB64rr_REV
+ { 2322, 1, 0, 0, "SUB8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(44<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2322 = SUB8i8
+ { 2323, 6, 0, 0, "SUB8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2323 = SUB8mi
+ { 2324, 6, 0, 0, "SUB8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(40<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #2324 = SUB8mr
+ { 2325, 3, 1, 0, "SUB8ri", 0, 0|21|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2325 = SUB8ri
+ { 2326, 7, 1, 0, "SUB8rm", 0|(1<<TID::MayLoad), 0|6|(42<<24), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #2326 = SUB8rm
+ { 2327, 3, 1, 0, "SUB8rr", 0, 0|3|(40<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #2327 = SUB8rr
+ { 2328, 3, 1, 0, "SUB8rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(42<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #2328 = SUB8rr_REV
+ { 2329, 7, 1, 0, "SUBPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(92<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2329 = SUBPDrm
+ { 2330, 3, 1, 0, "SUBPDrr", 0, 0|5|(1<<6)|(1<<8)|(92<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2330 = SUBPDrr
+ { 2331, 7, 1, 0, "SUBPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(92<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2331 = SUBPSrm
+ { 2332, 3, 1, 0, "SUBPSrr", 0, 0|5|(1<<8)|(92<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2332 = SUBPSrr
+ { 2333, 5, 0, 0, "SUBR_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(216<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2333 = SUBR_F32m
+ { 2334, 5, 0, 0, "SUBR_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(220<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2334 = SUBR_F64m
+ { 2335, 5, 0, 0, "SUBR_FI16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(222<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2335 = SUBR_FI16m
+ { 2336, 5, 0, 0, "SUBR_FI32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(218<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2336 = SUBR_FI32m
+ { 2337, 1, 0, 0, "SUBR_FPrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(9<<8)|(224<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2337 = SUBR_FPrST0
+ { 2338, 1, 0, 0, "SUBR_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(232<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2338 = SUBR_FST0r
+ { 2339, 7, 1, 0, "SUBR_Fp32m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #2339 = SUBR_Fp32m
+ { 2340, 7, 1, 0, "SUBR_Fp64m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2340 = SUBR_Fp64m
+ { 2341, 7, 1, 0, "SUBR_Fp64m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2341 = SUBR_Fp64m32
+ { 2342, 7, 1, 0, "SUBR_Fp80m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2342 = SUBR_Fp80m32
+ { 2343, 7, 1, 0, "SUBR_Fp80m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2343 = SUBR_Fp80m64
+ { 2344, 7, 1, 0, "SUBR_FpI16m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #2344 = SUBR_FpI16m32
+ { 2345, 7, 1, 0, "SUBR_FpI16m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2345 = SUBR_FpI16m64
+ { 2346, 7, 1, 0, "SUBR_FpI16m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2346 = SUBR_FpI16m80
+ { 2347, 7, 1, 0, "SUBR_FpI32m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #2347 = SUBR_FpI32m32
+ { 2348, 7, 1, 0, "SUBR_FpI32m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2348 = SUBR_FpI32m64
+ { 2349, 7, 1, 0, "SUBR_FpI32m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2349 = SUBR_FpI32m80
+ { 2350, 1, 0, 0, "SUBR_FrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(7<<8)|(224<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2350 = SUBR_FrST0
+ { 2351, 7, 1, 0, "SUBSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(92<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #2351 = SUBSDrm
+ { 2352, 7, 1, 0, "SUBSDrm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(92<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2352 = SUBSDrm_Int
+ { 2353, 3, 1, 0, "SUBSDrr", 0, 0|5|(11<<8)|(92<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #2353 = SUBSDrr
+ { 2354, 3, 1, 0, "SUBSDrr_Int", 0, 0|5|(11<<8)|(92<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2354 = SUBSDrr_Int
+ { 2355, 7, 1, 0, "SUBSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(92<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #2355 = SUBSSrm
+ { 2356, 7, 1, 0, "SUBSSrm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(92<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2356 = SUBSSrm_Int
+ { 2357, 3, 1, 0, "SUBSSrr", 0, 0|5|(12<<8)|(92<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #2357 = SUBSSrr
+ { 2358, 3, 1, 0, "SUBSSrr_Int", 0, 0|5|(12<<8)|(92<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2358 = SUBSSrr_Int
+ { 2359, 5, 0, 0, "SUB_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|28|(216<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2359 = SUB_F32m
+ { 2360, 5, 0, 0, "SUB_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|28|(220<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2360 = SUB_F64m
+ { 2361, 5, 0, 0, "SUB_FI16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|28|(222<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2361 = SUB_FI16m
+ { 2362, 5, 0, 0, "SUB_FI32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|28|(218<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2362 = SUB_FI32m
+ { 2363, 1, 0, 0, "SUB_FPrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(9<<8)|(232<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2363 = SUB_FPrST0
+ { 2364, 1, 0, 0, "SUB_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(224<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2364 = SUB_FST0r
+ { 2365, 3, 1, 0, "SUB_Fp32", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #2365 = SUB_Fp32
+ { 2366, 7, 1, 0, "SUB_Fp32m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #2366 = SUB_Fp32m
+ { 2367, 3, 1, 0, "SUB_Fp64", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #2367 = SUB_Fp64
+ { 2368, 7, 1, 0, "SUB_Fp64m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2368 = SUB_Fp64m
+ { 2369, 7, 1, 0, "SUB_Fp64m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2369 = SUB_Fp64m32
+ { 2370, 3, 1, 0, "SUB_Fp80", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #2370 = SUB_Fp80
+ { 2371, 7, 1, 0, "SUB_Fp80m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2371 = SUB_Fp80m32
+ { 2372, 7, 1, 0, "SUB_Fp80m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2372 = SUB_Fp80m64
+ { 2373, 7, 1, 0, "SUB_FpI16m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #2373 = SUB_FpI16m32
+ { 2374, 7, 1, 0, "SUB_FpI16m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2374 = SUB_FpI16m64
+ { 2375, 7, 1, 0, "SUB_FpI16m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2375 = SUB_FpI16m80
+ { 2376, 7, 1, 0, "SUB_FpI32m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #2376 = SUB_FpI32m32
+ { 2377, 7, 1, 0, "SUB_FpI32m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2377 = SUB_FpI32m64
+ { 2378, 7, 1, 0, "SUB_FpI32m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2378 = SUB_FpI32m80
+ { 2379, 1, 0, 0, "SUB_FrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(7<<8)|(232<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2379 = SUB_FrST0
+ { 2380, 0, 0, 0, "SWAPGS", 0|(1<<TID::UnmodeledSideEffects), 0|41|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #2380 = SWAPGS
+ { 2381, 0, 0, 0, "SYSCALL", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(5<<24), NULL, NULL, NULL, 0 }, // Inst #2381 = SYSCALL
+ { 2382, 0, 0, 0, "SYSENTER", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(52<<24), NULL, NULL, NULL, 0 }, // Inst #2382 = SYSENTER
+ { 2383, 0, 0, 0, "SYSEXIT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(53<<24), NULL, NULL, NULL, 0 }, // Inst #2383 = SYSEXIT
+ { 2384, 0, 0, 0, "SYSEXIT64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(1<<12)|(53<<24), NULL, NULL, NULL, 0 }, // Inst #2384 = SYSEXIT64
+ { 2385, 0, 0, 0, "SYSRET", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(7<<24), NULL, NULL, NULL, 0 }, // Inst #2385 = SYSRET
+ { 2386, 1, 0, 0, "TAILJMPd", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|1|(4<<13)|(233<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #2386 = TAILJMPd
+ { 2387, 5, 0, 0, "TAILJMPm", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|28|(255<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2387 = TAILJMPm
+ { 2388, 1, 0, 0, "TAILJMPr", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|20|(255<<24), NULL, NULL, NULL, OperandInfo57 }, // Inst #2388 = TAILJMPr
+ { 2389, 1, 0, 0, "TAILJMPr64", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|20|(255<<24), NULL, NULL, NULL, OperandInfo58 }, // Inst #2389 = TAILJMPr64
+ { 2390, 2, 0, 0, "TCRETURNdi", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo38 }, // Inst #2390 = TCRETURNdi
+ { 2391, 2, 0, 0, "TCRETURNdi64", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo38 }, // Inst #2391 = TCRETURNdi64
+ { 2392, 2, 0, 0, "TCRETURNri", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo55 }, // Inst #2392 = TCRETURNri
+ { 2393, 2, 0, 0, "TCRETURNri64", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo56 }, // Inst #2393 = TCRETURNri64
+ { 2394, 1, 0, 0, "TEST16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(3<<13)|(169<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2394 = TEST16i16
+ { 2395, 6, 0, 0, "TEST16mi", 0|(1<<TID::MayLoad), 0|24|(1<<6)|(3<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2395 = TEST16mi
+ { 2396, 2, 0, 0, "TEST16ri", 0, 0|16|(1<<6)|(3<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo54 }, // Inst #2396 = TEST16ri
+ { 2397, 6, 0, 0, "TEST16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo46 }, // Inst #2397 = TEST16rm
+ { 2398, 2, 0, 0, "TEST16rr", 0|(1<<TID::Commutable), 0|3|(1<<6)|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo47 }, // Inst #2398 = TEST16rr
+ { 2399, 1, 0, 0, "TEST32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<13)|(169<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2399 = TEST32i32
+ { 2400, 6, 0, 0, "TEST32mi", 0|(1<<TID::MayLoad), 0|24|(4<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2400 = TEST32mi
+ { 2401, 2, 0, 0, "TEST32ri", 0, 0|16|(4<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo55 }, // Inst #2401 = TEST32ri
+ { 2402, 6, 0, 0, "TEST32rm", 0|(1<<TID::MayLoad), 0|6|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo48 }, // Inst #2402 = TEST32rm
+ { 2403, 2, 0, 0, "TEST32rr", 0|(1<<TID::Commutable), 0|3|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo49 }, // Inst #2403 = TEST32rr
+ { 2404, 1, 0, 0, "TEST64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(169<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2404 = TEST64i32
+ { 2405, 6, 0, 0, "TEST64mi32", 0|(1<<TID::MayLoad), 0|24|(1<<12)|(4<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2405 = TEST64mi32
+ { 2406, 2, 0, 0, "TEST64ri32", 0, 0|16|(1<<12)|(4<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo56 }, // Inst #2406 = TEST64ri32
+ { 2407, 6, 0, 0, "TEST64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo50 }, // Inst #2407 = TEST64rm
+ { 2408, 2, 0, 0, "TEST64rr", 0|(1<<TID::Commutable), 0|3|(1<<12)|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #2408 = TEST64rr
+ { 2409, 1, 0, 0, "TEST8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(168<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2409 = TEST8i8
+ { 2410, 6, 0, 0, "TEST8mi", 0|(1<<TID::MayLoad), 0|24|(1<<13)|(246<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2410 = TEST8mi
+ { 2411, 2, 0, 0, "TEST8ri", 0, 0|16|(1<<13)|(246<<24), NULL, ImplicitList1, Barriers1, OperandInfo68 }, // Inst #2411 = TEST8ri
+ { 2412, 6, 0, 0, "TEST8rm", 0|(1<<TID::MayLoad), 0|6|(132<<24), NULL, ImplicitList1, Barriers1, OperandInfo69 }, // Inst #2412 = TEST8rm
+ { 2413, 2, 0, 0, "TEST8rr", 0|(1<<TID::Commutable), 0|3|(132<<24), NULL, ImplicitList1, Barriers1, OperandInfo67 }, // Inst #2413 = TEST8rr
+ { 2414, 4, 0, 0, "TLS_addr32", 0, 0, ImplicitList2, ImplicitList9, Barriers3, OperandInfo201 }, // Inst #2414 = TLS_addr32
+ { 2415, 4, 0, 0, "TLS_addr64", 0, 0, ImplicitList4, ImplicitList10, Barriers4, OperandInfo202 }, // Inst #2415 = TLS_addr64
+ { 2416, 0, 0, 0, "TRAP", 0|(1<<TID::Barrier)|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(11<<24), NULL, NULL, NULL, 0 }, // Inst #2416 = TRAP
+ { 2417, 0, 0, 0, "TST_F", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(228<<24), NULL, NULL, NULL, 0 }, // Inst #2417 = TST_F
+ { 2418, 1, 0, 0, "TST_Fp32", 0, 0|(2<<16), NULL, NULL, NULL, OperandInfo100 }, // Inst #2418 = TST_Fp32
+ { 2419, 1, 0, 0, "TST_Fp64", 0, 0|(2<<16), NULL, NULL, NULL, OperandInfo101 }, // Inst #2419 = TST_Fp64
+ { 2420, 1, 0, 0, "TST_Fp80", 0, 0|(2<<16), NULL, NULL, NULL, OperandInfo102 }, // Inst #2420 = TST_Fp80
+ { 2421, 6, 0, 0, "UCOMISDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo82 }, // Inst #2421 = UCOMISDrm
+ { 2422, 2, 0, 0, "UCOMISDrr", 0, 0|5|(1<<6)|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo105 }, // Inst #2422 = UCOMISDrr
+ { 2423, 6, 0, 0, "UCOMISSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo80 }, // Inst #2423 = UCOMISSrm
+ { 2424, 2, 0, 0, "UCOMISSrr", 0, 0|5|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo106 }, // Inst #2424 = UCOMISSrr
+ { 2425, 1, 0, 0, "UCOM_FIPr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(10<<8)|(232<<24), ImplicitList24, ImplicitList1, Barriers1, OperandInfo31 }, // Inst #2425 = UCOM_FIPr
+ { 2426, 1, 0, 0, "UCOM_FIr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(6<<8)|(232<<24), ImplicitList24, ImplicitList1, Barriers1, OperandInfo31 }, // Inst #2426 = UCOM_FIr
+ { 2427, 0, 0, 0, "UCOM_FPPr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(5<<8)|(233<<24), ImplicitList24, ImplicitList1, Barriers1, 0 }, // Inst #2427 = UCOM_FPPr
+ { 2428, 1, 0, 0, "UCOM_FPr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(8<<8)|(232<<24), ImplicitList24, ImplicitList1, Barriers1, OperandInfo31 }, // Inst #2428 = UCOM_FPr
+ { 2429, 2, 0, 0, "UCOM_FpIr32", 0, 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #2429 = UCOM_FpIr32
+ { 2430, 2, 0, 0, "UCOM_FpIr64", 0, 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #2430 = UCOM_FpIr64
+ { 2431, 2, 0, 0, "UCOM_FpIr80", 0, 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #2431 = UCOM_FpIr80
+ { 2432, 2, 0, 0, "UCOM_Fpr32", 0|(1<<TID::UnmodeledSideEffects), 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #2432 = UCOM_Fpr32
+ { 2433, 2, 0, 0, "UCOM_Fpr64", 0|(1<<TID::UnmodeledSideEffects), 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #2433 = UCOM_Fpr64
+ { 2434, 2, 0, 0, "UCOM_Fpr80", 0|(1<<TID::UnmodeledSideEffects), 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #2434 = UCOM_Fpr80
+ { 2435, 1, 0, 0, "UCOM_Fr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(8<<8)|(224<<24), ImplicitList24, ImplicitList1, Barriers1, OperandInfo31 }, // Inst #2435 = UCOM_Fr
+ { 2436, 7, 1, 0, "UNPCKHPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(21<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2436 = UNPCKHPDrm
+ { 2437, 3, 1, 0, "UNPCKHPDrr", 0, 0|5|(1<<6)|(1<<8)|(21<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2437 = UNPCKHPDrr
+ { 2438, 7, 1, 0, "UNPCKHPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(21<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2438 = UNPCKHPSrm
+ { 2439, 3, 1, 0, "UNPCKHPSrr", 0, 0|5|(1<<8)|(21<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2439 = UNPCKHPSrr
+ { 2440, 7, 1, 0, "UNPCKLPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(20<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2440 = UNPCKLPDrm
+ { 2441, 3, 1, 0, "UNPCKLPDrr", 0, 0|5|(1<<6)|(1<<8)|(20<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2441 = UNPCKLPDrr
+ { 2442, 7, 1, 0, "UNPCKLPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(20<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2442 = UNPCKLPSrm
+ { 2443, 3, 1, 0, "UNPCKLPSrr", 0, 0|5|(1<<8)|(20<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2443 = UNPCKLPSrr
+ { 2444, 3, 0, 0, "VASTART_SAVE_XMM_REGS", 0|(1<<TID::UsesCustomInserter)|(1<<TID::Variadic), 0, NULL, NULL, NULL, OperandInfo203 }, // Inst #2444 = VASTART_SAVE_XMM_REGS
+ { 2445, 5, 0, 0, "VERRm", 0|(1<<TID::UnmodeledSideEffects), 0|28|(1<<8), NULL, NULL, NULL, OperandInfo30 }, // Inst #2445 = VERRm
+ { 2446, 1, 0, 0, "VERRr", 0|(1<<TID::UnmodeledSideEffects), 0|20|(1<<8), NULL, NULL, NULL, OperandInfo93 }, // Inst #2446 = VERRr
+ { 2447, 5, 0, 0, "VERWm", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<8), NULL, NULL, NULL, OperandInfo30 }, // Inst #2447 = VERWm
+ { 2448, 1, 0, 0, "VERWr", 0|(1<<TID::UnmodeledSideEffects), 0|21|(1<<8), NULL, NULL, NULL, OperandInfo93 }, // Inst #2448 = VERWr
+ { 2449, 0, 0, 0, "VMCALL", 0|(1<<TID::UnmodeledSideEffects), 0|33|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #2449 = VMCALL
+ { 2450, 5, 0, 0, "VMCLEARm", 0|(1<<TID::UnmodeledSideEffects), 0|30|(1<<6)|(1<<8)|(199<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2450 = VMCLEARm
+ { 2451, 0, 0, 0, "VMLAUNCH", 0|(1<<TID::UnmodeledSideEffects), 0|34|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #2451 = VMLAUNCH
+ { 2452, 5, 0, 0, "VMPTRLDm", 0|(1<<TID::UnmodeledSideEffects), 0|30|(1<<8)|(199<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2452 = VMPTRLDm
+ { 2453, 5, 1, 0, "VMPTRSTm", 0|(1<<TID::UnmodeledSideEffects), 0|31|(1<<8)|(199<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2453 = VMPTRSTm
+ { 2454, 6, 1, 0, "VMREAD32rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(120<<24), NULL, NULL, NULL, OperandInfo11 }, // Inst #2454 = VMREAD32rm
+ { 2455, 2, 1, 0, "VMREAD32rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(120<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #2455 = VMREAD32rr
+ { 2456, 6, 1, 0, "VMREAD64rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(120<<24), NULL, NULL, NULL, OperandInfo15 }, // Inst #2456 = VMREAD64rm
+ { 2457, 2, 1, 0, "VMREAD64rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(120<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #2457 = VMREAD64rr
+ { 2458, 0, 0, 0, "VMRESUME", 0|(1<<TID::UnmodeledSideEffects), 0|35|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #2458 = VMRESUME
+ { 2459, 6, 1, 0, "VMWRITE32rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(121<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #2459 = VMWRITE32rm
+ { 2460, 2, 1, 0, "VMWRITE32rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(121<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #2460 = VMWRITE32rr
+ { 2461, 6, 1, 0, "VMWRITE64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(121<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #2461 = VMWRITE64rm
+ { 2462, 2, 1, 0, "VMWRITE64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(121<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #2462 = VMWRITE64rr
+ { 2463, 0, 0, 0, "VMXOFF", 0|(1<<TID::UnmodeledSideEffects), 0|36|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #2463 = VMXOFF
+ { 2464, 5, 0, 0, "VMXON", 0|(1<<TID::UnmodeledSideEffects), 0|30|(11<<8)|(199<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2464 = VMXON
+ { 2465, 1, 1, 0, "V_SET0", 0|(1<<TID::FoldableAsLoad)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo204 }, // Inst #2465 = V_SET0
+ { 2466, 1, 1, 0, "V_SETALLONES", 0|(1<<TID::FoldableAsLoad)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(1<<6)|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo204 }, // Inst #2466 = V_SETALLONES
+ { 2467, 0, 0, 0, "WAIT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(155<<24), NULL, NULL, NULL, 0 }, // Inst #2467 = WAIT
+ { 2468, 0, 0, 0, "WBINVD", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(9<<24), NULL, NULL, NULL, 0 }, // Inst #2468 = WBINVD
+ { 2469, 5, 0, 0, "WINCALL64m", 0|(1<<TID::Call)|(1<<TID::MayLoad)|(1<<TID::Variadic), 0|26|(255<<24), ImplicitList4, ImplicitList57, Barriers8, OperandInfo30 }, // Inst #2469 = WINCALL64m
+ { 2470, 1, 0, 0, "WINCALL64pcrel32", 0|(1<<TID::Call)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|1|(232<<24), ImplicitList4, ImplicitList57, Barriers8, OperandInfo5 }, // Inst #2470 = WINCALL64pcrel32
+ { 2471, 1, 0, 0, "WINCALL64r", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|18|(255<<24), ImplicitList4, ImplicitList57, Barriers8, OperandInfo58 }, // Inst #2471 = WINCALL64r
+ { 2472, 0, 0, 0, "WRMSR", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(48<<24), NULL, NULL, NULL, 0 }, // Inst #2472 = WRMSR
+ { 2473, 6, 0, 0, "XADD16rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(193<<24), NULL, NULL, NULL, OperandInfo7 }, // Inst #2473 = XADD16rm
+ { 2474, 2, 1, 0, "XADD16rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<6)|(1<<8)|(193<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #2474 = XADD16rr
+ { 2475, 6, 0, 0, "XADD32rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(193<<24), NULL, NULL, NULL, OperandInfo11 }, // Inst #2475 = XADD32rm
+ { 2476, 2, 1, 0, "XADD32rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(193<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #2476 = XADD32rr
+ { 2477, 6, 0, 0, "XADD64rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(1<<12)|(193<<24), NULL, NULL, NULL, OperandInfo15 }, // Inst #2477 = XADD64rm
+ { 2478, 2, 1, 0, "XADD64rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(1<<12)|(193<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #2478 = XADD64rr
+ { 2479, 6, 0, 0, "XADD8rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(192<<24), NULL, NULL, NULL, OperandInfo20 }, // Inst #2479 = XADD8rm
+ { 2480, 2, 1, 0, "XADD8rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(192<<24), NULL, NULL, NULL, OperandInfo67 }, // Inst #2480 = XADD8rr
+ { 2481, 1, 0, 0, "XCHG16ar", 0|(1<<TID::UnmodeledSideEffects), 0|2|(1<<6)|(144<<24), NULL, NULL, NULL, OperandInfo93 }, // Inst #2481 = XCHG16ar
+ { 2482, 7, 1, 0, "XCHG16rm", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(1<<6)|(135<<24), NULL, NULL, NULL, OperandInfo9 }, // Inst #2482 = XCHG16rm
+ { 2483, 3, 1, 0, "XCHG16rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(135<<24), NULL, NULL, NULL, OperandInfo10 }, // Inst #2483 = XCHG16rr
+ { 2484, 1, 0, 0, "XCHG32ar", 0|(1<<TID::UnmodeledSideEffects), 0|2|(144<<24), NULL, NULL, NULL, OperandInfo57 }, // Inst #2484 = XCHG32ar
+ { 2485, 7, 1, 0, "XCHG32rm", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(135<<24), NULL, NULL, NULL, OperandInfo13 }, // Inst #2485 = XCHG32rm
+ { 2486, 3, 1, 0, "XCHG32rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(135<<24), NULL, NULL, NULL, OperandInfo14 }, // Inst #2486 = XCHG32rr
+ { 2487, 1, 0, 0, "XCHG64ar", 0|(1<<TID::UnmodeledSideEffects), 0|2|(1<<12)|(144<<24), NULL, NULL, NULL, OperandInfo58 }, // Inst #2487 = XCHG64ar
+ { 2488, 7, 1, 0, "XCHG64rm", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(1<<12)|(135<<24), NULL, NULL, NULL, OperandInfo17 }, // Inst #2488 = XCHG64rm
+ { 2489, 3, 1, 0, "XCHG64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(135<<24), NULL, NULL, NULL, OperandInfo18 }, // Inst #2489 = XCHG64rr
+ { 2490, 7, 1, 0, "XCHG8rm", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(134<<24), NULL, NULL, NULL, OperandInfo22 }, // Inst #2490 = XCHG8rm
+ { 2491, 3, 1, 0, "XCHG8rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(134<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #2491 = XCHG8rr
+ { 2492, 1, 0, 0, "XCH_F", 0|(1<<TID::UnmodeledSideEffects), 0|2|(4<<8)|(200<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2492 = XCH_F
+ { 2493, 0, 0, 0, "XLAT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(215<<24), NULL, NULL, NULL, 0 }, // Inst #2493 = XLAT
+ { 2494, 1, 0, 0, "XOR16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(3<<13)|(53<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2494 = XOR16i16
+ { 2495, 6, 0, 0, "XOR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<6)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2495 = XOR16mi
+ { 2496, 6, 0, 0, "XOR16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2496 = XOR16mi8
+ { 2497, 6, 0, 0, "XOR16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #2497 = XOR16mr
+ { 2498, 3, 1, 0, "XOR16ri", 0, 0|22|(1<<6)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2498 = XOR16ri
+ { 2499, 3, 1, 0, "XOR16ri8", 0, 0|22|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2499 = XOR16ri8
+ { 2500, 7, 1, 0, "XOR16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #2500 = XOR16rm
+ { 2501, 3, 1, 0, "XOR16rr", 0|(1<<TID::Commutable), 0|3|(1<<6)|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2501 = XOR16rr
+ { 2502, 3, 1, 0, "XOR16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2502 = XOR16rr_REV
+ { 2503, 1, 0, 0, "XOR32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<13)|(53<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2503 = XOR32i32
+ { 2504, 6, 0, 0, "XOR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2504 = XOR32mi
+ { 2505, 6, 0, 0, "XOR32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2505 = XOR32mi8
+ { 2506, 6, 0, 0, "XOR32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #2506 = XOR32mr
+ { 2507, 3, 1, 0, "XOR32ri", 0, 0|22|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2507 = XOR32ri
+ { 2508, 3, 1, 0, "XOR32ri8", 0, 0|22|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2508 = XOR32ri8
+ { 2509, 7, 1, 0, "XOR32rm", 0|(1<<TID::MayLoad), 0|6|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #2509 = XOR32rm
+ { 2510, 3, 1, 0, "XOR32rr", 0|(1<<TID::Commutable), 0|3|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2510 = XOR32rr
+ { 2511, 3, 1, 0, "XOR32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2511 = XOR32rr_REV
+ { 2512, 1, 0, 0, "XOR64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(4<<13)|(53<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2512 = XOR64i32
+ { 2513, 6, 0, 0, "XOR64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<12)|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2513 = XOR64mi32
+ { 2514, 6, 0, 0, "XOR64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2514 = XOR64mi8
+ { 2515, 6, 0, 0, "XOR64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #2515 = XOR64mr
+ { 2516, 3, 1, 0, "XOR64ri32", 0, 0|22|(1<<12)|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2516 = XOR64ri32
+ { 2517, 3, 1, 0, "XOR64ri8", 0, 0|22|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2517 = XOR64ri8
+ { 2518, 7, 1, 0, "XOR64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #2518 = XOR64rm
+ { 2519, 3, 1, 0, "XOR64rr", 0|(1<<TID::Commutable), 0|3|(1<<12)|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2519 = XOR64rr
+ { 2520, 3, 1, 0, "XOR64rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2520 = XOR64rr_REV
+ { 2521, 1, 0, 0, "XOR8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(52<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2521 = XOR8i8
+ { 2522, 6, 0, 0, "XOR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2522 = XOR8mi
+ { 2523, 6, 0, 0, "XOR8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(48<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #2523 = XOR8mr
+ { 2524, 3, 1, 0, "XOR8ri", 0, 0|22|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2524 = XOR8ri
+ { 2525, 7, 1, 0, "XOR8rm", 0|(1<<TID::MayLoad), 0|6|(50<<24), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #2525 = XOR8rm
+ { 2526, 3, 1, 0, "XOR8rr", 0|(1<<TID::Commutable), 0|3|(48<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #2526 = XOR8rr
+ { 2527, 3, 1, 0, "XOR8rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(50<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #2527 = XOR8rr_REV
+ { 2528, 7, 1, 0, "XORPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2528 = XORPDrm
+ { 2529, 3, 1, 0, "XORPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2529 = XORPDrr
+ { 2530, 7, 1, 0, "XORPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2530 = XORPSrm
+ { 2531, 3, 1, 0, "XORPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2531 = XORPSrr
};
} // End llvm namespace
diff --git a/libclamav/c++/X86GenInstrNames.inc b/libclamav/c++/X86GenInstrNames.inc
index 42f4ac9..96aee25 100644
--- a/libclamav/c++/X86GenInstrNames.inc
+++ b/libclamav/c++/X86GenInstrNames.inc
@@ -21,7 +21,7 @@ namespace X86 {
IMPLICIT_DEF = 8,
SUBREG_TO_REG = 9,
COPY_TO_REGCLASS = 10,
- DEBUG_VALUE = 11,
+ DBG_VALUE = 11,
ABS_F = 12,
ABS_Fp32 = 13,
ABS_Fp64 = 14,
@@ -514,2020 +514,2035 @@ namespace X86 {
CRC32r8 = 501,
CRC64m64 = 502,
CRC64r64 = 503,
- CVTDQ2PDrm = 504,
- CVTDQ2PDrr = 505,
- CVTDQ2PSrm = 506,
- CVTDQ2PSrr = 507,
- CVTPD2DQrm = 508,
- CVTPD2DQrr = 509,
- CVTPD2PSrm = 510,
- CVTPD2PSrr = 511,
- CVTPS2DQrm = 512,
- CVTPS2DQrr = 513,
- CVTPS2PDrm = 514,
- CVTPS2PDrr = 515,
- CVTSD2SI64rm = 516,
- CVTSD2SI64rr = 517,
- CVTSD2SSrm = 518,
- CVTSD2SSrr = 519,
- CVTSI2SD64rm = 520,
- CVTSI2SD64rr = 521,
- CVTSI2SDrm = 522,
- CVTSI2SDrr = 523,
- CVTSI2SS64rm = 524,
- CVTSI2SS64rr = 525,
- CVTSI2SSrm = 526,
- CVTSI2SSrr = 527,
- CVTSS2SDrm = 528,
- CVTSS2SDrr = 529,
- CVTSS2SI64rm = 530,
- CVTSS2SI64rr = 531,
- CVTSS2SIrm = 532,
- CVTSS2SIrr = 533,
- CVTTPS2DQrm = 534,
- CVTTPS2DQrr = 535,
- CVTTSD2SI64rm = 536,
- CVTTSD2SI64rr = 537,
- CVTTSD2SIrm = 538,
- CVTTSD2SIrr = 539,
- CVTTSS2SI64rm = 540,
- CVTTSS2SI64rr = 541,
- CVTTSS2SIrm = 542,
- CVTTSS2SIrr = 543,
- CWD = 544,
- CWDE = 545,
- DEC16m = 546,
- DEC16r = 547,
- DEC32m = 548,
- DEC32r = 549,
- DEC64_16m = 550,
- DEC64_16r = 551,
- DEC64_32m = 552,
- DEC64_32r = 553,
- DEC64m = 554,
- DEC64r = 555,
- DEC8m = 556,
- DEC8r = 557,
- DIV16m = 558,
- DIV16r = 559,
- DIV32m = 560,
- DIV32r = 561,
- DIV64m = 562,
- DIV64r = 563,
- DIV8m = 564,
- DIV8r = 565,
- DIVPDrm = 566,
- DIVPDrr = 567,
- DIVPSrm = 568,
- DIVPSrr = 569,
- DIVR_F32m = 570,
- DIVR_F64m = 571,
- DIVR_FI16m = 572,
- DIVR_FI32m = 573,
- DIVR_FPrST0 = 574,
- DIVR_FST0r = 575,
- DIVR_Fp32m = 576,
- DIVR_Fp64m = 577,
- DIVR_Fp64m32 = 578,
- DIVR_Fp80m32 = 579,
- DIVR_Fp80m64 = 580,
- DIVR_FpI16m32 = 581,
- DIVR_FpI16m64 = 582,
- DIVR_FpI16m80 = 583,
- DIVR_FpI32m32 = 584,
- DIVR_FpI32m64 = 585,
- DIVR_FpI32m80 = 586,
- DIVR_FrST0 = 587,
- DIVSDrm = 588,
- DIVSDrm_Int = 589,
- DIVSDrr = 590,
- DIVSDrr_Int = 591,
- DIVSSrm = 592,
- DIVSSrm_Int = 593,
- DIVSSrr = 594,
- DIVSSrr_Int = 595,
- DIV_F32m = 596,
- DIV_F64m = 597,
- DIV_FI16m = 598,
- DIV_FI32m = 599,
- DIV_FPrST0 = 600,
- DIV_FST0r = 601,
- DIV_Fp32 = 602,
- DIV_Fp32m = 603,
- DIV_Fp64 = 604,
- DIV_Fp64m = 605,
- DIV_Fp64m32 = 606,
- DIV_Fp80 = 607,
- DIV_Fp80m32 = 608,
- DIV_Fp80m64 = 609,
- DIV_FpI16m32 = 610,
- DIV_FpI16m64 = 611,
- DIV_FpI16m80 = 612,
- DIV_FpI32m32 = 613,
- DIV_FpI32m64 = 614,
- DIV_FpI32m80 = 615,
- DIV_FrST0 = 616,
- DPPDrmi = 617,
- DPPDrri = 618,
- DPPSrmi = 619,
- DPPSrri = 620,
- EH_RETURN = 621,
- EH_RETURN64 = 622,
- ENTER = 623,
- EXTRACTPSmr = 624,
- EXTRACTPSrr = 625,
- F2XM1 = 626,
- FARCALL16i = 627,
- FARCALL16m = 628,
- FARCALL32i = 629,
- FARCALL32m = 630,
- FARCALL64 = 631,
- FARJMP16i = 632,
- FARJMP16m = 633,
- FARJMP32i = 634,
- FARJMP32m = 635,
- FARJMP64 = 636,
- FBLDm = 637,
- FBSTPm = 638,
- FCOM32m = 639,
- FCOM64m = 640,
- FCOMP32m = 641,
- FCOMP64m = 642,
- FCOMPP = 643,
- FDECSTP = 644,
- FFREE = 645,
- FICOM16m = 646,
- FICOM32m = 647,
- FICOMP16m = 648,
- FICOMP32m = 649,
- FINCSTP = 650,
- FISTTP32m = 651,
- FLDCW16m = 652,
- FLDENVm = 653,
- FLDL2E = 654,
- FLDL2T = 655,
- FLDLG2 = 656,
- FLDLN2 = 657,
- FLDPI = 658,
- FNCLEX = 659,
- FNINIT = 660,
- FNOP = 661,
- FNSTCW16m = 662,
- FNSTSW8r = 663,
- FNSTSWm = 664,
- FP32_TO_INT16_IN_MEM = 665,
- FP32_TO_INT32_IN_MEM = 666,
- FP32_TO_INT64_IN_MEM = 667,
- FP64_TO_INT16_IN_MEM = 668,
- FP64_TO_INT32_IN_MEM = 669,
- FP64_TO_INT64_IN_MEM = 670,
- FP80_TO_INT16_IN_MEM = 671,
- FP80_TO_INT32_IN_MEM = 672,
- FP80_TO_INT64_IN_MEM = 673,
- FPATAN = 674,
- FPREM = 675,
- FPREM1 = 676,
- FPTAN = 677,
- FP_REG_KILL = 678,
- FRNDINT = 679,
- FRSTORm = 680,
- FSAVEm = 681,
- FSCALE = 682,
- FSINCOS = 683,
- FSTENVm = 684,
- FS_MOV32rm = 685,
- FXAM = 686,
- FXRSTOR = 687,
- FXSAVE = 688,
- FXTRACT = 689,
- FYL2X = 690,
- FYL2XP1 = 691,
- FpGET_ST0_32 = 692,
- FpGET_ST0_64 = 693,
- FpGET_ST0_80 = 694,
- FpGET_ST1_32 = 695,
- FpGET_ST1_64 = 696,
- FpGET_ST1_80 = 697,
- FpSET_ST0_32 = 698,
- FpSET_ST0_64 = 699,
- FpSET_ST0_80 = 700,
- FpSET_ST1_32 = 701,
- FpSET_ST1_64 = 702,
- FpSET_ST1_80 = 703,
- FsANDNPDrm = 704,
- FsANDNPDrr = 705,
- FsANDNPSrm = 706,
- FsANDNPSrr = 707,
- FsANDPDrm = 708,
- FsANDPDrr = 709,
- FsANDPSrm = 710,
- FsANDPSrr = 711,
- FsFLD0SD = 712,
- FsFLD0SS = 713,
- FsMOVAPDrm = 714,
- FsMOVAPDrr = 715,
- FsMOVAPSrm = 716,
- FsMOVAPSrr = 717,
- FsORPDrm = 718,
- FsORPDrr = 719,
- FsORPSrm = 720,
- FsORPSrr = 721,
- FsXORPDrm = 722,
- FsXORPDrr = 723,
- FsXORPSrm = 724,
- FsXORPSrr = 725,
- GS_MOV32rm = 726,
- HADDPDrm = 727,
- HADDPDrr = 728,
- HADDPSrm = 729,
- HADDPSrr = 730,
- HLT = 731,
- HSUBPDrm = 732,
- HSUBPDrr = 733,
- HSUBPSrm = 734,
- HSUBPSrr = 735,
- IDIV16m = 736,
- IDIV16r = 737,
- IDIV32m = 738,
- IDIV32r = 739,
- IDIV64m = 740,
- IDIV64r = 741,
- IDIV8m = 742,
- IDIV8r = 743,
- ILD_F16m = 744,
- ILD_F32m = 745,
- ILD_F64m = 746,
- ILD_Fp16m32 = 747,
- ILD_Fp16m64 = 748,
- ILD_Fp16m80 = 749,
- ILD_Fp32m32 = 750,
- ILD_Fp32m64 = 751,
- ILD_Fp32m80 = 752,
- ILD_Fp64m32 = 753,
- ILD_Fp64m64 = 754,
- ILD_Fp64m80 = 755,
- IMUL16m = 756,
- IMUL16r = 757,
- IMUL16rm = 758,
- IMUL16rmi = 759,
- IMUL16rmi8 = 760,
- IMUL16rr = 761,
- IMUL16rri = 762,
- IMUL16rri8 = 763,
- IMUL32m = 764,
- IMUL32r = 765,
- IMUL32rm = 766,
- IMUL32rmi = 767,
- IMUL32rmi8 = 768,
- IMUL32rr = 769,
- IMUL32rri = 770,
- IMUL32rri8 = 771,
- IMUL64m = 772,
- IMUL64r = 773,
- IMUL64rm = 774,
- IMUL64rmi32 = 775,
- IMUL64rmi8 = 776,
- IMUL64rr = 777,
- IMUL64rri32 = 778,
- IMUL64rri8 = 779,
- IMUL8m = 780,
- IMUL8r = 781,
- IN16 = 782,
- IN16ri = 783,
- IN16rr = 784,
- IN32 = 785,
- IN32ri = 786,
- IN32rr = 787,
- IN8 = 788,
- IN8ri = 789,
- IN8rr = 790,
- INC16m = 791,
- INC16r = 792,
- INC32m = 793,
- INC32r = 794,
- INC64_16m = 795,
- INC64_16r = 796,
- INC64_32m = 797,
- INC64_32r = 798,
- INC64m = 799,
- INC64r = 800,
- INC8m = 801,
- INC8r = 802,
- INSERTPSrm = 803,
- INSERTPSrr = 804,
- INT = 805,
- INT3 = 806,
- INVD = 807,
- INVEPT = 808,
- INVLPG = 809,
- INVVPID = 810,
- IRET16 = 811,
- IRET32 = 812,
- IRET64 = 813,
- ISTT_FP16m = 814,
- ISTT_FP32m = 815,
- ISTT_FP64m = 816,
- ISTT_Fp16m32 = 817,
- ISTT_Fp16m64 = 818,
- ISTT_Fp16m80 = 819,
- ISTT_Fp32m32 = 820,
- ISTT_Fp32m64 = 821,
- ISTT_Fp32m80 = 822,
- ISTT_Fp64m32 = 823,
- ISTT_Fp64m64 = 824,
- ISTT_Fp64m80 = 825,
- IST_F16m = 826,
- IST_F32m = 827,
- IST_FP16m = 828,
- IST_FP32m = 829,
- IST_FP64m = 830,
- IST_Fp16m32 = 831,
- IST_Fp16m64 = 832,
- IST_Fp16m80 = 833,
- IST_Fp32m32 = 834,
- IST_Fp32m64 = 835,
- IST_Fp32m80 = 836,
- IST_Fp64m32 = 837,
- IST_Fp64m64 = 838,
- IST_Fp64m80 = 839,
- Int_CMPSDrm = 840,
- Int_CMPSDrr = 841,
- Int_CMPSSrm = 842,
- Int_CMPSSrr = 843,
- Int_COMISDrm = 844,
- Int_COMISDrr = 845,
- Int_COMISSrm = 846,
- Int_COMISSrr = 847,
- Int_CVTDQ2PDrm = 848,
- Int_CVTDQ2PDrr = 849,
- Int_CVTDQ2PSrm = 850,
- Int_CVTDQ2PSrr = 851,
- Int_CVTPD2DQrm = 852,
- Int_CVTPD2DQrr = 853,
- Int_CVTPD2PIrm = 854,
- Int_CVTPD2PIrr = 855,
- Int_CVTPD2PSrm = 856,
- Int_CVTPD2PSrr = 857,
- Int_CVTPI2PDrm = 858,
- Int_CVTPI2PDrr = 859,
- Int_CVTPI2PSrm = 860,
- Int_CVTPI2PSrr = 861,
- Int_CVTPS2DQrm = 862,
- Int_CVTPS2DQrr = 863,
- Int_CVTPS2PDrm = 864,
- Int_CVTPS2PDrr = 865,
- Int_CVTPS2PIrm = 866,
- Int_CVTPS2PIrr = 867,
- Int_CVTSD2SI64rm = 868,
- Int_CVTSD2SI64rr = 869,
- Int_CVTSD2SIrm = 870,
- Int_CVTSD2SIrr = 871,
- Int_CVTSD2SSrm = 872,
- Int_CVTSD2SSrr = 873,
- Int_CVTSI2SD64rm = 874,
- Int_CVTSI2SD64rr = 875,
- Int_CVTSI2SDrm = 876,
- Int_CVTSI2SDrr = 877,
- Int_CVTSI2SS64rm = 878,
- Int_CVTSI2SS64rr = 879,
- Int_CVTSI2SSrm = 880,
- Int_CVTSI2SSrr = 881,
- Int_CVTSS2SDrm = 882,
- Int_CVTSS2SDrr = 883,
- Int_CVTSS2SI64rm = 884,
- Int_CVTSS2SI64rr = 885,
- Int_CVTSS2SIrm = 886,
- Int_CVTSS2SIrr = 887,
- Int_CVTTPD2DQrm = 888,
- Int_CVTTPD2DQrr = 889,
- Int_CVTTPD2PIrm = 890,
- Int_CVTTPD2PIrr = 891,
- Int_CVTTPS2DQrm = 892,
- Int_CVTTPS2DQrr = 893,
- Int_CVTTPS2PIrm = 894,
- Int_CVTTPS2PIrr = 895,
- Int_CVTTSD2SI64rm = 896,
- Int_CVTTSD2SI64rr = 897,
- Int_CVTTSD2SIrm = 898,
- Int_CVTTSD2SIrr = 899,
- Int_CVTTSS2SI64rm = 900,
- Int_CVTTSS2SI64rr = 901,
- Int_CVTTSS2SIrm = 902,
- Int_CVTTSS2SIrr = 903,
- Int_UCOMISDrm = 904,
- Int_UCOMISDrr = 905,
- Int_UCOMISSrm = 906,
- Int_UCOMISSrr = 907,
- JA = 908,
- JA8 = 909,
- JAE = 910,
- JAE8 = 911,
- JB = 912,
- JB8 = 913,
- JBE = 914,
- JBE8 = 915,
- JCXZ8 = 916,
- JE = 917,
- JE8 = 918,
- JG = 919,
- JG8 = 920,
- JGE = 921,
- JGE8 = 922,
- JL = 923,
- JL8 = 924,
- JLE = 925,
- JLE8 = 926,
- JMP = 927,
- JMP32m = 928,
- JMP32r = 929,
- JMP64m = 930,
- JMP64pcrel32 = 931,
- JMP64r = 932,
- JMP8 = 933,
- JNE = 934,
- JNE8 = 935,
- JNO = 936,
- JNO8 = 937,
- JNP = 938,
- JNP8 = 939,
- JNS = 940,
- JNS8 = 941,
- JO = 942,
- JO8 = 943,
- JP = 944,
- JP8 = 945,
- JS = 946,
- JS8 = 947,
- LAHF = 948,
- LAR16rm = 949,
- LAR16rr = 950,
- LAR32rm = 951,
- LAR32rr = 952,
- LAR64rm = 953,
- LAR64rr = 954,
- LCMPXCHG16 = 955,
- LCMPXCHG32 = 956,
- LCMPXCHG64 = 957,
- LCMPXCHG8 = 958,
- LCMPXCHG8B = 959,
- LDDQUrm = 960,
- LDMXCSR = 961,
- LDS16rm = 962,
- LDS32rm = 963,
- LD_F0 = 964,
- LD_F1 = 965,
- LD_F32m = 966,
- LD_F64m = 967,
- LD_F80m = 968,
- LD_Fp032 = 969,
- LD_Fp064 = 970,
- LD_Fp080 = 971,
- LD_Fp132 = 972,
- LD_Fp164 = 973,
- LD_Fp180 = 974,
- LD_Fp32m = 975,
- LD_Fp32m64 = 976,
- LD_Fp32m80 = 977,
- LD_Fp64m = 978,
- LD_Fp64m80 = 979,
- LD_Fp80m = 980,
- LD_Frr = 981,
- LEA16r = 982,
- LEA32r = 983,
- LEA64_32r = 984,
- LEA64r = 985,
- LEAVE = 986,
- LEAVE64 = 987,
- LES16rm = 988,
- LES32rm = 989,
- LFENCE = 990,
- LFS16rm = 991,
- LFS32rm = 992,
- LFS64rm = 993,
- LGDTm = 994,
- LGS16rm = 995,
- LGS32rm = 996,
- LGS64rm = 997,
- LIDTm = 998,
- LLDT16m = 999,
- LLDT16r = 1000,
- LMSW16m = 1001,
- LMSW16r = 1002,
- LOCK_ADD16mi = 1003,
- LOCK_ADD16mi8 = 1004,
- LOCK_ADD16mr = 1005,
- LOCK_ADD32mi = 1006,
- LOCK_ADD32mi8 = 1007,
- LOCK_ADD32mr = 1008,
- LOCK_ADD64mi32 = 1009,
- LOCK_ADD64mi8 = 1010,
- LOCK_ADD64mr = 1011,
- LOCK_ADD8mi = 1012,
- LOCK_ADD8mr = 1013,
- LOCK_DEC16m = 1014,
- LOCK_DEC32m = 1015,
- LOCK_DEC64m = 1016,
- LOCK_DEC8m = 1017,
- LOCK_INC16m = 1018,
- LOCK_INC32m = 1019,
- LOCK_INC64m = 1020,
- LOCK_INC8m = 1021,
- LOCK_SUB16mi = 1022,
- LOCK_SUB16mi8 = 1023,
- LOCK_SUB16mr = 1024,
- LOCK_SUB32mi = 1025,
- LOCK_SUB32mi8 = 1026,
- LOCK_SUB32mr = 1027,
- LOCK_SUB64mi32 = 1028,
- LOCK_SUB64mi8 = 1029,
- LOCK_SUB64mr = 1030,
- LOCK_SUB8mi = 1031,
- LOCK_SUB8mr = 1032,
- LODSB = 1033,
- LODSD = 1034,
- LODSQ = 1035,
- LODSW = 1036,
- LOOP = 1037,
- LOOPE = 1038,
- LOOPNE = 1039,
- LRET = 1040,
- LRETI = 1041,
- LSL16rm = 1042,
- LSL16rr = 1043,
- LSL32rm = 1044,
- LSL32rr = 1045,
- LSL64rm = 1046,
- LSL64rr = 1047,
- LSS16rm = 1048,
- LSS32rm = 1049,
- LSS64rm = 1050,
- LTRm = 1051,
- LTRr = 1052,
- LXADD16 = 1053,
- LXADD32 = 1054,
- LXADD64 = 1055,
- LXADD8 = 1056,
- MASKMOVDQU = 1057,
- MASKMOVDQU64 = 1058,
- MAXPDrm = 1059,
- MAXPDrm_Int = 1060,
- MAXPDrr = 1061,
- MAXPDrr_Int = 1062,
- MAXPSrm = 1063,
- MAXPSrm_Int = 1064,
- MAXPSrr = 1065,
- MAXPSrr_Int = 1066,
- MAXSDrm = 1067,
- MAXSDrm_Int = 1068,
- MAXSDrr = 1069,
- MAXSDrr_Int = 1070,
- MAXSSrm = 1071,
- MAXSSrm_Int = 1072,
- MAXSSrr = 1073,
- MAXSSrr_Int = 1074,
- MFENCE = 1075,
- MINPDrm = 1076,
- MINPDrm_Int = 1077,
- MINPDrr = 1078,
- MINPDrr_Int = 1079,
- MINPSrm = 1080,
- MINPSrm_Int = 1081,
- MINPSrr = 1082,
- MINPSrr_Int = 1083,
- MINSDrm = 1084,
- MINSDrm_Int = 1085,
- MINSDrr = 1086,
- MINSDrr_Int = 1087,
- MINSSrm = 1088,
- MINSSrm_Int = 1089,
- MINSSrr = 1090,
- MINSSrr_Int = 1091,
- MMX_CVTPD2PIrm = 1092,
- MMX_CVTPD2PIrr = 1093,
- MMX_CVTPI2PDrm = 1094,
- MMX_CVTPI2PDrr = 1095,
- MMX_CVTPI2PSrm = 1096,
- MMX_CVTPI2PSrr = 1097,
- MMX_CVTPS2PIrm = 1098,
- MMX_CVTPS2PIrr = 1099,
- MMX_CVTTPD2PIrm = 1100,
- MMX_CVTTPD2PIrr = 1101,
- MMX_CVTTPS2PIrm = 1102,
- MMX_CVTTPS2PIrr = 1103,
- MMX_EMMS = 1104,
- MMX_FEMMS = 1105,
- MMX_MASKMOVQ = 1106,
- MMX_MASKMOVQ64 = 1107,
- MMX_MOVD64from64rr = 1108,
- MMX_MOVD64grr = 1109,
- MMX_MOVD64mr = 1110,
- MMX_MOVD64rm = 1111,
- MMX_MOVD64rr = 1112,
- MMX_MOVD64rrv164 = 1113,
- MMX_MOVD64to64rr = 1114,
- MMX_MOVDQ2Qrr = 1115,
- MMX_MOVNTQmr = 1116,
- MMX_MOVQ2DQrr = 1117,
- MMX_MOVQ2FR64rr = 1118,
- MMX_MOVQ64gmr = 1119,
- MMX_MOVQ64mr = 1120,
- MMX_MOVQ64rm = 1121,
- MMX_MOVQ64rr = 1122,
- MMX_MOVZDI2PDIrm = 1123,
- MMX_MOVZDI2PDIrr = 1124,
- MMX_PACKSSDWrm = 1125,
- MMX_PACKSSDWrr = 1126,
- MMX_PACKSSWBrm = 1127,
- MMX_PACKSSWBrr = 1128,
- MMX_PACKUSWBrm = 1129,
- MMX_PACKUSWBrr = 1130,
- MMX_PADDBrm = 1131,
- MMX_PADDBrr = 1132,
- MMX_PADDDrm = 1133,
- MMX_PADDDrr = 1134,
- MMX_PADDQrm = 1135,
- MMX_PADDQrr = 1136,
- MMX_PADDSBrm = 1137,
- MMX_PADDSBrr = 1138,
- MMX_PADDSWrm = 1139,
- MMX_PADDSWrr = 1140,
- MMX_PADDUSBrm = 1141,
- MMX_PADDUSBrr = 1142,
- MMX_PADDUSWrm = 1143,
- MMX_PADDUSWrr = 1144,
- MMX_PADDWrm = 1145,
- MMX_PADDWrr = 1146,
- MMX_PANDNrm = 1147,
- MMX_PANDNrr = 1148,
- MMX_PANDrm = 1149,
- MMX_PANDrr = 1150,
- MMX_PAVGBrm = 1151,
- MMX_PAVGBrr = 1152,
- MMX_PAVGWrm = 1153,
- MMX_PAVGWrr = 1154,
- MMX_PCMPEQBrm = 1155,
- MMX_PCMPEQBrr = 1156,
- MMX_PCMPEQDrm = 1157,
- MMX_PCMPEQDrr = 1158,
- MMX_PCMPEQWrm = 1159,
- MMX_PCMPEQWrr = 1160,
- MMX_PCMPGTBrm = 1161,
- MMX_PCMPGTBrr = 1162,
- MMX_PCMPGTDrm = 1163,
- MMX_PCMPGTDrr = 1164,
- MMX_PCMPGTWrm = 1165,
- MMX_PCMPGTWrr = 1166,
- MMX_PEXTRWri = 1167,
- MMX_PINSRWrmi = 1168,
- MMX_PINSRWrri = 1169,
- MMX_PMADDWDrm = 1170,
- MMX_PMADDWDrr = 1171,
- MMX_PMAXSWrm = 1172,
- MMX_PMAXSWrr = 1173,
- MMX_PMAXUBrm = 1174,
- MMX_PMAXUBrr = 1175,
- MMX_PMINSWrm = 1176,
- MMX_PMINSWrr = 1177,
- MMX_PMINUBrm = 1178,
- MMX_PMINUBrr = 1179,
- MMX_PMOVMSKBrr = 1180,
- MMX_PMULHUWrm = 1181,
- MMX_PMULHUWrr = 1182,
- MMX_PMULHWrm = 1183,
- MMX_PMULHWrr = 1184,
- MMX_PMULLWrm = 1185,
- MMX_PMULLWrr = 1186,
- MMX_PMULUDQrm = 1187,
- MMX_PMULUDQrr = 1188,
- MMX_PORrm = 1189,
- MMX_PORrr = 1190,
- MMX_PSADBWrm = 1191,
- MMX_PSADBWrr = 1192,
- MMX_PSHUFWmi = 1193,
- MMX_PSHUFWri = 1194,
- MMX_PSLLDri = 1195,
- MMX_PSLLDrm = 1196,
- MMX_PSLLDrr = 1197,
- MMX_PSLLQri = 1198,
- MMX_PSLLQrm = 1199,
- MMX_PSLLQrr = 1200,
- MMX_PSLLWri = 1201,
- MMX_PSLLWrm = 1202,
- MMX_PSLLWrr = 1203,
- MMX_PSRADri = 1204,
- MMX_PSRADrm = 1205,
- MMX_PSRADrr = 1206,
- MMX_PSRAWri = 1207,
- MMX_PSRAWrm = 1208,
- MMX_PSRAWrr = 1209,
- MMX_PSRLDri = 1210,
- MMX_PSRLDrm = 1211,
- MMX_PSRLDrr = 1212,
- MMX_PSRLQri = 1213,
- MMX_PSRLQrm = 1214,
- MMX_PSRLQrr = 1215,
- MMX_PSRLWri = 1216,
- MMX_PSRLWrm = 1217,
- MMX_PSRLWrr = 1218,
- MMX_PSUBBrm = 1219,
- MMX_PSUBBrr = 1220,
- MMX_PSUBDrm = 1221,
- MMX_PSUBDrr = 1222,
- MMX_PSUBQrm = 1223,
- MMX_PSUBQrr = 1224,
- MMX_PSUBSBrm = 1225,
- MMX_PSUBSBrr = 1226,
- MMX_PSUBSWrm = 1227,
- MMX_PSUBSWrr = 1228,
- MMX_PSUBUSBrm = 1229,
- MMX_PSUBUSBrr = 1230,
- MMX_PSUBUSWrm = 1231,
- MMX_PSUBUSWrr = 1232,
- MMX_PSUBWrm = 1233,
- MMX_PSUBWrr = 1234,
- MMX_PUNPCKHBWrm = 1235,
- MMX_PUNPCKHBWrr = 1236,
- MMX_PUNPCKHDQrm = 1237,
- MMX_PUNPCKHDQrr = 1238,
- MMX_PUNPCKHWDrm = 1239,
- MMX_PUNPCKHWDrr = 1240,
- MMX_PUNPCKLBWrm = 1241,
- MMX_PUNPCKLBWrr = 1242,
- MMX_PUNPCKLDQrm = 1243,
- MMX_PUNPCKLDQrr = 1244,
- MMX_PUNPCKLWDrm = 1245,
- MMX_PUNPCKLWDrr = 1246,
- MMX_PXORrm = 1247,
- MMX_PXORrr = 1248,
- MMX_V_SET0 = 1249,
- MMX_V_SETALLONES = 1250,
- MONITOR = 1251,
- MOV16ao16 = 1252,
- MOV16mi = 1253,
- MOV16mr = 1254,
- MOV16ms = 1255,
- MOV16o16a = 1256,
- MOV16r0 = 1257,
- MOV16ri = 1258,
- MOV16rm = 1259,
- MOV16rr = 1260,
- MOV16rr_REV = 1261,
- MOV16rs = 1262,
- MOV16sm = 1263,
- MOV16sr = 1264,
- MOV32ao32 = 1265,
- MOV32cr = 1266,
- MOV32dr = 1267,
- MOV32mi = 1268,
- MOV32mr = 1269,
- MOV32o32a = 1270,
- MOV32r0 = 1271,
- MOV32rc = 1272,
- MOV32rd = 1273,
- MOV32ri = 1274,
- MOV32rm = 1275,
- MOV32rr = 1276,
- MOV32rr_REV = 1277,
- MOV64FSrm = 1278,
- MOV64GSrm = 1279,
- MOV64ao64 = 1280,
- MOV64ao8 = 1281,
- MOV64cr = 1282,
- MOV64dr = 1283,
- MOV64mi32 = 1284,
- MOV64mr = 1285,
- MOV64ms = 1286,
- MOV64o64a = 1287,
- MOV64o8a = 1288,
- MOV64r0 = 1289,
- MOV64rc = 1290,
- MOV64rd = 1291,
- MOV64ri = 1292,
- MOV64ri32 = 1293,
- MOV64ri64i32 = 1294,
- MOV64rm = 1295,
- MOV64rr = 1296,
- MOV64rr_REV = 1297,
- MOV64rs = 1298,
- MOV64sm = 1299,
- MOV64sr = 1300,
- MOV64toPQIrr = 1301,
- MOV64toSDrm = 1302,
- MOV64toSDrr = 1303,
- MOV8ao8 = 1304,
- MOV8mi = 1305,
- MOV8mr = 1306,
- MOV8mr_NOREX = 1307,
- MOV8o8a = 1308,
- MOV8r0 = 1309,
- MOV8ri = 1310,
- MOV8rm = 1311,
- MOV8rm_NOREX = 1312,
- MOV8rr = 1313,
- MOV8rr_NOREX = 1314,
- MOV8rr_REV = 1315,
- MOVAPDmr = 1316,
- MOVAPDrm = 1317,
- MOVAPDrr = 1318,
- MOVAPSmr = 1319,
- MOVAPSrm = 1320,
- MOVAPSrr = 1321,
- MOVDDUPrm = 1322,
- MOVDDUPrr = 1323,
- MOVDI2PDIrm = 1324,
- MOVDI2PDIrr = 1325,
- MOVDI2SSrm = 1326,
- MOVDI2SSrr = 1327,
- MOVDQAmr = 1328,
- MOVDQArm = 1329,
- MOVDQArr = 1330,
- MOVDQUmr = 1331,
- MOVDQUmr_Int = 1332,
- MOVDQUrm = 1333,
- MOVDQUrm_Int = 1334,
- MOVHLPSrr = 1335,
- MOVHPDmr = 1336,
- MOVHPDrm = 1337,
- MOVHPSmr = 1338,
- MOVHPSrm = 1339,
- MOVLHPSrr = 1340,
- MOVLPDmr = 1341,
- MOVLPDrm = 1342,
- MOVLPDrr = 1343,
- MOVLPSmr = 1344,
- MOVLPSrm = 1345,
- MOVLPSrr = 1346,
- MOVLQ128mr = 1347,
- MOVLSD2PDrr = 1348,
- MOVLSS2PSrr = 1349,
- MOVMSKPDrr = 1350,
- MOVMSKPSrr = 1351,
- MOVNTDQArm = 1352,
- MOVNTDQmr = 1353,
- MOVNTImr = 1354,
- MOVNTPDmr = 1355,
- MOVNTPSmr = 1356,
- MOVPC32r = 1357,
- MOVPD2SDmr = 1358,
- MOVPD2SDrr = 1359,
- MOVPDI2DImr = 1360,
- MOVPDI2DIrr = 1361,
- MOVPQI2QImr = 1362,
- MOVPQIto64rr = 1363,
- MOVPS2SSmr = 1364,
- MOVPS2SSrr = 1365,
- MOVQI2PQIrm = 1366,
- MOVQxrxr = 1367,
- MOVSD2PDrm = 1368,
- MOVSD2PDrr = 1369,
- MOVSDmr = 1370,
- MOVSDrm = 1371,
- MOVSDrr = 1372,
- MOVSDto64mr = 1373,
- MOVSDto64rr = 1374,
- MOVSHDUPrm = 1375,
- MOVSHDUPrr = 1376,
- MOVSLDUPrm = 1377,
- MOVSLDUPrr = 1378,
- MOVSS2DImr = 1379,
- MOVSS2DIrr = 1380,
- MOVSS2PSrm = 1381,
- MOVSS2PSrr = 1382,
- MOVSSmr = 1383,
- MOVSSrm = 1384,
- MOVSSrr = 1385,
- MOVSX16rm8 = 1386,
- MOVSX16rm8W = 1387,
- MOVSX16rr8 = 1388,
- MOVSX16rr8W = 1389,
- MOVSX32rm16 = 1390,
- MOVSX32rm8 = 1391,
- MOVSX32rr16 = 1392,
- MOVSX32rr8 = 1393,
- MOVSX64rm16 = 1394,
- MOVSX64rm32 = 1395,
- MOVSX64rm8 = 1396,
- MOVSX64rr16 = 1397,
- MOVSX64rr32 = 1398,
- MOVSX64rr8 = 1399,
- MOVUPDmr = 1400,
- MOVUPDmr_Int = 1401,
- MOVUPDrm = 1402,
- MOVUPDrm_Int = 1403,
- MOVUPDrr = 1404,
- MOVUPSmr = 1405,
- MOVUPSmr_Int = 1406,
- MOVUPSrm = 1407,
- MOVUPSrm_Int = 1408,
- MOVUPSrr = 1409,
- MOVZDI2PDIrm = 1410,
- MOVZDI2PDIrr = 1411,
- MOVZPQILo2PQIrm = 1412,
- MOVZPQILo2PQIrr = 1413,
- MOVZQI2PQIrm = 1414,
- MOVZQI2PQIrr = 1415,
- MOVZSD2PDrm = 1416,
- MOVZSS2PSrm = 1417,
- MOVZX16rm8 = 1418,
- MOVZX16rm8W = 1419,
- MOVZX16rr8 = 1420,
- MOVZX16rr8W = 1421,
- MOVZX32_NOREXrm8 = 1422,
- MOVZX32_NOREXrr8 = 1423,
- MOVZX32rm16 = 1424,
- MOVZX32rm8 = 1425,
- MOVZX32rr16 = 1426,
- MOVZX32rr8 = 1427,
- MOVZX64rm16 = 1428,
- MOVZX64rm16_Q = 1429,
- MOVZX64rm32 = 1430,
- MOVZX64rm8 = 1431,
- MOVZX64rm8_Q = 1432,
- MOVZX64rr16 = 1433,
- MOVZX64rr16_Q = 1434,
- MOVZX64rr32 = 1435,
- MOVZX64rr8 = 1436,
- MOVZX64rr8_Q = 1437,
- MOV_Fp3232 = 1438,
- MOV_Fp3264 = 1439,
- MOV_Fp3280 = 1440,
- MOV_Fp6432 = 1441,
- MOV_Fp6464 = 1442,
- MOV_Fp6480 = 1443,
- MOV_Fp8032 = 1444,
- MOV_Fp8064 = 1445,
- MOV_Fp8080 = 1446,
- MPSADBWrmi = 1447,
- MPSADBWrri = 1448,
- MUL16m = 1449,
- MUL16r = 1450,
- MUL32m = 1451,
- MUL32r = 1452,
- MUL64m = 1453,
- MUL64r = 1454,
- MUL8m = 1455,
- MUL8r = 1456,
- MULPDrm = 1457,
- MULPDrr = 1458,
- MULPSrm = 1459,
- MULPSrr = 1460,
- MULSDrm = 1461,
- MULSDrm_Int = 1462,
- MULSDrr = 1463,
- MULSDrr_Int = 1464,
- MULSSrm = 1465,
- MULSSrm_Int = 1466,
- MULSSrr = 1467,
- MULSSrr_Int = 1468,
- MUL_F32m = 1469,
- MUL_F64m = 1470,
- MUL_FI16m = 1471,
- MUL_FI32m = 1472,
- MUL_FPrST0 = 1473,
- MUL_FST0r = 1474,
- MUL_Fp32 = 1475,
- MUL_Fp32m = 1476,
- MUL_Fp64 = 1477,
- MUL_Fp64m = 1478,
- MUL_Fp64m32 = 1479,
- MUL_Fp80 = 1480,
- MUL_Fp80m32 = 1481,
- MUL_Fp80m64 = 1482,
- MUL_FpI16m32 = 1483,
- MUL_FpI16m64 = 1484,
- MUL_FpI16m80 = 1485,
- MUL_FpI32m32 = 1486,
- MUL_FpI32m64 = 1487,
- MUL_FpI32m80 = 1488,
- MUL_FrST0 = 1489,
- MWAIT = 1490,
- NEG16m = 1491,
- NEG16r = 1492,
- NEG32m = 1493,
- NEG32r = 1494,
- NEG64m = 1495,
- NEG64r = 1496,
- NEG8m = 1497,
- NEG8r = 1498,
- NOOP = 1499,
- NOOPL = 1500,
- NOOPW = 1501,
- NOT16m = 1502,
- NOT16r = 1503,
- NOT32m = 1504,
- NOT32r = 1505,
- NOT64m = 1506,
- NOT64r = 1507,
- NOT8m = 1508,
- NOT8r = 1509,
- OR16i16 = 1510,
- OR16mi = 1511,
- OR16mi8 = 1512,
- OR16mr = 1513,
- OR16ri = 1514,
- OR16ri8 = 1515,
- OR16rm = 1516,
- OR16rr = 1517,
- OR16rr_REV = 1518,
- OR32i32 = 1519,
- OR32mi = 1520,
- OR32mi8 = 1521,
- OR32mr = 1522,
- OR32ri = 1523,
- OR32ri8 = 1524,
- OR32rm = 1525,
- OR32rr = 1526,
- OR32rr_REV = 1527,
- OR64i32 = 1528,
- OR64mi32 = 1529,
- OR64mi8 = 1530,
- OR64mr = 1531,
- OR64ri32 = 1532,
- OR64ri8 = 1533,
- OR64rm = 1534,
- OR64rr = 1535,
- OR64rr_REV = 1536,
- OR8i8 = 1537,
- OR8mi = 1538,
- OR8mr = 1539,
- OR8ri = 1540,
- OR8rm = 1541,
- OR8rr = 1542,
- OR8rr_REV = 1543,
- ORPDrm = 1544,
- ORPDrr = 1545,
- ORPSrm = 1546,
- ORPSrr = 1547,
- OUT16ir = 1548,
- OUT16rr = 1549,
- OUT32ir = 1550,
- OUT32rr = 1551,
- OUT8ir = 1552,
- OUT8rr = 1553,
- OUTSB = 1554,
- OUTSD = 1555,
- OUTSW = 1556,
- PABSBrm128 = 1557,
- PABSBrm64 = 1558,
- PABSBrr128 = 1559,
- PABSBrr64 = 1560,
- PABSDrm128 = 1561,
- PABSDrm64 = 1562,
- PABSDrr128 = 1563,
- PABSDrr64 = 1564,
- PABSWrm128 = 1565,
- PABSWrm64 = 1566,
- PABSWrr128 = 1567,
- PABSWrr64 = 1568,
- PACKSSDWrm = 1569,
- PACKSSDWrr = 1570,
- PACKSSWBrm = 1571,
- PACKSSWBrr = 1572,
- PACKUSDWrm = 1573,
- PACKUSDWrr = 1574,
- PACKUSWBrm = 1575,
- PACKUSWBrr = 1576,
- PADDBrm = 1577,
- PADDBrr = 1578,
- PADDDrm = 1579,
- PADDDrr = 1580,
- PADDQrm = 1581,
- PADDQrr = 1582,
- PADDSBrm = 1583,
- PADDSBrr = 1584,
- PADDSWrm = 1585,
- PADDSWrr = 1586,
- PADDUSBrm = 1587,
- PADDUSBrr = 1588,
- PADDUSWrm = 1589,
- PADDUSWrr = 1590,
- PADDWrm = 1591,
- PADDWrr = 1592,
- PALIGNR128rm = 1593,
- PALIGNR128rr = 1594,
- PALIGNR64rm = 1595,
- PALIGNR64rr = 1596,
- PANDNrm = 1597,
- PANDNrr = 1598,
- PANDrm = 1599,
- PANDrr = 1600,
- PAVGBrm = 1601,
- PAVGBrr = 1602,
- PAVGWrm = 1603,
- PAVGWrr = 1604,
- PBLENDVBrm0 = 1605,
- PBLENDVBrr0 = 1606,
- PBLENDWrmi = 1607,
- PBLENDWrri = 1608,
- PCMPEQBrm = 1609,
- PCMPEQBrr = 1610,
- PCMPEQDrm = 1611,
- PCMPEQDrr = 1612,
- PCMPEQQrm = 1613,
- PCMPEQQrr = 1614,
- PCMPEQWrm = 1615,
- PCMPEQWrr = 1616,
- PCMPESTRIArm = 1617,
- PCMPESTRIArr = 1618,
- PCMPESTRICrm = 1619,
- PCMPESTRICrr = 1620,
- PCMPESTRIOrm = 1621,
- PCMPESTRIOrr = 1622,
- PCMPESTRISrm = 1623,
- PCMPESTRISrr = 1624,
- PCMPESTRIZrm = 1625,
- PCMPESTRIZrr = 1626,
- PCMPESTRIrm = 1627,
- PCMPESTRIrr = 1628,
- PCMPESTRM128MEM = 1629,
- PCMPESTRM128REG = 1630,
- PCMPESTRM128rm = 1631,
- PCMPESTRM128rr = 1632,
- PCMPGTBrm = 1633,
- PCMPGTBrr = 1634,
- PCMPGTDrm = 1635,
- PCMPGTDrr = 1636,
- PCMPGTQrm = 1637,
- PCMPGTQrr = 1638,
- PCMPGTWrm = 1639,
- PCMPGTWrr = 1640,
- PCMPISTRIArm = 1641,
- PCMPISTRIArr = 1642,
- PCMPISTRICrm = 1643,
- PCMPISTRICrr = 1644,
- PCMPISTRIOrm = 1645,
- PCMPISTRIOrr = 1646,
- PCMPISTRISrm = 1647,
- PCMPISTRISrr = 1648,
- PCMPISTRIZrm = 1649,
- PCMPISTRIZrr = 1650,
- PCMPISTRIrm = 1651,
- PCMPISTRIrr = 1652,
- PCMPISTRM128MEM = 1653,
- PCMPISTRM128REG = 1654,
- PCMPISTRM128rm = 1655,
- PCMPISTRM128rr = 1656,
- PEXTRBmr = 1657,
- PEXTRBrr = 1658,
- PEXTRDmr = 1659,
- PEXTRDrr = 1660,
- PEXTRQmr = 1661,
- PEXTRQrr = 1662,
- PEXTRWmr = 1663,
- PEXTRWri = 1664,
- PHADDDrm128 = 1665,
- PHADDDrm64 = 1666,
- PHADDDrr128 = 1667,
- PHADDDrr64 = 1668,
- PHADDSWrm128 = 1669,
- PHADDSWrm64 = 1670,
- PHADDSWrr128 = 1671,
- PHADDSWrr64 = 1672,
- PHADDWrm128 = 1673,
- PHADDWrm64 = 1674,
- PHADDWrr128 = 1675,
- PHADDWrr64 = 1676,
- PHMINPOSUWrm128 = 1677,
- PHMINPOSUWrr128 = 1678,
- PHSUBDrm128 = 1679,
- PHSUBDrm64 = 1680,
- PHSUBDrr128 = 1681,
- PHSUBDrr64 = 1682,
- PHSUBSWrm128 = 1683,
- PHSUBSWrm64 = 1684,
- PHSUBSWrr128 = 1685,
- PHSUBSWrr64 = 1686,
- PHSUBWrm128 = 1687,
- PHSUBWrm64 = 1688,
- PHSUBWrr128 = 1689,
- PHSUBWrr64 = 1690,
- PINSRBrm = 1691,
- PINSRBrr = 1692,
- PINSRDrm = 1693,
- PINSRDrr = 1694,
- PINSRQrm = 1695,
- PINSRQrr = 1696,
- PINSRWrmi = 1697,
- PINSRWrri = 1698,
- PMADDUBSWrm128 = 1699,
- PMADDUBSWrm64 = 1700,
- PMADDUBSWrr128 = 1701,
- PMADDUBSWrr64 = 1702,
- PMADDWDrm = 1703,
- PMADDWDrr = 1704,
- PMAXSBrm = 1705,
- PMAXSBrr = 1706,
- PMAXSDrm = 1707,
- PMAXSDrr = 1708,
- PMAXSWrm = 1709,
- PMAXSWrr = 1710,
- PMAXUBrm = 1711,
- PMAXUBrr = 1712,
- PMAXUDrm = 1713,
- PMAXUDrr = 1714,
- PMAXUWrm = 1715,
- PMAXUWrr = 1716,
- PMINSBrm = 1717,
- PMINSBrr = 1718,
- PMINSDrm = 1719,
- PMINSDrr = 1720,
- PMINSWrm = 1721,
- PMINSWrr = 1722,
- PMINUBrm = 1723,
- PMINUBrr = 1724,
- PMINUDrm = 1725,
- PMINUDrr = 1726,
- PMINUWrm = 1727,
- PMINUWrr = 1728,
- PMOVMSKBrr = 1729,
- PMOVSXBDrm = 1730,
- PMOVSXBDrr = 1731,
- PMOVSXBQrm = 1732,
- PMOVSXBQrr = 1733,
- PMOVSXBWrm = 1734,
- PMOVSXBWrr = 1735,
- PMOVSXDQrm = 1736,
- PMOVSXDQrr = 1737,
- PMOVSXWDrm = 1738,
- PMOVSXWDrr = 1739,
- PMOVSXWQrm = 1740,
- PMOVSXWQrr = 1741,
- PMOVZXBDrm = 1742,
- PMOVZXBDrr = 1743,
- PMOVZXBQrm = 1744,
- PMOVZXBQrr = 1745,
- PMOVZXBWrm = 1746,
- PMOVZXBWrr = 1747,
- PMOVZXDQrm = 1748,
- PMOVZXDQrr = 1749,
- PMOVZXWDrm = 1750,
- PMOVZXWDrr = 1751,
- PMOVZXWQrm = 1752,
- PMOVZXWQrr = 1753,
- PMULDQrm = 1754,
- PMULDQrr = 1755,
- PMULHRSWrm128 = 1756,
- PMULHRSWrm64 = 1757,
- PMULHRSWrr128 = 1758,
- PMULHRSWrr64 = 1759,
- PMULHUWrm = 1760,
- PMULHUWrr = 1761,
- PMULHWrm = 1762,
- PMULHWrr = 1763,
- PMULLDrm = 1764,
- PMULLDrm_int = 1765,
- PMULLDrr = 1766,
- PMULLDrr_int = 1767,
- PMULLWrm = 1768,
- PMULLWrr = 1769,
- PMULUDQrm = 1770,
- PMULUDQrr = 1771,
- POP16r = 1772,
- POP16rmm = 1773,
- POP16rmr = 1774,
- POP32r = 1775,
- POP32rmm = 1776,
- POP32rmr = 1777,
- POP64r = 1778,
- POP64rmm = 1779,
- POP64rmr = 1780,
- POPCNT16rm = 1781,
- POPCNT16rr = 1782,
- POPCNT32rm = 1783,
- POPCNT32rr = 1784,
- POPCNT64rm = 1785,
- POPCNT64rr = 1786,
- POPF = 1787,
- POPFD = 1788,
- POPFQ = 1789,
- POPFS16 = 1790,
- POPFS32 = 1791,
- POPFS64 = 1792,
- POPGS16 = 1793,
- POPGS32 = 1794,
- POPGS64 = 1795,
- PORrm = 1796,
- PORrr = 1797,
- PREFETCHNTA = 1798,
- PREFETCHT0 = 1799,
- PREFETCHT1 = 1800,
- PREFETCHT2 = 1801,
- PSADBWrm = 1802,
- PSADBWrr = 1803,
- PSHUFBrm128 = 1804,
- PSHUFBrm64 = 1805,
- PSHUFBrr128 = 1806,
- PSHUFBrr64 = 1807,
- PSHUFDmi = 1808,
- PSHUFDri = 1809,
- PSHUFHWmi = 1810,
- PSHUFHWri = 1811,
- PSHUFLWmi = 1812,
- PSHUFLWri = 1813,
- PSIGNBrm128 = 1814,
- PSIGNBrm64 = 1815,
- PSIGNBrr128 = 1816,
- PSIGNBrr64 = 1817,
- PSIGNDrm128 = 1818,
- PSIGNDrm64 = 1819,
- PSIGNDrr128 = 1820,
- PSIGNDrr64 = 1821,
- PSIGNWrm128 = 1822,
- PSIGNWrm64 = 1823,
- PSIGNWrr128 = 1824,
- PSIGNWrr64 = 1825,
- PSLLDQri = 1826,
- PSLLDri = 1827,
- PSLLDrm = 1828,
- PSLLDrr = 1829,
- PSLLQri = 1830,
- PSLLQrm = 1831,
- PSLLQrr = 1832,
- PSLLWri = 1833,
- PSLLWrm = 1834,
- PSLLWrr = 1835,
- PSRADri = 1836,
- PSRADrm = 1837,
- PSRADrr = 1838,
- PSRAWri = 1839,
- PSRAWrm = 1840,
- PSRAWrr = 1841,
- PSRLDQri = 1842,
- PSRLDri = 1843,
- PSRLDrm = 1844,
- PSRLDrr = 1845,
- PSRLQri = 1846,
- PSRLQrm = 1847,
- PSRLQrr = 1848,
- PSRLWri = 1849,
- PSRLWrm = 1850,
- PSRLWrr = 1851,
- PSUBBrm = 1852,
- PSUBBrr = 1853,
- PSUBDrm = 1854,
- PSUBDrr = 1855,
- PSUBQrm = 1856,
- PSUBQrr = 1857,
- PSUBSBrm = 1858,
- PSUBSBrr = 1859,
- PSUBSWrm = 1860,
- PSUBSWrr = 1861,
- PSUBUSBrm = 1862,
- PSUBUSBrr = 1863,
- PSUBUSWrm = 1864,
- PSUBUSWrr = 1865,
- PSUBWrm = 1866,
- PSUBWrr = 1867,
- PTESTrm = 1868,
- PTESTrr = 1869,
- PUNPCKHBWrm = 1870,
- PUNPCKHBWrr = 1871,
- PUNPCKHDQrm = 1872,
- PUNPCKHDQrr = 1873,
- PUNPCKHQDQrm = 1874,
- PUNPCKHQDQrr = 1875,
- PUNPCKHWDrm = 1876,
- PUNPCKHWDrr = 1877,
- PUNPCKLBWrm = 1878,
- PUNPCKLBWrr = 1879,
- PUNPCKLDQrm = 1880,
- PUNPCKLDQrr = 1881,
- PUNPCKLQDQrm = 1882,
- PUNPCKLQDQrr = 1883,
- PUNPCKLWDrm = 1884,
- PUNPCKLWDrr = 1885,
- PUSH16r = 1886,
- PUSH16rmm = 1887,
- PUSH16rmr = 1888,
- PUSH32i16 = 1889,
- PUSH32i32 = 1890,
- PUSH32i8 = 1891,
- PUSH32r = 1892,
- PUSH32rmm = 1893,
- PUSH32rmr = 1894,
- PUSH64i16 = 1895,
- PUSH64i32 = 1896,
- PUSH64i8 = 1897,
- PUSH64r = 1898,
- PUSH64rmm = 1899,
- PUSH64rmr = 1900,
- PUSHF = 1901,
- PUSHFD = 1902,
- PUSHFQ64 = 1903,
- PUSHFS16 = 1904,
- PUSHFS32 = 1905,
- PUSHFS64 = 1906,
- PUSHGS16 = 1907,
- PUSHGS32 = 1908,
- PUSHGS64 = 1909,
- PXORrm = 1910,
- PXORrr = 1911,
- RCL16m1 = 1912,
- RCL16mCL = 1913,
- RCL16mi = 1914,
- RCL16r1 = 1915,
- RCL16rCL = 1916,
- RCL16ri = 1917,
- RCL32m1 = 1918,
- RCL32mCL = 1919,
- RCL32mi = 1920,
- RCL32r1 = 1921,
- RCL32rCL = 1922,
- RCL32ri = 1923,
- RCL64m1 = 1924,
- RCL64mCL = 1925,
- RCL64mi = 1926,
- RCL64r1 = 1927,
- RCL64rCL = 1928,
- RCL64ri = 1929,
- RCL8m1 = 1930,
- RCL8mCL = 1931,
- RCL8mi = 1932,
- RCL8r1 = 1933,
- RCL8rCL = 1934,
- RCL8ri = 1935,
- RCPPSm = 1936,
- RCPPSm_Int = 1937,
- RCPPSr = 1938,
- RCPPSr_Int = 1939,
- RCPSSm = 1940,
- RCPSSm_Int = 1941,
- RCPSSr = 1942,
- RCPSSr_Int = 1943,
- RCR16m1 = 1944,
- RCR16mCL = 1945,
- RCR16mi = 1946,
- RCR16r1 = 1947,
- RCR16rCL = 1948,
- RCR16ri = 1949,
- RCR32m1 = 1950,
- RCR32mCL = 1951,
- RCR32mi = 1952,
- RCR32r1 = 1953,
- RCR32rCL = 1954,
- RCR32ri = 1955,
- RCR64m1 = 1956,
- RCR64mCL = 1957,
- RCR64mi = 1958,
- RCR64r1 = 1959,
- RCR64rCL = 1960,
- RCR64ri = 1961,
- RCR8m1 = 1962,
- RCR8mCL = 1963,
- RCR8mi = 1964,
- RCR8r1 = 1965,
- RCR8rCL = 1966,
- RCR8ri = 1967,
- RDMSR = 1968,
- RDPMC = 1969,
- RDTSC = 1970,
- REP_MOVSB = 1971,
- REP_MOVSD = 1972,
- REP_MOVSQ = 1973,
- REP_MOVSW = 1974,
- REP_STOSB = 1975,
- REP_STOSD = 1976,
- REP_STOSQ = 1977,
- REP_STOSW = 1978,
- RET = 1979,
- RETI = 1980,
- ROL16m1 = 1981,
- ROL16mCL = 1982,
- ROL16mi = 1983,
- ROL16r1 = 1984,
- ROL16rCL = 1985,
- ROL16ri = 1986,
- ROL32m1 = 1987,
- ROL32mCL = 1988,
- ROL32mi = 1989,
- ROL32r1 = 1990,
- ROL32rCL = 1991,
- ROL32ri = 1992,
- ROL64m1 = 1993,
- ROL64mCL = 1994,
- ROL64mi = 1995,
- ROL64r1 = 1996,
- ROL64rCL = 1997,
- ROL64ri = 1998,
- ROL8m1 = 1999,
- ROL8mCL = 2000,
- ROL8mi = 2001,
- ROL8r1 = 2002,
- ROL8rCL = 2003,
- ROL8ri = 2004,
- ROR16m1 = 2005,
- ROR16mCL = 2006,
- ROR16mi = 2007,
- ROR16r1 = 2008,
- ROR16rCL = 2009,
- ROR16ri = 2010,
- ROR32m1 = 2011,
- ROR32mCL = 2012,
- ROR32mi = 2013,
- ROR32r1 = 2014,
- ROR32rCL = 2015,
- ROR32ri = 2016,
- ROR64m1 = 2017,
- ROR64mCL = 2018,
- ROR64mi = 2019,
- ROR64r1 = 2020,
- ROR64rCL = 2021,
- ROR64ri = 2022,
- ROR8m1 = 2023,
- ROR8mCL = 2024,
- ROR8mi = 2025,
- ROR8r1 = 2026,
- ROR8rCL = 2027,
- ROR8ri = 2028,
- ROUNDPDm_Int = 2029,
- ROUNDPDr_Int = 2030,
- ROUNDPSm_Int = 2031,
- ROUNDPSr_Int = 2032,
- ROUNDSDm_Int = 2033,
- ROUNDSDr_Int = 2034,
- ROUNDSSm_Int = 2035,
- ROUNDSSr_Int = 2036,
- RSM = 2037,
- RSQRTPSm = 2038,
- RSQRTPSm_Int = 2039,
- RSQRTPSr = 2040,
- RSQRTPSr_Int = 2041,
- RSQRTSSm = 2042,
- RSQRTSSm_Int = 2043,
- RSQRTSSr = 2044,
- RSQRTSSr_Int = 2045,
- SAHF = 2046,
- SAR16m1 = 2047,
- SAR16mCL = 2048,
- SAR16mi = 2049,
- SAR16r1 = 2050,
- SAR16rCL = 2051,
- SAR16ri = 2052,
- SAR32m1 = 2053,
- SAR32mCL = 2054,
- SAR32mi = 2055,
- SAR32r1 = 2056,
- SAR32rCL = 2057,
- SAR32ri = 2058,
- SAR64m1 = 2059,
- SAR64mCL = 2060,
- SAR64mi = 2061,
- SAR64r1 = 2062,
- SAR64rCL = 2063,
- SAR64ri = 2064,
- SAR8m1 = 2065,
- SAR8mCL = 2066,
- SAR8mi = 2067,
- SAR8r1 = 2068,
- SAR8rCL = 2069,
- SAR8ri = 2070,
- SBB16i16 = 2071,
- SBB16mi = 2072,
- SBB16mi8 = 2073,
- SBB16mr = 2074,
- SBB16ri = 2075,
- SBB16ri8 = 2076,
- SBB16rm = 2077,
- SBB16rr = 2078,
- SBB16rr_REV = 2079,
- SBB32i32 = 2080,
- SBB32mi = 2081,
- SBB32mi8 = 2082,
- SBB32mr = 2083,
- SBB32ri = 2084,
- SBB32ri8 = 2085,
- SBB32rm = 2086,
- SBB32rr = 2087,
- SBB32rr_REV = 2088,
- SBB64i32 = 2089,
- SBB64mi32 = 2090,
- SBB64mi8 = 2091,
- SBB64mr = 2092,
- SBB64ri32 = 2093,
- SBB64ri8 = 2094,
- SBB64rm = 2095,
- SBB64rr = 2096,
- SBB64rr_REV = 2097,
- SBB8i8 = 2098,
- SBB8mi = 2099,
- SBB8mr = 2100,
- SBB8ri = 2101,
- SBB8rm = 2102,
- SBB8rr = 2103,
- SBB8rr_REV = 2104,
- SCAS16 = 2105,
- SCAS32 = 2106,
- SCAS64 = 2107,
- SCAS8 = 2108,
- SETAEm = 2109,
- SETAEr = 2110,
- SETAm = 2111,
- SETAr = 2112,
- SETBEm = 2113,
- SETBEr = 2114,
- SETB_C16r = 2115,
- SETB_C32r = 2116,
- SETB_C64r = 2117,
- SETB_C8r = 2118,
- SETBm = 2119,
- SETBr = 2120,
- SETEm = 2121,
- SETEr = 2122,
- SETGEm = 2123,
- SETGEr = 2124,
- SETGm = 2125,
- SETGr = 2126,
- SETLEm = 2127,
- SETLEr = 2128,
- SETLm = 2129,
- SETLr = 2130,
- SETNEm = 2131,
- SETNEr = 2132,
- SETNOm = 2133,
- SETNOr = 2134,
- SETNPm = 2135,
- SETNPr = 2136,
- SETNSm = 2137,
- SETNSr = 2138,
- SETOm = 2139,
- SETOr = 2140,
- SETPm = 2141,
- SETPr = 2142,
- SETSm = 2143,
- SETSr = 2144,
- SFENCE = 2145,
- SGDTm = 2146,
- SHL16m1 = 2147,
- SHL16mCL = 2148,
- SHL16mi = 2149,
- SHL16r1 = 2150,
- SHL16rCL = 2151,
- SHL16ri = 2152,
- SHL32m1 = 2153,
- SHL32mCL = 2154,
- SHL32mi = 2155,
- SHL32r1 = 2156,
- SHL32rCL = 2157,
- SHL32ri = 2158,
- SHL64m1 = 2159,
- SHL64mCL = 2160,
- SHL64mi = 2161,
- SHL64r1 = 2162,
- SHL64rCL = 2163,
- SHL64ri = 2164,
- SHL8m1 = 2165,
- SHL8mCL = 2166,
- SHL8mi = 2167,
- SHL8r1 = 2168,
- SHL8rCL = 2169,
- SHL8ri = 2170,
- SHLD16mrCL = 2171,
- SHLD16mri8 = 2172,
- SHLD16rrCL = 2173,
- SHLD16rri8 = 2174,
- SHLD32mrCL = 2175,
- SHLD32mri8 = 2176,
- SHLD32rrCL = 2177,
- SHLD32rri8 = 2178,
- SHLD64mrCL = 2179,
- SHLD64mri8 = 2180,
- SHLD64rrCL = 2181,
- SHLD64rri8 = 2182,
- SHR16m1 = 2183,
- SHR16mCL = 2184,
- SHR16mi = 2185,
- SHR16r1 = 2186,
- SHR16rCL = 2187,
- SHR16ri = 2188,
- SHR32m1 = 2189,
- SHR32mCL = 2190,
- SHR32mi = 2191,
- SHR32r1 = 2192,
- SHR32rCL = 2193,
- SHR32ri = 2194,
- SHR64m1 = 2195,
- SHR64mCL = 2196,
- SHR64mi = 2197,
- SHR64r1 = 2198,
- SHR64rCL = 2199,
- SHR64ri = 2200,
- SHR8m1 = 2201,
- SHR8mCL = 2202,
- SHR8mi = 2203,
- SHR8r1 = 2204,
- SHR8rCL = 2205,
- SHR8ri = 2206,
- SHRD16mrCL = 2207,
- SHRD16mri8 = 2208,
- SHRD16rrCL = 2209,
- SHRD16rri8 = 2210,
- SHRD32mrCL = 2211,
- SHRD32mri8 = 2212,
- SHRD32rrCL = 2213,
- SHRD32rri8 = 2214,
- SHRD64mrCL = 2215,
- SHRD64mri8 = 2216,
- SHRD64rrCL = 2217,
- SHRD64rri8 = 2218,
- SHUFPDrmi = 2219,
- SHUFPDrri = 2220,
- SHUFPSrmi = 2221,
- SHUFPSrri = 2222,
- SIDTm = 2223,
- SIN_F = 2224,
- SIN_Fp32 = 2225,
- SIN_Fp64 = 2226,
- SIN_Fp80 = 2227,
- SLDT16m = 2228,
- SLDT16r = 2229,
- SLDT64m = 2230,
- SLDT64r = 2231,
- SMSW16m = 2232,
- SMSW16r = 2233,
- SMSW32r = 2234,
- SMSW64r = 2235,
- SQRTPDm = 2236,
- SQRTPDm_Int = 2237,
- SQRTPDr = 2238,
- SQRTPDr_Int = 2239,
- SQRTPSm = 2240,
- SQRTPSm_Int = 2241,
- SQRTPSr = 2242,
- SQRTPSr_Int = 2243,
- SQRTSDm = 2244,
- SQRTSDm_Int = 2245,
- SQRTSDr = 2246,
- SQRTSDr_Int = 2247,
- SQRTSSm = 2248,
- SQRTSSm_Int = 2249,
- SQRTSSr = 2250,
- SQRTSSr_Int = 2251,
- SQRT_F = 2252,
- SQRT_Fp32 = 2253,
- SQRT_Fp64 = 2254,
- SQRT_Fp80 = 2255,
- STC = 2256,
- STD = 2257,
- STI = 2258,
- STMXCSR = 2259,
- STRm = 2260,
- STRr = 2261,
- ST_F32m = 2262,
- ST_F64m = 2263,
- ST_FP32m = 2264,
- ST_FP64m = 2265,
- ST_FP80m = 2266,
- ST_FPrr = 2267,
- ST_Fp32m = 2268,
- ST_Fp64m = 2269,
- ST_Fp64m32 = 2270,
- ST_Fp80m32 = 2271,
- ST_Fp80m64 = 2272,
- ST_FpP32m = 2273,
- ST_FpP64m = 2274,
- ST_FpP64m32 = 2275,
- ST_FpP80m = 2276,
- ST_FpP80m32 = 2277,
- ST_FpP80m64 = 2278,
- ST_Frr = 2279,
- SUB16i16 = 2280,
- SUB16mi = 2281,
- SUB16mi8 = 2282,
- SUB16mr = 2283,
- SUB16ri = 2284,
- SUB16ri8 = 2285,
- SUB16rm = 2286,
- SUB16rr = 2287,
- SUB16rr_REV = 2288,
- SUB32i32 = 2289,
- SUB32mi = 2290,
- SUB32mi8 = 2291,
- SUB32mr = 2292,
- SUB32ri = 2293,
- SUB32ri8 = 2294,
- SUB32rm = 2295,
- SUB32rr = 2296,
- SUB32rr_REV = 2297,
- SUB64i32 = 2298,
- SUB64mi32 = 2299,
- SUB64mi8 = 2300,
- SUB64mr = 2301,
- SUB64ri32 = 2302,
- SUB64ri8 = 2303,
- SUB64rm = 2304,
- SUB64rr = 2305,
- SUB64rr_REV = 2306,
- SUB8i8 = 2307,
- SUB8mi = 2308,
- SUB8mr = 2309,
- SUB8ri = 2310,
- SUB8rm = 2311,
- SUB8rr = 2312,
- SUB8rr_REV = 2313,
- SUBPDrm = 2314,
- SUBPDrr = 2315,
- SUBPSrm = 2316,
- SUBPSrr = 2317,
- SUBR_F32m = 2318,
- SUBR_F64m = 2319,
- SUBR_FI16m = 2320,
- SUBR_FI32m = 2321,
- SUBR_FPrST0 = 2322,
- SUBR_FST0r = 2323,
- SUBR_Fp32m = 2324,
- SUBR_Fp64m = 2325,
- SUBR_Fp64m32 = 2326,
- SUBR_Fp80m32 = 2327,
- SUBR_Fp80m64 = 2328,
- SUBR_FpI16m32 = 2329,
- SUBR_FpI16m64 = 2330,
- SUBR_FpI16m80 = 2331,
- SUBR_FpI32m32 = 2332,
- SUBR_FpI32m64 = 2333,
- SUBR_FpI32m80 = 2334,
- SUBR_FrST0 = 2335,
- SUBSDrm = 2336,
- SUBSDrm_Int = 2337,
- SUBSDrr = 2338,
- SUBSDrr_Int = 2339,
- SUBSSrm = 2340,
- SUBSSrm_Int = 2341,
- SUBSSrr = 2342,
- SUBSSrr_Int = 2343,
- SUB_F32m = 2344,
- SUB_F64m = 2345,
- SUB_FI16m = 2346,
- SUB_FI32m = 2347,
- SUB_FPrST0 = 2348,
- SUB_FST0r = 2349,
- SUB_Fp32 = 2350,
- SUB_Fp32m = 2351,
- SUB_Fp64 = 2352,
- SUB_Fp64m = 2353,
- SUB_Fp64m32 = 2354,
- SUB_Fp80 = 2355,
- SUB_Fp80m32 = 2356,
- SUB_Fp80m64 = 2357,
- SUB_FpI16m32 = 2358,
- SUB_FpI16m64 = 2359,
- SUB_FpI16m80 = 2360,
- SUB_FpI32m32 = 2361,
- SUB_FpI32m64 = 2362,
- SUB_FpI32m80 = 2363,
- SUB_FrST0 = 2364,
- SWPGS = 2365,
- SYSCALL = 2366,
- SYSENTER = 2367,
- SYSEXIT = 2368,
- SYSEXIT64 = 2369,
- SYSRET = 2370,
- TAILJMPd = 2371,
- TAILJMPm = 2372,
- TAILJMPr = 2373,
- TAILJMPr64 = 2374,
- TCRETURNdi = 2375,
- TCRETURNdi64 = 2376,
- TCRETURNri = 2377,
- TCRETURNri64 = 2378,
- TEST16i16 = 2379,
- TEST16mi = 2380,
- TEST16ri = 2381,
- TEST16rm = 2382,
- TEST16rr = 2383,
- TEST32i32 = 2384,
- TEST32mi = 2385,
- TEST32ri = 2386,
- TEST32rm = 2387,
- TEST32rr = 2388,
- TEST64i32 = 2389,
- TEST64mi32 = 2390,
- TEST64ri32 = 2391,
- TEST64rm = 2392,
- TEST64rr = 2393,
- TEST8i8 = 2394,
- TEST8mi = 2395,
- TEST8ri = 2396,
- TEST8rm = 2397,
- TEST8rr = 2398,
- TLS_addr32 = 2399,
- TLS_addr64 = 2400,
- TRAP = 2401,
- TST_F = 2402,
- TST_Fp32 = 2403,
- TST_Fp64 = 2404,
- TST_Fp80 = 2405,
- UCOMISDrm = 2406,
- UCOMISDrr = 2407,
- UCOMISSrm = 2408,
- UCOMISSrr = 2409,
- UCOM_FIPr = 2410,
- UCOM_FIr = 2411,
- UCOM_FPPr = 2412,
- UCOM_FPr = 2413,
- UCOM_FpIr32 = 2414,
- UCOM_FpIr64 = 2415,
- UCOM_FpIr80 = 2416,
- UCOM_Fpr32 = 2417,
- UCOM_Fpr64 = 2418,
- UCOM_Fpr80 = 2419,
- UCOM_Fr = 2420,
- UNPCKHPDrm = 2421,
- UNPCKHPDrr = 2422,
- UNPCKHPSrm = 2423,
- UNPCKHPSrr = 2424,
- UNPCKLPDrm = 2425,
- UNPCKLPDrr = 2426,
- UNPCKLPSrm = 2427,
- UNPCKLPSrr = 2428,
- VASTART_SAVE_XMM_REGS = 2429,
- VERRm = 2430,
- VERRr = 2431,
- VERWm = 2432,
- VERWr = 2433,
- VMCALL = 2434,
- VMCLEARm = 2435,
- VMLAUNCH = 2436,
- VMPTRLDm = 2437,
- VMPTRSTm = 2438,
- VMREAD32rm = 2439,
- VMREAD32rr = 2440,
- VMREAD64rm = 2441,
- VMREAD64rr = 2442,
- VMRESUME = 2443,
- VMWRITE32rm = 2444,
- VMWRITE32rr = 2445,
- VMWRITE64rm = 2446,
- VMWRITE64rr = 2447,
- VMXOFF = 2448,
- VMXON = 2449,
- V_SET0 = 2450,
- V_SETALLONES = 2451,
- WAIT = 2452,
- WBINVD = 2453,
- WINCALL64m = 2454,
- WINCALL64pcrel32 = 2455,
- WINCALL64r = 2456,
- WRMSR = 2457,
- XADD16rm = 2458,
- XADD16rr = 2459,
- XADD32rm = 2460,
- XADD32rr = 2461,
- XADD64rm = 2462,
- XADD64rr = 2463,
- XADD8rm = 2464,
- XADD8rr = 2465,
- XCHG16ar = 2466,
- XCHG16rm = 2467,
- XCHG16rr = 2468,
- XCHG32ar = 2469,
- XCHG32rm = 2470,
- XCHG32rr = 2471,
- XCHG64ar = 2472,
- XCHG64rm = 2473,
- XCHG64rr = 2474,
- XCHG8rm = 2475,
- XCHG8rr = 2476,
- XCH_F = 2477,
- XLAT = 2478,
- XOR16i16 = 2479,
- XOR16mi = 2480,
- XOR16mi8 = 2481,
- XOR16mr = 2482,
- XOR16ri = 2483,
- XOR16ri8 = 2484,
- XOR16rm = 2485,
- XOR16rr = 2486,
- XOR16rr_REV = 2487,
- XOR32i32 = 2488,
- XOR32mi = 2489,
- XOR32mi8 = 2490,
- XOR32mr = 2491,
- XOR32ri = 2492,
- XOR32ri8 = 2493,
- XOR32rm = 2494,
- XOR32rr = 2495,
- XOR32rr_REV = 2496,
- XOR64i32 = 2497,
- XOR64mi32 = 2498,
- XOR64mi8 = 2499,
- XOR64mr = 2500,
- XOR64ri32 = 2501,
- XOR64ri8 = 2502,
- XOR64rm = 2503,
- XOR64rr = 2504,
- XOR64rr_REV = 2505,
- XOR8i8 = 2506,
- XOR8mi = 2507,
- XOR8mr = 2508,
- XOR8ri = 2509,
- XOR8rm = 2510,
- XOR8rr = 2511,
- XOR8rr_REV = 2512,
- XORPDrm = 2513,
- XORPDrr = 2514,
- XORPSrm = 2515,
- XORPSrr = 2516,
- INSTRUCTION_LIST_END = 2517
+ CS_PREFIX = 504,
+ CVTDQ2PDrm = 505,
+ CVTDQ2PDrr = 506,
+ CVTDQ2PSrm = 507,
+ CVTDQ2PSrr = 508,
+ CVTPD2DQrm = 509,
+ CVTPD2DQrr = 510,
+ CVTPD2PSrm = 511,
+ CVTPD2PSrr = 512,
+ CVTPS2DQrm = 513,
+ CVTPS2DQrr = 514,
+ CVTPS2PDrm = 515,
+ CVTPS2PDrr = 516,
+ CVTSD2SI64rm = 517,
+ CVTSD2SI64rr = 518,
+ CVTSD2SSrm = 519,
+ CVTSD2SSrr = 520,
+ CVTSI2SD64rm = 521,
+ CVTSI2SD64rr = 522,
+ CVTSI2SDrm = 523,
+ CVTSI2SDrr = 524,
+ CVTSI2SS64rm = 525,
+ CVTSI2SS64rr = 526,
+ CVTSI2SSrm = 527,
+ CVTSI2SSrr = 528,
+ CVTSS2SDrm = 529,
+ CVTSS2SDrr = 530,
+ CVTSS2SI64rm = 531,
+ CVTSS2SI64rr = 532,
+ CVTSS2SIrm = 533,
+ CVTSS2SIrr = 534,
+ CVTTPS2DQrm = 535,
+ CVTTPS2DQrr = 536,
+ CVTTSD2SI64rm = 537,
+ CVTTSD2SI64rr = 538,
+ CVTTSD2SIrm = 539,
+ CVTTSD2SIrr = 540,
+ CVTTSS2SI64rm = 541,
+ CVTTSS2SI64rr = 542,
+ CVTTSS2SIrm = 543,
+ CVTTSS2SIrr = 544,
+ CWD = 545,
+ CWDE = 546,
+ DEC16m = 547,
+ DEC16r = 548,
+ DEC32m = 549,
+ DEC32r = 550,
+ DEC64_16m = 551,
+ DEC64_16r = 552,
+ DEC64_32m = 553,
+ DEC64_32r = 554,
+ DEC64m = 555,
+ DEC64r = 556,
+ DEC8m = 557,
+ DEC8r = 558,
+ DIV16m = 559,
+ DIV16r = 560,
+ DIV32m = 561,
+ DIV32r = 562,
+ DIV64m = 563,
+ DIV64r = 564,
+ DIV8m = 565,
+ DIV8r = 566,
+ DIVPDrm = 567,
+ DIVPDrr = 568,
+ DIVPSrm = 569,
+ DIVPSrr = 570,
+ DIVR_F32m = 571,
+ DIVR_F64m = 572,
+ DIVR_FI16m = 573,
+ DIVR_FI32m = 574,
+ DIVR_FPrST0 = 575,
+ DIVR_FST0r = 576,
+ DIVR_Fp32m = 577,
+ DIVR_Fp64m = 578,
+ DIVR_Fp64m32 = 579,
+ DIVR_Fp80m32 = 580,
+ DIVR_Fp80m64 = 581,
+ DIVR_FpI16m32 = 582,
+ DIVR_FpI16m64 = 583,
+ DIVR_FpI16m80 = 584,
+ DIVR_FpI32m32 = 585,
+ DIVR_FpI32m64 = 586,
+ DIVR_FpI32m80 = 587,
+ DIVR_FrST0 = 588,
+ DIVSDrm = 589,
+ DIVSDrm_Int = 590,
+ DIVSDrr = 591,
+ DIVSDrr_Int = 592,
+ DIVSSrm = 593,
+ DIVSSrm_Int = 594,
+ DIVSSrr = 595,
+ DIVSSrr_Int = 596,
+ DIV_F32m = 597,
+ DIV_F64m = 598,
+ DIV_FI16m = 599,
+ DIV_FI32m = 600,
+ DIV_FPrST0 = 601,
+ DIV_FST0r = 602,
+ DIV_Fp32 = 603,
+ DIV_Fp32m = 604,
+ DIV_Fp64 = 605,
+ DIV_Fp64m = 606,
+ DIV_Fp64m32 = 607,
+ DIV_Fp80 = 608,
+ DIV_Fp80m32 = 609,
+ DIV_Fp80m64 = 610,
+ DIV_FpI16m32 = 611,
+ DIV_FpI16m64 = 612,
+ DIV_FpI16m80 = 613,
+ DIV_FpI32m32 = 614,
+ DIV_FpI32m64 = 615,
+ DIV_FpI32m80 = 616,
+ DIV_FrST0 = 617,
+ DPPDrmi = 618,
+ DPPDrri = 619,
+ DPPSrmi = 620,
+ DPPSrri = 621,
+ DS_PREFIX = 622,
+ EH_RETURN = 623,
+ EH_RETURN64 = 624,
+ ENTER = 625,
+ ES_PREFIX = 626,
+ EXTRACTPSmr = 627,
+ EXTRACTPSrr = 628,
+ F2XM1 = 629,
+ FARCALL16i = 630,
+ FARCALL16m = 631,
+ FARCALL32i = 632,
+ FARCALL32m = 633,
+ FARCALL64 = 634,
+ FARJMP16i = 635,
+ FARJMP16m = 636,
+ FARJMP32i = 637,
+ FARJMP32m = 638,
+ FARJMP64 = 639,
+ FBLDm = 640,
+ FBSTPm = 641,
+ FCOM32m = 642,
+ FCOM64m = 643,
+ FCOMP32m = 644,
+ FCOMP64m = 645,
+ FCOMPP = 646,
+ FDECSTP = 647,
+ FFREE = 648,
+ FICOM16m = 649,
+ FICOM32m = 650,
+ FICOMP16m = 651,
+ FICOMP32m = 652,
+ FINCSTP = 653,
+ FLDCW16m = 654,
+ FLDENVm = 655,
+ FLDL2E = 656,
+ FLDL2T = 657,
+ FLDLG2 = 658,
+ FLDLN2 = 659,
+ FLDPI = 660,
+ FNCLEX = 661,
+ FNINIT = 662,
+ FNOP = 663,
+ FNSTCW16m = 664,
+ FNSTSW8r = 665,
+ FNSTSWm = 666,
+ FP32_TO_INT16_IN_MEM = 667,
+ FP32_TO_INT32_IN_MEM = 668,
+ FP32_TO_INT64_IN_MEM = 669,
+ FP64_TO_INT16_IN_MEM = 670,
+ FP64_TO_INT32_IN_MEM = 671,
+ FP64_TO_INT64_IN_MEM = 672,
+ FP80_TO_INT16_IN_MEM = 673,
+ FP80_TO_INT32_IN_MEM = 674,
+ FP80_TO_INT64_IN_MEM = 675,
+ FPATAN = 676,
+ FPREM = 677,
+ FPREM1 = 678,
+ FPTAN = 679,
+ FP_REG_KILL = 680,
+ FRNDINT = 681,
+ FRSTORm = 682,
+ FSAVEm = 683,
+ FSCALE = 684,
+ FSINCOS = 685,
+ FSTENVm = 686,
+ FS_MOV32rm = 687,
+ FS_PREFIX = 688,
+ FXAM = 689,
+ FXRSTOR = 690,
+ FXSAVE = 691,
+ FXTRACT = 692,
+ FYL2X = 693,
+ FYL2XP1 = 694,
+ FpGET_ST0_32 = 695,
+ FpGET_ST0_64 = 696,
+ FpGET_ST0_80 = 697,
+ FpGET_ST1_32 = 698,
+ FpGET_ST1_64 = 699,
+ FpGET_ST1_80 = 700,
+ FpSET_ST0_32 = 701,
+ FpSET_ST0_64 = 702,
+ FpSET_ST0_80 = 703,
+ FpSET_ST1_32 = 704,
+ FpSET_ST1_64 = 705,
+ FpSET_ST1_80 = 706,
+ FsANDNPDrm = 707,
+ FsANDNPDrr = 708,
+ FsANDNPSrm = 709,
+ FsANDNPSrr = 710,
+ FsANDPDrm = 711,
+ FsANDPDrr = 712,
+ FsANDPSrm = 713,
+ FsANDPSrr = 714,
+ FsFLD0SD = 715,
+ FsFLD0SS = 716,
+ FsMOVAPDrm = 717,
+ FsMOVAPDrr = 718,
+ FsMOVAPSrm = 719,
+ FsMOVAPSrr = 720,
+ FsORPDrm = 721,
+ FsORPDrr = 722,
+ FsORPSrm = 723,
+ FsORPSrr = 724,
+ FsXORPDrm = 725,
+ FsXORPDrr = 726,
+ FsXORPSrm = 727,
+ FsXORPSrr = 728,
+ GS_MOV32rm = 729,
+ GS_PREFIX = 730,
+ HADDPDrm = 731,
+ HADDPDrr = 732,
+ HADDPSrm = 733,
+ HADDPSrr = 734,
+ HLT = 735,
+ HSUBPDrm = 736,
+ HSUBPDrr = 737,
+ HSUBPSrm = 738,
+ HSUBPSrr = 739,
+ IDIV16m = 740,
+ IDIV16r = 741,
+ IDIV32m = 742,
+ IDIV32r = 743,
+ IDIV64m = 744,
+ IDIV64r = 745,
+ IDIV8m = 746,
+ IDIV8r = 747,
+ ILD_F16m = 748,
+ ILD_F32m = 749,
+ ILD_F64m = 750,
+ ILD_Fp16m32 = 751,
+ ILD_Fp16m64 = 752,
+ ILD_Fp16m80 = 753,
+ ILD_Fp32m32 = 754,
+ ILD_Fp32m64 = 755,
+ ILD_Fp32m80 = 756,
+ ILD_Fp64m32 = 757,
+ ILD_Fp64m64 = 758,
+ ILD_Fp64m80 = 759,
+ IMUL16m = 760,
+ IMUL16r = 761,
+ IMUL16rm = 762,
+ IMUL16rmi = 763,
+ IMUL16rmi8 = 764,
+ IMUL16rr = 765,
+ IMUL16rri = 766,
+ IMUL16rri8 = 767,
+ IMUL32m = 768,
+ IMUL32r = 769,
+ IMUL32rm = 770,
+ IMUL32rmi = 771,
+ IMUL32rmi8 = 772,
+ IMUL32rr = 773,
+ IMUL32rri = 774,
+ IMUL32rri8 = 775,
+ IMUL64m = 776,
+ IMUL64r = 777,
+ IMUL64rm = 778,
+ IMUL64rmi32 = 779,
+ IMUL64rmi8 = 780,
+ IMUL64rr = 781,
+ IMUL64rri32 = 782,
+ IMUL64rri8 = 783,
+ IMUL8m = 784,
+ IMUL8r = 785,
+ IN16 = 786,
+ IN16ri = 787,
+ IN16rr = 788,
+ IN32 = 789,
+ IN32ri = 790,
+ IN32rr = 791,
+ IN8 = 792,
+ IN8ri = 793,
+ IN8rr = 794,
+ INC16m = 795,
+ INC16r = 796,
+ INC32m = 797,
+ INC32r = 798,
+ INC64_16m = 799,
+ INC64_16r = 800,
+ INC64_32m = 801,
+ INC64_32r = 802,
+ INC64m = 803,
+ INC64r = 804,
+ INC8m = 805,
+ INC8r = 806,
+ INSERTPSrm = 807,
+ INSERTPSrr = 808,
+ INT = 809,
+ INT3 = 810,
+ INVD = 811,
+ INVEPT = 812,
+ INVLPG = 813,
+ INVVPID = 814,
+ IRET16 = 815,
+ IRET32 = 816,
+ IRET64 = 817,
+ ISTT_FP16m = 818,
+ ISTT_FP32m = 819,
+ ISTT_FP64m = 820,
+ ISTT_Fp16m32 = 821,
+ ISTT_Fp16m64 = 822,
+ ISTT_Fp16m80 = 823,
+ ISTT_Fp32m32 = 824,
+ ISTT_Fp32m64 = 825,
+ ISTT_Fp32m80 = 826,
+ ISTT_Fp64m32 = 827,
+ ISTT_Fp64m64 = 828,
+ ISTT_Fp64m80 = 829,
+ IST_F16m = 830,
+ IST_F32m = 831,
+ IST_FP16m = 832,
+ IST_FP32m = 833,
+ IST_FP64m = 834,
+ IST_Fp16m32 = 835,
+ IST_Fp16m64 = 836,
+ IST_Fp16m80 = 837,
+ IST_Fp32m32 = 838,
+ IST_Fp32m64 = 839,
+ IST_Fp32m80 = 840,
+ IST_Fp64m32 = 841,
+ IST_Fp64m64 = 842,
+ IST_Fp64m80 = 843,
+ Int_CMPSDrm = 844,
+ Int_CMPSDrr = 845,
+ Int_CMPSSrm = 846,
+ Int_CMPSSrr = 847,
+ Int_COMISDrm = 848,
+ Int_COMISDrr = 849,
+ Int_COMISSrm = 850,
+ Int_COMISSrr = 851,
+ Int_CVTDQ2PDrm = 852,
+ Int_CVTDQ2PDrr = 853,
+ Int_CVTDQ2PSrm = 854,
+ Int_CVTDQ2PSrr = 855,
+ Int_CVTPD2DQrm = 856,
+ Int_CVTPD2DQrr = 857,
+ Int_CVTPD2PIrm = 858,
+ Int_CVTPD2PIrr = 859,
+ Int_CVTPD2PSrm = 860,
+ Int_CVTPD2PSrr = 861,
+ Int_CVTPI2PDrm = 862,
+ Int_CVTPI2PDrr = 863,
+ Int_CVTPI2PSrm = 864,
+ Int_CVTPI2PSrr = 865,
+ Int_CVTPS2DQrm = 866,
+ Int_CVTPS2DQrr = 867,
+ Int_CVTPS2PDrm = 868,
+ Int_CVTPS2PDrr = 869,
+ Int_CVTPS2PIrm = 870,
+ Int_CVTPS2PIrr = 871,
+ Int_CVTSD2SI64rm = 872,
+ Int_CVTSD2SI64rr = 873,
+ Int_CVTSD2SIrm = 874,
+ Int_CVTSD2SIrr = 875,
+ Int_CVTSD2SSrm = 876,
+ Int_CVTSD2SSrr = 877,
+ Int_CVTSI2SD64rm = 878,
+ Int_CVTSI2SD64rr = 879,
+ Int_CVTSI2SDrm = 880,
+ Int_CVTSI2SDrr = 881,
+ Int_CVTSI2SS64rm = 882,
+ Int_CVTSI2SS64rr = 883,
+ Int_CVTSI2SSrm = 884,
+ Int_CVTSI2SSrr = 885,
+ Int_CVTSS2SDrm = 886,
+ Int_CVTSS2SDrr = 887,
+ Int_CVTSS2SI64rm = 888,
+ Int_CVTSS2SI64rr = 889,
+ Int_CVTSS2SIrm = 890,
+ Int_CVTSS2SIrr = 891,
+ Int_CVTTPD2DQrm = 892,
+ Int_CVTTPD2DQrr = 893,
+ Int_CVTTPD2PIrm = 894,
+ Int_CVTTPD2PIrr = 895,
+ Int_CVTTPS2DQrm = 896,
+ Int_CVTTPS2DQrr = 897,
+ Int_CVTTPS2PIrm = 898,
+ Int_CVTTPS2PIrr = 899,
+ Int_CVTTSD2SI64rm = 900,
+ Int_CVTTSD2SI64rr = 901,
+ Int_CVTTSD2SIrm = 902,
+ Int_CVTTSD2SIrr = 903,
+ Int_CVTTSS2SI64rm = 904,
+ Int_CVTTSS2SI64rr = 905,
+ Int_CVTTSS2SIrm = 906,
+ Int_CVTTSS2SIrr = 907,
+ Int_UCOMISDrm = 908,
+ Int_UCOMISDrr = 909,
+ Int_UCOMISSrm = 910,
+ Int_UCOMISSrr = 911,
+ JAE_1 = 912,
+ JAE_4 = 913,
+ JA_1 = 914,
+ JA_4 = 915,
+ JBE_1 = 916,
+ JBE_4 = 917,
+ JB_1 = 918,
+ JB_4 = 919,
+ JCXZ8 = 920,
+ JE_1 = 921,
+ JE_4 = 922,
+ JGE_1 = 923,
+ JGE_4 = 924,
+ JG_1 = 925,
+ JG_4 = 926,
+ JLE_1 = 927,
+ JLE_4 = 928,
+ JL_1 = 929,
+ JL_4 = 930,
+ JMP32m = 931,
+ JMP32r = 932,
+ JMP64m = 933,
+ JMP64pcrel32 = 934,
+ JMP64r = 935,
+ JMP_1 = 936,
+ JMP_4 = 937,
+ JNE_1 = 938,
+ JNE_4 = 939,
+ JNO_1 = 940,
+ JNO_4 = 941,
+ JNP_1 = 942,
+ JNP_4 = 943,
+ JNS_1 = 944,
+ JNS_4 = 945,
+ JO_1 = 946,
+ JO_4 = 947,
+ JP_1 = 948,
+ JP_4 = 949,
+ JS_1 = 950,
+ JS_4 = 951,
+ LAHF = 952,
+ LAR16rm = 953,
+ LAR16rr = 954,
+ LAR32rm = 955,
+ LAR32rr = 956,
+ LAR64rm = 957,
+ LAR64rr = 958,
+ LCMPXCHG16 = 959,
+ LCMPXCHG32 = 960,
+ LCMPXCHG64 = 961,
+ LCMPXCHG8 = 962,
+ LCMPXCHG8B = 963,
+ LDDQUrm = 964,
+ LDMXCSR = 965,
+ LDS16rm = 966,
+ LDS32rm = 967,
+ LD_F0 = 968,
+ LD_F1 = 969,
+ LD_F32m = 970,
+ LD_F64m = 971,
+ LD_F80m = 972,
+ LD_Fp032 = 973,
+ LD_Fp064 = 974,
+ LD_Fp080 = 975,
+ LD_Fp132 = 976,
+ LD_Fp164 = 977,
+ LD_Fp180 = 978,
+ LD_Fp32m = 979,
+ LD_Fp32m64 = 980,
+ LD_Fp32m80 = 981,
+ LD_Fp64m = 982,
+ LD_Fp64m80 = 983,
+ LD_Fp80m = 984,
+ LD_Frr = 985,
+ LEA16r = 986,
+ LEA32r = 987,
+ LEA64_32r = 988,
+ LEA64r = 989,
+ LEAVE = 990,
+ LEAVE64 = 991,
+ LES16rm = 992,
+ LES32rm = 993,
+ LFENCE = 994,
+ LFS16rm = 995,
+ LFS32rm = 996,
+ LFS64rm = 997,
+ LGDTm = 998,
+ LGS16rm = 999,
+ LGS32rm = 1000,
+ LGS64rm = 1001,
+ LIDTm = 1002,
+ LLDT16m = 1003,
+ LLDT16r = 1004,
+ LMSW16m = 1005,
+ LMSW16r = 1006,
+ LOCK_ADD16mi = 1007,
+ LOCK_ADD16mi8 = 1008,
+ LOCK_ADD16mr = 1009,
+ LOCK_ADD32mi = 1010,
+ LOCK_ADD32mi8 = 1011,
+ LOCK_ADD32mr = 1012,
+ LOCK_ADD64mi32 = 1013,
+ LOCK_ADD64mi8 = 1014,
+ LOCK_ADD64mr = 1015,
+ LOCK_ADD8mi = 1016,
+ LOCK_ADD8mr = 1017,
+ LOCK_DEC16m = 1018,
+ LOCK_DEC32m = 1019,
+ LOCK_DEC64m = 1020,
+ LOCK_DEC8m = 1021,
+ LOCK_INC16m = 1022,
+ LOCK_INC32m = 1023,
+ LOCK_INC64m = 1024,
+ LOCK_INC8m = 1025,
+ LOCK_PREFIX = 1026,
+ LOCK_SUB16mi = 1027,
+ LOCK_SUB16mi8 = 1028,
+ LOCK_SUB16mr = 1029,
+ LOCK_SUB32mi = 1030,
+ LOCK_SUB32mi8 = 1031,
+ LOCK_SUB32mr = 1032,
+ LOCK_SUB64mi32 = 1033,
+ LOCK_SUB64mi8 = 1034,
+ LOCK_SUB64mr = 1035,
+ LOCK_SUB8mi = 1036,
+ LOCK_SUB8mr = 1037,
+ LODSB = 1038,
+ LODSD = 1039,
+ LODSQ = 1040,
+ LODSW = 1041,
+ LOOP = 1042,
+ LOOPE = 1043,
+ LOOPNE = 1044,
+ LRET = 1045,
+ LRETI = 1046,
+ LSL16rm = 1047,
+ LSL16rr = 1048,
+ LSL32rm = 1049,
+ LSL32rr = 1050,
+ LSL64rm = 1051,
+ LSL64rr = 1052,
+ LSS16rm = 1053,
+ LSS32rm = 1054,
+ LSS64rm = 1055,
+ LTRm = 1056,
+ LTRr = 1057,
+ LXADD16 = 1058,
+ LXADD32 = 1059,
+ LXADD64 = 1060,
+ LXADD8 = 1061,
+ MASKMOVDQU = 1062,
+ MASKMOVDQU64 = 1063,
+ MAXPDrm = 1064,
+ MAXPDrm_Int = 1065,
+ MAXPDrr = 1066,
+ MAXPDrr_Int = 1067,
+ MAXPSrm = 1068,
+ MAXPSrm_Int = 1069,
+ MAXPSrr = 1070,
+ MAXPSrr_Int = 1071,
+ MAXSDrm = 1072,
+ MAXSDrm_Int = 1073,
+ MAXSDrr = 1074,
+ MAXSDrr_Int = 1075,
+ MAXSSrm = 1076,
+ MAXSSrm_Int = 1077,
+ MAXSSrr = 1078,
+ MAXSSrr_Int = 1079,
+ MFENCE = 1080,
+ MINPDrm = 1081,
+ MINPDrm_Int = 1082,
+ MINPDrr = 1083,
+ MINPDrr_Int = 1084,
+ MINPSrm = 1085,
+ MINPSrm_Int = 1086,
+ MINPSrr = 1087,
+ MINPSrr_Int = 1088,
+ MINSDrm = 1089,
+ MINSDrm_Int = 1090,
+ MINSDrr = 1091,
+ MINSDrr_Int = 1092,
+ MINSSrm = 1093,
+ MINSSrm_Int = 1094,
+ MINSSrr = 1095,
+ MINSSrr_Int = 1096,
+ MMX_CVTPD2PIrm = 1097,
+ MMX_CVTPD2PIrr = 1098,
+ MMX_CVTPI2PDrm = 1099,
+ MMX_CVTPI2PDrr = 1100,
+ MMX_CVTPI2PSrm = 1101,
+ MMX_CVTPI2PSrr = 1102,
+ MMX_CVTPS2PIrm = 1103,
+ MMX_CVTPS2PIrr = 1104,
+ MMX_CVTTPD2PIrm = 1105,
+ MMX_CVTTPD2PIrr = 1106,
+ MMX_CVTTPS2PIrm = 1107,
+ MMX_CVTTPS2PIrr = 1108,
+ MMX_EMMS = 1109,
+ MMX_FEMMS = 1110,
+ MMX_MASKMOVQ = 1111,
+ MMX_MASKMOVQ64 = 1112,
+ MMX_MOVD64from64rr = 1113,
+ MMX_MOVD64grr = 1114,
+ MMX_MOVD64mr = 1115,
+ MMX_MOVD64rm = 1116,
+ MMX_MOVD64rr = 1117,
+ MMX_MOVD64rrv164 = 1118,
+ MMX_MOVD64to64rr = 1119,
+ MMX_MOVDQ2Qrr = 1120,
+ MMX_MOVNTQmr = 1121,
+ MMX_MOVQ2DQrr = 1122,
+ MMX_MOVQ2FR64rr = 1123,
+ MMX_MOVQ64gmr = 1124,
+ MMX_MOVQ64mr = 1125,
+ MMX_MOVQ64rm = 1126,
+ MMX_MOVQ64rr = 1127,
+ MMX_MOVZDI2PDIrm = 1128,
+ MMX_MOVZDI2PDIrr = 1129,
+ MMX_PACKSSDWrm = 1130,
+ MMX_PACKSSDWrr = 1131,
+ MMX_PACKSSWBrm = 1132,
+ MMX_PACKSSWBrr = 1133,
+ MMX_PACKUSWBrm = 1134,
+ MMX_PACKUSWBrr = 1135,
+ MMX_PADDBrm = 1136,
+ MMX_PADDBrr = 1137,
+ MMX_PADDDrm = 1138,
+ MMX_PADDDrr = 1139,
+ MMX_PADDQrm = 1140,
+ MMX_PADDQrr = 1141,
+ MMX_PADDSBrm = 1142,
+ MMX_PADDSBrr = 1143,
+ MMX_PADDSWrm = 1144,
+ MMX_PADDSWrr = 1145,
+ MMX_PADDUSBrm = 1146,
+ MMX_PADDUSBrr = 1147,
+ MMX_PADDUSWrm = 1148,
+ MMX_PADDUSWrr = 1149,
+ MMX_PADDWrm = 1150,
+ MMX_PADDWrr = 1151,
+ MMX_PANDNrm = 1152,
+ MMX_PANDNrr = 1153,
+ MMX_PANDrm = 1154,
+ MMX_PANDrr = 1155,
+ MMX_PAVGBrm = 1156,
+ MMX_PAVGBrr = 1157,
+ MMX_PAVGWrm = 1158,
+ MMX_PAVGWrr = 1159,
+ MMX_PCMPEQBrm = 1160,
+ MMX_PCMPEQBrr = 1161,
+ MMX_PCMPEQDrm = 1162,
+ MMX_PCMPEQDrr = 1163,
+ MMX_PCMPEQWrm = 1164,
+ MMX_PCMPEQWrr = 1165,
+ MMX_PCMPGTBrm = 1166,
+ MMX_PCMPGTBrr = 1167,
+ MMX_PCMPGTDrm = 1168,
+ MMX_PCMPGTDrr = 1169,
+ MMX_PCMPGTWrm = 1170,
+ MMX_PCMPGTWrr = 1171,
+ MMX_PEXTRWri = 1172,
+ MMX_PINSRWrmi = 1173,
+ MMX_PINSRWrri = 1174,
+ MMX_PMADDWDrm = 1175,
+ MMX_PMADDWDrr = 1176,
+ MMX_PMAXSWrm = 1177,
+ MMX_PMAXSWrr = 1178,
+ MMX_PMAXUBrm = 1179,
+ MMX_PMAXUBrr = 1180,
+ MMX_PMINSWrm = 1181,
+ MMX_PMINSWrr = 1182,
+ MMX_PMINUBrm = 1183,
+ MMX_PMINUBrr = 1184,
+ MMX_PMOVMSKBrr = 1185,
+ MMX_PMULHUWrm = 1186,
+ MMX_PMULHUWrr = 1187,
+ MMX_PMULHWrm = 1188,
+ MMX_PMULHWrr = 1189,
+ MMX_PMULLWrm = 1190,
+ MMX_PMULLWrr = 1191,
+ MMX_PMULUDQrm = 1192,
+ MMX_PMULUDQrr = 1193,
+ MMX_PORrm = 1194,
+ MMX_PORrr = 1195,
+ MMX_PSADBWrm = 1196,
+ MMX_PSADBWrr = 1197,
+ MMX_PSHUFWmi = 1198,
+ MMX_PSHUFWri = 1199,
+ MMX_PSLLDri = 1200,
+ MMX_PSLLDrm = 1201,
+ MMX_PSLLDrr = 1202,
+ MMX_PSLLQri = 1203,
+ MMX_PSLLQrm = 1204,
+ MMX_PSLLQrr = 1205,
+ MMX_PSLLWri = 1206,
+ MMX_PSLLWrm = 1207,
+ MMX_PSLLWrr = 1208,
+ MMX_PSRADri = 1209,
+ MMX_PSRADrm = 1210,
+ MMX_PSRADrr = 1211,
+ MMX_PSRAWri = 1212,
+ MMX_PSRAWrm = 1213,
+ MMX_PSRAWrr = 1214,
+ MMX_PSRLDri = 1215,
+ MMX_PSRLDrm = 1216,
+ MMX_PSRLDrr = 1217,
+ MMX_PSRLQri = 1218,
+ MMX_PSRLQrm = 1219,
+ MMX_PSRLQrr = 1220,
+ MMX_PSRLWri = 1221,
+ MMX_PSRLWrm = 1222,
+ MMX_PSRLWrr = 1223,
+ MMX_PSUBBrm = 1224,
+ MMX_PSUBBrr = 1225,
+ MMX_PSUBDrm = 1226,
+ MMX_PSUBDrr = 1227,
+ MMX_PSUBQrm = 1228,
+ MMX_PSUBQrr = 1229,
+ MMX_PSUBSBrm = 1230,
+ MMX_PSUBSBrr = 1231,
+ MMX_PSUBSWrm = 1232,
+ MMX_PSUBSWrr = 1233,
+ MMX_PSUBUSBrm = 1234,
+ MMX_PSUBUSBrr = 1235,
+ MMX_PSUBUSWrm = 1236,
+ MMX_PSUBUSWrr = 1237,
+ MMX_PSUBWrm = 1238,
+ MMX_PSUBWrr = 1239,
+ MMX_PUNPCKHBWrm = 1240,
+ MMX_PUNPCKHBWrr = 1241,
+ MMX_PUNPCKHDQrm = 1242,
+ MMX_PUNPCKHDQrr = 1243,
+ MMX_PUNPCKHWDrm = 1244,
+ MMX_PUNPCKHWDrr = 1245,
+ MMX_PUNPCKLBWrm = 1246,
+ MMX_PUNPCKLBWrr = 1247,
+ MMX_PUNPCKLDQrm = 1248,
+ MMX_PUNPCKLDQrr = 1249,
+ MMX_PUNPCKLWDrm = 1250,
+ MMX_PUNPCKLWDrr = 1251,
+ MMX_PXORrm = 1252,
+ MMX_PXORrr = 1253,
+ MMX_V_SET0 = 1254,
+ MMX_V_SETALLONES = 1255,
+ MONITOR = 1256,
+ MOV16ao16 = 1257,
+ MOV16mi = 1258,
+ MOV16mr = 1259,
+ MOV16ms = 1260,
+ MOV16o16a = 1261,
+ MOV16r0 = 1262,
+ MOV16ri = 1263,
+ MOV16rm = 1264,
+ MOV16rr = 1265,
+ MOV16rr_REV = 1266,
+ MOV16rs = 1267,
+ MOV16sm = 1268,
+ MOV16sr = 1269,
+ MOV32ao32 = 1270,
+ MOV32cr = 1271,
+ MOV32dr = 1272,
+ MOV32mi = 1273,
+ MOV32mr = 1274,
+ MOV32o32a = 1275,
+ MOV32r0 = 1276,
+ MOV32rc = 1277,
+ MOV32rd = 1278,
+ MOV32ri = 1279,
+ MOV32rm = 1280,
+ MOV32rr = 1281,
+ MOV32rr_REV = 1282,
+ MOV64FSrm = 1283,
+ MOV64GSrm = 1284,
+ MOV64ao64 = 1285,
+ MOV64ao8 = 1286,
+ MOV64cr = 1287,
+ MOV64dr = 1288,
+ MOV64mi32 = 1289,
+ MOV64mr = 1290,
+ MOV64ms = 1291,
+ MOV64o64a = 1292,
+ MOV64o8a = 1293,
+ MOV64r0 = 1294,
+ MOV64rc = 1295,
+ MOV64rd = 1296,
+ MOV64ri = 1297,
+ MOV64ri32 = 1298,
+ MOV64ri64i32 = 1299,
+ MOV64rm = 1300,
+ MOV64rr = 1301,
+ MOV64rr_REV = 1302,
+ MOV64rs = 1303,
+ MOV64sm = 1304,
+ MOV64sr = 1305,
+ MOV64toPQIrr = 1306,
+ MOV64toSDrm = 1307,
+ MOV64toSDrr = 1308,
+ MOV8ao8 = 1309,
+ MOV8mi = 1310,
+ MOV8mr = 1311,
+ MOV8mr_NOREX = 1312,
+ MOV8o8a = 1313,
+ MOV8r0 = 1314,
+ MOV8ri = 1315,
+ MOV8rm = 1316,
+ MOV8rm_NOREX = 1317,
+ MOV8rr = 1318,
+ MOV8rr_NOREX = 1319,
+ MOV8rr_REV = 1320,
+ MOVAPDmr = 1321,
+ MOVAPDrm = 1322,
+ MOVAPDrr = 1323,
+ MOVAPSmr = 1324,
+ MOVAPSrm = 1325,
+ MOVAPSrr = 1326,
+ MOVDDUPrm = 1327,
+ MOVDDUPrr = 1328,
+ MOVDI2PDIrm = 1329,
+ MOVDI2PDIrr = 1330,
+ MOVDI2SSrm = 1331,
+ MOVDI2SSrr = 1332,
+ MOVDQAmr = 1333,
+ MOVDQArm = 1334,
+ MOVDQArr = 1335,
+ MOVDQUmr = 1336,
+ MOVDQUmr_Int = 1337,
+ MOVDQUrm = 1338,
+ MOVDQUrm_Int = 1339,
+ MOVHLPSrr = 1340,
+ MOVHPDmr = 1341,
+ MOVHPDrm = 1342,
+ MOVHPSmr = 1343,
+ MOVHPSrm = 1344,
+ MOVLHPSrr = 1345,
+ MOVLPDmr = 1346,
+ MOVLPDrm = 1347,
+ MOVLPDrr = 1348,
+ MOVLPSmr = 1349,
+ MOVLPSrm = 1350,
+ MOVLPSrr = 1351,
+ MOVLQ128mr = 1352,
+ MOVLSD2PDrr = 1353,
+ MOVLSS2PSrr = 1354,
+ MOVMSKPDrr = 1355,
+ MOVMSKPSrr = 1356,
+ MOVNTDQArm = 1357,
+ MOVNTDQmr = 1358,
+ MOVNTImr = 1359,
+ MOVNTPDmr = 1360,
+ MOVNTPSmr = 1361,
+ MOVPC32r = 1362,
+ MOVPD2SDmr = 1363,
+ MOVPD2SDrr = 1364,
+ MOVPDI2DImr = 1365,
+ MOVPDI2DIrr = 1366,
+ MOVPQI2QImr = 1367,
+ MOVPQIto64rr = 1368,
+ MOVPS2SSmr = 1369,
+ MOVPS2SSrr = 1370,
+ MOVQI2PQIrm = 1371,
+ MOVQxrxr = 1372,
+ MOVSB = 1373,
+ MOVSD = 1374,
+ MOVSD2PDrm = 1375,
+ MOVSD2PDrr = 1376,
+ MOVSDmr = 1377,
+ MOVSDrm = 1378,
+ MOVSDrr = 1379,
+ MOVSDto64mr = 1380,
+ MOVSDto64rr = 1381,
+ MOVSHDUPrm = 1382,
+ MOVSHDUPrr = 1383,
+ MOVSLDUPrm = 1384,
+ MOVSLDUPrr = 1385,
+ MOVSS2DImr = 1386,
+ MOVSS2DIrr = 1387,
+ MOVSS2PSrm = 1388,
+ MOVSS2PSrr = 1389,
+ MOVSSmr = 1390,
+ MOVSSrm = 1391,
+ MOVSSrr = 1392,
+ MOVSW = 1393,
+ MOVSX16rm8 = 1394,
+ MOVSX16rm8W = 1395,
+ MOVSX16rr8 = 1396,
+ MOVSX16rr8W = 1397,
+ MOVSX32rm16 = 1398,
+ MOVSX32rm8 = 1399,
+ MOVSX32rr16 = 1400,
+ MOVSX32rr8 = 1401,
+ MOVSX64rm16 = 1402,
+ MOVSX64rm32 = 1403,
+ MOVSX64rm8 = 1404,
+ MOVSX64rr16 = 1405,
+ MOVSX64rr32 = 1406,
+ MOVSX64rr8 = 1407,
+ MOVUPDmr = 1408,
+ MOVUPDmr_Int = 1409,
+ MOVUPDrm = 1410,
+ MOVUPDrm_Int = 1411,
+ MOVUPDrr = 1412,
+ MOVUPSmr = 1413,
+ MOVUPSmr_Int = 1414,
+ MOVUPSrm = 1415,
+ MOVUPSrm_Int = 1416,
+ MOVUPSrr = 1417,
+ MOVZDI2PDIrm = 1418,
+ MOVZDI2PDIrr = 1419,
+ MOVZPQILo2PQIrm = 1420,
+ MOVZPQILo2PQIrr = 1421,
+ MOVZQI2PQIrm = 1422,
+ MOVZQI2PQIrr = 1423,
+ MOVZSD2PDrm = 1424,
+ MOVZSS2PSrm = 1425,
+ MOVZX16rm8 = 1426,
+ MOVZX16rm8W = 1427,
+ MOVZX16rr8 = 1428,
+ MOVZX16rr8W = 1429,
+ MOVZX32_NOREXrm8 = 1430,
+ MOVZX32_NOREXrr8 = 1431,
+ MOVZX32rm16 = 1432,
+ MOVZX32rm8 = 1433,
+ MOVZX32rr16 = 1434,
+ MOVZX32rr8 = 1435,
+ MOVZX64rm16 = 1436,
+ MOVZX64rm16_Q = 1437,
+ MOVZX64rm32 = 1438,
+ MOVZX64rm8 = 1439,
+ MOVZX64rm8_Q = 1440,
+ MOVZX64rr16 = 1441,
+ MOVZX64rr16_Q = 1442,
+ MOVZX64rr32 = 1443,
+ MOVZX64rr8 = 1444,
+ MOVZX64rr8_Q = 1445,
+ MOV_Fp3232 = 1446,
+ MOV_Fp3264 = 1447,
+ MOV_Fp3280 = 1448,
+ MOV_Fp6432 = 1449,
+ MOV_Fp6464 = 1450,
+ MOV_Fp6480 = 1451,
+ MOV_Fp8032 = 1452,
+ MOV_Fp8064 = 1453,
+ MOV_Fp8080 = 1454,
+ MPSADBWrmi = 1455,
+ MPSADBWrri = 1456,
+ MUL16m = 1457,
+ MUL16r = 1458,
+ MUL32m = 1459,
+ MUL32r = 1460,
+ MUL64m = 1461,
+ MUL64r = 1462,
+ MUL8m = 1463,
+ MUL8r = 1464,
+ MULPDrm = 1465,
+ MULPDrr = 1466,
+ MULPSrm = 1467,
+ MULPSrr = 1468,
+ MULSDrm = 1469,
+ MULSDrm_Int = 1470,
+ MULSDrr = 1471,
+ MULSDrr_Int = 1472,
+ MULSSrm = 1473,
+ MULSSrm_Int = 1474,
+ MULSSrr = 1475,
+ MULSSrr_Int = 1476,
+ MUL_F32m = 1477,
+ MUL_F64m = 1478,
+ MUL_FI16m = 1479,
+ MUL_FI32m = 1480,
+ MUL_FPrST0 = 1481,
+ MUL_FST0r = 1482,
+ MUL_Fp32 = 1483,
+ MUL_Fp32m = 1484,
+ MUL_Fp64 = 1485,
+ MUL_Fp64m = 1486,
+ MUL_Fp64m32 = 1487,
+ MUL_Fp80 = 1488,
+ MUL_Fp80m32 = 1489,
+ MUL_Fp80m64 = 1490,
+ MUL_FpI16m32 = 1491,
+ MUL_FpI16m64 = 1492,
+ MUL_FpI16m80 = 1493,
+ MUL_FpI32m32 = 1494,
+ MUL_FpI32m64 = 1495,
+ MUL_FpI32m80 = 1496,
+ MUL_FrST0 = 1497,
+ MWAIT = 1498,
+ NEG16m = 1499,
+ NEG16r = 1500,
+ NEG32m = 1501,
+ NEG32r = 1502,
+ NEG64m = 1503,
+ NEG64r = 1504,
+ NEG8m = 1505,
+ NEG8r = 1506,
+ NOOP = 1507,
+ NOOPL = 1508,
+ NOOPW = 1509,
+ NOT16m = 1510,
+ NOT16r = 1511,
+ NOT32m = 1512,
+ NOT32r = 1513,
+ NOT64m = 1514,
+ NOT64r = 1515,
+ NOT8m = 1516,
+ NOT8r = 1517,
+ OR16i16 = 1518,
+ OR16mi = 1519,
+ OR16mi8 = 1520,
+ OR16mr = 1521,
+ OR16ri = 1522,
+ OR16ri8 = 1523,
+ OR16rm = 1524,
+ OR16rr = 1525,
+ OR16rr_REV = 1526,
+ OR32i32 = 1527,
+ OR32mi = 1528,
+ OR32mi8 = 1529,
+ OR32mr = 1530,
+ OR32ri = 1531,
+ OR32ri8 = 1532,
+ OR32rm = 1533,
+ OR32rr = 1534,
+ OR32rr_REV = 1535,
+ OR64i32 = 1536,
+ OR64mi32 = 1537,
+ OR64mi8 = 1538,
+ OR64mr = 1539,
+ OR64ri32 = 1540,
+ OR64ri8 = 1541,
+ OR64rm = 1542,
+ OR64rr = 1543,
+ OR64rr_REV = 1544,
+ OR8i8 = 1545,
+ OR8mi = 1546,
+ OR8mr = 1547,
+ OR8ri = 1548,
+ OR8rm = 1549,
+ OR8rr = 1550,
+ OR8rr_REV = 1551,
+ ORPDrm = 1552,
+ ORPDrr = 1553,
+ ORPSrm = 1554,
+ ORPSrr = 1555,
+ OUT16ir = 1556,
+ OUT16rr = 1557,
+ OUT32ir = 1558,
+ OUT32rr = 1559,
+ OUT8ir = 1560,
+ OUT8rr = 1561,
+ OUTSB = 1562,
+ OUTSD = 1563,
+ OUTSW = 1564,
+ PABSBrm128 = 1565,
+ PABSBrm64 = 1566,
+ PABSBrr128 = 1567,
+ PABSBrr64 = 1568,
+ PABSDrm128 = 1569,
+ PABSDrm64 = 1570,
+ PABSDrr128 = 1571,
+ PABSDrr64 = 1572,
+ PABSWrm128 = 1573,
+ PABSWrm64 = 1574,
+ PABSWrr128 = 1575,
+ PABSWrr64 = 1576,
+ PACKSSDWrm = 1577,
+ PACKSSDWrr = 1578,
+ PACKSSWBrm = 1579,
+ PACKSSWBrr = 1580,
+ PACKUSDWrm = 1581,
+ PACKUSDWrr = 1582,
+ PACKUSWBrm = 1583,
+ PACKUSWBrr = 1584,
+ PADDBrm = 1585,
+ PADDBrr = 1586,
+ PADDDrm = 1587,
+ PADDDrr = 1588,
+ PADDQrm = 1589,
+ PADDQrr = 1590,
+ PADDSBrm = 1591,
+ PADDSBrr = 1592,
+ PADDSWrm = 1593,
+ PADDSWrr = 1594,
+ PADDUSBrm = 1595,
+ PADDUSBrr = 1596,
+ PADDUSWrm = 1597,
+ PADDUSWrr = 1598,
+ PADDWrm = 1599,
+ PADDWrr = 1600,
+ PALIGNR128rm = 1601,
+ PALIGNR128rr = 1602,
+ PALIGNR64rm = 1603,
+ PALIGNR64rr = 1604,
+ PANDNrm = 1605,
+ PANDNrr = 1606,
+ PANDrm = 1607,
+ PANDrr = 1608,
+ PAVGBrm = 1609,
+ PAVGBrr = 1610,
+ PAVGWrm = 1611,
+ PAVGWrr = 1612,
+ PBLENDVBrm0 = 1613,
+ PBLENDVBrr0 = 1614,
+ PBLENDWrmi = 1615,
+ PBLENDWrri = 1616,
+ PCMPEQBrm = 1617,
+ PCMPEQBrr = 1618,
+ PCMPEQDrm = 1619,
+ PCMPEQDrr = 1620,
+ PCMPEQQrm = 1621,
+ PCMPEQQrr = 1622,
+ PCMPEQWrm = 1623,
+ PCMPEQWrr = 1624,
+ PCMPESTRIArm = 1625,
+ PCMPESTRIArr = 1626,
+ PCMPESTRICrm = 1627,
+ PCMPESTRICrr = 1628,
+ PCMPESTRIOrm = 1629,
+ PCMPESTRIOrr = 1630,
+ PCMPESTRISrm = 1631,
+ PCMPESTRISrr = 1632,
+ PCMPESTRIZrm = 1633,
+ PCMPESTRIZrr = 1634,
+ PCMPESTRIrm = 1635,
+ PCMPESTRIrr = 1636,
+ PCMPESTRM128MEM = 1637,
+ PCMPESTRM128REG = 1638,
+ PCMPESTRM128rm = 1639,
+ PCMPESTRM128rr = 1640,
+ PCMPGTBrm = 1641,
+ PCMPGTBrr = 1642,
+ PCMPGTDrm = 1643,
+ PCMPGTDrr = 1644,
+ PCMPGTQrm = 1645,
+ PCMPGTQrr = 1646,
+ PCMPGTWrm = 1647,
+ PCMPGTWrr = 1648,
+ PCMPISTRIArm = 1649,
+ PCMPISTRIArr = 1650,
+ PCMPISTRICrm = 1651,
+ PCMPISTRICrr = 1652,
+ PCMPISTRIOrm = 1653,
+ PCMPISTRIOrr = 1654,
+ PCMPISTRISrm = 1655,
+ PCMPISTRISrr = 1656,
+ PCMPISTRIZrm = 1657,
+ PCMPISTRIZrr = 1658,
+ PCMPISTRIrm = 1659,
+ PCMPISTRIrr = 1660,
+ PCMPISTRM128MEM = 1661,
+ PCMPISTRM128REG = 1662,
+ PCMPISTRM128rm = 1663,
+ PCMPISTRM128rr = 1664,
+ PEXTRBmr = 1665,
+ PEXTRBrr = 1666,
+ PEXTRDmr = 1667,
+ PEXTRDrr = 1668,
+ PEXTRQmr = 1669,
+ PEXTRQrr = 1670,
+ PEXTRWmr = 1671,
+ PEXTRWri = 1672,
+ PHADDDrm128 = 1673,
+ PHADDDrm64 = 1674,
+ PHADDDrr128 = 1675,
+ PHADDDrr64 = 1676,
+ PHADDSWrm128 = 1677,
+ PHADDSWrm64 = 1678,
+ PHADDSWrr128 = 1679,
+ PHADDSWrr64 = 1680,
+ PHADDWrm128 = 1681,
+ PHADDWrm64 = 1682,
+ PHADDWrr128 = 1683,
+ PHADDWrr64 = 1684,
+ PHMINPOSUWrm128 = 1685,
+ PHMINPOSUWrr128 = 1686,
+ PHSUBDrm128 = 1687,
+ PHSUBDrm64 = 1688,
+ PHSUBDrr128 = 1689,
+ PHSUBDrr64 = 1690,
+ PHSUBSWrm128 = 1691,
+ PHSUBSWrm64 = 1692,
+ PHSUBSWrr128 = 1693,
+ PHSUBSWrr64 = 1694,
+ PHSUBWrm128 = 1695,
+ PHSUBWrm64 = 1696,
+ PHSUBWrr128 = 1697,
+ PHSUBWrr64 = 1698,
+ PINSRBrm = 1699,
+ PINSRBrr = 1700,
+ PINSRDrm = 1701,
+ PINSRDrr = 1702,
+ PINSRQrm = 1703,
+ PINSRQrr = 1704,
+ PINSRWrmi = 1705,
+ PINSRWrri = 1706,
+ PMADDUBSWrm128 = 1707,
+ PMADDUBSWrm64 = 1708,
+ PMADDUBSWrr128 = 1709,
+ PMADDUBSWrr64 = 1710,
+ PMADDWDrm = 1711,
+ PMADDWDrr = 1712,
+ PMAXSBrm = 1713,
+ PMAXSBrr = 1714,
+ PMAXSDrm = 1715,
+ PMAXSDrr = 1716,
+ PMAXSWrm = 1717,
+ PMAXSWrr = 1718,
+ PMAXUBrm = 1719,
+ PMAXUBrr = 1720,
+ PMAXUDrm = 1721,
+ PMAXUDrr = 1722,
+ PMAXUWrm = 1723,
+ PMAXUWrr = 1724,
+ PMINSBrm = 1725,
+ PMINSBrr = 1726,
+ PMINSDrm = 1727,
+ PMINSDrr = 1728,
+ PMINSWrm = 1729,
+ PMINSWrr = 1730,
+ PMINUBrm = 1731,
+ PMINUBrr = 1732,
+ PMINUDrm = 1733,
+ PMINUDrr = 1734,
+ PMINUWrm = 1735,
+ PMINUWrr = 1736,
+ PMOVMSKBrr = 1737,
+ PMOVSXBDrm = 1738,
+ PMOVSXBDrr = 1739,
+ PMOVSXBQrm = 1740,
+ PMOVSXBQrr = 1741,
+ PMOVSXBWrm = 1742,
+ PMOVSXBWrr = 1743,
+ PMOVSXDQrm = 1744,
+ PMOVSXDQrr = 1745,
+ PMOVSXWDrm = 1746,
+ PMOVSXWDrr = 1747,
+ PMOVSXWQrm = 1748,
+ PMOVSXWQrr = 1749,
+ PMOVZXBDrm = 1750,
+ PMOVZXBDrr = 1751,
+ PMOVZXBQrm = 1752,
+ PMOVZXBQrr = 1753,
+ PMOVZXBWrm = 1754,
+ PMOVZXBWrr = 1755,
+ PMOVZXDQrm = 1756,
+ PMOVZXDQrr = 1757,
+ PMOVZXWDrm = 1758,
+ PMOVZXWDrr = 1759,
+ PMOVZXWQrm = 1760,
+ PMOVZXWQrr = 1761,
+ PMULDQrm = 1762,
+ PMULDQrr = 1763,
+ PMULHRSWrm128 = 1764,
+ PMULHRSWrm64 = 1765,
+ PMULHRSWrr128 = 1766,
+ PMULHRSWrr64 = 1767,
+ PMULHUWrm = 1768,
+ PMULHUWrr = 1769,
+ PMULHWrm = 1770,
+ PMULHWrr = 1771,
+ PMULLDrm = 1772,
+ PMULLDrm_int = 1773,
+ PMULLDrr = 1774,
+ PMULLDrr_int = 1775,
+ PMULLWrm = 1776,
+ PMULLWrr = 1777,
+ PMULUDQrm = 1778,
+ PMULUDQrr = 1779,
+ POP16r = 1780,
+ POP16rmm = 1781,
+ POP16rmr = 1782,
+ POP32r = 1783,
+ POP32rmm = 1784,
+ POP32rmr = 1785,
+ POP64r = 1786,
+ POP64rmm = 1787,
+ POP64rmr = 1788,
+ POPCNT16rm = 1789,
+ POPCNT16rr = 1790,
+ POPCNT32rm = 1791,
+ POPCNT32rr = 1792,
+ POPCNT64rm = 1793,
+ POPCNT64rr = 1794,
+ POPF = 1795,
+ POPFD = 1796,
+ POPFQ = 1797,
+ POPFS16 = 1798,
+ POPFS32 = 1799,
+ POPFS64 = 1800,
+ POPGS16 = 1801,
+ POPGS32 = 1802,
+ POPGS64 = 1803,
+ PORrm = 1804,
+ PORrr = 1805,
+ PREFETCHNTA = 1806,
+ PREFETCHT0 = 1807,
+ PREFETCHT1 = 1808,
+ PREFETCHT2 = 1809,
+ PSADBWrm = 1810,
+ PSADBWrr = 1811,
+ PSHUFBrm128 = 1812,
+ PSHUFBrm64 = 1813,
+ PSHUFBrr128 = 1814,
+ PSHUFBrr64 = 1815,
+ PSHUFDmi = 1816,
+ PSHUFDri = 1817,
+ PSHUFHWmi = 1818,
+ PSHUFHWri = 1819,
+ PSHUFLWmi = 1820,
+ PSHUFLWri = 1821,
+ PSIGNBrm128 = 1822,
+ PSIGNBrm64 = 1823,
+ PSIGNBrr128 = 1824,
+ PSIGNBrr64 = 1825,
+ PSIGNDrm128 = 1826,
+ PSIGNDrm64 = 1827,
+ PSIGNDrr128 = 1828,
+ PSIGNDrr64 = 1829,
+ PSIGNWrm128 = 1830,
+ PSIGNWrm64 = 1831,
+ PSIGNWrr128 = 1832,
+ PSIGNWrr64 = 1833,
+ PSLLDQri = 1834,
+ PSLLDri = 1835,
+ PSLLDrm = 1836,
+ PSLLDrr = 1837,
+ PSLLQri = 1838,
+ PSLLQrm = 1839,
+ PSLLQrr = 1840,
+ PSLLWri = 1841,
+ PSLLWrm = 1842,
+ PSLLWrr = 1843,
+ PSRADri = 1844,
+ PSRADrm = 1845,
+ PSRADrr = 1846,
+ PSRAWri = 1847,
+ PSRAWrm = 1848,
+ PSRAWrr = 1849,
+ PSRLDQri = 1850,
+ PSRLDri = 1851,
+ PSRLDrm = 1852,
+ PSRLDrr = 1853,
+ PSRLQri = 1854,
+ PSRLQrm = 1855,
+ PSRLQrr = 1856,
+ PSRLWri = 1857,
+ PSRLWrm = 1858,
+ PSRLWrr = 1859,
+ PSUBBrm = 1860,
+ PSUBBrr = 1861,
+ PSUBDrm = 1862,
+ PSUBDrr = 1863,
+ PSUBQrm = 1864,
+ PSUBQrr = 1865,
+ PSUBSBrm = 1866,
+ PSUBSBrr = 1867,
+ PSUBSWrm = 1868,
+ PSUBSWrr = 1869,
+ PSUBUSBrm = 1870,
+ PSUBUSBrr = 1871,
+ PSUBUSWrm = 1872,
+ PSUBUSWrr = 1873,
+ PSUBWrm = 1874,
+ PSUBWrr = 1875,
+ PTESTrm = 1876,
+ PTESTrr = 1877,
+ PUNPCKHBWrm = 1878,
+ PUNPCKHBWrr = 1879,
+ PUNPCKHDQrm = 1880,
+ PUNPCKHDQrr = 1881,
+ PUNPCKHQDQrm = 1882,
+ PUNPCKHQDQrr = 1883,
+ PUNPCKHWDrm = 1884,
+ PUNPCKHWDrr = 1885,
+ PUNPCKLBWrm = 1886,
+ PUNPCKLBWrr = 1887,
+ PUNPCKLDQrm = 1888,
+ PUNPCKLDQrr = 1889,
+ PUNPCKLQDQrm = 1890,
+ PUNPCKLQDQrr = 1891,
+ PUNPCKLWDrm = 1892,
+ PUNPCKLWDrr = 1893,
+ PUSH16r = 1894,
+ PUSH16rmm = 1895,
+ PUSH16rmr = 1896,
+ PUSH32i16 = 1897,
+ PUSH32i32 = 1898,
+ PUSH32i8 = 1899,
+ PUSH32r = 1900,
+ PUSH32rmm = 1901,
+ PUSH32rmr = 1902,
+ PUSH64i16 = 1903,
+ PUSH64i32 = 1904,
+ PUSH64i8 = 1905,
+ PUSH64r = 1906,
+ PUSH64rmm = 1907,
+ PUSH64rmr = 1908,
+ PUSHF = 1909,
+ PUSHFD = 1910,
+ PUSHFQ64 = 1911,
+ PUSHFS16 = 1912,
+ PUSHFS32 = 1913,
+ PUSHFS64 = 1914,
+ PUSHGS16 = 1915,
+ PUSHGS32 = 1916,
+ PUSHGS64 = 1917,
+ PXORrm = 1918,
+ PXORrr = 1919,
+ RCL16m1 = 1920,
+ RCL16mCL = 1921,
+ RCL16mi = 1922,
+ RCL16r1 = 1923,
+ RCL16rCL = 1924,
+ RCL16ri = 1925,
+ RCL32m1 = 1926,
+ RCL32mCL = 1927,
+ RCL32mi = 1928,
+ RCL32r1 = 1929,
+ RCL32rCL = 1930,
+ RCL32ri = 1931,
+ RCL64m1 = 1932,
+ RCL64mCL = 1933,
+ RCL64mi = 1934,
+ RCL64r1 = 1935,
+ RCL64rCL = 1936,
+ RCL64ri = 1937,
+ RCL8m1 = 1938,
+ RCL8mCL = 1939,
+ RCL8mi = 1940,
+ RCL8r1 = 1941,
+ RCL8rCL = 1942,
+ RCL8ri = 1943,
+ RCPPSm = 1944,
+ RCPPSm_Int = 1945,
+ RCPPSr = 1946,
+ RCPPSr_Int = 1947,
+ RCPSSm = 1948,
+ RCPSSm_Int = 1949,
+ RCPSSr = 1950,
+ RCPSSr_Int = 1951,
+ RCR16m1 = 1952,
+ RCR16mCL = 1953,
+ RCR16mi = 1954,
+ RCR16r1 = 1955,
+ RCR16rCL = 1956,
+ RCR16ri = 1957,
+ RCR32m1 = 1958,
+ RCR32mCL = 1959,
+ RCR32mi = 1960,
+ RCR32r1 = 1961,
+ RCR32rCL = 1962,
+ RCR32ri = 1963,
+ RCR64m1 = 1964,
+ RCR64mCL = 1965,
+ RCR64mi = 1966,
+ RCR64r1 = 1967,
+ RCR64rCL = 1968,
+ RCR64ri = 1969,
+ RCR8m1 = 1970,
+ RCR8mCL = 1971,
+ RCR8mi = 1972,
+ RCR8r1 = 1973,
+ RCR8rCL = 1974,
+ RCR8ri = 1975,
+ RDMSR = 1976,
+ RDPMC = 1977,
+ RDTSC = 1978,
+ RDTSCP = 1979,
+ REPNE_PREFIX = 1980,
+ REP_MOVSB = 1981,
+ REP_MOVSD = 1982,
+ REP_MOVSQ = 1983,
+ REP_MOVSW = 1984,
+ REP_PREFIX = 1985,
+ REP_STOSB = 1986,
+ REP_STOSD = 1987,
+ REP_STOSQ = 1988,
+ REP_STOSW = 1989,
+ RET = 1990,
+ RETI = 1991,
+ ROL16m1 = 1992,
+ ROL16mCL = 1993,
+ ROL16mi = 1994,
+ ROL16r1 = 1995,
+ ROL16rCL = 1996,
+ ROL16ri = 1997,
+ ROL32m1 = 1998,
+ ROL32mCL = 1999,
+ ROL32mi = 2000,
+ ROL32r1 = 2001,
+ ROL32rCL = 2002,
+ ROL32ri = 2003,
+ ROL64m1 = 2004,
+ ROL64mCL = 2005,
+ ROL64mi = 2006,
+ ROL64r1 = 2007,
+ ROL64rCL = 2008,
+ ROL64ri = 2009,
+ ROL8m1 = 2010,
+ ROL8mCL = 2011,
+ ROL8mi = 2012,
+ ROL8r1 = 2013,
+ ROL8rCL = 2014,
+ ROL8ri = 2015,
+ ROR16m1 = 2016,
+ ROR16mCL = 2017,
+ ROR16mi = 2018,
+ ROR16r1 = 2019,
+ ROR16rCL = 2020,
+ ROR16ri = 2021,
+ ROR32m1 = 2022,
+ ROR32mCL = 2023,
+ ROR32mi = 2024,
+ ROR32r1 = 2025,
+ ROR32rCL = 2026,
+ ROR32ri = 2027,
+ ROR64m1 = 2028,
+ ROR64mCL = 2029,
+ ROR64mi = 2030,
+ ROR64r1 = 2031,
+ ROR64rCL = 2032,
+ ROR64ri = 2033,
+ ROR8m1 = 2034,
+ ROR8mCL = 2035,
+ ROR8mi = 2036,
+ ROR8r1 = 2037,
+ ROR8rCL = 2038,
+ ROR8ri = 2039,
+ ROUNDPDm_Int = 2040,
+ ROUNDPDr_Int = 2041,
+ ROUNDPSm_Int = 2042,
+ ROUNDPSr_Int = 2043,
+ ROUNDSDm_Int = 2044,
+ ROUNDSDr_Int = 2045,
+ ROUNDSSm_Int = 2046,
+ ROUNDSSr_Int = 2047,
+ RSM = 2048,
+ RSQRTPSm = 2049,
+ RSQRTPSm_Int = 2050,
+ RSQRTPSr = 2051,
+ RSQRTPSr_Int = 2052,
+ RSQRTSSm = 2053,
+ RSQRTSSm_Int = 2054,
+ RSQRTSSr = 2055,
+ RSQRTSSr_Int = 2056,
+ SAHF = 2057,
+ SAR16m1 = 2058,
+ SAR16mCL = 2059,
+ SAR16mi = 2060,
+ SAR16r1 = 2061,
+ SAR16rCL = 2062,
+ SAR16ri = 2063,
+ SAR32m1 = 2064,
+ SAR32mCL = 2065,
+ SAR32mi = 2066,
+ SAR32r1 = 2067,
+ SAR32rCL = 2068,
+ SAR32ri = 2069,
+ SAR64m1 = 2070,
+ SAR64mCL = 2071,
+ SAR64mi = 2072,
+ SAR64r1 = 2073,
+ SAR64rCL = 2074,
+ SAR64ri = 2075,
+ SAR8m1 = 2076,
+ SAR8mCL = 2077,
+ SAR8mi = 2078,
+ SAR8r1 = 2079,
+ SAR8rCL = 2080,
+ SAR8ri = 2081,
+ SBB16i16 = 2082,
+ SBB16mi = 2083,
+ SBB16mi8 = 2084,
+ SBB16mr = 2085,
+ SBB16ri = 2086,
+ SBB16ri8 = 2087,
+ SBB16rm = 2088,
+ SBB16rr = 2089,
+ SBB16rr_REV = 2090,
+ SBB32i32 = 2091,
+ SBB32mi = 2092,
+ SBB32mi8 = 2093,
+ SBB32mr = 2094,
+ SBB32ri = 2095,
+ SBB32ri8 = 2096,
+ SBB32rm = 2097,
+ SBB32rr = 2098,
+ SBB32rr_REV = 2099,
+ SBB64i32 = 2100,
+ SBB64mi32 = 2101,
+ SBB64mi8 = 2102,
+ SBB64mr = 2103,
+ SBB64ri32 = 2104,
+ SBB64ri8 = 2105,
+ SBB64rm = 2106,
+ SBB64rr = 2107,
+ SBB64rr_REV = 2108,
+ SBB8i8 = 2109,
+ SBB8mi = 2110,
+ SBB8mr = 2111,
+ SBB8ri = 2112,
+ SBB8rm = 2113,
+ SBB8rr = 2114,
+ SBB8rr_REV = 2115,
+ SCAS16 = 2116,
+ SCAS32 = 2117,
+ SCAS64 = 2118,
+ SCAS8 = 2119,
+ SETAEm = 2120,
+ SETAEr = 2121,
+ SETAm = 2122,
+ SETAr = 2123,
+ SETBEm = 2124,
+ SETBEr = 2125,
+ SETB_C16r = 2126,
+ SETB_C32r = 2127,
+ SETB_C64r = 2128,
+ SETB_C8r = 2129,
+ SETBm = 2130,
+ SETBr = 2131,
+ SETEm = 2132,
+ SETEr = 2133,
+ SETGEm = 2134,
+ SETGEr = 2135,
+ SETGm = 2136,
+ SETGr = 2137,
+ SETLEm = 2138,
+ SETLEr = 2139,
+ SETLm = 2140,
+ SETLr = 2141,
+ SETNEm = 2142,
+ SETNEr = 2143,
+ SETNOm = 2144,
+ SETNOr = 2145,
+ SETNPm = 2146,
+ SETNPr = 2147,
+ SETNSm = 2148,
+ SETNSr = 2149,
+ SETOm = 2150,
+ SETOr = 2151,
+ SETPm = 2152,
+ SETPr = 2153,
+ SETSm = 2154,
+ SETSr = 2155,
+ SFENCE = 2156,
+ SGDTm = 2157,
+ SHL16m1 = 2158,
+ SHL16mCL = 2159,
+ SHL16mi = 2160,
+ SHL16r1 = 2161,
+ SHL16rCL = 2162,
+ SHL16ri = 2163,
+ SHL32m1 = 2164,
+ SHL32mCL = 2165,
+ SHL32mi = 2166,
+ SHL32r1 = 2167,
+ SHL32rCL = 2168,
+ SHL32ri = 2169,
+ SHL64m1 = 2170,
+ SHL64mCL = 2171,
+ SHL64mi = 2172,
+ SHL64r1 = 2173,
+ SHL64rCL = 2174,
+ SHL64ri = 2175,
+ SHL8m1 = 2176,
+ SHL8mCL = 2177,
+ SHL8mi = 2178,
+ SHL8r1 = 2179,
+ SHL8rCL = 2180,
+ SHL8ri = 2181,
+ SHLD16mrCL = 2182,
+ SHLD16mri8 = 2183,
+ SHLD16rrCL = 2184,
+ SHLD16rri8 = 2185,
+ SHLD32mrCL = 2186,
+ SHLD32mri8 = 2187,
+ SHLD32rrCL = 2188,
+ SHLD32rri8 = 2189,
+ SHLD64mrCL = 2190,
+ SHLD64mri8 = 2191,
+ SHLD64rrCL = 2192,
+ SHLD64rri8 = 2193,
+ SHR16m1 = 2194,
+ SHR16mCL = 2195,
+ SHR16mi = 2196,
+ SHR16r1 = 2197,
+ SHR16rCL = 2198,
+ SHR16ri = 2199,
+ SHR32m1 = 2200,
+ SHR32mCL = 2201,
+ SHR32mi = 2202,
+ SHR32r1 = 2203,
+ SHR32rCL = 2204,
+ SHR32ri = 2205,
+ SHR64m1 = 2206,
+ SHR64mCL = 2207,
+ SHR64mi = 2208,
+ SHR64r1 = 2209,
+ SHR64rCL = 2210,
+ SHR64ri = 2211,
+ SHR8m1 = 2212,
+ SHR8mCL = 2213,
+ SHR8mi = 2214,
+ SHR8r1 = 2215,
+ SHR8rCL = 2216,
+ SHR8ri = 2217,
+ SHRD16mrCL = 2218,
+ SHRD16mri8 = 2219,
+ SHRD16rrCL = 2220,
+ SHRD16rri8 = 2221,
+ SHRD32mrCL = 2222,
+ SHRD32mri8 = 2223,
+ SHRD32rrCL = 2224,
+ SHRD32rri8 = 2225,
+ SHRD64mrCL = 2226,
+ SHRD64mri8 = 2227,
+ SHRD64rrCL = 2228,
+ SHRD64rri8 = 2229,
+ SHUFPDrmi = 2230,
+ SHUFPDrri = 2231,
+ SHUFPSrmi = 2232,
+ SHUFPSrri = 2233,
+ SIDTm = 2234,
+ SIN_F = 2235,
+ SIN_Fp32 = 2236,
+ SIN_Fp64 = 2237,
+ SIN_Fp80 = 2238,
+ SLDT16m = 2239,
+ SLDT16r = 2240,
+ SLDT64m = 2241,
+ SLDT64r = 2242,
+ SMSW16m = 2243,
+ SMSW16r = 2244,
+ SMSW32r = 2245,
+ SMSW64r = 2246,
+ SQRTPDm = 2247,
+ SQRTPDm_Int = 2248,
+ SQRTPDr = 2249,
+ SQRTPDr_Int = 2250,
+ SQRTPSm = 2251,
+ SQRTPSm_Int = 2252,
+ SQRTPSr = 2253,
+ SQRTPSr_Int = 2254,
+ SQRTSDm = 2255,
+ SQRTSDm_Int = 2256,
+ SQRTSDr = 2257,
+ SQRTSDr_Int = 2258,
+ SQRTSSm = 2259,
+ SQRTSSm_Int = 2260,
+ SQRTSSr = 2261,
+ SQRTSSr_Int = 2262,
+ SQRT_F = 2263,
+ SQRT_Fp32 = 2264,
+ SQRT_Fp64 = 2265,
+ SQRT_Fp80 = 2266,
+ SS_PREFIX = 2267,
+ STC = 2268,
+ STD = 2269,
+ STI = 2270,
+ STMXCSR = 2271,
+ STOSB = 2272,
+ STOSD = 2273,
+ STOSW = 2274,
+ STRm = 2275,
+ STRr = 2276,
+ ST_F32m = 2277,
+ ST_F64m = 2278,
+ ST_FP32m = 2279,
+ ST_FP64m = 2280,
+ ST_FP80m = 2281,
+ ST_FPrr = 2282,
+ ST_Fp32m = 2283,
+ ST_Fp64m = 2284,
+ ST_Fp64m32 = 2285,
+ ST_Fp80m32 = 2286,
+ ST_Fp80m64 = 2287,
+ ST_FpP32m = 2288,
+ ST_FpP64m = 2289,
+ ST_FpP64m32 = 2290,
+ ST_FpP80m = 2291,
+ ST_FpP80m32 = 2292,
+ ST_FpP80m64 = 2293,
+ ST_Frr = 2294,
+ SUB16i16 = 2295,
+ SUB16mi = 2296,
+ SUB16mi8 = 2297,
+ SUB16mr = 2298,
+ SUB16ri = 2299,
+ SUB16ri8 = 2300,
+ SUB16rm = 2301,
+ SUB16rr = 2302,
+ SUB16rr_REV = 2303,
+ SUB32i32 = 2304,
+ SUB32mi = 2305,
+ SUB32mi8 = 2306,
+ SUB32mr = 2307,
+ SUB32ri = 2308,
+ SUB32ri8 = 2309,
+ SUB32rm = 2310,
+ SUB32rr = 2311,
+ SUB32rr_REV = 2312,
+ SUB64i32 = 2313,
+ SUB64mi32 = 2314,
+ SUB64mi8 = 2315,
+ SUB64mr = 2316,
+ SUB64ri32 = 2317,
+ SUB64ri8 = 2318,
+ SUB64rm = 2319,
+ SUB64rr = 2320,
+ SUB64rr_REV = 2321,
+ SUB8i8 = 2322,
+ SUB8mi = 2323,
+ SUB8mr = 2324,
+ SUB8ri = 2325,
+ SUB8rm = 2326,
+ SUB8rr = 2327,
+ SUB8rr_REV = 2328,
+ SUBPDrm = 2329,
+ SUBPDrr = 2330,
+ SUBPSrm = 2331,
+ SUBPSrr = 2332,
+ SUBR_F32m = 2333,
+ SUBR_F64m = 2334,
+ SUBR_FI16m = 2335,
+ SUBR_FI32m = 2336,
+ SUBR_FPrST0 = 2337,
+ SUBR_FST0r = 2338,
+ SUBR_Fp32m = 2339,
+ SUBR_Fp64m = 2340,
+ SUBR_Fp64m32 = 2341,
+ SUBR_Fp80m32 = 2342,
+ SUBR_Fp80m64 = 2343,
+ SUBR_FpI16m32 = 2344,
+ SUBR_FpI16m64 = 2345,
+ SUBR_FpI16m80 = 2346,
+ SUBR_FpI32m32 = 2347,
+ SUBR_FpI32m64 = 2348,
+ SUBR_FpI32m80 = 2349,
+ SUBR_FrST0 = 2350,
+ SUBSDrm = 2351,
+ SUBSDrm_Int = 2352,
+ SUBSDrr = 2353,
+ SUBSDrr_Int = 2354,
+ SUBSSrm = 2355,
+ SUBSSrm_Int = 2356,
+ SUBSSrr = 2357,
+ SUBSSrr_Int = 2358,
+ SUB_F32m = 2359,
+ SUB_F64m = 2360,
+ SUB_FI16m = 2361,
+ SUB_FI32m = 2362,
+ SUB_FPrST0 = 2363,
+ SUB_FST0r = 2364,
+ SUB_Fp32 = 2365,
+ SUB_Fp32m = 2366,
+ SUB_Fp64 = 2367,
+ SUB_Fp64m = 2368,
+ SUB_Fp64m32 = 2369,
+ SUB_Fp80 = 2370,
+ SUB_Fp80m32 = 2371,
+ SUB_Fp80m64 = 2372,
+ SUB_FpI16m32 = 2373,
+ SUB_FpI16m64 = 2374,
+ SUB_FpI16m80 = 2375,
+ SUB_FpI32m32 = 2376,
+ SUB_FpI32m64 = 2377,
+ SUB_FpI32m80 = 2378,
+ SUB_FrST0 = 2379,
+ SWAPGS = 2380,
+ SYSCALL = 2381,
+ SYSENTER = 2382,
+ SYSEXIT = 2383,
+ SYSEXIT64 = 2384,
+ SYSRET = 2385,
+ TAILJMPd = 2386,
+ TAILJMPm = 2387,
+ TAILJMPr = 2388,
+ TAILJMPr64 = 2389,
+ TCRETURNdi = 2390,
+ TCRETURNdi64 = 2391,
+ TCRETURNri = 2392,
+ TCRETURNri64 = 2393,
+ TEST16i16 = 2394,
+ TEST16mi = 2395,
+ TEST16ri = 2396,
+ TEST16rm = 2397,
+ TEST16rr = 2398,
+ TEST32i32 = 2399,
+ TEST32mi = 2400,
+ TEST32ri = 2401,
+ TEST32rm = 2402,
+ TEST32rr = 2403,
+ TEST64i32 = 2404,
+ TEST64mi32 = 2405,
+ TEST64ri32 = 2406,
+ TEST64rm = 2407,
+ TEST64rr = 2408,
+ TEST8i8 = 2409,
+ TEST8mi = 2410,
+ TEST8ri = 2411,
+ TEST8rm = 2412,
+ TEST8rr = 2413,
+ TLS_addr32 = 2414,
+ TLS_addr64 = 2415,
+ TRAP = 2416,
+ TST_F = 2417,
+ TST_Fp32 = 2418,
+ TST_Fp64 = 2419,
+ TST_Fp80 = 2420,
+ UCOMISDrm = 2421,
+ UCOMISDrr = 2422,
+ UCOMISSrm = 2423,
+ UCOMISSrr = 2424,
+ UCOM_FIPr = 2425,
+ UCOM_FIr = 2426,
+ UCOM_FPPr = 2427,
+ UCOM_FPr = 2428,
+ UCOM_FpIr32 = 2429,
+ UCOM_FpIr64 = 2430,
+ UCOM_FpIr80 = 2431,
+ UCOM_Fpr32 = 2432,
+ UCOM_Fpr64 = 2433,
+ UCOM_Fpr80 = 2434,
+ UCOM_Fr = 2435,
+ UNPCKHPDrm = 2436,
+ UNPCKHPDrr = 2437,
+ UNPCKHPSrm = 2438,
+ UNPCKHPSrr = 2439,
+ UNPCKLPDrm = 2440,
+ UNPCKLPDrr = 2441,
+ UNPCKLPSrm = 2442,
+ UNPCKLPSrr = 2443,
+ VASTART_SAVE_XMM_REGS = 2444,
+ VERRm = 2445,
+ VERRr = 2446,
+ VERWm = 2447,
+ VERWr = 2448,
+ VMCALL = 2449,
+ VMCLEARm = 2450,
+ VMLAUNCH = 2451,
+ VMPTRLDm = 2452,
+ VMPTRSTm = 2453,
+ VMREAD32rm = 2454,
+ VMREAD32rr = 2455,
+ VMREAD64rm = 2456,
+ VMREAD64rr = 2457,
+ VMRESUME = 2458,
+ VMWRITE32rm = 2459,
+ VMWRITE32rr = 2460,
+ VMWRITE64rm = 2461,
+ VMWRITE64rr = 2462,
+ VMXOFF = 2463,
+ VMXON = 2464,
+ V_SET0 = 2465,
+ V_SETALLONES = 2466,
+ WAIT = 2467,
+ WBINVD = 2468,
+ WINCALL64m = 2469,
+ WINCALL64pcrel32 = 2470,
+ WINCALL64r = 2471,
+ WRMSR = 2472,
+ XADD16rm = 2473,
+ XADD16rr = 2474,
+ XADD32rm = 2475,
+ XADD32rr = 2476,
+ XADD64rm = 2477,
+ XADD64rr = 2478,
+ XADD8rm = 2479,
+ XADD8rr = 2480,
+ XCHG16ar = 2481,
+ XCHG16rm = 2482,
+ XCHG16rr = 2483,
+ XCHG32ar = 2484,
+ XCHG32rm = 2485,
+ XCHG32rr = 2486,
+ XCHG64ar = 2487,
+ XCHG64rm = 2488,
+ XCHG64rr = 2489,
+ XCHG8rm = 2490,
+ XCHG8rr = 2491,
+ XCH_F = 2492,
+ XLAT = 2493,
+ XOR16i16 = 2494,
+ XOR16mi = 2495,
+ XOR16mi8 = 2496,
+ XOR16mr = 2497,
+ XOR16ri = 2498,
+ XOR16ri8 = 2499,
+ XOR16rm = 2500,
+ XOR16rr = 2501,
+ XOR16rr_REV = 2502,
+ XOR32i32 = 2503,
+ XOR32mi = 2504,
+ XOR32mi8 = 2505,
+ XOR32mr = 2506,
+ XOR32ri = 2507,
+ XOR32ri8 = 2508,
+ XOR32rm = 2509,
+ XOR32rr = 2510,
+ XOR32rr_REV = 2511,
+ XOR64i32 = 2512,
+ XOR64mi32 = 2513,
+ XOR64mi8 = 2514,
+ XOR64mr = 2515,
+ XOR64ri32 = 2516,
+ XOR64ri8 = 2517,
+ XOR64rm = 2518,
+ XOR64rr = 2519,
+ XOR64rr_REV = 2520,
+ XOR8i8 = 2521,
+ XOR8mi = 2522,
+ XOR8mr = 2523,
+ XOR8ri = 2524,
+ XOR8rm = 2525,
+ XOR8rr = 2526,
+ XOR8rr_REV = 2527,
+ XORPDrm = 2528,
+ XORPDrr = 2529,
+ XORPSrm = 2530,
+ XORPSrr = 2531,
+ INSTRUCTION_LIST_END = 2532
};
}
} // End llvm namespace
diff --git a/libclamav/c++/X86GenRegisterInfo.inc b/libclamav/c++/X86GenRegisterInfo.inc
index 1dd0521..33bfe18 100644
--- a/libclamav/c++/X86GenRegisterInfo.inc
+++ b/libclamav/c++/X86GenRegisterInfo.inc
@@ -121,7 +121,7 @@ namespace { // Register classes...
// GR8_NOREX Register Class...
static const unsigned GR8_NOREX[] = {
- X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH, X86::SIL, X86::DIL, X86::BPL, X86::SPL,
+ X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH,
};
// RFP32 Register Class...
@@ -1271,8 +1271,9 @@ GR8_ABCD_HClass::GR8_ABCD_HClass() : TargetRegisterClass(GR8_ABCD_HRegClassID,
GR8_ABCD_LClass::GR8_ABCD_LClass() : TargetRegisterClass(GR8_ABCD_LRegClassID, "GR8_ABCD_L", GR8_ABCD_LVTs, GR8_ABCD_LSubclasses, GR8_ABCD_LSuperclasses, GR8_ABCD_LSubRegClasses, GR8_ABCD_LSuperRegClasses, 1, 1, 1, GR8_ABCD_L, GR8_ABCD_L + 4) {}
+ // In 64-bit mode, it's not safe to blindly allocate H registers.
static const unsigned X86_GR8_NOREX_AO_64[] = {
- X86::AL, X86::CL, X86::DL, X86::SIL, X86::DIL, X86::BL, X86::BPL
+ X86::AL, X86::CL, X86::DL, X86::BL
};
GR8_NOREXClass::iterator
@@ -1288,21 +1289,14 @@ GR8_ABCD_LClass::GR8_ABCD_LClass() : TargetRegisterClass(GR8_ABCD_LRegClassID,
GR8_NOREXClass::iterator
GR8_NOREXClass::allocation_order_end(const MachineFunction &MF) const {
const TargetMachine &TM = MF.getTarget();
- const TargetRegisterInfo *RI = TM.getRegisterInfo();
const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
- // Does the function dedicate RBP / EBP to being a frame ptr?
- if (!Subtarget.is64Bit())
- // In 32-mode, none of the 8-bit registers aliases EBP or ESP.
- return begin() + 8;
- else if (RI->hasFP(MF))
- // If so, don't allocate SPL or BPL.
- return array_endof(X86_GR8_NOREX_AO_64) - 1;
- else
- // If not, just don't allocate SPL.
+ if (Subtarget.is64Bit())
return array_endof(X86_GR8_NOREX_AO_64);
+ else
+ return end();
}
-GR8_NOREXClass::GR8_NOREXClass() : TargetRegisterClass(GR8_NOREXRegClassID, "GR8_NOREX", GR8_NOREXVTs, GR8_NOREXSubclasses, GR8_NOREXSuperclasses, GR8_NOREXSubRegClasses, GR8_NOREXSuperRegClasses, 1, 1, 1, GR8_NOREX, GR8_NOREX + 12) {}
+GR8_NOREXClass::GR8_NOREXClass() : TargetRegisterClass(GR8_NOREXRegClassID, "GR8_NOREX", GR8_NOREXVTs, GR8_NOREXSubclasses, GR8_NOREXSuperclasses, GR8_NOREXSubRegClasses, GR8_NOREXSuperRegClasses, 1, 1, 1, GR8_NOREX, GR8_NOREX + 8) {}
RFP32Class::RFP32Class() : TargetRegisterClass(RFP32RegClassID, "RFP32", RFP32VTs, RFP32Subclasses, RFP32Superclasses, RFP32SubRegClasses, RFP32SuperRegClasses, 4, 4, 1, RFP32, RFP32 + 7) {}
diff --git a/libclamav/c++/llvm/include/llvm/Intrinsics.gen b/libclamav/c++/llvm/include/llvm/Intrinsics.gen
index a5dc144..57eee07 100644
--- a/libclamav/c++/llvm/include/llvm/Intrinsics.gen
+++ b/libclamav/c++/llvm/include/llvm/Intrinsics.gen
@@ -166,6 +166,7 @@
eh_return_i32, // llvm.eh.return.i32
eh_return_i64, // llvm.eh.return.i64
eh_selector, // llvm.eh.selector
+ eh_sjlj_callsite, // llvm.eh.sjlj.callsite
eh_sjlj_longjmp, // llvm.eh.sjlj.longjmp
eh_sjlj_lsda, // llvm.eh.sjlj.lsda
eh_sjlj_setjmp, // llvm.eh.sjlj.setjmp
@@ -926,6 +927,7 @@
"llvm.eh.return.i32",
"llvm.eh.return.i64",
"llvm.eh.selector",
+ "llvm.eh.sjlj.callsite",
"llvm.eh.sjlj.longjmp",
"llvm.eh.sjlj.lsda",
"llvm.eh.sjlj.setjmp",
@@ -1691,6 +1693,7 @@
false,
false,
false,
+ false,
true,
true,
false,
@@ -2457,6 +2460,7 @@
if (Len == 18 && !memcmp(Name, "llvm.eh.return.i32", 18)) return Intrinsic::eh_return_i32;
if (Len == 18 && !memcmp(Name, "llvm.eh.return.i64", 18)) return Intrinsic::eh_return_i64;
if (Len == 16 && !memcmp(Name, "llvm.eh.selector", 16)) return Intrinsic::eh_selector;
+ if (Len == 21 && !memcmp(Name, "llvm.eh.sjlj.callsite", 21)) return Intrinsic::eh_sjlj_callsite;
if (Len == 20 && !memcmp(Name, "llvm.eh.sjlj.longjmp", 20)) return Intrinsic::eh_sjlj_longjmp;
if (Len == 17 && !memcmp(Name, "llvm.eh.sjlj.lsda", 17)) return Intrinsic::eh_sjlj_lsda;
if (Len == 19 && !memcmp(Name, "llvm.eh.sjlj.setjmp", 19)) return Intrinsic::eh_sjlj_setjmp;
@@ -4174,6 +4178,7 @@
case Intrinsic::memory_barrier: // llvm.memory.barrier
VerifyIntrinsicPrototype(ID, IF, 1, 5, MVT::isVoid, MVT::i1, MVT::i1, MVT::i1, MVT::i1, MVT::i1);
break;
+ case Intrinsic::eh_sjlj_callsite: // llvm.eh.sjlj.callsite
case Intrinsic::pcmarker: // llvm.pcmarker
case Intrinsic::ppc_altivec_dss: // llvm.ppc.altivec.dss
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::isVoid, MVT::i32);
@@ -5795,6 +5800,7 @@
ArgTys.push_back(IntegerType::get(Context, 1));
ArgTys.push_back(IntegerType::get(Context, 1));
break;
+ case Intrinsic::eh_sjlj_callsite: // llvm.eh.sjlj.callsite
case Intrinsic::pcmarker: // llvm.pcmarker
case Intrinsic::ppc_altivec_dss: // llvm.ppc.altivec.dss
ResultTy = Type::getVoidTy(Context);
@@ -6147,6 +6153,7 @@ AttrListPtr Intrinsic::getAttributes(ID id) { // No intrinsic can throw excepti
case Intrinsic::cttz:
case Intrinsic::dbg_declare:
case Intrinsic::dbg_value:
+ case Intrinsic::eh_sjlj_callsite:
case Intrinsic::eh_sjlj_longjmp:
case Intrinsic::eh_sjlj_lsda:
case Intrinsic::eh_sjlj_setjmp:
@@ -7077,6 +7084,8 @@ case Intrinsic::dbg_value:
return DoesNotAccessMemory;
case Intrinsic::eh_exception:
return OnlyReadsMemory;
+case Intrinsic::eh_sjlj_callsite:
+ return DoesNotAccessMemory;
case Intrinsic::eh_sjlj_longjmp:
return DoesNotAccessMemory;
case Intrinsic::eh_sjlj_lsda:
--
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